diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 3c67a45bbcf7660a5f121e53395f399bd3d8f4f2..767f58e01a395654c3681492007b0e5cd89e463e 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -101,3 +101,6 @@ # MLIR Sparsifier. /mlir/**/*SparseTensor*/ @aartbik @PeimingLiu @yinying-lisa-li @matthias-springer + +# BOLT +/bolt/ @aaupov @maksfb @rafaelauler @dcci diff --git a/.github/workflows/build-ci-container.yml b/.github/workflows/build-ci-container.yml index ad3d50d4d578adc7ff4a99b6c0fb70393d64c755..3f2bf57eb85088df72531a917d48e38f5eb92506 100644 --- a/.github/workflows/build-ci-container.yml +++ b/.github/workflows/build-ci-container.yml @@ -1,4 +1,3 @@ - name: Build CI Container permissions: @@ -19,9 +18,41 @@ on: - '.github/workflows/containers/github-action-ci/**' jobs: - build-ci-container: + # TODO(boomanaiden154): Switch this back to a single stage build when we can + # run this on the self-hosted runners and don't have to do it this way to + # avoid timeouts. + build-ci-container-stage1: if: github.repository_owner == 'llvm' runs-on: ubuntu-latest + steps: + - name: Checkout LLVM + uses: actions/checkout@v4 + with: + sparse-checkout: .github/workflows/containers/github-action-ci/ + - name: Change podman Root Direcotry + run: | + mkdir -p ~/.config/containers + sudo mkdir -p /mnt/podman + sudo chown `whoami`:`whoami` /mnt/podman + cp ./.github/workflows/containers/github-action-ci/storage.conf ~/.config/containers/storage.conf + podman info + - name: Build container stage1 + working-directory: ./.github/workflows/containers/github-action-ci/ + run: | + podman build -t stage1-toolchain --target stage1-toolchain -f stage1.Dockerfile . + - name: Save container image + run: | + podman save stage1-toolchain > stage1-toolchain.tar + - name: Upload container image + uses: actions/upload-artifact@v4 + with: + name: stage1-toolchain + path: stage1-toolchain.tar + retention-days: 1 + build-ci-container-stage2: + if: github.repository_owner == 'llvm' + runs-on: ubuntu-latest + needs: build-ci-container-stage1 permissions: packages: write steps: @@ -38,10 +69,27 @@ jobs: with: sparse-checkout: .github/workflows/containers/github-action-ci/ + - name: Change podman Root Direcotry + run: | + mkdir -p ~/.config/containers + sudo mkdir -p /mnt/podman + sudo chown `whoami`:`whoami` /mnt/podman + cp ./.github/workflows/containers/github-action-ci/storage.conf ~/.config/containers/storage.conf + podman info + + - name: Download stage1-toolchain + uses: actions/download-artifact@v4 + with: + name: stage1-toolchain + + - name: Load stage1-toolchain + run: | + podman load -i stage1-toolchain.tar + - name: Build Container working-directory: ./.github/workflows/containers/github-action-ci/ run: | - podman build -t ${{ steps.vars.outputs.container-name-tag }} . + podman build -t ${{ steps.vars.outputs.container-name-tag }} -f stage2.Dockerfile . podman tag ${{ steps.vars.outputs.container-name-tag }} ${{ steps.vars.outputs.container-name }}:latest - name: Test Container diff --git a/.github/workflows/containers/github-action-ci/Dockerfile b/.github/workflows/containers/github-action-ci/Dockerfile deleted file mode 100644 index 66fa81d5a10aede374ccdf3b248146930eb1bb14..0000000000000000000000000000000000000000 --- a/.github/workflows/containers/github-action-ci/Dockerfile +++ /dev/null @@ -1,55 +0,0 @@ -FROM docker.io/library/ubuntu:22.04 as base -ENV LLVM_SYSROOT=/opt/llvm - -FROM base as toolchain -ENV LLVM_VERSION=17.0.6 - -RUN apt-get update && \ - apt-get install -y \ - wget \ - gcc \ - g++ \ - cmake \ - ninja-build \ - python3 \ - git - -RUN wget https://github.com/llvm/llvm-project/archive/refs/tags/llvmorg-$LLVM_VERSION.tar.gz && tar -xf llvmorg-$LLVM_VERSION.tar.gz - -WORKDIR /llvm-project-llvmorg-$LLVM_VERSION - -RUN mkdir build - -RUN cmake -B ./build -G Ninja ./llvm \ - -C ./clang/cmake/caches/BOLT-PGO.cmake \ - -DBOOTSTRAP_LLVM_ENABLE_LLD=ON \ - -DBOOTSTRAP_BOOTSTRAP_LLVM_ENABLE_LLD=ON \ - -DPGO_INSTRUMENT_LTO=Thin \ - -DLLVM_ENABLE_RUNTIMES="compiler-rt" \ - -DCMAKE_INSTALL_PREFIX="$LLVM_SYSROOT" \ - -DLLVM_ENABLE_PROJECTS="bolt;clang;lld;clang-tools-extra" \ - -DLLVM_DISTRIBUTION_COMPONENTS="lld;compiler-rt;clang-format" \ - -DCLANG_DEFAULT_LINKER="lld" - -RUN ninja -C ./build stage2-clang-bolt stage2-install-distribution && ninja -C ./build install-distribution && rm -rf ./build - -FROM base - -COPY --from=toolchain $LLVM_SYSROOT $LLVM_SYSROOT - -# Need to install curl for hendrikmuhs/ccache-action -# Need nodejs for some of the GitHub actions. -# Need perl-modules for clang analyzer tests. -RUN apt-get update && \ - apt-get install -y \ - binutils \ - cmake \ - curl \ - libstdc++-11-dev \ - ninja-build \ - nodejs \ - perl-modules \ - python3-psutil - -ENV LLVM_SYSROOT=$LLVM_SYSROOT -ENV PATH=${LLVM_SYSROOT}/bin:${PATH} diff --git a/.github/workflows/containers/github-action-ci/bootstrap.patch b/.github/workflows/containers/github-action-ci/bootstrap.patch new file mode 100644 index 0000000000000000000000000000000000000000..55631c54a396f17dd89d8240c0a63c4904e92aae --- /dev/null +++ b/.github/workflows/containers/github-action-ci/bootstrap.patch @@ -0,0 +1,13 @@ +diff --git a/clang/cmake/caches/BOLT-PGO.cmake b/clang/cmake/caches/BOLT-PGO.cmake +index 1a04ca9a74e5..d092820e4115 100644 +--- a/clang/cmake/caches/BOLT-PGO.cmake ++++ b/clang/cmake/caches/BOLT-PGO.cmake +@@ -4,6 +4,8 @@ set(CLANG_BOOTSTRAP_TARGETS + stage2-clang-bolt + stage2-distribution + stage2-install-distribution ++ clang ++ lld + CACHE STRING "") + set(BOOTSTRAP_CLANG_BOOTSTRAP_TARGETS + clang-bolt diff --git a/.github/workflows/containers/github-action-ci/stage1.Dockerfile b/.github/workflows/containers/github-action-ci/stage1.Dockerfile new file mode 100644 index 0000000000000000000000000000000000000000..fbc4548e6636e8f8c7313c27bfea12ae03556736 --- /dev/null +++ b/.github/workflows/containers/github-action-ci/stage1.Dockerfile @@ -0,0 +1,44 @@ +FROM docker.io/library/ubuntu:22.04 as base +ENV LLVM_SYSROOT=/opt/llvm + +FROM base as stage1-toolchain +ENV LLVM_VERSION=17.0.6 + +RUN apt-get update && \ + apt-get install -y \ + wget \ + gcc \ + g++ \ + cmake \ + ninja-build \ + python3 \ + git \ + curl + +RUN curl -O -L https://github.com/llvm/llvm-project/archive/refs/tags/llvmorg-$LLVM_VERSION.tar.gz && tar -xf llvmorg-$LLVM_VERSION.tar.gz + +WORKDIR /llvm-project-llvmorg-$LLVM_VERSION + +COPY bootstrap.patch / + +# TODO(boomanaiden154): Remove the patch pulled from a LLVM PR once we bump +# the toolchain to version 18 and the patch is in-tree. +# TODO(boomanaiden154): Remove the bootstrap patch once we unsplit the build +# and no longer need to explicitly build the stage2 dependencies. +RUN curl https://github.com/llvm/llvm-project/commit/dd0356d741aefa25ece973d6cc4b55dcb73b84b4.patch | patch -p1 && cat /bootstrap.patch | patch -p1 + +RUN mkdir build + +RUN cmake -B ./build -G Ninja ./llvm \ + -C ./clang/cmake/caches/BOLT-PGO.cmake \ + -DBOOTSTRAP_LLVM_ENABLE_LLD=ON \ + -DBOOTSTRAP_BOOTSTRAP_LLVM_ENABLE_LLD=ON \ + -DPGO_INSTRUMENT_LTO=Thin \ + -DLLVM_ENABLE_RUNTIMES="compiler-rt" \ + -DCMAKE_INSTALL_PREFIX="$LLVM_SYSROOT" \ + -DLLVM_ENABLE_PROJECTS="bolt;clang;lld;clang-tools-extra" \ + -DLLVM_DISTRIBUTION_COMPONENTS="lld;compiler-rt;clang-format" \ + -DCLANG_DEFAULT_LINKER="lld" \ + -DBOOTSTRAP_CLANG_PGO_TRAINING_DATA_SOURCE_DIR=/llvm-project-llvmorg-$LLVM_VERSION/llvm + +RUN ninja -C ./build stage2-instrumented-clang stage2-instrumented-lld diff --git a/.github/workflows/containers/github-action-ci/stage2.Dockerfile b/.github/workflows/containers/github-action-ci/stage2.Dockerfile new file mode 100644 index 0000000000000000000000000000000000000000..e1a06cb68a589e38ae0b27014f63a729cf0ea791 --- /dev/null +++ b/.github/workflows/containers/github-action-ci/stage2.Dockerfile @@ -0,0 +1,27 @@ +FROM docker.io/library/ubuntu:22.04 as base +ENV LLVM_SYSROOT=/opt/llvm + +FROM stage1-toolchain AS stage2-toolchain + +RUN ninja -C ./build stage2-clang-bolt stage2-install-distribution && ninja -C ./build install-distribution && rm -rf ./build + +FROM base + +COPY --from=stage2-toolchain $LLVM_SYSROOT $LLVM_SYSROOT + +# Need to install curl for hendrikmuhs/ccache-action +# Need nodejs for some of the GitHub actions. +# Need perl-modules for clang analyzer tests. +RUN apt-get update && \ + apt-get install -y \ + binutils \ + cmake \ + curl \ + libstdc++-11-dev \ + ninja-build \ + nodejs \ + perl-modules \ + python3-psutil + +ENV LLVM_SYSROOT=$LLVM_SYSROOT +ENV PATH=${LLVM_SYSROOT}/bin:${PATH} diff --git a/.github/workflows/containers/github-action-ci/storage.conf b/.github/workflows/containers/github-action-ci/storage.conf new file mode 100644 index 0000000000000000000000000000000000000000..60f295ff1e9696b93fb61be2953c552189ffa9ea --- /dev/null +++ b/.github/workflows/containers/github-action-ci/storage.conf @@ -0,0 +1,4 @@ +[storage] + driver = "overlay" + runroot = "/mnt/podman/container" + graphroot = "/mnt/podman/image" diff --git a/.github/workflows/libclc-tests.yml b/.github/workflows/libclc-tests.yml index 29d050db2f12c017e90278ee487be5e3c2475db1..23192f776a985e1cc6ddc0c199e31ed50b31e168 100644 --- a/.github/workflows/libclc-tests.yml +++ b/.github/workflows/libclc-tests.yml @@ -36,5 +36,4 @@ jobs: name: Test libclc uses: ./.github/workflows/llvm-project-tests.yml with: - build_target: '' projects: clang;libclc diff --git a/.github/workflows/lldb-tests.yml b/.github/workflows/lldb-tests.yml index ef5d7c7d581b7d6310c7b66659908b2a7063acdf..6bb9721956258f13d3b684f9c3cdd943bf22d250 100644 --- a/.github/workflows/lldb-tests.yml +++ b/.github/workflows/lldb-tests.yml @@ -36,5 +36,4 @@ jobs: name: Build lldb uses: ./.github/workflows/llvm-project-tests.yml with: - build_target: '' projects: clang;lldb diff --git a/.github/workflows/llvm-project-tests.yml b/.github/workflows/llvm-project-tests.yml index 494263be7f0dfec8a11d8875a85a9b438380de3b..68b4a68d1af9846c91d16e906b50048e00f686a3 100644 --- a/.github/workflows/llvm-project-tests.yml +++ b/.github/workflows/llvm-project-tests.yml @@ -22,8 +22,9 @@ on: workflow_call: inputs: build_target: - required: true + required: false type: string + default: "all" projects: required: true @@ -103,14 +104,16 @@ jobs: # This should be a no-op for non-mac OSes PKG_CONFIG_PATH: /usr/local/Homebrew/Library/Homebrew/os/mac/pkgconfig//12 shell: bash + id: build-llvm run: | if [ "${{ runner.os }}" == "Linux" ]; then builddir="/mnt/build/" sudo mkdir -p $builddir sudo chown `whoami`:`whoami` $builddir else - builddir=build + builddir="$(pwd)"/build fi + echo "llvm-builddir=$builddir" >> "$GITHUB_OUTPUT" cmake -G Ninja \ -B "$builddir" \ -S llvm \ @@ -125,9 +128,11 @@ jobs: - name: Build and Test libclc if: "!startsWith(matrix.os, 'windows') && contains(inputs.projects, 'libclc')" + env: + LLVM_BUILDDIR: ${{ steps.build-llvm.outputs.llvm-builddir }} run: | # Make sure all of LLVM libraries that llvm-config needs are built. - ninja -C build - cmake -G Ninja -S libclc -B libclc-build -DLLVM_DIR="$(pwd)"/build/lib/cmake/llvm -DLIBCLC_TARGETS_TO_BUILD="amdgcn--;amdgcn--amdhsa;r600--;nvptx--;nvptx64--;nvptx--nvidiacl;nvptx64--nvidiacl" + ninja -C "$LLVM_BUILDDIR" + cmake -G Ninja -S libclc -B libclc-build -DLLVM_DIR="$LLVM_BUILDDIR"/lib/cmake/llvm -DLIBCLC_TARGETS_TO_BUILD="amdgcn--;amdgcn--amdhsa;r600--;nvptx--;nvptx64--;nvptx--nvidiacl;nvptx64--nvidiacl" ninja -C libclc-build ninja -C libclc-build test diff --git a/bolt/lib/Core/BinarySection.cpp b/bolt/lib/Core/BinarySection.cpp index a8fc4f07bd3e8f96e926593d41a6270612840c2d..97bc25193547539daf434dfce70cfe984007b9a3 100644 --- a/bolt/lib/Core/BinarySection.cpp +++ b/bolt/lib/Core/BinarySection.cpp @@ -72,7 +72,8 @@ BinarySection::hash(const BinaryData &BD, void BinarySection::emitAsData(MCStreamer &Streamer, const Twine &SectionName) const { - StringRef SectionContents = getContents(); + StringRef SectionContents = + isFinalized() ? getOutputContents() : getContents(); MCSectionELF *ELFSection = BC.Ctx->getELFSection(SectionName, getELFType(), getELFFlags()); diff --git a/bolt/lib/Passes/BinaryPasses.cpp b/bolt/lib/Passes/BinaryPasses.cpp index 8505d37491415fcf8be30da711fdde2deb10df33..bcb12272d1b466e0b8b769ea9845e3c268eb5ae6 100644 --- a/bolt/lib/Passes/BinaryPasses.cpp +++ b/bolt/lib/Passes/BinaryPasses.cpp @@ -582,6 +582,7 @@ bool CheckLargeFunctions::shouldOptimize(const BinaryFunction &BF) const { } void LowerAnnotations::runOnFunctions(BinaryContext &BC) { + // Convert GnuArgsSize annotations into CFIs. for (BinaryFunction *BF : BC.getAllBinaryFunctions()) { for (FunctionFragment &FF : BF->getLayout().fragments()) { // Reset at the start of the new fragment. @@ -589,43 +590,23 @@ void LowerAnnotations::runOnFunctions(BinaryContext &BC) { for (BinaryBasicBlock *const BB : FF) { for (auto II = BB->begin(); II != BB->end(); ++II) { - - // Convert GnuArgsSize annotations into CFIs. - if (BF->usesGnuArgsSize() && BC.MIB->isInvoke(*II)) { - const int64_t NewGnuArgsSize = BC.MIB->getGnuArgsSize(*II); - assert(NewGnuArgsSize >= 0 && - "Expected non-negative GNU_args_size."); - if (NewGnuArgsSize != CurrentGnuArgsSize) { - auto InsertII = BF->addCFIInstruction( - BB, II, - MCCFIInstruction::createGnuArgsSize(nullptr, NewGnuArgsSize)); - CurrentGnuArgsSize = NewGnuArgsSize; - II = std::next(InsertII); - } - } - - // Preserve selected annotations and strip the rest. - std::optional Offset = BF->requiresAddressTranslation() - ? BC.MIB->getOffset(*II) - : std::nullopt; - std::optional Size = BC.MIB->getSize(*II); - MCSymbol *Label = BC.MIB->getLabel(*II); - - BC.MIB->stripAnnotations(*II); - - if (Offset) - BC.MIB->setOffset(*II, *Offset); - if (Size) - BC.MIB->setSize(*II, *Size); - if (Label) - BC.MIB->setLabel(*II, Label); + if (!BF->usesGnuArgsSize() || !BC.MIB->isInvoke(*II)) + continue; + + const int64_t NewGnuArgsSize = BC.MIB->getGnuArgsSize(*II); + assert(NewGnuArgsSize >= 0 && "Expected non-negative GNU_args_size."); + if (NewGnuArgsSize == CurrentGnuArgsSize) + continue; + + auto InsertII = BF->addCFIInstruction( + BB, II, + MCCFIInstruction::createGnuArgsSize(nullptr, NewGnuArgsSize)); + CurrentGnuArgsSize = NewGnuArgsSize; + II = std::next(InsertII); } } } } - - // Release all memory taken by annotations - BC.MIB->freeAnnotations(); } // Check for dirty state in MCSymbol objects that might be a consequence diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index 0fa5dcee64a329cc6f6b706deb61415e667ff4ea..9a242d94dd773302931ee56344ac2c2bfdca46c7 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -2524,7 +2524,7 @@ void RewriteInstance::handleRelocation(const SectionRef &RelocatedSection, Expected SectionName = Section->getName(); if (SectionName && !SectionName->empty()) ReferencedSection = BC->getUniqueSectionByName(*SectionName); - } else if (ReferencedSymbol && + } else if (ReferencedSymbol && ContainingBF && (cantFail(Symbol.getFlags()) & SymbolRef::SF_Absolute)) { // This might be a relocation for an ABS symbols like __global_pointer$ on // RISC-V diff --git a/bolt/test/AArch64/ifunc.c b/bolt/test/AArch64/ifunc.c index c8c5c7c29d4a56d7e46ef33ef0406a76a7284a53..1744976f05b22cd4298c4d30065bb05f5beb37c4 100644 --- a/bolt/test/AArch64/ifunc.c +++ b/bolt/test/AArch64/ifunc.c @@ -51,8 +51,11 @@ // REL_CHECK: [[#REL_SYMB_ADDR]] {{.*}} FUNC {{.*}} resolver_foo static void foo() {} +static void bar() {} -static void *resolver_foo(void) { return foo; } +extern int use_foo; + +static void *resolver_foo(void) { return use_foo ? foo : bar; } __attribute__((ifunc("resolver_foo"))) void ifoo(); diff --git a/clang-tools-extra/clang-tidy/readability/CMakeLists.txt b/clang-tools-extra/clang-tidy/readability/CMakeLists.txt index a6c8cbd8eb448a8111af7f598b473981f8d971eb..5728c9970fb65d5334225cce3d3db69e013bdf62 100644 --- a/clang-tools-extra/clang-tidy/readability/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/readability/CMakeLists.txt @@ -55,6 +55,7 @@ add_clang_library(clangTidyReadabilityModule UniqueptrDeleteReleaseCheck.cpp UppercaseLiteralSuffixCheck.cpp UseAnyOfAllOfCheck.cpp + UseStdMinMaxCheck.cpp LINK_LIBS clangTidy diff --git a/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp b/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp index 87b299bf1ef1c57df47f7fc2955a10a5748bb0d1..bca2c425111f6cd1594316ca05971d290dbf1062 100644 --- a/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/readability/ReadabilityTidyModule.cpp @@ -58,6 +58,7 @@ #include "UniqueptrDeleteReleaseCheck.h" #include "UppercaseLiteralSuffixCheck.h" #include "UseAnyOfAllOfCheck.h" +#include "UseStdMinMaxCheck.h" namespace clang::tidy { namespace readability { @@ -163,6 +164,8 @@ public: "readability-uppercase-literal-suffix"); CheckFactories.registerCheck( "readability-use-anyofallof"); + CheckFactories.registerCheck( + "readability-use-std-min-max"); } }; diff --git a/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c5c2f3939c99bb3c24c2bd4f393bd6e2363867c --- /dev/null +++ b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.cpp @@ -0,0 +1,188 @@ +//===--- UseStdMinMaxCheck.cpp - clang-tidy -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "UseStdMinMaxCheck.h" +#include "../utils/ASTUtils.h" +#include "clang/AST/ASTContext.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/Lex/Preprocessor.h" + +using namespace clang::ast_matchers; + +namespace clang::tidy::readability { + +namespace { + +// Ignore if statements that are inside macros. +AST_MATCHER(IfStmt, isIfInMacro) { + return Node.getIfLoc().isMacroID() || Node.getEndLoc().isMacroID(); +} + +} // namespace + +static const llvm::StringRef AlgorithmHeader(""); + +static bool minCondition(const BinaryOperator::Opcode Op, const Expr *CondLhs, + const Expr *CondRhs, const Expr *AssignLhs, + const Expr *AssignRhs, const ASTContext &Context) { + if ((Op == BO_LT || Op == BO_LE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignRhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignLhs, Context))) + return true; + + if ((Op == BO_GT || Op == BO_GE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignLhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignRhs, Context))) + return true; + + return false; +} + +static bool maxCondition(const BinaryOperator::Opcode Op, const Expr *CondLhs, + const Expr *CondRhs, const Expr *AssignLhs, + const Expr *AssignRhs, const ASTContext &Context) { + if ((Op == BO_LT || Op == BO_LE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignLhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignRhs, Context))) + return true; + + if ((Op == BO_GT || Op == BO_GE) && + (tidy::utils::areStatementsIdentical(CondLhs, AssignRhs, Context) && + tidy::utils::areStatementsIdentical(CondRhs, AssignLhs, Context))) + return true; + + return false; +} + +QualType getNonTemplateAlias(QualType QT) { + while (true) { + // cast to a TypedefType + if (const TypedefType *TT = dyn_cast(QT)) { + // check if the typedef is a template and if it is dependent + if (!TT->getDecl()->getDescribedTemplate() && + !TT->getDecl()->getDeclContext()->isDependentContext()) + return QT; + QT = TT->getDecl()->getUnderlyingType(); + } + // cast to elaborated type + else if (const ElaboratedType *ET = dyn_cast(QT)) { + QT = ET->getNamedType(); + } else { + break; + } + } + return QT; +} + +static std::string createReplacement(const Expr *CondLhs, const Expr *CondRhs, + const Expr *AssignLhs, + const SourceManager &Source, + const LangOptions &LO, + StringRef FunctionName, + const BinaryOperator *BO) { + const llvm::StringRef CondLhsStr = Lexer::getSourceText( + Source.getExpansionRange(CondLhs->getSourceRange()), Source, LO); + const llvm::StringRef CondRhsStr = Lexer::getSourceText( + Source.getExpansionRange(CondRhs->getSourceRange()), Source, LO); + const llvm::StringRef AssignLhsStr = Lexer::getSourceText( + Source.getExpansionRange(AssignLhs->getSourceRange()), Source, LO); + + clang::QualType GlobalImplicitCastType; + clang::QualType LhsType = CondLhs->getType() + .getCanonicalType() + .getNonReferenceType() + .getUnqualifiedType(); + clang::QualType RhsType = CondRhs->getType() + .getCanonicalType() + .getNonReferenceType() + .getUnqualifiedType(); + if (LhsType != RhsType) { + GlobalImplicitCastType = getNonTemplateAlias(BO->getLHS()->getType()); + } + + return (AssignLhsStr + " = " + FunctionName + + (!GlobalImplicitCastType.isNull() + ? "<" + GlobalImplicitCastType.getAsString() + ">(" + : "(") + + CondLhsStr + ", " + CondRhsStr + ");") + .str(); +} + +UseStdMinMaxCheck::UseStdMinMaxCheck(StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context), + IncludeInserter(Options.getLocalOrGlobal("IncludeStyle", + utils::IncludeSorter::IS_LLVM), + areDiagsSelfContained()) {} + +void UseStdMinMaxCheck::storeOptions(ClangTidyOptions::OptionMap &Opts) { + Options.store(Opts, "IncludeStyle", IncludeInserter.getStyle()); +} + +void UseStdMinMaxCheck::registerMatchers(MatchFinder *Finder) { + auto AssignOperator = + binaryOperator(hasOperatorName("="), + hasLHS(expr(unless(isTypeDependent())).bind("AssignLhs")), + hasRHS(expr(unless(isTypeDependent())).bind("AssignRhs"))); + auto BinaryOperator = + binaryOperator(hasAnyOperatorName("<", ">", "<=", ">="), + hasLHS(expr(unless(isTypeDependent())).bind("CondLhs")), + hasRHS(expr(unless(isTypeDependent())).bind("CondRhs"))) + .bind("binaryOp"); + Finder->addMatcher( + ifStmt(stmt().bind("if"), unless(isIfInMacro()), + unless(hasElse(stmt())), // Ensure `if` has no `else` + hasCondition(BinaryOperator), + hasThen( + anyOf(stmt(AssignOperator), + compoundStmt(statementCountIs(1), has(AssignOperator)))), + hasParent(stmt(unless(ifStmt(hasElse( + equalsBoundNode("if"))))))), // Ensure `if` has no `else if` + this); +} + +void UseStdMinMaxCheck::registerPPCallbacks(const SourceManager &SM, + Preprocessor *PP, + Preprocessor *ModuleExpanderPP) { + IncludeInserter.registerPreprocessor(PP); +} + +void UseStdMinMaxCheck::check(const MatchFinder::MatchResult &Result) { + const auto *If = Result.Nodes.getNodeAs("if"); + const clang::LangOptions &LO = Result.Context->getLangOpts(); + const auto *CondLhs = Result.Nodes.getNodeAs("CondLhs"); + const auto *CondRhs = Result.Nodes.getNodeAs("CondRhs"); + const auto *AssignLhs = Result.Nodes.getNodeAs("AssignLhs"); + const auto *AssignRhs = Result.Nodes.getNodeAs("AssignRhs"); + const auto *BinaryOp = Result.Nodes.getNodeAs("binaryOp"); + const clang::BinaryOperatorKind BinaryOpcode = BinaryOp->getOpcode(); + const SourceLocation IfLocation = If->getIfLoc(); + const SourceLocation ThenLocation = If->getEndLoc(); + + auto ReplaceAndDiagnose = [&](const llvm::StringRef FunctionName) { + const SourceManager &Source = *Result.SourceManager; + diag(IfLocation, "use `%0` instead of `%1`") + << FunctionName << BinaryOp->getOpcodeStr() + << FixItHint::CreateReplacement( + SourceRange(IfLocation, Lexer::getLocForEndOfToken( + ThenLocation, 0, Source, LO)), + createReplacement(CondLhs, CondRhs, AssignLhs, Source, LO, + FunctionName, BinaryOp)) + << IncludeInserter.createIncludeInsertion( + Source.getFileID(If->getBeginLoc()), AlgorithmHeader); + }; + + if (minCondition(BinaryOpcode, CondLhs, CondRhs, AssignLhs, AssignRhs, + (*Result.Context))) { + ReplaceAndDiagnose("std::min"); + } else if (maxCondition(BinaryOpcode, CondLhs, CondRhs, AssignLhs, AssignRhs, + (*Result.Context))) { + ReplaceAndDiagnose("std::max"); + } +} + +} // namespace clang::tidy::readability diff --git a/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h new file mode 100644 index 0000000000000000000000000000000000000000..b8d8b8c4fe894a311c2930d3f96e75221be6cf18 --- /dev/null +++ b/clang-tools-extra/clang-tidy/readability/UseStdMinMaxCheck.h @@ -0,0 +1,42 @@ +//===--- UseStdMinMaxCheck.h - clang-tidy -----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_USESTDMINMAXCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_USESTDMINMAXCHECK_H + +#include "../ClangTidyCheck.h" +#include "../utils/IncludeInserter.h" + +namespace clang::tidy::readability { + +/// Replaces certain conditional statements with equivalent calls to +/// ``std::min`` or ``std::max``. +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/readability/UseStdMinMax.html +class UseStdMinMaxCheck : public ClangTidyCheck { +public: + UseStdMinMaxCheck(StringRef Name, ClangTidyContext *Context); + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus; + } + void registerPPCallbacks(const SourceManager &SM, Preprocessor *PP, + Preprocessor *ModuleExpanderPP) override; + void storeOptions(ClangTidyOptions::OptionMap &Opts) override; + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + std::optional getCheckTraversalKind() const override { + return TK_IgnoreUnlessSpelledInSource; + } + +private: + utils::IncludeInserter IncludeInserter; +}; + +} // namespace clang::tidy::readability + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_READABILITY_USESTDMINMAXCHECK_H diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 16309bd89bda4e8f3236232d6347253454a89ac0..e50914aed5f07a0c384b50b3ffd31805722a4a0b 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -100,6 +100,12 @@ Improvements to clang-tidy New checks ^^^^^^^^^^ +- New :doc:`readability-use-std-min-max + ` check. + + Replaces certain conditional statements with equivalent calls to + ``std::min`` or ``std::max``. + New check aliases ^^^^^^^^^^^^^^^^^ diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index f40192ed9dea274015df860ebb9d821b25dd3989..59ef69f390ee91211f28751513178f7e43388de5 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -385,6 +385,7 @@ Clang-Tidy Checks :doc:`readability-uniqueptr-delete-release `, "Yes" :doc:`readability-uppercase-literal-suffix `, "Yes" :doc:`readability-use-anyofallof `, + :doc:`readability-use-std-min-max `, "Yes" :doc:`zircon-temporary-objects `, diff --git a/clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst b/clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst new file mode 100644 index 0000000000000000000000000000000000000000..73712bdba83b7a261bfe6c1e9fbb15cb49fef00d --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/readability/use-std-min-max.rst @@ -0,0 +1,29 @@ +.. title:: clang-tidy - readability-use-std-min-max + +readability-use-std-min-max +=========================== + +Replaces certain conditional statements with equivalent calls to +``std::min`` or ``std::max``. +Note: This may impact performance in critical code due to potential +additional stores compared to the original if statement. + +Before: + +.. code-block:: c++ + + void foo() { + int a = 2, b = 3; + if (a < b) + a = b; + } + + +After: + +.. code-block:: c++ + + void foo() { + int a = 2, b = 3; + a = std::max(a, b); + } diff --git a/clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp b/clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp new file mode 100644 index 0000000000000000000000000000000000000000..9c0e2eabda348d5c647bc1d8a02226e58bb1a460 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/readability/use-std-min-max.cpp @@ -0,0 +1,254 @@ +// RUN: %check_clang_tidy -std=c++11-or-later %s readability-use-std-min-max %t -- -- -fno-delayed-template-parsing +#define MY_MACRO_MIN(a, b) ((a) < (b) ? (a) : (b)) + +constexpr int myConstexprMin(int a, int b) { + return a < b ? a : b; +} + +constexpr int myConstexprMax(int a, int b) { + return a > b ? a : b; +} + +#define MY_IF_MACRO(condition, statement) \ + if (condition) { \ + statement \ + } + +class MyClass { +public: + int member1; + int member2; +}; + +template + +void foo(T value7) { + int value1,value2,value3; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value2); + if (value1 < value2) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value1, value2); + if (value1 < value2) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value2, value1); + if (value2 > value1) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value2, value1); + if (value2 > value1) + value1 = value2; + + // No suggestion needed here + if (value1 == value2) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+3]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value4); + short value4; + if(value1` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::min(value1, myConstexprMax(value2, value3)); + if (value1 > myConstexprMax(value2, value3)) + value1 = myConstexprMax(value2, value3); + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value1, value2); + if (value1 <= value2) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value2); + if (value1 <= value2) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value2, value1); + if (value2 >= value1) + value1 = value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: value2 = std::min(value2, value1); + if (value2 >= value1) + value2 = value1; + + // CHECK-MESSAGES: :[[@LINE+3]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: obj.member1 = std::max(obj.member1, obj.member2); + MyClass obj; + if (obj.member1 < obj.member2) + obj.member1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(obj.member1, obj.member2); + if (obj.member1 < obj.member2) + obj.member2 = obj.member1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(obj.member2, obj.member1); + if (obj.member2 > obj.member1) + obj.member2 = obj.member1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: obj.member1 = std::max(obj.member2, obj.member1); + if (obj.member2 > obj.member1) + obj.member1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: obj.member1 = std::max(obj.member1, value4); + if (obj.member1 < value4) + obj.member1 = value4; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value3 = std::min(obj.member1 + value2, value3); + if (obj.member1 + value2 < value3) + value3 = obj.member1 + value2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(value1, obj.member2); + if (value1 <= obj.member2) + obj.member2 = value1; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, obj.member2); + if (value1 <= obj.member2) + value1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(obj.member2, value1); + if (obj.member2 >= value1) + value1 = obj.member2; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::min` instead of `>=` [readability-use-std-min-max] + // CHECK-FIXES: obj.member2 = std::min(obj.member2, value1); + if (obj.member2 >= value1) + obj.member2 = value1; + + // No suggestion needed here + if (MY_MACRO_MIN(value1, value2) < value3) + value3 = MY_MACRO_MIN(value1, value2); + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value4 = std::max(value4, value2); + if (value4 < value2){ + value4 = value2; + } + + // No suggestion needed here + if(value1 < value2) + value2 = value1; + else + value2 = value3; + + // No suggestion needed here + if(value1value2){ + value2 = value1; + } + + // CHECK-MESSAGES: :[[@LINE+3]]:5: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value1 = std::max(value1, value3); + if(value1 == value2){ + if(value1(value1, value4); + if(value1 == value2){ + if(value2 == value3){ + value3+=1; + if(value1value2){ + value2 = value3; + } + } + + // CHECK-MESSAGES: :[[@LINE+4]]:3: warning: use `std::min` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value6 = std::min(value5, value6); + unsigned int value5; + unsigned char value6; + if(value5 +struct MyVector +{ + using size_type = my_size; + size_type size() const; +}; + +void testVectorSizeType() { + MyVector v; + unsigned int value; + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `>` [readability-use-std-min-max] + // CHECK-FIXES: value = std::max(v.size(), value); + if (v.size() > value) + value = v.size(); + + // CHECK-MESSAGES: :[[@LINE+2]]:3: warning: use `std::max` instead of `<` [readability-use-std-min-max] + // CHECK-FIXES: value = std::max(value, v.size()); + if (value < v.size()) + value = v.size(); +} diff --git a/clang/docs/ClangFormatStyleOptions.rst b/clang/docs/ClangFormatStyleOptions.rst index 976d9e2716ef3f0267266738d049076c5ca0202f..0a8cc18c5b4cb583ce36caa8c4420bda59c0eb1a 100644 --- a/clang/docs/ClangFormatStyleOptions.rst +++ b/clang/docs/ClangFormatStyleOptions.rst @@ -1664,6 +1664,18 @@ the configuration (without a prefix: ``Auto``). Possible values: + * ``BTDS_Leave`` (in configuration: ``Leave``) + Do not change the line breaking before the declaration. + + .. code-block:: c++ + + template + T foo() { + } + template T foo(int aaaaaaaaaaaaaaaaaaaaa, + int bbbbbbbbbbbbbbbbbbbbb) { + } + * ``BTDS_No`` (in configuration: ``No``) Do not force break before declaration. ``PenaltyBreakTemplateDeclaration`` is taken into account. @@ -4142,6 +4154,25 @@ the configuration (without a prefix: ``Auto``). A(z); -> z; A(a, b); // will not be expanded. +.. _MainIncludeChar: + +**MainIncludeChar** (``MainIncludeCharDiscriminator``) :versionbadge:`clang-format 18` :ref:`¶ ` + When guessing whether a #include is the "main" include, only the include + directives that use the specified character are considered. + + Possible values: + + * ``MICD_Quote`` (in configuration: ``Quote``) + Main include uses quotes: ``#include "foo.hpp"`` (the default). + + * ``MICD_AngleBracket`` (in configuration: ``AngleBracket``) + Main include uses angle brackets: ``#include ``. + + * ``MICD_Any`` (in configuration: ``Any``) + Main include uses either quotes or angle brackets. + + + .. _MaxEmptyLinesToKeep: **MaxEmptyLinesToKeep** (``Unsigned``) :versionbadge:`clang-format 3.7` :ref:`¶ ` diff --git a/clang/docs/ClangLinkerWrapper.rst b/clang/docs/ClangLinkerWrapper.rst index fbabb4f8613b3a77caa0b11bef0d88577a7acb37..6d7770b50e7260014a3fa197d12256232b975c65 100644 --- a/clang/docs/ClangLinkerWrapper.rst +++ b/clang/docs/ClangLinkerWrapper.rst @@ -54,12 +54,30 @@ only for the linker wrapper will be forwarded to the wrapped linker job. --pass-remarks= Pass remarks for LTO --print-wrapped-module Print the wrapped module's IR for testing --ptxas-arg= Argument to pass to the 'ptxas' invocation + --relocatable Link device code to create a relocatable offloading application --save-temps Save intermediate results --sysroot Set the system root --verbose Verbose output from tools --v Display the version number and exit -- The separator for the wrapped linker arguments +Relocatable Linking +=================== + +The ``clang-linker-wrapper`` handles linking embedded device code and then +registering it with the appropriate runtime. Normally, this is only done when +the executable is created so other files containing device code can be linked +together. This can be somewhat problematic for users who wish to ship static +libraries that contain offloading code to users without a compatible offloading +toolchain. + +When using a relocatable link with ``-r``, the ``clang-linker-wrapper`` will +perform the device linking and registration eagerly. This will remove the +embedded device code and register it correctly with the runtime. Semantically, +this is similar to creating a shared library object. If standard relocatable +linking is desired, simply do not run the binaries through the +``clang-linker-wrapper``. This will simply append the embedded device code so +that it can be linked later. Example ======= diff --git a/clang/docs/OffloadingDesign.rst b/clang/docs/OffloadingDesign.rst index 209b89e0c5a165d3edcba69f55abd8a31e1d26ac..13bb924a77ad0b9afa17bca2a7dd336c324e8b32 100644 --- a/clang/docs/OffloadingDesign.rst +++ b/clang/docs/OffloadingDesign.rst @@ -470,3 +470,37 @@ We can see the steps created by clang to generate the offloading code using the # "nvptx64-nvidia-cuda" - "NVPTX::Assembler", inputs: ["/tmp/zaxpy-07f434.s"], output: "/tmp/zaxpy-0af7b7.o" # "x86_64-unknown-linux-gnu" - "clang", inputs: ["/tmp/zaxpy-e6a41b.bc", "/tmp/zaxpy-0af7b7.o"], output: "/tmp/zaxpy-416cad.o" # "x86_64-unknown-linux-gnu" - "Offload::Linker", inputs: ["/tmp/zaxpy-416cad.o"], output: "a.out" + +Relocatable Linking +------------------- + +The offloading compilation pipeline normally will defer the final device linking +and runtime registration until the ``clang-linker-wrapper`` is run to create the +executable. This is the standard behaviour when compiling for OpenMP offloading +or CUDA and HIP in ``-fgpu-rdc`` mode. However, there are some cases where the +user may wish to perform this device handling prematurely. This is described in +the :doc:`linker wrapper documentation`. + +Effectively, this allows the user to handle offloading specific linking ahead of +time when shipping objects or static libraries. This can be thought of as +performing a standard ``-fno-gpu-rdc`` compilation on a subset of object files. +This can be useful to reduce link time, prevent users from interacting with the +library's device code, or for shipping libraries to incompatible compilers. + +Normally, if a relocatable link is done using ``clang -r`` it will simply merge +the ``.llvm.offloading`` sections which will then be linked later when the +executable is created. However, if the ``-r`` flag is used with the offloading +toolchain, it will perform the device linking and registration phases and then +merge the registration code into the final relocatable object file. + +The following example shows how using the relocatable link with the offloading +pipeline can create a static library with offloading code that can be +redistributed without requiring any additional handling. + +.. code-block:: console + + $ clang++ -fopenmp -fopenmp-targets=nvptx64 foo.cpp -c + $ clang++ -lomptarget.devicertl --offload-link -r foo.o -o merged.o + $ llvm-ar rcs libfoo.a merged.o + # g++ app.cpp -L. -lfoo + diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 3596109bf044f06e31c047e780e21c4311fe1ec0..52a48c750fe55bfc4de2ac46b489e81d601da62b 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -164,6 +164,10 @@ Bug Fixes in This Version - Clang now accepts qualified partial/explicit specializations of variable templates that are not nominable in the lookup context of the specialization. +- Clang now doesn't produce false-positive warning `-Wconstant-logical-operand` + for logical operators in C23. + Fixes (`#64356 `_). + Bug Fixes to Compiler Builtins ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ @@ -197,10 +201,15 @@ Bug Fixes to C++ Support Fixes (`#67976 `_) - Fix crash and diagnostic with const qualified member operator new. Fixes (`#79748 `_) +- Fixed a crash where substituting into a requires-expression that involves parameter packs + during the equivalence determination of two constraint expressions. + (`#72557 `_) - Fix a crash when specializing an out-of-line member function with a default parameter where we did an incorrect specialization of the initialization of the default parameter. Fixes (`#68490 `_) +- Fix a crash when trying to call a varargs function that also has an explicit object parameter. + Fixes (`#80971 ICE when explicit object parameter be a function parameter pack`) Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index d6a55f39a4bede1c1602a9b12857863dbd0cb8fb..1942b0e67f65a3157a36ae1b7dbf55bf9398a10f 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -2613,6 +2613,9 @@ public: /// Return true if this is a fixed point or integer type. bool isFixedPointOrIntegerType() const; + /// Return true if this can be converted to (or from) a fixed point type. + bool isConvertibleToFixedPointType() const; + /// Return true if this is a saturated fixed point type according to /// ISO/IEC JTC1 SC22 WG14 N1169. This type can be signed or unsigned. bool isSaturatedFixedPointType() const; @@ -7493,6 +7496,10 @@ inline bool Type::isFixedPointOrIntegerType() const { return isFixedPointType() || isIntegerType(); } +inline bool Type::isConvertibleToFixedPointType() const { + return isRealFloatingType() || isFixedPointOrIntegerType(); +} + inline bool Type::isSaturatedFixedPointType() const { if (const auto *BT = dyn_cast(CanonicalType)) { return BT->getKind() >= BuiltinType::SatShortAccum && diff --git a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h index 1543f900e401d6d55d309547ab09b286e616d4b5..5c737a561a7c1389dd4af549f6f6505f98df488f 100644 --- a/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h +++ b/clang/include/clang/Analysis/FlowSensitive/DataflowEnvironment.h @@ -19,7 +19,6 @@ #include "clang/AST/DeclBase.h" #include "clang/AST/Expr.h" #include "clang/AST/Type.h" -#include "clang/Analysis/FlowSensitive/ControlFlowContext.h" #include "clang/Analysis/FlowSensitive/DataflowAnalysisContext.h" #include "clang/Analysis/FlowSensitive/DataflowLattice.h" #include "clang/Analysis/FlowSensitive/Formula.h" @@ -31,7 +30,6 @@ #include "llvm/ADT/MapVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" -#include #include #include @@ -81,6 +79,8 @@ public: return ComparisonResult::Unknown; } + /// DEPRECATED. Override `join` and/or `widen`, instead. + /// /// Modifies `MergedVal` to approximate both `Val1` and `Val2`. This could /// be a strict lattice join or a more general widening operation. /// @@ -105,6 +105,28 @@ public: return true; } + /// Modifies `JoinedVal` to approximate both `Val1` and `Val2`. This should + /// obey the properties of a lattice join. + /// + /// `Env1` and `Env2` can be used to query child values and path condition + /// implications of `Val1` and `Val2` respectively. + /// + /// Requirements: + /// + /// `Val1` and `Val2` must be distinct. + /// + /// `Val1`, `Val2`, and `JoinedVal` must model values of type `Type`. + /// + /// `Val1` and `Val2` must be assigned to the same storage location in + /// `Env1` and `Env2` respectively. + virtual void join(QualType Type, const Value &Val1, const Environment &Env1, + const Value &Val2, const Environment &Env2, + Value &JoinedVal, Environment &JoinedEnv) { + [[maybe_unused]] bool ShouldKeep = + merge(Type, Val1, Env1, Val2, Env2, JoinedVal, JoinedEnv); + assert(ShouldKeep && "dropping merged value is unsupported"); + } + /// This function may widen the current value -- replace it with an /// approximation that can reach a fixed point more quickly than iterated /// application of the transfer function alone. The previous value is diff --git a/clang/include/clang/Basic/BuiltinsAMDGPU.def b/clang/include/clang/Basic/BuiltinsAMDGPU.def index 5f8001e61a028249ce15859305d157e48a17f2f1..213311b96df74f0872ad1e3bf2224906cdca8582 100644 --- a/clang/include/clang/Basic/BuiltinsAMDGPU.def +++ b/clang/include/clang/Basic/BuiltinsAMDGPU.def @@ -69,6 +69,7 @@ BUILTIN(__builtin_amdgcn_s_dcache_inv, "v", "n") BUILTIN(__builtin_amdgcn_buffer_wbinvl1, "v", "n") BUILTIN(__builtin_amdgcn_fence, "vUicC*", "n") BUILTIN(__builtin_amdgcn_groupstaticsize, "Ui", "n") +BUILTIN(__builtin_amdgcn_wavefrontsize, "Ui", "nc") BUILTIN(__builtin_amdgcn_atomic_inc32, "UZiUZiD*UZiUicC*", "n") BUILTIN(__builtin_amdgcn_atomic_inc64, "UWiUWiD*UWiUicC*", "n") diff --git a/clang/include/clang/Basic/DiagnosticCommonKinds.td b/clang/include/clang/Basic/DiagnosticCommonKinds.td index b1bada65cb6b28cfca10f9c0d6b4276dbd657f5b..08bb1d81ba29f10c2361790a2f7efdd9055e3ca9 100644 --- a/clang/include/clang/Basic/DiagnosticCommonKinds.td +++ b/clang/include/clang/Basic/DiagnosticCommonKinds.td @@ -73,7 +73,7 @@ def warn_pragma_debug_unexpected_argument : Warning< def warn_fp_nan_inf_when_disabled : Warning< "use of %select{infinity|NaN}0%select{| via a macro}1 is undefined behavior " "due to the currently enabled floating-point options">, - InGroup>; + InGroup>; } // Parse && Sema diff --git a/clang/include/clang/Basic/DiagnosticDocs.td b/clang/include/clang/Basic/DiagnosticDocs.td index e9862422b4997ed8eaecc54bc4892b90b6dedf8f..8c024b5cad740a021dc795144387f618bb603cac 100644 --- a/clang/include/clang/Basic/DiagnosticDocs.td +++ b/clang/include/clang/Basic/DiagnosticDocs.td @@ -87,3 +87,12 @@ program by treating all string literals as having type ``const char *`` instead of ``char *``. This can cause unexpected behaviors with type-sensitive constructs like ``_Generic``. }]; + +defvar NanInfDisabledDocs = [{ +This warning is enabled when source code using the macros ``INFINITY`` or ``NAN`` +is compiled with floating-point options preventing these two values. This can +lead to undefined behavior. Check the order of command line arguments that modify +this behavior, such as ``-ffast-math``, ``-fhonor-infinities``, and +``-fhonor-nans`` (etc), as well as ``#pragma`` directives if this diagnostic is +generated unexpectedly. +}]; diff --git a/clang/include/clang/Basic/DiagnosticFrontendKinds.td b/clang/include/clang/Basic/DiagnosticFrontendKinds.td index 85ecfdf9de62d4403b730f6c5fb76303db89ad04..b1a282f5164a2a5578b2175a7b4b403d42d3ef4c 100644 --- a/clang/include/clang/Basic/DiagnosticFrontendKinds.td +++ b/clang/include/clang/Basic/DiagnosticFrontendKinds.td @@ -176,10 +176,10 @@ def err_verify_inconsistent_diags : Error< "'%0' diagnostics %select{expected|seen}1 but not %select{seen|expected}1: " "%2">; def err_verify_invalid_no_diags : Error< - "%select{expected|'expected-no-diagnostics'}0 directive cannot follow " - "%select{'expected-no-diagnostics' directive|other expected directives}0">; + "%select{expected|'%0-no-diagnostics'}1 directive cannot follow " + "%select{'%0-no-diagnostics' directive|other expected directives}1">; def err_verify_no_directives : Error< - "no expected directives found: consider use of 'expected-no-diagnostics'">; + "no expected directives found: consider use of '%0-no-diagnostics'">; def err_verify_nonconst_addrspace : Error< "qualifier 'const' is needed for variables in address space '%0'">; diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index f76e7a3392183ed6e9f88376bd26dae803491d59..b4dc4feee8e63afafb8877d79a62a642cc99820f 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -2982,6 +2982,9 @@ def err_trailing_requires_clause_on_deduction_guide : Error< "deduction guide cannot have a requires clause">; def err_constrained_non_templated_function : Error<"non-templated function cannot have a requires clause">; +def err_non_temp_spec_requires_clause : Error< + "%select{explicit|friend}0 specialization cannot have a trailing requires clause " + "unless it declares a function template">; def err_reference_to_function_with_unsatisfied_constraints : Error< "invalid reference to function %0: constraints not satisfied">; def err_requires_expr_local_parameter_default_argument : Error< diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 9cb7e0981384b0b12c00062efd81409d767cf2a0..f16de97f4e6bdafd7b5ec43b0719f1207c0558c7 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -1354,9 +1354,9 @@ let isScalarNarrowShift = 1 in { // Signed/Unsigned Saturating Rounded Shift Right Narrow (Immediate) def SCALAR_SQRSHRN_N: SInst<"vqrshrn_n", "(1<)1I", "SsSiSlSUsSUiSUl">; // Signed Saturating Shift Right Unsigned Narrow (Immediate) - def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "(1<)1I", "SsSiSl">; + def SCALAR_SQSHRUN_N: SInst<"vqshrun_n", "(1; // Signed Saturating Rounded Shift Right Unsigned Narrow (Immediate) - def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "(1<)1I", "SsSiSl">; + def SCALAR_SQRSHRUN_N: SInst<"vqrshrun_n", "(1; } //////////////////////////////////////////////////////////////////////////////// diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 695e1bddf9ffc6158703ea62c46adc959075b8f9..2da0e8d2aba9a475bdfa856e471ffaf377e39d02 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -44,6 +44,7 @@ defm SVLD1_ZA32 : ZALoad<"za32", "i", "aarch64_sme_ld1w", [ImmCheck<0, ImmCheck0 defm SVLD1_ZA64 : ZALoad<"za64", "l", "aarch64_sme_ld1d", [ImmCheck<0, ImmCheck0_7>]>; defm SVLD1_ZA128 : ZALoad<"za128", "q", "aarch64_sme_ld1q", [ImmCheck<0, ImmCheck0_15>]>; +let TargetGuard = "sme" in { def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr">; @@ -51,6 +52,7 @@ def SVLDR_VNUM_ZA : MInst<"svldr_vnum_za", "vmQl", "", def SVLDR_ZA : MInst<"svldr_za", "vmQ", "", [IsOverloadNone, IsStreamingCompatible, IsInOutZA], MemEltTyDefault, "aarch64_sme_ldr", []>; +} //////////////////////////////////////////////////////////////////////////////// // Stores @@ -81,6 +83,7 @@ defm SVST1_ZA32 : ZAStore<"za32", "i", "aarch64_sme_st1w", [ImmCheck<0, ImmCheck defm SVST1_ZA64 : ZAStore<"za64", "l", "aarch64_sme_st1d", [ImmCheck<0, ImmCheck0_7>]>; defm SVST1_ZA128 : ZAStore<"za128", "q", "aarch64_sme_st1q", [ImmCheck<0, ImmCheck0_15>]>; +let TargetGuard = "sme" in { def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str">; @@ -88,6 +91,7 @@ def SVSTR_VNUM_ZA : MInst<"svstr_vnum_za", "vm%l", "", def SVSTR_ZA : MInst<"svstr_za", "vm%", "", [IsOverloadNone, IsStreamingCompatible, IsInZA], MemEltTyDefault, "aarch64_sme_str", []>; +} //////////////////////////////////////////////////////////////////////////////// // Read horizontal/vertical ZA slices @@ -277,22 +281,22 @@ multiclass ZAAddSub { def NAME # _ZA32_VG1x2_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x2", "vm2", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x2", [IsStreaming, IsInOutZA], []>; def NAME # _ZA32_VG1X4_I32 : Inst<"sv" # n_suffix # "_za32[_{d}]_vg1x4", "vm4", "iUif", MergeNone, "aarch64_sme_" # n_suffix # "_za32_vg1x4", [IsStreaming, IsInOutZA], []>; + } - let TargetGuard = "sme-i16i64" in { - def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsInOutZA], []>; + let TargetGuard = "sme2,sme-i16i64" in { + def NAME # _WRITE_SINGLE_ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x2", "vm2d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_SINGLE_ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_write[_single]_za64[_{d}]_vg1x4", "vm4d", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_single_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_ZA64_VG1x2_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x2", "vm22", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _WRITE_ZA64_VG1x4_I64 : Inst<"sv" # n_suffix # "_write_za64[_{d}]_vg1x4", "vm44", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_write_za_vg1x4", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; - } + def NAME # _ZA64_VG1X2_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA64_VG1X4_I64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "lUl", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; + } - let TargetGuard = "sme-f64f64" in { - def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; - def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; - } + let TargetGuard = "sme2,sme-f64f64" in { + def NAME # _ZA64_VG1X2_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x2", "vm2", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x2", [IsStreaming, IsInOutZA], []>; + def NAME # _ZA64_VG1X4_F64 : Inst<"sv" # n_suffix # "_za64[_{d}]_vg1x4", "vm4", "d", MergeNone, "aarch64_sme_" # n_suffix # "_za64_vg1x4", [IsStreaming, IsInOutZA], []>; } } diff --git a/clang/include/clang/Format/Format.h b/clang/include/clang/Format/Format.h index 2ca80a7889f8cde5b6f7258e2a412b73f314bffa..cb14d98825400b392452d8b295ffdd5f3528a389 100644 --- a/clang/include/clang/Format/Format.h +++ b/clang/include/clang/Format/Format.h @@ -1031,6 +1031,16 @@ struct FormatStyle { /// Different ways to break after the template declaration. enum BreakTemplateDeclarationsStyle : int8_t { + /// Do not change the line breaking before the declaration. + /// \code + /// template + /// T foo() { + /// } + /// template T foo(int aaaaaaaaaaaaaaaaaaaaa, + /// int bbbbbbbbbbbbbbbbbbbbb) { + /// } + /// \endcode + BTDS_Leave, /// Do not force break before declaration. /// ``PenaltyBreakTemplateDeclaration`` is taken into account. /// \code @@ -4846,6 +4856,7 @@ struct FormatStyle { R.IncludeStyle.IncludeIsMainRegex && IncludeStyle.IncludeIsMainSourceRegex == R.IncludeStyle.IncludeIsMainSourceRegex && + IncludeStyle.MainIncludeChar == R.IncludeStyle.MainIncludeChar && IndentAccessModifiers == R.IndentAccessModifiers && IndentCaseBlocks == R.IndentCaseBlocks && IndentCaseLabels == R.IndentCaseLabels && diff --git a/clang/include/clang/Lex/Preprocessor.h b/clang/include/clang/Lex/Preprocessor.h index 9d0d53129a12dd92e3473409ca40169618302106..0836b7d439bb049054074c4cfa845d4e56bd085e 100644 --- a/clang/include/clang/Lex/Preprocessor.h +++ b/clang/include/clang/Lex/Preprocessor.h @@ -2838,7 +2838,8 @@ public: return AnnotationInfos.find(II)->second; } - void emitMacroExpansionWarnings(const Token &Identifier) const { + void emitMacroExpansionWarnings(const Token &Identifier, + bool IsIfnDef = false) const { IdentifierInfo *Info = Identifier.getIdentifierInfo(); if (Info->isDeprecatedMacro()) emitMacroDeprecationWarning(Identifier); @@ -2847,12 +2848,12 @@ public: !SourceMgr.isInMainFile(Identifier.getLocation())) emitRestrictExpansionWarning(Identifier); - if (Info->getName() == "INFINITY") - if (getLangOpts().NoHonorInfs) + if (!IsIfnDef) { + if (Info->getName() == "INFINITY" && getLangOpts().NoHonorInfs) emitRestrictInfNaNWarning(Identifier, 0); - if (Info->getName() == "NAN") - if (getLangOpts().NoHonorNaNs) + if (Info->getName() == "NAN" && getLangOpts().NoHonorNaNs) emitRestrictInfNaNWarning(Identifier, 1); + } } static void processPathForFileMacro(SmallVectorImpl &Path, diff --git a/clang/include/clang/Tooling/Inclusions/IncludeStyle.h b/clang/include/clang/Tooling/Inclusions/IncludeStyle.h index d6b2b0192477dca6cbb5bd2f96fc78f3c947cecb..c91e4a6b0ac54ac6ef003e1b5530383761237ad8 100644 --- a/clang/include/clang/Tooling/Inclusions/IncludeStyle.h +++ b/clang/include/clang/Tooling/Inclusions/IncludeStyle.h @@ -151,6 +151,21 @@ struct IncludeStyle { /// before any other include. /// \version 10 std::string IncludeIsMainSourceRegex; + + /// Character to consider in the include directives for the main header. + enum MainIncludeCharDiscriminator : int8_t { + /// Main include uses quotes: ``#include "foo.hpp"`` (the default). + MICD_Quote, + /// Main include uses angle brackets: ``#include ``. + MICD_AngleBracket, + /// Main include uses either quotes or angle brackets. + MICD_Any + }; + + /// When guessing whether a #include is the "main" include, only the include + /// directives that use the specified character are considered. + /// \version 18 + MainIncludeCharDiscriminator MainIncludeChar; }; } // namespace tooling @@ -174,6 +189,14 @@ struct ScalarEnumerationTraits< enumeration(IO &IO, clang::tooling::IncludeStyle::IncludeBlocksStyle &Value); }; +template <> +struct ScalarEnumerationTraits< + clang::tooling::IncludeStyle::MainIncludeCharDiscriminator> { + static void enumeration( + IO &IO, + clang::tooling::IncludeStyle::MainIncludeCharDiscriminator &Value); +}; + } // namespace yaml } // namespace llvm diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 63453890d98798a80b84146b4c345dfd6ab91cdb..089bc2094567f74252a81a1c571368458e9eb8d3 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -11427,6 +11427,10 @@ class FixedPointExprEvaluator return true; } + bool ZeroInitialization(const Expr *E) { + return Success(0, E); + } + //===--------------------------------------------------------------------===// // Visitor Methods //===--------------------------------------------------------------------===// diff --git a/clang/lib/AST/Interp/ByteCodeEmitter.cpp b/clang/lib/AST/Interp/ByteCodeEmitter.cpp index 409ce21506caae390bb9dd9aa074964058423a53..8bbfa928bd64573fc78c49baae47b7bfd40d2879 100644 --- a/clang/lib/AST/Interp/ByteCodeEmitter.cpp +++ b/clang/lib/AST/Interp/ByteCodeEmitter.cpp @@ -14,6 +14,7 @@ #include "Opcode.h" #include "Program.h" #include "clang/AST/ASTLambda.h" +#include "clang/AST/Attr.h" #include "clang/AST/DeclCXX.h" #include "clang/Basic/Builtins.h" #include @@ -116,7 +117,8 @@ Function *ByteCodeEmitter::compileFunc(const FunctionDecl *FuncDecl) { if (const auto *MD = dyn_cast(FuncDecl)) IsEligibleForCompilation = MD->isLambdaStaticInvoker(); if (!IsEligibleForCompilation) - IsEligibleForCompilation = FuncDecl->isConstexpr(); + IsEligibleForCompilation = + FuncDecl->isConstexpr() || FuncDecl->hasAttr(); // Compile the function body. if (!IsEligibleForCompilation || !visitFunc(FuncDecl)) { diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 10e32d9b7bcf38c41029ef42165005850c576423..59fddfc2da19577b99d2dd2dbae4d06c93f93a65 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -464,7 +464,7 @@ bool ByteCodeExprGen::VisitBinaryOperator(const BinaryOperator *BO) { // Special case for C++'s three-way/spaceship operator <=>, which // returns a std::{strong,weak,partial}_ordering (which is a class, so doesn't // have a PrimType). - if (!T) { + if (!T && Ctx.getLangOpts().CPlusPlus) { if (DiscardResult) return true; const ComparisonCategoryInfo *CmpInfo = @@ -820,6 +820,19 @@ bool ByteCodeExprGen::VisitImplicitValueInitExpr(const ImplicitValueIni return true; } + if (QT->isAnyComplexType()) { + assert(Initializing); + QualType ElemQT = QT->getAs()->getElementType(); + PrimType ElemT = classifyPrim(ElemQT); + for (unsigned I = 0; I < 2; ++I) { + if (!this->visitZeroInitializer(ElemT, ElemQT, E)) + return false; + if (!this->emitInitElem(ElemT, I, E)) + return false; + } + return true; + } + return false; } @@ -850,6 +863,10 @@ bool ByteCodeExprGen::visitInitList(ArrayRef Inits, assert(E->getType()->isRecordType()); const Record *R = getRecord(E->getType()); + if (Inits.size() == 1 && E->getType() == Inits[0]->getType()) { + return this->visitInitializer(Inits[0]); + } + unsigned InitIndex = 0; for (const Expr *Init : Inits) { if (!this->emitDupPtr(E)) @@ -1030,14 +1047,17 @@ bool ByteCodeExprGen::VisitSubstNonTypeTemplateParmExpr( template bool ByteCodeExprGen::VisitConstantExpr(const ConstantExpr *E) { - // Try to emit the APValue directly, without visiting the subexpr. - // This will only fail if we can't emit the APValue, so won't emit any - // diagnostics or any double values. std::optional T = classify(E->getType()); - if (T && E->hasAPValueResult() && - this->visitAPValue(E->getAPValueResult(), *T, E)) - return true; + if (T && E->hasAPValueResult()) { + // Try to emit the APValue directly, without visiting the subexpr. + // This will only fail if we can't emit the APValue, so won't emit any + // diagnostics or any double values. + if (DiscardResult) + return true; + if (this->visitAPValue(E->getAPValueResult(), *T, E)) + return true; + } return this->delegate(E->getSubExpr()); } @@ -1069,6 +1089,12 @@ bool ByteCodeExprGen::VisitUnaryExprOrTypeTraitExpr( if (Kind == UETT_SizeOf) { QualType ArgType = E->getTypeOfArgument(); + + // C++ [expr.sizeof]p2: "When applied to a reference or a reference type, + // the result is the size of the referenced type." + if (const auto *Ref = ArgType->getAs()) + ArgType = Ref->getPointeeType(); + CharUnits Size; if (ArgType->isVoidType() || ArgType->isFunctionType()) Size = CharUnits::One(); @@ -3006,21 +3032,53 @@ bool ByteCodeExprGen::VisitDeclRefExpr(const DeclRefExpr *E) { // pointer to the actual value) instead of a pointer to the pointer to the // value. bool IsReference = D->getType()->isReferenceType(); + // Complex values are copied in the AST via a simply assignment or + // ltor cast. But we represent them as two-element arrays, which means + // we pass them around as pointers. So, to assignm from them, we will + // have to copy both (primitive) elements instead. + bool IsComplex = D->getType()->isAnyComplexType(); // Check for local/global variables and parameters. if (auto It = Locals.find(D); It != Locals.end()) { const unsigned Offset = It->second.Offset; + // FIXME: Fix the code duplication here with the code in the global case. + if (Initializing && IsComplex) { + PrimType ElemT = classifyComplexElementType(D->getType()); + for (unsigned I = 0; I != 2; ++I) { + if (!this->emitGetPtrLocal(Offset, E)) + return false; + if (!this->emitArrayElemPop(ElemT, I, E)) + return false; + if (!this->emitInitElem(ElemT, I, E)) + return false; + } + return true; + } if (IsReference) return this->emitGetLocal(PT_Ptr, Offset, E); return this->emitGetPtrLocal(Offset, E); } else if (auto GlobalIndex = P.getGlobal(D)) { + if (Initializing && IsComplex) { + PrimType ElemT = classifyComplexElementType(D->getType()); + for (unsigned I = 0; I != 2; ++I) { + if (!this->emitGetPtrGlobal(*GlobalIndex, E)) + return false; + if (!this->emitArrayElemPop(ElemT, I, E)) + return false; + if (!this->emitInitElem(ElemT, I, E)) + return false; + } + return true; + } + if (IsReference) return this->emitGetGlobalPtr(*GlobalIndex, E); return this->emitGetPtrGlobal(*GlobalIndex, E); } else if (const auto *PVD = dyn_cast(D)) { if (auto It = this->Params.find(PVD); It != this->Params.end()) { + // FIXME: _Complex initializing case? if (IsReference || !It->second.IsPtr) return this->emitGetParamPtr(It->second.Offset, E); diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index a2d8c4e13010c6744e88a6d681c8e607330f7f8b..b0ec90a1f2851c49cc991858255c6b99e1d77e7f 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -317,7 +317,7 @@ bool ByteCodeStmtGen::visitCompoundStmt( template bool ByteCodeStmtGen::visitDeclStmt(const DeclStmt *DS) { for (auto *D : DS->decls()) { - if (isa(D)) + if (isa(D)) continue; const auto *VD = dyn_cast(D); diff --git a/clang/lib/AST/Interp/Descriptor.cpp b/clang/lib/AST/Interp/Descriptor.cpp index 5701cf0acf915dcd21ff8fcbe2b3785140fbe2de..f75a9fc4b466504b5d71363cf268169f95887222 100644 --- a/clang/lib/AST/Interp/Descriptor.cpp +++ b/clang/lib/AST/Interp/Descriptor.cpp @@ -63,6 +63,9 @@ static void dtorArrayTy(Block *, std::byte *Ptr, const Descriptor *D) { template static void moveArrayTy(Block *, const std::byte *Src, std::byte *Dst, const Descriptor *D) { + // FIXME: Need to copy the InitMap? + Src += sizeof(InitMapPtr); + Dst += sizeof(InitMapPtr); for (unsigned I = 0, NE = D->getNumElems(); I < NE; ++I) { const auto *SrcPtr = &reinterpret_cast(Src)[I]; auto *DstPtr = &reinterpret_cast(Dst)[I]; diff --git a/clang/lib/AST/Interp/Interp.cpp b/clang/lib/AST/Interp/Interp.cpp index 0766ad88e9224ec3b10e977a6345dcbe4ed4709c..683151f7caf5283828e13db9de6b4673a5b97cf6 100644 --- a/clang/lib/AST/Interp/Interp.cpp +++ b/clang/lib/AST/Interp/Interp.cpp @@ -272,7 +272,7 @@ static bool CheckConstant(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { } bool CheckDummy(InterpState &S, CodePtr OpPC, const Pointer &Ptr) { - return !Ptr.isZero() && !Ptr.isDummy(); + return !Ptr.isDummy(); } bool CheckNull(InterpState &S, CodePtr OpPC, const Pointer &Ptr, diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index e41604e125eba6e6e2bff1c2c9a6407b34e9c52b..a76e63395157f75c5f7d2766538df32d1be08853 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1855,13 +1855,38 @@ inline bool ArrayElemPtr(InterpState &S, CodePtr OpPC) { const T &Offset = S.Stk.pop(); const Pointer &Ptr = S.Stk.peek(); + if (!CheckDummy(S, OpPC, Ptr)) + return false; + + if (!OffsetHelper(S, OpPC, Offset, Ptr)) + return false; + + return NarrowPtr(S, OpPC); +} + +template ::T> +inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { + const T &Offset = S.Stk.pop(); + const Pointer &Ptr = S.Stk.pop(); + + if (!CheckDummy(S, OpPC, Ptr)) + return false; + if (!OffsetHelper(S, OpPC, Offset, Ptr)) return false; return NarrowPtr(S, OpPC); } -/// Just takes a pointer and checks if its' an incomplete +template ::T> +inline bool ArrayElemPop(InterpState &S, CodePtr OpPC, uint32_t Index) { + const Pointer &Ptr = S.Stk.pop(); + + S.Stk.push(Ptr.atIndex(Index).deref()); + return true; +} + +/// Just takes a pointer and checks if it's an incomplete /// array type. inline bool ArrayDecay(InterpState &S, CodePtr OpPC) { const Pointer &Ptr = S.Stk.pop(); @@ -1877,17 +1902,6 @@ inline bool ArrayDecay(InterpState &S, CodePtr OpPC) { return false; } -template ::T> -inline bool ArrayElemPtrPop(InterpState &S, CodePtr OpPC) { - const T &Offset = S.Stk.pop(); - const Pointer &Ptr = S.Stk.pop(); - - if (!OffsetHelper(S, OpPC, Offset, Ptr)) - return false; - - return NarrowPtr(S, OpPC); -} - inline bool Call(InterpState &S, CodePtr OpPC, const Function *Func) { if (Func->hasThisPointer()) { size_t ThisOffset = diff --git a/clang/lib/AST/Interp/InterpBuiltin.cpp b/clang/lib/AST/Interp/InterpBuiltin.cpp index 5976d4c3e7131d6eebe961060e137788900fd3fd..8f76b51ac033489bb128e1d50562a3da110b1f65 100644 --- a/clang/lib/AST/Interp/InterpBuiltin.cpp +++ b/clang/lib/AST/Interp/InterpBuiltin.cpp @@ -645,6 +645,19 @@ static bool interp__builtin_move(InterpState &S, CodePtr OpPC, return Func->getDecl()->isConstexpr(); } +static bool interp__builtin_eh_return_data_regno(InterpState &S, CodePtr OpPC, + const InterpFrame *Frame, + const Function *Func, + const CallExpr *Call) { + PrimType ArgT = *S.getContext().classify(Call->getArg(0)->getType()); + APSInt Arg = peekToAPSInt(S.Stk, ArgT); + + int Result = + S.getCtx().getTargetInfo().getEHDataRegisterNumber(Arg.getZExtValue()); + pushInt(S, Result); + return true; +} + bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F, const CallExpr *Call) { InterpFrame *Frame = S.Current; @@ -869,6 +882,11 @@ bool InterpretBuiltin(InterpState &S, CodePtr OpPC, const Function *F, return false; break; + case Builtin::BI__builtin_eh_return_data_regno: + if (!interp__builtin_eh_return_data_regno(S, OpPC, Frame, F, Call)) + return false; + break; + default: return false; } diff --git a/clang/lib/AST/Interp/Opcodes.td b/clang/lib/AST/Interp/Opcodes.td index e720b95498f17f15a95293589c28d1981a79ce4f..7f5bd7e5b44bca39e27ff48d24ace5147681b499 100644 --- a/clang/lib/AST/Interp/Opcodes.td +++ b/clang/lib/AST/Interp/Opcodes.td @@ -357,6 +357,12 @@ def ExpandPtr : Opcode; def ArrayElemPtr : AluOpcode; def ArrayElemPtrPop : AluOpcode; +def ArrayElemPop : Opcode { + let Args = [ArgUint32]; + let Types = [AllTypeClass]; + let HasGroup = 1; +} + //===----------------------------------------------------------------------===// // Direct field accessors //===----------------------------------------------------------------------===// diff --git a/clang/lib/AST/Interp/Pointer.h b/clang/lib/AST/Interp/Pointer.h index 53b89c51b5a81ae2a71c3f87d3fc6735f72b5b3b..fa2e03d71190f5565d7d68713beb83df0c9219ee 100644 --- a/clang/lib/AST/Interp/Pointer.h +++ b/clang/lib/AST/Interp/Pointer.h @@ -339,8 +339,12 @@ public: } /// Checks if a structure is a base class. bool isBaseClass() const { return isField() && getInlineDesc()->IsBase; } - /// Checks if the pointer pointers to a dummy value. - bool isDummy() const { return getDeclDesc()->isDummy(); } + /// Checks if the pointer points to a dummy value. + bool isDummy() const { + if (!Pointee) + return false; + return getDeclDesc()->isDummy(); + } /// Checks if an object or a subfield is mutable. bool isConst() const { diff --git a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp index 01db65866d1358790df4831906790611caf65ca8..24811ded970e81d332326e33bb1ab3cf5ebfed7d 100644 --- a/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp +++ b/clang/lib/Analysis/FlowSensitive/DataflowEnvironment.cpp @@ -86,15 +86,15 @@ static bool compareDistinctValues(QualType Type, Value &Val1, llvm_unreachable("All cases covered in switch"); } -/// Attempts to merge distinct values `Val1` and `Val2` in `Env1` and `Env2`, -/// respectively, of the same type `Type`. Merging generally produces a single +/// Attempts to join distinct values `Val1` and `Val2` in `Env1` and `Env2`, +/// respectively, of the same type `Type`. Joining generally produces a single /// value that (soundly) approximates the two inputs, although the actual /// meaning depends on `Model`. -static Value *mergeDistinctValues(QualType Type, Value &Val1, - const Environment &Env1, Value &Val2, - const Environment &Env2, - Environment &MergedEnv, - Environment::ValueModel &Model) { +static Value *joinDistinctValues(QualType Type, Value &Val1, + const Environment &Env1, Value &Val2, + const Environment &Env2, + Environment &JoinedEnv, + Environment::ValueModel &Model) { // Join distinct boolean values preserving information about the constraints // in the respective path conditions. if (isa(&Val1) && isa(&Val2)) { @@ -113,17 +113,17 @@ static Value *mergeDistinctValues(QualType Type, Value &Val1, // ``` auto &Expr1 = cast(Val1).formula(); auto &Expr2 = cast(Val2).formula(); - auto &A = MergedEnv.arena(); - auto &MergedVal = A.makeAtomRef(A.makeAtom()); - MergedEnv.assume( + auto &A = JoinedEnv.arena(); + auto &JoinedVal = A.makeAtomRef(A.makeAtom()); + JoinedEnv.assume( A.makeOr(A.makeAnd(A.makeAtomRef(Env1.getFlowConditionToken()), - A.makeEquals(MergedVal, Expr1)), + A.makeEquals(JoinedVal, Expr1)), A.makeAnd(A.makeAtomRef(Env2.getFlowConditionToken()), - A.makeEquals(MergedVal, Expr2)))); - return &A.makeBoolValue(MergedVal); + A.makeEquals(JoinedVal, Expr2)))); + return &A.makeBoolValue(JoinedVal); } - Value *MergedVal = nullptr; + Value *JoinedVal = nullptr; if (auto *RecordVal1 = dyn_cast(&Val1)) { auto *RecordVal2 = cast(&Val2); @@ -131,24 +131,21 @@ static Value *mergeDistinctValues(QualType Type, Value &Val1, // `RecordVal1` and `RecordVal2` may have different properties associated // with them. Create a new `RecordValue` with the same location but // without any properties so that we soundly approximate both values. If a - // particular analysis needs to merge properties, it should do so in - // `DataflowAnalysis::merge()`. - MergedVal = &MergedEnv.create(RecordVal1->getLoc()); + // particular analysis needs to join properties, it should do so in + // `DataflowAnalysis::join()`. + JoinedVal = &JoinedEnv.create(RecordVal1->getLoc()); else // If the locations for the two records are different, need to create a // completely new value. - MergedVal = MergedEnv.createValue(Type); + JoinedVal = JoinedEnv.createValue(Type); } else { - MergedVal = MergedEnv.createValue(Type); + JoinedVal = JoinedEnv.createValue(Type); } - // FIXME: Consider destroying `MergedValue` immediately if `ValueModel::merge` - // returns false to avoid storing unneeded values in `DACtx`. - if (MergedVal) - if (Model.merge(Type, Val1, Env1, Val2, Env2, *MergedVal, MergedEnv)) - return MergedVal; + if (JoinedVal) + Model.join(Type, Val1, Env1, Val2, Env2, *JoinedVal, JoinedEnv); - return nullptr; + return JoinedVal; } // When widening does not change `Current`, return value will equal `&Prev`. @@ -240,9 +237,9 @@ joinLocToVal(const llvm::MapVector &LocToVal, continue; } - if (Value *MergedVal = mergeDistinctValues( + if (Value *JoinedVal = joinDistinctValues( Loc->getType(), *Val, Env1, *It->second, Env2, JoinedEnv, Model)) { - Result.insert({Loc, MergedVal}); + Result.insert({Loc, JoinedVal}); } } @@ -657,10 +654,10 @@ Environment Environment::join(const Environment &EnvA, const Environment &EnvB, // cast. auto *Func = dyn_cast(EnvA.CallStack.back()); assert(Func != nullptr); - if (Value *MergedVal = - mergeDistinctValues(Func->getReturnType(), *EnvA.ReturnVal, EnvA, - *EnvB.ReturnVal, EnvB, JoinedEnv, Model)) - JoinedEnv.ReturnVal = MergedVal; + if (Value *JoinedVal = + joinDistinctValues(Func->getReturnType(), *EnvA.ReturnVal, EnvA, + *EnvB.ReturnVal, EnvB, JoinedEnv, Model)) + JoinedEnv.ReturnVal = JoinedVal; } if (EnvA.ReturnLoc == EnvB.ReturnLoc) diff --git a/clang/lib/Analysis/UnsafeBufferUsage.cpp b/clang/lib/Analysis/UnsafeBufferUsage.cpp index 823cd2a7b99691bbfeef8b13eab93735c14cf04e..a6dcf16b928e262a7d4d93cefe38d77dfc12450a 100644 --- a/clang/lib/Analysis/UnsafeBufferUsage.cpp +++ b/clang/lib/Analysis/UnsafeBufferUsage.cpp @@ -2870,19 +2870,6 @@ void clang::checkUnsafeBufferUsage(const Decl *D, #endif it = FixablesForAllVars.byVar.erase(it); } else if (Tracker.hasUnclaimedUses(it->first)) { -#ifndef NDEBUG - auto AllUnclaimed = Tracker.getUnclaimedUses(it->first); - for (auto UnclaimedDRE : AllUnclaimed) { - std::string UnclaimedUseTrace = - getDREAncestorString(UnclaimedDRE, D->getASTContext()); - - Handler.addDebugNoteForVar( - it->first, UnclaimedDRE->getBeginLoc(), - ("failed to produce fixit for '" + it->first->getNameAsString() + - "' : has an unclaimed use\nThe unclaimed DRE trace: " + - UnclaimedUseTrace)); - } -#endif it = FixablesForAllVars.byVar.erase(it); } else if (it->first->isInitCapture()) { #ifndef NDEBUG @@ -2892,10 +2879,30 @@ void clang::checkUnsafeBufferUsage(const Decl *D, "' : init capture")); #endif it = FixablesForAllVars.byVar.erase(it); - }else { - ++it; + } else { + ++it; + } + } + +#ifndef NDEBUG + for (const auto &it : UnsafeOps.byVar) { + const VarDecl *const UnsafeVD = it.first; + auto UnclaimedDREs = Tracker.getUnclaimedUses(UnsafeVD); + if (UnclaimedDREs.empty()) + continue; + const auto UnfixedVDName = UnsafeVD->getNameAsString(); + for (const clang::DeclRefExpr *UnclaimedDRE : UnclaimedDREs) { + std::string UnclaimedUseTrace = + getDREAncestorString(UnclaimedDRE, D->getASTContext()); + + Handler.addDebugNoteForVar( + UnsafeVD, UnclaimedDRE->getBeginLoc(), + ("failed to produce fixit for '" + UnfixedVDName + + "' : has an unclaimed use\nThe unclaimed DRE trace: " + + UnclaimedUseTrace)); } } +#endif // Fixpoint iteration for pointer assignments using DepMapTy = DenseMap>; diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 5502f685f64743bec654fc1b9f6593c7db7e542e..df8f71cf1d90086ec6509cab8c62fc21cedd8bb8 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -774,7 +774,7 @@ public: void EmitUndefinedBehaviorIntegerDivAndRemCheck(const BinOpInfo &Ops, llvm::Value *Zero,bool isDiv); // Common helper for getting how wide LHS of shift is. - static Value *GetWidthMinusOneValue(Value* LHS,Value* RHS); + static Value *GetMaximumShiftAmount(Value *LHS, Value *RHS); // Used for shifting constraints for OpenCL, do mask for powers of 2, URem for // non powers of two. @@ -4115,13 +4115,21 @@ Value *ScalarExprEmitter::EmitSub(const BinOpInfo &op) { return Builder.CreateExactSDiv(diffInChars, divisor, "sub.ptr.div"); } -Value *ScalarExprEmitter::GetWidthMinusOneValue(Value* LHS,Value* RHS) { +Value *ScalarExprEmitter::GetMaximumShiftAmount(Value *LHS, Value *RHS) { llvm::IntegerType *Ty; if (llvm::VectorType *VT = dyn_cast(LHS->getType())) Ty = cast(VT->getElementType()); else Ty = cast(LHS->getType()); - return llvm::ConstantInt::get(RHS->getType(), Ty->getBitWidth() - 1); + // For a given type of LHS the maximum shift amount is width(LHS)-1, however + // it can occur that width(LHS)-1 > range(RHS). Since there is no check for + // this in ConstantInt::get, this results in the value getting truncated. + // Constrain the return value to be max(RHS) in this case. + llvm::Type *RHSTy = RHS->getType(); + llvm::APInt RHSMax = llvm::APInt::getMaxValue(RHSTy->getScalarSizeInBits()); + if (RHSMax.ult(Ty->getBitWidth())) + return llvm::ConstantInt::get(RHSTy, RHSMax); + return llvm::ConstantInt::get(RHSTy, Ty->getBitWidth() - 1); } Value *ScalarExprEmitter::ConstrainShiftValue(Value *LHS, Value *RHS, @@ -4133,7 +4141,7 @@ Value *ScalarExprEmitter::ConstrainShiftValue(Value *LHS, Value *RHS, Ty = cast(LHS->getType()); if (llvm::isPowerOf2_64(Ty->getBitWidth())) - return Builder.CreateAnd(RHS, GetWidthMinusOneValue(LHS, RHS), Name); + return Builder.CreateAnd(RHS, GetMaximumShiftAmount(LHS, RHS), Name); return Builder.CreateURem( RHS, llvm::ConstantInt::get(RHS->getType(), Ty->getBitWidth()), Name); @@ -4166,7 +4174,7 @@ Value *ScalarExprEmitter::EmitShl(const BinOpInfo &Ops) { isa(Ops.LHS->getType())) { CodeGenFunction::SanitizerScope SanScope(&CGF); SmallVector, 2> Checks; - llvm::Value *WidthMinusOne = GetWidthMinusOneValue(Ops.LHS, Ops.RHS); + llvm::Value *WidthMinusOne = GetMaximumShiftAmount(Ops.LHS, Ops.RHS); llvm::Value *ValidExponent = Builder.CreateICmpULE(Ops.RHS, WidthMinusOne); if (SanitizeExponent) { @@ -4184,7 +4192,7 @@ Value *ScalarExprEmitter::EmitShl(const BinOpInfo &Ops) { Builder.CreateCondBr(ValidExponent, CheckShiftBase, Cont); llvm::Value *PromotedWidthMinusOne = (RHS == Ops.RHS) ? WidthMinusOne - : GetWidthMinusOneValue(Ops.LHS, RHS); + : GetMaximumShiftAmount(Ops.LHS, RHS); CGF.EmitBlock(CheckShiftBase); llvm::Value *BitsShiftedOff = Builder.CreateLShr( Ops.LHS, Builder.CreateSub(PromotedWidthMinusOne, RHS, "shl.zeros", @@ -4235,7 +4243,7 @@ Value *ScalarExprEmitter::EmitShr(const BinOpInfo &Ops) { isa(Ops.LHS->getType())) { CodeGenFunction::SanitizerScope SanScope(&CGF); llvm::Value *Valid = - Builder.CreateICmpULE(RHS, GetWidthMinusOneValue(Ops.LHS, RHS)); + Builder.CreateICmpULE(Ops.RHS, GetMaximumShiftAmount(Ops.LHS, Ops.RHS)); EmitBinOpCheck(std::make_pair(Valid, SanitizerKind::ShiftExponent), Ops); } diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 29db9543f3655321c3122be63db324d8a074eb8d..00e14071a4afeccb857c226ca8d54cfef1e744a5 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -1443,16 +1443,18 @@ Compilation *Driver::BuildCompilation(ArrayRef ArgList) { const ToolChain &TC = getToolChain( *UArgs, computeTargetTriple(*this, TargetTriple, *UArgs)); - // Check if the environment version is valid. + // Check if the environment version is valid except wasm case. llvm::Triple Triple = TC.getTriple(); - StringRef TripleVersionName = Triple.getEnvironmentVersionString(); - StringRef TripleObjectFormat = - Triple.getObjectFormatTypeName(Triple.getObjectFormat()); - if (Triple.getEnvironmentVersion().empty() && TripleVersionName != "" && - TripleVersionName != TripleObjectFormat) { - Diags.Report(diag::err_drv_triple_version_invalid) - << TripleVersionName << TC.getTripleString(); - ContainsError = true; + if (!Triple.isWasm()) { + StringRef TripleVersionName = Triple.getEnvironmentVersionString(); + StringRef TripleObjectFormat = + Triple.getObjectFormatTypeName(Triple.getObjectFormat()); + if (Triple.getEnvironmentVersion().empty() && TripleVersionName != "" && + TripleVersionName != TripleObjectFormat) { + Diags.Report(diag::err_drv_triple_version_invalid) + << TripleVersionName << TC.getTripleString(); + ContainsError = true; + } } // Report warning when arm64EC option is overridden by specified target diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 13bf242115437207c8ab01cb2c73f102aa48d99f..942ebbc410607804bbae79fe2b993c1890c36828 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -5972,6 +5972,14 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, << A->getAsString(Args) << A->getValue(); else A->render(Args, CmdArgs); + } else if (Triple.isAArch64() && Triple.isOSBinFormatELF()) { + // "all" is not supported on AArch64 since branch relaxation creates new + // basic blocks for some cross-section branches. + if (Val != "labels" && Val != "none" && !Val.starts_with("list=")) + D.Diag(diag::err_drv_invalid_value) + << A->getAsString(Args) << A->getValue(); + else + A->render(Args, CmdArgs); } else if (Triple.isNVPTX()) { // Do not pass the option to the GPU compilation. We still want it enabled // for the host-side compilation, so seeing it here is not an error. diff --git a/clang/lib/Format/BreakableToken.cpp b/clang/lib/Format/BreakableToken.cpp index 473908e8fee3b3da6557e77d3c2dc6be8931e209..75304908dc65066b2017327f71544f99350819bf 100644 --- a/clang/lib/Format/BreakableToken.cpp +++ b/clang/lib/Format/BreakableToken.cpp @@ -449,11 +449,11 @@ const FormatToken &BreakableComment::tokenAt(unsigned LineIndex) const { static bool mayReflowContent(StringRef Content) { Content = Content.trim(Blanks); - // Lines starting with '@' commonly have special meaning. + // Lines starting with '@' or '\' commonly have special meaning. // Lines starting with '-', '-#', '+' or '*' are bulleted/numbered lists. bool hasSpecialMeaningPrefix = false; for (StringRef Prefix : - {"@", "TODO", "FIXME", "XXX", "-# ", "- ", "+ ", "* "}) { + {"@", "\\", "TODO", "FIXME", "XXX", "-# ", "- ", "+ ", "* "}) { if (Content.starts_with(Prefix)) { hasSpecialMeaningPrefix = true; break; diff --git a/clang/lib/Format/ContinuationIndenter.cpp b/clang/lib/Format/ContinuationIndenter.cpp index a3aca4a725311edac503d71d9eec9069db5caacd..7fd04b23abdca6c16e4df21f648a4f510fb217c5 100644 --- a/clang/lib/Format/ContinuationIndenter.cpp +++ b/clang/lib/Format/ContinuationIndenter.cpp @@ -569,7 +569,10 @@ bool ContinuationIndenter::mustBreak(const LineState &State) { return true; } } - return Style.AlwaysBreakTemplateDeclarations != FormatStyle::BTDS_No; + return Style.AlwaysBreakTemplateDeclarations != FormatStyle::BTDS_No && + (Style.AlwaysBreakTemplateDeclarations != + FormatStyle::BTDS_Leave || + Current.NewlinesBefore > 0); } if (Previous.is(TT_FunctionAnnotationRParen) && State.Line->Type != LT_PreprocessorDirective) { @@ -1702,8 +1705,11 @@ void ContinuationIndenter::moveStatePastFakeLParens(LineState &State, // Special case for generic selection expressions, its comma-separated // expressions are not aligned to the opening paren like regular calls, but // rather continuation-indented relative to the _Generic keyword. - if (Previous && Previous->endsSequence(tok::l_paren, tok::kw__Generic)) - NewParenState.Indent = CurrentState.LastSpace; + if (Previous && Previous->endsSequence(tok::l_paren, tok::kw__Generic) && + State.Stack.size() > 1) { + NewParenState.Indent = State.Stack[State.Stack.size() - 2].Indent + + Style.ContinuationIndentWidth; + } if ((shouldUnindentNextOperator(Current) || (Previous && diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 01d6e9aca0d2985f24ae72c82cde3357c931e893..c5714af155f0b5135851365252c7732b3eb2c7ad 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -296,6 +296,7 @@ template <> struct ScalarEnumerationTraits { static void enumeration(IO &IO, FormatStyle::BreakTemplateDeclarationsStyle &Value) { + IO.enumCase(Value, "Leave", FormatStyle::BTDS_Leave); IO.enumCase(Value, "No", FormatStyle::BTDS_No); IO.enumCase(Value, "MultiLine", FormatStyle::BTDS_MultiLine); IO.enumCase(Value, "Yes", FormatStyle::BTDS_Yes); @@ -1018,6 +1019,7 @@ template <> struct MappingTraits { IO.mapOptional("MacroBlockBegin", Style.MacroBlockBegin); IO.mapOptional("MacroBlockEnd", Style.MacroBlockEnd); IO.mapOptional("Macros", Style.Macros); + IO.mapOptional("MainIncludeChar", Style.IncludeStyle.MainIncludeChar); IO.mapOptional("MaxEmptyLinesToKeep", Style.MaxEmptyLinesToKeep); IO.mapOptional("NamespaceIndentation", Style.NamespaceIndentation); IO.mapOptional("NamespaceMacros", Style.NamespaceMacros); @@ -1496,6 +1498,7 @@ FormatStyle getLLVMStyle(FormatStyle::LanguageKind Language) { {".*", 1, 0, false}}; LLVMStyle.IncludeStyle.IncludeIsMainRegex = "(Test)?$"; LLVMStyle.IncludeStyle.IncludeBlocks = tooling::IncludeStyle::IBS_Preserve; + LLVMStyle.IncludeStyle.MainIncludeChar = tooling::IncludeStyle::MICD_Quote; LLVMStyle.IndentAccessModifiers = false; LLVMStyle.IndentCaseLabels = false; LLVMStyle.IndentCaseBlocks = false; diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 7a62f5fd3dfbb31f046975a51a3d82c321e2a98a..cec56fad5315659858ace032bddf4ff1ab128449 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -5184,7 +5184,9 @@ bool TokenAnnotator::mustBreakBefore(const AnnotatedLine &Line, // concept ... if (Right.is(tok::kw_concept)) return Style.BreakBeforeConceptDeclarations == FormatStyle::BBCDS_Always; - return Style.AlwaysBreakTemplateDeclarations == FormatStyle::BTDS_Yes; + return Style.AlwaysBreakTemplateDeclarations == FormatStyle::BTDS_Yes || + (Style.AlwaysBreakTemplateDeclarations == FormatStyle::BTDS_Leave && + Right.NewlinesBefore > 0); } if (Left.ClosesRequiresClause && Right.isNot(tok::semi)) { switch (Style.RequiresClausePosition) { @@ -5617,7 +5619,11 @@ bool TokenAnnotator::canBreakBefore(const AnnotatedLine &Line, return Style.BreakBeforeConceptDeclarations != FormatStyle::BBCDS_Never; if (Right.is(TT_RequiresClause)) return true; - if (Left.ClosesTemplateDeclaration || Left.is(TT_FunctionAnnotationRParen)) + if (Left.ClosesTemplateDeclaration) { + return Style.AlwaysBreakTemplateDeclarations != FormatStyle::BTDS_Leave || + Right.NewlinesBefore > 0; + } + if (Left.is(TT_FunctionAnnotationRParen)) return true; if (Left.ClosesRequiresClause) return true; diff --git a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp index 304935a0a90b8e97282602d2ebcdb89344d62699..48330e936171810549597fac1f2122c4f1508787 100644 --- a/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp +++ b/clang/lib/Frontend/VerifyDiagnosticConsumer.cpp @@ -396,6 +396,12 @@ public: } }; +static std::string DetailedErrorString(const DiagnosticsEngine &Diags) { + if (Diags.getDiagnosticOptions().VerifyPrefixes.empty()) + return "expected"; + return *Diags.getDiagnosticOptions().VerifyPrefixes.begin(); +} + /// ParseDirective - Go through the comment and see if it indicates expected /// diagnostics. If so, then put them in the appropriate directive list. /// @@ -478,14 +484,14 @@ static bool ParseDirective(StringRef S, ExpectedData *ED, SourceManager &SM, if (NoDiag) { if (Status == VerifyDiagnosticConsumer::HasOtherExpectedDirectives) Diags.Report(Pos, diag::err_verify_invalid_no_diags) - << /*IsExpectedNoDiagnostics=*/true; + << DetailedErrorString(Diags) << /*IsExpectedNoDiagnostics=*/true; else Status = VerifyDiagnosticConsumer::HasExpectedNoDiagnostics; continue; } if (Status == VerifyDiagnosticConsumer::HasExpectedNoDiagnostics) { Diags.Report(Pos, diag::err_verify_invalid_no_diags) - << /*IsExpectedNoDiagnostics=*/false; + << DetailedErrorString(Diags) << /*IsExpectedNoDiagnostics=*/false; continue; } Status = VerifyDiagnosticConsumer::HasOtherExpectedDirectives; @@ -1104,7 +1110,8 @@ void VerifyDiagnosticConsumer::CheckDiagnostics() { // Produce an error if no expected-* directives could be found in the // source file(s) processed. if (Status == HasNoDirectives) { - Diags.Report(diag::err_verify_no_directives).setForceEmit(); + Diags.Report(diag::err_verify_no_directives).setForceEmit() + << DetailedErrorString(Diags); ++NumErrors; Status = HasNoDirectivesReported; } diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h index 1ad6853a97c9d2a0f8f20fe5cf2f7c1f0ebc9c02..c968d37fb8cd64a80096b9fb8f1372277f847e0a 100644 --- a/clang/lib/Headers/cpuid.h +++ b/clang/lib/Headers/cpuid.h @@ -200,6 +200,9 @@ #define bit_AMXINT8 0x02000000 /* Features in %eax for leaf 7 sub-leaf 1 */ +#define bit_SHA512 0x00000001 +#define bit_SM3 0x00000002 +#define bit_SM4 0x00000004 #define bit_RAOINT 0x00000008 #define bit_AVXVNNI 0x00000010 #define bit_AVX512BF16 0x00000020 @@ -211,7 +214,11 @@ /* Features in %edx for leaf 7 sub-leaf 1 */ #define bit_AVXVNNIINT8 0x00000010 #define bit_AVXNECONVERT 0x00000020 +#define bit_AMXCOMPLEX 0x00000100 +#define bit_AVXVNNIINT16 0x00000400 #define bit_PREFETCHI 0x00004000 +#define bit_USERMSR 0x00008000 +#define bit_AVX10 0x00080000 /* Features in %eax for leaf 13 sub-leaf 1 */ #define bit_XSAVEOPT 0x00000001 @@ -244,6 +251,9 @@ #define bit_RDPRU 0x00000010 #define bit_WBNOINVD 0x00000200 +/* Features in %ebx for leaf 0x24 */ +#define bit_AVX10_256 0x00020000 +#define bit_AVX10_512 0x00040000 #if __i386__ #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ diff --git a/clang/lib/Lex/PPDirectives.cpp b/clang/lib/Lex/PPDirectives.cpp index 9f82a6d073e3bac8f763330599d4d1235072b45c..a980f4bcbae1245f4197994b4f8152f330e77080 100644 --- a/clang/lib/Lex/PPDirectives.cpp +++ b/clang/lib/Lex/PPDirectives.cpp @@ -3288,7 +3288,7 @@ void Preprocessor::HandleIfdefDirective(Token &Result, return; } - emitMacroExpansionWarnings(MacroNameTok); + emitMacroExpansionWarnings(MacroNameTok, /*IsIfnDef=*/true); // Check to see if this is the last token on the #if[n]def line. CheckEndOfDirective(isIfndef ? "ifndef" : "ifdef"); diff --git a/clang/lib/Lex/PPExpressions.cpp b/clang/lib/Lex/PPExpressions.cpp index 1feb0eb18d71e6eaa18c0acd6ba596c526b39d15..8f25c67ec9dfbe40d1e73c9ac2efff1fb2b5d846 100644 --- a/clang/lib/Lex/PPExpressions.cpp +++ b/clang/lib/Lex/PPExpressions.cpp @@ -133,7 +133,9 @@ static bool EvaluateDefined(PPValue &Result, Token &PeekTok, DefinedTracker &DT, Result.Val.setIsUnsigned(false); // Result is signed intmax_t. DT.IncludedUndefinedIds = !Macro; - PP.emitMacroExpansionWarnings(PeekTok); + PP.emitMacroExpansionWarnings( + PeekTok, + (II->getName() == "INFINITY" || II->getName() == "NAN") ? true : false); // If there is a macro, mark it used. if (Result.Val != 0 && ValueLive) diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 481d952d2389bbeedd18f7dc68935eebb1f16bba..18a5d93ab8e8c639f8988032733892749faaf483 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -10440,6 +10440,60 @@ Sema::ActOnFunctionDeclarator(Scope *S, Declarator &D, DeclContext *DC, diag::ext_operator_new_delete_declared_inline) << NewFD->getDeclName(); + if (Expr *TRC = NewFD->getTrailingRequiresClause()) { + // C++20 [dcl.decl.general]p4: + // The optional requires-clause in an init-declarator or + // member-declarator shall be present only if the declarator declares a + // templated function. + // + // C++20 [temp.pre]p8: + // An entity is templated if it is + // - a template, + // - an entity defined or created in a templated entity, + // - a member of a templated entity, + // - an enumerator for an enumeration that is a templated entity, or + // - the closure type of a lambda-expression appearing in the + // declaration of a templated entity. + // + // [Note 6: A local class, a local or block variable, or a friend + // function defined in a templated entity is a templated entity. + // — end note] + // + // A templated function is a function template or a function that is + // templated. A templated class is a class template or a class that is + // templated. A templated variable is a variable template or a variable + // that is templated. + if (!FunctionTemplate) { + if (isFunctionTemplateSpecialization || isMemberSpecialization) { + // C++ [temp.expl.spec]p8 (proposed resolution for CWG2847): + // An explicit specialization shall not have a trailing + // requires-clause unless it declares a function template. + // + // Since a friend function template specialization cannot be + // definition, and since a non-template friend declaration with a + // trailing requires-clause must be a definition, we diagnose + // friend function template specializations with trailing + // requires-clauses on the same path as explicit specializations + // even though they aren't necessarily prohibited by the same + // language rule. + Diag(TRC->getBeginLoc(), diag::err_non_temp_spec_requires_clause) + << isFriend; + } else if (isFriend && NewFD->isTemplated() && + !D.isFunctionDefinition()) { + // C++ [temp.friend]p9: + // A non-template friend declaration with a requires-clause shall be + // a definition. + Diag(NewFD->getBeginLoc(), + diag::err_non_temp_friend_decl_with_requires_clause_must_be_def); + NewFD->setInvalidDecl(); + } else if (!NewFD->isTemplated() || + !(isa(NewFD) || D.isFunctionDefinition())) { + Diag(TRC->getBeginLoc(), + diag::err_constrained_non_templated_function); + } + } + } + // We do not add HD attributes to specializations here because // they may have different constexpr-ness compared to their // templates and, after maybeAddCUDAHostDeviceAttrs() is applied, @@ -12063,55 +12117,6 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, checkThisInStaticMemberFunctionType(Method); } - if (Expr *TRC = NewFD->getTrailingRequiresClause()) { - // C++20: dcl.decl.general p4: - // The optional requires-clause ([temp.pre]) in an init-declarator or - // member-declarator shall be present only if the declarator declares a - // templated function ([dcl.fct]). - // - // [temp.pre]/8: - // An entity is templated if it is - // - a template, - // - an entity defined ([basic.def]) or created ([class.temporary]) in a - // templated entity, - // - a member of a templated entity, - // - an enumerator for an enumeration that is a templated entity, or - // - the closure type of a lambda-expression ([expr.prim.lambda.closure]) - // appearing in the declaration of a templated entity. [Note 6: A local - // class, a local or block variable, or a friend function defined in a - // templated entity is a templated entity. — end note] - // - // A templated function is a function template or a function that is - // templated. A templated class is a class template or a class that is - // templated. A templated variable is a variable template or a variable - // that is templated. - - bool IsTemplate = NewFD->getDescribedFunctionTemplate(); - bool IsFriend = NewFD->getFriendObjectKind(); - if (!IsTemplate && // -a template - // defined... in a templated entity - !(DeclIsDefn && NewFD->isTemplated()) && - // a member of a templated entity - !(isa(NewFD) && NewFD->isTemplated()) && - // Don't complain about instantiations, they've already had these - // rules + others enforced. - !NewFD->isTemplateInstantiation() && - // If the function violates [temp.friend]p9 because it is missing - // a definition, and adding a definition would make it templated, - // then let that error take precedence. - !(!DeclIsDefn && IsFriend && NewFD->isTemplated())) { - Diag(TRC->getBeginLoc(), diag::err_constrained_non_templated_function); - } else if (!DeclIsDefn && !IsTemplate && IsFriend && - !NewFD->isTemplateInstantiation()) { - // C++ [temp.friend]p9: - // A non-template friend declaration with a requires-clause shall be a - // definition. - Diag(NewFD->getBeginLoc(), - diag::err_non_temp_friend_decl_with_requires_clause_must_be_def); - NewFD->setInvalidDecl(); - } - } - if (CXXConversionDecl *Conversion = dyn_cast(NewFD)) ActOnConversionDeclarator(Conversion); diff --git a/clang/lib/Sema/SemaExpr.cpp b/clang/lib/Sema/SemaExpr.cpp index d15278bce5a6ba9ef91f53519a3d6a8da5926cba..4049ab3bf6cafb67d4075e15a635cdc249626fac 100644 --- a/clang/lib/Sema/SemaExpr.cpp +++ b/clang/lib/Sema/SemaExpr.cpp @@ -14073,7 +14073,7 @@ inline QualType Sema::CheckLogicalOperands(ExprResult &LHS, ExprResult &RHS, Expr::EvalResult EVResult; if (RHS.get()->EvaluateAsInt(EVResult, Context)) { llvm::APSInt Result = EVResult.Val.getInt(); - if ((getLangOpts().Bool && !RHS.get()->getType()->isBooleanType() && + if ((getLangOpts().CPlusPlus && !RHS.get()->getType()->isBooleanType() && !RHS.get()->getExprLoc().isMacroID()) || (Result != 0 && Result != 1)) { Diag(Loc, diag::warn_logical_instead_of_bitwise) diff --git a/clang/lib/Sema/SemaOpenMP.cpp b/clang/lib/Sema/SemaOpenMP.cpp index 1556f6e8546135cfbe3a102efa1ac1f1e1127128..7f75cfc5b54f3532968cd7c38411708fa7499f70 100644 --- a/clang/lib/Sema/SemaOpenMP.cpp +++ b/clang/lib/Sema/SemaOpenMP.cpp @@ -21124,6 +21124,8 @@ Sema::ActOnOpenMPDependClause(const OMPDependClause::DependDataTy &Data, ExprTy = ATy->getElementType(); else ExprTy = BaseType->getPointeeType(); + if (BaseType.isNull() || ExprTy.isNull()) + return nullptr; ExprTy = ExprTy.getNonReferenceType(); const Expr *Length = OASE->getLength(); Expr::EvalResult Result; diff --git a/clang/lib/Sema/SemaOverload.cpp b/clang/lib/Sema/SemaOverload.cpp index 6a04d68b4f04140b718599405f88c9877fb21bfd..42960c229077c3e1dd674b901d2cd1493a3b1c13 100644 --- a/clang/lib/Sema/SemaOverload.cpp +++ b/clang/lib/Sema/SemaOverload.cpp @@ -2177,7 +2177,10 @@ static bool IsStandardConversion(Sema &S, Expr* From, QualType ToType, From->isIntegerConstantExpr(S.getASTContext())) { SCS.Second = ICK_Compatible_Conversion; FromType = ToType; - } else if (ToType->isFixedPointType() || FromType->isFixedPointType()) { + } else if ((ToType->isFixedPointType() && + FromType->isConvertibleToFixedPointType()) || + (FromType->isFixedPointType() && + ToType->isConvertibleToFixedPointType())) { SCS.Second = ICK_Fixed_Point_Conversion; FromType = ToType; } else { @@ -7719,8 +7722,8 @@ bool Sema::CheckNonDependentConversions( unsigned Offset = Method && Method->hasCXXExplicitFunctionObjectParameter() ? 1 : 0; - for (unsigned I = 0, N = std::min(ParamTypes.size(), Args.size()); I != N; - ++I) { + for (unsigned I = 0, N = std::min(ParamTypes.size() - Offset, Args.size()); + I != N; ++I) { QualType ParamType = ParamTypes[I + Offset]; if (!ParamType->isDependentType()) { unsigned ConvIdx; diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index e5999fa50117ec8813709725538283701c1aec4f..6d59180bc446d21e004de01e9a6d0965602e20cf 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -241,10 +241,38 @@ Response HandleFunctionTemplateDecl(const FunctionTemplateDecl *FTD, while (const Type *Ty = NNS ? NNS->getAsType() : nullptr) { if (NNS->isInstantiationDependent()) { - if (const auto *TSTy = Ty->getAs()) + if (const auto *TSTy = Ty->getAs()) { + ArrayRef Arguments = TSTy->template_arguments(); + // Prefer template arguments from the injected-class-type if possible. + // For example, + // ```cpp + // template struct S { + // template void foo(); + // }; + // template template + // ^^^^^^^^^^^^^ InjectedTemplateArgs + // They're of kind TemplateArgument::Pack, not of + // TemplateArgument::Type. + // void S::foo() {} + // ^^^^^^^ + // TSTy->template_arguments() (which are of PackExpansionType) + // ``` + // This meets the contract in + // TreeTransform::TryExpandParameterPacks that the template arguments + // for unexpanded parameters should be of a Pack kind. + if (TSTy->isCurrentInstantiation()) { + auto *RD = TSTy->getCanonicalTypeInternal()->getAsCXXRecordDecl(); + if (ClassTemplateDecl *CTD = RD->getDescribedClassTemplate()) + Arguments = CTD->getInjectedTemplateArgs(); + else if (auto *Specialization = + dyn_cast(RD)) + Arguments = + Specialization->getTemplateInstantiationArgs().asArray(); + } Result.addOuterTemplateArguments( - const_cast(FTD), TSTy->template_arguments(), + const_cast(FTD), Arguments, /*Final=*/false); + } } NNS = NNS->getPrefix(); diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp index 64028b2770215082bccff1dd75964c74c47a8eb6..4526fac64735bfb282213d3333273ee412d619f0 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/ASTUtils.cpp @@ -34,13 +34,16 @@ tryToFindPtrOrigin(const Expr *E, bool StopAtFirstRefCountedObj) { } if (auto *call = dyn_cast(E)) { if (auto *memberCall = dyn_cast(call)) { - std::optional IsGetterOfRefCt = isGetterOfRefCounted(memberCall->getMethodDecl()); - if (IsGetterOfRefCt && *IsGetterOfRefCt) { - E = memberCall->getImplicitObjectArgument(); - if (StopAtFirstRefCountedObj) { - return {E, true}; + if (auto *decl = memberCall->getMethodDecl()) { + std::optional IsGetterOfRefCt = + isGetterOfRefCounted(memberCall->getMethodDecl()); + if (IsGetterOfRefCt && *IsGetterOfRefCt) { + E = memberCall->getImplicitObjectArgument(); + if (StopAtFirstRefCountedObj) { + return {E, true}; + } + continue; } - continue; } } diff --git a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp index d275222ac6b5874bf2db91eb4f93244154b11274..4313da66efc0b7d13f2ed1f9f142d455fe3272cf 100644 --- a/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp +++ b/clang/lib/Tooling/Inclusions/HeaderIncludes.cpp @@ -234,8 +234,18 @@ int IncludeCategoryManager::getSortIncludePriority(StringRef IncludeName, return Ret; } bool IncludeCategoryManager::isMainHeader(StringRef IncludeName) const { - if (!IncludeName.starts_with("\"")) - return false; + switch (Style.MainIncludeChar) { + case IncludeStyle::MICD_Quote: + if (!IncludeName.starts_with("\"")) + return false; + break; + case IncludeStyle::MICD_AngleBracket: + if (!IncludeName.starts_with("<")) + return false; + break; + case IncludeStyle::MICD_Any: + break; + } IncludeName = IncludeName.drop_front(1).drop_back(1); // remove the surrounding "" or <> diff --git a/clang/lib/Tooling/Inclusions/IncludeStyle.cpp b/clang/lib/Tooling/Inclusions/IncludeStyle.cpp index da5bb00d1013a6344e001e22f75e965b0ce66147..05dfb50589de0c2f78d797ea734b5cb03aa916c9 100644 --- a/clang/lib/Tooling/Inclusions/IncludeStyle.cpp +++ b/clang/lib/Tooling/Inclusions/IncludeStyle.cpp @@ -28,5 +28,12 @@ void ScalarEnumerationTraits::enumeration( IO.enumCase(Value, "Regroup", IncludeStyle::IBS_Regroup); } +void ScalarEnumerationTraits:: + enumeration(IO &IO, IncludeStyle::MainIncludeCharDiscriminator &Value) { + IO.enumCase(Value, "Quote", IncludeStyle::MICD_Quote); + IO.enumCase(Value, "AngleBracket", IncludeStyle::MICD_AngleBracket); + IO.enumCase(Value, "Any", IncludeStyle::MICD_Any); +} + } // namespace yaml } // namespace llvm diff --git a/clang/test/AST/Interp/builtin-functions.cpp b/clang/test/AST/Interp/builtin-functions.cpp index ce7c8bd357908b2b0862cccdf77bc279526a8359..d6ed2d862b0949637dbbf99421d2ca943f459353 100644 --- a/clang/test/AST/Interp/builtin-functions.cpp +++ b/clang/test/AST/Interp/builtin-functions.cpp @@ -363,3 +363,16 @@ namespace ffs { char ffs6[__builtin_ffsl(0x10L) == 5 ? 1 : -1]; char ffs7[__builtin_ffsll(0x100LL) == 9 ? 1 : -1]; } + +namespace EhReturnDataRegno { + void test11(int X) { + switch (X) { + case __builtin_eh_return_data_regno(0): // constant foldable. + break; + } + + __builtin_eh_return_data_regno(X); // expected-error {{argument to '__builtin_eh_return_data_regno' must be a constant integer}} \ + // ref-error {{argument to '__builtin_eh_return_data_regno' must be a constant integer}} + + } +} diff --git a/clang/test/AST/Interp/complex.cpp b/clang/test/AST/Interp/complex.cpp index 7f02bfa18bbdb0eff5ba0ff62e146f028988097b..7d625ab1f378ecfc9100f6ff261d4c6689260b83 100644 --- a/clang/test/AST/Interp/complex.cpp +++ b/clang/test/AST/Interp/complex.cpp @@ -102,6 +102,16 @@ static_assert(__imag(I3) == 0, ""); // constexpr _Complex _BitInt(8) A = 0;// = {4}; +constexpr _Complex double Doubles[4] = {{1.0, 2.0}}; +static_assert(__real(Doubles[0]) == 1.0, ""); +static_assert(__imag(Doubles[0]) == 2.0, ""); +static_assert(__real(Doubles[1]) == 0.0, ""); +static_assert(__imag(Doubles[1]) == 0.0, ""); +static_assert(__real(Doubles[2]) == 0.0, ""); +static_assert(__imag(Doubles[2]) == 0.0, ""); +static_assert(__real(Doubles[3]) == 0.0, ""); +static_assert(__imag(Doubles[3]) == 0.0, ""); + void func(void) { __complex__ int arr; _Complex int result; @@ -194,3 +204,21 @@ namespace ZeroInit { constexpr int ignored = (fcomplex(), 0); } + +namespace DeclRefCopy { + constexpr _Complex int ComplexInt = 42 + 24i; + + constexpr _Complex int B = ComplexInt; + constexpr _Complex int ArrayOfComplexInt[4] = {ComplexInt, ComplexInt, ComplexInt, ComplexInt}; + static_assert(__real(ArrayOfComplexInt[0]) == 42, ""); + static_assert(__imag(ArrayOfComplexInt[0]) == 24, ""); + static_assert(__real(ArrayOfComplexInt[3]) == 42, ""); + static_assert(__imag(ArrayOfComplexInt[3]) == 24, ""); + + constexpr int localComplexArray() { + _Complex int A = 42 + 24i; + _Complex int ArrayOfComplexInt[4] = {A, A, A, A}; + return __real(ArrayOfComplexInt[0]) + __imag(ArrayOfComplexInt[3]); + } + static_assert(localComplexArray() == (24 + 42), ""); +} diff --git a/clang/test/AST/Interp/cxx20.cpp b/clang/test/AST/Interp/cxx20.cpp index 50a7c02925878d5d6954a49678b9c0e1de1f88a8..0af553a77892e6fe740bb019989af164acf2a6ca 100644 --- a/clang/test/AST/Interp/cxx20.cpp +++ b/clang/test/AST/Interp/cxx20.cpp @@ -752,3 +752,16 @@ namespace TryCatch { } static_assert(foo() == 11); } + +namespace IgnoredConstantExpr { + consteval int immediate() { return 0;} + struct ReferenceToNestedMembers { + int m; + int a = ((void)immediate(), m); + int b = ((void)immediate(), this->m); + }; + struct ReferenceToNestedMembersTest { + void* m = nullptr; + ReferenceToNestedMembers j{0}; + } test_reference_to_nested_members; +} diff --git a/clang/test/AST/Interp/literals.cpp b/clang/test/AST/Interp/literals.cpp index 0031e577580aaa096c3867bbd20b13312e463af7..f5b5f77ffc624bb259e13ae0e6ae1a8320be5757 100644 --- a/clang/test/AST/Interp/literals.cpp +++ b/clang/test/AST/Interp/literals.cpp @@ -1,7 +1,7 @@ -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++11 -verify %s -// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++20 -verify %s -// RUN: %clang_cc1 -std=c++11 -fms-extensions -Wno-vla -verify=ref %s -// RUN: %clang_cc1 -std=c++20 -fms-extensions -Wno-vla -verify=ref %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++11 -verify=expected,both %s +// RUN: %clang_cc1 -fexperimental-new-constant-interpreter -Wno-vla -fms-extensions -std=c++20 -verify=expected,both %s +// RUN: %clang_cc1 -std=c++11 -fms-extensions -Wno-vla -verify=ref,both %s +// RUN: %clang_cc1 -std=c++20 -fms-extensions -Wno-vla -verify=ref,both %s #define INT_MIN (~__INT_MAX__) #define INT_MAX __INT_MAX__ @@ -11,21 +11,19 @@ typedef __PTRDIFF_TYPE__ ptrdiff_t; static_assert(true, ""); -static_assert(false, ""); // expected-error{{failed}} ref-error{{failed}} +static_assert(false, ""); // both-error{{failed}} static_assert(nullptr == nullptr, ""); static_assert(__null == __null, ""); static_assert(1 == 1, ""); -static_assert(1 == 3, ""); // expected-error{{failed}} ref-error{{failed}} +static_assert(1 == 3, ""); // both-error{{failed}} constexpr void* v = nullptr; static_assert(__null == v, ""); constexpr int number = 10; static_assert(number == 10, ""); -static_assert(number != 10, ""); // expected-error{{failed}} \ - // ref-error{{failed}} \ - // expected-note{{evaluates to}} \ - // ref-note{{evaluates to}} +static_assert(number != 10, ""); // both-error{{failed}} \ + // both-note{{evaluates to}} static_assert(__objc_yes, ""); static_assert(!__objc_no, ""); @@ -38,22 +36,14 @@ static_assert(one == 1, ""); constexpr bool b2 = bool(); static_assert(!b2, ""); -constexpr int Failed1 = 1 / 0; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{division by zero}} \ - // expected-note {{declared here}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{division by zero}} \ - // ref-note {{declared here}} -constexpr int Failed2 = Failed1 + 1; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{declared here}} \ - // expected-note {{initializer of 'Failed1' is not a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{declared here}} \ - // ref-note {{initializer of 'Failed1' is not a constant expression}} -static_assert(Failed2 == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{initializer of 'Failed2' is not a constant expression}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{initializer of 'Failed2' is not a constant expression}} +constexpr int Failed1 = 1 / 0; // both-error {{must be initialized by a constant expression}} \ + // both-note {{division by zero}} \ + // both-note {{declared here}} +constexpr int Failed2 = Failed1 + 1; // both-error {{must be initialized by a constant expression}} \ + // both-note {{declared here}} \ + // both-note {{initializer of 'Failed1' is not a constant expression}} +static_assert(Failed2 == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{initializer of 'Failed2' is not a constant expression}} namespace ScalarTypes { constexpr int ScalarInitInt = int(); @@ -112,10 +102,8 @@ namespace IntegralCasts { static_assert(!nu, ""); }; -constexpr int UninitI; // expected-error {{must be initialized by a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} -constexpr int *UninitPtr; // expected-error {{must be initialized by a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} +constexpr int UninitI; // both-error {{must be initialized by a constant expression}} +constexpr int *UninitPtr; // both-error {{must be initialized by a constant expression}} constexpr bool getTrue() { return true; } constexpr bool getFalse() { return false; } @@ -134,7 +122,7 @@ static_assert(false == 0, ""); static_assert(!5 == false, ""); static_assert(!0, ""); static_assert(-true, ""); -static_assert(-false, ""); //expected-error{{failed}} ref-error{{failed}} +static_assert(-false, ""); //both-error{{failed}} static_assert(~0 == -1, ""); static_assert(~1 == -2, ""); @@ -143,10 +131,8 @@ static_assert(~255 == -256, ""); static_assert(~INT_MIN == INT_MAX, ""); static_assert(~INT_MAX == INT_MIN, ""); -static_assert(-(1 << 31), ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{outside the range of representable values}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{outside the range of representable values}} \ +static_assert(-(1 << 31), ""); // both-error {{not an integral constant expression}} \ + // both-note {{outside the range of representable values}} namespace PrimitiveEmptyInitList { constexpr int a = {}; @@ -199,10 +185,8 @@ namespace PointerComparison { constexpr void *pv = (void*)&s.a; constexpr void *qv = (void*)&s.b; constexpr bool v1 = null < (int*)0; - constexpr bool v2 = null < pv; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{comparison between 'nullptr' and '&s.a' has unspecified value}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{comparison between 'nullptr' and '&s.a' has unspecified value}} \ + constexpr bool v2 = null < pv; // both-error {{must be initialized by a constant expression}} \ + // both-note {{comparison between 'nullptr' and '&s.a' has unspecified value}} constexpr bool v3 = null == pv; // ok constexpr bool v4 = qv == pv; // ok @@ -213,10 +197,8 @@ namespace PointerComparison { // ref-note {{unequal pointers to void}} constexpr bool v8 = qv > (void*)&s.a; // ref-error {{constant expression}} \ // ref-note {{unequal pointers to void}} - constexpr bool v6 = qv > null; // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{comparison between '&s.b' and 'nullptr' has unspecified value}} \ - // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{comparison between '&s.b' and 'nullptr' has unspecified value}} + constexpr bool v6 = qv > null; // both-error {{must be initialized by a constant expression}} \ + // both-note {{comparison between '&s.b' and 'nullptr' has unspecified value}} constexpr bool v7 = qv <= (void*)&s.b; // ok @@ -229,13 +211,13 @@ namespace PointerComparison { constexpr long m3 = (&m3 + 1) - (&m3); static_assert(m3 == 1, ""); - constexpr long m4 = &m4 + 2 - &m4; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{cannot refer to element 2 of non-array object}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{cannot refer to element 2 of non-array object}} + constexpr long m4 = &m4 + 2 - &m4; // both-error {{must be initialized by a constant expression}} \ + // both-note {{cannot refer to element 2 of non-array object}} } namespace SizeOf { + static_assert(alignof(char&) == 1, ""); + constexpr int soint = sizeof(int); constexpr int souint = sizeof(unsigned int); static_assert(soint == souint, ""); @@ -257,11 +239,9 @@ namespace SizeOf { static_assert(sizeof(bool) == 1, ""); static_assert(sizeof(char) == 1, ""); - constexpr int F = sizeof(void); // expected-error{{incomplete type 'void'}} \ - // ref-error{{incomplete type 'void'}} + constexpr int F = sizeof(void); // both-error{{incomplete type 'void'}} - constexpr int F2 = sizeof(gimme); // expected-error{{to a function type}} \ - // ref-error{{to a function type}} + constexpr int F2 = sizeof(gimme); // both-error{{to a function type}} struct S { @@ -273,22 +253,19 @@ namespace SizeOf { void func() { int n = 12; - constexpr int oofda = sizeof(int[n++]); // expected-error {{must be initialized by a constant expression}} \ - // ref-error {{must be initialized by a constant expression}} + constexpr int oofda = sizeof(int[n++]); // both-error {{must be initialized by a constant expression}} } #if __cplusplus >= 201402L constexpr int IgnoredRejected() { // ref-error {{never produces a constant expression}} int n = 0; - sizeof(int[n++]); // expected-warning {{expression result unused}} \ - // ref-warning {{expression result unused}} \ + sizeof(int[n++]); // both-warning {{expression result unused}} \ // ref-note 2{{subexpression not valid in a constant expression}} return n; } /// FIXME: This is rejected because the parameter so sizeof() is not constant. /// produce a proper diagnostic. - static_assert(IgnoredRejected() == 0, ""); // expected-error {{not an integral constant expression}} \ - // ref-error {{not an integral constant expression}} \ + static_assert(IgnoredRejected() == 0, ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'IgnoredRejected()'}} #endif @@ -317,32 +294,22 @@ namespace rem { static_assert(-3 % -4 == -3, ""); constexpr int zero() { return 0; } - static_assert(10 % zero() == 20, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{division by zero}} - + static_assert(10 % zero() == 20, ""); // both-error {{not an integral constant expression}} \ + // both-note {{division by zero}} static_assert(true % true == 0, ""); static_assert(false % true == 0, ""); - static_assert(true % false == 10, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{division by zero}} - constexpr int x = INT_MIN % - 1; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{value 2147483648 is outside the range}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{value 2147483648 is outside the range}} \ - + static_assert(true % false == 10, ""); // both-error {{not an integral constant expression}} \ + // both-note {{division by zero}} + constexpr int x = INT_MIN % - 1; // both-error {{must be initialized by a constant expression}} \ + // both-note {{value 2147483648 is outside the range}} }; namespace div { constexpr int zero() { return 0; } static_assert(12 / 3 == 4, ""); - static_assert(12 / zero() == 12, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{division by zero}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{division by zero}} + static_assert(12 / zero() == 12, ""); // both-error {{not an integral constant expression}} \ + // both-note {{division by zero}} static_assert(12 / -3 == -4, ""); static_assert(-12 / 3 == -4, ""); @@ -351,11 +318,8 @@ namespace div { constexpr long unsigned RHS = 3; static_assert(LHS / RHS == 4, ""); - constexpr int x = INT_MIN / - 1; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{value 2147483648 is outside the range}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{value 2147483648 is outside the range}} \ - + constexpr int x = INT_MIN / - 1; // both-error {{must be initialized by a constant expression}} \ + // both-note {{value 2147483648 is outside the range}} }; namespace cond { @@ -446,8 +410,7 @@ namespace bitXor { #if __cplusplus >= 201402L constexpr bool IgnoredUnary() { bool bo = true; - !bo; // expected-warning {{expression result unused}} \ - // ref-warning {{expression result unused}} + !bo; // both-warning {{expression result unused}} return bo; } static_assert(IgnoredUnary(), ""); @@ -482,15 +445,11 @@ namespace strings { #pragma clang diagnostic ignored "-Wmultichar" constexpr int mc = 'abc'; static_assert(mc == 'abc', ""); - __WCHAR_TYPE__ wm = L'abc'; // ref-error{{wide character literals may not contain multiple characters}} \ - // expected-error{{wide character literals may not contain multiple characters}} - __WCHAR_TYPE__ wu = u'abc'; // ref-error{{Unicode character literals may not contain multiple characters}} \ - // expected-error{{Unicode character literals may not contain multiple characters}} - __WCHAR_TYPE__ wU = U'abc'; // ref-error{{Unicode character literals may not contain multiple characters}} \ - // expected-error{{Unicode character literals may not contain multiple characters}} + __WCHAR_TYPE__ wm = L'abc'; // both-error{{wide character literals may not contain multiple characters}} + __WCHAR_TYPE__ wu = u'abc'; // both-error{{Unicode character literals may not contain multiple characters}} + __WCHAR_TYPE__ wU = U'abc'; // both-error{{Unicode character literals may not contain multiple characters}} #if __cplusplus > 201103L - __WCHAR_TYPE__ wu8 = u8'abc'; // ref-error{{Unicode character literals may not contain multiple characters}} \ - // expected-error{{Unicode character literals may not contain multiple characters}} + __WCHAR_TYPE__ wu8 = u8'abc'; // both-error{{Unicode character literals may not contain multiple characters}} #endif #pragma clang diagnostic pop @@ -507,26 +466,19 @@ namespace strings { static_assert(foo2[3] == '\0', ""); static_assert(foo2[6] == 'f', ""); static_assert(foo2[7] == '\0', ""); - static_assert(foo2[8] == '\0', ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{read of dereferenced one-past-the-end pointer}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{read of dereferenced one-past-the-end pointer}} + static_assert(foo2[8] == '\0', ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of dereferenced one-past-the-end pointer}} constexpr char foo3[4] = "abc"; static_assert(foo3[3] == '\0', ""); - static_assert(foo3[4] == '\0', ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{read of dereferenced one-past-the-end pointer}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{read of dereferenced one-past-the-end pointer}} + static_assert(foo3[4] == '\0', ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of dereferenced one-past-the-end pointer}} - constexpr char foo4[2] = "abcd"; // expected-error {{initializer-string for char array is too long}} \ - // ref-error {{initializer-string for char array is too long}} + constexpr char foo4[2] = "abcd"; // both-error {{initializer-string for char array is too long}} static_assert(foo4[0] == 'a', ""); static_assert(foo4[1] == 'b', ""); - static_assert(foo4[2] == '\0', ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{read of dereferenced one-past-the-end pointer}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{read of dereferenced one-past-the-end pointer}} + static_assert(foo4[2] == '\0', ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of dereferenced one-past-the-end pointer}} constexpr char foo5[12] = "abc\xff"; #if defined(__CHAR_UNSIGNED__) || __CHAR_BIT__ > 8 @@ -574,16 +526,13 @@ namespace IncDec { constexpr int three() { int a = 0; - return ++a + ++a; // expected-warning {{multiple unsequenced modifications to 'a'}} \ - // ref-warning {{multiple unsequenced modifications to 'a'}} \ - + return ++a + ++a; // both-warning {{multiple unsequenced modifications to 'a'}} } static_assert(three() == 3, ""); constexpr bool incBool() { bool b = false; - return ++b; // expected-error {{ISO C++17 does not allow incrementing expression of type bool}} \ - // ref-error {{ISO C++17 does not allow incrementing expression of type bool}} + return ++b; // both-error {{ISO C++17 does not allow incrementing expression of type bool}} } static_assert(incBool(), ""); @@ -611,73 +560,54 @@ namespace IncDec { } return 1; } - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - static_assert(uninit(), ""); // ref-error {{not an integral constant expression}} \ + static_assert(uninit(), ""); // both-error {{not an integral constant expression}} \ // ref-note {{in call to 'uninit()'}} \ - // expected-error {{not an integral constant expression}} \ // expected-note {{in call to 'uninit()'}} - constexpr int OverFlow() { // ref-error {{never produces a constant expression}} \ - // expected-error {{never produces a constant expression}} + constexpr int OverFlow() { // both-error {{never produces a constant expression}} int a = INT_MAX; - ++a; // ref-note 2{{is outside the range}} \ - // expected-note 2{{is outside the range}} + ++a; // both-note 2{{is outside the range}} return -1; } - static_assert(OverFlow() == -1, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'OverFlow()'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'OverFlow()'}} - + static_assert(OverFlow() == -1, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'OverFlow()'}} - constexpr int UnderFlow() { // ref-error {{never produces a constant expression}} \ - // expected-error {{never produces a constant expression}} + constexpr int UnderFlow() { // both-error {{never produces a constant expression}} int a = INT_MIN; - --a; // ref-note 2{{is outside the range}} \ - // expected-note 2{{is outside the range}} + --a; // both-note 2{{is outside the range}} return -1; } - static_assert(UnderFlow() == -1, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'UnderFlow()'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'UnderFlow()'}} + static_assert(UnderFlow() == -1, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'UnderFlow()'}} constexpr int getTwo() { int i = 1; @@ -691,26 +621,20 @@ namespace IncDec { static_assert(sub(7) == 5, ""); constexpr int add(int a, int b) { - a += b; // expected-note {{is outside the range of representable values}} \ - // ref-note {{is outside the range of representable values}} + a += b; // both-note {{is outside the range of representable values}} return a; } static_assert(add(1, 2) == 3, ""); - static_assert(add(INT_MAX, 1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'add}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'add}} + static_assert(add(INT_MAX, 1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'add}} constexpr int sub(int a, int b) { - a -= b; // expected-note {{is outside the range of representable values}} \ - // ref-note {{is outside the range of representable values}} + a -= b; // both-note {{is outside the range of representable values}} return a; } static_assert(sub(10, 20) == -10, ""); - static_assert(sub(INT_MIN, 1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'sub}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'sub}} + static_assert(sub(INT_MIN, 1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'sub}} constexpr int subAll(int a) { return (a -= a); @@ -792,26 +716,18 @@ namespace IncDec { constexpr int IntRem(int a, int b) { int r; r = a; - r %= b; // expected-note {{division by zero}} \ - // ref-note {{division by zero}} \ - // expected-note {{outside the range of representable values}} \ - // ref-note {{outside the range of representable values}} + r %= b; // both-note {{division by zero}} \ + // both-note {{outside the range of representable values}} return r; } static_assert(IntRem(2, 2) == 0, ""); static_assert(IntRem(2, 1) == 0, ""); static_assert(IntRem(9, 7) == 2, ""); - static_assert(IntRem(5, 0) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntRem(5, 0)'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntRem(5, 0)'}} - - static_assert(IntRem(INT_MIN, -1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntRem}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntRem}} - + static_assert(IntRem(5, 0) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntRem(5, 0)'}} + static_assert(IntRem(INT_MIN, -1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntRem}} constexpr bool BoolDiv(bool b1, bool b2) { bool a; @@ -825,25 +741,19 @@ namespace IncDec { constexpr int IntDiv(int a, int b) { int r; r = a; - r /= b; // expected-note {{division by zero}} \ - // ref-note {{division by zero}} \ - // expected-note {{outside the range of representable values}} \ - // ref-note {{outside the range of representable values}} + r /= b; // both-note {{division by zero}} \ + // both-note {{outside the range of representable values}} return r; } static_assert(IntDiv(2, 2) == 1, ""); static_assert(IntDiv(12, 20) == 0, ""); static_assert(IntDiv(2, 1) == 2, ""); static_assert(IntDiv(9, 7) == 1, ""); - static_assert(IntDiv(5, 0) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntDiv(5, 0)'}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntDiv(5, 0)'}} + static_assert(IntDiv(5, 0) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntDiv(5, 0)'}} - static_assert(IntDiv(INT_MIN, -1) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntDiv}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntDiv}} + static_assert(IntDiv(INT_MIN, -1) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntDiv}} constexpr bool BoolMul(bool b1, bool b2) { bool a; @@ -859,18 +769,15 @@ namespace IncDec { constexpr int IntMul(int a, int b) { int r; r = a; - r *= b; // expected-note {{is outside the range of representable values of type 'int'}} \ - // ref-note {{is outside the range of representable values of type 'int'}} + r *= b; // both-note {{is outside the range of representable values of type 'int'}} return r; } static_assert(IntMul(2, 2) == 4, ""); static_assert(IntMul(12, 20) == 240, ""); static_assert(IntMul(2, 1) == 2, ""); static_assert(IntMul(9, 7) == 63, ""); - static_assert(IntMul(INT_MAX, 2) == 0, ""); // expected-error {{not an integral constant expression}} \ - // expected-note {{in call to 'IntMul}} \ - // ref-error {{not an integral constant expression}} \ - // ref-note {{in call to 'IntMul}} + static_assert(IntMul(INT_MAX, 2) == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{in call to 'IntMul}} constexpr int arr[] = {1,2,3}; constexpr int ptrInc1() { const int *p = arr; @@ -885,11 +792,9 @@ namespace IncDec { } static_assert(ptrInc2() == 2, ""); - constexpr int ptrInc3() { // expected-error {{never produces a constant expression}} \ - // ref-error {{never produces a constant expression}} + constexpr int ptrInc3() { // both-error {{never produces a constant expression}} const int *p = arr; - p += 12; // expected-note {{cannot refer to element 12 of array of 3 elements}} \ - // ref-note {{cannot refer to element 12 of array of 3 elements}} + p += 12; // both-note {{cannot refer to element 12 of array of 3 elements}} return *p; } @@ -901,11 +806,9 @@ namespace IncDec { } static_assert(ptrIncDec1() == 2, ""); - constexpr int ptrDec1() { // expected-error {{never produces a constant expression}} \ - // ref-error {{never produces a constant expression}} + constexpr int ptrDec1() { // both-error {{never produces a constant expression}} const int *p = arr; - p -= 1; // expected-note {{cannot refer to element -1 of array of 3 elements}} \ - // ref-note {{cannot refer to element -1 of array of 3 elements}} + p -= 1; // both-note {{cannot refer to element -1 of array of 3 elements}} return *p; } @@ -1133,10 +1036,8 @@ namespace PredefinedExprs { } constexpr char heh(unsigned index) { - __FUNCTION__; // ref-warning {{result unused}} \ - // expected-warning {{result unused}} - __extension__ __FUNCTION__; // ref-warning {{result unused}} \ - // expected-warning {{result unused}} + __FUNCTION__; // both-warning {{result unused}} + __extension__ __FUNCTION__; // both-warning {{result unused}} return __FUNCTION__[index]; } static_assert(heh(0) == 'h', ""); @@ -1158,8 +1059,7 @@ namespace NE { #if __cplusplus > 201402L constexpr int a() { int b = 0; - (void)noexcept(++b); // expected-warning {{expression with side effects has no effect in an unevaluated context}} \ - // ref-warning {{expression with side effects has no effect in an unevaluated context}} + (void)noexcept(++b); // both-warning {{expression with side effects has no effect in an unevaluated context}} return b; } @@ -1170,60 +1070,38 @@ namespace NE { namespace PointerCasts { constexpr int M = 10; constexpr const int *P = &M; - constexpr intptr_t A = (intptr_t)P; // ref-error {{must be initialized by a constant expression}} \ - // ref-note {{cast that performs the conversions of a reinterpret_cast}} \ - // expected-error {{must be initialized by a constant expression}} \ - // expected-note {{cast that performs the conversions of a reinterpret_cast}} + constexpr intptr_t A = (intptr_t)P; // both-error {{must be initialized by a constant expression}} \ + // both-note {{cast that performs the conversions of a reinterpret_cast}} - int array[(intptr_t)(char*)0]; // ref-warning {{variable length array folded to constant array}} \ - // expected-warning {{variable length array folded to constant array}} + int array[(intptr_t)(char*)0]; // both-warning {{variable length array folded to constant array}} } namespace InvalidDeclRefs { - bool b00; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b00, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-const variable}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-const variable}} - - float b01; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b01, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-constexpr variable}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-constexpr variable}} - - extern const int b02; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b02, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{initializer of 'b02' is unknown}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{initializer of 'b02' is unknown}} - - int b03 = 3; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(b03, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-const variable}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-const variable}} + bool b00; // both-note {{declared here}} + static_assert(b00, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-const variable}} + + float b01; // both-note {{declared here}} + static_assert(b01, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-constexpr variable}} + + extern const int b02; // both-note {{declared here}} + static_assert(b02, ""); // both-error {{not an integral constant expression}} \ + // both-note {{initializer of 'b02' is unknown}} + + int b03 = 3; // both-note {{declared here}} + static_assert(b03, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-const variable}} } namespace NonConstReads { - void *p = nullptr; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(!p, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-constexpr variable 'p'}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-constexpr variable 'p'}} - - int arr[!p]; // ref-error {{variable length array}} \ - // expected-error {{variable length array}} - - int z; // ref-note {{declared here}} \ - // expected-note {{declared here}} - static_assert(z == 0, ""); // ref-error {{not an integral constant expression}} \ - // ref-note {{read of non-const variable 'z'}} \ - // expected-error {{not an integral constant expression}} \ - // expected-note {{read of non-const variable 'z'}} + void *p = nullptr; // both-note {{declared here}} + static_assert(!p, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-constexpr variable 'p'}} + + int arr[!p]; // both-error {{variable length array}} + + int z; // both-note {{declared here}} + static_assert(z == 0, ""); // both-error {{not an integral constant expression}} \ + // both-note {{read of non-const variable 'z'}} } diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index c6aac7938a297174037b2101d1859286e91a2352..5ce1e6e09a0b74d82043f17877f91e1290837c33 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -7,6 +7,10 @@ // RUN: %clang_cc1 -verify=ref -std=c++20 %s // RUN: %clang_cc1 -verify=ref -triple i686 %s +/// Used to crash. +struct Empty {}; +constexpr Empty e = {Empty()}; + struct BoolPair { bool first; bool second; diff --git a/clang/test/AST/Interp/switch.cpp b/clang/test/AST/Interp/switch.cpp index 79b630f8007489a4ce801d8f231d0ccfeec470f0..8136f92f5dfd3f1799b70b8ed1506e94b90d9378 100644 --- a/clang/test/AST/Interp/switch.cpp +++ b/clang/test/AST/Interp/switch.cpp @@ -1,5 +1,5 @@ -// RUN: %clang_cc1 -std=c++17 -fexperimental-new-constant-interpreter -verify %s -// RUN: %clang_cc1 -std=c++17 -verify=ref %s +// RUN: %clang_cc1 -std=c++17 -fexperimental-new-constant-interpreter -verify=expected,both %s +// RUN: %clang_cc1 -std=c++17 -verify=ref,both %s constexpr bool isEven(int a) { bool v = false; @@ -75,20 +75,14 @@ constexpr int test(int val) { } static_assert(test(1) == 100, ""); -constexpr int bad(int val) { return val / 0; } // expected-warning {{division by zero}} \ - // ref-warning {{division by zero}} -constexpr int another_test(int val) { // expected-note {{declared here}} \ - // ref-note {{declared here}} +constexpr int bad(int val) { return val / 0; } // both-warning {{division by zero}} +constexpr int another_test(int val) { // both-note {{declared here}} switch (val) { - case bad(val): return 100; // expected-error {{case value is not a constant expression}} \ - // expected-note {{cannot be used in a constant expression}} \ - // ref-error {{case value is not a constant expression}} \ - // ref-note {{cannot be used in a constant expression}} + case bad(val): return 100; // both-error {{case value is not a constant expression}} \ + // both-note {{cannot be used in a constant expression}} default: return -1; } return 0; } -static_assert(another_test(1) == 100, ""); // expected-error {{static assertion failed}} \ - // expected-note {{evaluates to}} \ - // ref-error {{static assertion failed}} \ - // ref-note {{evaluates to}} +static_assert(another_test(1) == 100, ""); // both-error {{static assertion failed}} \ + // both-note {{evaluates to}} diff --git a/clang/test/AST/fixed-point-zero-init.cpp b/clang/test/AST/fixed-point-zero-init.cpp new file mode 100644 index 0000000000000000000000000000000000000000..abe8aa8c396a858f5f1df4d01d7ef41aecc9ae41 --- /dev/null +++ b/clang/test/AST/fixed-point-zero-init.cpp @@ -0,0 +1,5 @@ +// RUN: %clang_cc1 -ffixed-point %s -verify +// expected-no-diagnostics + +constexpr _Accum a[2] = {}; +static_assert(a[0] == 0 && a[0] != 1); diff --git a/clang/test/AST/ms-constexpr.cpp b/clang/test/AST/ms-constexpr.cpp index e85af8494f3344a0ac42641ede76f1cd28551bb1..673af1234f4430766b25ad917d45e5cba0d39f84 100644 --- a/clang/test/AST/ms-constexpr.cpp +++ b/clang/test/AST/ms-constexpr.cpp @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -ast-dump -verify %s | FileCheck %s +// RUN: %clang_cc1 -fms-compatibility -fms-compatibility-version=19.33 -std=c++20 -ast-dump -verify %s -fexperimental-new-constant-interpreter | FileCheck %s // expected-no-diagnostics // CHECK: used f1 'bool ()' diff --git a/clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp b/clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp new file mode 100644 index 0000000000000000000000000000000000000000..16d3b89b3ac4e74562ce81800c8de1eeaa4185f1 --- /dev/null +++ b/clang/test/Analysis/Checkers/WebKit/member-function-pointer-crash.cpp @@ -0,0 +1,26 @@ +// RUN: %clang_analyze_cc1 -analyzer-checker=alpha.webkit.UncountedLocalVarsChecker -verify %s + +#include "mock-types.h" + +class RenderStyle; + +class FillLayer { +public: + void ref() const; + void deref() const; +}; + +class FillLayersPropertyWrapper { +public: + typedef const FillLayer& (RenderStyle::*LayersGetter)() const; + +private: + bool canInterpolate(const RenderStyle& from) const + { + auto* fromLayer = &(from.*m_layersGetter)(); + // expected-warning@-1{{Local variable 'fromLayer' is uncounted and unsafe}} + return true; + } + + LayersGetter m_layersGetter; +}; diff --git a/clang/test/CXX/drs/dr28xx.cpp b/clang/test/CXX/drs/dr28xx.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7f72003d66f1e3353bf5d6d9cbff00af884f9e0b --- /dev/null +++ b/clang/test/CXX/drs/dr28xx.cpp @@ -0,0 +1,60 @@ +// RUN: %clang_cc1 -std=c++98 -verify=expected %s +// RUN: %clang_cc1 -std=c++11 -verify=expected %s +// RUN: %clang_cc1 -std=c++14 -verify=expected %s +// RUN: %clang_cc1 -std=c++17 -verify=expected %s +// RUN: %clang_cc1 -std=c++20 -verify=expected,since-cxx20 %s +// RUN: %clang_cc1 -std=c++23 -verify=expected,since-cxx20,since-cxx23 %s +// RUN: %clang_cc1 -std=c++2c -verify=expected,since-cxx20,since-cxx23,since-cxx26 %s + +#if __cplusplus < 202002L +// expected-no-diagnostics +#endif + +namespace dr2847 { // dr2847: 19 + +#if __cplusplus >= 202002L + +template +void i(); + +struct A { + template + void f() requires true; + + template<> + void f() requires true; + // since-cxx20-error@-1 {{explicit specialization cannot have a trailing requires clause unless it declares a function template}} + + friend void i() requires true; + // since-cxx20-error@-1 {{friend specialization cannot have a trailing requires clause unless it declares a function template}} +}; + +template +struct B { + void f() requires true; + + template + void g() requires true; + + template + void h() requires true; + + template<> + void h() requires true; + // since-cxx20-error@-1 {{explicit specialization cannot have a trailing requires clause unless it declares a function template}} + + friend void i() requires true; + // since-cxx20-error@-1 {{friend specialization cannot have a trailing requires clause unless it declares a function template}} +}; + +template<> +void B::f() requires true; +// since-cxx20-error@-1 {{explicit specialization cannot have a trailing requires clause unless it declares a function template}} + +template<> +template +void B::g() requires true; + +#endif + +} // namespace dr2847 diff --git a/clang/test/CodeGen/aarch64-neon-intrinsics.c b/clang/test/CodeGen/aarch64-neon-intrinsics.c index 7c53b9b0af6bbcf265aa3aa9a5c1be592002d1fe..eeb50d095a5c97837dbc6e20ba665e5aca198bf3 100644 --- a/clang/test/CodeGen/aarch64-neon-intrinsics.c +++ b/clang/test/CodeGen/aarch64-neon-intrinsics.c @@ -14132,8 +14132,8 @@ int32_t test_vqshrund_n_s64(int64_t a) { // CHECK: [[VQRSHRUNH_N_S16:%.*]] = call <8 x i8> @llvm.aarch64.neon.sqrshrun.v8i8(<8 x i16> [[TMP0]], i32 8) // CHECK: [[TMP1:%.*]] = extractelement <8 x i8> [[VQRSHRUNH_N_S16]], i64 0 // CHECK: ret i8 [[TMP1]] -int8_t test_vqrshrunh_n_s16(int16_t a) { - return (int8_t)vqrshrunh_n_s16(a, 8); +uint8_t test_vqrshrunh_n_s16(int16_t a) { + return (uint8_t)vqrshrunh_n_s16(a, 8); } // CHECK-LABEL: @test_vqrshruns_n_s32( @@ -14141,15 +14141,15 @@ int8_t test_vqrshrunh_n_s16(int16_t a) { // CHECK: [[VQRSHRUNS_N_S32:%.*]] = call <4 x i16> @llvm.aarch64.neon.sqrshrun.v4i16(<4 x i32> [[TMP0]], i32 16) // CHECK: [[TMP1:%.*]] = extractelement <4 x i16> [[VQRSHRUNS_N_S32]], i64 0 // CHECK: ret i16 [[TMP1]] -int16_t test_vqrshruns_n_s32(int32_t a) { - return (int16_t)vqrshruns_n_s32(a, 16); +uint16_t test_vqrshruns_n_s32(int32_t a) { + return (uint16_t)vqrshruns_n_s32(a, 16); } // CHECK-LABEL: @test_vqrshrund_n_s64( // CHECK: [[VQRSHRUND_N_S64:%.*]] = call i32 @llvm.aarch64.neon.sqrshrun.i32(i64 %a, i32 32) // CHECK: ret i32 [[VQRSHRUND_N_S64]] -int32_t test_vqrshrund_n_s64(int64_t a) { - return (int32_t)vqrshrund_n_s64(a, 32); +uint32_t test_vqrshrund_n_s64(int64_t a) { + return (uint32_t)vqrshrund_n_s64(a, 32); } // CHECK-LABEL: @test_vcvts_n_f32_s32( diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c index 695e0afa3d0de75d53148068dbdcb1f2de494b41..a333d85818d2fac9bb865cf6842f3a7599e6bd59 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i32.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c index a3c3d8bf13db6fc8aa2691e4230548096a047ee3..7617dcef7ea973789bdffe38c32b8a06287b6a49 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_add-i64.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-i16i64 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c index 2c2f100ac7f8ccd814cc304178fc05227285be96..5fa4c35ed770ff0f4a31c4e886eca154bb9d84b9 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_cnt.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c index 0502073097d541167c0fb585cf85e72f6c2f8f60..b26e32e5ff833255f72529e79b27168c9acc94b6 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c index 60feebced32d2e1c903d3ed8b4c198314cbcdd03..02d4d034befb78a39f7ba0d2935c0f713c207d68 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ld1_vnum.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c index b0c1dd904284f548a7b7c9be11714599666c6ce5..c2c89aee03b5e6ea568977ecda8604f50b1656a0 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_ldr.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c index 3dcc2c70d3cfcd67875a3bd366666cf5f27a420c..e036cb45feff36e240f71b59000779e4b4dac2b4 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za32.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c index 06a6a19ca3f7a67524256a9d408e17850909acc5..84338597cdb30b2502de06645cf5ef42de1176d8 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mopa-za64.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c index 69641df8a80fb181cd7b8226585f89e6e49b09e0..7b1a8b0a0201ffcd65cf1106883ecc7649fc4ed4 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za32.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c index d726855c9743fb9527a74af82d1a3656719868a7..3d2a4e4d2b38e0cadd69f34313fbe5effd95253e 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_mops-za64.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +sve -target-feature +bf16 -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme-f64f64 -target-feature +sme-i16i64 -target-feature +bf16 -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c index ed1e70a3a469f507d1be846db8c34699dd021238..9e44d1c92534663d69764d8e96b6538aaa40ba43 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_read.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c index f93f3e5138b24df1257eac9c011c51f07a3c25d7..d8e4b853308d0f36c34569e9e14a5e165a5652fa 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c index b4bc041a21d5889700da9a6beb91fba04fa43853..467cf9fd092a04ce5942f83443fcdb0b3a25fc8e 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_st1_vnum.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c index 2ad7e364257235482013d30896b487c77d40e218..e58021bf8bf4563faa92e5e0b0b62af937779a7a 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_str.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c index a00a48ceafccb726a89f71f0ba573026855de53a..483e813275028fb08f0a495c69ee505bb1728cd3 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_write.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSME_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c index 9963c0e48b8e7b3ab9c000264bffa0b57f7b4280..1baa43b7187b71f4725b78021fa501339e9c46ab 100644 --- a/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c +++ b/clang/test/CodeGen/aarch64-sme-intrinsics/acle_sme_zero.c @@ -1,8 +1,8 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -target-feature +sve -S -O1 -Werror -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK,CHECK-C +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -emit-llvm -o - -x c++ %s | FileCheck %s -check-prefixes=CHECK,CHECK-CXX +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -S -O1 -Werror -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c index cfc2ee0f77be697c3b50e77c1fe53e521cfb9cc5..2cc99d4fb88d5f115b178313ac5114ba3f09c544 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_add.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c index 720254c84212034106d49756755171c267fe952f..1ff7a7fedf1bf3e4f984bf589dbac807355a5ea5 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_bmop.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c index a5dec263bff2c2c9095826d90f0ca8b629688192..257cb595250181634fd5eff2559d82ad9cea5649 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_clamp.c @@ -1,15 +1,15 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve \ -// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -Werror -emit-llvm -disable-O0-optnone -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 \ +// RUN: -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c index a8d881b1e2ed3ddf764e5b3bf39d48559a62a062..79a11c2ec153e4828bc613f5cbb22a84ade0ae59 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvt.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c index f03e998131df517374bbd4a287c28148ce30b819..2b2b2e5c0f411d3070ef17ebad75fd3c546bb1da 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_cvtn.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -D__SVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +bf16 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c index b90358112e47f15a77c7c644504fffde2cabc485..8d1e358176c30fb42fd00be5587d02ad60409386 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_frint.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c index 7c210fbe6923e92a786ef07509cebd15389e6725..70c31a4a87e7e9d3001fc6ef7c03601b47e3fcb6 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c index d7ef75ce01dd70d68de373e0ef487fbc1526307f..5bc9c9088517e8a7fa90a1a109b20edbd9f888b3 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x2.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c index f65c0ef61f8187113e176befae0d46b3217d1672..82c004e3105a43666bf02cc0ba378ba9996f6050 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti2_lane_zt_x4.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c index cbab1cc8e81bd4527415f5180691e751d44a8be4..e8706f9576915fb217e2bbffccb6a418d7264c02 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c index f7f16281ff4061aa7b9565189c12d2ba45adfe78..99feafbd682acbc9b92b465dec185cd40bf26a48 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x2.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c index 3fedfdc33089329fb2a13315b2d282214e4a2df2..0f0c33e48bd97b15a958dbc5c42ecacfb4bda06b 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_luti4_lane_zt_x4.c @@ -2,9 +2,9 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c index 4b9b4363ec62960ca7ba111067a48d501e7fb206..a4e2616784efa78f8892021669e55d6cd103bf5e 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_max.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s // REQUIRES: aarch64-registered-target #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c index 5e499573304c8186bdf2a4cf8f4307e4f8c60f13..3e554212cb70be1b162d16d01dc41f503574a346 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_maxnm.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c index 26c175c76532b7698d4f49c3bfb294589768cd7a..a438fd395219bb01790a666c028949a2253d004f 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_min.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s // REQUIRES: aarch64-registered-target #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c index 8c5e7eb4019919d42487fb212aa4cc6f03b4a46c..b0cbdc748dc80c9cba8ed5da5a4ab495a0b4279d 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_minnm.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c index b552bbb66a259e4bcbc27a08d56fa1c634bc823f..5cc0e0e1d36e1a154a8338ceccb26ff00e42b0c9 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mop.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c index cd87ee009995007d871075a457e23de01847a9f4..5fd4b04056526e231256099345e0013bc138923a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_read.c @@ -1,9 +1,9 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c index 6847eb99af2df3d526fe547858ac630faafb5571..b86cb19c01e308daba77863c743f61e8b64b9590 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_reinterpret_svcount_svbool.c @@ -2,10 +2,10 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c index c7da703ddb27183a0c593b86fece5453699f0bcf..7af8c589994fbb632bf4d5258003b4b2182e9d93 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_sub.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c index 6f20b37f87897db243eff6cf806355d781c5b029..5937a288dd846845cf7ebc5d7d1fc5c1fa206c90 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx2.c @@ -2,12 +2,12 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c index 781b699c882bb7a03ba9eb80afaf1bf572dec075..f54c09d5ef2c3755fffad71cc85d7953c12bfcaa 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_unpkx4.c @@ -2,12 +2,12 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c index 2b24f65efc26638b2ea95d56d7df94f6f33d0459..2fb5d3bea27c2346d135a152ada425ca07ac2cd3 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_add.c @@ -2,11 +2,11 @@ // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -fclang-abi-compat=latest -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-i16i64 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c index 32f9bc3ab88086dbc05f78c5893834fda2a58af8..eee927acc22e3420387edd9fbcbac153e54a41a2 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_qrshr.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f64f64 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c index 8735016ae728cf2d9a1418b5c442b80f8053476e..6308d6c596f164ae40df2fc0abe84137a120caa9 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_rshl.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c index 32eb9a4b40c4056308a2504b43df8708cf029fc7..c2ecbf93bfaa7859211e7cad94b22f9ea0e7266a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx2.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes=mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c index 6e9d5cf4492f545b8dc7135f2cbab3495aa9531b..784c24c8e7cb6872645ac96432033f607b725c89 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_selx4.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -passes mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include #ifdef SVE_OVERLOADED_FORMS diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c index f4dadef8fa5789d96ea596b4402a8d8b6704c651..6349cec771199ecda8a07dc5f811f0f7d8e7c52a 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx2.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c index ff7f0c501f55075334cef9e15f2ab9c06893305b..3d56948e25f73bb60ebd27bc65fd9753ab6ba5a1 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_uzpx4.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c index 3f13b3a0db73d95ecec21c0b92e8cd98c3f737e0..4cc1f3af32ec0584a4402d7b8a7b67980170193f 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx2.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c index b8408ea31ed0b49bb21973d27a5ef09978da5f31..cc356600ab53331a6f74903f5cd0df64cea23184 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_vector_zipx4.c @@ -1,10 +1,10 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c index 33733356f3078f72d0b894904a3aeaa628d70702..069bf13ff8d281fd617dbaf963a27699231573b3 100644 --- a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_write.c @@ -1,11 +1,11 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: aarch64-registered-target -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sve -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -target-feature +sve -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK -// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -target-feature +sve -disable-O0-optnone -Werror -Wall -o /dev/null %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s +// RUN: %clang_cc1 -DSVE_OVERLOADED_FORMS -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -emit-llvm -o - -x c++ %s | opt -S -p mem2reg,instcombine,tailcallelim | FileCheck %s -check-prefix=CPP-CHECK +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme2 -S -disable-O0-optnone -Werror -Wall -o /dev/null %s #include diff --git a/clang/test/CodeGen/ubsan-shift-bitint.c b/clang/test/CodeGen/ubsan-shift-bitint.c new file mode 100644 index 0000000000000000000000000000000000000000..844d5c4ad846188fc01d0d2d695df8851cac310c --- /dev/null +++ b/clang/test/CodeGen/ubsan-shift-bitint.c @@ -0,0 +1,36 @@ +// RUN: %clang_cc1 %s -O0 -fsanitize=shift-exponent -emit-llvm -std=c2x -triple=x86_64-unknown-linux -o - | FileCheck %s + +// Checking that the code generation is using the unextended/untruncated +// exponent values and capping the values accordingly + +// CHECK-LABEL: define{{.*}} i32 @test_left_variable +int test_left_variable(unsigned _BitInt(5) b, unsigned _BitInt(2) e) { + // CHECK: [[E_REG:%.+]] = load [[E_SIZE:i2]] + // CHECK: icmp ule [[E_SIZE]] [[E_REG]], -1 + return b << e; +} + +// CHECK-LABEL: define{{.*}} i32 @test_right_variable +int test_right_variable(unsigned _BitInt(2) b, unsigned _BitInt(3) e) { + // CHECK: [[E_REG:%.+]] = load [[E_SIZE:i3]] + // CHECK: icmp ule [[E_SIZE]] [[E_REG]], 1 + return b >> e; +} + +// Old code generation would give false positives on left shifts when: +// value(e) > (width(b) - 1 % 2 ** width(e)) +// CHECK-LABEL: define{{.*}} i32 @test_left_literal +int test_left_literal(unsigned _BitInt(5) b) { + // CHECK-NOT: br i1 false, label %cont, label %handler.shift_out_of_bounds + // CHECK: br i1 true, label %cont, label %handler.shift_out_of_bounds + return b << 3uwb; +} + +// Old code generation would give false positives on right shifts when: +// (value(e) % 2 ** width(b)) < width(b) +// CHECK-LABEL: define{{.*}} i32 @test_right_literal +int test_right_literal(unsigned _BitInt(2) b) { + // CHECK-NOT: br i1 true, label %cont, label %handler.shift_out_of_bounds + // CHECK: br i1 false, label %cont, label %handler.shift_out_of_bounds + return b >> 4uwb; +} diff --git a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl index 8d9e4e018b12e5a96ee0e9796d78df9bffd91cea..7d9010ee9067d679f552f9c73818f1d525723ae0 100644 --- a/clang/test/CodeGenOpenCL/builtins-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-amdgcn.cl @@ -832,6 +832,13 @@ void test_atomic_inc_dec(local uint *lptr, global uint *gptr, uint val) { res = __builtin_amdgcn_atomic_dec32((volatile global uint*)gptr, val, __ATOMIC_SEQ_CST, ""); } +// CHECK-LABEL test_wavefrontsize( +unsigned test_wavefrontsize() { + + // CHECK: call i32 @llvm.amdgcn.wavefrontsize() + return __builtin_amdgcn_wavefrontsize(); +} + // CHECK-DAG: [[$WI_RANGE]] = !{i32 0, i32 1024} // CHECK-DAG: [[$WS_RANGE]] = !{i16 1, i16 1025} // CHECK-DAG: attributes #[[$NOUNWIND_READONLY]] = { convergent mustprogress nocallback nofree nounwind willreturn memory(none) } diff --git a/clang/test/Driver/fbasic-block-sections.c b/clang/test/Driver/fbasic-block-sections.c index 24262209d1e4d51426f4a994c3f3b2d78d096852..e13cc81e910be363c0b6c683361dd44a2cd80a33 100644 --- a/clang/test/Driver/fbasic-block-sections.c +++ b/clang/test/Driver/fbasic-block-sections.c @@ -2,6 +2,10 @@ // RUN: %clang -### --target=x86_64 -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-ALL %s // RUN: %clang -### --target=x86_64 -fbasic-block-sections=list=%s %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LIST %s // RUN: %clang -### --target=x86_64 -fbasic-block-sections=labels %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LABELS %s +// RUN: %clang -### --target=aarch64 -fbasic-block-sections=none %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-NONE %s +// RUN: %clang -### --target=aarch64 -fbasic-block-sections=list=%s %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LIST %s +// RUN: %clang -### --target=aarch64 -fbasic-block-sections=labels %s -S 2>&1 | FileCheck -check-prefix=CHECK-OPT-LABELS %s +// RUN: not %clang -### --target=aarch64 -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-INVALID-VALUE %s // RUN: not %clang -c --target=arm-unknown-linux -fbasic-block-sections=all %s -S 2>&1 | FileCheck -check-prefix=CHECK-TRIPLE %s // RUN: %clang -### --target=arm-unknown-linux -fbasic-block-sections=all -fbasic-block-sections=none %s -S 2>&1 \ // RUN: | FileCheck -check-prefix=CHECK-NOOPT %s diff --git a/clang/test/Driver/android-version.cpp b/clang/test/Driver/invalid-version.cpp similarity index 54% rename from clang/test/Driver/android-version.cpp rename to clang/test/Driver/invalid-version.cpp index d365b701c0223b67953907873f5d99a68982c0c5..6a4702a9b66b0f765057948b892f48d468bd5277 100644 --- a/clang/test/Driver/android-version.cpp +++ b/clang/test/Driver/invalid-version.cpp @@ -14,3 +14,18 @@ // RUN: FileCheck --check-prefix=CHECK-TARGET %s // CHECK-TARGET: "aarch64-unknown-linux-android31" + +// RUN: not %clang --target=armv7-linux-gnuS -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-ERROR2 %s + +// CHECK-ERROR2: error: version 'S' in target triple 'armv7-unknown-linux-gnuS' is invalid + +// RUN: %clang --target=wasm32-unknown-wasi-preview2 -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-WASM %s + +// CHECK-WASM: "-triple" "wasm32-unknown-wasi-preview2" + +// RUN: %clang --target=wasm32-wasi-pthread -c %s -### 2>&1 | \ +// RUN: FileCheck --check-prefix=CHECK-WASM1 %s + +// CHECK-WASM1: "-triple" "wasm32-unknown-wasi-pthread" diff --git a/clang/test/Driver/linker-wrapper-image.c b/clang/test/Driver/linker-wrapper-image.c index b5d8ae217a9723d78fc868dd397d83bd05b47fb3..08f860f6cab0de421da75a5771232b55e3c6869e 100644 --- a/clang/test/Driver/linker-wrapper-image.c +++ b/clang/test/Driver/linker-wrapper-image.c @@ -9,6 +9,8 @@ // RUN: -fembed-offload-object=%t.out // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-linux-gnu \ // RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=OPENMP,OPENMP-ELF +// RUN: clang-linker-wrapper --print-wrapped-module --dry-run -r --host-triple=x86_64-unknown-linux-gnu \ +// RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=OPENMP-ELF,OPENMP-REL // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-windows-gnu \ // RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=OPENMP,OPENMP-COFF @@ -19,6 +21,8 @@ // OPENMP-COFF: @__start_omp_offloading_entries = weak_odr hidden constant [0 x %struct.__tgt_offload_entry] zeroinitializer, section "omp_offloading_entries$OA" // OPENMP-COFF-NEXT: @__stop_omp_offloading_entries = weak_odr hidden constant [0 x %struct.__tgt_offload_entry] zeroinitializer, section "omp_offloading_entries$OZ" +// OPENMP-REL: @.omp_offloading.device_image = internal unnamed_addr constant [[[SIZE:[0-9]+]] x i8] c"\10\FF\10\AD{{.*}}", section ".llvm.offloading.relocatable", align 8 + // OPENMP: @.omp_offloading.device_image = internal unnamed_addr constant [[[SIZE:[0-9]+]] x i8] c"\10\FF\10\AD{{.*}}", section ".llvm.offloading", align 8 // OPENMP-NEXT: @.omp_offloading.device_images = internal unnamed_addr constant [1 x %__tgt_device_image] [%__tgt_device_image { ptr getelementptr inbounds ([[[BEGIN:[0-9]+]] x i8], ptr @.omp_offloading.device_image, i64 1, i64 0), ptr getelementptr inbounds ([[[END:[0-9]+]] x i8], ptr @.omp_offloading.device_image, i64 1, i64 0), ptr @__start_omp_offloading_entries, ptr @__stop_omp_offloading_entries }] // OPENMP-NEXT: @.omp_offloading.descriptor = internal constant %__tgt_bin_desc { i32 1, ptr @.omp_offloading.device_images, ptr @__start_omp_offloading_entries, ptr @__stop_omp_offloading_entries } @@ -42,6 +46,8 @@ // RUN: -fembed-offload-object=%t.out // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-linux-gnu \ // RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=CUDA,CUDA-ELF +// RUN: clang-linker-wrapper --print-wrapped-module --dry-run -r --host-triple=x86_64-unknown-linux-gnu \ +// RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=CUDA,CUDA-ELF // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-windows-gnu \ // RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=CUDA,CUDA-COFF @@ -140,6 +146,8 @@ // RUN: -fembed-offload-object=%t.out // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-linux-gnu \ // RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=HIP,HIP-ELF +// RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-linux-gnu -r \ +// RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=HIP,HIP-ELF // RUN: clang-linker-wrapper --print-wrapped-module --dry-run --host-triple=x86_64-unknown-windows-gnu \ // RUN: --linker-path=/usr/bin/ld -- %t.o -o a.out 2>&1 | FileCheck %s --check-prefixes=HIP,HIP-COFF diff --git a/clang/test/Driver/linker-wrapper.c b/clang/test/Driver/linker-wrapper.c index a8667c99977c5cc3d1c2c0a0d896c9e8aac233cd..010001b83d7c2de669058304aa99a54903b03aca 100644 --- a/clang/test/Driver/linker-wrapper.c +++ b/clang/test/Driver/linker-wrapper.c @@ -176,10 +176,36 @@ __attribute__((visibility("protected"), used)) int x; // RUN: --image=file=%t.elf.o,kind=openmp,triple=x86_64-unknown-linux-gnu \ // RUN: --image=file=%t.elf.o,kind=openmp,triple=x86_64-unknown-linux-gnu // RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o -fembed-offload-object=%t.out -// RUN: llvm-ar rcs %t.a %t.o // RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ -// RUN: --linker-path=/usr/bin/ld.lld -- -r --whole-archive %t.a --no-whole-archive \ +// RUN: --linker-path=/usr/bin/ld.lld -- -r %t.o \ // RUN: %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=RELOCATABLE-LINK -// RELOCATABLE-LINK-NOT: clang{{.*}} -o {{.*}}.img --target=x86_64-unknown-linux-gnu +// RELOCATABLE-LINK: clang{{.*}} -o {{.*}}.img --target=x86_64-unknown-linux-gnu // RELOCATABLE-LINK: /usr/bin/ld.lld{{.*}}-r +// RELOCATABLE-LINK: llvm-objcopy{{.*}}a.out --remove-section .llvm.offloading + +// RUN: clang-offload-packager -o %t.out \ +// RUN: --image=file=%t.elf.o,kind=hip,triple=amdgcn-amd-amdhsa,arch=gfx90a \ +// RUN: --image=file=%t.elf.o,kind=hip,triple=amdgcn-amd-amdhsa,arch=gfx90a +// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o -fembed-offload-object=%t.out +// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ +// RUN: --linker-path=/usr/bin/ld.lld -- -r %t.o \ +// RUN: %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=RELOCATABLE-LINK-HIP + +// RELOCATABLE-LINK-HIP: clang{{.*}} -o {{.*}}.img --target=amdgcn-amd-amdhsa +// RELOCATABLE-LINK-HIP: clang-offload-bundler{{.*}} -type=o -bundle-align=4096 -targets=host-x86_64-unknown-linux,hipv4-amdgcn-amd-amdhsa--gfx90a -input=/dev/null -input={{.*}} -output={{.*}} +// RELOCATABLE-LINK-HIP: /usr/bin/ld.lld{{.*}}-r +// RELOCATABLE-LINK-HIP: llvm-objcopy{{.*}}a.out --remove-section .llvm.offloading + +// RUN: clang-offload-packager -o %t.out \ +// RUN: --image=file=%t.elf.o,kind=cuda,triple=nvptx64-nvidia-cuda,arch=sm_89 \ +// RUN: --image=file=%t.elf.o,kind=cuda,triple=nvptx64-nvidia-cuda,arch=sm_89 +// RUN: %clang -cc1 %s -triple x86_64-unknown-linux-gnu -emit-obj -o %t.o -fembed-offload-object=%t.out +// RUN: clang-linker-wrapper --host-triple=x86_64-unknown-linux-gnu --dry-run \ +// RUN: --linker-path=/usr/bin/ld.lld -- -r %t.o \ +// RUN: %t.o -o a.out 2>&1 | FileCheck %s --check-prefix=RELOCATABLE-LINK-CUDA + +// RELOCATABLE-LINK-CUDA: clang{{.*}} -o {{.*}}.img --target=nvptx64-nvidia-cuda +// RELOCATABLE-LINK-CUDA: fatbinary{{.*}} -64 --create {{.*}}.fatbin --image=profile=sm_89,file={{.*}}.img +// RELOCATABLE-LINK-CUDA: /usr/bin/ld.lld{{.*}}-r +// RELOCATABLE-LINK-CUDA: llvm-objcopy{{.*}}a.out --remove-section .llvm.offloading diff --git a/clang/test/Driver/wasm-features.c b/clang/test/Driver/wasm-features.c index 1a43361a4a108069cbd211a251a04d1662543e57..5dae5dbc89b905fa0ff77f83450091415d23b64a 100644 --- a/clang/test/Driver/wasm-features.c +++ b/clang/test/Driver/wasm-features.c @@ -2,51 +2,89 @@ // CHECK: "-fvisibility=hidden" -// RUN: %clang --target=wasm32-unknown-unknown -### %s 2>&1 | FileCheck %s -check-prefix=DEFAULT // RUN: %clang --target=wasm32-unknown-unknown -### %s -mcpu=mvp 2>&1 | FileCheck %s -check-prefix=MVP +// RUN: %clang --target=wasm32-unknown-unknown -### %s 2>&1 | FileCheck %s -check-prefix=GENERIC +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mcpu=generic 2>&1 | FileCheck %s -check-prefix=GENERIC // RUN: %clang --target=wasm32-unknown-unknown -### %s -mcpu=bleeding-edge 2>&1 | FileCheck %s -check-prefix=BLEEDING-EDGE +// MVP: "-target-cpu" "mvp" +// GENERIC: "-target-cpu" "generic" +// BLEEDING-EDGE: "-target-cpu" "bleeding-edge" + // RUN: %clang --target=wasm32-unknown-unknown -### %s -mbulk-memory 2>&1 | FileCheck %s -check-prefix=BULK-MEMORY // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-bulk-memory 2>&1 | FileCheck %s -check-prefix=NO-BULK-MEMORY // BULK-MEMORY: "-target-feature" "+bulk-memory" // NO-BULK-MEMORY: "-target-feature" "-bulk-memory" -// DEFAULT-NOT: "-target-feature" "-bulk-memory" -// MVP-NOT: "-target-feature" "+bulk-memory" -// BLEEDING-EDGE-NOT: "-target-feature" "-bulk-memory" // RUN: %clang --target=wasm32-unknown-unknown -### %s -mmutable-globals 2>&1 | FileCheck %s -check-prefix=MUTABLE-GLOBALS // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-mutable-globals 2>&1 | FileCheck %s -check-prefix=NO-MUTABLE-GLOBALS // MUTABLE-GLOBALS: "-target-feature" "+mutable-globals" // NO-MUTABLE-GLOBALS: "-target-feature" "-mutable-globals" -// DEFAULT-NOT: "-target-feature" "-mutable-globals" -// MVP-NOT: "-target-feature" "+mutable-globals" -// BLEEDING-EDGE-NOT: "-target-feature" "-mutable-globals" // RUN: %clang --target=wasm32-unknown-unknown -### %s -msign-ext 2>&1 | FileCheck %s -check-prefix=SIGN-EXT // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-sign-ext 2>&1 | FileCheck %s -check-prefix=NO-SIGN-EXT // SIGN-EXT: "-target-feature" "+sign-ext" // NO-SIGN-EXT: "-target-feature" "-sign-ext" -// DEFAULT-NOT: "-target-feature" "-sign-ext" -// MVP-NOT: "-target-feature" "+sign-ext" -// BLEEDING-EDGE-NOT: "-target-feature" "-sign-ext" // RUN: %clang --target=wasm32-unknown-unknown -### %s -mnontrapping-fptoint 2>&1 | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-nontrapping-fptoint 2>&1 | FileCheck %s -check-prefix=NO-NONTRAPPING-FPTOINT // NONTRAPPING-FPTOINT: "-target-feature" "+nontrapping-fptoint" // NO-NONTRAPPING-FPTOINT: "-target-feature" "-nontrapping-fptoint" -// DEFAULT-NOT: "-target-feature" "-nontrapping-fptoint" -// MVP-NOT: "-target-feature" "+nontrapping-fptoint" -// BLEEDING-EDGE-NOT: "-target-feature" "-nontrapping-fptoint" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mmultivalue 2>&1 | FileCheck %s -check-prefix=MULTIVALUE +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-multivalue 2>&1 | FileCheck %s -check-prefix=NO-MULTIVALUE + +// MULTIVALUE: "-target-feature" "+multivalue" +// NO-MULTIVALUE: "-target-feature" "-multivalue" // RUN: %clang --target=wasm32-unknown-unknown -### %s -mmultimemory 2>&1 | FileCheck %s -check-prefix=MULTIMEMORY // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-multimemory 2>&1 | FileCheck %s -check-prefix=NO-MULTIMEMORY // MULTIMEMORY: "-target-feature" "+multimemory" // NO-MULTIMEMORY: "-target-feature" "-multimemory" -// DEFAULT-NOT: "-target-feature" "-multimemory" -// MVP-NOT: "-target-feature" "+multimemory" -// BLEEDING-EDGE-NOT: "-target-feature" "-multimemory" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -matomics 2>&1 | FileCheck %s -check-prefix=ATOMICS +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-atomics 2>&1 | FileCheck %s -check-prefix=NO-ATOMICS + +// ATOMICS: "-target-feature" "+atomics" +// NO-ATOMICS: "-target-feature" "-atomics" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mtail-call 2>&1 | FileCheck %s -check-prefix=TAIL-CALL +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-tail-call 2>&1 | FileCheck %s -check-prefix=NO-TAIL-CALL + +// TAIL-CALL: "-target-feature" "+tail-call" +// NO-TAIL-CALL: "-target-feature" "-tail-call" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mreference-types 2>&1 | FileCheck %s -check-prefix=REFERENCE-TYPES +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-reference-types 2>&1 | FileCheck %s -check-prefix=NO-REFERENCE-TYPES + +// REFERENCE-TYPES: "-target-feature" "+reference-types" +// NO-REFERENCE-TYPES: "-target-feature" "-reference-types" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -msimd128 2>&1 | FileCheck %s -check-prefix=SIMD128 +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-simd128 2>&1 | FileCheck %s -check-prefix=NO-SIMD128 + +// SIMD128: "-target-feature" "+simd128" +// NO-SIMD128: "-target-feature" "-simd128" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mrelaxed-simd 2>&1 | FileCheck %s -check-prefix=RELAXED-SIMD +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-relaxed-simd 2>&1 | FileCheck %s -check-prefix=NO-RELAXED-SIMD + +// RELAXED-SIMD: "-target-feature" "+relaxed-simd" +// NO-RELAXED-SIMD: "-target-feature" "-relaxed-simd" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mexception-handling 2>&1 | FileCheck %s -check-prefix=EXCEPTION-HANDLING +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-exception-handling 2>&1 | FileCheck %s -check-prefix=NO-EXCEPTION-HANDLING + +// EXCEPTION-HANDLING: "-target-feature" "+exception-handling" +// NO-EXCEPTION-HANDLING: "-target-feature" "-exception-handling" + +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mextended-const 2>&1 | FileCheck %s -check-prefix=EXTENDED-CONST +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-extended-const 2>&1 | FileCheck %s -check-prefix=NO-EXTENDED-CONST + +// EXTENDED-CONST: "-target-feature" "+extended-const" +// NO-EXTENDED-CONST: "-target-feature" "-extended-const" diff --git a/clang/test/Format/clang-format-ignore.cpp b/clang/test/Format/clang-format-ignore.cpp index b4e526463000ae3a7bbaaee51a6d839429d2dee3..fb49fa9dd52c650676e32c65507ad341442f6a04 100644 --- a/clang/test/Format/clang-format-ignore.cpp +++ b/clang/test/Format/clang-format-ignore.cpp @@ -1,4 +1,3 @@ -// UNSUPPORTED: system-windows // RUN: rm -rf %t.dir // RUN: mkdir -p %t.dir/level1/level2 diff --git a/clang/test/Frontend/fixed_point_errors.cpp b/clang/test/Frontend/fixed_point_errors.cpp index 4097cd73c845050c6e27867d76c30c9e59b6dee3..ef064bc38873d81bdac971625e2453166acd4674 100644 --- a/clang/test/Frontend/fixed_point_errors.cpp +++ b/clang/test/Frontend/fixed_point_errors.cpp @@ -14,3 +14,7 @@ int fract_int = 10r; // expected-error{{invalid suffix 'r' on integer consta float accum_flt = 0.0k; // expected-error{{invalid suffix 'k' on floating constant}} float fract_flt = 0.0r; // expected-error{{invalid suffix 'r' on floating constant}} #endif + +#ifndef WITHOUT_FIXED_POINT +const char *c = 10.0k; // expected-error{{cannot initialize a variable of type 'const char *' with an rvalue of type '_Accum'}} +#endif diff --git a/clang/test/Frontend/verify.c b/clang/test/Frontend/verify.c index c549011d7b7a9a261b1b918969e88418ef247c9b..afd1c7d6907e20ba987e04682fdd0d1768cb6b35 100644 --- a/clang/test/Frontend/verify.c +++ b/clang/test/Frontend/verify.c @@ -187,3 +187,32 @@ unexpected b; // expected-error@33 1-1 {{unknown type}} #endif #endif + +#ifdef TEST10 +// RUN: not %clang_cc1 -DTEST10 -verify=foo %s 2>&1 | FileCheck -check-prefix=CHECK10 %s + +// CHECK10: error: no expected directives found: consider use of 'foo-no-diagnostics' +#endif + +#ifdef TEST11 +// RUN: not %clang_cc1 -DTEST11 -verify=foo %s 2>&1 | FileCheck -check-prefix=CHECK11 %s + +// foo-no-diagnostics +// foo-note {{}} + +// CHECK11: error: 'foo-error' diagnostics seen but not expected: +// CHECK11-NEXT: Line 201: expected directive cannot follow 'foo-no-diagnostics' directive +// CHECK11-NEXT: 1 error generated. +#endif + +#ifdef TEST12 +// RUN: not %clang_cc1 -DTEST12 -verify=foo %s 2>&1 | FileCheck -check-prefix=CHECK12 %s + +#warning X +// foo-warning@-1 {{X}} +// foo-no-diagnostics + +// CHECK12: error: 'foo-error' diagnostics seen but not expected: +// CHECK12-NEXT: Line 213: 'foo-no-diagnostics' directive cannot follow other expected directives +// CHECK12-NEXT: 1 error generated. +#endif diff --git a/clang/test/OpenMP/bug69085.c b/clang/test/OpenMP/bug69085.c new file mode 100644 index 0000000000000000000000000000000000000000..1017ea53b41e3dcc96b5424c88d907c54cd2b575 --- /dev/null +++ b/clang/test/OpenMP/bug69085.c @@ -0,0 +1,10 @@ +// RUN: %clang_cc1 -verify -O0 -fopenmp-simd %s + +int k[-1]; // expected-error {{'k' declared as an array with a negative size}} + +void foo() { + #pragma omp task depend(inout: k [:]) + { + k[0] = 1; + } +} diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index add96c0046cc73b750c27312866621678c7c4c6c..ea81c662044306c9891c8f3e1f7a40b95a333a96 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -163,6 +163,7 @@ // CHECK-NOT: __riscv_smnpm{{.*$}} // CHECK-NOT: __riscv_ssnpm{{.*$}} // CHECK-NOT: __riscv_sspm{{.*$}} +// CHECK-NOT: __riscv_ssqosid{{.*$}} // CHECK-NOT: __riscv_supm{{.*$}} // CHECK-NOT: __riscv_zaamo {{.*$}} // CHECK-NOT: __riscv_zacas {{.*$}} @@ -1599,19 +1600,27 @@ // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_sspm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s -// RUN: %clang --target=riscv64 \ -// RUN: -march=rv64i_sspm0p8 -E -dM %s -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_sspm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s // CHECK-SSPM-EXT: __riscv_sspm 8000{{$}} // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_supm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s -// RUN: %clang --target=riscv64 \ -// RUN: -march=rv64i_supm0p8 -E -dM %s -menable-experimental-extensions \ +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_supm0p8 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s // CHECK-SUPM-EXT: __riscv_supm 8000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32i_ssqosid1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64i_ssqosid1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-SSQOSID-EXT %s +// CHECK-SSQOSID-EXT: __riscv_ssqosid 1000000{{$}} + // Misaligned // RUN: %clang --target=riscv32-unknown-linux-gnu -march=rv32i -E -dM %s \ diff --git a/clang/test/Preprocessor/wasm-target-features.c b/clang/test/Preprocessor/wasm-target-features.c index c225e226b69ba14e821249e5753141d6b60d1bf9..eccd432aa8eee66d12bf146a291bf0f6cd10696c 100644 --- a/clang/test/Preprocessor/wasm-target-features.c +++ b/clang/test/Preprocessor/wasm-target-features.c @@ -144,6 +144,27 @@ // MVP-NOT:#define __wasm_reference_types__ // MVP-NOT:#define __wasm_extended_const__ // MVP-NOT:#define __wasm_multimemory__ +// MVP-NOT:#define __wasm_relaxed_simd__ + +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm32-unknown-unknown -mcpu=generic \ +// RUN: | FileCheck %s -check-prefix=GENERIC +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm64-unknown-unknown -mcpu=generic \ +// RUN: | FileCheck %s -check-prefix=GENERIC +// +// GENERIC-DAG:#define __wasm_sign_ext__ 1{{$}} +// GENERIC-DAG:#define __wasm_mutable_globals__ 1{{$}} +// GENERIC-NOT:#define __wasm_nontrapping_fptoint__ 1{{$}} +// GENERIC-NOT:#define __wasm_bulk_memory__ 1{{$}} +// GENERIC-NOT:#define __wasm_simd128__ 1{{$}} +// GENERIC-NOT:#define __wasm_atomics__ 1{{$}} +// GENERIC-NOT:#define __wasm_tail_call__ 1{{$}} +// GENERIC-NOT:#define __wasm_multimemory__ 1{{$}} +// GENERIC-NOT:#define __wasm_exception_handling__ 1{{$}} +// GENERIC-NOT:#define __wasm_multivalue__ 1{{$}} +// GENERIC-NOT:#define __wasm_reference_types__ 1{{$}} +// GENERIC-NOT:#define __wasm_extended_const__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge \ @@ -160,11 +181,11 @@ // BLEEDING-EDGE-DAG:#define __wasm_mutable_globals__ 1{{$}} // BLEEDING-EDGE-DAG:#define __wasm_tail_call__ 1{{$}} // BLEEDING-EDGE-DAG:#define __wasm_multimemory__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_unimplemented_simd128__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_exception_handling__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_multivalue__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_reference_types__ 1{{$}} // BLEEDING-EDGE-NOT:#define __wasm_extended_const__ 1{{$}} +// BLEEDING-EDGE-NOT:#define __wasm_relaxed_simd__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge -mno-simd128 \ diff --git a/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c b/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c index ed47101d6443096146f145f9f63057c25d37b4eb..c72510beddb13cd58ccb518e8cfb8dcbaaa273cc 100644 --- a/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c +++ b/clang/test/Sema/fp-eval-pragma-with-float-double_t-1.c @@ -1,23 +1,40 @@ // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ -// RUN: -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -fexperimental-new-constant-interpreter + +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=source -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=source -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=source \ // RUN: -DNOERROR %s - +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=source \ +// RUN: -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=double %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=double %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=extended %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=extended %s - +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter #ifdef NOERROR // expected-no-diagnostics diff --git a/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c b/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c index 61bf7c970807cbc055c125970a858da873e9146c..f26b43f7cd378a6dc95f49cb25b2360623643ce9 100644 --- a/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c +++ b/clang/test/Sema/fp-eval-pragma-with-float-double_t-2.c @@ -1,21 +1,41 @@ // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -x c++ -DCPP -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=double -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=double -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=double -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=double -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=extended %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=extended %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=extended %s -fexperimental-new-constant-interpreter #ifdef NOERROR // expected-no-diagnostics diff --git a/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c b/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c index 8be5c5535af39d8982b73f5bc3231935ea0b21a2..d58a36dc108ae49dcef8785736ecb88b98f48807 100644 --- a/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c +++ b/clang/test/Sema/fp-eval-pragma-with-float-double_t-3.c @@ -1,22 +1,40 @@ // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -x c++ -DCPP -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -x c++ -DCPP -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=extended -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=extended -DNOERROR %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=extended -DNOERROR %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=extended -DNOERROR %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=source %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=source %s -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ // RUN: -ffp-eval-method=double %s +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter + // RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ // RUN: -ffp-eval-method=double %s - +// RUN: %clang_cc1 -verify -triple x86_64-linux-gnu -fsyntax-only -x c++ -DCPP \ +// RUN: -ffp-eval-method=double %s -fexperimental-new-constant-interpreter #ifdef NOERROR // expected-no-diagnostics diff --git a/clang/test/Sema/struct-cast.c b/clang/test/Sema/struct-cast.c index 74d00c42c295e039afac92a1f813322f775d2993..05e5fa4f92ca7693e19837046c7140270ced3e44 100644 --- a/clang/test/Sema/struct-cast.c +++ b/clang/test/Sema/struct-cast.c @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -fsyntax-only %s -verify +// RUN: %clang_cc1 -fsyntax-only %s -fexperimental-new-constant-interpreter -verify // expected-no-diagnostics struct S { diff --git a/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp b/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp index 8a610fa0e737e1f20ee1289b89fec5a33767b9cf..03a432e05851d1f9fa4bc13fda282e05bdd5e09f 100644 --- a/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp +++ b/clang/test/Sema/warn-infinity-nan-disabled-lnx.cpp @@ -1,13 +1,31 @@ -// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs -menable-no-nans +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -std=c++23 -// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown %s +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-infs -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs +// RUN: -menable-no-infs -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-nans -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-nans +// RUN: -funsafe-math-optimizations -menable-no-nans -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-infs -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-nans -std=c++23 // no-fast-no-diagnostics @@ -133,13 +151,41 @@ int compareit(float a, float b) { // no-inf-warning@+1 {{use of infinity is undefined behavior due to the currently enabled floating-point options}} p = __builtin_isfinite(a); - // These should NOT warn, since they are not using NaN or infinity. +// These should NOT warn, since they are not using NaN or infinity. j = a > 1.1; j = b < 1.1; j = a >= 1.1; j = b <= 1.1; j = isunorderedf(a, b); +#ifndef INFINITY + j = a; +#endif +#ifndef NAN + j = b; +#endif +#ifdef INFINITY + j = a; +#endif +#ifdef NAN + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(INFINITY) + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(NAN) + j = b; +#endif +#if defined(NAN) + j = a; +#elifndef(INFINITY) + j = b; +#endif + // no-inf-no-nan-warning@+4 {{use of NaN via a macro is undefined behavior due to the currently enabled floating-point options}} // no-inf-no-nan-warning@+3 {{use of NaN is undefined behavior due to the currently enabled floating-point options}} // no-nan-warning@+2 {{use of NaN via a macro is undefined behavior due to the currently enabled floating-point options}} @@ -173,4 +219,4 @@ int compareit(float a, float b) { j = numeric_limits::infinity(); return 0; -} +} diff --git a/clang/test/Sema/warn-infinity-nan-disabled-win.cpp b/clang/test/Sema/warn-infinity-nan-disabled-win.cpp index 19a575386e32932a158a9ee9bf46a139b15e6e36..51f9d325619ba042b837efc7be7896d743f004b0 100644 --- a/clang/test/Sema/warn-infinity-nan-disabled-win.cpp +++ b/clang/test/Sema/warn-infinity-nan-disabled-win.cpp @@ -1,16 +1,34 @@ // Use of NAN macro will trigger a warning "infinity defined in macro" because // on Windows the NAN macro is defined using INFINITY. See below. -// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs -menable-no-nans +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -std=c++23 -// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown %s +// RUN: %clang_cc1 -x c++ -verify=no-inf-no-nan \ +// RUN: -triple powerpc64le-unknown-unknown %s -menable-no-infs \ +// RUN: -menable-no-nans -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-infs -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-inf -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-infs +// RUN: -menable-no-infs -funsafe-math-optimizations -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ +// RUN: -menable-no-nans -std=c++23 // RUN: %clang_cc1 -x c++ -verify=no-nan -triple powerpc64le-unknown-unknown %s \ -// RUN: -menable-no-nans +// RUN: -funsafe-math-optimizations -menable-no-nans -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-infs -std=c++23 + +// RUN: %clang_cc1 -x c++ -verify=no-fast -triple powerpc64le-unknown-unknown \ +// RUN: %s -Wno-nan-infinity-disabled -menable-no-nans -std=c++23 // no-fast-no-diagnostics @@ -136,13 +154,41 @@ int compareit(float a, float b) { // no-inf-warning@+1 {{use of infinity is undefined behavior due to the currently enabled floating-point options}} p = __builtin_isfinite(a); - // These should NOT warn, since they are not using NaN or infinity. +// These should NOT warn, since they are not using NaN or infinity. j = a > 1.1; j = b < 1.1; j = a >= 1.1; j = b <= 1.1; j = isunorderedf(a, b); +#ifndef INFINITY + j = a; +#endif +#ifndef NAN + j = b; +#endif +#ifdef INFINITY + j = a; +#endif +#ifdef NAN + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(INFINITY) + j = b; +#endif +#if defined(INFINITY) + j = a; +#elifndef(NAN) + j = b; +#endif +#if defined(NAN) + j = a; +#elifndef(INFINITY) + j = b; +#endif + // no-inf-no-nan-warning@+4 {{use of infinity via a macro is undefined behavior due to the currently enabled floating-point option}} // no-inf-no-nan-warning@+3 {{use of NaN via a macro is undefined behavior due to the currently enabled floating-point options}} // no-inf-warning@+2 {{use of infinity via a macro is undefined behavior due to the currently enabled floating-point options}} @@ -176,4 +222,4 @@ int compareit(float a, float b) { j = numeric_limits::infinity(); return 0; -} +} diff --git a/clang/test/Sema/warn-int-in-bool-context.c b/clang/test/Sema/warn-int-in-bool-context.c index a6890161b5af89d2449aebc1f5db8bcb46029267..c111a5af23f5772a0d593b3691c44ef7b8955945 100644 --- a/clang/test/Sema/warn-int-in-bool-context.c +++ b/clang/test/Sema/warn-int-in-bool-context.c @@ -79,3 +79,14 @@ int test(int a, unsigned b, enum num n) { // Don't warn in macros. return SHIFT(1, a); } + +int GH64356(int arg) { + if ((arg == 1) && (1 == 1)) return 1; + return 0; + + if ((64 > 32) && (32 < 64)) + return 2; + + if ((1 == 1) && (arg == 1)) return 1; + return 0; +} diff --git a/clang/test/SemaCXX/cxx11-default-member-initializers.cpp b/clang/test/SemaCXX/cxx11-default-member-initializers.cpp index 9c18c73be8f68e8ff5675df9019740d2c98099b9..dd8e9c6b7fc11f0384840513a17afa4723cb484e 100644 --- a/clang/test/SemaCXX/cxx11-default-member-initializers.cpp +++ b/clang/test/SemaCXX/cxx11-default-member-initializers.cpp @@ -1,5 +1,7 @@ // RUN: %clang_cc1 -std=c++11 -verify %s -pedantic +// RUN: %clang_cc1 -std=c++11 -verify %s -pedantic -fexperimental-new-constant-interpreter // RUN: %clang_cc1 -std=c++20 -verify %s -pedantic +// RUN: %clang_cc1 -std=c++20 -verify %s -pedantic -fexperimental-new-constant-interpreter namespace PR31692 { diff --git a/clang/test/SemaCXX/cxx1z-copy-omission.cpp b/clang/test/SemaCXX/cxx1z-copy-omission.cpp index f46a17af833867737a297c0d7d4a08bf27eb0179..92ebfdd8e4c735737e2f77b8dbbbf799198da32c 100644 --- a/clang/test/SemaCXX/cxx1z-copy-omission.cpp +++ b/clang/test/SemaCXX/cxx1z-copy-omission.cpp @@ -1,4 +1,5 @@ // RUN: %clang_cc1 -std=c++1z -verify -Wno-unused %s +// RUN: %clang_cc1 -std=c++1z -verify -Wno-unused %s -fexperimental-new-constant-interpreter struct Noncopyable { Noncopyable(); diff --git a/clang/test/SemaCXX/cxx20-using-enum.cpp b/clang/test/SemaCXX/cxx20-using-enum.cpp index 872353aad8a0d48e2f4d575830588dade217e87c..d16df4e1b9d3cd2310fdd07be7111c66c7a088e4 100644 --- a/clang/test/SemaCXX/cxx20-using-enum.cpp +++ b/clang/test/SemaCXX/cxx20-using-enum.cpp @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -fsyntax-only -std=c++17 -verify %s -// RUN: %clang_cc1 -fsyntax-only -std=c++20 -verify %s +// RUN: %clang_cc1 -fsyntax-only -std=c++17 -verify %s -fexperimental-new-constant-interpreter +// RUN: %clang_cc1 -fsyntax-only -std=c++20 -verify %s -fexperimental-new-constant-interpreter // p1099 'using enum ELABORATED-ENUM-SPECIFIER ;' diff --git a/clang/test/SemaCXX/cxx2b-deducing-this.cpp b/clang/test/SemaCXX/cxx2b-deducing-this.cpp index aab35828096a8ef02ad43fbcf3b3199146534b73..30131d6adc4db01e3b7d90b19cb2f036dde8172d 100644 --- a/clang/test/SemaCXX/cxx2b-deducing-this.cpp +++ b/clang/test/SemaCXX/cxx2b-deducing-this.cpp @@ -636,3 +636,13 @@ struct D { } }; } + +namespace GH80971 { +struct S { + auto f(this auto self...) { } +}; + +int bug() { + S{}.f(0); +} +} diff --git a/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug.cpp b/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug.cpp index e08f70d97e3912ff9561253e2e3e442108769d4d..5fff0854d454673dc9c765f9bb74a4801ba4f725 100644 --- a/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug.cpp +++ b/clang/test/SemaCXX/warn-unsafe-buffer-usage-debug.cpp @@ -98,3 +98,10 @@ void test_struct_claim_use() { x[6] = 8; // expected-warning{{unsafe buffer access}} x++; // expected-warning{{unsafe pointer arithmetic}} } + +void use(int*); +void array2d(int idx) { + int buffer[10][5]; // expected-warning{{'buffer' is an unsafe buffer that does not perform bounds checks}} + use(buffer[idx]); // expected-note{{used in buffer access here}} \ + // debug-note{{safe buffers debug: failed to produce fixit for 'buffer' : has an unclaimed use}} +} diff --git a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp index b6fea2e0b4b31751a56dbf1c5dc92de0733ce41a..0142efcdc3ee86593f764290b24f190f71f0be7c 100644 --- a/clang/test/SemaTemplate/concepts-out-of-line-def.cpp +++ b/clang/test/SemaTemplate/concepts-out-of-line-def.cpp @@ -581,3 +581,21 @@ void S::test(T target, U... value) } {} } // namespace GH74447 + +namespace GH72557 { + +template +concept IsAnyOf = true; + +template struct DerivedCollection { + template + requires IsAnyOf + unsigned long index(); +}; + +template +template + requires IsAnyOf +unsigned long DerivedCollection::index() {} + +} // namespace GH72557 diff --git a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp index b682cc293d54b210d91cf35a4917c93176b265bf..095cf5ed3816959b14dd727dc1c3cc7361f9bf10 100644 --- a/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp +++ b/clang/tools/clang-linker-wrapper/ClangLinkerWrapper.cpp @@ -241,6 +241,70 @@ Expected findProgram(StringRef Name, ArrayRef Paths) { return *Path; } +/// Returns the hashed value for a constant string. +std::string getHash(StringRef Str) { + llvm::MD5 Hasher; + llvm::MD5::MD5Result Hash; + Hasher.update(Str); + Hasher.final(Hash); + return llvm::utohexstr(Hash.low(), /*LowerCase=*/true); +} + +/// Renames offloading entry sections in a relocatable link so they do not +/// conflict with a later link job. +Error relocateOffloadSection(const ArgList &Args, StringRef Output) { + llvm::Triple Triple( + Args.getLastArgValue(OPT_host_triple_EQ, sys::getDefaultTargetTriple())); + if (Triple.isOSWindows()) + return createStringError( + inconvertibleErrorCode(), + "Relocatable linking is not supported on COFF targets"); + + Expected ObjcopyPath = + findProgram("llvm-objcopy", {getMainExecutable("llvm-objcopy")}); + if (!ObjcopyPath) + return ObjcopyPath.takeError(); + + // Use the linker output file to get a unique hash. This creates a unique + // identifier to rename the sections to that is deterministic to the contents. + auto BufferOrErr = DryRun ? MemoryBuffer::getMemBuffer("") + : MemoryBuffer::getFileOrSTDIN(Output); + if (!BufferOrErr) + return createStringError(inconvertibleErrorCode(), "Failed to open %s", + Output.str().c_str()); + std::string Suffix = "_" + getHash((*BufferOrErr)->getBuffer()); + + SmallVector ObjcopyArgs = { + *ObjcopyPath, + Output, + }; + + // Remove the old .llvm.offloading section to prevent further linking. + ObjcopyArgs.emplace_back("--remove-section"); + ObjcopyArgs.emplace_back(".llvm.offloading"); + for (StringRef Prefix : {"omp", "cuda", "hip"}) { + auto Section = (Prefix + "_offloading_entries").str(); + // Rename the offloading entires to make them private to this link unit. + ObjcopyArgs.emplace_back("--rename-section"); + ObjcopyArgs.emplace_back( + Args.MakeArgString(Section + "=" + Section + Suffix)); + + // Rename the __start_ / __stop_ symbols appropriately to iterate over the + // newly renamed section containing the offloading entries. + ObjcopyArgs.emplace_back("--redefine-sym"); + ObjcopyArgs.emplace_back(Args.MakeArgString("__start_" + Section + "=" + + "__start_" + Section + Suffix)); + ObjcopyArgs.emplace_back("--redefine-sym"); + ObjcopyArgs.emplace_back(Args.MakeArgString("__stop_" + Section + "=" + + "__stop_" + Section + Suffix)); + } + + if (Error Err = executeCommands(*ObjcopyPath, ObjcopyArgs)) + return Err; + + return Error::success(); +} + /// Runs the wrapped linker job with the newly created input. Error runLinker(ArrayRef Files, const ArgList &Args) { llvm::TimeTraceScope TimeScope("Execute host linker"); @@ -265,6 +329,10 @@ Error runLinker(ArrayRef Files, const ArgList &Args) { LinkerArgs.push_back(Arg); if (Error Err = executeCommands(LinkerPath, LinkerArgs)) return Err; + + if (Args.hasArg(OPT_relocatable)) + return relocateOffloadSection(Args, ExecutableName); + return Error::success(); } @@ -910,7 +978,8 @@ wrapDeviceImages(ArrayRef> Buffers, case OFK_OpenMP: if (Error Err = offloading::wrapOpenMPBinaries( M, BuffersToWrap, - offloading::getOffloadEntryArray(M, "omp_offloading_entries"))) + offloading::getOffloadEntryArray(M, "omp_offloading_entries"), + /*Suffix=*/"", /*Relocatable=*/Args.hasArg(OPT_relocatable))) return std::move(Err); break; case OFK_Cuda: @@ -1356,12 +1425,6 @@ Expected>> getDeviceInput(const ArgList &Args) { llvm::TimeTraceScope TimeScope("ExtractDeviceCode"); - // If the user is requesting a reloctable link we ignore the device code. The - // actual linker will merge the embedded device code sections so they can be - // linked when the executable is finally created. - if (Args.hasArg(OPT_relocatable)) - return SmallVector>{}; - StringRef Root = Args.getLastArgValue(OPT_sysroot_EQ); SmallVector LibraryPaths; for (const opt::Arg *Arg : Args.filtered(OPT_library_path, OPT_libpath)) diff --git a/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td b/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td index c59cb0fb3e7cbfcf77926886dbff4df9a95a706e..763426570c2a6fe9f1e1ee771121a30c95b4bb4f 100644 --- a/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td +++ b/clang/tools/clang-linker-wrapper/LinkerWrapperOpts.td @@ -127,8 +127,9 @@ def version : Flag<["--", "-"], "version">, Flags<[HelpHidden]>, Alias; def whole_archive : Flag<["--", "-"], "whole-archive">, Flags<[HelpHidden]>; def no_whole_archive : Flag<["--", "-"], "no-whole-archive">, Flags<[HelpHidden]>; -def relocatable : Flag<["--", "-"], "relocatable">, Flags<[HelpHidden]>; -def r : Flag<["-"], "r">, Alias, Flags<[HelpHidden]>; +def relocatable : Flag<["--", "-"], "relocatable">, + HelpText<"Link device code to create a relocatable offloading application">; +def r : Flag<["-"], "r">, Alias; // link.exe-style linker options. def out : Joined<["/", "-", "/?", "-?"], "out:">, Flags<[HelpHidden]>; diff --git a/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp index a6f4c45504fa6d5f6f333d6c0b4389a1b08fc069..b8fc528dbdce07ad44eb6ed9023c30fa300eedf3 100644 --- a/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/SignAnalysisTest.cpp @@ -364,18 +364,17 @@ public: LatticeTransferState State(L, Env); TransferMatchSwitch(Elt, getASTContext(), State); } - bool merge(QualType Type, const Value &Val1, const Environment &Env1, - const Value &Val2, const Environment &Env2, Value &MergedVal, - Environment &MergedEnv) override; + void join(QualType Type, const Value &Val1, const Environment &Env1, + const Value &Val2, const Environment &Env2, Value &MergedVal, + Environment &MergedEnv) override; private: CFGMatchSwitch> TransferMatchSwitch; }; -// Copied from crubit. -BoolValue &mergeBoolValues(BoolValue &Bool1, const Environment &Env1, - BoolValue &Bool2, const Environment &Env2, - Environment &MergedEnv) { +BoolValue &joinBoolValues(BoolValue &Bool1, const Environment &Env1, + BoolValue &Bool2, const Environment &Env2, + Environment &JoinedEnv) { if (&Bool1 == &Bool2) { return Bool1; } @@ -383,41 +382,40 @@ BoolValue &mergeBoolValues(BoolValue &Bool1, const Environment &Env1, auto &B1 = Bool1.formula(); auto &B2 = Bool2.formula(); - auto &A = MergedEnv.arena(); - auto &MergedBool = MergedEnv.makeAtomicBoolValue(); + auto &A = JoinedEnv.arena(); + auto &JoinedBool = JoinedEnv.makeAtomicBoolValue(); // If `Bool1` and `Bool2` is constrained to the same true / false value, - // `MergedBool` can be constrained similarly without needing to consider the - // path taken - this simplifies the flow condition tracked in `MergedEnv`. + // `JoinedBool` can be constrained similarly without needing to consider the + // path taken - this simplifies the flow condition tracked in `JoinedEnv`. // Otherwise, information about which path was taken is used to associate - // `MergedBool` with `Bool1` and `Bool2`. + // `JoinedBool` with `Bool1` and `Bool2`. if (Env1.proves(B1) && Env2.proves(B2)) { - MergedEnv.assume(MergedBool.formula()); + JoinedEnv.assume(JoinedBool.formula()); } else if (Env1.proves(A.makeNot(B1)) && Env2.proves(A.makeNot(B2))) { - MergedEnv.assume(A.makeNot(MergedBool.formula())); + JoinedEnv.assume(A.makeNot(JoinedBool.formula())); } - return MergedBool; + return JoinedBool; } -bool SignPropagationAnalysis::merge(QualType Type, const Value &Val1, - const Environment &Env1, const Value &Val2, - const Environment &Env2, Value &MergedVal, - Environment &MergedEnv) { +void SignPropagationAnalysis::join(QualType Type, const Value &Val1, + const Environment &Env1, const Value &Val2, + const Environment &Env2, Value &JoinedVal, + Environment &JoinedEnv) { if (!Type->isIntegerType()) - return false; + return; SignProperties Ps1 = getSignProperties(Val1, Env1); SignProperties Ps2 = getSignProperties(Val2, Env2); if (!Ps1.Neg || !Ps2.Neg) - return false; - BoolValue &MergedNeg = - mergeBoolValues(*Ps1.Neg, Env1, *Ps2.Neg, Env2, MergedEnv); - BoolValue &MergedZero = - mergeBoolValues(*Ps1.Zero, Env1, *Ps2.Zero, Env2, MergedEnv); - BoolValue &MergedPos = - mergeBoolValues(*Ps1.Pos, Env1, *Ps2.Pos, Env2, MergedEnv); - setSignProperties(MergedVal, - SignProperties{&MergedNeg, &MergedZero, &MergedPos}); - return true; + return; + BoolValue &JoinedNeg = + joinBoolValues(*Ps1.Neg, Env1, *Ps2.Neg, Env2, JoinedEnv); + BoolValue &JoinedZero = + joinBoolValues(*Ps1.Zero, Env1, *Ps2.Zero, Env2, JoinedEnv); + BoolValue &JoinedPos = + joinBoolValues(*Ps1.Pos, Env1, *Ps2.Pos, Env2, JoinedEnv); + setSignProperties(JoinedVal, + SignProperties{&JoinedNeg, &JoinedZero, &JoinedPos}); } template diff --git a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp index 466d33358fd388bd415a18ab5f610f7961343f02..3bca9cced8d6f75cd852f210548243de80402b2b 100644 --- a/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TypeErasedDataflowAnalysisTest.cpp @@ -672,26 +672,23 @@ public: : ComparisonResult::Different; } - bool merge(QualType Type, const Value &Val1, const Environment &Env1, - const Value &Val2, const Environment &Env2, Value &MergedVal, - Environment &MergedEnv) override { - // Nothing to say about a value that is not a pointer. + void join(QualType Type, const Value &Val1, const Environment &Env1, + const Value &Val2, const Environment &Env2, Value &JoinedVal, + Environment &JoinedEnv) override { + // Nothing to say about a value that is not a pointer... if (!Type->isPointerType()) - return false; + return; + // ... or, a pointer without the `is_null` property. auto *IsNull1 = cast_or_null(Val1.getProperty("is_null")); - if (IsNull1 == nullptr) - return false; - auto *IsNull2 = cast_or_null(Val2.getProperty("is_null")); - if (IsNull2 == nullptr) - return false; + if (IsNull1 == nullptr || IsNull2 == nullptr) + return; if (IsNull1 == IsNull2) - MergedVal.setProperty("is_null", *IsNull1); + JoinedVal.setProperty("is_null", *IsNull1); else - MergedVal.setProperty("is_null", MergedEnv.makeTopBoolValue()); - return true; + JoinedVal.setProperty("is_null", JoinedEnv.makeTopBoolValue()); } }; @@ -1176,7 +1173,7 @@ TEST_F(FlowConditionTest, Join) { // Note: currently, arbitrary function calls are uninterpreted, so the test // exercises this case. If and when we change that, this test will not add to // coverage (although it may still test a valuable case). -TEST_F(FlowConditionTest, OpaqueFlowConditionMergesToOpaqueBool) { +TEST_F(FlowConditionTest, OpaqueFlowConditionJoinsToOpaqueBool) { std::string Code = R"( bool foo(); @@ -1211,7 +1208,7 @@ TEST_F(FlowConditionTest, OpaqueFlowConditionMergesToOpaqueBool) { // the first instance), so the test exercises this case. If and when we change // that, this test will not add to coverage (although it may still test a // valuable case). -TEST_F(FlowConditionTest, OpaqueFieldFlowConditionMergesToOpaqueBool) { +TEST_F(FlowConditionTest, OpaqueFieldFlowConditionJoinsToOpaqueBool) { std::string Code = R"( struct Rec { Rec* Next; @@ -1249,7 +1246,7 @@ TEST_F(FlowConditionTest, OpaqueFieldFlowConditionMergesToOpaqueBool) { // condition is not meaningfully interpreted. Adds to above by nesting the // interestnig case inside a normal branch. This protects against degenerate // solutions which only test for empty flow conditions, for example. -TEST_F(FlowConditionTest, OpaqueFlowConditionInsideBranchMergesToOpaqueBool) { +TEST_F(FlowConditionTest, OpaqueFlowConditionInsideBranchJoinsToOpaqueBool) { std::string Code = R"( bool foo(); diff --git a/clang/unittests/Format/ConfigParseTest.cpp b/clang/unittests/Format/ConfigParseTest.cpp index 3f1fc893516947b0059d1c7dc652a2d95636a11c..7493b0a4450f9b05b530b6d2d1bf640b4ca8b29b 100644 --- a/clang/unittests/Format/ConfigParseTest.cpp +++ b/clang/unittests/Format/ConfigParseTest.cpp @@ -695,6 +695,8 @@ TEST(ConfigParseTest, ParsesConfiguration) { FormatStyle::RTBS_TopLevelDefinitions); Style.AlwaysBreakTemplateDeclarations = FormatStyle::BTDS_Yes; + CHECK_PARSE("AlwaysBreakTemplateDeclarations: Leave", + AlwaysBreakTemplateDeclarations, FormatStyle::BTDS_Leave); CHECK_PARSE("AlwaysBreakTemplateDeclarations: No", AlwaysBreakTemplateDeclarations, FormatStyle::BTDS_No); CHECK_PARSE("AlwaysBreakTemplateDeclarations: MultiLine", diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 2f7febd49de42aa3303500db4877659a879fe048..b1a2247bb85d6f180dd6963883587d0f7e3f9ea5 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -10697,6 +10697,74 @@ TEST_F(FormatTest, WrapsTemplateDeclarations) { verifyFormat("template void\nfoo(aaaaaaaaaaaaaaaaaaaaaaaaaa " "bbbbbbbbbbbbbbbbbbbb) {}", NeverBreak); + + auto Style = getLLVMStyle(); + Style.AlwaysBreakTemplateDeclarations = FormatStyle::BTDS_Leave; + + verifyNoChange("template \n" + "class C {};", + Style); + verifyFormat("template class C {};", Style); + + verifyNoChange("template \n" + "void f();", + Style); + verifyFormat("template void f();", Style); + + verifyNoChange("template \n" + "void f() {}", + Style); + verifyFormat("template void f() {}", Style); + + verifyNoChange("template \n" + "// T can be A, B or C.\n" + "struct C {};", + Style); + verifyFormat("template // T can be A, B or C.\n" + "struct C {};", + Style); + + verifyNoChange("template \n" + "C(T) noexcept;", + Style); + verifyFormat("template C(T) noexcept;", Style); + + verifyNoChange("template \n" + "class A {\n" + "public:\n" + " E *f();\n" + "};", + Style); + verifyFormat("template class A {\n" + "public:\n" + " E *f();\n" + "};", + Style); + + verifyNoChange("template \n" + "constexpr int simple(int) {\n" + " char c;\n" + " return 1;\n" + "}", + Style); + verifyFormat("template constexpr int simple(int) {\n" + " char c;\n" + " return 1;\n" + "}", + Style); + + Style.RequiresClausePosition = FormatStyle::RCPS_WithPreceding; + verifyNoChange("template \n" + "requires(x > 1)\n" + "constexpr int with_req(int) {\n" + " return 1;\n" + "}", + Style); + verifyFormat("template requires(x > 1)\n" + "constexpr int with_req(int) {\n" + " return 1;\n" + "}", + Style); } TEST_F(FormatTest, WrapsTemplateDeclarationsWithComments) { @@ -24147,6 +24215,15 @@ TEST_F(FormatTest, C11Generic) { " double _Complex: dc,\n" " long double _Complex: ldc)"); + verifyFormat("while (_Generic(x, //\n" + " long: x)(x) > x) {\n" + "}"); + verifyFormat("while (_Generic(x, //\n" + " long: x)(x)) {\n" + "}"); + verifyFormat("x(_Generic(x, //\n" + " long: x)(x));"); + FormatStyle Style = getLLVMStyle(); Style.ColumnLimit = 40; verifyFormat("#define LIMIT_MAX(T) \\\n" diff --git a/clang/unittests/Format/FormatTestComments.cpp b/clang/unittests/Format/FormatTestComments.cpp index c249f4d9333fd079744a0cc22b26af369d641f2c..d705cf34d8af029e1a211e6e9d2ff92b5d884cdb 100644 --- a/clang/unittests/Format/FormatTestComments.cpp +++ b/clang/unittests/Format/FormatTestComments.cpp @@ -1909,6 +1909,14 @@ TEST_F(FormatTestComments, ReflowsComments) { "// @param arg", getLLVMStyleWithColumns(20))); + // Don't reflow lines starting with '\'. + verifyFormat("// long long long\n" + "// long\n" + "// \\param arg", + "// long long long long\n" + "// \\param arg", + getLLVMStyleWithColumns(20)); + // Don't reflow lines starting with 'TODO'. EXPECT_EQ("// long long long\n" "// long\n" diff --git a/clang/unittests/Format/SortIncludesTest.cpp b/clang/unittests/Format/SortIncludesTest.cpp index ec142e03b12854e712ea8e85a3a620cec9dd7d14..772eb53806b4b115add911062a5d2451d09c9fe6 100644 --- a/clang/unittests/Format/SortIncludesTest.cpp +++ b/clang/unittests/Format/SortIncludesTest.cpp @@ -976,6 +976,112 @@ TEST_F(SortIncludesTest, EXPECT_EQ(Code, sort(Code, "input.h", 0)); } +TEST_F(SortIncludesTest, MainIncludeChar) { + std::string Code = "#include \n" + "#include \"quote/input.h\"\n" + "#include \n"; + + // Default behavior + EXPECT_EQ("#include \"quote/input.h\"\n" + "#include \n" + "#include \n", + sort(Code, "input.cc", 1)); + + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Quote; + EXPECT_EQ("#include \"quote/input.h\"\n" + "#include \n" + "#include \n", + sort(Code, "input.cc", 1)); + + Style.MainIncludeChar = tooling::IncludeStyle::MICD_AngleBracket; + EXPECT_EQ("#include \n" + "#include \"quote/input.h\"\n" + "#include \n", + sort(Code, "input.cc", 1)); +} + +TEST_F(SortIncludesTest, MainIncludeCharAnyPickQuote) { + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Any; + EXPECT_EQ("#include \"input.h\"\n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \"input.h\"\n" + "#include \n", + "input.cc", 1)); +} + +TEST_F(SortIncludesTest, MainIncludeCharAnyPickAngleBracket) { + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Any; + EXPECT_EQ("#include \n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \n" + "#include \n", + "input.cc", 1)); +} + +TEST_F(SortIncludesTest, MainIncludeCharQuoteAndRegroup) { + Style.IncludeCategories = { + {"lib-a", 1, 0, false}, {"lib-b", 2, 0, false}, {"lib-c", 3, 0, false}}; + Style.IncludeBlocks = tooling::IncludeStyle::IBS_Regroup; + Style.MainIncludeChar = tooling::IncludeStyle::MICD_Quote; + + EXPECT_EQ("#include \"lib-b/input.h\"\n" + "\n" + "#include \n" + "#include \n" + "#include \n" + "\n" + "#include \n" + "#include \n" + "\n" + "#include \n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \n" + "#include \n" + "#include \n" + "#include \"lib-b/input.h\"\n" + "#include \n" + "#include \n" + "#include \n" + "#include \n", + "input.cc")); +} + +TEST_F(SortIncludesTest, MainIncludeCharAngleBracketAndRegroup) { + Style.IncludeCategories = { + {"lib-a", 1, 0, false}, {"lib-b", 2, 0, false}, {"lib-c", 3, 0, false}}; + Style.IncludeBlocks = tooling::IncludeStyle::IBS_Regroup; + Style.MainIncludeChar = tooling::IncludeStyle::MICD_AngleBracket; + + EXPECT_EQ("#include \n" + "\n" + "#include \n" + "#include \n" + "\n" + "#include \"lib-b/input.h\"\n" + "#include \n" + "#include \n" + "\n" + "#include \n" + "#include \n" + "#include \n", + sort("#include \n" + "#include \n" + "#include \n" + "#include \n" + "#include \"lib-b/input.h\"\n" + "#include \n" + "#include \n" + "#include \n" + "#include \n", + "input.cc")); +} + TEST_F(SortIncludesTest, DoNotRegroupGroupsInGoogleObjCStyle) { FmtStyle = getGoogleStyle(FormatStyle::LK_ObjC); diff --git a/compiler-rt/lib/asan/asan_descriptions.cpp b/compiler-rt/lib/asan/asan_descriptions.cpp index ef6f3e0a096f8287a1c9593a995ce78ba64a05dc..05a277cfa0a845b6ecb130c6ec79de340b81113f 100644 --- a/compiler-rt/lib/asan/asan_descriptions.cpp +++ b/compiler-rt/lib/asan/asan_descriptions.cpp @@ -245,11 +245,11 @@ static void PrintAccessAndVarIntersection(const StackVarDescr &var, uptr addr, InternalScopedString str; str.AppendF(" [%zd, %zd)", var.beg, var_end); // Render variable name. - str.AppendF(" '"); + str.Append(" '"); for (uptr i = 0; i < var.name_len; ++i) { str.AppendF("%c", var.name_pos[i]); } - str.AppendF("'"); + str.Append("'"); if (var.line > 0) { str.AppendF(" (line %zd)", var.line); } @@ -260,7 +260,7 @@ static void PrintAccessAndVarIntersection(const StackVarDescr &var, uptr addr, str.AppendF("%s <== Memory access at offset %zd %s this variable%s\n", d.Location(), addr, pos_descr, d.Default()); } else { - str.AppendF("\n"); + str.Append("\n"); } Printf("%s", str.data()); } diff --git a/compiler-rt/lib/hwasan/hwasan_report.cpp b/compiler-rt/lib/hwasan/hwasan_report.cpp index 12a4fa47f215192176b58f88299a1fe1fcdd8a39..c3d260d1a61fa23115ab5f28672eea66e95a091c 100644 --- a/compiler-rt/lib/hwasan/hwasan_report.cpp +++ b/compiler-rt/lib/hwasan/hwasan_report.cpp @@ -388,7 +388,7 @@ static void PrintTagInfoAroundAddr(uptr addr, uptr num_rows, print_tag(s, row + i); s.Append(row + i == addr ? "]" : " "); } - s.AppendF("\n"); + s.Append("\n"); } } @@ -418,10 +418,10 @@ static void PrintTagsAroundAddr(uptr addr, GetTag get_tag, tag_t short_tag = get_short_tag(tag_addr); s.AppendF("%02x", short_tag); } else { - s.AppendF(".."); + s.Append(".."); } }); - s.AppendF( + s.Append( "See " "https://clang.llvm.org/docs/" "HardwareAssistedAddressSanitizerDesign.html#short-granules for a " @@ -947,16 +947,16 @@ TailOverwrittenReport::~TailOverwrittenReport() { InternalScopedString s; u8 *tail = tail_copy; - s.AppendF("Tail contains: "); - for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.AppendF(".. "); + s.Append("Tail contains: "); + for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.Append(".. "); for (uptr i = 0; i < tail_size; i++) s.AppendF("%02x ", tail[i]); - s.AppendF("\n"); - s.AppendF("Expected: "); - for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.AppendF(".. "); + s.Append("\n"); + s.Append("Expected: "); + for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.Append(".. "); for (uptr i = 0; i < tail_size; i++) s.AppendF("%02x ", actual_expected[i]); - s.AppendF("\n"); - s.AppendF(" "); - for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.AppendF(" "); + s.Append("\n"); + s.Append(" "); + for (uptr i = 0; i < kShadowAlignment - tail_size; i++) s.Append(" "); for (uptr i = 0; i < tail_size; i++) s.AppendF("%s ", actual_expected[i] != tail[i] ? "^^" : " "); diff --git a/compiler-rt/lib/memprof/memprof_allocator.cpp b/compiler-rt/lib/memprof/memprof_allocator.cpp index af46ffdb248e28bbd4aa092d5fdfda676367b79e..35e941228525a8c9ca4ece4604c63c993249b97a 100644 --- a/compiler-rt/lib/memprof/memprof_allocator.cpp +++ b/compiler-rt/lib/memprof/memprof_allocator.cpp @@ -515,8 +515,7 @@ struct Allocator { return ptr; } - void CommitBack(MemprofThreadLocalMallocStorage *ms, - BufferedStackTrace *stack) { + void CommitBack(MemprofThreadLocalMallocStorage *ms) { AllocatorCache *ac = GetAllocatorCache(ms); allocator.SwallowCache(ac); } @@ -561,7 +560,7 @@ struct Allocator { return reinterpret_cast(p - kChunkHeaderSize)->UsedSize(); } - void Purge(BufferedStackTrace *stack) { allocator.ForceReleaseToOS(); } + void Purge() { allocator.ForceReleaseToOS(); } void PrintStats() { allocator.PrintStats(); } @@ -583,8 +582,7 @@ static MemprofAllocator &get_allocator() { return instance.allocator; } void InitializeAllocator() { instance.InitLinkerInitialized(); } void MemprofThreadLocalMallocStorage::CommitBack() { - GET_STACK_TRACE_MALLOC; - instance.CommitBack(this, &stack); + instance.CommitBack(this); } void PrintInternalAllocatorStats() { instance.PrintStats(); } @@ -699,7 +697,7 @@ static const void *memprof_malloc_begin(const void *p) { return (const void *)m->Beg(); } -uptr memprof_malloc_usable_size(const void *ptr, uptr pc, uptr bp) { +uptr memprof_malloc_usable_size(const void *ptr) { if (!ptr) return 0; uptr usable_size = instance.AllocationSize(reinterpret_cast(ptr)); @@ -714,7 +712,7 @@ using namespace __memprof; uptr __sanitizer_get_estimated_allocated_size(uptr size) { return size; } int __sanitizer_get_ownership(const void *p) { - return memprof_malloc_usable_size(p, 0, 0) != 0; + return memprof_malloc_usable_size(p) != 0; } const void *__sanitizer_get_allocated_begin(const void *p) { @@ -722,7 +720,7 @@ const void *__sanitizer_get_allocated_begin(const void *p) { } uptr __sanitizer_get_allocated_size(const void *p) { - return memprof_malloc_usable_size(p, 0, 0); + return memprof_malloc_usable_size(p); } uptr __sanitizer_get_allocated_size_fast(const void *p) { @@ -732,6 +730,8 @@ uptr __sanitizer_get_allocated_size_fast(const void *p) { return ret; } +void __sanitizer_purge_allocator() { instance.Purge(); } + int __memprof_profile_dump() { instance.FinishAndWrite(); // In the future we may want to return non-zero if there are any errors diff --git a/compiler-rt/lib/memprof/memprof_allocator.h b/compiler-rt/lib/memprof/memprof_allocator.h index 14c61c7325e3f0394be50e2e6ad5d9431cf78678..f583cee020e4ffd866e587d9dc01e9be88b9b5a2 100644 --- a/compiler-rt/lib/memprof/memprof_allocator.h +++ b/compiler-rt/lib/memprof/memprof_allocator.h @@ -99,7 +99,7 @@ void *memprof_aligned_alloc(uptr alignment, uptr size, BufferedStackTrace *stack); int memprof_posix_memalign(void **memptr, uptr alignment, uptr size, BufferedStackTrace *stack); -uptr memprof_malloc_usable_size(const void *ptr, uptr pc, uptr bp); +uptr memprof_malloc_usable_size(const void *ptr); void PrintInternalAllocatorStats(); diff --git a/compiler-rt/lib/memprof/memprof_descriptions.cpp b/compiler-rt/lib/memprof/memprof_descriptions.cpp index 48b74b6bc87fb530e7ce579bf11707f00ea47ff0..4fbe2943e65391e0c0502cade8f1cca7a84f30a9 100644 --- a/compiler-rt/lib/memprof/memprof_descriptions.cpp +++ b/compiler-rt/lib/memprof/memprof_descriptions.cpp @@ -51,7 +51,7 @@ void DescribeThread(MemprofThreadContext *context) { InternalScopedString str; str.AppendF("Thread %s", MemprofThreadIdAndName(context).c_str()); if (context->parent_tid == kInvalidTid) { - str.AppendF(" created by unknown thread\n"); + str.Append(" created by unknown thread\n"); Printf("%s", str.data()); return; } diff --git a/compiler-rt/lib/memprof/memprof_interceptors.cpp b/compiler-rt/lib/memprof/memprof_interceptors.cpp index 8925ec5bbaa3728204446aacce95b63948eb4aea..a267f6d3d6717b0c62a7473165087ff8181d4ccd 100644 --- a/compiler-rt/lib/memprof/memprof_interceptors.cpp +++ b/compiler-rt/lib/memprof/memprof_interceptors.cpp @@ -163,7 +163,7 @@ INTERCEPTOR(int, pthread_create, void *thread, void *attr, } INTERCEPTOR(int, pthread_join, void *t, void **arg) { - return real_pthread_join(t, arg); + return REAL(pthread_join)(t, arg); } DEFINE_REAL_PTHREAD_FUNCTIONS diff --git a/compiler-rt/lib/memprof/memprof_internal.h b/compiler-rt/lib/memprof/memprof_internal.h index 990e62ce1a55d345032faac0455154349d3f1b51..423ffac5ef73a668f3908a5071b307971edb54a2 100644 --- a/compiler-rt/lib/memprof/memprof_internal.h +++ b/compiler-rt/lib/memprof/memprof_internal.h @@ -20,10 +20,6 @@ #include "sanitizer_common/sanitizer_libc.h" #include "sanitizer_common/sanitizer_stacktrace.h" -#if __has_feature(address_sanitizer) || defined(__SANITIZE_ADDRESS__) -#error "The MemProfiler run-time should not be instrumented by MemProfiler" -#endif - // Build-time configuration options. // If set, memprof will intercept C++ exception api call(s). diff --git a/compiler-rt/lib/memprof/memprof_malloc_linux.cpp b/compiler-rt/lib/memprof/memprof_malloc_linux.cpp index ef753fcaa4addd8f2dfbd8c3055817be6e70678c..aba6295a4a049c77ef76623d65d635d02c52bf63 100644 --- a/compiler-rt/lib/memprof/memprof_malloc_linux.cpp +++ b/compiler-rt/lib/memprof/memprof_malloc_linux.cpp @@ -104,9 +104,7 @@ INTERCEPTOR(void *, aligned_alloc, uptr boundary, uptr size) { #endif // SANITIZER_INTERCEPT_ALIGNED_ALLOC INTERCEPTOR(uptr, malloc_usable_size, void *ptr) { - GET_CURRENT_PC_BP_SP; - (void)sp; - return memprof_malloc_usable_size(ptr, pc, bp); + return memprof_malloc_usable_size(ptr); } #if SANITIZER_INTERCEPT_MALLOPT_AND_MALLINFO diff --git a/compiler-rt/lib/memprof/memprof_mapping.h b/compiler-rt/lib/memprof/memprof_mapping.h index ba05b88db3070784052c6d762f492723189fb2cd..1cc0836834cdf07bff71f31fb73815ba428cdccf 100644 --- a/compiler-rt/lib/memprof/memprof_mapping.h +++ b/compiler-rt/lib/memprof/memprof_mapping.h @@ -29,8 +29,6 @@ extern uptr kHighMemEnd; // Initialized in __memprof_init. } // namespace __memprof -#define SHADOW_ENTRY_SIZE 8 - // Size of memory block mapped to a single shadow location #define MEM_GRANULARITY 64ULL @@ -39,6 +37,8 @@ extern uptr kHighMemEnd; // Initialized in __memprof_init. #define MEM_TO_SHADOW(mem) \ ((((mem) & SHADOW_MASK) >> SHADOW_SCALE) + (SHADOW_OFFSET)) +#define SHADOW_ENTRY_SIZE (MEM_GRANULARITY >> SHADOW_SCALE) + #define kLowMemBeg 0 #define kLowMemEnd (SHADOW_OFFSET ? SHADOW_OFFSET - 1 : 0) diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp index 561eae9ab7806582bf6cde2b5824344f3645e14b..1a0e00d5d5af21d08926d4219fb7c23b3e072e8f 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_libcdep.cpp @@ -63,7 +63,7 @@ class StackTraceTextPrinter { if (dedup_frames_-- > 0) { if (dedup_token_->length()) - dedup_token_->AppendF("--"); + dedup_token_->Append("--"); if (stack->info.function) dedup_token_->Append(stack->info.function); } @@ -99,7 +99,7 @@ void StackTrace::PrintTo(InternalScopedString *output) const { output, &dedup_token); if (trace == nullptr || size == 0) { - output->AppendF(" \n\n"); + output->Append(" \n\n"); return; } @@ -111,7 +111,7 @@ void StackTrace::PrintTo(InternalScopedString *output) const { } // Always add a trailing empty line after stack trace. - output->AppendF("\n"); + output->Append("\n"); // Append deduplication token, if non-empty. if (dedup_token.length()) @@ -198,7 +198,7 @@ void __sanitizer_symbolize_pc(uptr pc, const char *fmt, char *out_buf, StackTraceTextPrinter printer(fmt, '\0', &output, nullptr); if (!printer.ProcessAddressFrames(pc)) { output.clear(); - output.AppendF(""); + output.Append(""); } CopyStringToBuffer(output, out_buf, out_buf_size); } diff --git a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp index 748d832ccc211d0abf1f2e463cb25ffa3ada117e..b23796fccf6e3ee85b770b5039074b77f5927946 100644 --- a/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp +++ b/compiler-rt/lib/sanitizer_common/sanitizer_stacktrace_printer.cpp @@ -152,12 +152,12 @@ static void MaybeBuildIdToBuffer(const AddressInfo &info, bool PrefixSpace, InternalScopedString *buffer) { if (info.uuid_size) { if (PrefixSpace) - buffer->AppendF(" "); - buffer->AppendF("(BuildId: "); + buffer->Append(" "); + buffer->Append("(BuildId: "); for (uptr i = 0; i < info.uuid_size; ++i) { buffer->AppendF("%02x", info.uuid[i]); } - buffer->AppendF(")"); + buffer->Append(")"); } } @@ -249,7 +249,7 @@ void FormattedStackTracePrinter::RenderFrame(InternalScopedString *buffer, MaybeBuildIdToBuffer(*info, /*PrefixSpace=*/true, buffer); #endif } else { - buffer->AppendF("()"); + buffer->Append("()"); } break; case 'M': @@ -339,7 +339,7 @@ void StackTracePrinter::RenderSourceLocation(InternalScopedString *buffer, buffer->AppendF("%s(%d", StripPathPrefix(file, strip_path_prefix), line); if (column > 0) buffer->AppendF(",%d", column); - buffer->AppendF(")"); + buffer->Append(")"); return; } diff --git a/flang/include/flang/Lower/ConvertCall.h b/flang/include/flang/Lower/ConvertCall.h index f8171236bb39d9951d902d94ce38f93dbfd50087..bc082907e61760ad538a2e9567d1aa9c689933e3 100644 --- a/flang/include/flang/Lower/ConvertCall.h +++ b/flang/include/flang/Lower/ConvertCall.h @@ -30,7 +30,9 @@ namespace Fortran::lower { /// link to internal procedures. /// \p isElemental must be set to true if elemental call is being produced. /// It is only used for HLFIR. -fir::ExtendedValue genCallOpAndResult( +/// The returned boolean indicates if finalization has been emitted in +/// \p stmtCtx for the result. +std::pair genCallOpAndResult( mlir::Location loc, Fortran::lower::AbstractConverter &converter, Fortran::lower::SymMap &symMap, Fortran::lower::StatementContext &stmtCtx, Fortran::lower::CallerInterface &caller, mlir::FunctionType callSiteType, diff --git a/flang/include/flang/Optimizer/Builder/MutableBox.h b/flang/include/flang/Optimizer/Builder/MutableBox.h index 8cd8f28dd9a10ebc6234db73c7b24975996f4d33..0573d2b238c20f67d9495f8133c519095ffb5738 100644 --- a/flang/include/flang/Optimizer/Builder/MutableBox.h +++ b/flang/include/flang/Optimizer/Builder/MutableBox.h @@ -150,7 +150,8 @@ void syncMutableBoxFromIRBox(fir::FirOpBuilder &builder, mlir::Location loc, fir::ExtendedValue genMutableBoxRead(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, - bool mayBePolymorphic = true); + bool mayBePolymorphic = true, + bool preserveLowerBounds = true); /// Returns the fir.ref> of a MutableBoxValue filled with the current /// association / allocation properties. If the fir.ref already exists diff --git a/flang/include/flang/Optimizer/Dialect/FIRDialect.h b/flang/include/flang/Optimizer/Dialect/FIRDialect.h index e8bf9f0cf503b2e554aa15c37ee81c1a26ba404f..440fe77059a4a7d1b8dffe694e66f3146f90292d 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRDialect.h +++ b/flang/include/flang/Optimizer/Dialect/FIRDialect.h @@ -67,6 +67,9 @@ bool canLegallyInline(mlir::Operation *op, mlir::Region *reg, bool, mlir::IRMapping &map); bool canLegallyInline(mlir::Operation *, mlir::Operation *, bool); +// Register the FIRInlinerInterface to FIROpsDialect +void addFIRInlinerExtension(mlir::DialectRegistry ®istry); + } // namespace fir #endif // FORTRAN_OPTIMIZER_DIALECT_FIRDIALECT_H diff --git a/flang/include/flang/Optimizer/Support/InitFIR.h b/flang/include/flang/Optimizer/Support/InitFIR.h index b5c41699205f42f2c84feacc4c3eeda161a499f5..f376840afd842a0c576441e68bced2a57aa4e837 100644 --- a/flang/include/flang/Optimizer/Support/InitFIR.h +++ b/flang/include/flang/Optimizer/Support/InitFIR.h @@ -53,6 +53,13 @@ inline void registerDialects(mlir::DialectRegistry ®istry) { registry.insert(); } +// Register FIR Extensions +inline void addFIRExtensions(mlir::DialectRegistry ®istry, + bool addFIRInlinerInterface = true) { + if (addFIRInlinerInterface) + addFIRInlinerExtension(registry); +} + inline void loadNonCodegenDialects(mlir::MLIRContext &context) { mlir::DialectRegistry registry; registerNonCodegenDialects(registry); diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index 18bc1689c854730c82e6d1d81735f7160b78f072..44e80e946ed8322111e2761f8dce747a3e370a30 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -786,6 +786,10 @@ void CodeGenAction::generateLLVMIR() { llvm::OptimizationLevel level = mapToLevel(opts); fir::support::loadDialects(*mlirCtx); + mlir::DialectRegistry registry; + fir::support::registerNonCodegenDialects(registry); + fir::support::addFIRExtensions(registry); + mlirCtx->appendDialectRegistry(registry); fir::support::registerLLVMTranslation(*mlirCtx); // Set-up the MLIR pass manager diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp index bb8fd2e945f4374baa9015c5206ed7c5ec31f167..f60cdbb690e7cd4f8f1d098574e57214e6396963 100644 --- a/flang/lib/Lower/ConvertCall.cpp +++ b/flang/lib/Lower/ConvertCall.cpp @@ -42,6 +42,8 @@ static llvm::cl::opt useHlfirIntrinsicOps( llvm::cl::desc("Lower via HLFIR transformational intrinsic operations such " "as hlfir.sum")); +static constexpr char tempResultName[] = ".tmp.func_result"; + /// Helper to package a Value and its properties into an ExtendedValue. static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, llvm::ArrayRef extents, @@ -147,7 +149,7 @@ static bool mustCastFuncOpToCopeWithImplicitInterfaceMismatch( return false; } -fir::ExtendedValue Fortran::lower::genCallOpAndResult( +std::pair Fortran::lower::genCallOpAndResult( mlir::Location loc, Fortran::lower::AbstractConverter &converter, Fortran::lower::SymMap &symMap, Fortran::lower::StatementContext &stmtCtx, Fortran::lower::CallerInterface &caller, mlir::FunctionType callSiteType, @@ -478,6 +480,7 @@ fir::ExtendedValue Fortran::lower::genCallOpAndResult( [](const auto &) {}); // 7.5.6.3 point 5. Derived-type finalization for nonpointer function. + bool resultIsFinalized = false; // Check if the derived-type is finalizable if it is a monomorphic // derived-type. // For polymorphic and unlimited polymorphic enities call the runtime @@ -499,6 +502,7 @@ fir::ExtendedValue Fortran::lower::genCallOpAndResult( fir::runtime::genDerivedTypeDestroy(*bldr, loc, fir::getBase(*allocatedResult)); }); + resultIsFinalized = true; } else { const Fortran::semantics::DerivedTypeSpec &typeSpec = retTy->GetDerivedTypeSpec(); @@ -513,14 +517,17 @@ fir::ExtendedValue Fortran::lower::genCallOpAndResult( mlir::Value box = bldr->createBox(loc, *allocatedResult); fir::runtime::genDerivedTypeDestroy(*bldr, loc, box); }); + resultIsFinalized = true; } } } - return *allocatedResult; + return {*allocatedResult, resultIsFinalized}; } + // subroutine call if (!resultType) - return mlir::Value{}; // subroutine call + return {fir::ExtendedValue{mlir::Value{}}, /*resultIsFinalized=*/false}; + // For now, Fortran return values are implemented with a single MLIR // function return value. assert(callNumResults == 1 && "Expected exactly one result in FUNCTION call"); @@ -533,10 +540,10 @@ fir::ExtendedValue Fortran::lower::genCallOpAndResult( funcType.getResults()[0].dyn_cast(); mlir::Value len = builder.createIntegerConstant( loc, builder.getCharacterLengthType(), charTy.getLen()); - return fir::CharBoxValue{callResult, len}; + return {fir::CharBoxValue{callResult, len}, /*resultIsFinalized=*/false}; } - return callResult; + return {callResult, /*resultIsFinalized=*/false}; } static hlfir::EntityWithAttributes genStmtFunctionRef( @@ -1389,7 +1396,7 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, // Prepare lowered arguments according to the interface // and map the lowered values to the dummy // arguments. - fir::ExtendedValue result = Fortran::lower::genCallOpAndResult( + auto [result, resultIsFinalized] = Fortran::lower::genCallOpAndResult( loc, callContext.converter, callContext.symMap, callContext.stmtCtx, caller, callSiteType, callContext.resultType, callContext.isElementalProcWithArrayArgs()); @@ -1404,24 +1411,43 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, if (!fir::getBase(result)) return std::nullopt; // subroutine call. - hlfir::Entity resultEntity = - extendedValueToHlfirEntity(loc, builder, result, ".tmp.func_result"); + if (fir::isPointerType(fir::getBase(result).getType())) + return extendedValueToHlfirEntity(loc, builder, result, tempResultName); - if (!fir::isPointerType(fir::getBase(result).getType())) { + if (!resultIsFinalized) { + hlfir::Entity resultEntity = + extendedValueToHlfirEntity(loc, builder, result, tempResultName); resultEntity = loadTrivialScalar(loc, builder, resultEntity); - if (resultEntity.isVariable()) { - // Function result must not be freed, since it is allocated on the stack. - // Note that in non-elemental case, genCallOpAndResult() - // is responsible for establishing the clean-up that destroys - // the derived type result or deallocates its components - // without finalization. + // If the result has no finalization, it can be moved into an expression. + // In such case, the expression should not be freed after its use since + // the result is stack allocated or deallocation (for allocatable results) + // was already inserted in genCallOpAndResult. auto asExpr = builder.create( loc, resultEntity, /*mustFree=*/builder.createBool(loc, false)); - resultEntity = hlfir::EntityWithAttributes{asExpr.getResult()}; + return hlfir::EntityWithAttributes{asExpr.getResult()}; } + return hlfir::EntityWithAttributes{resultEntity}; } - return hlfir::EntityWithAttributes{resultEntity}; + // If the result has finalization, it cannot be moved because use of its + // value have been created in the statement context and may be emitted + // after the hlfir.expr destroy, so the result is kept as a variable in + // HLFIR. This may lead to copies when passing the result to an argument + // with VALUE, and this do not convey the fact that the result will not + // change, but is correct, and using hlfir.expr without the move would + // trigger a copy that may be avoided. + + // Load allocatable results before emitting the hlfir.declare and drop its + // lower bounds: this is not a variable From the Fortran point of view, so + // the lower bounds are ones when inquired on the caller side. + const auto *allocatable = result.getBoxOf(); + fir::ExtendedValue loadedResult = + allocatable + ? fir::factory::genMutableBoxRead(builder, loc, *allocatable, + /*mayBePolymorphic=*/true, + /*preserveLowerBounds=*/false) + : result; + return extendedValueToHlfirEntity(loc, builder, loadedResult, tempResultName); } /// Create an optional dummy argument value from an entity that may be diff --git a/flang/lib/Lower/ConvertExpr.cpp b/flang/lib/Lower/ConvertExpr.cpp index a2b28aa2e049128946c67a8ac2cd6a92e0a2f810..d157db2cde49612e3049a266bb40b3bd9b6aa83d 100644 --- a/flang/lib/Lower/ConvertExpr.cpp +++ b/flang/lib/Lower/ConvertExpr.cpp @@ -2846,8 +2846,10 @@ public: } } - ExtValue result = Fortran::lower::genCallOpAndResult( - loc, converter, symMap, stmtCtx, caller, callSiteType, resultType); + ExtValue result = + Fortran::lower::genCallOpAndResult(loc, converter, symMap, stmtCtx, + caller, callSiteType, resultType) + .first; // Sync pointers and allocatables that may have been modified during the // call. @@ -4866,8 +4868,10 @@ private: [&](const auto &) { return fir::getBase(exv); }); caller.placeInput(argIface, arg); } - return Fortran::lower::genCallOpAndResult( - loc, converter, symMap, getElementCtx(), caller, callSiteType, retTy); + return Fortran::lower::genCallOpAndResult(loc, converter, symMap, + getElementCtx(), caller, + callSiteType, retTy) + .first; }; } diff --git a/flang/lib/Lower/OpenMP.cpp b/flang/lib/Lower/OpenMP.cpp index 0a68aba162618bb9c3e8b1910aa5b9a42db4ba55..ad4cffc707535f7d3f56707e2e4e8b339a8f9a1c 100644 --- a/flang/lib/Lower/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP.cpp @@ -2143,6 +2143,19 @@ static fir::ExtendedValue getExtendedValue(fir::ExtendedValue base, }); } +#ifndef NDEBUG +static bool isThreadPrivate(Fortran::lower::SymbolRef sym) { + if (const auto *details = + sym->detailsIf()) { + for (const auto &obj : details->objects()) + if (!obj->test(Fortran::semantics::Symbol::Flag::OmpThreadprivate)) + return false; + return true; + } + return sym->test(Fortran::semantics::Symbol::Flag::OmpThreadprivate); +} +#endif + static void threadPrivatizeVars(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval) { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); @@ -2150,18 +2163,21 @@ static void threadPrivatizeVars(Fortran::lower::AbstractConverter &converter, mlir::OpBuilder::InsertPoint insPt = firOpBuilder.saveInsertionPoint(); firOpBuilder.setInsertionPointToStart(firOpBuilder.getAllocaBlock()); - // Get the original ThreadprivateOp corresponding to the symbol and use the - // symbol value from that operation to create one ThreadprivateOp copy - // operation inside the parallel region. + // If the symbol corresponds to the original ThreadprivateOp, use the symbol + // value from that operation to create one ThreadprivateOp copy operation + // inside the parallel region. + // In some cases, however, the symbol will correspond to the original, + // non-threadprivate variable. This can happen, for instance, with a common + // block, declared in a separate module, used by a parent procedure and + // privatized in its child procedure. auto genThreadprivateOp = [&](Fortran::lower::SymbolRef sym) -> mlir::Value { - mlir::Value symOriThreadprivateValue = converter.getSymbolAddress(sym); - mlir::Operation *op = symOriThreadprivateValue.getDefiningOp(); + assert(isThreadPrivate(sym)); + mlir::Value symValue = converter.getSymbolAddress(sym); + mlir::Operation *op = symValue.getDefiningOp(); if (auto declOp = mlir::dyn_cast(op)) op = declOp.getMemref().getDefiningOp(); - assert(mlir::isa(op) && - "Threadprivate operation not created"); - mlir::Value symValue = - mlir::dyn_cast(op).getSymAddr(); + if (mlir::isa(op)) + symValue = mlir::dyn_cast(op).getSymAddr(); return firOpBuilder.create( currentLocation, symValue.getType(), symValue); }; @@ -2250,26 +2266,69 @@ createAndSetPrivatizedLoopVar(Fortran::lower::AbstractConverter &converter, return storeOp; } +struct OpWithBodyGenInfo { + /// A type for a code-gen callback function. This takes as argument the op for + /// which the code is being generated and returns the arguments of the op's + /// region. + using GenOMPRegionEntryCBFn = + std::function( + mlir::Operation *)>; + + OpWithBodyGenInfo(Fortran::lower::AbstractConverter &converter, + mlir::Location loc, Fortran::lower::pft::Evaluation &eval) + : converter(converter), loc(loc), eval(eval) {} + + OpWithBodyGenInfo &setGenNested(bool value) { + genNested = value; + return *this; + } + + OpWithBodyGenInfo &setOuterCombined(bool value) { + outerCombined = value; + return *this; + } + + OpWithBodyGenInfo &setClauses(const Fortran::parser::OmpClauseList *value) { + clauses = value; + return *this; + } + + OpWithBodyGenInfo &setDataSharingProcessor(DataSharingProcessor *value) { + dsp = value; + return *this; + } + + OpWithBodyGenInfo &setGenRegionEntryCb(GenOMPRegionEntryCBFn value) { + genRegionEntryCB = value; + return *this; + } + + /// [inout] converter to use for the clauses. + Fortran::lower::AbstractConverter &converter; + /// [in] location in source code. + mlir::Location loc; + /// [in] current PFT node/evaluation. + Fortran::lower::pft::Evaluation &eval; + /// [in] whether to generate FIR for nested evaluations + bool genNested = true; + /// [in] is this an outer operation - prevents privatization. + bool outerCombined = false; + /// [in] list of clauses to process. + const Fortran::parser::OmpClauseList *clauses = nullptr; + /// [in] if provided, processes the construct's data-sharing attributes. + DataSharingProcessor *dsp = nullptr; + /// [in] if provided, emits the op's region entry. Otherwise, an emtpy block + /// is created in the region. + GenOMPRegionEntryCBFn genRegionEntryCB = nullptr; +}; + /// Create the body (block) for an OpenMP Operation. /// -/// \param [in] op - the operation the body belongs to. -/// \param [inout] converter - converter to use for the clauses. -/// \param [in] loc - location in source code. -/// \param [in] eval - current PFT node/evaluation. -/// \param [in] genNested - whether to generate FIR for nested evaluations -/// \oaran [in] clauses - list of clauses to process. -/// \param [in] args - block arguments (induction variable[s]) for the -//// region. -/// \param [in] outerCombined - is this an outer operation - prevents -/// privatization. +/// \param [in] op - the operation the body belongs to. +/// \param [in] info - options controlling code-gen for the construction. template -static void createBodyOfOp( - Op &op, Fortran::lower::AbstractConverter &converter, mlir::Location &loc, - Fortran::lower::pft::Evaluation &eval, bool genNested, - const Fortran::parser::OmpClauseList *clauses = nullptr, - const llvm::SmallVector &args = {}, - bool outerCombined = false, DataSharingProcessor *dsp = nullptr) { - fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); +static void createBodyOfOp(Op &op, OpWithBodyGenInfo &info) { + fir::FirOpBuilder &firOpBuilder = info.converter.getFirOpBuilder(); auto insertMarker = [](fir::FirOpBuilder &builder) { mlir::Value undef = builder.create(builder.getUnknownLoc(), @@ -2281,71 +2340,58 @@ static void createBodyOfOp( // argument. Also update the symbol's address with the mlir argument value. // e.g. For loops the argument is the induction variable. And all further // uses of the induction variable should use this mlir value. - if (args.size()) { - std::size_t loopVarTypeSize = 0; - for (const Fortran::semantics::Symbol *arg : args) - loopVarTypeSize = std::max(loopVarTypeSize, arg->GetUltimate().size()); - mlir::Type loopVarType = getLoopVarType(converter, loopVarTypeSize); - llvm::SmallVector tiv(args.size(), loopVarType); - llvm::SmallVector locs(args.size(), loc); - firOpBuilder.createBlock(&op.getRegion(), {}, tiv, locs); - // The argument is not currently in memory, so make a temporary for the - // argument, and store it there, then bind that location to the argument. - mlir::Operation *storeOp = nullptr; - for (auto [argIndex, argSymbol] : llvm::enumerate(args)) { - mlir::Value indexVal = - fir::getBase(op.getRegion().front().getArgument(argIndex)); - storeOp = - createAndSetPrivatizedLoopVar(converter, loc, indexVal, argSymbol); + auto regionArgs = + [&]() -> llvm::SmallVector { + if (info.genRegionEntryCB != nullptr) { + return info.genRegionEntryCB(op); } - firOpBuilder.setInsertionPointAfter(storeOp); - } else { - firOpBuilder.createBlock(&op.getRegion()); - } + firOpBuilder.createBlock(&op.getRegion()); + return {}; + }(); // Mark the earliest insertion point. mlir::Operation *marker = insertMarker(firOpBuilder); // If it is an unstructured region and is not the outer region of a combined // construct, create empty blocks for all evaluations. - if (eval.lowerAsUnstructured() && !outerCombined) + if (info.eval.lowerAsUnstructured() && !info.outerCombined) Fortran::lower::createEmptyRegionBlocks( - firOpBuilder, eval.getNestedEvaluations()); + firOpBuilder, info.eval.getNestedEvaluations()); // Start with privatization, so that the lowering of the nested // code will use the right symbols. constexpr bool isLoop = std::is_same_v || std::is_same_v; - bool privatize = clauses && !outerCombined; + bool privatize = info.clauses && !info.outerCombined; firOpBuilder.setInsertionPoint(marker); std::optional tempDsp; if (privatize) { - if (!dsp) { - tempDsp.emplace(converter, *clauses, eval); + if (!info.dsp) { + tempDsp.emplace(info.converter, *info.clauses, info.eval); tempDsp->processStep1(); } } if constexpr (std::is_same_v) { - threadPrivatizeVars(converter, eval); - if (clauses) { + threadPrivatizeVars(info.converter, info.eval); + if (info.clauses) { firOpBuilder.setInsertionPoint(marker); - ClauseProcessor(converter, *clauses).processCopyin(); + ClauseProcessor(info.converter, *info.clauses).processCopyin(); } } - if (genNested) { + if (info.genNested) { // genFIR(Evaluation&) tries to patch up unterminated blocks, causing // a lot of complications for our approach if the terminator generation // is delayed past this point. Insert a temporary terminator here, then // delete it. firOpBuilder.setInsertionPointToEnd(&op.getRegion().back()); - auto *temp = Fortran::lower::genOpenMPTerminator(firOpBuilder, - op.getOperation(), loc); + auto *temp = Fortran::lower::genOpenMPTerminator( + firOpBuilder, op.getOperation(), info.loc); firOpBuilder.setInsertionPointAfter(marker); - genNestedEvaluations(converter, eval); + genNestedEvaluations(info.converter, info.eval); temp->erase(); } @@ -2380,28 +2426,28 @@ static void createBodyOfOp( mlir::Block *exit = firOpBuilder.createBlock(®ion); for (mlir::Block *b : exits) { firOpBuilder.setInsertionPointToEnd(b); - firOpBuilder.create(loc, exit); + firOpBuilder.create(info.loc, exit); } return exit; }; if (auto *exitBlock = getUniqueExit(op.getRegion())) { firOpBuilder.setInsertionPointToEnd(exitBlock); - auto *term = Fortran::lower::genOpenMPTerminator(firOpBuilder, - op.getOperation(), loc); + auto *term = Fortran::lower::genOpenMPTerminator( + firOpBuilder, op.getOperation(), info.loc); // Only insert lastprivate code when there actually is an exit block. // Such a block may not exist if the nested code produced an infinite // loop (this may not make sense in production code, but a user could // write that and we should handle it). firOpBuilder.setInsertionPoint(term); if (privatize) { - if (!dsp) { + if (!info.dsp) { assert(tempDsp.has_value()); tempDsp->processStep2(op, isLoop); } else { - if (isLoop && args.size() > 0) - dsp->setLoopIV(converter.getSymbolAddress(*args[0])); - dsp->processStep2(op, isLoop); + if (isLoop && regionArgs.size() > 0) + info.dsp->setLoopIV(info.converter.getSymbolAddress(*regionArgs[0])); + info.dsp->processStep2(op, isLoop); } } } @@ -2476,16 +2522,10 @@ static void genBodyOfTargetDataOp( } template -static OpTy genOpWithBody(Fortran::lower::AbstractConverter &converter, - Fortran::lower::pft::Evaluation &eval, bool genNested, - mlir::Location currentLocation, bool outerCombined, - const Fortran::parser::OmpClauseList *clauseList, - Args &&...args) { - auto op = converter.getFirOpBuilder().create( - currentLocation, std::forward(args)...); - createBodyOfOp(op, converter, currentLocation, eval, genNested, - clauseList, - /*args=*/{}, outerCombined); +static OpTy genOpWithBody(OpWithBodyGenInfo &info, Args &&...args) { + auto op = info.converter.getFirOpBuilder().create( + info.loc, std::forward(args)...); + createBodyOfOp(op, info); return op; } @@ -2493,11 +2533,10 @@ static mlir::omp::MasterOp genMasterOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval, bool genNested, mlir::Location currentLocation) { - return genOpWithBody(converter, eval, genNested, - currentLocation, - /*outerCombined=*/false, - /*clauseList=*/nullptr, - /*resultTypes=*/mlir::TypeRange()); + return genOpWithBody( + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested), + /*resultTypes=*/mlir::TypeRange()); } static mlir::omp::OrderedRegionOp @@ -2505,9 +2544,9 @@ genOrderedRegionOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval, bool genNested, mlir::Location currentLocation) { return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, - /*clauseList=*/nullptr, /*simd=*/false); + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested), + /*simd=*/false); } static mlir::omp::ParallelOp @@ -2534,7 +2573,10 @@ genParallelOp(Fortran::lower::AbstractConverter &converter, cp.processReduction(currentLocation, reductionVars, reductionDeclSymbols); return genOpWithBody( - converter, eval, genNested, currentLocation, outerCombined, &clauseList, + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested) + .setOuterCombined(outerCombined) + .setClauses(&clauseList), /*resultTypes=*/mlir::TypeRange(), ifClauseOperand, numThreadsClauseOperand, allocateOperands, allocatorOperands, reductionVars, @@ -2553,8 +2595,9 @@ genSectionOp(Fortran::lower::AbstractConverter &converter, // Currently only private/firstprivate clause is handled, and // all privatization is done within `omp.section` operations. return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, §ionsClauseList); + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested) + .setClauses(§ionsClauseList)); } static mlir::omp::SingleOp @@ -2574,9 +2617,10 @@ genSingleOp(Fortran::lower::AbstractConverter &converter, ClauseProcessor(converter, endClauseList).processNowait(nowaitAttr); return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, &beginClauseList, allocateOperands, - allocatorOperands, nowaitAttr); + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested) + .setClauses(&beginClauseList), + allocateOperands, allocatorOperands, nowaitAttr); } static mlir::omp::TaskOp @@ -2607,9 +2651,10 @@ genTaskOp(Fortran::lower::AbstractConverter &converter, currentLocation, llvm::omp::Directive::OMPD_task); return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, &clauseList, ifClauseOperand, finalClauseOperand, - untiedAttr, mergeableAttr, + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested) + .setClauses(&clauseList), + ifClauseOperand, finalClauseOperand, untiedAttr, mergeableAttr, /*in_reduction_vars=*/mlir::ValueRange(), /*in_reductions=*/nullptr, priorityClauseOperand, dependTypeOperands.empty() @@ -2630,8 +2675,9 @@ genTaskGroupOp(Fortran::lower::AbstractConverter &converter, cp.processTODO( currentLocation, llvm::omp::Directive::OMPD_taskgroup); return genOpWithBody( - converter, eval, genNested, currentLocation, - /*outerCombined=*/false, &clauseList, + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested) + .setClauses(&clauseList), /*task_reduction_vars=*/mlir::ValueRange(), /*task_reductions=*/nullptr, allocateOperands, allocatorOperands); } @@ -3014,7 +3060,10 @@ genTeamsOp(Fortran::lower::AbstractConverter &converter, currentLocation, llvm::omp::Directive::OMPD_teams); return genOpWithBody( - converter, eval, genNested, currentLocation, outerCombined, &clauseList, + OpWithBodyGenInfo(converter, currentLocation, eval) + .setGenNested(genNested) + .setOuterCombined(outerCombined) + .setClauses(&clauseList), /*num_teams_lower=*/nullptr, numTeamsClauseOperand, ifClauseOperand, threadLimitClauseOperand, allocateOperands, allocatorOperands, reductionVars, @@ -3211,6 +3260,33 @@ static void convertLoopBounds(Fortran::lower::AbstractConverter &converter, } } +static llvm::SmallVector +genLoopVars(mlir::Operation *op, Fortran::lower::AbstractConverter &converter, + mlir::Location &loc, + const llvm::SmallVector &args) { + fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); + auto ®ion = op->getRegion(0); + + std::size_t loopVarTypeSize = 0; + for (const Fortran::semantics::Symbol *arg : args) + loopVarTypeSize = std::max(loopVarTypeSize, arg->GetUltimate().size()); + mlir::Type loopVarType = getLoopVarType(converter, loopVarTypeSize); + llvm::SmallVector tiv(args.size(), loopVarType); + llvm::SmallVector locs(args.size(), loc); + firOpBuilder.createBlock(®ion, {}, tiv, locs); + // The argument is not currently in memory, so make a temporary for the + // argument, and store it there, then bind that location to the argument. + mlir::Operation *storeOp = nullptr; + for (auto [argIndex, argSymbol] : llvm::enumerate(args)) { + mlir::Value indexVal = fir::getBase(region.front().getArgument(argIndex)); + storeOp = + createAndSetPrivatizedLoopVar(converter, loc, indexVal, argSymbol); + } + firOpBuilder.setInsertionPointAfter(storeOp); + + return args; +} + static void createSimdLoop(Fortran::lower::AbstractConverter &converter, Fortran::lower::pft::Evaluation &eval, @@ -3258,9 +3334,16 @@ createSimdLoop(Fortran::lower::AbstractConverter &converter, auto *nestedEval = getCollapsedLoopEval( eval, Fortran::lower::getCollapseValue(loopOpClauseList)); - createBodyOfOp(simdLoopOp, converter, loc, *nestedEval, - /*genNested=*/true, &loopOpClauseList, - iv, /*outer=*/false, &dsp); + + auto ivCallback = [&](mlir::Operation *op) { + return genLoopVars(op, converter, loc, iv); + }; + + createBodyOfOp( + simdLoopOp, OpWithBodyGenInfo(converter, loc, *nestedEval) + .setClauses(&loopOpClauseList) + .setDataSharingProcessor(&dsp) + .setGenRegionEntryCb(ivCallback)); } static void createWsLoop(Fortran::lower::AbstractConverter &converter, @@ -3333,9 +3416,16 @@ static void createWsLoop(Fortran::lower::AbstractConverter &converter, auto *nestedEval = getCollapsedLoopEval( eval, Fortran::lower::getCollapseValue(beginClauseList)); - createBodyOfOp(wsLoopOp, converter, loc, *nestedEval, - /*genNested=*/true, &beginClauseList, iv, - /*outer=*/false, &dsp); + + auto ivCallback = [&](mlir::Operation *op) { + return genLoopVars(op, converter, loc, iv); + }; + + createBodyOfOp( + wsLoopOp, OpWithBodyGenInfo(converter, loc, *nestedEval) + .setClauses(&beginClauseList) + .setDataSharingProcessor(&dsp) + .setGenRegionEntryCb(ivCallback)); } static void createSimdWsLoop( @@ -3616,8 +3706,8 @@ genOMP(Fortran::lower::AbstractConverter &converter, currentLocation, mlir::FlatSymbolRefAttr::get(firOpBuilder.getContext(), global.getSymName())); }(); - createBodyOfOp(criticalOp, converter, currentLocation, - eval, /*genNested=*/true); + auto genInfo = OpWithBodyGenInfo(converter, currentLocation, eval); + createBodyOfOp(criticalOp, genInfo); } static void @@ -3659,13 +3749,11 @@ genOMP(Fortran::lower::AbstractConverter &converter, } // SECTIONS construct - genOpWithBody(converter, eval, - /*genNested=*/false, currentLocation, - /*outerCombined=*/false, - /*clauseList=*/nullptr, - /*reduction_vars=*/mlir::ValueRange(), - /*reductions=*/nullptr, allocateOperands, - allocatorOperands, nowaitClauseOperand); + genOpWithBody( + OpWithBodyGenInfo(converter, currentLocation, eval).setGenNested(false), + /*reduction_vars=*/mlir::ValueRange(), + /*reductions=*/nullptr, allocateOperands, allocatorOperands, + nowaitClauseOperand); const auto §ionBlocks = std::get(sectionsConstruct.t); diff --git a/flang/lib/Optimizer/Builder/MutableBox.cpp b/flang/lib/Optimizer/Builder/MutableBox.cpp index 61813f6b71dc5a9e4b04a8492353e84857f88f5e..4d8860b60915c435bb2fee7a8251723e239fd6bb 100644 --- a/flang/lib/Optimizer/Builder/MutableBox.cpp +++ b/flang/lib/Optimizer/Builder/MutableBox.cpp @@ -406,7 +406,8 @@ static bool readToBoxValue(const fir::MutableBoxValue &box, fir::ExtendedValue fir::factory::genMutableBoxRead(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, - bool mayBePolymorphic) { + bool mayBePolymorphic, + bool preserveLowerBounds) { if (box.hasAssumedRank()) TODO(loc, "assumed rank allocatables or pointers"); llvm::SmallVector lbounds; @@ -414,7 +415,8 @@ fir::factory::genMutableBoxRead(fir::FirOpBuilder &builder, mlir::Location loc, llvm::SmallVector lengths; if (readToBoxValue(box, mayBePolymorphic)) { auto reader = MutablePropertyReader(builder, loc, box); - reader.getLowerBounds(lbounds); + if (preserveLowerBounds) + reader.getLowerBounds(lbounds); return fir::BoxValue{reader.getIrBox(), lbounds, box.nonDeferredLenParams()}; } @@ -422,6 +424,8 @@ fir::factory::genMutableBoxRead(fir::FirOpBuilder &builder, mlir::Location loc, // fir.box. auto addr = MutablePropertyReader(builder, loc, box).read(lbounds, extents, lengths); + if (!preserveLowerBounds) + lbounds.clear(); auto rank = box.rank(); if (box.isCharacter()) { auto len = lengths.empty() ? mlir::Value{} : lengths[0]; diff --git a/flang/lib/Optimizer/Dialect/FIRDialect.cpp b/flang/lib/Optimizer/Dialect/FIRDialect.cpp index d0176731c292d32092682f07aedc6f305f8b1c62..f4589fda1845875d993b305cf1d441edfd9f58f1 100644 --- a/flang/lib/Optimizer/Dialect/FIRDialect.cpp +++ b/flang/lib/Optimizer/Dialect/FIRDialect.cpp @@ -67,7 +67,14 @@ fir::FIROpsDialect::FIROpsDialect(mlir::MLIRContext *ctx) #include "flang/Optimizer/Dialect/FIROps.cpp.inc" >(); registerOpExternalInterfaces(); - addInterfaces(); +} + +// Register the FIRInlinerInterface to FIROpsDialect +void fir::addFIRInlinerExtension(mlir::DialectRegistry ®istry) { + registry.addExtension( + +[](mlir::MLIRContext *ctx, fir::FIROpsDialect *dialect) { + dialect->addInterface(); + }); } // anchor the class vtable to this compilation unit diff --git a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp index 15258e3e9c309deab26b28f5b29a0ad3c3daefce..bd8d3d92d480b6de88cd464348f5eaf4de0a5a40 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp @@ -159,6 +159,22 @@ createArrayTemp(mlir::Location loc, fir::FirOpBuilder &builder, return {hlfir::Entity{declareOp.getBase()}, trueVal}; } +/// Copy \p source into a new temporary and package the temporary into a +/// tuple. The temporary may be heap or stack allocated. +static mlir::Value copyInTempAndPackage(mlir::Location loc, + fir::FirOpBuilder &builder, + hlfir::Entity source) { + auto [temp, cleanup] = hlfir::createTempFromMold(loc, builder, source); + builder.create(loc, source, temp, temp.isAllocatable(), + /*keep_lhs_length_if_realloc=*/false, + /*temporary_lhs=*/true); + // Dereference allocatable temporary directly to simplify processing + // of its uses. + if (temp.isAllocatable()) + temp = hlfir::derefPointersAndAllocatables(loc, builder, temp); + return packageBufferizedExpr(loc, builder, temp, cleanup); +} + struct AsExprOpConversion : public mlir::OpConversionPattern { using mlir::OpConversionPattern::OpConversionPattern; explicit AsExprOpConversion(mlir::MLIRContext *ctx) @@ -178,12 +194,7 @@ struct AsExprOpConversion : public mlir::OpConversionPattern { } // Otherwise, create a copy in a new buffer. hlfir::Entity source = hlfir::Entity{adaptor.getVar()}; - auto [temp, cleanup] = hlfir::createTempFromMold(loc, builder, source); - builder.create(loc, source, temp, temp.isAllocatable(), - /*keep_lhs_length_if_realloc=*/false, - /*temporary_lhs=*/true); - mlir::Value bufferizedExpr = - packageBufferizedExpr(loc, builder, temp, cleanup); + mlir::Value bufferizedExpr = copyInTempAndPackage(loc, builder, source); rewriter.replaceOp(asExpr, bufferizedExpr); return mlir::success(); } @@ -542,12 +553,7 @@ struct AssociateOpConversion // non-trivial value with more than one use. We will have to make a copy and // use that hlfir::Entity source = hlfir::Entity{bufferizedExpr}; - auto [temp, cleanup] = hlfir::createTempFromMold(loc, builder, source); - builder.create(loc, source, temp, temp.isAllocatable(), - /*keep_lhs_length_if_realloc=*/false, - /*temporary_lhs=*/true); - mlir::Value bufferTuple = - packageBufferizedExpr(loc, builder, temp, cleanup); + mlir::Value bufferTuple = copyInTempAndPackage(loc, builder, source); bufferizedExpr = getBufferizedExprStorage(bufferTuple); replaceWith(bufferizedExpr, hlfir::Entity{bufferizedExpr}.getFirBase(), getBufferizedExprMustFreeFlag(bufferTuple)); diff --git a/flang/lib/Semantics/resolve-directives.cpp b/flang/lib/Semantics/resolve-directives.cpp index 8d38790d2006a1b2e95fdfdb6494ced9fca27118..4b6d083671bc9257b4c77a9a8e177ecab344610f 100644 --- a/flang/lib/Semantics/resolve-directives.cpp +++ b/flang/lib/Semantics/resolve-directives.cpp @@ -2467,7 +2467,8 @@ void OmpAttributeVisitor::CheckDataCopyingClause( // either 'private' or 'threadprivate' in enclosing context. if (!checkSymbol->test(Symbol::Flag::OmpThreadprivate) && !(HasSymbolInEnclosingScope(symbol, currScope()) && - symbol.test(Symbol::Flag::OmpPrivate))) { + (symbol.test(Symbol::Flag::OmpPrivate) || + symbol.test(Symbol::Flag::OmpFirstPrivate)))) { context_.Say(name.source, "COPYPRIVATE variable '%s' is not PRIVATE or THREADPRIVATE in " "outer context"_err_en_US, diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index 6914f95837f676a16b5fef9c020cb2bf4c82fc52..36deab969456d0331aea2997f52ce929da5f7c4e 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -5648,7 +5648,9 @@ void DeclarationVisitor::Post(const parser::ProcDecl &x) { const auto &name{std::get(x.t)}; const Symbol *procInterface{nullptr}; if (interfaceName_) { - procInterface = interfaceName_->symbol; + procInterface = interfaceName_->symbol->has() + ? interfaceName_->symbol->get().specific() + : interfaceName_->symbol; } auto attrs{HandleSaveName(name.source, GetAttrs())}; DerivedTypeDetails *dtDetails{nullptr}; diff --git a/flang/test/HLFIR/as_expr-codegen-polymorphic.fir b/flang/test/HLFIR/as_expr-codegen-polymorphic.fir new file mode 100644 index 0000000000000000000000000000000000000000..30a8da72c3e486cc08f5cbba3aa34e03c8c9c92a --- /dev/null +++ b/flang/test/HLFIR/as_expr-codegen-polymorphic.fir @@ -0,0 +1,38 @@ +// Test hlfir.as_expr codegen for polymorphic expressions. + +// RUN: fir-opt %s -bufferize-hlfir | FileCheck %s + +!t = !fir.type +func.func @as_expr_class(%arg0 : !fir.class, %arg1: !fir.ref) { + %0 = hlfir.as_expr %arg0 : (!fir.class) -> !hlfir.expr + hlfir.assign %0 to %arg1 : !hlfir.expr, !fir.ref + return +} +// CHECK-LABEL: func.func @as_expr_class( +// CHECK: %[[VAL_5:.*]] = arith.constant true +// CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = ".tmp"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +// ... copy ... +// CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref>>> +// CHECK: %[[VAL_12:.*]] = fir.undefined tuple>>, i1> +// CHECK: %[[VAL_13:.*]] = fir.insert_value %[[VAL_12]], %[[VAL_5]], [1 : index] : (tuple>>, i1>, i1) -> tuple>>, i1> +// CHECK: %[[VAL_14:.*]] = fir.insert_value %[[VAL_13]], %[[VAL_11]], [0 : index] : (tuple>>, i1>, !fir.class>>) -> tuple>>, i1> +// CHECK: hlfir.assign %[[VAL_11]] to %{{.*}} : !fir.class>>, !fir.ref> + + +func.func @as_expr_class_2(%arg0 : !fir.class>) { + %0 = hlfir.as_expr %arg0 : (!fir.class>) -> !hlfir.expr + %c1 = arith.constant 1 : index + %1 = hlfir.apply %0, %c1 : (!hlfir.expr, index) -> !hlfir.expr + return +} +// CHECK-LABEL: func.func @as_expr_class_2( +// CHECK: %[[VAL_9:.*]] = arith.constant true +// CHECK: %[[VAL_10:.*]]:2 = hlfir.declare %{{.*}} {fortran_attrs = #fir.var_attrs, uniq_name = ".tmp"} : (!fir.ref>>>>) -> (!fir.ref>>>>, !fir.ref>>>>) +// CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 +// ... copy ... +// CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_10]]#0 : !fir.ref>>>> +// CHECK: %[[VAL_16:.*]] = fir.undefined tuple>>>, i1> +// CHECK: %[[VAL_17:.*]] = fir.insert_value %[[VAL_16]], %[[VAL_9]], [1 : index] : (tuple>>>, i1>, i1) -> tuple>>>, i1> +// CHECK: %[[VAL_18:.*]] = fir.insert_value %[[VAL_17]], %[[VAL_15]], [0 : index] : (tuple>>>, i1>, !fir.class>>>) -> tuple>>>, i1> +// CHECK: %[[VAL_19:.*]] = arith.constant 1 : index +// CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_15]] (%[[VAL_19]]) : (!fir.class>>>, index) -> !fir.class> diff --git a/flang/test/HLFIR/bufferize-poly-expr.fir b/flang/test/HLFIR/bufferize-poly-expr.fir index df43c74b2aaccba82c18df4a4a259d397e9541e8..dfa62a9ac5ab72b3369a78fd8206d847dd56cfd1 100644 --- a/flang/test/HLFIR/bufferize-poly-expr.fir +++ b/flang/test/HLFIR/bufferize-poly-expr.fir @@ -26,12 +26,12 @@ func.func @test_poly_expr_without_associate() { // CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_4]]#1 : (!fir.class>>) -> !fir.box // CHECK: %[[VAL_12:.*]] = fir.call @_FortranAAllocatableApplyMold(%[[VAL_10]], %[[VAL_11]], %[[VAL_9]]) : (!fir.ref>, !fir.box, i32) -> none // CHECK: hlfir.assign %[[VAL_4]]#0 to %[[VAL_8]]#0 realloc temporary_lhs : !fir.class>>, !fir.ref>>> -// CHECK: %[[VAL_13:.*]] = fir.undefined tuple>>>, i1> -// CHECK: %[[VAL_14:.*]] = fir.insert_value %[[VAL_13]], %[[VAL_7]], [1 : index] : (tuple>>>, i1>, i1) -> tuple>>>, i1> -// CHECK: %[[VAL_15:.*]] = fir.insert_value %[[VAL_14]], %[[VAL_8]]#0, [0 : index] : (tuple>>>, i1>, !fir.ref>>>) -> tuple>>>, i1> -// CHECK: hlfir.assign %[[VAL_8]]#0 to %[[VAL_2]]#0 realloc : !fir.ref>>>, !fir.ref>>> -// CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref>>> -// CHECK: %[[VAL_17:.*]] = fir.box_addr %[[VAL_16]] : (!fir.class>>) -> !fir.heap> +// CHECK: %[[VAL_8B:.*]] = fir.load %[[VAL_8]]#0 +// CHECK: %[[VAL_13:.*]] = fir.undefined tuple>>, i1> +// CHECK: %[[VAL_14:.*]] = fir.insert_value %[[VAL_13]], %[[VAL_7]], [1 : index] : (tuple>>, i1>, i1) -> tuple>>, i1> +// CHECK: %[[VAL_15:.*]] = fir.insert_value %[[VAL_14]], %[[VAL_8B]], [0 : index] : (tuple>>, i1>, !fir.class>>) -> tuple>>, i1> +// CHECK: hlfir.assign %[[VAL_8B]] to %[[VAL_2]]#0 realloc : !fir.class>>, !fir.ref>>> +// CHECK: %[[VAL_17:.*]] = fir.box_addr %[[VAL_8B]] : (!fir.class>>) -> !fir.heap> // CHECK: fir.freemem %[[VAL_17]] : !fir.heap> // CHECK: return // CHECK: } @@ -81,14 +81,13 @@ func.func @test_poly_expr_with_associate(%arg1: !fir.class>>>) -> !fir.box // CHECK: %[[VAL_18:.*]] = fir.call @_FortranAAllocatableApplyMold(%[[VAL_16]], %[[VAL_17]], %[[VAL_15]]) : (!fir.ref>, !fir.box, i32) -> none // CHECK: hlfir.assign %[[VAL_5]] to %[[VAL_14]]#0 realloc temporary_lhs : !fir.class>>>, !fir.ref>>>> -// CHECK: %[[VAL_19:.*]] = fir.undefined tuple>>>>, i1> -// CHECK: %[[VAL_20:.*]] = fir.insert_value %[[VAL_19]], %[[VAL_13]], [1 : index] : (tuple>>>>, i1>, i1) -> tuple>>>>, i1> -// CHECK: %[[VAL_21:.*]] = fir.insert_value %[[VAL_20]], %[[VAL_14]]#0, [0 : index] : (tuple>>>>, i1>, !fir.ref>>>>) -> tuple>>>>, i1> +// CHECK: %[[VAL_14B:.*]] = fir.load %[[VAL_14]]#0 +// CHECK: %[[VAL_19:.*]] = fir.undefined tuple>>>, i1> +// CHECK: %[[VAL_20:.*]] = fir.insert_value %[[VAL_19]], %[[VAL_13]], [1 : index] : (tuple>>>, i1>, i1) -> tuple>>>, i1> +// CHECK: %[[VAL_21:.*]] = fir.insert_value %[[VAL_20]], %[[VAL_14B]], [0 : index] : (tuple>>>, i1>, !fir.class>>>) -> tuple>>>, i1> // CHECK: %[[VAL_22:.*]] = arith.constant 0 : index // CHECK: %[[VAL_23:.*]]:3 = fir.box_dims %[[VAL_5]], %[[VAL_22]] : (!fir.class>>>, index) -> (index, index, index) // CHECK: %[[VAL_24:.*]] = fir.shape %[[VAL_23]]#1 : (index) -> !fir.shape<1> -// CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref>>>> -// CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_14]]#1 : !fir.ref>>>> // CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>>>>) -> !fir.box // CHECK: %[[VAL_28:.*]] = fir.call @_FortranADestroy(%[[VAL_27]]) fastmath : (!fir.box) -> none // CHECK: %[[VAL_29:.*]] = arith.constant 3 : index @@ -96,10 +95,10 @@ func.func @test_poly_expr_with_associate(%arg1: !fir.class>>, index) -> !fir.class> -// CHECK: %[[VAL_34:.*]] = hlfir.designate %[[VAL_25]] (%[[VAL_32]]) : (!fir.class>>>, index) -> !fir.class> +// CHECK: %[[VAL_34:.*]] = hlfir.designate %[[VAL_14B]] (%[[VAL_32]]) : (!fir.class>>>, index) -> !fir.class> // CHECK: fir.dispatch "assign"(%[[VAL_33]] : !fir.class>) (%[[VAL_33]], %[[VAL_34]] : !fir.class>, !fir.class>) {pass_arg_pos = 0 : i32} // CHECK: } -// CHECK: %[[VAL_35:.*]] = fir.box_addr %[[VAL_26]] : (!fir.class>>>) -> !fir.heap>> +// CHECK: %[[VAL_35:.*]] = fir.box_addr %[[VAL_14B]] : (!fir.class>>>) -> !fir.heap>> // CHECK: fir.freemem %[[VAL_35]] : !fir.heap>> // CHECK: return // CHECK: } diff --git a/flang/test/Lower/HLFIR/function-return-as-expr.f90 b/flang/test/Lower/HLFIR/function-return-as-expr.f90 index 7c8e73779d79e9a2da1be9faf6a8f0da5709e81c..ae4f679a0fe6022b2b0c47bf43f8e61aaf516eee 100644 --- a/flang/test/Lower/HLFIR/function-return-as-expr.f90 +++ b/flang/test/Lower/HLFIR/function-return-as-expr.f90 @@ -66,11 +66,26 @@ contains end function inner end subroutine test4 ! CHECK-LABEL: func.func @_QPtest4() { -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %{{.*}} {uniq_name = ".tmp.func_result"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref>> -! CHECK: %[[VAL_8:.*]] = arith.constant false -! CHECK: %[[VAL_9:.*]] = hlfir.as_expr %[[VAL_7]] move %[[VAL_8]] : (!fir.class>, i1) -> !hlfir.expr -! CHECK: hlfir.assign %[[VAL_9]] to %{{.*}}#0 realloc : !hlfir.expr, !fir.ref>> +! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0:.*]] : !fir.ref>> +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = ".tmp.func_result"} : (!fir.class>) -> (!fir.class>, !fir.class>) +! CHECK: hlfir.assign %[[VAL_7]]#0 to %{{.*}}#0 realloc : !fir.class>, !fir.ref>> +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>>) -> !fir.box +! CHECK: fir.call @_FortranADestroy(%[[VAL_10]]) fastmath : (!fir.box) -> none + +subroutine test4b + class(*), allocatable :: p(:, :) + p = inner() +contains + function inner() + class(*), allocatable :: inner(:, :) + end function inner +end subroutine test4b +! CHECK-LABEL: func.func @_QPtest4b() { +! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_0:.*]] : !fir.ref>>> +! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]] {uniq_name = ".tmp.func_result"} : (!fir.class>>) -> (!fir.class>>, !fir.class>>) +! CHECK: hlfir.assign %[[VAL_7]]#0 to %{{.*}}#0 realloc : !fir.class>>, !fir.ref>>> +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_0]] : (!fir.ref>>>) -> !fir.box +! CHECK: fir.call @_FortranADestroy(%[[VAL_10]]) fastmath : (!fir.box) -> none subroutine test5 use types diff --git a/flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 b/flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 new file mode 100644 index 0000000000000000000000000000000000000000..28616f7595a0d6fed460dae0c1e27f94faa949d6 --- /dev/null +++ b/flang/test/Lower/OpenMP/threadprivate-commonblock-use.f90 @@ -0,0 +1,29 @@ +! This test checks lowering of OpenMP Threadprivate Directive. +! Test for common block, defined in one module, used in a subroutine of +! another module and privatized in a nested subroutine. + +!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s + +!CHECK: fir.global common @cmn_(dense<0> : vector<4xi8>) : !fir.array<4xi8> +module m0 + common /cmn/ k1 + !$omp threadprivate(/cmn/) +end + +module m1 +contains + subroutine ss1 + use m0 + contains +!CHECK-LABEL: func @_QMm1Fss1Pss2 +!CHECK: %[[CMN:.*]] = fir.address_of(@cmn_) : !fir.ref> +!CHECK: omp.parallel +!CHECK: %{{.*}} = omp.threadprivate %[[CMN]] : !fir.ref> -> !fir.ref> + subroutine ss2 + !$omp parallel copyin (k1) + !$omp end parallel + end subroutine ss2 + end subroutine ss1 +end + +end diff --git a/flang/test/Semantics/OpenMP/copyprivate03.f90 b/flang/test/Semantics/OpenMP/copyprivate03.f90 index eccc308b1d5abdaa81a2046acc79dcbe561ba829..9d39fdb6b13c8696c7a5e591cbb610b86893cefc 100644 --- a/flang/test/Semantics/OpenMP/copyprivate03.f90 +++ b/flang/test/Semantics/OpenMP/copyprivate03.f90 @@ -34,6 +34,13 @@ program omp_copyprivate !$omp end parallel !$omp end parallel sections + !The use of FIRSTPRIVATE with COPYPRIVATE is allowed + !$omp parallel firstprivate(a) + !$omp single + a = a + k + !$omp end single copyprivate(a) + !$omp end parallel + print *, a, b end program omp_copyprivate diff --git a/flang/tools/bbc/bbc.cpp b/flang/tools/bbc/bbc.cpp index 98d9258e023e55800de1d69974cbcd3e045e3dcf..9d5caf5c6804ea68a71fd1fe09d2d0f7e277b4b0 100644 --- a/flang/tools/bbc/bbc.cpp +++ b/flang/tools/bbc/bbc.cpp @@ -326,6 +326,7 @@ static mlir::LogicalResult convertFortranSourceToMLIR( // translate to FIR dialect of MLIR mlir::DialectRegistry registry; fir::support::registerNonCodegenDialects(registry); + fir::support::addFIRExtensions(registry); mlir::MLIRContext ctx(registry); fir::support::loadNonCodegenDialects(ctx); auto &defKinds = semanticsContext.defaultKinds(); diff --git a/flang/tools/fir-opt/fir-opt.cpp b/flang/tools/fir-opt/fir-opt.cpp index 92af79e50fa4e10461f364ae48e3c29cfa182958..1846c1b317848feac8069081d67da56432efc319 100644 --- a/flang/tools/fir-opt/fir-opt.cpp +++ b/flang/tools/fir-opt/fir-opt.cpp @@ -40,6 +40,7 @@ int main(int argc, char **argv) { #endif DialectRegistry registry; fir::support::registerDialects(registry); + fir::support::addFIRExtensions(registry); return failed(MlirOptMain(argc, argv, "FIR modular optimizer driver\n", registry)); } diff --git a/flang/tools/tco/tco.cpp b/flang/tools/tco/tco.cpp index 2153e0e3e62492b9fd21acbfe954bb9a1ea70afe..45284e74f58456a0026bec1142d15a3e3cc4652a 100644 --- a/flang/tools/tco/tco.cpp +++ b/flang/tools/tco/tco.cpp @@ -90,6 +90,7 @@ compileFIR(const mlir::PassPipelineCLParser &passPipeline) { sourceMgr.AddNewSourceBuffer(std::move(*fileOrErr), SMLoc()); mlir::DialectRegistry registry; fir::support::registerDialects(registry); + fir::support::addFIRExtensions(registry); mlir::MLIRContext context(registry); fir::support::loadDialects(context); fir::support::registerLLVMTranslation(context); diff --git a/libc/config/linux/aarch64/entrypoints.txt b/libc/config/linux/aarch64/entrypoints.txt index 1ff9c909355b2644cf64fd966e3dea3a95ebc313..5b03080787dc89c0663245201f76698f2d6f5513 100644 --- a/libc/config/linux/aarch64/entrypoints.txt +++ b/libc/config/linux/aarch64/entrypoints.txt @@ -379,7 +379,15 @@ set(TARGET_LIBM_ENTRYPOINTS if(LIBC_COMPILER_HAS_FLOAT128) list(APPEND TARGET_LIBM_ENTRYPOINTS # math.h C23 _Float128 entrypoints + libc.src.math.ceilf128 + libc.src.math.copysignf128 libc.src.math.fabsf128 + libc.src.math.floorf128 + libc.src.math.fmaxf128 + libc.src.math.fminf128 + libc.src.math.roundf128 + libc.src.math.sqrtf128 + libc.src.math.truncf128 ) endif() diff --git a/libc/config/linux/riscv/entrypoints.txt b/libc/config/linux/riscv/entrypoints.txt index 7473ac8e2066efc5793e1b34264fcf080c0a6bae..5e98538c91b4e940f7e9f4a05bea9d193e5abeab 100644 --- a/libc/config/linux/riscv/entrypoints.txt +++ b/libc/config/linux/riscv/entrypoints.txt @@ -385,6 +385,21 @@ set(TARGET_LIBM_ENTRYPOINTS libc.src.math.truncl ) +if(LIBC_COMPILER_HAS_FLOAT128) + list(APPEND TARGET_LIBM_ENTRYPOINTS + # math.h C23 _Float128 entrypoints + libc.src.math.ceilf128 + libc.src.math.copysignf128 + libc.src.math.fabsf128 + libc.src.math.floorf128 + libc.src.math.fmaxf128 + libc.src.math.fminf128 + libc.src.math.roundf128 + libc.src.math.sqrtf128 + libc.src.math.truncf128 + ) +endif() + if(LLVM_LIBC_FULL_BUILD) list(APPEND TARGET_LIBC_ENTRYPOINTS # compiler entrypoints (no corresponding header) diff --git a/libc/config/linux/x86_64/entrypoints.txt b/libc/config/linux/x86_64/entrypoints.txt index a1236817d2d18da963007ba7080756291e665d0a..b35fc9fc6866b4e50ece504ac98d64d5ec131c1c 100644 --- a/libc/config/linux/x86_64/entrypoints.txt +++ b/libc/config/linux/x86_64/entrypoints.txt @@ -102,6 +102,16 @@ set(TARGET_LIBC_ENTRYPOINTS libc.src.stdbit.stdc_leading_ones_ui libc.src.stdbit.stdc_leading_ones_ul libc.src.stdbit.stdc_leading_ones_ull + libc.src.stdbit.stdc_trailing_zeros_uc + libc.src.stdbit.stdc_trailing_zeros_us + libc.src.stdbit.stdc_trailing_zeros_ui + libc.src.stdbit.stdc_trailing_zeros_ul + libc.src.stdbit.stdc_trailing_zeros_ull + libc.src.stdbit.stdc_trailing_ones_uc + libc.src.stdbit.stdc_trailing_ones_us + libc.src.stdbit.stdc_trailing_ones_ui + libc.src.stdbit.stdc_trailing_ones_ul + libc.src.stdbit.stdc_trailing_ones_ull # stdlib.h entrypoints libc.src.stdlib.abs diff --git a/libc/docs/math/index.rst b/libc/docs/math/index.rst index bf58f559c451411c2ac7d5cf7d426da78fb3f8dd..3af7e106fc99380ca3440ea1304fb0aeab602939 100644 --- a/libc/docs/math/index.rst +++ b/libc/docs/math/index.rst @@ -114,7 +114,7 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | ceill | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| ceilf128 | |check| | | | | | | | | | | | | +| ceilf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | copysign | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ @@ -122,7 +122,7 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | copysignl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| copysignf128 | |check| | |check| | | | | | | | | | | | +| copysignf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fabs | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ @@ -130,7 +130,7 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fabsl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| fabsf128 | |check| | |check| | | | | | | | | | | | +| fabsf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fdim | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ @@ -144,13 +144,13 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | floorl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| floorf128 | |check| | | | | | | | | | | | | +| floorf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fmax | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fmaxf | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| fmaxf128 | |check| | | | | | | | | | | | | +| fmaxf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fmaxl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ @@ -158,7 +158,7 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fminf | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| fminf128 | |check| | | | | | | | | | | | | +| fminf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | fminl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ @@ -270,7 +270,7 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | roundl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| roundf128 | |check| | | | | | | | | | | | | +| roundf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | scalbn | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ @@ -284,7 +284,7 @@ Basic Operations +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ | truncl | |check| | |check| | |check| | |check| | |check| | | | |check| | |check| | |check| | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ -| truncf128 | |check| | | | | | | | | | | | | +| truncf128 | |check| | |check| | | |check| | | | | | | | | | +--------------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+---------+ diff --git a/libc/include/CMakeLists.txt b/libc/include/CMakeLists.txt index 4f4d8434757d700168182729ae3985a3f4096316..332410453b54d1072112195ba47bfb8d81b0c586 100644 --- a/libc/include/CMakeLists.txt +++ b/libc/include/CMakeLists.txt @@ -73,6 +73,7 @@ add_gen_header( DEPENDS .llvm_libc_common_h .llvm-libc-types.imaxdiv_t + .llvm-libc-macros.inttypes_macros ) add_gen_header( diff --git a/libc/include/inttypes.h.def b/libc/include/inttypes.h.def index 94cdc2f21eaf70bbc709486b952b95ca17a0f6eb..a99d4e931f51458437065cf1cff92fcda999bc3c 100644 --- a/libc/include/inttypes.h.def +++ b/libc/include/inttypes.h.def @@ -10,6 +10,7 @@ #define LLVM_LIBC_INTTYPES_H #include <__llvm-libc-common.h> +#include #include %%public_api() diff --git a/libc/include/llvm-libc-macros/CMakeLists.txt b/libc/include/llvm-libc-macros/CMakeLists.txt index c5a7e742cadd138ace131189477503c53fb7fe98..562769a5e84cef0e011244f6376320a0f9a08599 100644 --- a/libc/include/llvm-libc-macros/CMakeLists.txt +++ b/libc/include/llvm-libc-macros/CMakeLists.txt @@ -221,3 +221,9 @@ add_macro_header( HDR wchar-macros.h ) + +add_macro_header( + inttypes_macros + HDR + inttypes-macros.h +) diff --git a/libc/include/llvm-libc-macros/inttypes-macros.h b/libc/include/llvm-libc-macros/inttypes-macros.h new file mode 100644 index 0000000000000000000000000000000000000000..fc3e2517f1947127f8f03cb7ffae72d5b0717589 --- /dev/null +++ b/libc/include/llvm-libc-macros/inttypes-macros.h @@ -0,0 +1,289 @@ +//===-- Definition of macros from inttypes.h ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +#ifndef __LLVM_LIBC_MACROS_INTTYPES_MACROS_H +#define __LLVM_LIBC_MACROS_INTTYPES_MACROS_H + +// fprintf/scanf format macros. +// POSIX.1-2008, Technical Corrigendum 1, XBD/TC1-2008/0050 [211] is applied. + +// clang provides these macros, so we don't need to define them. +// TODO: ISO C23 will provide binary notations. + +#ifndef __clang__ +#if __UINTPTR_MAX__ == __UINT64_MAX__ +#define __PRI64 "l" +#define __PRIPTR "l" +#elif __UINTPTR_MAX__ == __UINT32_MAX__ +#define __PRI64 "ll" +#define __PRIPTR "" +#else +// CHERI achitecture for example, has 128-bit pointers that use special "P" +// format. +#error "Unsupported pointer format" +#endif +#define __INT8_FMTd__ "hhd" +#define __INT16_FMTd__ "hd" +#define __INT32_FMTd__ "d" +#define __INT64_FMTd__ __PRI64 "d" +#define __INT_LEAST8_FMTd__ "hhd" +#define __INT_LEAST16_FMTd__ "hd" +#define __INT_LEAST32_FMTd__ "d" +#define __INT_LEAST64_FMTd__ __PRI64 "d" +#define __INT_FAST8_FMTd__ "hhd" +#define __INT_FAST16_FMTd__ "hd" +#define __INT_FAST32_FMTd__ "d" +#define __INT_FAST64_FMTd__ __PRI64 "d" +#define __INTMAX_FMTd__ __PRI64 "d" +#define __INTPTR_FMTd__ __PRIPTR "d" + +#define __INT8_FMTi__ "hhi" +#define __INT16_FMTi__ "hi" +#define __INT32_FMTi__ "i" +#define __INT64_FMTi__ __PRI64 "i" +#define __INT_LEAST8_FMTi__ "hhi" +#define __INT_LEAST16_FMTi__ "hi" +#define __INT_LEAST32_FMTi__ "i" +#define __INT_LEAST64_FMTi__ __PRI64 "i" +#define __INT_FAST8_FMTi__ "hhi" +#define __INT_FAST16_FMTi__ "hi" +#define __INT_FAST32_FMTi__ "i" +#define __INT_FAST64_FMTi__ __PRI64 "i" +#define __INTMAX_FMTi__ __PRI64 "i" +#define __INTPTR_FMTi__ __PRIPTR "i" + +#define __UINT8_FMTo__ "hho" +#define __UINT16_FMTo__ "ho" +#define __UINT32_FMTo__ "o" +#define __UINT64_FMTo__ __PRI64 "o" +#define __UINT_LEAST8_FMTo__ "hho" +#define __UINT_LEAST16_FMTo__ "ho" +#define __UINT_LEAST32_FMTo__ "o" +#define __UINT_LEAST64_FMTo__ __PRI64 "o" +#define __UINT_FAST8_FMTo__ "hho" +#define __UINT_FAST16_FMTo__ "ho" +#define __UINT_FAST32_FMTo__ "o" +#define __UINT_FAST64_FMTo__ __PRI64 "o" +#define __UINTMAX_FMTo__ __PRI64 "o" +#define __UINTPTR_FMTo__ __PRIPTR "o" + +#define __UINT8_FMTu__ "hhu" +#define __UINT16_FMTu__ "hu" +#define __UINT32_FMTu__ "u" +#define __UINT64_FMTu__ __PRI64 "u" +#define __UINT_LEAST8_FMTu__ "hhu" +#define __UINT_LEAST16_FMTu__ "hu" +#define __UINT_LEAST32_FMTu__ "u" +#define __UINT_LEAST64_FMTu__ __PRI64 "u" +#define __UINT_FAST8_FMTu__ "hhu" +#define __UINT_FAST16_FMTu__ "hu" +#define __UINT_FAST32_FMTu__ "u" +#define __UINT_FAST64_FMTu__ __PRI64 "u" +#define __UINTMAX_FMTu__ __PRI64 "u" +#define __UINTPTR_FMTu__ __PRIPTR "u" + +#define __UINT8_FMTx__ "hhx" +#define __UINT16_FMTx__ "hx" +#define __UINT32_FMTx__ "x" +#define __UINT64_FMTx__ __PRI64 "x" +#define __UINT_LEAST8_FMTx__ "hhx" +#define __UINT_LEAST16_FMTx__ "hx" +#define __UINT_LEAST32_FMTx__ "x" +#define __UINT_LEAST64_FMTx__ __PRI64 "x" +#define __UINT_FAST8_FMTx__ "hhx" +#define __UINT_FAST16_FMTx__ "hx" +#define __UINT_FAST32_FMTx__ "x" +#define __UINT_FAST64_FMTx__ __PRI64 "x" +#define __UINTMAX_FMTx__ __PRI64 "x" +#define __UINTPTR_FMTx__ __PRIPTR "x" + +#define __UINT8_FMTX__ "hhX" +#define __UINT16_FMTX__ "hX" +#define __UINT32_FMTX__ "X" +#define __UINT64_FMTX__ __PRI64 "X" +#define __UINT_LEAST8_FMTX__ "hhX" +#define __UINT_LEAST16_FMTX__ "hX" +#define __UINT_LEAST32_FMTX__ "X" +#define __UINT_LEAST64_FMTX__ __PRI64 "X" +#define __UINT_FAST8_FMTX__ "hhX" +#define __UINT_FAST16_FMTX__ "hX" +#define __UINT_FAST32_FMTX__ "X" +#define __UINT_FAST64_FMTX__ __PRI64 "X" +#define __UINTMAX_FMTX__ __PRI64 "X" +#define __UINTPTR_FMTX__ __PRIPTR "X" +#endif + +// The fprintf() macros for signed integers. +#define PRId8 __INT8_FMTd__ +#define PRId16 __INT16_FMTd__ +#define PRId32 __INT32_FMTd__ +#define PRId64 __INT64_FMTd__ +#define PRIdLEAST8 __INT_LEAST8_FMTd__ +#define PRIdLEAST16 __INT_LEAST16_FMTd__ +#define PRIdLEAST32 __INT_LEAST32_FMTd__ +#define PRIdLEAST64 __INT_LEAST64_FMTd__ +#define PRIdFAST8 __INT_FAST8_FMTd__ +#define PRIdFAST16 __INT_FAST16_FMTd__ +#define PRIdFAST32 __INT_FAST32_FMTd__ +#define PRIdFAST64 __INT_FAST64_FMTd__ +#define PRIdMAX __INTMAX_FMTd__ +#define PRIdPTR __INTPTR_FMTd__ + +#define PRIi8 __INT8_FMTi__ +#define PRIi16 __INT16_FMTi__ +#define PRIi32 __INT32_FMTi__ +#define PRIi64 __INT64_FMTi__ +#define PRIiLEAST8 __INT_LEAST8_FMTi__ +#define PRIiLEAST16 __INT_LEAST16_FMTi__ +#define PRIiLEAST32 __INT_LEAST32_FMTi__ +#define PRIiLEAST64 __INT_LEAST64_FMTi__ +#define PRIiFAST8 __INT_FAST8_FMTi__ +#define PRIiFAST16 __INT_FAST16_FMTi__ +#define PRIiFAST32 __INT_FAST32_FMTi__ +#define PRIiFAST64 __INT_FAST64_FMTi__ +#define PRIiMAX __INTMAX_FMTi__ +#define PRIiPTR __INTPTR_FMTi__ + +// The fprintf() macros for unsigned integers. +#define PRIo8 __UINT8_FMTo__ +#define PRIo16 __UINT16_FMTo__ +#define PRIo32 __UINT32_FMTo__ +#define PRIo64 __UINT64_FMTo__ +#define PRIoLEAST8 __UINT_LEAST8_FMTo__ +#define PRIoLEAST16 __UINT_LEAST16_FMTo__ +#define PRIoLEAST32 __UINT_LEAST32_FMTo__ +#define PRIoLEAST64 __UINT_LEAST64_FMTo__ +#define PRIoFAST8 __UINT_FAST8_FMTo__ +#define PRIoFAST16 __UINT_FAST16_FMTo__ +#define PRIoFAST32 __UINT_FAST32_FMTo__ +#define PRIoFAST64 __UINT_FAST64_FMTo__ +#define PRIoMAX __UINTMAX_FMTo__ +#define PRIoPTR __UINTPTR_FMTo__ + +#define PRIu8 __UINT8_FMTu__ +#define PRIu16 __UINT16_FMTu__ +#define PRIu32 __UINT32_FMTu__ +#define PRIu64 __UINT64_FMTu__ +#define PRIuLEAST8 __UINT_LEAST8_FMTu__ +#define PRIuLEAST16 __UINT_LEAST16_FMTu__ +#define PRIuLEAST32 __UINT_LEAST32_FMTu__ +#define PRIuLEAST64 __UINT_LEAST64_FMTu__ +#define PRIuFAST8 __UINT_FAST8_FMTu__ +#define PRIuFAST16 __UINT_FAST16_FMTu__ +#define PRIuFAST32 __UINT_FAST32_FMTu__ +#define PRIuFAST64 __UINT_FAST64_FMTu__ +#define PRIuMAX __UINTMAX_FMTu__ +#define PRIuPTR __UINTPTR_FMTu__ + +#define PRIx8 __UINT8_FMTx__ +#define PRIx16 __UINT16_FMTx__ +#define PRIx32 __UINT32_FMTx__ +#define PRIx64 __UINT64_FMTx__ +#define PRIxLEAST8 __UINT_LEAST8_FMTx__ +#define PRIxLEAST16 __UINT_LEAST16_FMTx__ +#define PRIxLEAST32 __UINT_LEAST32_FMTx__ +#define PRIxLEAST64 __UINT_LEAST64_FMTx__ +#define PRIxFAST8 __UINT_FAST8_FMTx__ +#define PRIxFAST16 __UINT_FAST16_FMTx__ +#define PRIxFAST32 __UINT_FAST32_FMTx__ +#define PRIxFAST64 __UINT_FAST64_FMTx__ +#define PRIxMAX __UINTMAX_FMTx__ +#define PRIxPTR __UINTPTR_FMTx__ + +#define PRIX8 __UINT8_FMTX__ +#define PRIX16 __UINT16_FMTX__ +#define PRIX32 __UINT32_FMTX__ +#define PRIX64 __UINT64_FMTX__ +#define PRIXLEAST8 __UINT_LEAST8_FMTX__ +#define PRIXLEAST16 __UINT_LEAST16_FMTX__ +#define PRIXLEAST32 __UINT_LEAST32_FMTX__ +#define PRIXLEAST64 __UINT_LEAST64_FMTX__ +#define PRIXFAST8 __UINT_FAST8_FMTX__ +#define PRIXFAST16 __UINT_FAST16_FMTX__ +#define PRIXFAST32 __UINT_FAST32_FMTX__ +#define PRIXFAST64 __UINT_FAST64_FMTX__ +#define PRIXMAX __UINTMAX_FMTX__ +#define PRIXPTR __UINTPTR_FMTX__ + +// The fscanf() macros for signed integers. +#define SCNd8 __INT8_FMTd__ +#define SCNd16 __INT16_FMTd__ +#define SCNd32 __INT32_FMTd__ +#define SCNd64 __INT64_FMTd__ +#define SCNdLEAST8 __INT_LEAST8_FMTd__ +#define SCNdLEAST16 __INT_LEAST16_FMTd__ +#define SCNdLEAST32 __INT_LEAST32_FMTd__ +#define SCNdLEAST64 __INT_LEAST64_FMTd__ +#define SCNdFAST8 __INT_FAST8_FMTd__ +#define SCNdFAST16 __INT_FAST16_FMTd__ +#define SCNdFAST32 __INT_FAST32_FMTd__ +#define SCNdFAST64 __INT_FAST64_FMTd__ +#define SCNdMAX __INTMAX_FMTd__ +#define SCNdPTR __INTPTR_FMTd__ + +#define SCNi8 __INT8_FMTi__ +#define SCNi16 __INT16_FMTi__ +#define SCNi32 __INT32_FMTi__ +#define SCNi64 __INT64_FMTi__ +#define SCNiLEAST8 __INT_LEAST8_FMTi__ +#define SCNiLEAST16 __INT_LEAST16_FMTi__ +#define SCNiLEAST32 __INT_LEAST32_FMTi__ +#define SCNiLEAST64 __INT_LEAST64_FMTi__ +#define SCNiFAST8 __INT_FAST8_FMTi__ +#define SCNiFAST16 __INT_FAST16_FMTi__ +#define SCNiFAST32 __INT_FAST32_FMTi__ +#define SCNiFAST64 __INT_FAST64_FMTi__ +#define SCNiMAX __INTMAX_FMTi__ +#define SCNiPTR __INTPTR_FMTi__ + +// The fscanf() macros for unsigned integers. +#define SCNo8 __UINT8_FMTo__ +#define SCNo16 __UINT16_FMTo__ +#define SCNo32 __UINT32_FMTo__ +#define SCNo64 __UINT64_FMTo__ +#define SCNoLEAST8 __UINT_LEAST8_FMTo__ +#define SCNoLEAST16 __UINT_LEAST16_FMTo__ +#define SCNoLEAST32 __UINT_LEAST32_FMTo__ +#define SCNoLEAST64 __UINT_LEAST64_FMTo__ +#define SCNoFAST8 __UINT_FAST8_FMTo__ +#define SCNoFAST16 __UINT_FAST16_FMTo__ +#define SCNoFAST32 __UINT_FAST32_FMTo__ +#define SCNoFAST64 __UINT_FAST64_FMTo__ +#define SCNoMAX __UINTMAX_FMTo__ +#define SCNoPTR __UINTPTR_FMTo__ + +#define SCNu8 __UINT8_FMTu__ +#define SCNu16 __UINT16_FMTu__ +#define SCNu32 __UINT32_FMTu__ +#define SCNu64 __UINT64_FMTu__ +#define SCNuLEAST8 __UINT_LEAST8_FMTu__ +#define SCNuLEAST16 __UINT_LEAST16_FMTu__ +#define SCNuLEAST32 __UINT_LEAST32_FMTu__ +#define SCNuLEAST64 __UINT_LEAST64_FMTu__ +#define SCNuFAST8 __UINT_FAST8_FMTu__ +#define SCNuFAST16 __UINT_FAST16_FMTu__ +#define SCNuFAST32 __UINT_FAST32_FMTu__ +#define SCNuFAST64 __UINT_FAST64_FMTu__ +#define SCNuMAX __UINTMAX_FMTu__ +#define SCNuPTR __UINTPTR_FMTu__ + +#define SCNx8 __UINT8_FMTx__ +#define SCNx16 __UINT16_FMTx__ +#define SCNx32 __UINT32_FMTx__ +#define SCNx64 __UINT64_FMTx__ +#define SCNxLEAST8 __UINT_LEAST8_FMTx__ +#define SCNxLEAST16 __UINT_LEAST16_FMTx__ +#define SCNxLEAST32 __UINT_LEAST32_FMTx__ +#define SCNxLEAST64 __UINT_LEAST64_FMTx__ +#define SCNxFAST8 __UINT_FAST8_FMTx__ +#define SCNxFAST16 __UINT_FAST16_FMTx__ +#define SCNxFAST32 __UINT_FAST32_FMTx__ +#define SCNxFAST64 __UINT_FAST64_FMTx__ +#define SCNxMAX __UINTMAX_FMTx__ +#define SCNxPTR __UINTPTR_FMTx__ + +#endif // __LLVM_LIBC_MACROS_INTTYPES_MACROS_H diff --git a/libc/include/llvm-libc-macros/stdbit-macros.h b/libc/include/llvm-libc-macros/stdbit-macros.h index cc964a5268b0d743387e1a6972922e10b11839ce..c55529e5c0e943a9e896be41a5f79ed2decbb0c6 100644 --- a/libc/include/llvm-libc-macros/stdbit-macros.h +++ b/libc/include/llvm-libc-macros/stdbit-macros.h @@ -9,6 +9,7 @@ #ifndef __LLVM_LIBC_MACROS_STDBIT_MACROS_H #define __LLVM_LIBC_MACROS_STDBIT_MACROS_H +// TODO(https://github.com/llvm/llvm-project/issues/80509): support _BitInt(). #ifdef __cplusplus inline unsigned stdc_leading_zeros(unsigned char x) { return stdc_leading_zeros_uc(x); @@ -40,6 +41,36 @@ inline unsigned stdc_leading_ones(unsigned long x) { inline unsigned stdc_leading_ones(unsigned long long x) { return stdc_leading_ones_ull(x); } +inline unsigned stdc_trailing_zeros(unsigned char x) { + return stdc_trailing_zeros_uc(x); +} +inline unsigned stdc_trailing_zeros(unsigned short x) { + return stdc_trailing_zeros_us(x); +} +inline unsigned stdc_trailing_zeros(unsigned x) { + return stdc_trailing_zeros_ui(x); +} +inline unsigned stdc_trailing_zeros(unsigned long x) { + return stdc_trailing_zeros_ul(x); +} +inline unsigned stdc_trailing_zeros(unsigned long long x) { + return stdc_trailing_zeros_ull(x); +} +inline unsigned stdc_trailing_ones(unsigned char x) { + return stdc_trailing_ones_uc(x); +} +inline unsigned stdc_trailing_ones(unsigned short x) { + return stdc_trailing_ones_us(x); +} +inline unsigned stdc_trailing_ones(unsigned x) { + return stdc_trailing_ones_ui(x); +} +inline unsigned stdc_trailing_ones(unsigned long x) { + return stdc_trailing_ones_ul(x); +} +inline unsigned stdc_trailing_ones(unsigned long long x) { + return stdc_trailing_ones_ull(x); +} #else #define stdc_leading_zeros(x) \ _Generic((x), \ @@ -55,6 +86,20 @@ inline unsigned stdc_leading_ones(unsigned long long x) { unsigned: stdc_leading_ones_ui, \ unsigned long: stdc_leading_ones_ul, \ unsigned long long: stdc_leading_ones_ull)(x) +#define stdc_trailing_zeros(x) \ + _Generic((x), \ + unsigned char: stdc_trailing_zeros_uc, \ + unsigned short: stdc_trailing_zeros_us, \ + unsigned: stdc_trailing_zeros_ui, \ + unsigned long: stdc_trailing_zeros_ul, \ + unsigned long long: stdc_trailing_zeros_ull)(x) +#define stdc_trailing_ones(x) \ + _Generic((x), \ + unsigned char: stdc_trailing_ones_uc, \ + unsigned short: stdc_trailing_ones_us, \ + unsigned: stdc_trailing_ones_ui, \ + unsigned long: stdc_trailing_ones_ul, \ + unsigned long long: stdc_trailing_ones_ull)(x) #endif // __cplusplus #endif // __LLVM_LIBC_MACROS_STDBIT_MACROS_H diff --git a/libc/spec/stdc.td b/libc/spec/stdc.td index 607dda7c9041f89de6b52bd5e4547b6b065b72c2..97dabbc5cf07afd5c7b2171c94e0469322726718 100644 --- a/libc/spec/stdc.td +++ b/libc/spec/stdc.td @@ -775,7 +775,10 @@ def StdC : StandardSpec<"stdc"> { HeaderSpec StdBit = HeaderSpec< "stdbit.h", [ - Macro<"stdc_leading_zeros"> + Macro<"stdc_leading_zeros">, + Macro<"stdc_leading_ones">, + Macro<"stdc_trailing_zeros">, + Macro<"stdc_trailing_ones"> ], // Macros [], // Types [], // Enumerations @@ -789,7 +792,17 @@ def StdC : StandardSpec<"stdc"> { FunctionSpec<"stdc_leading_ones_us", RetValSpec, [ArgSpec]>, FunctionSpec<"stdc_leading_ones_ui", RetValSpec, [ArgSpec]>, FunctionSpec<"stdc_leading_ones_ul", RetValSpec, [ArgSpec]>, - FunctionSpec<"stdc_leading_ones_ull", RetValSpec, [ArgSpec]> + FunctionSpec<"stdc_leading_ones_ull", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_uc", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_us", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_ui", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_ul", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_zeros_ull", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_ones_uc", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_ones_us", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_ones_ui", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_ones_ul", RetValSpec, [ArgSpec]>, + FunctionSpec<"stdc_trailing_ones_ull", RetValSpec, [ArgSpec]> ] // Functions >; diff --git a/libc/src/__support/FPUtil/CMakeLists.txt b/libc/src/__support/FPUtil/CMakeLists.txt index 47c102a47426c97a9b6904978ce545a707c42027..3307d33434f0b303cbde5416803e1eae8126f0db 100644 --- a/libc/src/__support/FPUtil/CMakeLists.txt +++ b/libc/src/__support/FPUtil/CMakeLists.txt @@ -143,16 +143,6 @@ add_header_library( libc.src.__support.uint128 ) -add_header_library( - xfloat - HDRS - XFloat.h - DEPENDS - .fp_bits - .normal_float - libc.src.__support.uint -) - add_header_library( sqrt HDRS diff --git a/libc/src/__support/FPUtil/XFloat.h b/libc/src/__support/FPUtil/XFloat.h deleted file mode 100644 index fe334f8a33011d32b15ff16b6a1027bd690fe259..0000000000000000000000000000000000000000 --- a/libc/src/__support/FPUtil/XFloat.h +++ /dev/null @@ -1,180 +0,0 @@ -//===-- Utility class to manipulate wide floats. ----------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "FPBits.h" -#include "NormalFloat.h" -#include "src/__support/UInt.h" - -#include - -namespace LIBC_NAMESPACE { -namespace fputil { - -// Store and manipulate positive double precision numbers at |Precision| bits. -template class XFloat { - static constexpr uint64_t OneMask = (uint64_t(1) << 63); - UInt man; - static constexpr uint64_t WORDCOUNT = Precision / 64; - int exp; - - size_t bit_width(uint64_t x) { - if (x == 0) - return 0; - size_t shift = 0; - while ((OneMask & x) == 0) { - ++shift; - x <<= 1; - } - return 64 - shift; - } - -public: - XFloat() : exp(0) { - for (int i = 0; i < WORDCOUNT; ++i) - man[i] = 0; - } - - XFloat(const XFloat &other) : exp(other.exp) { - for (int i = 0; i < WORDCOUNT; ++i) - man[i] = other.man[i]; - } - - explicit XFloat(double x) { - auto xn = NormalFloat(x); - exp = xn.exponent; - man[WORDCOUNT - 1] = xn.mantissa << 11; - for (int i = 0; i < WORDCOUNT - 1; ++i) - man[i] = 0; - } - - XFloat(int e, const UInt &bits) : exp(e) { - for (size_t i = 0; i < WORDCOUNT; ++i) - man[i] = bits[i]; - } - - // Multiply this number with x and store the result in this number. - void mul(double x) { - auto xn = NormalFloat(x); - exp += xn.exponent; - uint64_t carry = man.mul(xn.mantissa << 11); - size_t carry_width = bit_width(carry); - carry_width = (carry_width == 64 ? 64 : 63); - man.shift_right(carry_width); - man[WORDCOUNT - 1] = man[WORDCOUNT - 1] + (carry << (64 - carry_width)); - exp += carry_width == 64 ? 1 : 0; - normalize(); - } - - void drop_int() { - if (exp < 0) - return; - if (exp > int(Precision - 1)) { - for (size_t i = 0; i < WORDCOUNT; ++i) - man[i] = 0; - return; - } - - man.shift_left(exp + 1); - man.shift_right(exp + 1); - - normalize(); - } - - double mul(const XFloat &other) { - constexpr size_t row_words = 2 * WORDCOUNT + 1; - constexpr size_t row_precision = row_words * 64; - constexpr size_t result_bits = 2 * Precision; - UInt rows[WORDCOUNT]; - - for (size_t r = 0; r < WORDCOUNT; ++r) { - for (size_t i = 0; i < row_words; ++i) { - if (i < WORDCOUNT) - rows[r][i] = man[i]; - else - rows[r][i] = 0; - } - rows[r].mul(other.man[r]); - rows[r].shift_left(r * 64); - } - - for (size_t r = 1; r < WORDCOUNT; ++r) { - rows[0].add(rows[r]); - } - int result_exp = exp + other.exp; - uint64_t carry = rows[0][row_words - 1]; - if (carry) { - size_t carry_width = bit_width(carry); - rows[0].shift_right(carry_width); - rows[0][row_words - 2] = - rows[0][row_words - 2] + (carry << (64 - carry_width)); - result_exp += carry_width; - } - - if (rows[0][row_words - 2] & OneMask) { - ++result_exp; - } else { - rows[0].shift_left(1); - } - - UInt result_man; - for (size_t i = 0; i < result_bits / 64; ++i) - result_man[i] = rows[0][i]; - XFloat result(result_exp, result_man); - result.normalize(); - return double(result); - } - - explicit operator double() { - normalize(); - - constexpr uint64_t one = uint64_t(1) << 10; - constexpr uint64_t excess_mask = (one << 1) - 1; - uint64_t excess = man[WORDCOUNT - 1] & excess_mask; - uint64_t new_man = man[WORDCOUNT - 1] >> 11; - if (excess > one) { - // We have to round up. - ++new_man; - } else if (excess == one) { - bool greater_than_one = false; - for (size_t i = 0; i < WORDCOUNT - 1; ++i) { - greater_than_one = (man[i] != 0); - if (greater_than_one) - break; - } - if (greater_than_one || (new_man & 1) != 0) { - ++new_man; - } - } - - if (new_man == (uint64_t(1) << 53)) - ++exp; - - // We use NormalFloat as it can produce subnormal numbers or underflow to 0 - // if necessary. - NormalFloat d(exp, new_man, 0); - return double(d); - } - - // Normalizes this number. - void normalize() { - uint64_t man_bits = 0; - for (size_t i = 0; i < WORDCOUNT; ++i) - man_bits |= man[i]; - - if (man_bits == 0) - return; - - while ((man[WORDCOUNT - 1] & OneMask) == 0) { - man.shift_left(1); - --exp; - } - } -}; - -} // namespace fputil -} // namespace LIBC_NAMESPACE diff --git a/libc/src/__support/GPU/amdgpu/utils.h b/libc/src/__support/GPU/amdgpu/utils.h index 96e3efccb3b5a5c4564f1be5cf8a8589a5369851..58bbe29cb3a7d79327b7d099496a5bab5a559c93 100644 --- a/libc/src/__support/GPU/amdgpu/utils.h +++ b/libc/src/__support/GPU/amdgpu/utils.h @@ -113,10 +113,7 @@ LIBC_INLINE uint32_t get_lane_size() { return LANE_SIZE; } /// Returns the id of the thread inside of an AMD wavefront executing together. [[clang::convergent]] LIBC_INLINE uint32_t get_lane_id() { - if constexpr (LANE_SIZE == 64) - return __builtin_amdgcn_mbcnt_hi(~0u, __builtin_amdgcn_mbcnt_lo(~0u, 0u)); - else - return __builtin_amdgcn_mbcnt_lo(~0u, 0u); + return __builtin_amdgcn_mbcnt_hi(~0u, __builtin_amdgcn_mbcnt_lo(~0u, 0u)); } /// Returns the bit-mask of active threads in the current wavefront. @@ -134,11 +131,7 @@ LIBC_INLINE uint32_t get_lane_size() { return LANE_SIZE; } [[clang::convergent]] LIBC_INLINE uint64_t ballot(uint64_t lane_mask, bool x) { // the lane_mask & gives the nvptx semantics when lane_mask is a subset of // the active threads - if constexpr (LANE_SIZE == 64) { - return lane_mask & __builtin_amdgcn_ballot_w64(x); - } else { - return lane_mask & __builtin_amdgcn_ballot_w32(x); - } + return lane_mask & __builtin_amdgcn_ballot_w64(x); } /// Waits for all the threads in the block to converge and issues a fence. @@ -153,15 +146,8 @@ LIBC_INLINE uint32_t get_lane_size() { return LANE_SIZE; } } /// Returns the current value of the GPU's processor clock. -/// NOTE: The RDNA3 and RDNA2 architectures use a 20-bit cycle cycle counter. -LIBC_INLINE uint64_t processor_clock() { - if constexpr (LIBC_HAS_BUILTIN(__builtin_amdgcn_s_memtime)) - return __builtin_amdgcn_s_memtime(); - else if constexpr (LIBC_HAS_BUILTIN(__builtin_readcyclecounter)) - return __builtin_readcyclecounter(); - else - return 0; -} +/// NOTE: The RDNA3 and RDNA2 architectures use a 20-bit cycle counter. +LIBC_INLINE uint64_t processor_clock() { return __builtin_readcyclecounter(); } /// Returns a fixed-frequency timestamp. The actual frequency is dependent on /// the card and can only be queried via the driver. diff --git a/libc/src/__support/float_to_string.h b/libc/src/__support/float_to_string.h index 1431aeffa5b21082420c19516b57d246b7288f80..f30110d47b2192f36ebd8d99b48dda6ad07673d3 100644 --- a/libc/src/__support/float_to_string.h +++ b/libc/src/__support/float_to_string.h @@ -651,7 +651,8 @@ template <> class FloatToString { int int_block_index = 0; static constexpr size_t BLOCK_BUFFER_LEN = - internal::div_ceil(internal::log10_pow2(FLOAT_AS_INT_WIDTH), BLOCK_SIZE); + internal::div_ceil(internal::log10_pow2(FLOAT_AS_INT_WIDTH), BLOCK_SIZE) + + 1; BlockInt block_buffer[BLOCK_BUFFER_LEN] = {0}; size_t block_buffer_valid = 0; @@ -693,6 +694,7 @@ template <> class FloatToString { int_block_index = 0; while (float_as_int > 0) { + LIBC_ASSERT(int_block_index < static_cast(BLOCK_BUFFER_LEN)); block_buffer[int_block_index] = grab_digits(float_as_int); ++int_block_index; } @@ -785,6 +787,8 @@ public: if (block_index > static_cast(block_buffer_valid) || block_index < 0) return 0; + LIBC_ASSERT(block_index < static_cast(BLOCK_BUFFER_LEN)); + return block_buffer[block_index]; } diff --git a/libc/src/errno/libc_errno.cpp b/libc/src/errno/libc_errno.cpp index e54bdd156d6bc43cf2ae92f8785ea1450a855765..30b0a67a3241d81ff6c64c95422dd4d4e7c4d4ce 100644 --- a/libc/src/errno/libc_errno.cpp +++ b/libc/src/errno/libc_errno.cpp @@ -44,5 +44,7 @@ LIBC_NAMESPACE::Errno::operator int() { return errno; } #endif // LIBC_FULL_BUILD +namespace LIBC_NAMESPACE { // Define the global `libc_errno` instance. -LIBC_NAMESPACE::Errno libc_errno; +Errno libc_errno; +} // namespace LIBC_NAMESPACE diff --git a/libc/src/errno/libc_errno.h b/libc/src/errno/libc_errno.h index 632faeaaeff66a8c62040be48a596b065ac958cf..5afc0a41d348ae85179ffb6102f8dede6b8e0b11 100644 --- a/libc/src/errno/libc_errno.h +++ b/libc/src/errno/libc_errno.h @@ -39,8 +39,9 @@ struct Errno { void operator=(int); operator int(); }; -} // namespace LIBC_NAMESPACE -extern LIBC_NAMESPACE::Errno libc_errno; +extern Errno libc_errno; + +} // namespace LIBC_NAMESPACE #endif // LLVM_LIBC_SRC_ERRNO_LIBC_ERRNO_H diff --git a/libc/src/math/gpu/vendor/amdgpu/platform.h b/libc/src/math/gpu/vendor/amdgpu/platform.h index 160a8508cd8b95747ed262b5e60643d03b4d3bd6..e5a9f810cd107295f685ff3bd57c5ff296e1c157 100644 --- a/libc/src/math/gpu/vendor/amdgpu/platform.h +++ b/libc/src/math/gpu/vendor/amdgpu/platform.h @@ -32,87 +32,11 @@ extern const LIBC_INLINE_VAR uint8_t __oclc_correctly_rounded_sqrt32 = 1; // Disable finite math optimizations. extern const LIBC_INLINE_VAR uint8_t __oclc_finite_only_opt = 0; -#if defined(__gfx700__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7000; -#elif defined(__gfx701__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7001; -#elif defined(__gfx702__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7002; -#elif defined(__gfx703__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7003; -#elif defined(__gfx704__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7004; -#elif defined(__gfx705__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 7005; -#elif defined(__gfx801__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8001; -#elif defined(__gfx802__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8002; -#elif defined(__gfx803__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8003; -#elif defined(__gfx805__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8005; -#elif defined(__gfx810__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 8100; -#elif defined(__gfx900__) +// Set the ISA value to a high enough value that the ROCm device library math +// functions will assume we have fast FMA operations among other features. This +// is determined to be safe on all targets by looking at the source code. +// https://github.com/ROCm/ROCm-Device-Libs/blob/amd-stg-open/ocml/src/opts.h extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9000; -#elif defined(__gfx902__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9002; -#elif defined(__gfx904__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9004; -#elif defined(__gfx906__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9006; -#elif defined(__gfx908__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9008; -#elif defined(__gfx909__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9009; -#elif defined(__gfx90a__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9010; -#elif defined(__gfx90c__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9012; -#elif defined(__gfx940__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9400; -#elif defined(__gfx941__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9401; -#elif defined(__gfx942__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 9402; -#elif defined(__gfx1010__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10100; -#elif defined(__gfx1011__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10101; -#elif defined(__gfx1012__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10102; -#elif defined(__gfx1013__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10103; -#elif defined(__gfx1030__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10300; -#elif defined(__gfx1031__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10301; -#elif defined(__gfx1032__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10302; -#elif defined(__gfx1033__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10303; -#elif defined(__gfx1034__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10304; -#elif defined(__gfx1035__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10305; -#elif defined(__gfx1036__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 10306; -#elif defined(__gfx1100__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11000; -#elif defined(__gfx1101__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11001; -#elif defined(__gfx1102__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11002; -#elif defined(__gfx1103__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11003; -#elif defined(__gfx1150__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11500; -#elif defined(__gfx1151__) -extern const LIBC_INLINE_VAR uint32_t __oclc_ISA_version = 11501; -#else -#error "Unknown AMDGPU architecture" -#endif } // These aliases cause clang to emit the control constants with ODR linkage. diff --git a/libc/src/stdbit/CMakeLists.txt b/libc/src/stdbit/CMakeLists.txt index d7daff44dfda6d832cd64e162dd68854da29cd67..129621f139289491232c5021f1b493508b845959 100644 --- a/libc/src/stdbit/CMakeLists.txt +++ b/libc/src/stdbit/CMakeLists.txt @@ -1,99 +1,20 @@ -add_entrypoint_object( - stdc_leading_zeros_uc - SRCS - stdc_leading_zeros_uc.cpp - HDRS - stdc_leading_zeros_uc.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_us - SRCS - stdc_leading_zeros_us.cpp - HDRS - stdc_leading_zeros_us.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_ui - SRCS - stdc_leading_zeros_ui.cpp - HDRS - stdc_leading_zeros_ui.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_ul - SRCS - stdc_leading_zeros_ul.cpp - HDRS - stdc_leading_zeros_ul.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_zeros_ull - SRCS - stdc_leading_zeros_ull.cpp - HDRS - stdc_leading_zeros_ull.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_uc - SRCS - stdc_leading_ones_uc.cpp - HDRS - stdc_leading_ones_uc.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_us - SRCS - stdc_leading_ones_us.cpp - HDRS - stdc_leading_ones_us.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_ui - SRCS - stdc_leading_ones_ui.cpp - HDRS - stdc_leading_ones_ui.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_ul - SRCS - stdc_leading_ones_ul.cpp - HDRS - stdc_leading_ones_ul.h - DEPENDS - libc.src.__support.CPP.bit -) - -add_entrypoint_object( - stdc_leading_ones_ull - SRCS - stdc_leading_ones_ull.cpp - HDRS - stdc_leading_ones_ull.h - DEPENDS - libc.src.__support.CPP.bit -) +set(prefixes + leading_zeros + leading_ones + trailing_zeros + trailing_ones +) +set(suffixes c s i l ll) +foreach(prefix IN LISTS prefixes) + foreach(suffix IN LISTS suffixes) + add_entrypoint_object( + stdc_${prefix}_u${suffix} + SRCS + stdc_${prefix}_u${suffix}.cpp + HDRS + stdc_${prefix}_u${suffix}.h + DEPENDS + libc.src.__support.CPP.bit + ) + endforeach() +endforeach() diff --git a/libc/src/stdbit/stdc_trailing_ones_uc.cpp b/libc/src/stdbit/stdc_trailing_ones_uc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..eabb21367e2858025f8ff0c06305e223bbdcf759 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_uc.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_ones_uc ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_ones_uc.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_ones_uc, (unsigned char value)) { + return static_cast(cpp::countr_one(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_ones_uc.h b/libc/src/stdbit/stdc_trailing_ones_uc.h new file mode 100644 index 0000000000000000000000000000000000000000..9736e21e1f280aed8eacd6727b316dd388ccff03 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_uc.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_ones_uc --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UC_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UC_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_ones_uc(unsigned char value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UC_H diff --git a/libc/src/stdbit/stdc_trailing_ones_ui.cpp b/libc/src/stdbit/stdc_trailing_ones_ui.cpp new file mode 100644 index 0000000000000000000000000000000000000000..87eb54fe5f026b9f03c5dacbd010e43e6cf289ce --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_ui.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_ones_ui ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_ones_ui.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_ones_ui, (unsigned value)) { + return static_cast(cpp::countr_one(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_ones_ui.h b/libc/src/stdbit/stdc_trailing_ones_ui.h new file mode 100644 index 0000000000000000000000000000000000000000..aad7fcf0daf557bc0f19c297e56d7cfe99f9cc75 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_ui.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_ones_ui --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UI_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UI_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_ones_ui(unsigned value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UI_H diff --git a/libc/src/stdbit/stdc_trailing_ones_ul.cpp b/libc/src/stdbit/stdc_trailing_ones_ul.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d358a21ac3371f85a7c70c518475dd79c0d849c --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_ul.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_ones_ul ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_ones_ul.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_ones_ul, (unsigned long value)) { + return static_cast(cpp::countr_one(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_ones_ul.h b/libc/src/stdbit/stdc_trailing_ones_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..80589501b1ed23c9dabef26c53863d56fd4193fa --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_ul.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_ones_ul --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UL_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UL_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_ones_ul(unsigned long value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_UL_H diff --git a/libc/src/stdbit/stdc_trailing_ones_ull.cpp b/libc/src/stdbit/stdc_trailing_ones_ull.cpp new file mode 100644 index 0000000000000000000000000000000000000000..fb5fffe07817d06a1818da1caa72136c09e4c2c9 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_ull.cpp @@ -0,0 +1,21 @@ +//===-- Implementation of stdc_trailing_ones_ull --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_ones_ull.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_ones_ull, + (unsigned long long value)) { + return static_cast(cpp::countr_one(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_ones_ull.h b/libc/src/stdbit/stdc_trailing_ones_ull.h new file mode 100644 index 0000000000000000000000000000000000000000..3d3f0b306789acb47b4316599ead9837358688ad --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_ull.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_ones_ull --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_ULL_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_ULL_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_ones_ull(unsigned long long value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_ULL_H diff --git a/libc/src/stdbit/stdc_trailing_ones_us.cpp b/libc/src/stdbit/stdc_trailing_ones_us.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ee7ff4f78d489cb472f20b9f41f5856991f5e29c --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_us.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_ones_us ---------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_ones_us.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_ones_us, (unsigned short value)) { + return static_cast(cpp::countr_one(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_ones_us.h b/libc/src/stdbit/stdc_trailing_ones_us.h new file mode 100644 index 0000000000000000000000000000000000000000..b783cd22ad2debe4ef8f5cb24d10af55fca4c1cd --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_ones_us.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_ones_us --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_US_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_US_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_ones_us(unsigned short value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ONES_US_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_uc.cpp b/libc/src/stdbit/stdc_trailing_zeros_uc.cpp new file mode 100644 index 0000000000000000000000000000000000000000..36924c5a053adc27537a364ba1b7b2ca9c42ffbb --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_uc.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_uc --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_uc.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_uc, (unsigned char value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_uc.h b/libc/src/stdbit/stdc_trailing_zeros_uc.h new file mode 100644 index 0000000000000000000000000000000000000000..866201e5acea815e4fd8a92634af7c2495c556f6 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_uc.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_uc --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UC_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UC_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_uc(unsigned char value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UC_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_ui.cpp b/libc/src/stdbit/stdc_trailing_zeros_ui.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a264fd97f251f76baa97d57db10a1b97aa12b7d7 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ui.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_ui --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_ui.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_ui, (unsigned value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_ui.h b/libc/src/stdbit/stdc_trailing_zeros_ui.h new file mode 100644 index 0000000000000000000000000000000000000000..0642e312f4fe73246a27cf1b448c0a6a09f1450e --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ui.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_ui --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UI_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UI_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_ui(unsigned value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UI_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_ul.cpp b/libc/src/stdbit/stdc_trailing_zeros_ul.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8e0c36cb099650088e2c24d587646c2d6b3790c9 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ul.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_ul --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_ul.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_ul, (unsigned long value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_ul.h b/libc/src/stdbit/stdc_trailing_zeros_ul.h new file mode 100644 index 0000000000000000000000000000000000000000..e10b4474753a0a1f2ac4ef91ba97c9f29dbfe204 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ul.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_ul --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UL_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UL_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_ul(unsigned long value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_UL_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_ull.cpp b/libc/src/stdbit/stdc_trailing_zeros_ull.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77cb20cb1ba45dbe07666a6643f7d50aeebfaa80 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ull.cpp @@ -0,0 +1,21 @@ +//===-- Implementation of stdc_trailing_zeros_ull -------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_ull.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_ull, + (unsigned long long value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_ull.h b/libc/src/stdbit/stdc_trailing_zeros_ull.h new file mode 100644 index 0000000000000000000000000000000000000000..f95169d29f45edf868708f93a1a84050719f7fcf --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_ull.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_ull -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_ULL_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_ULL_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_ull(unsigned long long value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_ULL_H diff --git a/libc/src/stdbit/stdc_trailing_zeros_us.cpp b/libc/src/stdbit/stdc_trailing_zeros_us.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a5b9f4a7d849856c7a2e3d94fabdfddebc2aa77a --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_us.cpp @@ -0,0 +1,20 @@ +//===-- Implementation of stdc_trailing_zeros_us --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/stdbit/stdc_trailing_zeros_us.h" + +#include "src/__support/CPP/bit.h" +#include "src/__support/common.h" + +namespace LIBC_NAMESPACE { + +LLVM_LIBC_FUNCTION(unsigned, stdc_trailing_zeros_us, (unsigned short value)) { + return static_cast(cpp::countr_zero(value)); +} + +} // namespace LIBC_NAMESPACE diff --git a/libc/src/stdbit/stdc_trailing_zeros_us.h b/libc/src/stdbit/stdc_trailing_zeros_us.h new file mode 100644 index 0000000000000000000000000000000000000000..ddbdf0d647abdd22dc1e1aea79a6a861f850b311 --- /dev/null +++ b/libc/src/stdbit/stdc_trailing_zeros_us.h @@ -0,0 +1,18 @@ +//===-- Implementation header for stdc_trailing_zeros_us --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_US_H +#define LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_US_H + +namespace LIBC_NAMESPACE { + +unsigned stdc_trailing_zeros_us(unsigned short value); + +} // namespace LIBC_NAMESPACE + +#endif // LLVM_LIBC_SRC_STDBIT_STDC_TRAILING_ZEROS_US_H diff --git a/libc/src/stdio/printf_core/converter.cpp b/libc/src/stdio/printf_core/converter.cpp index 74a36cbf7432fbe53e447b47ffb77b48983048e1..52412aef3c5c150b624e703198c253232348f0c8 100644 --- a/libc/src/stdio/printf_core/converter.cpp +++ b/libc/src/stdio/printf_core/converter.cpp @@ -58,6 +58,8 @@ int convert(Writer *writer, const FormatSection &to_conv) { case 'o': case 'x': case 'X': + case 'b': + case 'B': return convert_int(writer, to_conv); #ifndef LIBC_COPT_PRINTF_DISABLE_FLOAT case 'f': diff --git a/libc/src/stdio/printf_core/int_converter.h b/libc/src/stdio/printf_core/int_converter.h index 7744d801cbc189f5c3ce445b4ec4584236ec4f42..2efbf53d4093821081d803083d302b4ea1d709f8 100644 --- a/libc/src/stdio/printf_core/int_converter.h +++ b/libc/src/stdio/printf_core/int_converter.h @@ -33,14 +33,17 @@ using HexFmt = IntegerToString; using HexFmtUppercase = IntegerToString; using OctFmt = IntegerToString; using DecFmt = IntegerToString; +using BinFmt = IntegerToString; LIBC_INLINE constexpr size_t num_buf_size() { - constexpr auto max = [](size_t a, size_t b) -> size_t { - return (a < b) ? b : a; - }; - return max(HexFmt::buffer_size(), - max(HexFmtUppercase::buffer_size(), - max(OctFmt::buffer_size(), DecFmt::buffer_size()))); + cpp::array sizes{ + HexFmt::buffer_size(), HexFmtUppercase::buffer_size(), + OctFmt::buffer_size(), DecFmt::buffer_size(), BinFmt::buffer_size()}; + + auto result = sizes[0]; + for (size_t i = 1; i < sizes.size(); i++) + result = cpp::max(result, sizes[i]); + return result; } LIBC_INLINE cpp::optional @@ -52,6 +55,8 @@ num_to_strview(uintmax_t num, cpp::span bufref, char conv_name) { return HexFmtUppercase::format_to(bufref, num); } else if (conv_name == 'o') { return OctFmt::format_to(bufref, num); + } else if (to_lower(conv_name) == 'b') { + return BinFmt::format_to(bufref, num); } else { return DecFmt::format_to(bufref, num); } @@ -116,6 +121,11 @@ LIBC_INLINE int convert_int(Writer *writer, const FormatSection &to_conv) { prefix_len = 2; prefix[0] = '0'; prefix[1] = a + ('x' - 'a'); + } else if ((to_lower(to_conv.conv_name) == 'b') && + ((flags & FormatFlags::ALTERNATE_FORM) != 0) && num != 0) { + prefix_len = 2; + prefix[0] = '0'; + prefix[1] = a + ('b' - 'a'); } else { prefix_len = (sign_char == 0 ? 0 : 1); prefix[0] = sign_char; diff --git a/libc/src/stdio/printf_core/parser.h b/libc/src/stdio/printf_core/parser.h index ab491655275fb9cae2731cd791683304fc35deed..1e7d2e58c924a6eff5fe5a01bd63d638860bcd77 100644 --- a/libc/src/stdio/printf_core/parser.h +++ b/libc/src/stdio/printf_core/parser.h @@ -159,6 +159,8 @@ public: case ('x'): case ('X'): case ('u'): + case ('b'): + case ('B'): switch (lm) { case (LengthModifier::hh): case (LengthModifier::h): @@ -484,6 +486,8 @@ private: case ('x'): case ('X'): case ('u'): + case ('b'): + case ('B'): switch (lm) { case (LengthModifier::hh): case (LengthModifier::h): diff --git a/libc/src/unistd/linux/CMakeLists.txt b/libc/src/unistd/linux/CMakeLists.txt index 42190079141b067b53d2613d4668f6c5b832a859..df85d44e9e9edc1d474560662b61e985495ecbc3 100644 --- a/libc/src/unistd/linux/CMakeLists.txt +++ b/libc/src/unistd/linux/CMakeLists.txt @@ -283,6 +283,7 @@ add_entrypoint_object( libc.include.unistd libc.include.sys_syscall libc.src.__support.OSUtil.osutil + libc.src.__support.macros.sanitizer libc.src.errno.errno ) @@ -309,6 +310,7 @@ add_entrypoint_object( libc.include.unistd libc.include.sys_syscall libc.src.__support.OSUtil.osutil + libc.src.__support.macros.sanitizer libc.src.errno.errno ) diff --git a/libc/src/unistd/linux/pread.cpp b/libc/src/unistd/linux/pread.cpp index 614de9732c6271a941f9766bf6a0b72c695a9fc2..11cefc5c2f3a8979193dde1c00689247bfdd00ed 100644 --- a/libc/src/unistd/linux/pread.cpp +++ b/libc/src/unistd/linux/pread.cpp @@ -10,7 +10,7 @@ #include "src/__support/OSUtil/syscall.h" // For internal syscall function. #include "src/__support/common.h" - +#include "src/__support/macros/sanitizer.h" // for MSAN_UNPOISON #include "src/errno/libc_errno.h" #include // For uint64_t. #include // For syscall numbers. @@ -28,6 +28,9 @@ LLVM_LIBC_FUNCTION(ssize_t, pread, ssize_t ret = LIBC_NAMESPACE::syscall_impl(SYS_pread64, fd, buf, count, offset); #endif + // The cast is important since there is a check that dereferences the pointer + // which fails on void*. + MSAN_UNPOISON(reinterpret_cast(buf), count); if (ret < 0) { libc_errno = static_cast(-ret); return -1; diff --git a/libc/test/IntegrationTest/test.h b/libc/test/IntegrationTest/test.h index c015bb44586ff13a73b2a1b9082f99965160d6ee..64906ef179391b42ed28d69cff61b0cc3c798843 100644 --- a/libc/test/IntegrationTest/test.h +++ b/libc/test/IntegrationTest/test.h @@ -68,9 +68,12 @@ //////////////////////////////////////////////////////////////////////////////// // Errno checks. -#define ASSERT_ERRNO_EQ(VAL) ASSERT_EQ(VAL, static_cast(libc_errno)) -#define ASSERT_ERRNO_SUCCESS() ASSERT_EQ(0, static_cast(libc_errno)) -#define ASSERT_ERRNO_FAILURE() ASSERT_NE(0, static_cast(libc_errno)) +#define ASSERT_ERRNO_EQ(VAL) \ + ASSERT_EQ(VAL, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_SUCCESS() \ + ASSERT_EQ(0, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_FAILURE() \ + ASSERT_NE(0, static_cast(LIBC_NAMESPACE::libc_errno)) // Integration tests are compiled with -ffreestanding which stops treating // the main function as a non-overloadable special function. Hence, we use a diff --git a/libc/test/UnitTest/ErrnoSetterMatcher.h b/libc/test/UnitTest/ErrnoSetterMatcher.h index 6b15bd4e9b79a423c4120447ea85ae6d01f9458a..745ba4182023e21dac6269d2bebeeccc846d8044 100644 --- a/libc/test/UnitTest/ErrnoSetterMatcher.h +++ b/libc/test/UnitTest/ErrnoSetterMatcher.h @@ -109,8 +109,8 @@ public: bool match(T got) { actual_return = got; - actual_errno = libc_errno; - libc_errno = 0; + actual_errno = LIBC_NAMESPACE::libc_errno; + LIBC_NAMESPACE::libc_errno = 0; if constexpr (ignore_errno()) return return_cmp.compare(actual_return); else diff --git a/libc/test/UnitTest/FPMatcher.h b/libc/test/UnitTest/FPMatcher.h index 210690a9c6ece1a0a2f497ad09df8889cc429be7..c4a1cfa1bc1d488556f454eff69fae8ad6799ede 100644 --- a/libc/test/UnitTest/FPMatcher.h +++ b/libc/test/UnitTest/FPMatcher.h @@ -132,8 +132,8 @@ template struct FPTest : public Test { #define EXPECT_MATH_ERRNO(expected) \ do { \ if (math_errhandling & MATH_ERRNO) { \ - int actual = libc_errno; \ - libc_errno = 0; \ + int actual = LIBC_NAMESPACE::libc_errno; \ + LIBC_NAMESPACE::libc_errno = 0; \ EXPECT_EQ(actual, expected); \ } \ } while (0) @@ -141,8 +141,8 @@ template struct FPTest : public Test { #define ASSERT_MATH_ERRNO(expected) \ do { \ if (math_errhandling & MATH_ERRNO) { \ - int actual = libc_errno; \ - libc_errno = 0; \ + int actual = LIBC_NAMESPACE::libc_errno; \ + LIBC_NAMESPACE::libc_errno = 0; \ ASSERT_EQ(actual, expected); \ } \ } while (0) diff --git a/libc/test/UnitTest/FuchsiaTest.h b/libc/test/UnitTest/FuchsiaTest.h index 1b75379658139890f8063ba2c9ea7658396b2818..e9e8348ee5ddb04a5bb741c28fd81d7ed7f35e55 100644 --- a/libc/test/UnitTest/FuchsiaTest.h +++ b/libc/test/UnitTest/FuchsiaTest.h @@ -14,9 +14,12 @@ #define WITH_SIGNAL(X) #X // These macros are used in string unittests. -#define ASSERT_ERRNO_EQ(VAL) ASSERT_EQ(VAL, static_cast(libc_errno)) -#define ASSERT_ERRNO_SUCCESS() ASSERT_EQ(0, static_cast(libc_errno)) -#define ASSERT_ERRNO_FAILURE() ASSERT_NE(0, static_cast(libc_errno)) +#define ASSERT_ERRNO_EQ(VAL) \ + ASSERT_EQ(VAL, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_SUCCESS() \ + ASSERT_EQ(0, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_FAILURE() \ + ASSERT_NE(0, static_cast(LIBC_NAMESPACE::libc_errno)) #ifndef EXPECT_DEATH // Since zxtest has ASSERT_DEATH but not EXPECT_DEATH, wrap calling it diff --git a/libc/test/UnitTest/LibcTest.h b/libc/test/UnitTest/LibcTest.h index 1a90d10d7ec01b770ecad9a742d4f547f0fcafd9..047f18036b0ac248279d1c6f6462ea65dd16d503 100644 --- a/libc/test/UnitTest/LibcTest.h +++ b/libc/test/UnitTest/LibcTest.h @@ -446,9 +446,12 @@ CString libc_make_test_file_path_func(const char *file_name); //////////////////////////////////////////////////////////////////////////////// // Errno checks. -#define ASSERT_ERRNO_EQ(VAL) ASSERT_EQ(VAL, static_cast(libc_errno)) -#define ASSERT_ERRNO_SUCCESS() ASSERT_EQ(0, static_cast(libc_errno)) -#define ASSERT_ERRNO_FAILURE() ASSERT_NE(0, static_cast(libc_errno)) +#define ASSERT_ERRNO_EQ(VAL) \ + ASSERT_EQ(VAL, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_SUCCESS() \ + ASSERT_EQ(0, static_cast(LIBC_NAMESPACE::libc_errno)) +#define ASSERT_ERRNO_FAILURE() \ + ASSERT_NE(0, static_cast(LIBC_NAMESPACE::libc_errno)) //////////////////////////////////////////////////////////////////////////////// // Subprocess checks. diff --git a/libc/test/include/stdbit_test.cpp b/libc/test/include/stdbit_test.cpp index 6e48b0f2f75944133d7d0663512c943c4647776f..8d5d4c162938ec6fa66143b38e550746a769394a 100644 --- a/libc/test/include/stdbit_test.cpp +++ b/libc/test/include/stdbit_test.cpp @@ -33,6 +33,16 @@ unsigned stdc_leading_ones_us(unsigned short) noexcept { return 0xBBU; } unsigned stdc_leading_ones_ui(unsigned) noexcept { return 0xBCU; } unsigned stdc_leading_ones_ul(unsigned long) noexcept { return 0xBDU; } unsigned stdc_leading_ones_ull(unsigned long long) noexcept { return 0xBFU; } +unsigned stdc_trailing_zeros_uc(unsigned char) noexcept { return 0xCAU; } +unsigned stdc_trailing_zeros_us(unsigned short) noexcept { return 0xCBU; } +unsigned stdc_trailing_zeros_ui(unsigned) noexcept { return 0xCCU; } +unsigned stdc_trailing_zeros_ul(unsigned long) noexcept { return 0xCDU; } +unsigned stdc_trailing_zeros_ull(unsigned long long) noexcept { return 0xCFU; } +unsigned stdc_trailing_ones_uc(unsigned char) noexcept { return 0xDAU; } +unsigned stdc_trailing_ones_us(unsigned short) noexcept { return 0xDBU; } +unsigned stdc_trailing_ones_ui(unsigned) noexcept { return 0xDCU; } +unsigned stdc_trailing_ones_ul(unsigned long) noexcept { return 0xDDU; } +unsigned stdc_trailing_ones_ull(unsigned long long) noexcept { return 0xDFU; } } #include "include/llvm-libc-macros/stdbit-macros.h" @@ -52,3 +62,19 @@ TEST(LlvmLibcStdbitTest, TypeGenericMacroLeadingOnes) { EXPECT_EQ(stdc_leading_ones(0UL), 0xBDU); EXPECT_EQ(stdc_leading_ones(0ULL), 0xBFU); } + +TEST(LlvmLibcStdbitTest, TypeGenericMacroTrailingZeros) { + EXPECT_EQ(stdc_trailing_zeros(static_cast(0U)), 0xCAU); + EXPECT_EQ(stdc_trailing_zeros(static_cast(0U)), 0xCBU); + EXPECT_EQ(stdc_trailing_zeros(0U), 0xCCU); + EXPECT_EQ(stdc_trailing_zeros(0UL), 0xCDU); + EXPECT_EQ(stdc_trailing_zeros(0ULL), 0xCFU); +} + +TEST(LlvmLibcStdbitTest, TypeGenericMacroTrailingOnes) { + EXPECT_EQ(stdc_trailing_ones(static_cast(0U)), 0xDAU); + EXPECT_EQ(stdc_trailing_ones(static_cast(0U)), 0xDBU); + EXPECT_EQ(stdc_trailing_ones(0U), 0xDCU); + EXPECT_EQ(stdc_trailing_ones(0UL), 0xDDU); + EXPECT_EQ(stdc_trailing_ones(0ULL), 0xDFU); +} diff --git a/libc/test/integration/src/pthread/pthread_create_test.cpp b/libc/test/integration/src/pthread/pthread_create_test.cpp index 5da91c6ec9a7d2a34159e1585005e02a67163031..29da4d5c3c8d79b0e5a5f4b21a1510ebd7bc874f 100644 --- a/libc/test/integration/src/pthread/pthread_create_test.cpp +++ b/libc/test/integration/src/pthread/pthread_create_test.cpp @@ -332,7 +332,7 @@ static void run_failure_tests() { } TEST_MAIN() { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; run_success_tests(); run_failure_tests(); return 0; diff --git a/libc/test/integration/src/pthread/pthread_join_test.cpp b/libc/test/integration/src/pthread/pthread_join_test.cpp index da1a968aa47d384f85c75e2552977487e9a5fc69..994fa57a6b3373c6513210eaaf9aafd63bd8f4e6 100644 --- a/libc/test/integration/src/pthread/pthread_join_test.cpp +++ b/libc/test/integration/src/pthread/pthread_join_test.cpp @@ -25,7 +25,7 @@ static void nullJoinTest() { } TEST_MAIN() { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; nullJoinTest(); return 0; } diff --git a/libc/test/integration/src/unistd/getcwd_test.cpp b/libc/test/integration/src/unistd/getcwd_test.cpp index 87687d09b9e7aff011737a1774819ce7a1b5b876..551768187bf018e936d90cfbeab5794469cd27b0 100644 --- a/libc/test/integration/src/unistd/getcwd_test.cpp +++ b/libc/test/integration/src/unistd/getcwd_test.cpp @@ -31,12 +31,12 @@ TEST_MAIN(int argc, char **argv, char **envp) { cwd = LIBC_NAMESPACE::getcwd(buffer, 0); ASSERT_TRUE(cwd == nullptr); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Insufficient size cwd = LIBC_NAMESPACE::getcwd(buffer, 2); ASSERT_TRUE(cwd == nullptr); - int err = libc_errno; + int err = LIBC_NAMESPACE::libc_errno; ASSERT_EQ(err, ERANGE); return 0; diff --git a/libc/test/src/__support/str_to_double_test.cpp b/libc/test/src/__support/str_to_double_test.cpp index b66935f0988e0567c9238d3c134d085cdcbaefdc..3c6d03978803b6a9abc348c9317a922a9613dbca 100644 --- a/libc/test/src/__support/str_to_double_test.cpp +++ b/libc/test/src/__support/str_to_double_test.cpp @@ -90,7 +90,7 @@ TEST(LlvmLibcStrToDblTest, SimpleDecimalConversionExtraTypes) { uint64_t double_output_mantissa = 0; uint32_t output_exp2 = 0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto double_result = internal::simple_decimal_conversion("123456789012345678900"); diff --git a/libc/test/src/__support/str_to_float_test.cpp b/libc/test/src/__support/str_to_float_test.cpp index 3102fa7aa91ec18a67ea0b3be8c9d1f4b01edc94..f23d8706d77da838df647e5af6941e373b3c5809 100644 --- a/libc/test/src/__support/str_to_float_test.cpp +++ b/libc/test/src/__support/str_to_float_test.cpp @@ -46,7 +46,7 @@ TEST(LlvmLibcStrToFltTest, SimpleDecimalConversionExtraTypes) { uint32_t float_output_mantissa = 0; uint32_t output_exp2 = 0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto float_result = internal::simple_decimal_conversion("123456789012345678900"); float_output_mantissa = float_result.num.mantissa; diff --git a/libc/test/src/__support/str_to_fp_test.h b/libc/test/src/__support/str_to_fp_test.h index 32a313309392910337085b5f25bd224722384b47..bddff035fdd16231e1948d4247b50f9e8e063131 100644 --- a/libc/test/src/__support/str_to_fp_test.h +++ b/libc/test/src/__support/str_to_fp_test.h @@ -66,7 +66,7 @@ template struct LlvmLibcStrToFloatTest : public testing::Test { const int expectedErrno = 0) { StorageType actual_output_mantissa = 0; uint32_t actual_output_exp2 = 0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto result = internal::simple_decimal_conversion(numStart); diff --git a/libc/test/src/dirent/dirent_test.cpp b/libc/test/src/dirent/dirent_test.cpp index e2e0399673be66dd03daf698dcbaa11e146058bf..41f522a6a75fba3dce10150fde1c1c9268602854 100644 --- a/libc/test/src/dirent/dirent_test.cpp +++ b/libc/test/src/dirent/dirent_test.cpp @@ -55,17 +55,17 @@ TEST(LlvmLibcDirentTest, SimpleOpenAndRead) { } TEST(LlvmLibcDirentTest, OpenNonExistentDir) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ::DIR *dir = LIBC_NAMESPACE::opendir("___xyz123__.non_existent__"); ASSERT_TRUE(dir == nullptr); ASSERT_ERRNO_EQ(ENOENT); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } TEST(LlvmLibcDirentTest, OpenFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ::DIR *dir = LIBC_NAMESPACE::opendir("testdata/file1.txt"); ASSERT_TRUE(dir == nullptr); ASSERT_ERRNO_EQ(ENOTDIR); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/errno/errno_test.cpp b/libc/test/src/errno/errno_test.cpp index 876ebfc0ac2696f56f4fb124794fcfc7589f5e30..b0db22a85f3bc9b593cd3fe9b6856808406c6dac 100644 --- a/libc/test/src/errno/errno_test.cpp +++ b/libc/test/src/errno/errno_test.cpp @@ -11,6 +11,6 @@ TEST(LlvmLibcErrnoTest, Basic) { int test_val = 123; - libc_errno = test_val; + LIBC_NAMESPACE::libc_errno = test_val; ASSERT_ERRNO_EQ(test_val); } diff --git a/libc/test/src/math/RoundToIntegerTest.h b/libc/test/src/math/RoundToIntegerTest.h index 5239528c9246e102bcf2c780b314162c9a9142f6..9bd4ba52f61ba80c1d5d6eb71f06d77f1b9174a7 100644 --- a/libc/test/src/math/RoundToIntegerTest.h +++ b/libc/test/src/math/RoundToIntegerTest.h @@ -51,7 +51,7 @@ private: void test_one_input(RoundToIntegerFunc func, F input, I expected, bool expectError) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); ASSERT_EQ(func(input), expected); diff --git a/libc/test/src/math/acosf_test.cpp b/libc/test/src/math/acosf_test.cpp index 81f697c315a28099f3cca7c996b967ff7da3d649..c273184d58f3e605c9d8a41b75f274377aaf8fc2 100644 --- a/libc/test/src/math/acosf_test.cpp +++ b/libc/test/src/math/acosf_test.cpp @@ -22,7 +22,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; using LlvmLibcAcosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAcosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/acoshf_test.cpp b/libc/test/src/math/acoshf_test.cpp index 6d43105c83c28a1b862b1ded3d344aedfadfc4b5..a0e845b2b247ee8eabfbce4389a5ccad7dfc9cb4 100644 --- a/libc/test/src/math/acoshf_test.cpp +++ b/libc/test/src/math/acoshf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcAcoshfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAcoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acoshf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/asinf_test.cpp b/libc/test/src/math/asinf_test.cpp index 77ac2bc216f77c62a1eff97de823a24731a58739..a24fdcc36e140a867e32217be993df0dbf152ba5 100644 --- a/libc/test/src/math/asinf_test.cpp +++ b/libc/test/src/math/asinf_test.cpp @@ -23,7 +23,7 @@ using LlvmLibcAsinfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAsinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/asinhf_test.cpp b/libc/test/src/math/asinhf_test.cpp index 9b925bf254a93fd6b25a79dcbe65fb21373d70b4..3127861c9a1be5963b126ef1e0eb34ca44616eb4 100644 --- a/libc/test/src/math/asinhf_test.cpp +++ b/libc/test/src/math/asinhf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcAsinhfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAsinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/atanf_test.cpp b/libc/test/src/math/atanf_test.cpp index b5d30fbd5679e7d04e36b04b4c3f90e19c2c8e2e..1fa7165805c7d19d58a36f37bcc136cb79bf602e 100644 --- a/libc/test/src/math/atanf_test.cpp +++ b/libc/test/src/math/atanf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcAtanfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAtanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanf(aNaN)); EXPECT_FP_EXCEPTION(0); diff --git a/libc/test/src/math/atanhf_test.cpp b/libc/test/src/math/atanhf_test.cpp index 9dea65dccd8fd378e6fed747237adfbbc4896ba8..1b45436094da4420ff12ae6df49494a4e5496cd0 100644 --- a/libc/test/src/math/atanhf_test.cpp +++ b/libc/test/src/math/atanhf_test.cpp @@ -23,7 +23,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcAtanhfTest, SpecialNumbers) { using Sign = LIBC_NAMESPACE::fputil::Sign; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanhf(aNaN)); EXPECT_FP_EXCEPTION(0); diff --git a/libc/test/src/math/cosf_test.cpp b/libc/test/src/math/cosf_test.cpp index 9a988d76c598f43694b93192f8d9d772ccd5096a..93ab06dc80b261e6569e8c9d79e65349a14dd94d 100644 --- a/libc/test/src/math/cosf_test.cpp +++ b/libc/test/src/math/cosf_test.cpp @@ -24,7 +24,7 @@ using LlvmLibcCosfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::cosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/coshf_test.cpp b/libc/test/src/math/coshf_test.cpp index 843ecb8925ad3838d2dc9988f66ea9e8a5a006ee..3b8e14fb5f03429360e4c2411cbf2a782c939535 100644 --- a/libc/test/src/math/coshf_test.cpp +++ b/libc/test/src/math/coshf_test.cpp @@ -23,7 +23,7 @@ using LlvmLibcCoshfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::coshf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -42,7 +42,7 @@ TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { } TEST_F(LlvmLibcCoshfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::coshf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/exp10_test.cpp b/libc/test/src/math/exp10_test.cpp index e9990b3ed8e6d2d11b0b8efecfef2117f3403cb4..d71b5a22303745d82e82253d52ccdc8e74869813 100644 --- a/libc/test/src/math/exp10_test.cpp +++ b/libc/test/src/math/exp10_test.cpp @@ -106,7 +106,7 @@ TEST_F(LlvmLibcExp10Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::exp10(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/exp10f_test.cpp b/libc/test/src/math/exp10f_test.cpp index 0866488935c202b1d194e56f4e36003a4aae074a..4e2d065f1292ab12f6ea5dd7b146855ece4e1af3 100644 --- a/libc/test/src/math/exp10f_test.cpp +++ b/libc/test/src/math/exp10f_test.cpp @@ -21,7 +21,7 @@ using LlvmLibcExp10fTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::exp10f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -40,7 +40,7 @@ TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp10fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp10f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -55,7 +55,7 @@ TEST_F(LlvmLibcExp10fTest, Overflow) { } TEST_F(LlvmLibcExp10fTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( 0.0f, LIBC_NAMESPACE::exp10f(FPBits(0xff7fffffU).get_val()), FE_UNDERFLOW); @@ -97,7 +97,7 @@ TEST_F(LlvmLibcExp10fTest, TrickyInputs) { 0x41200000, // x = 10.0f }; for (int i = 0; i < N; ++i) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float x = FPBits(INPUTS[i]).get_val(); EXPECT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp10, x, LIBC_NAMESPACE::exp10f(x), 0.5); @@ -113,14 +113,14 @@ TEST_F(LlvmLibcExp10fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::exp10f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp10, x, LIBC_NAMESPACE::exp10f(x), 0.5); diff --git a/libc/test/src/math/exp2_test.cpp b/libc/test/src/math/exp2_test.cpp index d66c9b757625d163c85d0456404fb2a6d287528f..2f9d7b3a2a6c90b047cb5271c4c96a643c3388fc 100644 --- a/libc/test/src/math/exp2_test.cpp +++ b/libc/test/src/math/exp2_test.cpp @@ -81,7 +81,7 @@ TEST_F(LlvmLibcExp2Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::exp2(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/exp2f_test.cpp b/libc/test/src/math/exp2f_test.cpp index 18607b1d04910407014005579cc51bdcf8106206..f5ea8554be5c0fbf286ab78497a05b6b304ec6e2 100644 --- a/libc/test/src/math/exp2f_test.cpp +++ b/libc/test/src/math/exp2f_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcExp2fTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::exp2f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -41,7 +41,7 @@ TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp2fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp2f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -72,7 +72,7 @@ TEST_F(LlvmLibcExp2fTest, TrickyInputs) { 0xc3150000U, /*-0x1.2ap+7f*/ }; for (int i = 0; i < N; ++i) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float x = FPBits(INPUTS[i]).get_val(); EXPECT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp2, x, LIBC_NAMESPACE::exp2f(x), 0.5); @@ -81,7 +81,7 @@ TEST_F(LlvmLibcExp2fTest, TrickyInputs) { } TEST_F(LlvmLibcExp2fTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( 0.0f, LIBC_NAMESPACE::exp2f(FPBits(0xff7fffffU).get_val()), FE_UNDERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -109,14 +109,14 @@ TEST_F(LlvmLibcExp2fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::exp2f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp2, x, LIBC_NAMESPACE::exp2f(x), 0.5); diff --git a/libc/test/src/math/exp_test.cpp b/libc/test/src/math/exp_test.cpp index 454107f307d867f37bffcd5749c2ad5fb86ba15d..006db00b91949e52db3ce0781c96bd1060fb0b3b 100644 --- a/libc/test/src/math/exp_test.cpp +++ b/libc/test/src/math/exp_test.cpp @@ -79,7 +79,7 @@ TEST_F(LlvmLibcExpTest, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::exp(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/expf_test.cpp b/libc/test/src/math/expf_test.cpp index 0ac64ceec1c71c896f1ee1fb012974d09cb42d7f..ffd9da500488b12678d353c02a06bd4c9e069c6d 100644 --- a/libc/test/src/math/expf_test.cpp +++ b/libc/test/src/math/expf_test.cpp @@ -21,7 +21,7 @@ using LlvmLibcExpfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExpfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::expf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -40,7 +40,7 @@ TEST_F(LlvmLibcExpfTest, SpecialNumbers) { } TEST_F(LlvmLibcExpfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -55,7 +55,7 @@ TEST_F(LlvmLibcExpfTest, Overflow) { } TEST_F(LlvmLibcExpfTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( 0.0f, LIBC_NAMESPACE::expf(FPBits(0xff7fffffU).get_val()), FE_UNDERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -76,7 +76,7 @@ TEST_F(LlvmLibcExpfTest, Underflow) { TEST_F(LlvmLibcExpfTest, Borderline) { float x; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; x = FPBits(0x42affff8U).get_val(); ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp, x, LIBC_NAMESPACE::expf(x), 0.5); @@ -110,14 +110,14 @@ TEST_F(LlvmLibcExpfTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::expf(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; EXPECT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Exp, x, LIBC_NAMESPACE::expf(x), 0.5); diff --git a/libc/test/src/math/expm1_test.cpp b/libc/test/src/math/expm1_test.cpp index 99ef8275eab739afe4ac2667ee1c744c9edf9ca4..ccc6e36095481fdf11388e484a93222f65bb10e0 100644 --- a/libc/test/src/math/expm1_test.cpp +++ b/libc/test/src/math/expm1_test.cpp @@ -75,7 +75,7 @@ TEST_F(LlvmLibcExpm1Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::expm1(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/expm1f_test.cpp b/libc/test/src/math/expm1f_test.cpp index cc820803cc30bfbce2593e076585ed15c20f85ca..94a9301f8eb2224b49bf064d5d0d4417307f01f7 100644 --- a/libc/test/src/math/expm1f_test.cpp +++ b/libc/test/src/math/expm1f_test.cpp @@ -21,7 +21,7 @@ using LlvmLibcExpm1fTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::expm1f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -40,7 +40,7 @@ TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { } TEST_F(LlvmLibcExpm1fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expm1f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); @@ -55,7 +55,7 @@ TEST_F(LlvmLibcExpm1fTest, Overflow) { } TEST_F(LlvmLibcExpm1fTest, Underflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(-1.0f, LIBC_NAMESPACE::expm1f(FPBits(0xff7fffffU).get_val())); float x = FPBits(0xc2cffff8U).get_val(); @@ -70,7 +70,7 @@ TEST_F(LlvmLibcExpm1fTest, Underflow) { TEST_F(LlvmLibcExpm1fTest, Borderline) { float x; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; x = FPBits(0x42affff8U).get_val(); ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Expm1, x, LIBC_NAMESPACE::expm1f(x), 0.5); @@ -119,14 +119,14 @@ TEST_F(LlvmLibcExpm1fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::expm1f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Expm1, x, LIBC_NAMESPACE::expm1f(x), 0.5); diff --git a/libc/test/src/math/log10_test.cpp b/libc/test/src/math/log10_test.cpp index de9206f2daec2ef1976e65707983f7d8441883ba..ed4a24b95159517fa69effc0c8e556f658f01519 100644 --- a/libc/test/src/math/log10_test.cpp +++ b/libc/test/src/math/log10_test.cpp @@ -102,7 +102,7 @@ TEST_F(LlvmLibcLog10Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log10(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/log1p_test.cpp b/libc/test/src/math/log1p_test.cpp index f70c0f87560cdd76db8c23d8bc14968a8df561d6..d769659356c941a84638348caeba9c25dce1d0c4 100644 --- a/libc/test/src/math/log1p_test.cpp +++ b/libc/test/src/math/log1p_test.cpp @@ -102,7 +102,7 @@ TEST_F(LlvmLibcLog1pTest, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log1p(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/log1pf_test.cpp b/libc/test/src/math/log1pf_test.cpp index 37144838552cc0cfab923584a934f124f2f75b71..2f6330ee6ce631c97b44c3249239939b169bbeff 100644 --- a/libc/test/src/math/log1pf_test.cpp +++ b/libc/test/src/math/log1pf_test.cpp @@ -76,7 +76,7 @@ TEST_F(LlvmLibcLog1pfTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Log1p, x, LIBC_NAMESPACE::log1pf(x), 0.5); } diff --git a/libc/test/src/math/log2_test.cpp b/libc/test/src/math/log2_test.cpp index 65eae58b3508a627f2957a3eccc46e51fea15d43..f4ee0ff5185b4787f96791407cf16ac68eed8218 100644 --- a/libc/test/src/math/log2_test.cpp +++ b/libc/test/src/math/log2_test.cpp @@ -101,7 +101,7 @@ TEST_F(LlvmLibcLog2Test, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log2(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/log2f_test.cpp b/libc/test/src/math/log2f_test.cpp index 0793bf8a0409124c0665fad8050abae131709844..d8b4808f5cda120b56b619ffa19379f9d8c1ae19 100644 --- a/libc/test/src/math/log2f_test.cpp +++ b/libc/test/src/math/log2f_test.cpp @@ -52,13 +52,13 @@ TEST_F(LlvmLibcLog2fTest, InFloatRange) { float x = FPBits(v).get_val(); if (isnan(x) || isinf(x)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::log2f(x); // If the computation resulted in an error or did not produce valid result // in the single-precision floating point range, then ignore comparing with // MPFR result as MPFR can still produce valid results because of its // wider precision. - if (isnan(result) || isinf(result) || libc_errno != 0) + if (isnan(result) || isinf(result) || LIBC_NAMESPACE::libc_errno != 0) continue; ASSERT_MPFR_MATCH_ALL_ROUNDING(mpfr::Operation::Log2, x, LIBC_NAMESPACE::log2f(x), 0.5); diff --git a/libc/test/src/math/log_test.cpp b/libc/test/src/math/log_test.cpp index 457117c1757a7fc00316490dc955c4f1fff2125c..b1f1ab775462b1fb7dd5938f60cdacbe2c5294f1 100644 --- a/libc/test/src/math/log_test.cpp +++ b/libc/test/src/math/log_test.cpp @@ -100,7 +100,7 @@ TEST_F(LlvmLibcLogTest, InDoubleRange) { double x = FPBits(v).get_val(); if (isnan(x) || isinf(x) || x < 0.0) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::log(x); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/powf_test.cpp b/libc/test/src/math/powf_test.cpp index 608bd85bbf0c7904c6b309d9864c6ce579273d77..3dffeb603499fe7b296e931300045a479ffd262e 100644 --- a/libc/test/src/math/powf_test.cpp +++ b/libc/test/src/math/powf_test.cpp @@ -72,7 +72,7 @@ TEST_F(LlvmLibcPowfTest, InFloatRange) { if (isnan(y) || isinf(y)) continue; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::powf(x, y); ++cc; if (isnan(result) || isinf(result)) diff --git a/libc/test/src/math/sincosf_test.cpp b/libc/test/src/math/sincosf_test.cpp index 76fda6354f63ac2798fb79eb67ceeb5a826a314f..2c0c7eaaa25f07f195b6673136877add77b93689 100644 --- a/libc/test/src/math/sincosf_test.cpp +++ b/libc/test/src/math/sincosf_test.cpp @@ -25,7 +25,7 @@ using LIBC_NAMESPACE::testing::SDCOMP26094_VALUES; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcSinCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float sin, cos; LIBC_NAMESPACE::sincosf(aNaN, &sin, &cos); diff --git a/libc/test/src/math/sinf_test.cpp b/libc/test/src/math/sinf_test.cpp index 32afc4f1c60d117dae6d7a854bf696d14d64a7b9..94c1114e688984dc5f50d50367d617772912161a 100644 --- a/libc/test/src/math/sinf_test.cpp +++ b/libc/test/src/math/sinf_test.cpp @@ -25,7 +25,7 @@ using LIBC_NAMESPACE::testing::SDCOMP26094_VALUES; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcSinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/sinhf_test.cpp b/libc/test/src/math/sinhf_test.cpp index 765fdc6c2bcc4d0527377dad4f7157cabc5a4341..f14150bb04420eb286ec709e633226322e5ace7a 100644 --- a/libc/test/src/math/sinhf_test.cpp +++ b/libc/test/src/math/sinhf_test.cpp @@ -23,7 +23,7 @@ using LlvmLibcSinhfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcSinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinhf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -66,7 +66,7 @@ TEST_F(LlvmLibcSinhfTest, SmallValues) { } TEST_F(LlvmLibcSinhfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::sinhf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/RoundToIntegerTest.h b/libc/test/src/math/smoke/RoundToIntegerTest.h index 1fdff23e9159c05c0b3f955245df619645314940..59694131f7f5dd2f7818cb0b5aa8ef2cab186351 100644 --- a/libc/test/src/math/smoke/RoundToIntegerTest.h +++ b/libc/test/src/math/smoke/RoundToIntegerTest.h @@ -46,7 +46,7 @@ private: void test_one_input(RoundToIntegerFunc func, F input, I expected, bool expectError) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); ASSERT_EQ(func(input), expected); diff --git a/libc/test/src/math/smoke/acosf_test.cpp b/libc/test/src/math/smoke/acosf_test.cpp index 2d8fba96718c5c7434003aca2ad341d9a4e43e5a..864c9ea4d3175daf0a12ec0e536264c0242b035c 100644 --- a/libc/test/src/math/smoke/acosf_test.cpp +++ b/libc/test/src/math/smoke/acosf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAcosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAcosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/acoshf_test.cpp b/libc/test/src/math/smoke/acoshf_test.cpp index 85c24e08ab79abde11b7605aba1b26ed5cd5743c..b3ba740c2024d35528df006452defde6e9ea2e00 100644 --- a/libc/test/src/math/smoke/acoshf_test.cpp +++ b/libc/test/src/math/smoke/acoshf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAcoshfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAcoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::acoshf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/asinf_test.cpp b/libc/test/src/math/smoke/asinf_test.cpp index 57bb7dcf6e841103a5521ba4acb5267a47a634a9..e6afb23a397fe148e883fa2a88e3f8133bfa30da 100644 --- a/libc/test/src/math/smoke/asinf_test.cpp +++ b/libc/test/src/math/smoke/asinf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAsinfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAsinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/asinhf_test.cpp b/libc/test/src/math/smoke/asinhf_test.cpp index 0c6ac537ef1c817878d4728a38fb66c0945b90b9..7a520cdc050a227b540147469c5b71af4d9c9be2 100644 --- a/libc/test/src/math/smoke/asinhf_test.cpp +++ b/libc/test/src/math/smoke/asinhf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAsinhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAsinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::asinhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/atanf_test.cpp b/libc/test/src/math/smoke/atanf_test.cpp index 156ce0744b0e963faaad8aeef9bca2577f027d71..8cc1b418f869c2c4baa94d0b8ded628b42bd3477 100644 --- a/libc/test/src/math/smoke/atanf_test.cpp +++ b/libc/test/src/math/smoke/atanf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcAtanfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAtanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanf(aNaN)); diff --git a/libc/test/src/math/smoke/atanhf_test.cpp b/libc/test/src/math/smoke/atanhf_test.cpp index c613f9bdf35f337a76eeb41b1c2353bd27b621b1..e1d6d2532d39e34df88feb2823afea41d410364b 100644 --- a/libc/test/src/math/smoke/atanhf_test.cpp +++ b/libc/test/src/math/smoke/atanhf_test.cpp @@ -20,7 +20,7 @@ using LlvmLibcAtanhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcAtanhfTest, SpecialNumbers) { using Sign = LIBC_NAMESPACE::fputil::Sign; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::atanhf(aNaN)); diff --git a/libc/test/src/math/smoke/cosf_test.cpp b/libc/test/src/math/smoke/cosf_test.cpp index c9efc791885f014e9a83a81b99606e28d3d87f3b..539c428eadf113f59df2337358486ae8c65ff4bc 100644 --- a/libc/test/src/math/smoke/cosf_test.cpp +++ b/libc/test/src/math/smoke/cosf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcCosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::cosf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/coshf_test.cpp b/libc/test/src/math/smoke/coshf_test.cpp index aa224dcc156f0900fd3456402d71bd7b347e6b55..e38802f93647432fbf855afd533bd7ceef8cd968 100644 --- a/libc/test/src/math/smoke/coshf_test.cpp +++ b/libc/test/src/math/smoke/coshf_test.cpp @@ -20,7 +20,7 @@ using LlvmLibcCoshfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::coshf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -39,7 +39,7 @@ TEST_F(LlvmLibcCoshfTest, SpecialNumbers) { } TEST_F(LlvmLibcCoshfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::coshf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/exp10f_test.cpp b/libc/test/src/math/smoke/exp10f_test.cpp index d242edf04fb37064740916c88f24aa2e191edf99..f6533e983dacd8b13587390ac43e84e5fa547acd 100644 --- a/libc/test/src/math/smoke/exp10f_test.cpp +++ b/libc/test/src/math/smoke/exp10f_test.cpp @@ -18,7 +18,7 @@ using LlvmLibcExp10fTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::exp10f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -41,7 +41,7 @@ TEST_F(LlvmLibcExp10fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp10fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp10f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/exp2f_test.cpp b/libc/test/src/math/smoke/exp2f_test.cpp index e4e56ed23bcffe1145e28ce94e7b3b20874a5eff..7baab630a4cbc47a6b83ae743d85ce99d196f5b0 100644 --- a/libc/test/src/math/smoke/exp2f_test.cpp +++ b/libc/test/src/math/smoke/exp2f_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcExp2fTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::exp2f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -43,7 +43,7 @@ TEST_F(LlvmLibcExp2fTest, SpecialNumbers) { } TEST_F(LlvmLibcExp2fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::exp2f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/expf_test.cpp b/libc/test/src/math/smoke/expf_test.cpp index 24fc35b552ca2e48703ee0968ca68290d15ddee5..2968704f83e355a0557eef6a05691a4d9be43b8c 100644 --- a/libc/test/src/math/smoke/expf_test.cpp +++ b/libc/test/src/math/smoke/expf_test.cpp @@ -18,7 +18,7 @@ using LlvmLibcExpfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExpfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::expf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -37,7 +37,7 @@ TEST_F(LlvmLibcExpfTest, SpecialNumbers) { } TEST_F(LlvmLibcExpfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/expm1f_test.cpp b/libc/test/src/math/smoke/expm1f_test.cpp index 3d6dae77ec00424f372ac12e15c4960c05a8e8a4..4ef8d50ba551a7bde4e30b15f927265303a5877b 100644 --- a/libc/test/src/math/smoke/expm1f_test.cpp +++ b/libc/test/src/math/smoke/expm1f_test.cpp @@ -18,7 +18,7 @@ using LlvmLibcExpm1fTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_ALL_ROUNDING(aNaN, LIBC_NAMESPACE::expm1f(aNaN)); EXPECT_MATH_ERRNO(0); @@ -37,7 +37,7 @@ TEST_F(LlvmLibcExpm1fTest, SpecialNumbers) { } TEST_F(LlvmLibcExpm1fTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::expm1f(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/sincosf_test.cpp b/libc/test/src/math/smoke/sincosf_test.cpp index 0de47f3307fe6f9e393e1dfce9cac5d89362d273..a1447ad57e116225c41ac8386953dd6ea22e7827 100644 --- a/libc/test/src/math/smoke/sincosf_test.cpp +++ b/libc/test/src/math/smoke/sincosf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcSinCosfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcSinCosfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float sin, cos; LIBC_NAMESPACE::sincosf(aNaN, &sin, &cos); diff --git a/libc/test/src/math/smoke/sinf_test.cpp b/libc/test/src/math/smoke/sinf_test.cpp index bbd7634e0028ab9109dcb23eb482f91651016d3c..e51726646bc6869f133c537c8949cbe6a435de3a 100644 --- a/libc/test/src/math/smoke/sinf_test.cpp +++ b/libc/test/src/math/smoke/sinf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcSinfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcSinfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/sinhf_test.cpp b/libc/test/src/math/smoke/sinhf_test.cpp index 0563ccbf77aaaf97beb31e5b6945f6f46c800d7e..23334293b73fe4bbbe66cbaaac6b79bc98dc6187 100644 --- a/libc/test/src/math/smoke/sinhf_test.cpp +++ b/libc/test/src/math/smoke/sinhf_test.cpp @@ -20,7 +20,7 @@ using LlvmLibcSinhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcSinhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::sinhf(aNaN)); EXPECT_MATH_ERRNO(0); @@ -50,7 +50,7 @@ TEST_F(LlvmLibcSinhfTest, SmallValues) { } TEST_F(LlvmLibcSinhfTest, Overflow) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ_WITH_EXCEPTION( inf, LIBC_NAMESPACE::sinhf(FPBits(0x7f7fffffU).get_val()), FE_OVERFLOW); EXPECT_MATH_ERRNO(ERANGE); diff --git a/libc/test/src/math/smoke/tanf_test.cpp b/libc/test/src/math/smoke/tanf_test.cpp index fa93da29829a4c89aaaf470c502faae975d96a78..53a153254b3111fc8ff3fa46e132b5c5c2bef880 100644 --- a/libc/test/src/math/smoke/tanf_test.cpp +++ b/libc/test/src/math/smoke/tanf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcTanfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcTanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/smoke/tanhf_test.cpp b/libc/test/src/math/smoke/tanhf_test.cpp index f32e8cc9591f98cb5d81f2fcae7360edfe206fda..7cb80dca7919eb52c3bf21e4767b7bbddce5303f 100644 --- a/libc/test/src/math/smoke/tanhf_test.cpp +++ b/libc/test/src/math/smoke/tanhf_test.cpp @@ -19,7 +19,7 @@ using LlvmLibcTanhfTest = LIBC_NAMESPACE::testing::FPTest; TEST_F(LlvmLibcTanhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/tanf_test.cpp b/libc/test/src/math/tanf_test.cpp index 5621e819522fc457b90ea4e8c572bc1174d590fa..c8d9d52e3f695446222175360cffeda8ab10f8be 100644 --- a/libc/test/src/math/tanf_test.cpp +++ b/libc/test/src/math/tanf_test.cpp @@ -25,7 +25,7 @@ using LIBC_NAMESPACE::testing::SDCOMP26094_VALUES; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcTanfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/math/tanhf_test.cpp b/libc/test/src/math/tanhf_test.cpp index 862ba6cc7eeb7a1db17e83e679388a6c75bf325d..28da7ffbeddd1883869d62a0f98a0f37b5ed9a5e 100644 --- a/libc/test/src/math/tanhf_test.cpp +++ b/libc/test/src/math/tanhf_test.cpp @@ -22,7 +22,7 @@ using LlvmLibcTanhfTest = LIBC_NAMESPACE::testing::FPTest; namespace mpfr = LIBC_NAMESPACE::testing::mpfr; TEST_F(LlvmLibcTanhfTest, SpecialNumbers) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_FP_EQ(aNaN, LIBC_NAMESPACE::tanhf(aNaN)); EXPECT_MATH_ERRNO(0); diff --git a/libc/test/src/sched/affinity_test.cpp b/libc/test/src/sched/affinity_test.cpp index 38433edecbd0c0608f3a2c585d7b130a5ca109ec..b5085203e5ce0a425e976bef6c1e4ec42eab98af 100644 --- a/libc/test/src/sched/affinity_test.cpp +++ b/libc/test/src/sched/affinity_test.cpp @@ -17,7 +17,7 @@ TEST(LlvmLibcSchedAffinityTest, SmokeTest) { cpu_set_t mask; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; pid_t tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); ASSERT_GT(tid, pid_t(0)); @@ -32,15 +32,15 @@ TEST(LlvmLibcSchedAffinityTest, BadMask) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; pid_t tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT( LIBC_NAMESPACE::sched_getaffinity(tid, sizeof(cpu_set_t), nullptr), Fails(EFAULT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT( LIBC_NAMESPACE::sched_setaffinity(tid, sizeof(cpu_set_t), nullptr), Fails(EFAULT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sched/cpu_count_test.cpp b/libc/test/src/sched/cpu_count_test.cpp index ca3e80818a5c14902ea8a233890608c77509aa0e..5250368a261622ebf6ec580497981a782cdf6549 100644 --- a/libc/test/src/sched/cpu_count_test.cpp +++ b/libc/test/src/sched/cpu_count_test.cpp @@ -17,7 +17,7 @@ TEST(LlvmLibcSchedCpuCountTest, SmokeTest) { cpu_set_t mask; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; pid_t tid = LIBC_NAMESPACE::syscall_impl(SYS_gettid); ASSERT_GT(tid, pid_t(0)); diff --git a/libc/test/src/sched/get_priority_test.cpp b/libc/test/src/sched/get_priority_test.cpp index 4ff7890c4f404c9dd9f870ebf8175abb2cad4dbd..59205c51e4a164f044a39cc1eecb3324c74c59c5 100644 --- a/libc/test/src/sched/get_priority_test.cpp +++ b/libc/test/src/sched/get_priority_test.cpp @@ -58,7 +58,7 @@ TEST(LlvmLibcSchedGetPriorityTest, HandleBadPolicyTest) { } TEST(LlvmLibcSchedGetPriorityTest, SmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // We Test: // SCHED_OTHER, SCHED_FIFO, SCHED_RR diff --git a/libc/test/src/sched/param_and_scheduler_test.cpp b/libc/test/src/sched/param_and_scheduler_test.cpp index 7fcb667a31a9d41c3787197468ecc9cfeae16327..8e81f2ed1517f0d63d4853b17fc5e4d46a1f76ad 100644 --- a/libc/test/src/sched/param_and_scheduler_test.cpp +++ b/libc/test/src/sched/param_and_scheduler_test.cpp @@ -37,7 +37,7 @@ class SchedTest : public LIBC_NAMESPACE::testing::Test { public: void testSched(int policy, bool can_set) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int init_policy = LIBC_NAMESPACE::sched_getscheduler(0); ASSERT_GE(init_policy, 0); @@ -55,38 +55,40 @@ public: // Negative pid ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(-1, policy, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getscheduler(-1), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Invalid Policy ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy | 128, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Out of bounds priority param.sched_priority = min_priority - 1; ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; param.sched_priority = max_priority + 1; ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, ¶m), -1); // A bit hard to test as depending if we are root or not we can run into // different issues. - ASSERT_TRUE(libc_errno == EINVAL || libc_errno == EPERM); - libc_errno = 0; + ASSERT_TRUE(LIBC_NAMESPACE::libc_errno == EINVAL || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; // Some sched policies require permissions, so skip param.sched_priority = min_priority; // Success / missing permissions. ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, ¶m), can_set ? 0 : -1); - ASSERT_TRUE(can_set ? (libc_errno == 0) - : (libc_errno == EINVAL || libc_errno == EPERM)); - libc_errno = 0; + ASSERT_TRUE(can_set ? (LIBC_NAMESPACE::libc_errno == 0) + : (LIBC_NAMESPACE::libc_errno == EINVAL || + LIBC_NAMESPACE::libc_errno == EPERM)); + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getscheduler(0), can_set ? policy : init_policy); @@ -96,12 +98,12 @@ public: param.sched_priority = -1; ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; param.sched_priority = max_priority + 1; ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; for (int priority = min_priority; priority <= max_priority; ++priority) { ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(0, ¶m), 0); @@ -113,17 +115,18 @@ public: // Negative pid ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(-1, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(-1, ¶m), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Success / missing permissions ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, ¶m), can_set ? 0 : -1); - ASSERT_TRUE(can_set ? (libc_errno == 0) - : (libc_errno == EINVAL || libc_errno == EPERM)); - libc_errno = 0; + ASSERT_TRUE(can_set ? (LIBC_NAMESPACE::libc_errno == 0) + : (LIBC_NAMESPACE::libc_errno == EINVAL || + LIBC_NAMESPACE::libc_errno == EPERM)); + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(0, ¶m), 0); ASSERT_ERRNO_SUCCESS(); @@ -134,7 +137,7 @@ public: // Null test ASSERT_EQ(LIBC_NAMESPACE::sched_setscheduler(0, policy, nullptr), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } }; @@ -152,13 +155,13 @@ LIST_SCHED_TESTS(SCHED_BATCH, true) LIST_SCHED_TESTS(SCHED_IDLE, true) TEST(LlvmLibcSchedParamAndSchedulerTest, NullParamTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_setparam(0, nullptr), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::sched_getparam(0, nullptr), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sched/sched_rr_get_interval_test.cpp b/libc/test/src/sched/sched_rr_get_interval_test.cpp index 5e024f07ced1231a64cecda7da3ef45792851be6..c22a2c76d743cda2e250ac2bc52469448b412ff9 100644 --- a/libc/test/src/sched/sched_rr_get_interval_test.cpp +++ b/libc/test/src/sched/sched_rr_get_interval_test.cpp @@ -17,7 +17,7 @@ #include TEST(LlvmLibcSchedRRGetIntervalTest, SmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; auto SetSched = [&](int policy) { int min_priority = LIBC_NAMESPACE::sched_get_priority_min(policy); ASSERT_GE(min_priority, 0); @@ -58,19 +58,19 @@ TEST(LlvmLibcSchedRRGetIntervalTest, SmokeTest) { // Null timespec ASSERT_EQ(LIBC_NAMESPACE::sched_rr_get_interval(0, nullptr), -1); ASSERT_ERRNO_EQ(EFAULT); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // Negative pid ASSERT_EQ(LIBC_NAMESPACE::sched_rr_get_interval(-1, &ts), -1); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } // Negative tests don't have SCHED_RR set SetSched(SCHED_OTHER); ASSERT_EQ(LIBC_NAMESPACE::sched_rr_get_interval(0, &ts), 0); ASSERT_ERRNO_SUCCESS(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // TODO: Missing unkown pid -> ESRCH. This is read only so safe to try a few // unlikely values. diff --git a/libc/test/src/sched/yield_test.cpp b/libc/test/src/sched/yield_test.cpp index 5e4e07bc199b66629a2c947f04320de2e8549373..f1627a71fa9adc3a07b4551c6a40178fcd4ee31e 100644 --- a/libc/test/src/sched/yield_test.cpp +++ b/libc/test/src/sched/yield_test.cpp @@ -11,7 +11,7 @@ #include "test/UnitTest/Test.h" TEST(LlvmLibcSchedYieldTest, SmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // sched_yield() always succeeds, just do a basic test that errno/ret are // properly 0. ASSERT_EQ(LIBC_NAMESPACE::sched_yield(), 0); diff --git a/libc/test/src/signal/sigaltstack_test.cpp b/libc/test/src/signal/sigaltstack_test.cpp index 5e1a3a4e2062c3594d2f30c2d22c033bd4854f6d..12bf2bf5e3723a3c26cc3b9e016d3f8368ac4586 100644 --- a/libc/test/src/signal/sigaltstack_test.cpp +++ b/libc/test/src/signal/sigaltstack_test.cpp @@ -47,7 +47,7 @@ static void handler(int) { TEST(LlvmLibcSignalTest, SigaltstackRunOnAltStack) { struct sigaction action; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::sigaction(SIGUSR1, nullptr, &action), Succeeds(0)); action.sa_handler = handler; diff --git a/libc/test/src/signal/signal_test.cpp b/libc/test/src/signal/signal_test.cpp index 78f8bfbd719b1d0bc4df991e3c7de6f93466f95d..70e95a8c159a8b621e2af34881ee45f0eb59564b 100644 --- a/libc/test/src/signal/signal_test.cpp +++ b/libc/test/src/signal/signal_test.cpp @@ -19,7 +19,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcSignal, Invalid) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::sighandler_t valid = +[](int) {}; EXPECT_THAT((void *)LIBC_NAMESPACE::signal(0, valid), Fails(EINVAL, (void *)SIG_ERR)); diff --git a/libc/test/src/signal/sigprocmask_test.cpp b/libc/test/src/signal/sigprocmask_test.cpp index 3e7e3a5c62db273f0daf7cee7d94e3c0dcd1be89..12403f68b59304d03c31c7401b6121bac73ebd12 100644 --- a/libc/test/src/signal/sigprocmask_test.cpp +++ b/libc/test/src/signal/sigprocmask_test.cpp @@ -33,7 +33,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; // This tests for invalid input. TEST_F(LlvmLibcSignalTest, SigprocmaskInvalid) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; sigset_t valid; // 17 and -4 are out of the range for sigprocmask's how paramater. diff --git a/libc/test/src/stdbit/CMakeLists.txt b/libc/test/src/stdbit/CMakeLists.txt index a8c3c9f883532db07feff8c7a5e79fe04f79a7a0..fab5f67bbd9be4122ab13967c11872dd833ea6eb 100644 --- a/libc/test/src/stdbit/CMakeLists.txt +++ b/libc/test/src/stdbit/CMakeLists.txt @@ -1,112 +1,23 @@ add_custom_target(libc-stdbit-tests) -add_libc_test( - stdc_leading_zeros_uc_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_uc_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_uc -) - -add_libc_test( - stdc_leading_zeros_us_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_us_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_us -) - -add_libc_test( - stdc_leading_zeros_ui_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_ui_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_ui -) - -add_libc_test( - stdc_leading_zeros_ul_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_ul_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_ul -) - -add_libc_test( - stdc_leading_zeros_ull_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_zeros_ull_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_zeros_ull -) - -add_libc_test( - stdc_leading_ones_uc_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_uc_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_uc -) - -add_libc_test( - stdc_leading_ones_us_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_us_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_us -) - -add_libc_test( - stdc_leading_ones_ui_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_ui_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_ui -) - -add_libc_test( - stdc_leading_ones_ul_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_ul_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_ul -) - -add_libc_test( - stdc_leading_ones_ull_test - SUITE - libc-stdbit-tests - SRCS - stdc_leading_ones_ull_test.cpp - DEPENDS - libc.src.__support.CPP.limits - libc.src.stdbit.stdc_leading_ones_ull -) - +set(prefixes + leading_zeros + leading_ones + trailing_zeros + trailing_ones +) +set(suffixes c s i l ll) +foreach(prefix IN LISTS prefixes) + foreach(suffix IN LISTS suffixes) + add_libc_test( + stdc_${prefix}_u${suffix}_test + SUITE + libc-stdbit-tests + SRCS + stdc_${prefix}_u${suffix}_test.cpp + DEPENDS + libc.src.__support.CPP.limits + libc.src.stdbit.stdc_${prefix}_u${suffix} + ) + endforeach() +endforeach() diff --git a/libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp b/libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..79d4e5b8b8032da9b796729a06d300fd41e0db29 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_ones_uc_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_ones_uc -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_ones_uc.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingOnesUcTest, ALL) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_uc(UCHAR_MAX), + static_cast(UCHAR_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingOnesUcTest, ZeroHot) { + for (unsigned i = 0U; i != UCHAR_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_uc(~(1U << i)), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_ones_ui_test.cpp b/libc/test/src/stdbit/stdc_trailing_ones_ui_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..51e49f1e9e5feff89cd21ea5e56c611e2e13fe9e --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_ones_ui_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_ones_ui -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_ones_ui.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingOnesUiTest, ALL) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_ui(UINT_MAX), + static_cast(UINT_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingOnesUiTest, ZeroHot) { + for (unsigned i = 0U; i != UINT_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_ui(~(1U << i)), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_ones_ul_test.cpp b/libc/test/src/stdbit/stdc_trailing_ones_ul_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..2aebe2e814ca9f595f6e7c92a0036257a15bcf64 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_ones_ul_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_ones_ul -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_ones_ul.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingOnesUlTest, ALL) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_ul(ULONG_MAX), + static_cast(ULONG_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingOnesUlTest, ZeroHot) { + for (unsigned i = 0U; i != ULONG_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_ul(~(1UL << i)), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_ones_ull_test.cpp b/libc/test/src/stdbit/stdc_trailing_ones_ull_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..38c5100efc06e573bca0376941a1276bb034558f --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_ones_ull_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_ones_ull ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_ones_ull.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingOnesUllTest, ALL) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_ull(ULLONG_MAX), + static_cast(ULLONG_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingOnesUllTest, ZeroHot) { + for (unsigned i = 0U; i != ULLONG_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_ull(~(1ULL << i)), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp b/libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..7ab15743ed1e0437dbd151a318e65a382bc57576 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_ones_us_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_ones_us -------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_ones_us.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingOnesUsTest, ALL) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_us(USHRT_MAX), + static_cast(USHRT_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingOnesUsTest, ZeroHot) { + for (unsigned i = 0U; i != USHRT_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_ones_us(~(1U << i)), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..c02b518865d9f7738ffd5ff8a242a2b1d07664ad --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_uc_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_uc ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_uc.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUcTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_uc(0U), + static_cast(UCHAR_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUcTest, OneHot) { + for (unsigned i = 0U; i != UCHAR_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_uc(1U << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ad9b126335172ff3a3e5bbf9de1e4bdf19a0acd8 --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_ui_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_ui ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_ui.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUiTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ui(0U), + static_cast(UINT_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUiTest, OneHot) { + for (unsigned i = 0U; i != UINT_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ui(1U << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..6d7f4b3cb093df7833a6039cd7af6065233b973f --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_ul_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_ul ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_ul.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUlTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ul(0U), + static_cast(ULONG_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUlTest, OneHot) { + for (unsigned i = 0U; i != ULONG_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ul(1UL << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..64b93b12e6051e3a1883b94de477780802cceb4f --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_ull_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_ull -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_ull.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUllTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ull(0U), + static_cast(ULLONG_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUllTest, OneHot) { + for (unsigned i = 0U; i != ULLONG_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_ull(1ULL << i), i); +} diff --git a/libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp b/libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a9f8327dfd91409a7b646b155e02023d946b26de --- /dev/null +++ b/libc/test/src/stdbit/stdc_trailing_zeros_us_test.cpp @@ -0,0 +1,21 @@ +//===-- Unittests for stdc_trailing_zeros_us ------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "src/__support/CPP/limits.h" +#include "src/stdbit/stdc_trailing_zeros_us.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcStdcTrailingZerosUsTest, Zero) { + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_us(0U), + static_cast(USHRT_WIDTH)); +} + +TEST(LlvmLibcStdcTrailingZerosUsTest, OneHot) { + for (unsigned i = 0U; i != USHRT_WIDTH; ++i) + EXPECT_EQ(LIBC_NAMESPACE::stdc_trailing_zeros_us(1U << i), i); +} diff --git a/libc/test/src/stdio/CMakeLists.txt b/libc/test/src/stdio/CMakeLists.txt index ffc238443863bff4e82c7857fa9b7bdccfb620cd..8db2293ab74a97a60f2c0b3374ef20ce176ebff5 100644 --- a/libc/test/src/stdio/CMakeLists.txt +++ b/libc/test/src/stdio/CMakeLists.txt @@ -132,6 +132,7 @@ add_fp_unittest( DEPENDS libc.src.stdio.sprintf libc.src.__support.FPUtil.fp_bits + libc.include.inttypes COMPILE_OPTIONS ${sprintf_test_copts} ) diff --git a/libc/test/src/stdio/fgetc_test.cpp b/libc/test/src/stdio/fgetc_test.cpp index 6e6c0ed9b26bf6cfe991655897e69064ca9f3006..989bb312afadf4345f0a0ebedbd7fecd5e8e1db8 100644 --- a/libc/test/src/stdio/fgetc_test.cpp +++ b/libc/test/src/stdio/fgetc_test.cpp @@ -33,7 +33,7 @@ public: // This is an error and not a real EOF. ASSERT_EQ(LIBC_NAMESPACE::feof(file), 0); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); diff --git a/libc/test/src/stdio/fgetc_unlocked_test.cpp b/libc/test/src/stdio/fgetc_unlocked_test.cpp index 0d704ecee750c028543129882f368d8387484d53..48d7a043cad7c3fdaacee71682dc639da94c9dd6 100644 --- a/libc/test/src/stdio/fgetc_unlocked_test.cpp +++ b/libc/test/src/stdio/fgetc_unlocked_test.cpp @@ -36,7 +36,7 @@ public: // This is an error and not a real EOF. ASSERT_EQ(LIBC_NAMESPACE::feof(file), 0); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); diff --git a/libc/test/src/stdio/fgets_test.cpp b/libc/test/src/stdio/fgets_test.cpp index aab8bae3d97e9900278d140818d24016e96e3ec3..d005a71710d21a875cfb6b4c079bf68acef9966f 100644 --- a/libc/test/src/stdio/fgets_test.cpp +++ b/libc/test/src/stdio/fgets_test.cpp @@ -36,7 +36,7 @@ TEST(LlvmLibcFgetsTest, WriteAndReadCharacters) { // This is an error and not a real EOF. ASSERT_EQ(LIBC_NAMESPACE::feof(file), 0); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); diff --git a/libc/test/src/stdio/fileop_test.cpp b/libc/test/src/stdio/fileop_test.cpp index d620aa076ef0dcbccde19b6dc440a013c03e553f..f5dbc49818390d47f50df32ce7d7e9be723cb1e9 100644 --- a/libc/test/src/stdio/fileop_test.cpp +++ b/libc/test/src/stdio/fileop_test.cpp @@ -39,7 +39,7 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_THAT(LIBC_NAMESPACE::fread(read_data, 1, sizeof(CONTENT), file), returns(EQ(size_t(0))).with_errno(NE(0))); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(file); ASSERT_EQ(LIBC_NAMESPACE::ferror(file), 0); @@ -70,7 +70,7 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_THAT(LIBC_NAMESPACE::fwrite(CONTENT, 1, sizeof(CONTENT), file), returns(EQ(size_t(0))).with_errno(NE(0))); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(file); @@ -78,15 +78,15 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_THAT(LIBC_NAMESPACE::fputs(CONTENT, file), returns(EQ(EOF)).with_errno(NE(0))); ASSERT_NE(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(file); ASSERT_EQ(LIBC_NAMESPACE::ferror(file), 0); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::fwrite("nothing", 1, 1, file), returns(EQ(0)).with_errno(NE(0))); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::fclose(file), 0); @@ -101,10 +101,10 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { ASSERT_EQ(LIBC_NAMESPACE::ferror(file), 0); // This is not a readable file. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::fread(data, 1, 1, file), returns(EQ(0)).with_errno(NE(0))); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(file)); @@ -119,15 +119,15 @@ TEST(LlvmLibcFILETest, SimpleFileOperations) { // Check that the other functions correctly set libc_errno. - // libc_errno = 0; + // LIBC_NAMESPACE::libc_errno = 0; // ASSERT_NE(LIBC_NAMESPACE::fseek(file, 0, SEEK_SET), 0); // ASSERT_ERRNO_FAILURE(); - // libc_errno = 0; + // LIBC_NAMESPACE::libc_errno = 0; // ASSERT_NE(LIBC_NAMESPACE::fclose(file), 0); // ASSERT_ERRNO_FAILURE(); - // libc_errno = 0; + // LIBC_NAMESPACE::libc_errno = 0; // ASSERT_EQ(LIBC_NAMESPACE::fopen("INVALID FILE NAME", "r"), // static_cast(nullptr)); // ASSERT_ERRNO_FAILURE(); @@ -163,7 +163,7 @@ TEST(LlvmLibcFILETest, FOpenFWriteSizeGreaterThanOne) { constexpr size_t WRITE_NMEMB = sizeof(WRITE_DATA) / sizeof(MyStruct); constexpr char FILENAME[] = "testdata/fread_fwrite.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; FILE *file = LIBC_NAMESPACE::fopen(FILENAME, "w"); ASSERT_FALSE(file == nullptr); ASSERT_EQ(size_t(0), LIBC_NAMESPACE::fwrite(WRITE_DATA, 0, 1, file)); diff --git a/libc/test/src/stdio/fopencookie_test.cpp b/libc/test/src/stdio/fopencookie_test.cpp index 2edfc7e210d7e449bb630ed9efebadccda762a4d..6c86b8759801e1b9bc3a231385452f3b1c1ca68b 100644 --- a/libc/test/src/stdio/fopencookie_test.cpp +++ b/libc/test/src/stdio/fopencookie_test.cpp @@ -67,7 +67,7 @@ int seek_ss(void *cookie, off64_t *offset, int whence) { } else if (whence == SEEK_END) { new_offset = *offset + ss->endpos; } else { - libc_errno = EINVAL; + LIBC_NAMESPACE::libc_errno = EINVAL; return -1; } if (new_offset < 0 || size_t(new_offset) > ss->bufsize) @@ -115,7 +115,7 @@ TEST(LlvmLibcFOpenCookie, ReadOnlyCookieTest) { ASSERT_EQ(size_t(0), LIBC_NAMESPACE::fwrite(CONTENT, 1, sizeof(CONTENT), f)); ASSERT_NE(LIBC_NAMESPACE::ferror(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(f); ASSERT_EQ(LIBC_NAMESPACE::ferror(f), 0); @@ -149,7 +149,7 @@ TEST(LlvmLibcFOpenCookie, WriteOnlyCookieTest) { LIBC_NAMESPACE::fread(read_data, 1, sizeof(WRITE_DATA), f)); ASSERT_NE(LIBC_NAMESPACE::ferror(f), 0); ASSERT_ERRNO_EQ(EBADF); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(f); ASSERT_EQ(LIBC_NAMESPACE::ferror(f), 0); @@ -178,7 +178,7 @@ TEST(LlvmLibcFOpenCookie, AppendOnlyCookieTest) { ASSERT_EQ(LIBC_NAMESPACE::fread(read_data, 1, READ_SIZE, f), size_t(0)); ASSERT_NE(LIBC_NAMESPACE::ferror(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr(f); ASSERT_EQ(LIBC_NAMESPACE::ferror(f), 0); diff --git a/libc/test/src/stdio/printf_core/converter_test.cpp b/libc/test/src/stdio/printf_core/converter_test.cpp index 8404ef6ec7db4dbbec9554a16d617a7d6f3a7254..9da749f3b8ad1ab6d651947b3200730289e07091 100644 --- a/libc/test/src/stdio/printf_core/converter_test.cpp +++ b/libc/test/src/stdio/printf_core/converter_test.cpp @@ -210,6 +210,20 @@ TEST_F(LlvmLibcPrintfConverterTest, HexConversion) { ASSERT_EQ(writer.get_chars_written(), 18); } +TEST_F(LlvmLibcPrintfConverterTest, BinaryConversion) { + LIBC_NAMESPACE::printf_core::FormatSection section; + section.has_conv = true; + section.raw_string = "%b"; + section.conv_name = 'b'; + section.conv_val_raw = 42; + LIBC_NAMESPACE::printf_core::convert(&writer, section); + + wb.buff[wb.buff_cur] = '\0'; + + ASSERT_STREQ(str, "101010"); + ASSERT_EQ(writer.get_chars_written(), 6); +} + TEST_F(LlvmLibcPrintfConverterTest, PointerConversion) { LIBC_NAMESPACE::printf_core::FormatSection section; diff --git a/libc/test/src/stdio/remove_test.cpp b/libc/test/src/stdio/remove_test.cpp index 539c23d0fb90608a3bf29119b7ef865109e5dbab..72875600903a65350ec1630dcbf594fd7f8b6ed4 100644 --- a/libc/test/src/stdio/remove_test.cpp +++ b/libc/test/src/stdio/remove_test.cpp @@ -20,7 +20,7 @@ TEST(LlvmLibcRemoveTest, CreateAndRemoveFile) { // The test strategy is to create a file and remove it, and also verify that // it was removed. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; @@ -39,7 +39,7 @@ TEST(LlvmLibcRemoveTest, CreateAndRemoveFile) { TEST(LlvmLibcRemoveTest, CreateAndRemoveDir) { // The test strategy is to create a dir and remove it, and also verify that // it was removed. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "remove.test.dir"; diff --git a/libc/test/src/stdio/setvbuf_test.cpp b/libc/test/src/stdio/setvbuf_test.cpp index 725694bb8ae1c138930cadbf46752b372d6250b3..d42ebac12ead286522c329623bb1ab434481a91b 100644 --- a/libc/test/src/stdio/setvbuf_test.cpp +++ b/libc/test/src/stdio/setvbuf_test.cpp @@ -102,6 +102,6 @@ TEST(LlvmLibcSetbufTest, InvalidBufferMode) { 0); ASSERT_ERRNO_EQ(EINVAL); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(0, LIBC_NAMESPACE::fclose(f)); } diff --git a/libc/test/src/stdio/sprintf_test.cpp b/libc/test/src/stdio/sprintf_test.cpp index 1468bffe2a031ddaa66a9e34e893dbe6e38c9bb3..186b37e2898af60c1d0e92b3d06a1e94f757f6ef 100644 --- a/libc/test/src/stdio/sprintf_test.cpp +++ b/libc/test/src/stdio/sprintf_test.cpp @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "test/UnitTest/RoundingModeUtils.h" #include "test/UnitTest/Test.h" +#include // TODO: Add a comment here explaining the printf format string. @@ -33,6 +34,25 @@ using LIBC_NAMESPACE::fputil::testing::RoundingMode; EXPECT_EQ(actual_written, static_cast(sizeof(expected_str) - 1)); \ EXPECT_STREQ(actual_str, expected_str); +#define macro_test(FMT, X, expected) \ + do { \ + for (char &c : buff) { \ + c = 0; \ + } \ + LIBC_NAMESPACE::sprintf(buff, "%" FMT, X); \ + ASSERT_STREQ(buff, expected); \ + } while (0) + +TEST(LlvmLibcSPrintfTest, Macros) { + char buff[128]; + macro_test(PRIu8, 1, "1"); + macro_test(PRIX16, 0xAA, "AA"); + macro_test(PRId32, -123, "-123"); + macro_test(PRIX32, 0xFFFFFF85, "FFFFFF85"); + macro_test(PRIo8, 0xFF, "377"); + macro_test(PRIo64, 0123, "123"); +} + TEST(LlvmLibcSPrintfTest, SimpleNoConv) { char buff[64]; int written; @@ -390,6 +410,119 @@ TEST(LlvmLibcSPrintfTest, HexConv) { ASSERT_STREQ(buff, "007F 0x1000000000 002 "); } +TEST(LlvmLibcSPrintfTest, BinConv) { + char buff[64]; + int written; + + // Basic Tests. + + written = LIBC_NAMESPACE::sprintf(buff, "%b", 42); + EXPECT_EQ(written, 6); + ASSERT_STREQ(buff, "101010"); + + written = LIBC_NAMESPACE::sprintf(buff, "%B", 12081991); + EXPECT_EQ(written, 24); + ASSERT_STREQ(buff, "101110000101101101000111"); + + // Min Width Tests. + + written = LIBC_NAMESPACE::sprintf(buff, "%10b", 0b101010); + EXPECT_EQ(written, 10); + ASSERT_STREQ(buff, " 101010"); + + written = LIBC_NAMESPACE::sprintf(buff, "%2B", 0b101010); + EXPECT_EQ(written, 6); + ASSERT_STREQ(buff, "101010"); + + // Precision Tests. + + written = LIBC_NAMESPACE::sprintf(buff, "%b", 0); + EXPECT_EQ(written, 1); + ASSERT_STREQ(buff, "0"); + + written = LIBC_NAMESPACE::sprintf(buff, "%.0b", 0); + EXPECT_EQ(written, 0); + ASSERT_STREQ(buff, ""); + + written = LIBC_NAMESPACE::sprintf(buff, "%.5b", 0b111); + EXPECT_EQ(written, 5); + ASSERT_STREQ(buff, "00111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%.2b", 0b111); + EXPECT_EQ(written, 3); + ASSERT_STREQ(buff, "111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%3b", 0b111); + EXPECT_EQ(written, 3); + ASSERT_STREQ(buff, "111"); + + // Flag Tests. + + written = LIBC_NAMESPACE::sprintf(buff, "%-5b", 0b111); + EXPECT_EQ(written, 5); + ASSERT_STREQ(buff, "111 "); + + written = LIBC_NAMESPACE::sprintf(buff, "%#b", 0b111); + EXPECT_EQ(written, 5); + ASSERT_STREQ(buff, "0b111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%#b", 0); + EXPECT_EQ(written, 1); + ASSERT_STREQ(buff, "0"); + + written = LIBC_NAMESPACE::sprintf(buff, "%#B", 0b111); + EXPECT_EQ(written, 5); + ASSERT_STREQ(buff, "0B111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%05b", 0b111); + EXPECT_EQ(written, 5); + ASSERT_STREQ(buff, "00111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%0#6b", 0b111); + EXPECT_EQ(written, 6); + ASSERT_STREQ(buff, "0b0111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%-#6b", 0b111); + EXPECT_EQ(written, 6); + ASSERT_STREQ(buff, "0b111 "); + + // Combined Tests. + + written = LIBC_NAMESPACE::sprintf(buff, "%#-07b", 0b111); + EXPECT_EQ(written, 7); + ASSERT_STREQ(buff, "0b111 "); + + written = LIBC_NAMESPACE::sprintf(buff, "%7.5b", 0b111); + EXPECT_EQ(written, 7); + ASSERT_STREQ(buff, " 00111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%#9.5B", 0b111); + EXPECT_EQ(written, 9); + ASSERT_STREQ(buff, " 0B00111"); + + written = LIBC_NAMESPACE::sprintf(buff, "%#.b", 0); + EXPECT_EQ(written, 0); + ASSERT_STREQ(buff, ""); + + written = LIBC_NAMESPACE::sprintf(buff, "%-7.5b", 0b111); + EXPECT_EQ(written, 7); + ASSERT_STREQ(buff, "00111 "); + + written = LIBC_NAMESPACE::sprintf(buff, "%5.4b", 0b1111); + EXPECT_EQ(written, 5); + ASSERT_STREQ(buff, " 1111"); + + // Multiple Conversion Tests. + + written = LIBC_NAMESPACE::sprintf(buff, "%10B %-#10b", 0b101, 0b110); + EXPECT_EQ(written, 21); + ASSERT_STREQ(buff, " 101 0b110 "); + + written = LIBC_NAMESPACE::sprintf(buff, "%-5.4b%#.4b", 0b101, 0b110); + EXPECT_EQ(written, 11); + ASSERT_STREQ(buff, "0101 0b0110"); +} + TEST(LlvmLibcSPrintfTest, PointerConv) { char buff[64]; int written; diff --git a/libc/test/src/stdio/unlocked_fileop_test.cpp b/libc/test/src/stdio/unlocked_fileop_test.cpp index cf20701ca0e3b7ab1febac539470399f514f8ab6..09697a6452f4860663700b60054acd035e969dab 100644 --- a/libc/test/src/stdio/unlocked_fileop_test.cpp +++ b/libc/test/src/stdio/unlocked_fileop_test.cpp @@ -37,7 +37,7 @@ TEST(LlvmLibcFILETest, UnlockedReadAndWrite) { LIBC_NAMESPACE::fread_unlocked(data, 1, sizeof(READ_SIZE), f)); ASSERT_NE(LIBC_NAMESPACE::ferror_unlocked(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr_unlocked(f); ASSERT_EQ(LIBC_NAMESPACE::ferror_unlocked(f), 0); @@ -58,7 +58,7 @@ TEST(LlvmLibcFILETest, UnlockedReadAndWrite) { LIBC_NAMESPACE::fwrite_unlocked(CONTENT, 1, sizeof(CONTENT), f)); ASSERT_NE(LIBC_NAMESPACE::ferror_unlocked(f), 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; LIBC_NAMESPACE::clearerr_unlocked(f); ASSERT_EQ(LIBC_NAMESPACE::ferror_unlocked(f), 0); diff --git a/libc/test/src/stdlib/StrtolTest.h b/libc/test/src/stdlib/StrtolTest.h index 50ed4cca3950e99839eb3265f668a090a81dd81b..8a67848e4c3302e839da515a0de8c0555977d232 100644 --- a/libc/test/src/stdlib/StrtolTest.h +++ b/libc/test/src/stdlib/StrtolTest.h @@ -35,7 +35,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { void InvalidBase(FunctionT func) { const char *ten = "10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(ten, nullptr, -1), ReturnT(0)); ASSERT_ERRNO_EQ(EINVAL); } @@ -45,23 +45,23 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // TODO: Look into collapsing these repeated segments. const char *ten = "10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(ten, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - ten, ptrdiff_t(2)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(ten, nullptr, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); const char *hundred = "100"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(hundred, &str_end, 10), ReturnT(100)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - hundred, ptrdiff_t(3)); const char *big_number = "1234567890"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(big_number, &str_end, 10), ReturnT(1234567890)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - big_number, ptrdiff_t(10)); @@ -69,7 +69,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // This number is larger than 2^32, meaning that if long is only 32 bits // wide, strtol will return LONG_MAX. const char *bigger_number = "12345678900"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; if constexpr (sizeof(ReturnT) < 8) { ASSERT_EQ(func(bigger_number, &str_end, 10), T_MAX); ASSERT_ERRNO_EQ(ERANGE); @@ -80,14 +80,14 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { EXPECT_EQ(str_end - bigger_number, ptrdiff_t(11)); const char *too_big_number = "123456789012345678901"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(too_big_number, &str_end, 10), T_MAX); ASSERT_ERRNO_EQ(ERANGE); EXPECT_EQ(str_end - too_big_number, ptrdiff_t(21)); const char *long_number_range_test = "10000000000000000000000000000000000000000000000000"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(long_number_range_test, &str_end, 10), T_MAX); ASSERT_ERRNO_EQ(ERANGE); EXPECT_EQ(str_end - long_number_range_test, ptrdiff_t(50)); @@ -95,19 +95,19 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // For most negative numbers, the unsigned functions treat it the same as // casting a negative variable to an unsigned type. const char *negative = "-100"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative, &str_end, 10), ReturnT(-100)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - negative, ptrdiff_t(4)); const char *big_negative_number = "-1234567890"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(big_negative_number, &str_end, 10), ReturnT(-1234567890)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - big_negative_number, ptrdiff_t(11)); const char *too_big_negative_number = "-123456789012345678901"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // If the number is signed, it should return the smallest negative number // for the current type, but if it's unsigned it should max out and return // the largest positive number for the current type. From the standard: @@ -125,73 +125,73 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *spaces_before = " 10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(spaces_before, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - spaces_before, ptrdiff_t(7)); const char *spaces_after = "10 "; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(spaces_after, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - spaces_after, ptrdiff_t(2)); const char *word_before = "word10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(word_before, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - word_before, ptrdiff_t(0)); const char *word_after = "10word"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(word_after, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - word_after, ptrdiff_t(2)); const char *two_numbers = "10 999"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(two_numbers, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - two_numbers, ptrdiff_t(2)); const char *two_signs = "--10 999"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(two_signs, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - two_signs, ptrdiff_t(0)); const char *sign_before = "+2=4"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(sign_before, &str_end, 10), ReturnT(2)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - sign_before, ptrdiff_t(2)); const char *sign_after = "2+2=4"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(sign_after, &str_end, 10), ReturnT(2)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - sign_after, ptrdiff_t(1)); const char *tab_before = "\t10"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(tab_before, &str_end, 10), ReturnT(10)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - tab_before, ptrdiff_t(3)); const char *all_together = "\t -12345and+67890"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(all_together, &str_end, 10), ReturnT(-12345)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - all_together, ptrdiff_t(9)); const char *just_spaces = " "; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_spaces, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_spaces, ptrdiff_t(0)); const char *just_space_and_sign = " +"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_space_and_sign, &str_end, 10), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_space_and_sign, ptrdiff_t(0)); @@ -209,12 +209,12 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { for (int first_digit = 0; first_digit <= 36; ++first_digit) { small_string[0] = int_to_b36_char(first_digit); if (first_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(first_digit)); ASSERT_ERRNO_SUCCESS(); } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } @@ -227,18 +227,18 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { for (int second_digit = 0; second_digit <= 36; ++second_digit) { small_string[1] = int_to_b36_char(second_digit); if (first_digit < base && second_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ( func(small_string, nullptr, base), static_cast(second_digit + (first_digit * base))); ASSERT_ERRNO_SUCCESS(); } else if (first_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(first_digit)); ASSERT_ERRNO_SUCCESS(); } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } @@ -256,14 +256,14 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { if (first_digit < base && second_digit < base && third_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(third_digit + (second_digit * base) + (first_digit * base * base))); ASSERT_ERRNO_SUCCESS(); } else if (first_digit < base && second_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ( func(small_string, nullptr, base), static_cast(second_digit + (first_digit * base))); @@ -273,23 +273,23 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // The number is treated as a one digit hexadecimal. if (base == 16 && first_digit == 0 && second_digit == 33) { if (third_digit < base) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(third_digit)); ASSERT_ERRNO_SUCCESS(); } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), static_cast(first_digit)); ASSERT_ERRNO_SUCCESS(); } } else { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(small_string, nullptr, base), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); } @@ -303,19 +303,19 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *no_prefix = "123abc"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(no_prefix, &str_end, 16), ReturnT(0x123abc)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - no_prefix, ptrdiff_t(6)); const char *yes_prefix = "0x456def"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(yes_prefix, &str_end, 16), ReturnT(0x456def)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - yes_prefix, ptrdiff_t(8)); const char *letter_after_prefix = "0xabc123"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(letter_after_prefix, &str_end, 16), ReturnT(0xabc123)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - letter_after_prefix, ptrdiff_t(8)); @@ -326,7 +326,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for unsigned 32 bit numbers const char *max_32_bit_value = "0xFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_32_bit_value, &str_end, 0), ((is_signed_v && sizeof(ReturnT) == 4) ? T_MAX @@ -335,7 +335,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { EXPECT_EQ(str_end - max_32_bit_value, ptrdiff_t(10)); const char *negative_max_32_bit_value = "-0xFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative_max_32_bit_value, &str_end, 0), ((is_signed_v && sizeof(ReturnT) == 4) ? T_MIN @@ -346,13 +346,13 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for signed 32 bit numbers const char *max_31_bit_value = "0x7FFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_31_bit_value, &str_end, 0), ReturnT(0x7FFFFFFF)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - max_31_bit_value, ptrdiff_t(10)); const char *negative_max_31_bit_value = "-0x7FFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative_max_31_bit_value, &str_end, 0), -ReturnT(0x7FFFFFFF)); ASSERT_ERRNO_SUCCESS(); @@ -361,7 +361,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for unsigned 64 bit numbers const char *max_64_bit_value = "0xFFFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_64_bit_value, &str_end, 0), (is_signed_v || sizeof(ReturnT) < 8 ? T_MAX @@ -372,7 +372,7 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // See the end of CleanBase10Decode for an explanation of how this large // negative number can end up as T_MAX. const char *negative_max_64_bit_value = "-0xFFFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ( func(negative_max_64_bit_value, &str_end, 0), (is_signed_v @@ -384,14 +384,14 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { // Max size for signed 64 bit numbers const char *max_63_bit_value = "0x7FFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(max_63_bit_value, &str_end, 0), (sizeof(ReturnT) < 8 ? T_MAX : ReturnT(0x7FFFFFFFFFFFFFFF))); ASSERT_ERRNO_EQ(sizeof(ReturnT) < 8 ? ERANGE : 0); EXPECT_EQ(str_end - max_63_bit_value, ptrdiff_t(18)); const char *negative_max_63_bit_value = "-0x7FFFFFFFFFFFFFFF"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(negative_max_63_bit_value, &str_end, 0), (sizeof(ReturnT) >= 8 ? -ReturnT(0x7FFFFFFFFFFFFFFF) : (is_signed_v ? T_MIN : T_MAX))); @@ -403,23 +403,23 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *just_prefix = "0x"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_prefix, &str_end, 16), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_prefix, ptrdiff_t(1)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_prefix, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_prefix, ptrdiff_t(1)); const char *prefix_with_x_after = "0xx"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(prefix_with_x_after, &str_end, 16), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - prefix_with_x_after, ptrdiff_t(1)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(prefix_with_x_after, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - prefix_with_x_after, ptrdiff_t(1)); @@ -429,43 +429,43 @@ struct StrtoTest : public LIBC_NAMESPACE::testing::Test { char *str_end = nullptr; const char *base_ten = "12345"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_ten, &str_end, 0), ReturnT(12345)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_ten, ptrdiff_t(5)); const char *base_sixteen_no_prefix = "123abc"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_sixteen_no_prefix, &str_end, 0), ReturnT(123)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_sixteen_no_prefix, ptrdiff_t(3)); const char *base_sixteen_with_prefix = "0x456def"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_sixteen_with_prefix, &str_end, 0), ReturnT(0x456def)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_sixteen_with_prefix, ptrdiff_t(8)); const char *base_eight_with_prefix = "012345"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(base_eight_with_prefix, &str_end, 0), ReturnT(012345)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - base_eight_with_prefix, ptrdiff_t(6)); const char *just_zero = "0"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_zero, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_zero, ptrdiff_t(1)); const char *just_zero_x = "0x"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_zero_x, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_zero_x, ptrdiff_t(1)); const char *just_zero_eight = "08"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(func(just_zero_eight, &str_end, 0), ReturnT(0)); ASSERT_ERRNO_SUCCESS(); EXPECT_EQ(str_end - just_zero_eight, ptrdiff_t(1)); diff --git a/libc/test/src/stdlib/atof_test.cpp b/libc/test/src/stdlib/atof_test.cpp index 858ab326e38d0131b0a1d9b5784b577156098c34..1e4259b792d7ef1b1cf16be79a88ba438c938b99 100644 --- a/libc/test/src/stdlib/atof_test.cpp +++ b/libc/test/src/stdlib/atof_test.cpp @@ -23,13 +23,13 @@ TEST(LlvmLibcAToFTest, SimpleTest) { LIBC_NAMESPACE::fputil::FPBits expected_fp = LIBC_NAMESPACE::fputil::FPBits(uint64_t(0x405ec00000000000)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::atof("123"), Succeeds(expected_fp.get_val())); } TEST(LlvmLibcAToFTest, FailedParsingTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // atof does not flag errors. EXPECT_THAT(LIBC_NAMESPACE::atof("???"), Succeeds(0.0)); } diff --git a/libc/test/src/stdlib/strtod_test.cpp b/libc/test/src/stdlib/strtod_test.cpp index e68c8610b40704cd91ddaf2d0c7b9299a4c58549..92d14640e653320f238ba72575c11e2019a590dc 100644 --- a/libc/test/src/stdlib/strtod_test.cpp +++ b/libc/test/src/stdlib/strtod_test.cpp @@ -46,7 +46,7 @@ public: LIBC_NAMESPACE::fputil::FPBits expected_fp = LIBC_NAMESPACE::fputil::FPBits(expectedRawData); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; double result = LIBC_NAMESPACE::strtod(inputString, &str_end); if (expectedErrno == 0) EXPECT_THAT(result, Succeeds(expected_fp.get_val())); diff --git a/libc/test/src/stdlib/strtof_test.cpp b/libc/test/src/stdlib/strtof_test.cpp index b43c32f9026164de63bfe357c5b2624d0eb8e68f..d7991745b69e6cdbfa15d57513325fbe8f34d9d8 100644 --- a/libc/test/src/stdlib/strtof_test.cpp +++ b/libc/test/src/stdlib/strtof_test.cpp @@ -43,7 +43,7 @@ public: LIBC_NAMESPACE::fputil::FPBits expected_fp = LIBC_NAMESPACE::fputil::FPBits(expectedRawData); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; float result = LIBC_NAMESPACE::strtof(inputString, &str_end); EXPECT_EQ(str_end - inputString, expectedStrLen); diff --git a/libc/test/src/stdlib/strtoint32_test.cpp b/libc/test/src/stdlib/strtoint32_test.cpp index 4ca20f3333f56013358b8d073808c8c318554a5c..a7c9141d9f79b02197cd0b93db672ff938793ced 100644 --- a/libc/test/src/stdlib/strtoint32_test.cpp +++ b/libc/test/src/stdlib/strtoint32_test.cpp @@ -20,7 +20,7 @@ int32_t strtoint32(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); @@ -32,7 +32,7 @@ uint32_t strtouint32(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); diff --git a/libc/test/src/stdlib/strtoint64_test.cpp b/libc/test/src/stdlib/strtoint64_test.cpp index f8d807b146f2ec4e0a8916639f2c9687d8e486b6..350b5aca4c8508cae20c7b31c1b460a0ab1bc72e 100644 --- a/libc/test/src/stdlib/strtoint64_test.cpp +++ b/libc/test/src/stdlib/strtoint64_test.cpp @@ -20,7 +20,7 @@ int64_t strtoint64(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); @@ -32,7 +32,7 @@ uint64_t strtouint64(const char *__restrict str, char **__restrict str_end, int base) { auto result = internal::strtointeger(str, base); if (result.has_error()) - libc_errno = result.error; + LIBC_NAMESPACE::libc_errno = result.error; if (str_end != nullptr) *str_end = const_cast(str + result.parsed_len); diff --git a/libc/test/src/stdlib/strtold_test.cpp b/libc/test/src/stdlib/strtold_test.cpp index cbe0a47b9b710b86a8a47dfd2970e5402e405263..0525589795565793b5e659270586a17915bc7647 100644 --- a/libc/test/src/stdlib/strtold_test.cpp +++ b/libc/test/src/stdlib/strtold_test.cpp @@ -77,7 +77,7 @@ public: LIBC_NAMESPACE::fputil::FPBits(expectedRawData); const int expected_errno = expectedErrno; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; long double result = LIBC_NAMESPACE::strtold(inputString, &str_end); LIBC_NAMESPACE::fputil::FPBits actual_fp = diff --git a/libc/test/src/string/strdup_test.cpp b/libc/test/src/string/strdup_test.cpp index caf8c2e61c0e2a5e6d028b9efc01c04652301110..fd3cceaaa17cfc762e047c96ffa05ef0b5b77347 100644 --- a/libc/test/src/string/strdup_test.cpp +++ b/libc/test/src/string/strdup_test.cpp @@ -15,7 +15,7 @@ TEST(LlvmLibcStrDupTest, EmptyString) { const char *empty = ""; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; char *result = LIBC_NAMESPACE::strdup(empty); ASSERT_ERRNO_SUCCESS(); @@ -28,7 +28,7 @@ TEST(LlvmLibcStrDupTest, EmptyString) { TEST(LlvmLibcStrDupTest, AnyString) { const char *abc = "abc"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; char *result = LIBC_NAMESPACE::strdup(abc); ASSERT_ERRNO_SUCCESS(); @@ -39,7 +39,7 @@ TEST(LlvmLibcStrDupTest, AnyString) { } TEST(LlvmLibcStrDupTest, NullPtr) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; char *result = LIBC_NAMESPACE::strdup(nullptr); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/sys/mman/linux/madvise_test.cpp b/libc/test/src/sys/mman/linux/madvise_test.cpp index e45cf19f8913ec79487cd4ba5c902f5f7e726a52..6768d111c0d913b1b57c4342c905827f6b3ac2dc 100644 --- a/libc/test/src/sys/mman/linux/madvise_test.cpp +++ b/libc/test/src/sys/mman/linux/madvise_test.cpp @@ -20,7 +20,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMadviseTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -38,7 +38,7 @@ TEST(LlvmLibcMadviseTest, NoError) { } TEST(LlvmLibcMadviseTest, Error_BadPtr) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::madvise(nullptr, 8, MADV_SEQUENTIAL), Fails(ENOMEM)); } diff --git a/libc/test/src/sys/mman/linux/mincore_test.cpp b/libc/test/src/sys/mman/linux/mincore_test.cpp index 2814694849fc60ece2f4239a7be5558719695c2f..8e0c29c2ac177701e9e02b7fa48d39090a317b4e 100644 --- a/libc/test/src/sys/mman/linux/mincore_test.cpp +++ b/libc/test/src/sys/mman/linux/mincore_test.cpp @@ -27,7 +27,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMincoreTest, UnMappedMemory) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; unsigned char vec; int res = LIBC_NAMESPACE::mincore(nullptr, 1, &vec); EXPECT_THAT(res, Fails(ENOMEM, -1)); @@ -39,7 +39,7 @@ TEST(LlvmLibcMincoreTest, UnalignedAddr) { MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(static_cast(addr) + 1, 1, nullptr); EXPECT_THAT(res, Fails(EINVAL, -1)); EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); @@ -51,7 +51,7 @@ TEST(LlvmLibcMincoreTest, InvalidVec) { MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, 1, nullptr); EXPECT_THAT(res, Fails(EFAULT, -1)); } @@ -63,7 +63,7 @@ TEST(LlvmLibcMincoreTest, NoError) { EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); unsigned char vec; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, 1, &vec); EXPECT_THAT(res, Succeeds()); EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); @@ -76,7 +76,7 @@ TEST(LlvmLibcMincoreTest, NegativeLength) { EXPECT_NE(addr, MAP_FAILED); EXPECT_EQ(reinterpret_cast(addr) % page_size, 0ul); unsigned char vec; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, -1, &vec); EXPECT_THAT(res, Fails(ENOMEM, -1)); EXPECT_THAT(LIBC_NAMESPACE::munmap(addr, page_size), Succeeds()); @@ -102,11 +102,11 @@ TEST(LlvmLibcMincoreTest, PageOut) { // page out the memory { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::madvise(addr, page_size, MADV_DONTNEED), Succeeds()); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int res = LIBC_NAMESPACE::mincore(addr, page_size, &vec); EXPECT_EQ(vec & 1u, 0u); EXPECT_THAT(res, Succeeds()); diff --git a/libc/test/src/sys/mman/linux/mlock_test.cpp b/libc/test/src/sys/mman/linux/mlock_test.cpp index f1d1af1e769203bba2f18f28be165f8f53449a11..804038a68a7e098ee494490f3aafdde78aed251d 100644 --- a/libc/test/src/sys/mman/linux/mlock_test.cpp +++ b/libc/test/src/sys/mman/linux/mlock_test.cpp @@ -120,7 +120,7 @@ TEST(LlvmLibcMlockTest, MLock2) { TEST(LlvmLibcMlockTest, InvalidFlag) { size_t alloc_size = 128; // page size - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -151,8 +151,9 @@ TEST(LlvmLibcMlockTest, MLockAll) { Succeeds()); auto retval = LIBC_NAMESPACE::mlockall(MCL_CURRENT); if (retval == -1) { - EXPECT_TRUE(libc_errno == ENOMEM || libc_errno == EPERM); - libc_errno = 0; + EXPECT_TRUE(LIBC_NAMESPACE::libc_errno == ENOMEM || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; return; } unsigned char vec; @@ -164,8 +165,9 @@ TEST(LlvmLibcMlockTest, MLockAll) { { auto retval = LIBC_NAMESPACE::mlockall(MCL_FUTURE); if (retval == -1) { - EXPECT_TRUE(libc_errno == ENOMEM || libc_errno == EPERM); - libc_errno = 0; + EXPECT_TRUE(LIBC_NAMESPACE::libc_errno == ENOMEM || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; return; } PageHolder holder; @@ -180,8 +182,9 @@ TEST(LlvmLibcMlockTest, MLockAll) { { auto retval = LIBC_NAMESPACE::mlockall(MCL_FUTURE | MCL_ONFAULT); if (retval == -1) { - EXPECT_TRUE(libc_errno == ENOMEM || libc_errno == EPERM); - libc_errno = 0; + EXPECT_TRUE(LIBC_NAMESPACE::libc_errno == ENOMEM || + LIBC_NAMESPACE::libc_errno == EPERM); + LIBC_NAMESPACE::libc_errno = 0; return; } PageHolder holder; diff --git a/libc/test/src/sys/mman/linux/mmap_test.cpp b/libc/test/src/sys/mman/linux/mmap_test.cpp index b996f26db8605f4a5df05b741c87c888818dac7c..dcbc75808f13cd65f1780fd4a5eec866d297adc2 100644 --- a/libc/test/src/sys/mman/linux/mmap_test.cpp +++ b/libc/test/src/sys/mman/linux/mmap_test.cpp @@ -19,7 +19,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMMapTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -34,7 +34,7 @@ TEST(LlvmLibcMMapTest, NoError) { } TEST(LlvmLibcMMapTest, Error_InvalidSize) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, 0, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); EXPECT_THAT(addr, Fails(EINVAL, MAP_FAILED)); diff --git a/libc/test/src/sys/mman/linux/mprotect_test.cpp b/libc/test/src/sys/mman/linux/mprotect_test.cpp index 96f625984101dc4bc6699b4743075b7d7866bf5e..46e449e54779fa03875a3692a8d9446e22673461 100644 --- a/libc/test/src/sys/mman/linux/mprotect_test.cpp +++ b/libc/test/src/sys/mman/linux/mprotect_test.cpp @@ -21,7 +21,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcMProtectTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/sys/mman/linux/posix_madvise_test.cpp b/libc/test/src/sys/mman/linux/posix_madvise_test.cpp index d20db69042b7adc43b0140ab736d6b01347a49d6..ee6489c5ed2f53a7a509acfb776a49bc7c14ceb6 100644 --- a/libc/test/src/sys/mman/linux/posix_madvise_test.cpp +++ b/libc/test/src/sys/mman/linux/posix_madvise_test.cpp @@ -20,7 +20,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcPosixMadviseTest, NoError) { size_t alloc_size = 128; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; void *addr = LIBC_NAMESPACE::mmap(nullptr, alloc_size, PROT_READ, MAP_ANONYMOUS | MAP_PRIVATE, -1, 0); ASSERT_ERRNO_SUCCESS(); @@ -38,7 +38,7 @@ TEST(LlvmLibcPosixMadviseTest, NoError) { } TEST(LlvmLibcPosixMadviseTest, Error_BadPtr) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // posix_madvise is a no-op on DONTNEED, so it shouldn't fail even with the // nullptr. EXPECT_EQ(LIBC_NAMESPACE::posix_madvise(nullptr, 8, POSIX_MADV_DONTNEED), 0); diff --git a/libc/test/src/sys/prctl/linux/prctl_test.cpp b/libc/test/src/sys/prctl/linux/prctl_test.cpp index 6278dcec588af7467598552978c8c6c7c1f86a52..b528edc65595d849291abceb61565cf3d6b48d9f 100644 --- a/libc/test/src/sys/prctl/linux/prctl_test.cpp +++ b/libc/test/src/sys/prctl/linux/prctl_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcSysPrctlTest, GetSetName) { TEST(LlvmLibcSysPrctlTest, GetTHPDisable) { // Manually check errno since the return value logic here is not // covered in ErrnoSetterMatcher. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int ret = LIBC_NAMESPACE::prctl(PR_GET_THP_DISABLE, 0, 0, 0, 0); ASSERT_ERRNO_SUCCESS(); // PR_GET_THP_DISABLE return (as the function result) the current diff --git a/libc/test/src/sys/random/linux/getrandom_test.cpp b/libc/test/src/sys/random/linux/getrandom_test.cpp index 5a595afb0cdaa7a211379f155c197f5539bad597..e3481b73ca002793b3f312ca50dcd4cd409ae9f1 100644 --- a/libc/test/src/sys/random/linux/getrandom_test.cpp +++ b/libc/test/src/sys/random/linux/getrandom_test.cpp @@ -15,13 +15,13 @@ TEST(LlvmLibcGetRandomTest, InvalidFlag) { LIBC_NAMESPACE::cpp::array buffer; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::getrandom(buffer.data(), buffer.size(), -1), LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails(EINVAL)); } TEST(LlvmLibcGetRandomTest, InvalidBuffer) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::getrandom(nullptr, 65536, 0), LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails(EFAULT)); } diff --git a/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp b/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp index 1a0d79f4e7527dded64f4a1cc6344c3f3e7a6c0a..62d21c33e99868cfe7c6526b3db26817c49684eb 100644 --- a/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp +++ b/libc/test/src/sys/resource/getrlimit_setrlimit_test.cpp @@ -29,7 +29,7 @@ TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { constexpr const char *TEST_FILE1 = "testdata/resource_limits1.test"; constexpr const char *TEST_FILE2 = "testdata/resource_limits2.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd1 = LIBC_NAMESPACE::open(TEST_FILE1, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd1, 0); @@ -54,7 +54,7 @@ TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { ASSERT_LT(fd2, 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::close(fd1), Succeeds(0)); fd2 = LIBC_NAMESPACE::open(TEST_FILE2, O_RDONLY); @@ -64,7 +64,7 @@ TEST(LlvmLibcResourceLimitsTest, SetNoFileLimit) { ASSERT_LT(fd1, 0); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::close(fd2), Succeeds(0)); ASSERT_THAT(LIBC_NAMESPACE::unlink(TEST_FILE1), Succeeds(0)); diff --git a/libc/test/src/sys/select/select_ui_test.cpp b/libc/test/src/sys/select/select_ui_test.cpp index 2e6baced801b106b1aa7d8d785a932f41be11451..a158cab8ff058430ed13197d98a633e99605d298 100644 --- a/libc/test/src/sys/select/select_ui_test.cpp +++ b/libc/test/src/sys/select/select_ui_test.cpp @@ -18,7 +18,7 @@ // Instead, one has to run it manually and press a key on the keyboard // to make the test succeed. TEST(LlvmLibcSelectTest, ReadStdinAfterSelect) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; constexpr int STDIN_FD = 0; fd_set set; FD_ZERO(&set); diff --git a/libc/test/src/sys/sendfile/sendfile_test.cpp b/libc/test/src/sys/sendfile/sendfile_test.cpp index 5ea9ca8d05c5abe6dacf8dcaeb2669dedd752bc6..59025438a24671e7fb5c25f067417db28df55bb7 100644 --- a/libc/test/src/sys/sendfile/sendfile_test.cpp +++ b/libc/test/src/sys/sendfile/sendfile_test.cpp @@ -35,7 +35,7 @@ TEST(LlvmLibcSendfileTest, CreateAndTransfer) { constexpr const char *OUT_FILE = "testdata/sendfile_out.test"; const char IN_DATA[] = "sendfile test"; constexpr ssize_t IN_SIZE = ssize_t(sizeof(IN_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int in_fd = LIBC_NAMESPACE::open(IN_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(in_fd, 0); diff --git a/libc/test/src/sys/stat/chmod_test.cpp b/libc/test/src/sys/stat/chmod_test.cpp index 6fd056b2bd6cc31175e6fe88eb4f5a72ea4bb4a8..c688996615ceef16e7dff1af371003006fc26e7c 100644 --- a/libc/test/src/sys/stat/chmod_test.cpp +++ b/libc/test/src/sys/stat/chmod_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { constexpr const char *TEST_FILE = "testdata/chmod.test"; const char WRITE_DATA[] = "test data"; constexpr ssize_t WRITE_SIZE = ssize_t(sizeof(WRITE_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY); ASSERT_GT(fd, 0); @@ -46,7 +46,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { // Opening for writing should fail. EXPECT_EQ(LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // But opening for reading should succeed. fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_RDONLY); EXPECT_GT(fd, 0); @@ -57,9 +57,9 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { } TEST(LlvmLibcChmodTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_THAT(LIBC_NAMESPACE::chmod("non-existent-file", S_IRUSR), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/fchmod_test.cpp b/libc/test/src/sys/stat/fchmod_test.cpp index a0a93b03d22ed91ae6ee971c4175c7249865d405..91c0f68b8708c842ca3c357678852e30534178f5 100644 --- a/libc/test/src/sys/stat/fchmod_test.cpp +++ b/libc/test/src/sys/stat/fchmod_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { constexpr const char *TEST_FILE = "testdata/fchmod.test"; const char WRITE_DATA[] = "test data"; constexpr ssize_t WRITE_SIZE = ssize_t(sizeof(WRITE_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY); ASSERT_GT(fd, 0); @@ -46,7 +46,7 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { // Opening for writing should fail. EXPECT_EQ(LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // But opening for reading should succeed. fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_RDONLY); EXPECT_GT(fd, 0); @@ -57,8 +57,8 @@ TEST(LlvmLibcChmodTest, ChangeAndOpen) { } TEST(LlvmLibcChmodTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::fchmod(-1, S_IRUSR), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/fchmodat_test.cpp b/libc/test/src/sys/stat/fchmodat_test.cpp index e2cf170728ec1e3ddc6cef5ffd8a17e7727b32b6..c43ef8ae13315a1bd30ef60b81815ae1b2523bc4 100644 --- a/libc/test/src/sys/stat/fchmodat_test.cpp +++ b/libc/test/src/sys/stat/fchmodat_test.cpp @@ -30,7 +30,7 @@ TEST(LlvmLibcFchmodatTest, ChangeAndOpen) { constexpr const char *TEST_FILE_BASENAME = "fchmodat.test"; const char WRITE_DATA[] = "fchmodat test"; constexpr ssize_t WRITE_SIZE = ssize_t(sizeof(WRITE_DATA)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -49,7 +49,7 @@ TEST(LlvmLibcFchmodatTest, ChangeAndOpen) { // Opening for writing should fail. EXPECT_EQ(LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_WRONLY), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // But opening for reading should succeed. fd = LIBC_NAMESPACE::open(TEST_FILE, O_APPEND | O_RDONLY); EXPECT_GT(fd, 0); @@ -63,10 +63,10 @@ TEST(LlvmLibcFchmodatTest, ChangeAndOpen) { } TEST(LlvmLibcFchmodatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_THAT( LIBC_NAMESPACE::fchmodat(AT_FDCWD, "non-existent-file", S_IRUSR, 0), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/fstat_test.cpp b/libc/test/src/sys/stat/fstat_test.cpp index 33769ea1f05af771569b627b6efc8d283dc02025..1379eae26a47aed2669ef6554973df5d6d4fced1 100644 --- a/libc/test/src/sys/stat/fstat_test.cpp +++ b/libc/test/src/sys/stat/fstat_test.cpp @@ -26,7 +26,7 @@ TEST(LlvmLibcFStatTest, CreatAndReadMode) { // make it readonly using chmod. We test that chmod actually succeeded by // trying to open the file for writing and failing. constexpr const char *TEST_FILE = "testdata/fstat.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -42,9 +42,9 @@ TEST(LlvmLibcFStatTest, CreatAndReadMode) { } TEST(LlvmLibcFStatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; struct stat statbuf; ASSERT_THAT(LIBC_NAMESPACE::fstat(-1, &statbuf), Fails(EBADF)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/lstat_test.cpp b/libc/test/src/sys/stat/lstat_test.cpp index a3b3c2cb0c1df28bda9bef2c41a04b285251a8b2..b44b3d1a59ce7bf3327850e3ff537974c92a0b48 100644 --- a/libc/test/src/sys/stat/lstat_test.cpp +++ b/libc/test/src/sys/stat/lstat_test.cpp @@ -26,7 +26,7 @@ TEST(LlvmLibcLStatTest, CreatAndReadMode) { // make it readonly using chmod. We test that chmod actually succeeded by // trying to open the file for writing and failing. constexpr const char *TEST_FILE = "testdata/lstat.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -42,10 +42,10 @@ TEST(LlvmLibcLStatTest, CreatAndReadMode) { } TEST(LlvmLibcLStatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; struct stat statbuf; ASSERT_THAT(LIBC_NAMESPACE::lstat("non-existent-file", &statbuf), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/sys/stat/stat_test.cpp b/libc/test/src/sys/stat/stat_test.cpp index 1286e12fd6110c147981476f35e3b21efefc4a28..baf363382022ad3f103d293e36a735662fd66a74 100644 --- a/libc/test/src/sys/stat/stat_test.cpp +++ b/libc/test/src/sys/stat/stat_test.cpp @@ -26,7 +26,7 @@ TEST(LlvmLibcStatTest, CreatAndReadMode) { // make it readonly using chmod. We test that chmod actually succeeded by // trying to open the file for writing and failing. constexpr const char *TEST_FILE = "testdata/stat.test"; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_CREAT | O_WRONLY, S_IRWXU); ASSERT_GT(fd, 0); @@ -42,10 +42,10 @@ TEST(LlvmLibcStatTest, CreatAndReadMode) { } TEST(LlvmLibcStatTest, NonExistentFile) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; struct stat statbuf; ASSERT_THAT(LIBC_NAMESPACE::stat("non-existent-file", &statbuf), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/termios/termios_test.cpp b/libc/test/src/termios/termios_test.cpp index 790c010c5b7eb80b0787c34044177a227a6972ff..f8fc09a8bbf0e29dffa00b2b89e45f3204fde620 100644 --- a/libc/test/src/termios/termios_test.cpp +++ b/libc/test/src/termios/termios_test.cpp @@ -30,21 +30,21 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcTermiosTest, SpeedSmokeTest) { struct termios t; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::cfsetispeed(&t, B50), Succeeds(0)); ASSERT_EQ(LIBC_NAMESPACE::cfgetispeed(&t), speed_t(B50)); ASSERT_THAT(LIBC_NAMESPACE::cfsetospeed(&t, B75), Succeeds(0)); ASSERT_EQ(LIBC_NAMESPACE::cfgetospeed(&t), speed_t(B75)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::cfsetispeed(&t, ~CBAUD), Fails(EINVAL)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::cfsetospeed(&t, ~CBAUD), Fails(EINVAL)); } TEST(LlvmLibcTermiosTest, GetAttrSmokeTest) { struct termios t; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open("/dev/tty", O_RDONLY); if (fd < 0) return; // When /dev/tty is not available, no point continuing. @@ -54,7 +54,7 @@ TEST(LlvmLibcTermiosTest, GetAttrSmokeTest) { } TEST(LlvmLibcTermiosTest, TcGetSidSmokeTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open("/dev/tty", O_RDONLY); if (fd < 0) return; // When /dev/tty is not available, no point continuing. diff --git a/libc/test/src/time/gmtime_test.cpp b/libc/test/src/time/gmtime_test.cpp index d4bcc7d5831e95abeb74cf3679b299687802b3f1..433fbf6667057faf4452c1ca486ca1e796cea7be 100644 --- a/libc/test/src/time/gmtime_test.cpp +++ b/libc/test/src/time/gmtime_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcGmTime, OutOfRange) { EXPECT_TRUE(tm_data == nullptr); ASSERT_ERRNO_EQ(EOVERFLOW); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; seconds = INT_MIN * static_cast( TimeConstants::NUMBER_OF_SECONDS_IN_LEAP_YEAR) - 1; diff --git a/libc/test/src/time/nanosleep_test.cpp b/libc/test/src/time/nanosleep_test.cpp index 8baaa29df478500dd305475663bffd8620d7e8bd..2a6eea4d5e161316317e089e9accef7a3ee7818c 100644 --- a/libc/test/src/time/nanosleep_test.cpp +++ b/libc/test/src/time/nanosleep_test.cpp @@ -18,7 +18,7 @@ namespace cpp = LIBC_NAMESPACE::cpp; TEST(LlvmLibcNanosleep, SmokeTest) { // TODO: When we have the code to read clocks, test that time has passed. using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; struct timespec tim = {1, 500}; struct timespec tim2 = {0, 0}; diff --git a/libc/test/src/unistd/access_test.cpp b/libc/test/src/unistd/access_test.cpp index 1371afa1a00fa604a77c5279db4b266bfeddf35a..808cd5f3c8d82446cc4eb36155510d364636c47c 100644 --- a/libc/test/src/unistd/access_test.cpp +++ b/libc/test/src/unistd/access_test.cpp @@ -21,7 +21,7 @@ TEST(LlvmLibcAccessTest, CreateAndTest) { // The test strategy is to repeatedly create a file in different modes and // test that it is accessable in those modes but not in others. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "access.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); @@ -46,10 +46,10 @@ TEST(LlvmLibcAccessTest, CreateAndTest) { ASSERT_ERRNO_SUCCESS(); ASSERT_EQ(LIBC_NAMESPACE::access(TEST_FILE, R_OK), -1); ASSERT_ERRNO_EQ(EACCES); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::access(TEST_FILE, W_OK), -1); ASSERT_ERRNO_EQ(EACCES); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_THAT(LIBC_NAMESPACE::unlink(TEST_FILE), Succeeds(0)); } diff --git a/libc/test/src/unistd/chdir_test.cpp b/libc/test/src/unistd/chdir_test.cpp index f187a771a1220a80ca1ca8b94015a78b70e928af..51dc7bb15d3ee6d822205c2c9c5b143019480d7c 100644 --- a/libc/test/src/unistd/chdir_test.cpp +++ b/libc/test/src/unistd/chdir_test.cpp @@ -27,7 +27,7 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { auto TEST_FILE = libc_make_test_file_path(FILENAME2); constexpr const char *FILENAME3 = "chdir.test"; auto TEST_FILE_BASE = libc_make_test_file_path(FILENAME3); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_PATH); ASSERT_GT(fd, 0); @@ -42,8 +42,8 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { } TEST(LlvmLibcChdirTest, ChangeToNonExistentDir) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; ASSERT_THAT(LIBC_NAMESPACE::chdir("non-existent-dir"), Fails(ENOENT)); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/unistd/dup2_test.cpp b/libc/test/src/unistd/dup2_test.cpp index 6fa09670e90a9014c469b8371bc4844c94539123..2b2b3f3eef9a8eb2dc1a248f031e9b3024605dfc 100644 --- a/libc/test/src/unistd/dup2_test.cpp +++ b/libc/test/src/unistd/dup2_test.cpp @@ -20,7 +20,7 @@ TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { constexpr int DUPFD = 0xD0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "dup2.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); diff --git a/libc/test/src/unistd/dup3_test.cpp b/libc/test/src/unistd/dup3_test.cpp index cb0761ad0d87d5a66a7aab380c82bd5c3b1fad61..7b1c8e0e25190f91e8b91a0223e1202a7b74e9b3 100644 --- a/libc/test/src/unistd/dup3_test.cpp +++ b/libc/test/src/unistd/dup3_test.cpp @@ -25,7 +25,7 @@ TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { constexpr int DUPFD = 0xD0; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "dup3.test"; diff --git a/libc/test/src/unistd/dup_test.cpp b/libc/test/src/unistd/dup_test.cpp index f303cda5caacf3088ff01241faa5305af9550f3e..c7bf877142102cf628e0fdf2157fb8bdb754614f 100644 --- a/libc/test/src/unistd/dup_test.cpp +++ b/libc/test/src/unistd/dup_test.cpp @@ -19,7 +19,7 @@ #include TEST(LlvmLibcdupTest, ReadAndWriteViaDup) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; constexpr const char *FILENAME = "dup.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); diff --git a/libc/test/src/unistd/fchdir_test.cpp b/libc/test/src/unistd/fchdir_test.cpp index 0d1fc810a9e30eef31a1ce6f71ccb6e8b12840f0..ae88e1f22ed6b7684ce025c37253b383236d25d2 100644 --- a/libc/test/src/unistd/fchdir_test.cpp +++ b/libc/test/src/unistd/fchdir_test.cpp @@ -27,7 +27,7 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { auto TEST_FILE = libc_make_test_file_path(FILENAME2); constexpr const char *FILENAME3 = "fchdir.test"; auto TEST_FILE_BASE = libc_make_test_file_path(FILENAME3); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int dir_fd = LIBC_NAMESPACE::open(TEST_DIR, O_DIRECTORY); ASSERT_GT(dir_fd, 0); @@ -47,8 +47,8 @@ TEST(LlvmLibcChdirTest, ChangeAndOpen) { TEST(LlvmLibcChdirTest, ChangeToNonExistentDir) { using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Fails; - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_EQ(LIBC_NAMESPACE::fchdir(0), -1); ASSERT_ERRNO_FAILURE(); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; } diff --git a/libc/test/src/unistd/ftruncate_test.cpp b/libc/test/src/unistd/ftruncate_test.cpp index d338ceb9ec42f6431c487ef1ccfffa435edbf619..2fe4002692a87bdc964f4c64c95ff33f8db66f29 100644 --- a/libc/test/src/unistd/ftruncate_test.cpp +++ b/libc/test/src/unistd/ftruncate_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcFtruncateTest, CreateAndTruncate) { // 2. Read it to make sure what was written is actually in the file. // 3. Truncate to 1 byte. // 4. Try to read more than 1 byte and fail. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(fd, 0); diff --git a/libc/test/src/unistd/isatty_test.cpp b/libc/test/src/unistd/isatty_test.cpp index 8f9c58f56b07582b01fc612f734ca4a1f22aa408..c20eead46c060e7fb2ddc33f1ab21cbe665ba12a 100644 --- a/libc/test/src/unistd/isatty_test.cpp +++ b/libc/test/src/unistd/isatty_test.cpp @@ -21,7 +21,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; TEST(LlvmLibcIsATTYTest, StdInOutTests) { // If stdin is connected to a terminal, assume that all of the standard i/o // fds are. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; if (LIBC_NAMESPACE::isatty(0)) { EXPECT_THAT(LIBC_NAMESPACE::isatty(0), Succeeds(1)); // stdin EXPECT_THAT(LIBC_NAMESPACE::isatty(1), Succeeds(1)); // stdout @@ -34,14 +34,14 @@ TEST(LlvmLibcIsATTYTest, StdInOutTests) { } TEST(LlvmLibcIsATTYTest, BadFdTest) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; EXPECT_THAT(LIBC_NAMESPACE::isatty(-1), Fails(EBADF, 0)); // invalid fd } TEST(LlvmLibcIsATTYTest, DevTTYTest) { constexpr const char *FILENAME = "/dev/tty"; auto TTY_FILE = libc_make_test_file_path(FILENAME); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TTY_FILE, O_RDONLY); if (fd > 0) { ASSERT_ERRNO_SUCCESS(); @@ -53,7 +53,7 @@ TEST(LlvmLibcIsATTYTest, DevTTYTest) { TEST(LlvmLibcIsATTYTest, FileTest) { constexpr const char *FILENAME = "isatty.test"; auto TEST_FILE = libc_make_test_file_path(FILENAME); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(fd, 0); diff --git a/libc/test/src/unistd/link_test.cpp b/libc/test/src/unistd/link_test.cpp index fd377dd02114c148cd73377799b0aede6d79a428..3f1af2ec63f570b7a7c224fad2efa18211300ae9 100644 --- a/libc/test/src/unistd/link_test.cpp +++ b/libc/test/src/unistd/link_test.cpp @@ -28,7 +28,7 @@ TEST(LlvmLibcLinkTest, CreateAndUnlink) { // 2. Create a link to that file. // 3. Open the link to check that the link was created. // 4. Cleanup the file and its link. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(write_fd, 0); diff --git a/libc/test/src/unistd/linkat_test.cpp b/libc/test/src/unistd/linkat_test.cpp index 50384b1ecafb0cfc0dad06b52a02af82069f96e2..c6e4575604289c6693b0c618d74343691688276f 100644 --- a/libc/test/src/unistd/linkat_test.cpp +++ b/libc/test/src/unistd/linkat_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcLinkatTest, CreateAndUnlink) { // 2. Create a link to that file. // 3. Open the link to check that the link was created. // 4. Cleanup the file and its link. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE_PATH, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/unistd/readlink_test.cpp b/libc/test/src/unistd/readlink_test.cpp index 1919938082213368aa323c45112e4b2d1624f86e..20f3951349118a04659273e16c785ce48ec301d6 100644 --- a/libc/test/src/unistd/readlink_test.cpp +++ b/libc/test/src/unistd/readlink_test.cpp @@ -22,7 +22,7 @@ TEST(LlvmLibcReadlinkTest, CreateAndUnlink) { auto LINK_VAL = libc_make_test_file_path(FILENAME); constexpr const char *FILENAME2 = "readlink.test.link"; auto LINK = libc_make_test_file_path(FILENAME2); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // The test strategy is as follows: // 1. Create a symlink with value LINK_VAL. diff --git a/libc/test/src/unistd/readlinkat_test.cpp b/libc/test/src/unistd/readlinkat_test.cpp index 03b35c5718ab5480b54a9c2ba0b4ac4669b6c6d6..39d81d9ba544a64985c889d17a55ec810b4a3146 100644 --- a/libc/test/src/unistd/readlinkat_test.cpp +++ b/libc/test/src/unistd/readlinkat_test.cpp @@ -24,7 +24,7 @@ TEST(LlvmLibcReadlinkatTest, CreateAndUnlink) { auto LINK_VAL = libc_make_test_file_path(FILENAME); constexpr const char *FILENAME2 = "readlinkat.test.link"; auto LINK = libc_make_test_file_path(FILENAME2); - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; // The test strategy is as follows: // 1. Create a symlink with value LINK_VAL. diff --git a/libc/test/src/unistd/symlink_test.cpp b/libc/test/src/unistd/symlink_test.cpp index 2be0431e473eb4cd84f287aad9192c03cc8fbe65..9e8b81c38269b2227b18824f12abd1ecc40fbc8b 100644 --- a/libc/test/src/unistd/symlink_test.cpp +++ b/libc/test/src/unistd/symlink_test.cpp @@ -30,7 +30,7 @@ TEST(LlvmLibcSymlinkTest, CreateAndUnlink) { // 2. Create a symlink to that file. // 3. Open the symlink to check that the symlink was created. // 4. Cleanup the file and its symlink. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(write_fd, 0); diff --git a/libc/test/src/unistd/symlinkat_test.cpp b/libc/test/src/unistd/symlinkat_test.cpp index 4888574b6cd4c9edfbe649c759e3cd5773294bf7..b6588a988b7974afbdcc4dd0d087dd70b76682dc 100644 --- a/libc/test/src/unistd/symlinkat_test.cpp +++ b/libc/test/src/unistd/symlinkat_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcSymlinkatTest, CreateAndUnlink) { // 2. Create a link to that file. // 3. Open the link to check that the link was created. // 4. Cleanup the file and its link. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int write_fd = LIBC_NAMESPACE::open(TEST_FILE_PATH, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/unistd/syscall_test.cpp b/libc/test/src/unistd/syscall_test.cpp index aabbffc20d1ba3680a4d5aeab165adae842c9260..cee29bd9afa308b4f36f5989b6e725712d0f1f1b 100644 --- a/libc/test/src/unistd/syscall_test.cpp +++ b/libc/test/src/unistd/syscall_test.cpp @@ -27,7 +27,7 @@ using LIBC_NAMESPACE::testing::ErrnoSetterMatcher::Succeeds; // because the macro generates a call to the actual internal function // (__llvm_libc_syscall) which is inside the namespace. TEST(LlvmLibcSyscallTest, TrivialCall) { - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; ASSERT_GE(LIBC_NAMESPACE::syscall(SYS_gettid), 0l); ASSERT_ERRNO_SUCCESS(); diff --git a/libc/test/src/unistd/truncate_test.cpp b/libc/test/src/unistd/truncate_test.cpp index a4cb9323bb865ba7c120712a3b7875a633f7445e..261dd63d2afc4cc90fd97b966819d6436451cd8a 100644 --- a/libc/test/src/unistd/truncate_test.cpp +++ b/libc/test/src/unistd/truncate_test.cpp @@ -34,7 +34,7 @@ TEST(LlvmLibcTruncateTest, CreateAndTruncate) { // 2. Read it to make sure what was written is actually in the file. // 3. Truncate to 1 byte. // 4. Try to read more than 1 byte and fail. - libc_errno = 0; + LIBC_NAMESPACE::libc_errno = 0; int fd = LIBC_NAMESPACE::open(TEST_FILE, O_WRONLY | O_CREAT, S_IRWXU); ASSERT_ERRNO_SUCCESS(); ASSERT_GT(fd, 0); diff --git a/libcxx/include/__config b/libcxx/include/__config index d356960e9e62b4b6f21bdae902f7faadf887fd51..0797880cb2f5da7e64fb11fd33b71a24dae3c937 100644 --- a/libcxx/include/__config +++ b/libcxx/include/__config @@ -325,6 +325,12 @@ // clang-format on # ifndef _LIBCPP_HARDENING_MODE + +# ifndef _LIBCPP_HARDENING_MODE_DEFAULT +# error _LIBCPP_HARDENING_MODE_DEFAULT is not defined. This definition should be set at configuration time in the \ +`__config_site` header, please make sure your installation of libc++ is not broken. +# endif + # define _LIBCPP_HARDENING_MODE _LIBCPP_HARDENING_MODE_DEFAULT # endif diff --git a/libcxx/include/__memory/uninitialized_algorithms.h b/libcxx/include/__memory/uninitialized_algorithms.h index 9733bb748f665d15073aa1bc230d403a08f0c09d..7e25a5c5fa19bba7b8eaa1a6c1ea8379f3eb022f 100644 --- a/libcxx/include/__memory/uninitialized_algorithms.h +++ b/libcxx/include/__memory/uninitialized_algorithms.h @@ -643,7 +643,7 @@ __uninitialized_allocator_relocate(_Alloc& __alloc, _Tp* __first, _Tp* __last, _ __guard.__complete(); std::__allocator_destroy(__alloc, __first, __last); } else { - __builtin_memcpy(__result, __first, sizeof(_Tp) * (__last - __first)); + __builtin_memcpy(const_cast<__remove_const_t<_Tp>*>(__result), __first, sizeof(_Tp) * (__last - __first)); } } diff --git a/libcxx/test/libcxx/containers/sequences/deque/abi.compile.pass.cpp b/libcxx/test/libcxx/containers/sequences/deque/abi.compile.pass.cpp index 37e87d59503eea87ea9805631f3bbbc1e364e7db..9910befb0349e78e72d81d4ff20a135f72d4a145 100644 --- a/libcxx/test/libcxx/containers/sequences/deque/abi.compile.pass.cpp +++ b/libcxx/test/libcxx/containers/sequences/deque/abi.compile.pass.cpp @@ -22,7 +22,7 @@ class small_iter_allocator { public: using value_type = T; using pointer = small_pointer; - using size_type = std::int16_t; + using size_type = std::uint16_t; using difference_type = std::int16_t; small_iter_allocator() TEST_NOEXCEPT {} @@ -37,27 +37,51 @@ public: friend bool operator!=(small_iter_allocator, small_iter_allocator) { return false; } }; +template +class final_small_iter_allocator final { +public: + using value_type = T; + using pointer = small_pointer; + using size_type = std::uint16_t; + using difference_type = std::int16_t; + + final_small_iter_allocator() TEST_NOEXCEPT {} + + template + final_small_iter_allocator(final_small_iter_allocator) TEST_NOEXCEPT {} + + T* allocate(std::size_t n); + void deallocate(T* p, std::size_t); + + friend bool operator==(final_small_iter_allocator, final_small_iter_allocator) { return true; } + friend bool operator!=(final_small_iter_allocator, final_small_iter_allocator) { return false; } +}; + #if __SIZE_WIDTH__ == 64 static_assert(sizeof(std::deque) == 48, ""); static_assert(sizeof(std::deque >) == 48, ""); static_assert(sizeof(std::deque >) == 80, ""); static_assert(sizeof(std::deque >) == 12, ""); +static_assert(sizeof(std::deque >) == 16, ""); static_assert(sizeof(std::deque) == 48, ""); static_assert(sizeof(std::deque >) == 48, ""); static_assert(sizeof(std::deque >) == 80, ""); static_assert(sizeof(std::deque >) == 12, ""); +static_assert(sizeof(std::deque >) == 16, ""); static_assert(TEST_ALIGNOF(std::deque) == 8, ""); static_assert(TEST_ALIGNOF(std::deque >) == 8, ""); static_assert(TEST_ALIGNOF(std::deque >) == 8, ""); static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); +static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); static_assert(TEST_ALIGNOF(std::deque) == 8, ""); static_assert(TEST_ALIGNOF(std::deque >) == 8, ""); static_assert(TEST_ALIGNOF(std::deque >) == 8, ""); static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); +static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); #elif __SIZE_WIDTH__ == 32 @@ -65,21 +89,25 @@ static_assert(sizeof(std::deque) == 24, ""); static_assert(sizeof(std::deque >) == 24, ""); static_assert(sizeof(std::deque >) == 48, ""); static_assert(sizeof(std::deque >) == 12, ""); +static_assert(sizeof(std::deque >) == 16, ""); static_assert(sizeof(std::deque) == 24, ""); static_assert(sizeof(std::deque >) == 24, ""); static_assert(sizeof(std::deque >) == 48, ""); static_assert(sizeof(std::deque >) == 12, ""); +static_assert(sizeof(std::deque >) == 16, ""); static_assert(TEST_ALIGNOF(std::deque) == 4, ""); static_assert(TEST_ALIGNOF(std::deque >) == 4, ""); static_assert(TEST_ALIGNOF(std::deque >) == 4, ""); static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); +static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); static_assert(TEST_ALIGNOF(std::deque) == 4, ""); static_assert(TEST_ALIGNOF(std::deque >) == 4, ""); static_assert(TEST_ALIGNOF(std::deque >) == 4, ""); static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); +static_assert(TEST_ALIGNOF(std::deque >) == 2, ""); #else # error std::size_t has an unexpected size diff --git a/libcxx/test/libcxx/containers/sequences/list/abi.compile.pass.cpp b/libcxx/test/libcxx/containers/sequences/list/abi.compile.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ace45d661df6e367a2e072e6ef4969625d1e5c8 --- /dev/null +++ b/libcxx/test/libcxx/containers/sequences/list/abi.compile.pass.cpp @@ -0,0 +1,86 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "min_allocator.h" +#include "test_allocator.h" +#include "test_macros.h" + +template +class small_pointer { + std::uint16_t offset; +}; + +template +class small_iter_allocator { +public: + using value_type = T; + using pointer = small_pointer; + using size_type = std::int16_t; + using difference_type = std::int16_t; + + small_iter_allocator() TEST_NOEXCEPT {} + + template + small_iter_allocator(small_iter_allocator) TEST_NOEXCEPT {} + + T* allocate(std::size_t n); + void deallocate(T* p, std::size_t); + + friend bool operator==(small_iter_allocator, small_iter_allocator) { return true; } + friend bool operator!=(small_iter_allocator, small_iter_allocator) { return false; } +}; + +#if __SIZE_WIDTH__ == 64 + +static_assert(sizeof(std::list) == 24, ""); +static_assert(sizeof(std::list >) == 24, ""); +static_assert(sizeof(std::list >) == 40, ""); +static_assert(sizeof(std::list >) == 6, ""); + +static_assert(sizeof(std::list) == 24, ""); +static_assert(sizeof(std::list >) == 24, ""); +static_assert(sizeof(std::list >) == 40, ""); +static_assert(sizeof(std::list >) == 6, ""); + +static_assert(TEST_ALIGNOF(std::list) == 8, ""); +static_assert(TEST_ALIGNOF(std::list >) == 8, ""); +static_assert(TEST_ALIGNOF(std::list >) == 8, ""); +static_assert(TEST_ALIGNOF(std::list >) == 2, ""); + +static_assert(TEST_ALIGNOF(std::list) == 8, ""); +static_assert(TEST_ALIGNOF(std::list >) == 8, ""); +static_assert(TEST_ALIGNOF(std::list >) == 8, ""); +static_assert(TEST_ALIGNOF(std::list >) == 2, ""); + +#elif __SIZE_WIDTH__ == 32 + +static_assert(sizeof(std::list) == 12, ""); +static_assert(sizeof(std::list >) == 12, ""); +static_assert(sizeof(std::list >) == 24, ""); +static_assert(sizeof(std::list >) == 6, ""); + +static_assert(sizeof(std::list) == 12, ""); +static_assert(sizeof(std::list >) == 12, ""); +static_assert(sizeof(std::list >) == 24, ""); +static_assert(sizeof(std::list >) == 6, ""); + +static_assert(TEST_ALIGNOF(std::list) == 4, ""); +static_assert(TEST_ALIGNOF(std::list >) == 4, ""); +static_assert(TEST_ALIGNOF(std::list >) == 4, ""); +static_assert(TEST_ALIGNOF(std::list >) == 2, ""); + +static_assert(TEST_ALIGNOF(std::list) == 4, ""); +static_assert(TEST_ALIGNOF(std::list >) == 4, ""); +static_assert(TEST_ALIGNOF(std::list >) == 4, ""); +static_assert(TEST_ALIGNOF(std::list >) == 2, ""); + +#else +# error std::size_t has an unexpected size +#endif diff --git a/libcxx/test/libcxx/containers/sequences/vector.bool/abi.compile.pass.cpp b/libcxx/test/libcxx/containers/sequences/vector.bool/abi.compile.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48337a0c5cc1b70510d35174c7f4fc6a95b2b311 --- /dev/null +++ b/libcxx/test/libcxx/containers/sequences/vector.bool/abi.compile.pass.cpp @@ -0,0 +1,66 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "min_allocator.h" +#include "test_allocator.h" +#include "test_macros.h" + +template +class small_pointer { + std::uint16_t offset; +}; + +template +class small_iter_allocator { +public: + using value_type = T; + using pointer = small_pointer; + using size_type = std::int16_t; + using difference_type = std::int16_t; + + small_iter_allocator() TEST_NOEXCEPT {} + + template + small_iter_allocator(small_iter_allocator) TEST_NOEXCEPT {} + + T* allocate(std::size_t n); + void deallocate(T* p, std::size_t); + + friend bool operator==(small_iter_allocator, small_iter_allocator) { return true; } + friend bool operator!=(small_iter_allocator, small_iter_allocator) { return false; } +}; + +#if __SIZE_WIDTH__ == 64 + +static_assert(sizeof(std::vector) == 24, ""); +static_assert(sizeof(std::vector >) == 24, ""); +static_assert(sizeof(std::vector >) == 40, ""); +static_assert(sizeof(std::vector >) == 6, ""); + +static_assert(TEST_ALIGNOF(std::vector) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 2, ""); + +#elif __SIZE_WIDTH__ == 32 + +static_assert(sizeof(std::vector) == 12, ""); +static_assert(sizeof(std::vector >) == 12, ""); +static_assert(sizeof(std::vector >) == 24, ""); +static_assert(sizeof(std::vector >) == 6, ""); + +static_assert(TEST_ALIGNOF(std::vector) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 2, ""); + +#else +# error std::size_t has an unexpected size +#endif diff --git a/libcxx/test/libcxx/containers/sequences/vector/abi.compile.pass.cpp b/libcxx/test/libcxx/containers/sequences/vector/abi.compile.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..b03f48434a0e0ec9499e4777a4ff6cdd489e49f5 --- /dev/null +++ b/libcxx/test/libcxx/containers/sequences/vector/abi.compile.pass.cpp @@ -0,0 +1,86 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include + +#include "min_allocator.h" +#include "test_allocator.h" +#include "test_macros.h" + +template +class small_pointer { + std::uint16_t offset; +}; + +template +class small_iter_allocator { +public: + using value_type = T; + using pointer = small_pointer; + using size_type = std::int16_t; + using difference_type = std::int16_t; + + small_iter_allocator() TEST_NOEXCEPT {} + + template + small_iter_allocator(small_iter_allocator) TEST_NOEXCEPT {} + + T* allocate(std::size_t n); + void deallocate(T* p, std::size_t); + + friend bool operator==(small_iter_allocator, small_iter_allocator) { return true; } + friend bool operator!=(small_iter_allocator, small_iter_allocator) { return false; } +}; + +#if __SIZE_WIDTH__ == 64 + +static_assert(sizeof(std::vector) == 24, ""); +static_assert(sizeof(std::vector >) == 24, ""); +static_assert(sizeof(std::vector >) == 40, ""); +static_assert(sizeof(std::vector >) == 6, ""); + +static_assert(sizeof(std::vector) == 24, ""); +static_assert(sizeof(std::vector >) == 24, ""); +static_assert(sizeof(std::vector >) == 40, ""); +static_assert(sizeof(std::vector >) == 6, ""); + +static_assert(TEST_ALIGNOF(std::vector) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 2, ""); + +static_assert(TEST_ALIGNOF(std::vector) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 8, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 2, ""); + +#elif __SIZE_WIDTH__ == 32 + +static_assert(sizeof(std::vector) == 12, ""); +static_assert(sizeof(std::vector >) == 12, ""); +static_assert(sizeof(std::vector >) == 24, ""); +static_assert(sizeof(std::vector >) == 6, ""); + +static_assert(sizeof(std::vector) == 12, ""); +static_assert(sizeof(std::vector >) == 12, ""); +static_assert(sizeof(std::vector >) == 24, ""); +static_assert(sizeof(std::vector >) == 6, ""); + +static_assert(TEST_ALIGNOF(std::vector) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 2, ""); + +static_assert(TEST_ALIGNOF(std::vector) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 4, ""); +static_assert(TEST_ALIGNOF(std::vector >) == 2, ""); + +#else +# error std::size_t has an unexpected size +#endif diff --git a/libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp b/libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp new file mode 100644 index 0000000000000000000000000000000000000000..62fff96ac5abe3b7ff87cd42aaea653752e273ef --- /dev/null +++ b/libcxx/test/libcxx/containers/sequences/vector/const_T.compile.pass.cpp @@ -0,0 +1,18 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// Make sure that `vector` works + +#include + +void test() { + std::vector v; + v.emplace_back(1); + v.push_back(1); + v.resize(3); +} diff --git a/libunwind/CMakeLists.txt b/libunwind/CMakeLists.txt index bb1b052f61d8752ae2eaeae08538d1e3b26a2291..806d5a783ec39c383ebabbdfa1e57a5248176554 100644 --- a/libunwind/CMakeLists.txt +++ b/libunwind/CMakeLists.txt @@ -21,6 +21,7 @@ set(LIBUNWIND_LIBCXX_PATH "${CMAKE_CURRENT_LIST_DIR}/../libcxx" CACHE PATH "Specify path to libc++ source.") include(GNUInstallDirs) +include(CheckSymbolExists) #=============================================================================== # Setup CMake Options @@ -96,6 +97,20 @@ endif() option(LIBUNWIND_HIDE_SYMBOLS "Do not export any symbols from the static library." ${LIBUNWIND_DEFAULT_HIDE_SYMBOLS}) +# If toolchain is FPXX, we switch to FP64 to save the full FPRs. See: +# https://web.archive.org/web/20180828210612/https://dmz-portal.mips.com/wiki/MIPS_O32_ABI_-_FR0_and_FR1_Interlinking +check_symbol_exists(__mips_hard_float "" __MIPSHF) +check_symbol_exists(_ABIO32 "" __MIPS_O32) +if (__MIPSHF AND __MIPS_O32) + file(WRITE ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c + "#if __mips_fpr != 0\n" + "# error\n" + "#endif\n") + try_compile(MIPS_FPABI_FPXX ${CMAKE_BINARY_DIR} + ${CMAKE_BINARY_DIR}${CMAKE_FILES_DIRECTORY}/CMakeTmp/mips_is_fpxx.c + CMAKE_FLAGS -DCMAKE_C_LINK_EXECUTABLE='echo') +endif() + #=============================================================================== # Configure System #=============================================================================== @@ -179,6 +194,10 @@ if (WIN32) add_compile_flags_if_supported(-Wno-dll-attribute-on-redeclaration) endif() +if (MIPS_FPABI_FPXX) + add_compile_flags(-mfp64) +endif() + # Get feature flags. # Exceptions # Catches C++ exceptions only and tells the compiler to assume that extern C diff --git a/lld/ELF/Arch/LoongArch.cpp b/lld/ELF/Arch/LoongArch.cpp index ab2ec5b447d00047ef543c316e52334eaf87f9da..3e9d6e0e7420083bcc6585bb1530ad483d86bf1d 100644 --- a/lld/ELF/Arch/LoongArch.cpp +++ b/lld/ELF/Arch/LoongArch.cpp @@ -36,6 +36,8 @@ public: bool usesOnlyLowPageBits(RelType type) const override; void relocate(uint8_t *loc, const Relocation &rel, uint64_t val) const override; + bool relaxOnce(int pass) const override; + void finalizeRelax(int passes) const override; }; } // end anonymous namespace @@ -465,8 +467,9 @@ RelExpr LoongArch::getRelExpr(const RelType type, const Symbol &s, case R_LARCH_TLS_GD_HI20: return R_TLSGD_GOT; case R_LARCH_RELAX: - // LoongArch linker relaxation is not implemented yet. - return R_NONE; + return config->relax ? R_RELAX_HINT : R_NONE; + case R_LARCH_ALIGN: + return R_RELAX_HINT; // Other known relocs that are explicitly unimplemented: // @@ -659,6 +662,155 @@ void LoongArch::relocate(uint8_t *loc, const Relocation &rel, } } +static bool relax(InputSection &sec) { + const uint64_t secAddr = sec.getVA(); + const MutableArrayRef relocs = sec.relocs(); + auto &aux = *sec.relaxAux; + bool changed = false; + ArrayRef sa = ArrayRef(aux.anchors); + uint64_t delta = 0; + + std::fill_n(aux.relocTypes.get(), relocs.size(), R_LARCH_NONE); + aux.writes.clear(); + for (auto [i, r] : llvm::enumerate(relocs)) { + const uint64_t loc = secAddr + r.offset - delta; + uint32_t &cur = aux.relocDeltas[i], remove = 0; + switch (r.type) { + case R_LARCH_ALIGN: { + const uint64_t addend = + r.sym->isUndefined() ? Log2_64(r.addend) + 1 : r.addend; + const uint64_t allBytes = (1ULL << (addend & 0xff)) - 4; + const uint64_t align = 1ULL << (addend & 0xff); + const uint64_t maxBytes = addend >> 8; + const uint64_t off = loc & (align - 1); + const uint64_t curBytes = off == 0 ? 0 : align - off; + // All bytes beyond the alignment boundary should be removed. + // If emit bytes more than max bytes to emit, remove all. + if (maxBytes != 0 && curBytes > maxBytes) + remove = allBytes; + else + remove = allBytes - curBytes; + // If we can't satisfy this alignment, we've found a bad input. + if (LLVM_UNLIKELY(static_cast(remove) < 0)) { + errorOrWarn(getErrorLocation((const uint8_t *)loc) + + "insufficient padding bytes for " + lld::toString(r.type) + + ": " + Twine(allBytes) + " bytes available for " + + "requested alignment of " + Twine(align) + " bytes"); + remove = 0; + } + break; + } + } + + // For all anchors whose offsets are <= r.offset, they are preceded by + // the previous relocation whose `relocDeltas` value equals `delta`. + // Decrease their st_value and update their st_size. + for (; sa.size() && sa[0].offset <= r.offset; sa = sa.slice(1)) { + if (sa[0].end) + sa[0].d->size = sa[0].offset - delta - sa[0].d->value; + else + sa[0].d->value = sa[0].offset - delta; + } + delta += remove; + if (delta != cur) { + cur = delta; + changed = true; + } + } + + for (const SymbolAnchor &a : sa) { + if (a.end) + a.d->size = a.offset - delta - a.d->value; + else + a.d->value = a.offset - delta; + } + // Inform assignAddresses that the size has changed. + if (!isUInt<32>(delta)) + fatal("section size decrease is too large: " + Twine(delta)); + sec.bytesDropped = delta; + return changed; +} + +// When relaxing just R_LARCH_ALIGN, relocDeltas is usually changed only once in +// the absence of a linker script. For call and load/store R_LARCH_RELAX, code +// shrinkage may reduce displacement and make more relocations eligible for +// relaxation. Code shrinkage may increase displacement to a call/load/store +// target at a higher fixed address, invalidating an earlier relaxation. Any +// change in section sizes can have cascading effect and require another +// relaxation pass. +bool LoongArch::relaxOnce(int pass) const { + if (config->relocatable) + return false; + + if (pass == 0) + initSymbolAnchors(); + + SmallVector storage; + bool changed = false; + for (OutputSection *osec : outputSections) { + if (!(osec->flags & SHF_EXECINSTR)) + continue; + for (InputSection *sec : getInputSections(*osec, storage)) + changed |= relax(*sec); + } + return changed; +} + +void LoongArch::finalizeRelax(int passes) const { + log("relaxation passes: " + Twine(passes)); + SmallVector storage; + for (OutputSection *osec : outputSections) { + if (!(osec->flags & SHF_EXECINSTR)) + continue; + for (InputSection *sec : getInputSections(*osec, storage)) { + RelaxAux &aux = *sec->relaxAux; + if (!aux.relocDeltas) + continue; + + MutableArrayRef rels = sec->relocs(); + ArrayRef old = sec->content(); + size_t newSize = old.size() - aux.relocDeltas[rels.size() - 1]; + uint8_t *p = context().bAlloc.Allocate(newSize); + uint64_t offset = 0; + int64_t delta = 0; + sec->content_ = p; + sec->size = newSize; + sec->bytesDropped = 0; + + // Update section content: remove NOPs for R_LARCH_ALIGN and rewrite + // instructions for relaxed relocations. + for (size_t i = 0, e = rels.size(); i != e; ++i) { + uint32_t remove = aux.relocDeltas[i] - delta; + delta = aux.relocDeltas[i]; + if (remove == 0 && aux.relocTypes[i] == R_LARCH_NONE) + continue; + + // Copy from last location to the current relocated location. + const Relocation &r = rels[i]; + uint64_t size = r.offset - offset; + memcpy(p, old.data() + offset, size); + p += size; + offset = r.offset + remove; + } + memcpy(p, old.data() + offset, old.size() - offset); + + // Subtract the previous relocDeltas value from the relocation offset. + // For a pair of R_LARCH_XXX/R_LARCH_RELAX with the same offset, decrease + // their r_offset by the same delta. + delta = 0; + for (size_t i = 0, e = rels.size(); i != e;) { + uint64_t cur = rels[i].offset; + do { + rels[i].offset -= delta; + if (aux.relocTypes[i] != R_LARCH_NONE) + rels[i].type = aux.relocTypes[i]; + } while (++i != e && rels[i].offset == cur); + delta = aux.relocDeltas[i - 1]; + } + } + } +} + TargetInfo *elf::getLoongArchTargetInfo() { static LoongArch target; return ⌖ diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 8ce92b4badfbd7e1b63f8603e395e4f04470eecb..5fcab4d39d43a86f2b22891c31d4771882913cee 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -45,6 +45,7 @@ public: uint64_t val) const override; void relocateAlloc(InputSectionBase &sec, uint8_t *buf) const override; bool relaxOnce(int pass) const override; + void finalizeRelax(int passes) const override; }; } // end anonymous namespace @@ -104,26 +105,6 @@ static uint32_t setLO12_S(uint32_t insn, uint32_t imm) { (extractBits(imm, 4, 0) << 7); } -namespace { -struct SymbolAnchor { - uint64_t offset; - Defined *d; - bool end; // true for the anchor of st_value+st_size -}; -} // namespace - -struct elf::RISCVRelaxAux { - // This records symbol start and end offsets which will be adjusted according - // to the nearest relocDeltas element. - SmallVector anchors; - // For relocations[i], the actual offset is - // r_offset - (i ? relocDeltas[i-1] : 0). - std::unique_ptr relocDeltas; - // For relocations[i], the actual type is relocTypes[i]. - std::unique_ptr relocTypes; - SmallVector writes; -}; - RISCV::RISCV() { copyRel = R_RISCV_COPY; pltRel = R_RISCV_JUMP_SLOT; @@ -695,13 +676,13 @@ void RISCV::relocateAlloc(InputSectionBase &sec, uint8_t *buf) const { } } -static void initSymbolAnchors() { +void elf::initSymbolAnchors() { SmallVector storage; for (OutputSection *osec : outputSections) { if (!(osec->flags & SHF_EXECINSTR)) continue; for (InputSection *sec : getInputSections(*osec, storage)) { - sec->relaxAux = make(); + sec->relaxAux = make(); if (sec->relocs().size()) { sec->relaxAux->relocDeltas = std::make_unique(sec->relocs().size()); @@ -948,7 +929,7 @@ bool RISCV::relaxOnce(int pass) const { return changed; } -void elf::riscvFinalizeRelax(int passes) { +void RISCV::finalizeRelax(int passes) const { llvm::TimeTraceScope timeScope("Finalize RISC-V relaxation"); log("relaxation passes: " + Twine(passes)); SmallVector storage; @@ -956,7 +937,7 @@ void elf::riscvFinalizeRelax(int passes) { if (!(osec->flags & SHF_EXECINSTR)) continue; for (InputSection *sec : getInputSections(*osec, storage)) { - RISCVRelaxAux &aux = *sec->relaxAux; + RelaxAux &aux = *sec->relaxAux; if (!aux.relocDeltas) continue; diff --git a/lld/ELF/InputSection.cpp b/lld/ELF/InputSection.cpp index 0e0b9783bd88a0fccf98f7c52076d8139ef26278..3d726b4c4b777d3b5b9d9a4683e4f079dea5f7ae 100644 --- a/lld/ELF/InputSection.cpp +++ b/lld/ELF/InputSection.cpp @@ -354,9 +354,10 @@ InputSectionBase *InputSection::getRelocatedSection() const { template void InputSection::copyRelocations(uint8_t *buf) { - if (config->relax && !config->relocatable && config->emachine == EM_RISCV) { - // On RISC-V, relaxation might change relocations: copy from internal ones - // that are updated by relaxation. + if (config->relax && !config->relocatable && + (config->emachine == EM_RISCV || config->emachine == EM_LOONGARCH)) { + // On LoongArch and RISC-V, relaxation might change relocations: copy + // from internal ones that are updated by relaxation. InputSectionBase *sec = getRelocatedSection(); copyRelocations(buf, llvm::make_range(sec->relocations.begin(), sec->relocations.end())); diff --git a/lld/ELF/InputSection.h b/lld/ELF/InputSection.h index bb9dff38ae02995af0a6eb69d5a5d1312bcce7ec..b8af962877b4e92e71503691b1db57f3373729ba 100644 --- a/lld/ELF/InputSection.h +++ b/lld/ELF/InputSection.h @@ -102,7 +102,23 @@ protected: link(link), info(info) {} }; -struct RISCVRelaxAux; +struct SymbolAnchor { + uint64_t offset; + Defined *d; + bool end; // true for the anchor of st_value+st_size +}; + +struct RelaxAux { + // This records symbol start and end offsets which will be adjusted according + // to the nearest relocDeltas element. + SmallVector anchors; + // For relocations[i], the actual offset is + // r_offset - (i ? relocDeltas[i-1] : 0). + std::unique_ptr relocDeltas; + // For relocations[i], the actual type is relocTypes[i]. + std::unique_ptr relocTypes; + SmallVector writes; +}; // This corresponds to a section of an input file. class InputSectionBase : public SectionBase { @@ -227,9 +243,9 @@ public: // basic blocks. JumpInstrMod *jumpInstrMod = nullptr; - // Auxiliary information for RISC-V linker relaxation. RISC-V does not use - // jumpInstrMod. - RISCVRelaxAux *relaxAux; + // Auxiliary information for RISC-V and LoongArch linker relaxation. + // They do not use jumpInstrMod. + RelaxAux *relaxAux; // The compressed content size when `compressed` is true. size_t compressedSize; diff --git a/lld/ELF/Target.h b/lld/ELF/Target.h index ab6b6b9c013ba3ff55042deab6e90b41c61b628e..ed00e81c0e6c81b0dc08b95b5bfb9eb99f6eb7ad 100644 --- a/lld/ELF/Target.h +++ b/lld/ELF/Target.h @@ -95,6 +95,8 @@ public: // Do a linker relaxation pass and return true if we changed something. virtual bool relaxOnce(int pass) const { return false; } + // Do finalize relaxation after collecting relaxation infos. + virtual void finalizeRelax(int passes) const {} virtual void applyJumpInstrMod(uint8_t *loc, JumpModType type, JumpModType val) const {} @@ -236,6 +238,7 @@ void addArmSyntheticSectionMappingSymbol(Defined *); void sortArmMappingSymbols(); void convertArmInstructionstoBE8(InputSection *sec, uint8_t *buf); void createTaggedSymbols(const SmallVector &files); +void initSymbolAnchors(); LLVM_LIBRARY_VISIBILITY extern const TargetInfo *target; TargetInfo *getTarget(); diff --git a/lld/ELF/Writer.cpp b/lld/ELF/Writer.cpp index 501c10f358497b5e1b67230acdec1dcb73ee8a43..6df43a34be013a7ea0c17a705e9503b0963af5e3 100644 --- a/lld/ELF/Writer.cpp +++ b/lld/ELF/Writer.cpp @@ -1752,8 +1752,8 @@ template void Writer::finalizeAddressDependentContent() { } } } - if (!config->relocatable && config->emachine == EM_RISCV) - riscvFinalizeRelax(pass); + if (!config->relocatable) + target->finalizeRelax(pass); if (config->relocatable) for (OutputSection *sec : outputSections) diff --git a/lld/test/COFF/def-export-cpp.s b/lld/test/COFF/def-export-cpp.s index e00b35b1c5b39bb8d32ed1b80b74e15473b3196b..370b8ddba4104b4ded7a92e728c4d652156716eb 100644 --- a/lld/test/COFF/def-export-cpp.s +++ b/lld/test/COFF/def-export-cpp.s @@ -10,6 +10,7 @@ # IMPLIB: File: foo.dll # IMPLIB: Name type: undecorate +# IMPLIB-NEXT: Export name: GetPathOnDisk # IMPLIB-NEXT: Symbol: __imp_?GetPathOnDisk@@YA_NPEA_W@Z # IMPLIB-NEXT: Symbol: ?GetPathOnDisk@@YA_NPEA_W@Z diff --git a/lld/test/COFF/def-export-stdcall.s b/lld/test/COFF/def-export-stdcall.s index f015e205c74a33ddeab796578e88fdd5b2c906f9..7e4e04c77cbe7a56147efa149f82f7b9ce0b793f 100644 --- a/lld/test/COFF/def-export-stdcall.s +++ b/lld/test/COFF/def-export-stdcall.s @@ -6,15 +6,19 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix UNDECORATED-EXPORTS %s # UNDECORATED-IMPLIB: Name type: noprefix +# UNDECORATED-IMPLIB-NEXT: Export name: _underscored # UNDECORATED-IMPLIB-NEXT: __imp___underscored # UNDECORATED-IMPLIB-NEXT: __underscored # UNDECORATED-IMPLIB: Name type: undecorate +# UNDECORATED-IMPLIB-NEXT: Export name: fastcall # UNDECORATED-IMPLIB-NEXT: __imp_@fastcall@8 # UNDECORATED-IMPLIB-NEXT: fastcall@8 # UNDECORATED-IMPLIB: Name type: undecorate +# UNDECORATED-IMPLIB-NEXT: Export name: stdcall # UNDECORATED-IMPLIB-NEXT: __imp__stdcall@8 # UNDECORATED-IMPLIB-NEXT: _stdcall@8 # UNDECORATED-IMPLIB: Name type: undecorate +# UNDECORATED-IMPLIB-NEXT: Export name: vectorcall # UNDECORATED-IMPLIB-NEXT: __imp_vectorcall@@8 # UNDECORATED-IMPLIB-NEXT: vectorcall@@8 @@ -30,12 +34,15 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix DECORATED-EXPORTS %s # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8 # DECORATED-IMPLIB-NEXT: @fastcall@8 # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-IMPLIB-NEXT: _stdcall@8 # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8 # DECORATED-IMPLIB-NEXT: vectorcall@@8 @@ -51,14 +58,17 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix DECORATED-MINGW-EXPORTS %s # DECORATED-MINGW-IMPLIB: Name type: name +# DECORATED-MINGW-IMPLIB-NEXT: Export name: @fastcall@8 # DECORATED-MINGW-IMPLIB-NEXT: __imp_@fastcall@8 # DECORATED-MINGW-IMPLIB-NEXT: fastcall@8 # DECORATED-MINGW-IMPLIB: Name type: noprefix +# DECORATED-MINGW-IMPLIB-NEXT: Export name: stdcall@8 # DECORATED-MINGW-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-MINGW-IMPLIB-NEXT: _stdcall@8 # GNU tools don't support vectorcall, but this test is just to track that # lld's behaviour remains consistent over time. # DECORATED-MINGW-IMPLIB: Name type: name +# DECORATED-MINGW-IMPLIB-NEXT: Export name: vectorcall@@8 # DECORATED-MINGW-IMPLIB-NEXT: __imp_vectorcall@@8 # DECORATED-MINGW-IMPLIB-NEXT: vectorcall@@8 @@ -75,14 +85,17 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix MINGW-KILL-AT-EXPORTS %s # MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB: Export name: fastcall # MINGW-KILL-AT-IMPLIB: __imp__fastcall # MINGW-KILL-AT-IMPLIB-NEXT: _fastcall # MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB-NEXT: Export name: stdcall # MINGW-KILL-AT-IMPLIB-NEXT: __imp__stdcall # MINGW-KILL-AT-IMPLIB-NEXT: _stdcall # GNU tools don't support vectorcall, but this test is just to track that # lld's behaviour remains consistent over time. # MINGW-KILL-AT-IMPLIB: Name type: noprefix +# MINGW-KILL-AT-IMPLIB-NEXT: Export name: vectorcall # MINGW-KILL-AT-IMPLIB-NEXT: __imp__vectorcall # MINGW-KILL-AT-IMPLIB-NEXT: _vectorcall diff --git a/lld/test/COFF/dllexport.s b/lld/test/COFF/dllexport.s index a238b70ce1b4f698def930ca91083da619c99b7d..b04ebc3a33c3e2d1fbc40db0f8a5d946722b4b38 100644 --- a/lld/test/COFF/dllexport.s +++ b/lld/test/COFF/dllexport.s @@ -6,15 +6,19 @@ # RUN: llvm-readobj --coff-exports %t.dll | FileCheck -check-prefix DECORATED-EXPORTS %s # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: @fastcall@8 # DECORATED-IMPLIB-NEXT: __imp_@fastcall@8 # DECORATED-IMPLIB-NEXT: @fastcall@8 # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: _stdcall@8 # DECORATED-IMPLIB-NEXT: __imp__stdcall@8 # DECORATED-IMPLIB-NEXT: _stdcall@8 # DECORATED-IMPLIB: Name type: noprefix +# DECORATED-IMPLIB-NEXT: Export name: _underscored # DECORATED-IMPLIB-NEXT: __imp___underscored # DECORATED-IMPLIB-NEXT: __underscored # DECORATED-IMPLIB: Name type: name +# DECORATED-IMPLIB-NEXT: Export name: vectorcall@@8 # DECORATED-IMPLIB-NEXT: __imp_vectorcall@@8 # DECORATED-IMPLIB-NEXT: vectorcall@@8 diff --git a/lld/test/ELF/loongarch-relax-align.s b/lld/test/ELF/loongarch-relax-align.s new file mode 100644 index 0000000000000000000000000000000000000000..ab61e15d5caca28ef83e42c2ff7efd444e8608fb --- /dev/null +++ b/lld/test/ELF/loongarch-relax-align.s @@ -0,0 +1,126 @@ +# REQUIRES: loongarch + +# RUN: llvm-mc --filetype=obj --triple=loongarch32 --mattr=+relax %s -o %t.32.o +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.64.o +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.32.o -o %t.32 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.64.o -o %t.64 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.32.o --no-relax -o %t.32n +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.64.o --no-relax -o %t.64n +# RUN: llvm-objdump -td --no-show-raw-insn %t.32 | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.64 | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.32n | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.64n | FileCheck %s + +## Test the R_LARCH_ALIGN without symbol index. +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.o64.o --defsym=old=1 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.o64.o -o %t.o64 +# RUN: ld.lld --section-start=.text=0x10000 --section-start=.text2=0x20000 -e 0 %t.o64.o --no-relax -o %t.o64n +# RUN: llvm-objdump -td --no-show-raw-insn %t.o64 | FileCheck %s +# RUN: llvm-objdump -td --no-show-raw-insn %t.o64n | FileCheck %s + +## -r keeps section contents unchanged. +# RUN: ld.lld -r %t.64.o -o %t.64.r +# RUN: llvm-objdump -dr --no-show-raw-insn %t.64.r | FileCheck %s --check-prefix=CHECKR + +# CHECK-DAG: {{0*}}10000 l .text {{0*}}44 .Ltext_start +# CHECK-DAG: {{0*}}10038 l .text {{0*}}0c .L1 +# CHECK-DAG: {{0*}}10040 l .text {{0*}}04 .L2 +# CHECK-DAG: {{0*}}20000 l .text2 {{0*}}14 .Ltext2_start + +# CHECK: <.Ltext_start>: +# CHECK-NEXT: break 1 +# CHECK-NEXT: break 2 +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: break 3 +# CHECK-NEXT: break 4 +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 0 +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 56 +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 64 +# CHECK-EMPTY: +# CHECK-NEXT: <.L1>: +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-EMPTY: +# CHECK-NEXT: <.L2>: +# CHECK-NEXT: break 5 + +# CHECK: <.Ltext2_start>: +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 0 +# CHECK-NEXT: nop +# CHECK-NEXT: nop +# CHECK-NEXT: break 6 + +# CHECKR: <.Ltext2_start>: +# CHECKR-NEXT: pcalau12i $a0, 0 +# CHECKR-NEXT: {{0*}}00: R_LARCH_PCALA_HI20 .Ltext2_start +# CHECKR-NEXT: {{0*}}00: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: addi.d $a0, $a0, 0 +# CHECKR-NEXT: {{0*}}04: R_LARCH_PCALA_LO12 .Ltext2_start +# CHECKR-NEXT: {{0*}}04: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: nop +# CHECKR-NEXT: {{0*}}08: R_LARCH_ALIGN .Lalign_symbol+0x4 +# CHECKR-NEXT: nop +# CHECKR-NEXT: nop +# CHECKR-NEXT: break 6 + +.macro .fake_p2align_4 max=0 + .ifdef old + .if \max==0 + .reloc ., R_LARCH_ALIGN, 0xc + nop; nop; nop + .endif + .else + .reloc ., R_LARCH_ALIGN, .Lalign_symbol + 0x4 + (\max << 8) + nop; nop; nop + .endif +.endm + + .text +.Lalign_symbol: +.Ltext_start: + break 1 + break 2 +## +0x8: Emit 2 nops, delete 1 nop. + .fake_p2align_4 + + break 3 +## +0x14: Emit 3 nops > 8 bytes, not emit. + .fake_p2align_4 8 + + break 4 + .fake_p2align_4 8 +## +0x18: Emit 2 nops <= 8 bytes. + +## Compensate +.ifdef old + nop; nop +.endif + +## +0x20: Test symbol value and symbol size can be handled. + la.pcrel $a0, .Ltext_start + la.pcrel $a0, .L1 + la.pcrel $a0, .L2 + +## +0x38: Emit 2 nops, delete 1 nop. +.L1: + .fake_p2align_4 +.L2: + break 5 + .size .L1, . - .L1 + .size .L2, . - .L2 + .size .Ltext_start, . - .Ltext_start + +## Test another text section. + .section .text2,"ax",@progbits +.Ltext2_start: + la.pcrel $a0, .Ltext2_start + .fake_p2align_4 + break 6 + .size .Ltext2_start, . - .Ltext2_start diff --git a/lld/test/ELF/loongarch-relax-emit-relocs.s b/lld/test/ELF/loongarch-relax-emit-relocs.s new file mode 100644 index 0000000000000000000000000000000000000000..581fce8c95caa4e25a1d1d40459df7c1d34fb782 --- /dev/null +++ b/lld/test/ELF/loongarch-relax-emit-relocs.s @@ -0,0 +1,49 @@ +# REQUIRES: loongarch +## Test that we can handle --emit-relocs while relaxing. + +# RUN: llvm-mc --filetype=obj --triple=loongarch32 --mattr=+relax %s -o %t.32.o +# RUN: llvm-mc --filetype=obj --triple=loongarch64 --mattr=+relax %s -o %t.64.o +# RUN: ld.lld -Ttext=0x10000 --emit-relocs %t.32.o -o %t.32 +# RUN: ld.lld -Ttext=0x10000 --emit-relocs %t.64.o -o %t.64 +# RUN: llvm-objdump -dr %t.32 | FileCheck %s +# RUN: llvm-objdump -dr %t.64 | FileCheck %s + +## -r should keep original relocations. +# RUN: ld.lld -r %t.64.o -o %t.64.r +# RUN: llvm-objdump -dr %t.64.r | FileCheck %s --check-prefix=CHECKR + +## --no-relax should keep original relocations. +## TODO Due to R_LARCH_RELAX is not relaxed, it plays same as --relax now. +# RUN: ld.lld -Ttext=0x10000 --emit-relocs --no-relax %t.64.o -o %t.64.norelax +# RUN: llvm-objdump -dr %t.64.norelax | FileCheck %s + +# CHECK: 00010000 <_start>: +# CHECK-NEXT: pcalau12i $a0, 0 +# CHECK-NEXT: R_LARCH_PCALA_HI20 _start +# CHECK-NEXT: R_LARCH_RELAX *ABS* +# CHECK-NEXT: addi.{{[dw]}} $a0, $a0, 0 +# CHECK-NEXT: R_LARCH_PCALA_LO12 _start +# CHECK-NEXT: R_LARCH_RELAX *ABS* +# CHECK-NEXT: nop +# CHECK-NEXT: R_LARCH_ALIGN .Lla-relax-align0+0x4 +# CHECK-NEXT: nop +# CHECK-NEXT: ret + +# CHECKR: <_start>: +# CHECKR-NEXT: pcalau12i $a0, 0 +# CHECKR-NEXT: R_LARCH_PCALA_HI20 _start +# CHECKR-NEXT: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: addi.d $a0, $a0, 0 +# CHECKR-NEXT: R_LARCH_PCALA_LO12 _start +# CHECKR-NEXT: R_LARCH_RELAX *ABS* +# CHECKR-NEXT: nop +# CHECKR-NEXT: R_LARCH_ALIGN .Lla-relax-align0+0x4 +# CHECKR-NEXT: nop +# CHECKR-NEXT: nop +# CHECKR-NEXT: ret + +.global _start +_start: + la.pcrel $a0, _start + .p2align 4 + ret diff --git a/lld/test/wasm/build-id.test b/lld/test/wasm/build-id.test index b767d8de4a423b85851291418db479d31a7fd507..dd6e2237108f38dc26af92f052dd95cf1476907e 100644 --- a/lld/test/wasm/build-id.test +++ b/lld/test/wasm/build-id.test @@ -43,18 +43,18 @@ foo: # DEFAULT: Contents of section build_id: -# DEFAULT-NEXT: 0000 10299168 1e3c845a 3c8f80ae 2f16cc22 .).h.<.Z<.../.." -# DEFAULT-NEXT: 0010 2d +# DEFAULT-NEXT: 0079 10299168 1e3c845a 3c8f80ae 2f16cc22 .).h.<.Z<.../.." +# DEFAULT-NEXT: 0089 2d # SHA1: Contents of section build_id: -# SHA1-NEXT: 0000 145abdda 387a9bc4 e3aed3c3 3319cd37 .Z..8z......3..7 -# SHA1-NEXT: 0010 0212237c e4 ..#|. +# SHA1-NEXT: 0079 145abdda 387a9bc4 e3aed3c3 3319cd37 .Z..8z......3..7 +# SHA1-NEXT: 0089 0212237c e4 ..#|. # UUID: Contents of section build_id: -# UUID-NEXT: 0000 10 +# UUID-NEXT: 0079 10 # HEX: Contents of section build_id: -# HEX-NEXT: 0000 04123456 78 ..4Vx +# HEX-NEXT: 0079 04123456 78 ..4Vx # NONE-NOT: Contents of section build_id: diff --git a/lld/test/wasm/merge-string-debug.s b/lld/test/wasm/merge-string-debug.s index 73e31d5361f41f9367e50661bcd1d252dcc44f49..0075a834e06477f58f7b28af1ea13abdcbb59a43 100644 --- a/lld/test/wasm/merge-string-debug.s +++ b/lld/test/wasm/merge-string-debug.s @@ -29,13 +29,13 @@ # CHECK: Hex dump of section '.debug_str': -# CHECK-O0: 0x00000000 636c616e 67207665 7273696f 6e203133 clang version 13 -# CHECK-O0: 0x00000010 2e302e30 00666f6f 62617200 636c616e .0.0.foobar.clan -# CHECK-O0: 0x00000020 67207665 7273696f 6e203133 2e302e30 g version 13.0.0 -# CHECK-O0: 0x00000030 00626172 00666f6f 00 .bar.foo. +# CHECK-O0: 0x00000025 636c616e 67207665 7273696f 6e203133 clang version 13 +# CHECK-O0: 0x00000035 2e302e30 00666f6f 62617200 636c616e .0.0.foobar.clan +# CHECK-O0: 0x00000045 67207665 7273696f 6e203133 2e302e30 g version 13.0.0 +# CHECK-O0: 0x00000055 00626172 00666f6f 00 .bar.foo. -# CHECK-O1: 0x00000000 666f6f62 61720066 6f6f0063 6c616e67 foobar.foo.clang -# CHECK-O1: 0x00000010 20766572 73696f6e 2031332e 302e3000 version 13.0.0. +# CHECK-O1: 0x00000025 666f6f62 61720066 6f6f0063 6c616e67 foobar.foo.clang +# CHECK-O1: 0x00000035 20766572 73696f6e 2031332e 302e3000 version 13.0.0. # CHECK-OFFSETS: Hex dump of section '.debug_str_offsets': -# CHECK-OFFSETS: 0x00000000 00000000 00000000 00000000 ............ +# CHECK-OFFSETS: 0x0000007e 00000000 00000000 00000000 ............ diff --git a/lld/test/wasm/startstop.ll b/lld/test/wasm/startstop.ll index 4341d371f8e65ea692268bc1faea755bb0f5a0a5..e7a5c80f91f287903681a954231b74cd9def62e1 100644 --- a/lld/test/wasm/startstop.ll +++ b/lld/test/wasm/startstop.ll @@ -34,12 +34,12 @@ entry: ; CHECK-NEXT: Value: 1024 ; CHECK-NEXT: Content: 03000000040000002A0000002B000000 -; ASM: 00000001 : +; ASM: 0000006e : ; ASM-EMPTY: -; ASM-NEXT: 3: i32.const 1024 -; ASM-NEXT: 9: end +; ASM-NEXT: 70: i32.const 1024 +; ASM-NEXT: 76: end -; ASM: 0000000a : +; ASM: 00000077 : ; ASM-EMPTY: -; ASM-NEXT: c: i32.const 1040 -; ASM-NEXT: 12: end +; ASM-NEXT: 79: i32.const 1040 +; ASM-NEXT: 7f: end diff --git a/lldb/bindings/headers.swig b/lldb/bindings/headers.swig index 408db90b925f15ed3ac452d2b727b5a4d576d7a6..e8d0cda288141c9bf292416ee21a940b854a8951 100644 --- a/lldb/bindings/headers.swig +++ b/lldb/bindings/headers.swig @@ -54,6 +54,7 @@ #include "lldb/API/SBScriptObject.h" #include "lldb/API/SBSection.h" #include "lldb/API/SBSourceManager.h" +#include "lldb/API/SBStatisticsOptions.h" #include "lldb/API/SBStream.h" #include "lldb/API/SBStringList.h" #include "lldb/API/SBStructuredData.h" diff --git a/lldb/bindings/interface/SBStatisticsOptionsDocstrings.i b/lldb/bindings/interface/SBStatisticsOptionsDocstrings.i new file mode 100644 index 0000000000000000000000000000000000000000..f72cf84319e19bab19f6307655fa8385f0a6b2e1 --- /dev/null +++ b/lldb/bindings/interface/SBStatisticsOptionsDocstrings.i @@ -0,0 +1,8 @@ +%feature("docstring", +"A container for options to use when dumping statistics." +) lldb::SBStatisticsOptions; + +%feature("docstring", "Sets whether the statistics should only dump a summary." +) lldb::SBStatisticsOptions::SetSummaryOnly; +%feature("docstring", "Gets whether the statistics only dump a summary." +) lldb::SBStatisticsOptions::GetSummaryOnly; diff --git a/lldb/bindings/interfaces.swig b/lldb/bindings/interfaces.swig index 9ca479218f621c54aeea903efb2ec114e1c391af..a31a0b4af1eb6c3b3f7abfaa4b5a31bdf1621dca 100644 --- a/lldb/bindings/interfaces.swig +++ b/lldb/bindings/interfaces.swig @@ -56,6 +56,7 @@ %include "./interface/SBReproducerDocstrings.i" %include "./interface/SBSectionDocstrings.i" %include "./interface/SBSourceManagerDocstrings.i" +%include "./interface/SBStatisticsOptionsDocstrings.i" %include "./interface/SBStreamDocstrings.i" %include "./interface/SBStringListDocstrings.i" %include "./interface/SBStructuredDataDocstrings.i" @@ -131,6 +132,7 @@ %include "lldb/API/SBScriptObject.h" %include "lldb/API/SBSection.h" %include "lldb/API/SBSourceManager.h" +%include "lldb/API/SBStatisticsOptions.h" %include "lldb/API/SBStream.h" %include "lldb/API/SBStringList.h" %include "lldb/API/SBStructuredData.h" diff --git a/lldb/docs/lldb-gdb-remote.txt b/lldb/docs/lldb-gdb-remote.txt index 58269e4c2b688ba829c3f86f2817312dd80d41c7..6c29de61daba7edd46ae0e5d28b9074d46872492 100644 --- a/lldb/docs/lldb-gdb-remote.txt +++ b/lldb/docs/lldb-gdb-remote.txt @@ -38,7 +38,45 @@ read packet: + read packet: $OK#9a send packet: + +//---------------------------------------------------------------------- +// "QSupported" +// +// BRIEF +// Query the GDB remote server for features it supports +// +// PRIORITY TO IMPLEMENT +// Optional. +//---------------------------------------------------------------------- + +QSupported is a standard GDB Remote Serial Protocol packet, but +there are several additions to the response that lldb can parse. +They are not all listed here. + +An example exchange: + +send packet: qSupported:xmlRegisters=i386,arm,mips,arc;multiprocess+;fork-events+;vfork-events+ + +read packet: qXfer:features:read+;PacketSize=20000;qEcho+;native-signals+;SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;SupportedWatchpointTypes=aarch64-mask,aarch64-bas; + +In the example above, three lldb extensions are shown: + PacketSize=20000 + The base 16 maximum packet size that the stub can handle. + SupportedCompressions= + A list of compression types that the stub can use to compress packets + when the QEnableCompression packet is used to request one of them. + SupportedWatchpointTypes= + A list of watchpoint types that this stub can manage. + Currently defined names are: + x86_64 64-bit x86-64 watchpoints + (1, 2, 4, 8 byte watchpoints aligned to those amounts) + aarch64-bas AArch64 Byte Address Select watchpoints + (any number of contiguous bytes within a doubleword) + aarch64-mask AArch64 MASK watchpoints + (any power-of-2 region of memory from 8 to 2GB, aligned) + If nothing is specified, lldb will default to sending power-of-2 + watchpoints, up to a pointer size, `sizeof(void*)`, a reasonable + baseline assumption. //---------------------------------------------------------------------- // "A" - launch args packet @@ -594,7 +632,7 @@ read packet: /E;AAAAAAAAA With LLDB, for register information, remote GDB servers can add support for the "qRegisterInfoN" packet where "N" is a zero based -base16 register number that must start at zero and increase by one +base 16 register number that must start at zero and increase by one for each register that is supported. The response is done in typical GDB remote fashion where a series of "KEY:VALUE;" pairs are returned. An example for the x86_64 registers is included below: @@ -1053,7 +1091,7 @@ Suggested key names: // 64-bit slices so it may be impossible to know until you're attached to a real // process to know what you're working with. // -// All numeric fields return base-16 numbers without any "0x" prefix. +// All numeric fields return base 16 numbers without any "0x" prefix. //---------------------------------------------------------------------- An i386 process: @@ -1085,7 +1123,7 @@ main-binary-uuid: is the UUID of a firmware type binary that the gdb stub knows main-binary-address: is the load address of the firmware type binary main-binary-slide: is the slide of the firmware type binary, if address isn't known -binary-addresses: A comma-separated list of binary load addresses base16. +binary-addresses: A comma-separated list of binary load addresses base 16. lldb will parse the binaries in memory to get UUIDs, then try to find the binaries & debug info by UUID. Intended for use with a small number of firmware type binaries where the @@ -1302,7 +1340,7 @@ tuples to return are: dirty-pages:[][,#00 // -// $C:#00 +// $C:#00 // // Where "#00" is the actual checksum value if noack mode is not enabled. The checksum // value is for the "N" or -// "C:" bytes in the packet. +// "C:" bytes in the packet. // -// The size of the uncompressed payload in base10 is provided because it will simplify +// The size of the uncompressed payload in base 10 is provided because it will simplify // decompression if the final buffer size needed is known ahead of time. // // Compression on low-latency connections is unlikely to be an improvement. Particularly diff --git a/lldb/include/lldb/API/LLDB.h b/lldb/include/lldb/API/LLDB.h index f5f1b87a046c2a636e6be5df023a9cab5a08430c..c83eb92fcfb30af2c58939fa035959aab0fa1ae9 100644 --- a/lldb/include/lldb/API/LLDB.h +++ b/lldb/include/lldb/API/LLDB.h @@ -56,6 +56,7 @@ #include "lldb/API/SBReproducer.h" #include "lldb/API/SBSection.h" #include "lldb/API/SBSourceManager.h" +#include "lldb/API/SBStatisticsOptions.h" #include "lldb/API/SBStream.h" #include "lldb/API/SBStringList.h" #include "lldb/API/SBStructuredData.h" diff --git a/lldb/include/lldb/API/SBDefines.h b/lldb/include/lldb/API/SBDefines.h index 92d823fa1dfe25005a5724c2a7f79a5e184c34ea..1181920677b46f50e7c1a2e7c35ae6d746b8fbe1 100644 --- a/lldb/include/lldb/API/SBDefines.h +++ b/lldb/include/lldb/API/SBDefines.h @@ -99,6 +99,7 @@ class LLDB_API SBReproducer; class LLDB_API SBScriptObject; class LLDB_API SBSection; class LLDB_API SBSourceManager; +class LLDB_API SBStatisticsOptions; class LLDB_API SBStream; class LLDB_API SBStringList; class LLDB_API SBStructuredData; diff --git a/lldb/include/lldb/API/SBProcess.h b/lldb/include/lldb/API/SBProcess.h index 8c1c81418f83d12daa3f0438f18f95c07c19ac55..4f92a41f3028a20972c0e6137f01c184454b7646 100644 --- a/lldb/include/lldb/API/SBProcess.h +++ b/lldb/include/lldb/API/SBProcess.h @@ -398,6 +398,15 @@ public: /// valid. lldb::SBProcessInfo GetProcessInfo(); + /// Get the file specification for the core file that is currently being used + /// for the process. If the process is not loaded from a core file, then an + /// invalid file specification will be returned. + /// + /// \return + /// The path to the core file for this target or an invalid file spec if + /// the process isn't loaded from a core file. + lldb::SBFileSpec GetCoreFile(); + /// Allocate memory within the process. /// /// This function will allocate memory in the process's address space. diff --git a/lldb/include/lldb/API/SBStatisticsOptions.h b/lldb/include/lldb/API/SBStatisticsOptions.h new file mode 100644 index 0000000000000000000000000000000000000000..8019ed4315ca21143ba7bf00ad18ec3765254a7b --- /dev/null +++ b/lldb/include/lldb/API/SBStatisticsOptions.h @@ -0,0 +1,36 @@ +//===-- SBStatisticsOptions.h -----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLDB_API_SBSTATISTICSOPTIONS_H +#define LLDB_API_SBSTATISTICSOPTIONS_H + +#include "lldb/API/SBDefines.h" + +namespace lldb { + +/// This class handles the verbosity when dumping statistics +class LLDB_API SBStatisticsOptions { +public: + SBStatisticsOptions(); + SBStatisticsOptions(const lldb::SBStatisticsOptions &rhs); + ~SBStatisticsOptions(); + + const SBStatisticsOptions &operator=(const lldb::SBStatisticsOptions &rhs); + + void SetSummaryOnly(bool b); + bool GetSummaryOnly(); + +protected: + friend class SBTarget; + const lldb_private::StatisticsOptions &ref() const; + +private: + std::unique_ptr m_opaque_up; +}; +} // namespace lldb +#endif // LLDB_API_SBSTATISTICSOPTIONS_H diff --git a/lldb/include/lldb/API/SBTarget.h b/lldb/include/lldb/API/SBTarget.h index 83087623088c5b49d8438d11a8fd959c7f594925..f7bdd3093d2025daa433472212a621c349d35704 100644 --- a/lldb/include/lldb/API/SBTarget.h +++ b/lldb/include/lldb/API/SBTarget.h @@ -17,6 +17,7 @@ #include "lldb/API/SBFileSpec.h" #include "lldb/API/SBFileSpecList.h" #include "lldb/API/SBLaunchInfo.h" +#include "lldb/API/SBStatisticsOptions.h" #include "lldb/API/SBSymbolContextList.h" #include "lldb/API/SBType.h" #include "lldb/API/SBValue.h" @@ -90,6 +91,15 @@ public: /// A SBStructuredData with the statistics collected. lldb::SBStructuredData GetStatistics(); + /// Returns a dump of the collected statistics. + /// + /// \param[in] options + /// An objects object that contains all options for the statistics dumping. + /// + /// \return + /// A SBStructuredData with the statistics collected. + lldb::SBStructuredData GetStatistics(SBStatisticsOptions options); + /// Return the platform object associated with the target. /// /// After return, the platform object should be checked for diff --git a/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h b/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h index a9ec070bbcfe2f40f10757b9702c4e6ca1a917fd..7d6d9f442b38529d5d802ee4e3f12b977e37e886 100644 --- a/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h +++ b/lldb/include/lldb/Breakpoint/WatchpointAlgorithms.h @@ -11,7 +11,7 @@ #include "lldb/Breakpoint/WatchpointResource.h" #include "lldb/Utility/ArchSpec.h" -#include "lldb/lldb-public.h" +#include "lldb/lldb-private.h" #include @@ -58,7 +58,7 @@ public: /// watchpoint cannot be set. static std::vector AtomizeWatchpointRequest( lldb::addr_t addr, size_t size, bool read, bool write, - lldb::WatchpointHardwareFeature supported_features, ArchSpec &arch); + WatchpointHardwareFeature supported_features, ArchSpec &arch); protected: struct Region { diff --git a/lldb/include/lldb/Target/PostMortemProcess.h b/lldb/include/lldb/Target/PostMortemProcess.h index 7207fc99ef29a4111cfe2cdc3c5cbe453a8a034f..9c9cd7fa599bc3b7529d2295737cfa8bd7171b99 100644 --- a/lldb/include/lldb/Target/PostMortemProcess.h +++ b/lldb/include/lldb/Target/PostMortemProcess.h @@ -24,7 +24,16 @@ class PostMortemProcess : public Process { using Process::Process; public: + PostMortemProcess(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, + const FileSpec &core_file) + : Process(target_sp, listener_sp), m_core_file(core_file) {} + bool IsLiveDebugSession() const override { return false; } + + FileSpec GetCoreFile() const override { return m_core_file; } + +protected: + FileSpec m_core_file; }; } // namespace lldb_private diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 7048921d6034fd218ee742ac1accad50b2f47cbc..0ad626ffd3613c7c9fe136190b589cb802e766f9 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -1503,6 +1503,13 @@ public: virtual bool IsLiveDebugSession() const { return true; }; + /// Provide a way to retrieve the core dump file that is loaded for debugging. + /// Only available if IsLiveDebugSession() returns true. + /// + /// \return + /// File path to the core file. + virtual FileSpec GetCoreFile() const { return {}; } + /// Before lldb detaches from a process, it warns the user that they are /// about to lose their debug session. In some cases, this warning doesn't /// need to be emitted -- for instance, with core file debugging where the diff --git a/lldb/include/lldb/Target/ProcessTrace.h b/lldb/include/lldb/Target/ProcessTrace.h index 037dea232cc024d09c8dcaebe618cfba8f3c8d59..7a025100f68032a08f618a5618aecb46b8e0d828 100644 --- a/lldb/include/lldb/Target/ProcessTrace.h +++ b/lldb/include/lldb/Target/ProcessTrace.h @@ -27,7 +27,8 @@ public: static llvm::StringRef GetPluginDescriptionStatic(); - ProcessTrace(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp); + ProcessTrace(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, + const FileSpec &core_file); ~ProcessTrace() override; diff --git a/lldb/include/lldb/Target/Statistics.h b/lldb/include/lldb/Target/Statistics.h index f672786f58f84d6c16890f20faf9823692369953..f838fa17f80c24086a9c24022e17ac0155591749 100644 --- a/lldb/include/lldb/Target/Statistics.h +++ b/lldb/include/lldb/Target/Statistics.h @@ -130,10 +130,15 @@ struct ConstStringStats { ConstString::MemoryStats stats = ConstString::GetMemoryStats(); }; +struct StatisticsOptions { + bool summary_only = false; +}; + /// A class that represents statistics for a since lldb_private::Target. class TargetStats { public: - llvm::json::Value ToJSON(Target &target); + llvm::json::Value ToJSON(Target &target, + const lldb_private::StatisticsOptions &options); void SetLaunchOrAttachTime(); void SetFirstPrivateStopTime(); @@ -171,9 +176,15 @@ public: /// The single target to emit statistics for if non NULL, otherwise dump /// statistics only for the specified target. /// + /// \param summary_only + /// If true, only report high level summary statistics without + /// targets/modules/breakpoints etc.. details. + /// /// \return /// Returns a JSON value that contains all target metrics. - static llvm::json::Value ReportStatistics(Debugger &debugger, Target *target); + static llvm::json::Value + ReportStatistics(Debugger &debugger, Target *target, + const lldb_private::StatisticsOptions &options); protected: // Collecting stats can be set to true to collect stats that are expensive diff --git a/lldb/include/lldb/Target/Target.h b/lldb/include/lldb/Target/Target.h index c37682e2a03859f5d6f50e9799b252535c1c56f0..8f57358981d4d2732e345422201cdbf11a389134 100644 --- a/lldb/include/lldb/Target/Target.h +++ b/lldb/include/lldb/Target/Target.h @@ -1599,7 +1599,8 @@ public: /// /// \return /// Returns a JSON value that contains all target metrics. - llvm::json::Value ReportStatistics(); + llvm::json::Value + ReportStatistics(const lldb_private::StatisticsOptions &options); TargetStats &GetStatistics() { return m_stats; } diff --git a/lldb/include/lldb/lldb-enumerations.h b/lldb/include/lldb/lldb-enumerations.h index 50cbccba4d7c56fe5e527fae21410e21c6fe84f4..392d333c23a44705f18a149173ba332d1ff0b2c5 100644 --- a/lldb/include/lldb/lldb-enumerations.h +++ b/lldb/include/lldb/lldb-enumerations.h @@ -448,32 +448,6 @@ enum WatchpointWriteType { eWatchpointWriteTypeOnModify }; -/// The hardware and native stub capabilities for a given target, -/// for translating a user's watchpoint request into hardware -/// capable watchpoint resources. -FLAGS_ENUM(WatchpointHardwareFeature){ - /// lldb will fall back to a default that assumes the target - /// can watch up to pointer-size power-of-2 regions, aligned to - /// power-of-2. - eWatchpointHardwareFeatureUnknown = (1u << 0), - - /// Intel systems can watch 1, 2, 4, or 8 bytes (in 64-bit targets), - /// aligned naturally. - eWatchpointHardwareX86 = (1u << 1), - - /// ARM systems with Byte Address Select watchpoints - /// can watch any consecutive series of bytes up to the - /// size of a pointer (4 or 8 bytes), at a pointer-size - /// alignment. - eWatchpointHardwareArmBAS = (1u << 2), - - /// ARM systems with MASK watchpoints can watch any power-of-2 - /// sized region from 8 bytes to 2 gigabytes, aligned to that - /// same power-of-2 alignment. - eWatchpointHardwareArmMASK = (1u << 3), -}; -LLDB_MARK_AS_BITMASK_ENUM(WatchpointHardwareFeature) - /// Programming language type. /// /// These enumerations use the same language enumerations as the DWARF diff --git a/lldb/include/lldb/lldb-forward.h b/lldb/include/lldb/lldb-forward.h index d89ad21512215f7fabf0db8af08d866b386b0755..10ba921b9dac8c5886fef61783bed9fb3c59b1fd 100644 --- a/lldb/include/lldb/lldb-forward.h +++ b/lldb/include/lldb/lldb-forward.h @@ -298,6 +298,7 @@ struct CompilerContext; struct LineEntry; struct PropertyDefinition; struct ScriptSummaryFormat; +struct StatisticsOptions; struct StringSummaryFormat; template class StreamBuffer; diff --git a/lldb/include/lldb/lldb-private-enumerations.h b/lldb/include/lldb/lldb-private-enumerations.h index 5f1597200a83e753607a312626b507b1dbb990c7..9e8ab56305bef3ca752560a43fa6af3b9af14a31 100644 --- a/lldb/include/lldb/lldb-private-enumerations.h +++ b/lldb/include/lldb/lldb-private-enumerations.h @@ -9,6 +9,7 @@ #ifndef LLDB_LLDB_PRIVATE_ENUMERATIONS_H #define LLDB_LLDB_PRIVATE_ENUMERATIONS_H +#include "lldb/lldb-enumerations.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/FormatProviders.h" #include "llvm/Support/raw_ostream.h" @@ -282,4 +283,30 @@ enum InterruptionControl : bool { DoNotAllowInterruption = false, }; +/// The hardware and native stub capabilities for a given target, +/// for translating a user's watchpoint request into hardware +/// capable watchpoint resources. +FLAGS_ENUM(WatchpointHardwareFeature){ + /// lldb will fall back to a default that assumes the target + /// can watch up to pointer-size power-of-2 regions, aligned to + /// power-of-2. + eWatchpointHardwareFeatureUnknown = (1u << 0), + + /// Intel systems can watch 1, 2, 4, or 8 bytes (in 64-bit targets), + /// aligned naturally. + eWatchpointHardwareX86 = (1u << 1), + + /// ARM systems with Byte Address Select watchpoints + /// can watch any consecutive series of bytes up to the + /// size of a pointer (4 or 8 bytes), at a pointer-size + /// alignment. + eWatchpointHardwareArmBAS = (1u << 2), + + /// ARM systems with MASK watchpoints can watch any power-of-2 + /// sized region from 8 bytes to 2 gigabytes, aligned to that + /// same power-of-2 alignment. + eWatchpointHardwareArmMASK = (1u << 3), +}; +LLDB_MARK_AS_BITMASK_ENUM(WatchpointHardwareFeature) + #endif // LLDB_LLDB_PRIVATE_ENUMERATIONS_H diff --git a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py index 3341b6e54a3bc74890f8a813d81281944bfce25a..75522158b32210cf5eb0ec600742014db57895e6 100644 --- a/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py +++ b/lldb/packages/Python/lldbsuite/test/tools/lldb-server/gdbremote_testcase.py @@ -921,6 +921,8 @@ class GdbRemoteTestCaseBase(Base, metaclass=GdbRemoteTestCaseFactory): "qSaveCore", "native-signals", "QNonStop", + "SupportedWatchpointTypes", + "SupportedCompressions", ] def parse_qSupported_response(self, context): diff --git a/lldb/source/API/CMakeLists.txt b/lldb/source/API/CMakeLists.txt index 7d478ecc7f599e92bb764c505133da68d6652b29..57cc44f764675398d7503b8bcedd1d7052605001 100644 --- a/lldb/source/API/CMakeLists.txt +++ b/lldb/source/API/CMakeLists.txt @@ -69,6 +69,7 @@ add_lldb_library(liblldb SHARED ${option_framework} SBScriptObject.cpp SBSection.cpp SBSourceManager.cpp + SBStatisticsOptions.cpp SBStream.cpp SBStringList.cpp SBStructuredData.cpp diff --git a/lldb/source/API/SBProcess.cpp b/lldb/source/API/SBProcess.cpp index 4864ea0e7d0268dad783172e4093f1dd4c19983b..a9fe915324683ec102b2ef045d00dc2786311031 100644 --- a/lldb/source/API/SBProcess.cpp +++ b/lldb/source/API/SBProcess.cpp @@ -1244,6 +1244,17 @@ lldb::SBProcessInfo SBProcess::GetProcessInfo() { return sb_proc_info; } +lldb::SBFileSpec SBProcess::GetCoreFile() { + LLDB_INSTRUMENT_VA(this); + + ProcessSP process_sp(GetSP()); + FileSpec core_file; + if (process_sp) { + core_file = process_sp->GetCoreFile(); + } + return SBFileSpec(core_file); +} + lldb::addr_t SBProcess::AllocateMemory(size_t size, uint32_t permissions, lldb::SBError &sb_error) { LLDB_INSTRUMENT_VA(this, size, permissions, sb_error); diff --git a/lldb/source/API/SBStatisticsOptions.cpp b/lldb/source/API/SBStatisticsOptions.cpp new file mode 100644 index 0000000000000000000000000000000000000000..77a7e26a6bd4b5569bf5fe4b4a5deffb94060329 --- /dev/null +++ b/lldb/source/API/SBStatisticsOptions.cpp @@ -0,0 +1,49 @@ +//===-- SBStatisticsOptions.cpp -------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "lldb/API/SBStatisticsOptions.h" +#include "lldb/Target/Statistics.h" +#include "lldb/Utility/Instrumentation.h" + +#include "Utils.h" + +using namespace lldb; +using namespace lldb_private; + +SBStatisticsOptions::SBStatisticsOptions() + : m_opaque_up(new StatisticsOptions()) { + LLDB_INSTRUMENT_VA(this); + m_opaque_up->summary_only = false; +} + +SBStatisticsOptions::SBStatisticsOptions(const SBStatisticsOptions &rhs) { + LLDB_INSTRUMENT_VA(this, rhs); + + m_opaque_up = clone(rhs.m_opaque_up); +} + +SBStatisticsOptions::~SBStatisticsOptions() = default; + +const SBStatisticsOptions & +SBStatisticsOptions::operator=(const SBStatisticsOptions &rhs) { + LLDB_INSTRUMENT_VA(this, rhs); + + if (this != &rhs) + m_opaque_up = clone(rhs.m_opaque_up); + return *this; +} + +void SBStatisticsOptions::SetSummaryOnly(bool b) { + m_opaque_up->summary_only = b; +} + +bool SBStatisticsOptions::GetSummaryOnly() { return m_opaque_up->summary_only; } + +const lldb_private::StatisticsOptions &SBStatisticsOptions::ref() const { + return *m_opaque_up; +} diff --git a/lldb/source/API/SBTarget.cpp b/lldb/source/API/SBTarget.cpp index 8e616afbcb4e8dfc8fab11297c427e1d1912f282..cc9f1fdd76afaa5ab96810fd72ead766b1a08f25 100644 --- a/lldb/source/API/SBTarget.cpp +++ b/lldb/source/API/SBTarget.cpp @@ -199,15 +199,22 @@ SBDebugger SBTarget::GetDebugger() const { SBStructuredData SBTarget::GetStatistics() { LLDB_INSTRUMENT_VA(this); + SBStatisticsOptions options; + return GetStatistics(options); +} + +SBStructuredData SBTarget::GetStatistics(SBStatisticsOptions options) { + LLDB_INSTRUMENT_VA(this); SBStructuredData data; TargetSP target_sp(GetSP()); if (!target_sp) return data; std::string json_str = - llvm::formatv("{0:2}", - DebuggerStats::ReportStatistics(target_sp->GetDebugger(), - target_sp.get())).str(); + llvm::formatv("{0:2}", DebuggerStats::ReportStatistics( + target_sp->GetDebugger(), target_sp.get(), + options.ref())) + .str(); data.m_impl_up->SetObjectSP(StructuredData::ParseJSON(json_str)); return data; } diff --git a/lldb/source/Breakpoint/WatchpointAlgorithms.cpp b/lldb/source/Breakpoint/WatchpointAlgorithms.cpp index 94f1dfffbf2932f914094e28b047b8bf8f50f577..3caf29b04317f241e636f6f3e4ae02e4df98f19a 100644 --- a/lldb/source/Breakpoint/WatchpointAlgorithms.cpp +++ b/lldb/source/Breakpoint/WatchpointAlgorithms.cpp @@ -27,8 +27,7 @@ WatchpointAlgorithms::AtomizeWatchpointRequest( std::vector entries; - if (supported_features & - WatchpointHardwareFeature::eWatchpointHardwareArmMASK) { + if (supported_features & eWatchpointHardwareArmMASK) { entries = PowerOf2Watchpoints(addr, size, /*min_byte_size*/ 1, diff --git a/lldb/source/Commands/CommandObjectStats.cpp b/lldb/source/Commands/CommandObjectStats.cpp index 262de0bda144a6023ad15711abd058d0e1ebb049..b23b7024c8217602be2cb1b19f15a2f364fe0577 100644 --- a/lldb/source/Commands/CommandObjectStats.cpp +++ b/lldb/source/Commands/CommandObjectStats.cpp @@ -75,6 +75,9 @@ class CommandObjectStatsDump : public CommandObjectParsed { case 'a': m_all_targets = true; break; + case 's': + m_stats_options.summary_only = true; + break; default: llvm_unreachable("Unimplemented option"); } @@ -83,13 +86,17 @@ class CommandObjectStatsDump : public CommandObjectParsed { void OptionParsingStarting(ExecutionContext *execution_context) override { m_all_targets = false; + m_stats_options = StatisticsOptions(); } llvm::ArrayRef GetDefinitions() override { return llvm::ArrayRef(g_statistics_dump_options); } + const StatisticsOptions &GetStatisticsOptions() { return m_stats_options; } + bool m_all_targets = false; + StatisticsOptions m_stats_options = StatisticsOptions(); }; public: @@ -109,7 +116,8 @@ protected: target = m_exe_ctx.GetTargetPtr(); result.AppendMessageWithFormatv( - "{0:2}", DebuggerStats::ReportStatistics(GetDebugger(), target)); + "{0:2}", DebuggerStats::ReportStatistics( + GetDebugger(), target, m_options.GetStatisticsOptions())); result.SetStatus(eReturnStatusSuccessFinishResult); } diff --git a/lldb/source/Commands/Options.td b/lldb/source/Commands/Options.td index ed3167727bcd326b0b6d70215bc8b221f8f085c8..a87f457105aac0c1bf3efec51d38054272825df8 100644 --- a/lldb/source/Commands/Options.td +++ b/lldb/source/Commands/Options.td @@ -1412,4 +1412,7 @@ let Command = "trace schema" in { let Command = "statistics dump" in { def statistics_dump_all: Option<"all-targets", "a">, Group<1>, Desc<"Include statistics for all targets.">; + def statistics_dump_summary: Option<"summary", "s">, Group<1>, + Desc<"Dump only high-level summary statistics." + "Exclude targets, modules, breakpoints etc... details.">; } diff --git a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp index 601f5df43dbba4e3d8af80b961f598c317e6156f..997b59085110323715b0c35761210675a576bad0 100644 --- a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp +++ b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.cpp @@ -32,7 +32,7 @@ namespace { class ProcessFreeBSDKernelFVC : public ProcessFreeBSDKernel { public: ProcessFreeBSDKernelFVC(lldb::TargetSP target_sp, lldb::ListenerSP listener, - fvc_t *fvc); + fvc_t *fvc, const FileSpec &core_file); ~ProcessFreeBSDKernelFVC(); @@ -67,8 +67,9 @@ private: } // namespace ProcessFreeBSDKernel::ProcessFreeBSDKernel(lldb::TargetSP target_sp, - ListenerSP listener_sp) - : PostMortemProcess(target_sp, listener_sp) {} + ListenerSP listener_sp, + const FileSpec &core_file) + : PostMortemProcess(target_sp, listener_sp, core_file) {} lldb::ProcessSP ProcessFreeBSDKernel::CreateInstance(lldb::TargetSP target_sp, ListenerSP listener_sp, @@ -82,7 +83,7 @@ lldb::ProcessSP ProcessFreeBSDKernel::CreateInstance(lldb::TargetSP target_sp, crash_file->GetPath().c_str(), nullptr, nullptr, nullptr); if (fvc) return std::make_shared(target_sp, listener_sp, - fvc); + fvc, *crash_file); #endif #if defined(__FreeBSD__) @@ -91,7 +92,7 @@ lldb::ProcessSP ProcessFreeBSDKernel::CreateInstance(lldb::TargetSP target_sp, crash_file->GetPath().c_str(), O_RDONLY, nullptr, nullptr); if (kvm) return std::make_shared(target_sp, listener_sp, - kvm); + kvm, *crash_file); #endif } return nullptr; @@ -276,8 +277,9 @@ lldb::addr_t ProcessFreeBSDKernel::FindSymbol(const char *name) { ProcessFreeBSDKernelFVC::ProcessFreeBSDKernelFVC(lldb::TargetSP target_sp, ListenerSP listener_sp, - fvc_t *fvc) - : ProcessFreeBSDKernel(target_sp, listener_sp), m_fvc(fvc) {} + fvc_t *fvc, + const FileSpec &core_file) + : ProcessFreeBSDKernel(target_sp, listener_sp, crash_file), m_fvc(fvc) {} ProcessFreeBSDKernelFVC::~ProcessFreeBSDKernelFVC() { if (m_fvc) @@ -303,8 +305,9 @@ const char *ProcessFreeBSDKernelFVC::GetError() { return fvc_geterr(m_fvc); } ProcessFreeBSDKernelKVM::ProcessFreeBSDKernelKVM(lldb::TargetSP target_sp, ListenerSP listener_sp, - kvm_t *fvc) - : ProcessFreeBSDKernel(target_sp, listener_sp), m_kvm(fvc) {} + kvm_t *fvc, + const FileSpec &core_file) + : ProcessFreeBSDKernel(target_sp, listener_sp, core_file), m_kvm(fvc) {} ProcessFreeBSDKernelKVM::~ProcessFreeBSDKernelKVM() { if (m_kvm) diff --git a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h index 5bd463126307cd97f4918123af71f84bf7927189..06c9d062441e5afd2580dcb2d3d99cb6db07f879 100644 --- a/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h +++ b/lldb/source/Plugins/Process/FreeBSDKernel/ProcessFreeBSDKernel.h @@ -13,7 +13,8 @@ class ProcessFreeBSDKernel : public lldb_private::PostMortemProcess { public: - ProcessFreeBSDKernel(lldb::TargetSP target_sp, lldb::ListenerSP listener); + ProcessFreeBSDKernel(lldb::TargetSP target_sp, lldb::ListenerSP listener, + const lldb_private::FileSpec &core_file); static lldb::ProcessSP CreateInstance(lldb::TargetSP target_sp, lldb::ListenerSP listener, diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp index 7723009787f7f6139d22fc28f2888c7ba0a8546d..36812c27a5b6d59d96ea7c04b4c685bfceae9f6b 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.cpp @@ -99,7 +99,7 @@ bool ProcessElfCore::CanDebug(lldb::TargetSP target_sp, ProcessElfCore::ProcessElfCore(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, const FileSpec &core_file) - : PostMortemProcess(target_sp, listener_sp), m_core_file(core_file) {} + : PostMortemProcess(target_sp, listener_sp, core_file) {} // Destructor ProcessElfCore::~ProcessElfCore() { @@ -261,8 +261,8 @@ Status ProcessElfCore::DoLoadCore() { exe_module_spec.GetFileSpec().SetFile(m_nt_file_entries[0].path, FileSpec::Style::native); if (exe_module_spec.GetFileSpec()) { - exe_module_sp = GetTarget().GetOrCreateModule(exe_module_spec, - true /* notify */); + exe_module_sp = + GetTarget().GetOrCreateModule(exe_module_spec, true /* notify */); if (exe_module_sp) GetTarget().SetExecutableModule(exe_module_sp, eLoadDependentsNo); } diff --git a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h index 1454e8735a677b5542e83a4fbbcd68f313be7f47..2cec635bbacfec50ae9b842f648ce58d3147f7c9 100644 --- a/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h +++ b/lldb/source/Plugins/Process/elf-core/ProcessElfCore.h @@ -127,7 +127,6 @@ private: VMRangeToPermissions; lldb::ModuleSP m_core_module_sp; - lldb_private::FileSpec m_core_file; std::string m_dyld_plugin_name; // True if m_thread_contexts contains valid entries diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp index 7bb449841851399f79d4d8810971e94810edbe34..6f8aa262289946688257dd79b3849736292d316d 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.cpp @@ -403,6 +403,18 @@ void GDBRemoteCommunicationClient::GetRemoteQSupported() { x.split(compressions, ','); if (!compressions.empty()) MaybeEnableCompression(compressions); + } else if (x.consume_front("SupportedWatchpointTypes=")) { + llvm::SmallVector watchpoint_types; + x.split(watchpoint_types, ','); + m_watchpoint_types = eWatchpointHardwareFeatureUnknown; + for (auto wp_type : watchpoint_types) { + if (wp_type == "x86_64") + m_watchpoint_types |= eWatchpointHardwareX86; + if (wp_type == "aarch64-mask") + m_watchpoint_types |= eWatchpointHardwareArmMASK; + if (wp_type == "aarch64-bas") + m_watchpoint_types |= eWatchpointHardwareArmBAS; + } } else if (x.consume_front("PacketSize=")) { StringExtractorGDBRemote packet_response(x); m_max_packet_size = @@ -1828,6 +1840,11 @@ std::optional GDBRemoteCommunicationClient::GetWatchpointSlotCount() { return num; } +WatchpointHardwareFeature +GDBRemoteCommunicationClient::GetSupportedWatchpointTypes() { + return m_watchpoint_types; +} + std::optional GDBRemoteCommunicationClient::GetWatchpointReportedAfter() { if (m_qHostInfo_is_valid == eLazyBoolCalculate) GetHostInfo(); diff --git a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h index 866b0773d86d56e72e58f3fcf3441fe3e668c928..bd2d3e232b4645f9ab2a92c2324ca6b9839ff107 100644 --- a/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h +++ b/lldb/source/Plugins/Process/gdb-remote/GDBRemoteCommunicationClient.h @@ -199,6 +199,8 @@ public: std::optional GetWatchpointReportedAfter(); + WatchpointHardwareFeature GetSupportedWatchpointTypes(); + const ArchSpec &GetHostArchitecture(); std::chrono::seconds GetHostDefaultPacketTimeout(); @@ -581,6 +583,8 @@ protected: lldb::tid_t m_curr_tid_run = LLDB_INVALID_THREAD_ID; uint32_t m_num_supported_hardware_watchpoints = 0; + WatchpointHardwareFeature m_watchpoint_types = + eWatchpointHardwareFeatureUnknown; uint32_t m_low_mem_addressing_bits = 0; uint32_t m_high_mem_addressing_bits = 0; diff --git a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp index 4e3447e767c35bb2d300f840fbaf65abbf22e8fd..629b191f3117aa34238a5df1091603e5632e2365 100644 --- a/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp +++ b/lldb/source/Plugins/Process/gdb-remote/ProcessGDBRemote.cpp @@ -3156,16 +3156,7 @@ Status ProcessGDBRemote::EnableWatchpoint(WatchpointSP wp_sp, bool notify) { ArchSpec target_arch = GetTarget().GetArchitecture(); WatchpointHardwareFeature supported_features = - eWatchpointHardwareFeatureUnknown; - - // LWP_TODO: enable MASK watchpoint for arm64 debugserver - // when it reports that it supports them. - if (target_arch.GetTriple().getOS() == llvm::Triple::MacOSX && - target_arch.GetTriple().getArch() == llvm::Triple::aarch64) { -#if 0 - supported_features |= eWatchpointHardwareArmMASK; -#endif - } + m_gdb_comm.GetSupportedWatchpointTypes(); std::vector resources = WatchpointAlgorithms::AtomizeWatchpointRequest( diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp index a2ea19388b75f2057258e31495fff8ef43b2dbdb..3961dcf0fbcc0eabc9c8ffa2517ccd7239c3841e 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.cpp @@ -111,8 +111,8 @@ bool ProcessMachCore::CanDebug(lldb::TargetSP target_sp, ProcessMachCore::ProcessMachCore(lldb::TargetSP target_sp, ListenerSP listener_sp, const FileSpec &core_file) - : PostMortemProcess(target_sp, listener_sp), m_core_aranges(), - m_core_range_infos(), m_core_module_sp(), m_core_file(core_file), + : PostMortemProcess(target_sp, listener_sp, core_file), m_core_aranges(), + m_core_range_infos(), m_core_module_sp(), m_dyld_addr(LLDB_INVALID_ADDRESS), m_mach_kernel_addr(LLDB_INVALID_ADDRESS) {} diff --git a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h index c8820209e3f38306387f0c626be392d7b05ca5de..8996ae116614bf61150ac599f8a972fe433c7fe1 100644 --- a/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h +++ b/lldb/source/Plugins/Process/mach-core/ProcessMachCore.h @@ -130,7 +130,6 @@ private: VMRangeToFileOffset m_core_aranges; VMRangeToPermissions m_core_range_infos; lldb::ModuleSP m_core_module_sp; - lldb_private::FileSpec m_core_file; lldb::addr_t m_dyld_addr; lldb::addr_t m_mach_kernel_addr; llvm::StringRef m_dyld_plugin_name; diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp index b72307c7e4b96568c22792336230a2e74e66ba59..13599f4a1553fdb7560ee4d0db693abe100bc854 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.cpp @@ -156,7 +156,7 @@ ProcessMinidump::ProcessMinidump(lldb::TargetSP target_sp, lldb::ListenerSP listener_sp, const FileSpec &core_file, DataBufferSP core_data) - : PostMortemProcess(target_sp, listener_sp), m_core_file(core_file), + : PostMortemProcess(target_sp, listener_sp, core_file), m_core_data(std::move(core_data)), m_active_exception(nullptr), m_is_wow64(false) {} diff --git a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h index 0e4e52c0113fb958b0526af7663e273616be82cc..3f3123a0a8b5d3f0154b97d6c2c3201bf49e78fb 100644 --- a/lldb/source/Plugins/Process/minidump/ProcessMinidump.h +++ b/lldb/source/Plugins/Process/minidump/ProcessMinidump.h @@ -107,7 +107,6 @@ protected: JITLoaderList &GetJITLoaders() override; private: - FileSpec m_core_file; lldb::DataBufferSP m_core_data; llvm::ArrayRef m_thread_list; const minidump::ExceptionStream *m_active_exception; diff --git a/lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp b/lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp index 47fe0020ce18de7c21a80349e360867bf49d09a6..f46bff8f7d12e381c4dfb3d03d6ff372e92af1c3 100644 --- a/lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp +++ b/lldb/source/Plugins/SymbolVendor/MacOSX/SymbolVendorMacOSX.cpp @@ -118,7 +118,13 @@ SymbolVendorMacOSX::CreateInstance(const lldb::ModuleSP &module_sp, FileSpec dsym_fspec(module_sp->GetSymbolFileFileSpec()); ObjectFileSP dsym_objfile_sp; - if (!dsym_fspec) { + // On Darwin, we store the debug information either in object files, + // using the debug map to tie them to the executable, or in a dSYM. We + // pass through this routine both for binaries and for .o files, but in the + // latter case there will never be an external debug file. So we shouldn't + // do all the stats needed to find it. + if (!dsym_fspec && module_sp->GetObjectFile()->CalculateType() != + ObjectFile::eTypeObjectFile) { // No symbol file was specified in the module, lets try and find one // ourselves. FileSpec file_spec = obj_file->GetFileSpec(); diff --git a/lldb/source/Target/ProcessTrace.cpp b/lldb/source/Target/ProcessTrace.cpp index 3a41f257627c2374cf90faac30e19d736eef3832..4718a7ca50a7cb453087be08dffa1d503283fd21 100644 --- a/lldb/source/Target/ProcessTrace.cpp +++ b/lldb/source/Target/ProcessTrace.cpp @@ -36,15 +36,16 @@ ProcessSP ProcessTrace::CreateInstance(TargetSP target_sp, bool can_connect) { if (can_connect) return nullptr; - return std::make_shared(target_sp, listener_sp); + return std::make_shared(target_sp, listener_sp, *crash_file); } bool ProcessTrace::CanDebug(TargetSP target_sp, bool plugin_specified_by_name) { return plugin_specified_by_name; } -ProcessTrace::ProcessTrace(TargetSP target_sp, ListenerSP listener_sp) - : PostMortemProcess(target_sp, listener_sp) {} +ProcessTrace::ProcessTrace(TargetSP target_sp, ListenerSP listener_sp, + const FileSpec &core_file) + : PostMortemProcess(target_sp, listener_sp, core_file) {} ProcessTrace::~ProcessTrace() { Clear(); diff --git a/lldb/source/Target/Statistics.cpp b/lldb/source/Target/Statistics.cpp index 4699710035b2d6185031e4a75cdc08bbc7ce9f2e..ec0a4c84692deaccb833a66931bceede929fb7dc 100644 --- a/lldb/source/Target/Statistics.cpp +++ b/lldb/source/Target/Statistics.cpp @@ -12,6 +12,7 @@ #include "lldb/Core/Module.h" #include "lldb/Interpreter/CommandInterpreter.h" #include "lldb/Symbol/SymbolFile.h" +#include "lldb/Target/DynamicLoader.h" #include "lldb/Target/Process.h" #include "lldb/Target/Target.h" #include "lldb/Target/UnixSignals.h" @@ -100,60 +101,94 @@ llvm::json::Value ConstStringStats::ToJSON() const { return obj; } -json::Value TargetStats::ToJSON(Target &target) { - CollectStats(target); +json::Value +TargetStats::ToJSON(Target &target, + const lldb_private::StatisticsOptions &options) { + json::Object target_metrics_json; + ProcessSP process_sp = target.GetProcessSP(); + const bool summary_only = options.summary_only; + if (!summary_only) { + CollectStats(target); - json::Array json_module_uuid_array; - for (auto module_identifier : m_module_identifiers) - json_module_uuid_array.emplace_back(module_identifier); + json::Array json_module_uuid_array; + for (auto module_identifier : m_module_identifiers) + json_module_uuid_array.emplace_back(module_identifier); - json::Object target_metrics_json{ - {m_expr_eval.name, m_expr_eval.ToJSON()}, - {m_frame_var.name, m_frame_var.ToJSON()}, - {"moduleIdentifiers", std::move(json_module_uuid_array)}}; + target_metrics_json.try_emplace(m_expr_eval.name, m_expr_eval.ToJSON()); + target_metrics_json.try_emplace(m_frame_var.name, m_frame_var.ToJSON()); + target_metrics_json.try_emplace("moduleIdentifiers", + std::move(json_module_uuid_array)); - if (m_launch_or_attach_time && m_first_private_stop_time) { - double elapsed_time = - elapsed(*m_launch_or_attach_time, *m_first_private_stop_time); - target_metrics_json.try_emplace("launchOrAttachTime", elapsed_time); - } - if (m_launch_or_attach_time && m_first_public_stop_time) { - double elapsed_time = - elapsed(*m_launch_or_attach_time, *m_first_public_stop_time); - target_metrics_json.try_emplace("firstStopTime", elapsed_time); + if (m_launch_or_attach_time && m_first_private_stop_time) { + double elapsed_time = + elapsed(*m_launch_or_attach_time, *m_first_private_stop_time); + target_metrics_json.try_emplace("launchOrAttachTime", elapsed_time); + } + if (m_launch_or_attach_time && m_first_public_stop_time) { + double elapsed_time = + elapsed(*m_launch_or_attach_time, *m_first_public_stop_time); + target_metrics_json.try_emplace("firstStopTime", elapsed_time); + } + target_metrics_json.try_emplace("targetCreateTime", + m_create_time.get().count()); + + json::Array breakpoints_array; + double totalBreakpointResolveTime = 0.0; + // Report both the normal breakpoint list and the internal breakpoint list. + for (int i = 0; i < 2; ++i) { + BreakpointList &breakpoints = target.GetBreakpointList(i == 1); + std::unique_lock lock; + breakpoints.GetListMutex(lock); + size_t num_breakpoints = breakpoints.GetSize(); + for (size_t i = 0; i < num_breakpoints; i++) { + Breakpoint *bp = breakpoints.GetBreakpointAtIndex(i).get(); + breakpoints_array.push_back(bp->GetStatistics()); + totalBreakpointResolveTime += bp->GetResolveTime().count(); + } + } + target_metrics_json.try_emplace("breakpoints", + std::move(breakpoints_array)); + target_metrics_json.try_emplace("totalBreakpointResolveTime", + totalBreakpointResolveTime); + + if (process_sp) { + UnixSignalsSP unix_signals_sp = process_sp->GetUnixSignals(); + if (unix_signals_sp) + target_metrics_json.try_emplace( + "signals", unix_signals_sp->GetHitCountStatistics()); + } } - target_metrics_json.try_emplace("targetCreateTime", - m_create_time.get().count()); - - json::Array breakpoints_array; - double totalBreakpointResolveTime = 0.0; - // Rport both the normal breakpoint list and the internal breakpoint list. - for (int i = 0; i < 2; ++i) { - BreakpointList &breakpoints = target.GetBreakpointList(i == 1); + + // Counting "totalSharedLibraryEventHitCount" from breakpoints of kind + // "shared-library-event". + { + uint32_t shared_library_event_breakpoint_hit_count = 0; + // The "shared-library-event" is only found in the internal breakpoint list. + BreakpointList &breakpoints = target.GetBreakpointList(/* internal */ true); std::unique_lock lock; breakpoints.GetListMutex(lock); size_t num_breakpoints = breakpoints.GetSize(); for (size_t i = 0; i < num_breakpoints; i++) { Breakpoint *bp = breakpoints.GetBreakpointAtIndex(i).get(); - breakpoints_array.push_back(bp->GetStatistics()); - totalBreakpointResolveTime += bp->GetResolveTime().count(); + if (strcmp(bp->GetBreakpointKind(), "shared-library-event") == 0) + shared_library_event_breakpoint_hit_count += bp->GetHitCount(); } + + target_metrics_json.try_emplace("totalSharedLibraryEventHitCount", + shared_library_event_breakpoint_hit_count); } - ProcessSP process_sp = target.GetProcessSP(); if (process_sp) { - UnixSignalsSP unix_signals_sp = process_sp->GetUnixSignals(); - if (unix_signals_sp) - target_metrics_json.try_emplace("signals", - unix_signals_sp->GetHitCountStatistics()); uint32_t stop_id = process_sp->GetStopID(); target_metrics_json.try_emplace("stopCount", stop_id); - } - target_metrics_json.try_emplace("breakpoints", std::move(breakpoints_array)); - target_metrics_json.try_emplace("totalBreakpointResolveTime", - totalBreakpointResolveTime); - target_metrics_json.try_emplace("sourceMapDeduceCount", m_source_map_deduce_count); + llvm::StringRef dyld_plugin_name; + if (process_sp->GetDynamicLoader()) + dyld_plugin_name = process_sp->GetDynamicLoader()->GetPluginName(); + target_metrics_json.try_emplace("dyldPluginName", dyld_plugin_name); + } + target_metrics_json.try_emplace("sourceMapDeduceCount", + m_source_map_deduce_count); return target_metrics_json; } @@ -184,8 +219,12 @@ void TargetStats::IncreaseSourceMapDeduceCount() { bool DebuggerStats::g_collecting_stats = false; -llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, - Target *target) { +llvm::json::Value DebuggerStats::ReportStatistics( + Debugger &debugger, Target *target, + const lldb_private::StatisticsOptions &options) { + + const bool summary_only = options.summary_only; + json::Array json_targets; json::Array json_modules; double symtab_parse_time = 0.0; @@ -197,12 +236,7 @@ llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, uint32_t debug_index_loaded = 0; uint32_t debug_index_saved = 0; uint64_t debug_info_size = 0; - if (target) { - json_targets.emplace_back(target->ReportStatistics()); - } else { - for (const auto &target : debugger.GetTargetList().Targets()) - json_targets.emplace_back(target->ReportStatistics()); - } + std::vector modules; std::lock_guard guard( Module::GetAllocationModuleCollectionMutex()); @@ -215,15 +249,6 @@ llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, for (size_t image_idx = 0; image_idx < num_modules; ++image_idx) { Module *module = Module::GetAllocatedModuleAtIndex(image_idx); ModuleStats module_stat; - module_stat.identifier = (intptr_t)module; - module_stat.path = module->GetFileSpec().GetPath(); - if (ConstString object_name = module->GetObjectName()) { - module_stat.path.append(1, '('); - module_stat.path.append(object_name.GetStringRef().str()); - module_stat.path.append(1, ')'); - } - module_stat.uuid = module->GetUUID().GetAsString(); - module_stat.triple = module->GetArchitecture().GetTriple().str(); module_stat.symtab_parse_time = module->GetSymtabParseTime().get().count(); module_stat.symtab_index_time = module->GetSymtabIndexTime().get().count(); Symtab *symtab = module->GetSymtab(); @@ -237,13 +262,14 @@ llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, } SymbolFile *sym_file = module->GetSymbolFile(); if (sym_file) { - - if (sym_file->GetObjectFile() != module->GetObjectFile()) - module_stat.symfile_path = - sym_file->GetObjectFile()->GetFileSpec().GetPath(); - module_stat.debug_index_time = sym_file->GetDebugInfoIndexTime().count(); - module_stat.debug_parse_time = sym_file->GetDebugInfoParseTime().count(); - module_stat.debug_info_size = sym_file->GetDebugInfoSize(); + if (!summary_only) { + if (sym_file->GetObjectFile() != module->GetObjectFile()) + module_stat.symfile_path = + sym_file->GetObjectFile()->GetFileSpec().GetPath(); + ModuleList symbol_modules = sym_file->GetDebugInfoModules(); + for (const auto &symbol_module : symbol_modules.Modules()) + module_stat.symfile_modules.push_back((intptr_t)symbol_module.get()); + } module_stat.debug_info_index_loaded_from_cache = sym_file->GetDebugInfoIndexWasLoadedFromCache(); if (module_stat.debug_info_index_loaded_from_cache) @@ -252,9 +278,9 @@ llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, sym_file->GetDebugInfoIndexWasSavedToCache(); if (module_stat.debug_info_index_saved_to_cache) ++debug_index_saved; - ModuleList symbol_modules = sym_file->GetDebugInfoModules(); - for (const auto &symbol_module: symbol_modules.Modules()) - module_stat.symfile_modules.push_back((intptr_t)symbol_module.get()); + module_stat.debug_index_time = sym_file->GetDebugInfoIndexTime().count(); + module_stat.debug_parse_time = sym_file->GetDebugInfoParseTime().count(); + module_stat.debug_info_size = sym_file->GetDebugInfoSize(); module_stat.symtab_stripped = module->GetObjectFile()->IsStripped(); if (module_stat.symtab_stripped) ++num_stripped_modules; @@ -284,21 +310,21 @@ llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, if (module_stat.debug_info_had_incomplete_types) ++num_modules_with_incomplete_types; - json_modules.emplace_back(module_stat.ToJSON()); + if (!summary_only) { + module_stat.identifier = (intptr_t)module; + module_stat.path = module->GetFileSpec().GetPath(); + if (ConstString object_name = module->GetObjectName()) { + module_stat.path.append(1, '('); + module_stat.path.append(object_name.GetStringRef().str()); + module_stat.path.append(1, ')'); + } + module_stat.uuid = module->GetUUID().GetAsString(); + module_stat.triple = module->GetArchitecture().GetTriple().str(); + json_modules.emplace_back(module_stat.ToJSON()); + } } - ConstStringStats const_string_stats; - json::Object json_memory{ - {"strings", const_string_stats.ToJSON()}, - }; - - json::Value cmd_stats = debugger.GetCommandInterpreter().GetStatistics(); - json::Object global_stats{ - {"targets", std::move(json_targets)}, - {"modules", std::move(json_modules)}, - {"memory", std::move(json_memory)}, - {"commands", std::move(cmd_stats)}, {"totalSymbolTableParseTime", symtab_parse_time}, {"totalSymbolTableIndexTime", symtab_index_time}, {"totalSymbolTablesLoadedFromCache", symtabs_loaded}, @@ -316,5 +342,25 @@ llvm::json::Value DebuggerStats::ReportStatistics(Debugger &debugger, {"totalDebugInfoEnabled", num_debug_info_enabled_modules}, {"totalSymbolTableStripped", num_stripped_modules}, }; + + if (target) { + json_targets.emplace_back(target->ReportStatistics(options)); + } else { + for (const auto &target : debugger.GetTargetList().Targets()) + json_targets.emplace_back(target->ReportStatistics(options)); + } + global_stats.try_emplace("targets", std::move(json_targets)); + + if (!summary_only) { + ConstStringStats const_string_stats; + json::Object json_memory{ + {"strings", const_string_stats.ToJSON()}, + }; + json::Value cmd_stats = debugger.GetCommandInterpreter().GetStatistics(); + global_stats.try_emplace("modules", std::move(json_modules)); + global_stats.try_emplace("memory", std::move(json_memory)); + global_stats.try_emplace("commands", std::move(cmd_stats)); + } + return std::move(global_stats); } diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index e969340fdf1eba5c54c3bfe233d8c05e98fd6572..e17bfcb5d5e2ad53d138d8329e71a82ed9987825 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -4962,4 +4962,7 @@ std::recursive_mutex &Target::GetAPIMutex() { } /// Get metrics associated with this target in JSON format. -llvm::json::Value Target::ReportStatistics() { return m_stats.ToJSON(*this); } +llvm::json::Value +Target::ReportStatistics(const lldb_private::StatisticsOptions &options) { + return m_stats.ToJSON(*this, options); +} diff --git a/lldb/source/Target/TargetList.cpp b/lldb/source/Target/TargetList.cpp index 121b6253d2a59d227c1778406b889a4a7e3b1ddf..b5d308739d0facdbd78d8d3eb9eec5bdd17d0d44 100644 --- a/lldb/source/Target/TargetList.cpp +++ b/lldb/source/Target/TargetList.cpp @@ -532,9 +532,13 @@ void TargetList::SetSelectedTarget(uint32_t index) { } void TargetList::SetSelectedTarget(const TargetSP &target_sp) { - std::lock_guard guard(m_target_list_mutex); - auto it = llvm::find(m_target_list, target_sp); - SetSelectedTargetInternal(std::distance(m_target_list.begin(), it)); + // Don't allow an invalid target shared pointer or a target that has been + // destroyed to become the selected target. + if (target_sp && target_sp->IsValid()) { + std::lock_guard guard(m_target_list_mutex); + auto it = llvm::find(m_target_list, target_sp); + SetSelectedTargetInternal(std::distance(m_target_list.begin(), it)); + } } lldb::TargetSP TargetList::GetSelectedTarget() { diff --git a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py index d6907075820ece75d6eb9a77ed66fbeb090ed2ae..7ec5e0d7c8309baba983889c15d56e534b26cb60 100644 --- a/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py +++ b/lldb/test/API/functionalities/postmortem/elf-core/TestLinuxCore.py @@ -633,6 +633,17 @@ class LinuxCoreTestCase(TestBase): self.expect("register read --all") + def test_get_core_file_api(self): + """ + Test SBProcess::GetCoreFile() API can successfully get the core file. + """ + core_file_name = "linux-x86_64.core" + target = self.dbg.CreateTarget("linux-x86_64.out") + process = target.LoadCore(core_file_name) + self.assertTrue(process, PROCESS_IS_VALID) + self.assertEqual(process.GetCoreFile().GetFilename(), core_file_name) + self.dbg.DeleteTarget(target) + def check_memory_regions(self, process, region_count): region_list = process.GetMemoryRegions() self.assertEqual(region_list.GetSize(), region_count) diff --git a/lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py b/lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py index fe55922fe4c3130703cc5c9e0ca3d4d916f373f6..457a2022fe4b8fe10125905669f46e28a9a7b577 100644 --- a/lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py +++ b/lldb/test/API/functionalities/stats_api/TestStatisticsAPI.py @@ -16,7 +16,10 @@ class TestStatsAPI(TestBase): """ self.build() exe = self.getBuildArtifact("a.out") - target = self.dbg.CreateTarget(exe) + # Launch a process and break + (target, process, thread, bkpt) = lldbutil.run_to_source_breakpoint( + self, "break here", lldb.SBFileSpec("main.c") + ) # Test enabling/disabling stats self.assertFalse(target.GetCollectingStats()) @@ -74,6 +77,24 @@ class TestStatsAPI(TestBase): 'Make sure the "failures" key in in "frameVariable" dictionary"', ) + # Test statistics summary. + stats_options = lldb.SBStatisticsOptions() + stats_options.SetSummaryOnly(True) + stats_summary = target.GetStatistics(stats_options) + stream_summary = lldb.SBStream() + stats_summary.GetAsJSON(stream_summary) + debug_stats_summary = json.loads(stream_summary.GetData()) + self.assertNotIn("modules", debug_stats_summary) + self.assertNotIn("memory", debug_stats_summary) + self.assertNotIn("commands", debug_stats_summary) + + # Summary values should be the same as in full statistics. + # Except the parse time on Mac OS X is not deterministic. + for key, value in debug_stats_summary.items(): + self.assertIn(key, debug_stats) + if key != "targets" and not key.endswith("Time"): + self.assertEqual(debug_stats[key], value) + def test_command_stats_api(self): """ Test GetCommandInterpreter::GetStatistics() API. diff --git a/lldb/test/API/functionalities/stats_api/main.c b/lldb/test/API/functionalities/stats_api/main.c index 03b2213bb9a36c589f8e5342bea47a7d63b28573..02fea2eb75ff0de532b9f5d8dd33f355966c010f 100644 --- a/lldb/test/API/functionalities/stats_api/main.c +++ b/lldb/test/API/functionalities/stats_api/main.c @@ -1,3 +1,3 @@ int main(void) { - return 0; + return 0; // break here } diff --git a/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py b/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py index f7ceb47c0b6159eae5d9604ccd6f8ba6ae2c59cb..c5e161497e6281dc9ac18381b80fc39021f5d4f9 100644 --- a/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py +++ b/lldb/test/API/functionalities/watchpoint/large-watchpoint/TestLargeWatchpoint.py @@ -25,11 +25,6 @@ class UnalignedWatchpointTestCase(TestBase): @skipIf(archs=no_match(["arm64", "arm64e", "aarch64"])) @skipUnlessDarwin - # LWP_TODO: until debugserver advertises that it supports - # MASK watchpoints, this test can't be enabled, lldb won't - # try to send watchpoints larger than 8 bytes. - @skipIfDarwin - # debugserver only gained the ability to watch larger regions # with this patch. @skipIfOutOfTreeDebugserver diff --git a/lldb/test/API/python_api/target/TestTargetAPI.py b/lldb/test/API/python_api/target/TestTargetAPI.py index c8e1904428c8aa05ad1d913213de28582094e60a..63d34340a8836ec0c3e1073c75d169123c55683a 100644 --- a/lldb/test/API/python_api/target/TestTargetAPI.py +++ b/lldb/test/API/python_api/target/TestTargetAPI.py @@ -526,3 +526,9 @@ class TargetAPITestCase(TestBase): target.IsLoaded(module), "Running the target should " "have loaded its modules.", ) + + @no_debug_info_test + def test_setting_selected_target_with_invalid_target(self): + """Make sure we don't crash when trying to select invalid target.""" + target = lldb.SBTarget() + self.dbg.SetSelectedTarget(target) diff --git a/lldb/tools/debugserver/source/RNBRemote.cpp b/lldb/tools/debugserver/source/RNBRemote.cpp index 224ed033fc4217918d6bec9b92238d1a04e1f8df..feea4c914ec5368b13e22143fd43b628c151ae26 100644 --- a/lldb/tools/debugserver/source/RNBRemote.cpp +++ b/lldb/tools/debugserver/source/RNBRemote.cpp @@ -3557,10 +3557,10 @@ static bool GetProcessNameFrom_vAttach(const char *&p, rnb_err_t RNBRemote::HandlePacket_qSupported(const char *p) { uint32_t max_packet_size = 128 * 1024; // 128KBytes is a reasonable max packet // size--debugger can always use less - char buf[256]; - snprintf(buf, sizeof(buf), - "qXfer:features:read+;PacketSize=%x;qEcho+;native-signals+", - max_packet_size); + std::stringstream reply; + reply << "qXfer:features:read+;PacketSize=" << std::hex << max_packet_size + << ";"; + reply << "qEcho+;native-signals+;"; bool enable_compression = false; (void)enable_compression; @@ -3574,15 +3574,17 @@ rnb_err_t RNBRemote::HandlePacket_qSupported(const char *p) { #endif if (enable_compression) { - strcat(buf, ";SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;" - "DefaultCompressionMinSize="); - char numbuf[16]; - snprintf(numbuf, sizeof(numbuf), "%zu", m_compression_minsize); - numbuf[sizeof(numbuf) - 1] = '\0'; - strcat(buf, numbuf); - } + reply << "SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;"; + } - return SendPacket(buf); +#if (defined(__arm64__) || defined(__aarch64__)) + reply << "SupportedWatchpointTypes=aarch64-mask,aarch64-bas;"; +#endif +#if defined(__x86_64__) + reply << "SupportedWatchpointTypes=x86_64;"; +#endif + + return SendPacket(reply.str().c_str()); } static bool process_does_not_exist (nub_process_t pid) { @@ -4478,46 +4480,25 @@ rnb_err_t RNBRemote::HandlePacket_SetEnableAsyncProfiling(const char *p) { return SendPacket("OK"); } -// QEnableCompression:type:;minsize:; +// QEnableCompression:type:; // // type: must be a type previously reported by the qXfer:features: // SupportedCompressions list -// -// minsize: is optional; by default the qXfer:features: -// DefaultCompressionMinSize value is used -// debugserver may have a better idea of what a good minimum packet size to -// compress is than lldb. rnb_err_t RNBRemote::HandlePacket_QEnableCompression(const char *p) { p += sizeof("QEnableCompression:") - 1; - size_t new_compression_minsize = m_compression_minsize; - const char *new_compression_minsize_str = strstr(p, "minsize:"); - if (new_compression_minsize_str) { - new_compression_minsize_str += strlen("minsize:"); - errno = 0; - new_compression_minsize = strtoul(new_compression_minsize_str, NULL, 10); - if (errno != 0 || new_compression_minsize == ULONG_MAX) { - new_compression_minsize = m_compression_minsize; - } - } - if (strstr(p, "type:zlib-deflate;") != nullptr) { EnableCompressionNextSendPacket(compression_types::zlib_deflate); - m_compression_minsize = new_compression_minsize; return SendPacket("OK"); } else if (strstr(p, "type:lz4;") != nullptr) { EnableCompressionNextSendPacket(compression_types::lz4); - m_compression_minsize = new_compression_minsize; return SendPacket("OK"); } else if (strstr(p, "type:lzma;") != nullptr) { EnableCompressionNextSendPacket(compression_types::lzma); - m_compression_minsize = new_compression_minsize; return SendPacket("OK"); } else if (strstr(p, "type:lzfse;") != nullptr) { EnableCompressionNextSendPacket(compression_types::lzfse); - m_compression_minsize = new_compression_minsize; return SendPacket("OK"); } diff --git a/lldb/unittests/Core/CMakeLists.txt b/lldb/unittests/Core/CMakeLists.txt index b3cddd150635b15f51c69d4e74545747d01faadc..d40c357e3f463be477b58236114bba42c77e2cd1 100644 --- a/lldb/unittests/Core/CMakeLists.txt +++ b/lldb/unittests/Core/CMakeLists.txt @@ -7,6 +7,7 @@ add_lldb_unittest(LLDBCoreTests FormatEntityTest.cpp MangledTest.cpp ModuleSpecTest.cpp + ProgressReportTest.cpp RichManglingContextTest.cpp SourceLocationSpecTest.cpp SourceManagerTest.cpp diff --git a/lldb/unittests/Core/DiagnosticEventTest.cpp b/lldb/unittests/Core/DiagnosticEventTest.cpp index bca8f3789955abb302ce8971c58ae8418890bb29..d06f164e87e70c0bfa6230ff73b08f2a5a32f8fe 100644 --- a/lldb/unittests/Core/DiagnosticEventTest.cpp +++ b/lldb/unittests/Core/DiagnosticEventTest.cpp @@ -11,6 +11,7 @@ #include "Plugins/Platform/MacOSX/PlatformMacOSX.h" #include "Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h" #include "TestingSupport/SubsystemRAII.h" +#include "TestingSupport/TestUtilities.h" #include "lldb/Core/Debugger.h" #include "lldb/Core/DebuggerEvents.h" #include "lldb/Host/FileSystem.h" @@ -26,8 +27,6 @@ using namespace lldb_private::repro; static const constexpr std::chrono::seconds TIMEOUT(0); static const constexpr size_t DEBUGGERS = 3; -static std::once_flag debugger_initialize_flag; - namespace { class DiagnosticEventTest : public ::testing::Test { public: @@ -35,7 +34,7 @@ public: FileSystem::Initialize(); HostInfo::Initialize(); PlatformMacOSX::Initialize(); - std::call_once(debugger_initialize_flag, + std::call_once(TestUtilities::g_debugger_initialize_flag, []() { Debugger::Initialize(nullptr); }); ArchSpec arch("x86_64-apple-macosx-"); Platform::SetHostPlatform( diff --git a/lldb/unittests/Core/ProgressReportTest.cpp b/lldb/unittests/Core/ProgressReportTest.cpp new file mode 100644 index 0000000000000000000000000000000000000000..559f3ef1ae46bfea1e34151c36508333a7a49a84 --- /dev/null +++ b/lldb/unittests/Core/ProgressReportTest.cpp @@ -0,0 +1,128 @@ +//===-- ProgressReportTest.cpp --------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "Plugins/Platform/MacOSX/PlatformMacOSX.h" +#include "Plugins/Platform/MacOSX/PlatformRemoteMacOSX.h" +#include "TestingSupport/SubsystemRAII.h" +#include "TestingSupport/TestUtilities.h" +#include "lldb/Core/Debugger.h" +#include "lldb/Core/Progress.h" +#include "lldb/Host/FileSystem.h" +#include "lldb/Host/HostInfo.h" +#include "lldb/Utility/Listener.h" +#include "gtest/gtest.h" +#include +#include + +using namespace lldb; +using namespace lldb_private; + +class ProgressReportTest : public ::testing::Test { + SubsystemRAII subsystems; + + // The debugger's initialization function can't be called with no arguments + // so calling it using SubsystemRAII will cause the test build to fail as + // SubsystemRAII will call Initialize with no arguments. As such we set it up + // here the usual way. + void SetUp() override { + std::call_once(TestUtilities::g_debugger_initialize_flag, + []() { Debugger::Initialize(nullptr); }); + }; +}; + +TEST_F(ProgressReportTest, TestReportCreation) { + std::chrono::milliseconds timeout(100); + + // Set up the debugger, make sure that was done properly. + ArchSpec arch("x86_64-apple-macosx-"); + Platform::SetHostPlatform(PlatformRemoteMacOSX::CreateInstance(true, &arch)); + + DebuggerSP debugger_sp = Debugger::CreateInstance(); + ASSERT_TRUE(debugger_sp); + + // Get the debugger's broadcaster. + Broadcaster &broadcaster = debugger_sp->GetBroadcaster(); + + // Create a listener, make sure it can receive events and that it's + // listening to the correct broadcast bit. + ListenerSP listener_sp = Listener::MakeListener("progress-listener"); + + listener_sp->StartListeningForEvents(&broadcaster, + Debugger::eBroadcastBitProgress); + EXPECT_TRUE( + broadcaster.EventTypeHasListeners(Debugger::eBroadcastBitProgress)); + + EventSP event_sp; + const ProgressEventData *data; + + // Scope this for RAII on the progress objects. + // Create progress reports and check that their respective events for having + // started and ended are broadcasted. + { + Progress progress1("Progress report 1", "Starting report 1"); + Progress progress2("Progress report 2", "Starting report 2"); + Progress progress3("Progress report 3", "Starting report 3"); + } + + // Start popping events from the queue, they should have been recevied + // in this order: + // Starting progress: 1, 2, 3 + // Ending progress: 3, 2, 1 + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetDetails(), "Starting report 1"); + ASSERT_FALSE(data->IsFinite()); + ASSERT_FALSE(data->GetCompleted()); + ASSERT_EQ(data->GetTotal(), Progress::kNonDeterministicTotal); + ASSERT_EQ(data->GetMessage(), "Progress report 1: Starting report 1"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetDetails(), "Starting report 2"); + ASSERT_FALSE(data->IsFinite()); + ASSERT_FALSE(data->GetCompleted()); + ASSERT_EQ(data->GetTotal(), Progress::kNonDeterministicTotal); + ASSERT_EQ(data->GetMessage(), "Progress report 2: Starting report 2"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + ASSERT_EQ(data->GetDetails(), "Starting report 3"); + ASSERT_FALSE(data->IsFinite()); + ASSERT_FALSE(data->GetCompleted()); + ASSERT_EQ(data->GetTotal(), Progress::kNonDeterministicTotal); + ASSERT_EQ(data->GetMessage(), "Progress report 3: Starting report 3"); + + // Progress report objects should be destroyed at this point so + // get each report from the queue and check that they've been + // destroyed in reverse order. + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetTitle(), "Progress report 3"); + ASSERT_TRUE(data->GetCompleted()); + ASSERT_FALSE(data->IsFinite()); + ASSERT_EQ(data->GetMessage(), "Progress report 3: Starting report 3"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetTitle(), "Progress report 2"); + ASSERT_TRUE(data->GetCompleted()); + ASSERT_FALSE(data->IsFinite()); + ASSERT_EQ(data->GetMessage(), "Progress report 2: Starting report 2"); + + EXPECT_TRUE(listener_sp->GetEvent(event_sp, timeout)); + data = ProgressEventData::GetEventDataFromEvent(event_sp.get()); + + ASSERT_EQ(data->GetTitle(), "Progress report 1"); + ASSERT_TRUE(data->GetCompleted()); + ASSERT_FALSE(data->IsFinite()); + ASSERT_EQ(data->GetMessage(), "Progress report 1: Starting report 1"); +} diff --git a/lldb/unittests/TestingSupport/TestUtilities.cpp b/lldb/unittests/TestingSupport/TestUtilities.cpp index 9e5523e4875479a11f7bb1c2e888404b7a74826a..efdc6c5eb234a722820061ebc16bc1b19437e214 100644 --- a/lldb/unittests/TestingSupport/TestUtilities.cpp +++ b/lldb/unittests/TestingSupport/TestUtilities.cpp @@ -19,6 +19,7 @@ using namespace lldb_private; extern const char *TestMainArgv0; +std::once_flag TestUtilities::g_debugger_initialize_flag; std::string lldb_private::GetInputFilePath(const llvm::Twine &name) { llvm::SmallString<128> result = llvm::sys::path::parent_path(TestMainArgv0); llvm::sys::fs::make_absolute(result); diff --git a/lldb/unittests/TestingSupport/TestUtilities.h b/lldb/unittests/TestingSupport/TestUtilities.h index 811c4c1521269b733e0cf2319eeb9a533d0ec3e1..7d040d64db8d8bc31258edca51caa4278098e847 100644 --- a/lldb/unittests/TestingSupport/TestUtilities.h +++ b/lldb/unittests/TestingSupport/TestUtilities.h @@ -31,6 +31,11 @@ namespace lldb_private { std::string GetInputFilePath(const llvm::Twine &name); +class TestUtilities { +public: + static std::once_flag g_debugger_initialize_flag; +}; + class TestFile { public: static llvm::Expected fromYaml(llvm::StringRef Yaml); @@ -51,6 +56,6 @@ private: std::string Buffer; }; -} +} // namespace lldb_private #endif diff --git a/llvm/docs/CommandGuide/llvm-mca.rst b/llvm/docs/CommandGuide/llvm-mca.rst index 324e1e6e7bd11e53e5cb99f5c48cbf453630f56a..eae5e1406b899efbdc9da4eff210b71c5c3ed3dd 100644 --- a/llvm/docs/CommandGuide/llvm-mca.rst +++ b/llvm/docs/CommandGuide/llvm-mca.rst @@ -350,7 +350,7 @@ an InstrumentRegion does not need a comment to end the region. Comments that are prefixed with `LLVM-MCA-` but do not correspond to a valid `INSTRUMENT_TYPE` for the target cause an error, except for `BEGIN` and `END`, since those correspond to AnalysisRegions. Comments -that do not start with `LLVM-MCA-` are ignored by :program `llvm-mca`. +that do not start with `LLVM-MCA-` are ignored by :program:`llvm-mca`. An instruction (a MCInst) is added to an InstrumentRegion R only if its location is in range [R.RangeStart, R.RangeEnd]. @@ -908,6 +908,7 @@ process instructions. * Retire (Instruction is retired; writes are architecturally committed). The in-order pipeline implements the following sequence of stages: + * InOrderIssue (Instruction is issued to the processor pipelines). * Retire (Instruction is retired; writes are architecturally committed). diff --git a/llvm/docs/CommandGuide/llvm-objcopy.rst b/llvm/docs/CommandGuide/llvm-objcopy.rst index 6e13cd94b92fdafd68cf2cee732cca91de577986..42d11fa17ccac0c1e0bf67e767076cbebeda4edd 100644 --- a/llvm/docs/CommandGuide/llvm-objcopy.rst +++ b/llvm/docs/CommandGuide/llvm-objcopy.rst @@ -117,6 +117,11 @@ multiple file formats. If specified, symbol and section names specified by other switches are treated as extended POSIX regular expression patterns. +.. option:: --remove-symbol-prefix + +Remove ```` from the start of every symbol name. No-op for symbols that do +not start with ````. + .. option:: --remove-section
, -R Remove the specified section from the output. Can be specified multiple times diff --git a/llvm/docs/Passes.rst b/llvm/docs/Passes.rst index 0d0353ed6b611b5906f8a89aa8e1784c7a52d508..2edad5cd3c881abeb2783fab20f6b63da568132c 100644 --- a/llvm/docs/Passes.rst +++ b/llvm/docs/Passes.rst @@ -7,6 +7,9 @@ LLVM's Analysis and Transform Passes Introduction ============ +.. warning:: This document is not updated frequently, and the list of passes + is most likely incomplete. It is possible to list passes known by the opt + tool using ``opt -print-passes``. This document serves as a high level summary of the optimization features that LLVM provides. Optimizations are implemented as Passes that traverse some @@ -193,15 +196,12 @@ memory operations it depends on. It builds on alias analysis information, and tries to provide a lazy, caching interface to a common kind of alias information query. -``module-debuginfo``: Decodes module-level debug info ------------------------------------------------------ +``print``: Decodes module-level debug info +------------------------------------------------------------ -This pass decodes the debug info metadata in a module and prints in a +This pass decodes the debug info metadata in a module and prints it to standard output in a (sufficiently-prepared-) human-readable form. -For example, run this pass from ``opt`` along with the ``-analyze`` option, and -it'll print to standard output. - ``postdomtree``: Post-Dominator Tree Construction ------------------------------------------------- @@ -228,18 +228,18 @@ standard error in a human-readable form. ``print-cfg-sccs``: Print SCCs of each function CFG --------------------------------------------------- -This pass, only available in ``opt``, printsthe SCCs of each function CFG to +This pass, only available in ``opt``, prints the SCCs of each function CFG to standard error in a human-readable fom. -``print-function``: Print function to stderr --------------------------------------------- +``function(print)``: Print function to stderr +--------------------------------------------- The ``PrintFunctionPass`` class is designed to be pipelined with other ``FunctionPasses``, and prints out the functions of the module as they are processed. -``print-module``: Print module to stderr ----------------------------------------- +``module(print)``: Print module to stderr +----------------------------------------- This pass simply prints out the entire module when it is executed. @@ -924,17 +924,8 @@ code size or making it harder to reverse engineer code. ``strip-dead-debug-info``: Strip debug info for unused symbols -------------------------------------------------------------- -.. FIXME: this description is the same as for -strip - -performs code stripping. this transformation can delete: - -* names for virtual registers -* symbols for internal globals and functions -* debug information - -note that this transformation makes code much less readable, so it should only -be used in situations where the strip utility would be used, such as reducing -code size or making it harder to reverse engineer code. +Performs code stripping. Similar to strip, but only strips debug info for +unused symbols. ``strip-dead-prototypes``: Strip Unused Function Prototypes ----------------------------------------------------------- @@ -947,32 +938,13 @@ functions). ``strip-debug-declare``: Strip all ``llvm.dbg.declare`` intrinsics ------------------------------------------------------------------ -.. FIXME: this description is the same as for -strip - -This pass implements code stripping. Specifically, it can delete: - -#. names for virtual registers -#. symbols for internal globals and functions -#. debug information - -Note that this transformation makes code much less readable, so it should only -be used in situations where the 'strip' utility would be used, such as reducing -code size or making it harder to reverse engineer code. +Performs code stripping. Similar to strip, but only strips +``llvm.dbg.declare`` intrinsics. ``strip-nondebug``: Strip all symbols, except dbg symbols, from a module ------------------------------------------------------------------------ -.. FIXME: this description is the same as for -strip - -This pass implements code stripping. Specifically, it can delete: - -#. names for virtual registers -#. symbols for internal globals and functions -#. debug information - -Note that this transformation makes code much less readable, so it should only -be used in situations where the 'strip' utility would be used, such as reducing -code size or making it harder to reverse engineer code. +Performs code stripping. Similar to strip, but dbg info is preserved. ``tailcallelim``: Tail Call Elimination --------------------------------------- diff --git a/llvm/docs/RISCVUsage.rst b/llvm/docs/RISCVUsage.rst index c9e99c9b98e371497c51c206fddbe49f6b6ac472..2233c90e91b195b54a24ddd2bbaffde3449f0793 100644 --- a/llvm/docs/RISCVUsage.rst +++ b/llvm/docs/RISCVUsage.rst @@ -21,10 +21,10 @@ and ISA extensions with pragmatic variances. The most recent specification can be found at: https://github.com/riscv/riscv-isa-manual/releases/. `The official RISC-V International specification page -`_. is also worth checking, but +`__. is also worth checking, but tends to significantly lag the specifications linked above. Make sure to check the `wiki for not yet integrated extensions -`_ and note +`__ and note that in addition, we sometimes carry support for extensions that have not yet been ratified (these will be marked as experimental - see below) and support various vendor-specific extensions (see below). @@ -234,7 +234,7 @@ Supported .. _riscv-profiles-extensions-note: ``Za128rs``, ``Za64rs``, ``Zic64b``, ``Ziccamoa``, ``Ziccif``, ``Zicclsm``, ``Ziccrse``, ``Shcounterenvw``, ``Shgatpa``, ``Shtvala``, ``Shvsatpa``, ``Shvstvala``, ``Shvstvecd``, ``Ssccptr``, ``Sscounterenw``, ``Ssstateen``, ``Ssstrict``, ``Sstvala``, ``Sstvecd``, ``Ssu64xl``, ``Svade``, ``Svbare`` - These extensions are defined as part of the `RISC-V Profiles specification `_. They do not introduce any new features themselves, but instead describe existing hardware features. + These extensions are defined as part of the `RISC-V Profiles specification `__. They do not introduce any new features themselves, but instead describe existing hardware features. Experimental Extensions ======================= @@ -244,19 +244,22 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised. ``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm`` - LLVM implements the `v0.8.1 draft specification ` + LLVM implements the `v0.8.1 draft specification `__. + +``experimental-ssqosid`` + LLVM implements assembler support for the `v1.0-rc1 draft specification `_. ``experimental-zabha`` - LLVM implements assembler support for the `v1.0-rc1 draft specification `_. + LLVM implements assembler support for the `v1.0-rc1 draft specification `__. ``experimental-zacas`` - LLVM implements the `1.0-rc1 draft specification `_. + LLVM implements the `1.0-rc1 draft specification `__. ``experimental-zalasr`` - LLVM implements the `0.0.5 draft specification `_. + LLVM implements the `0.0.5 draft specification `__. ``experimental-zfbfmin``, ``experimental-zvfbfmin``, ``experimental-zvfbfwma`` - LLVM implements assembler support for the `1.0.0-rc2 specification `_. + LLVM implements assembler support for the `1.0.0-rc2 specification `__. ``experimental-zicfilp``, ``experimental-zicfiss`` LLVM implements the `0.4 draft specification `__. @@ -280,71 +283,71 @@ Vendor Extensions Vendor extensions are extensions which are not standardized by RISC-V International, and are instead defined by a hardware vendor. The term vendor extension roughly parallels the definition of a `non-standard` extension from Section 1.3 of the Volume I: RISC-V Unprivileged ISA specification. In particular, we expect to eventually accept both `custom` extensions and `non-conforming` extensions. -Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISCV sync calls for discussion. For a general idea of the factors likely to be considered, please see the `Clang documentation `_. +Inclusion of a vendor extension will be considered on a case by case basis. All proposals should be brought to the bi-weekly RISCV sync calls for discussion. For a general idea of the factors likely to be considered, please see the `Clang documentation `__. -It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions `_. Exceptions to this naming will need to be strongly motivated. +It is our intention to follow the naming conventions described in `riscv-non-isa/riscv-toolchain-conventions `__. Exceptions to this naming will need to be strongly motivated. The current vendor extensions supported are: ``XTHeadBa`` - LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadBa (address-generation) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadBb`` - LLVM implements `the THeadBb (basic bit-manipulation) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadBb (basic bit-manipulation) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadBs`` - LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadBs (single-bit operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadCondMov`` - LLVM implements `the THeadCondMov (conditional move) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadCondMov (conditional move) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadCmo`` - LLVM implements `the THeadCmo (cache management operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadCmo (cache management operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadFMemIdx`` - LLVM implements `the THeadFMemIdx (indexed memory operations for floating point) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadFMemIdx (indexed memory operations for floating point) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTheadMac`` - LLVM implements `the XTheadMac (multiply-accumulate instructions) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the XTheadMac (multiply-accumulate instructions) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadMemIdx`` - LLVM implements `the THeadMemIdx (indexed memory operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadMemIdx (indexed memory operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadMemPair`` - LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadMemPair (two-GPR memory operations) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadSync`` - LLVM implements `the THeadSync (multi-core synchronization instructions) vendor-defined instructions specified in `_ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. + LLVM implements `the THeadSync (multi-core synchronization instructions) vendor-defined instructions specified in `__ by T-HEAD of Alibaba. Instructions are prefixed with `th.` as described in the specification. ``XTHeadVdot`` - LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `_ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above. + LLVM implements `version 1.0.0 of the THeadV-family custom instructions specification `__ by T-HEAD of Alibaba. All instructions are prefixed with `th.` as described in the specification, and the riscv-toolchain-convention document linked above. ``XVentanaCondOps`` - LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `_ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. + LLVM implements `version 1.0.0 of the VTx-family custom instructions specification `__ by Ventana Micro Systems. All instructions are prefixed with `vt.` as described in the specification, and the riscv-toolchain-convention document linked above. These instructions are only available for riscv64 at this time. ``XSfvcp`` - LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification `_ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. + LLVM implements `version 1.0.0 of the SiFive Vector Coprocessor Interface (VCIX) Software Specification `__ by SiFive. All instructions are prefixed with `sf.vc.` as described in the specification, and the riscv-toolchain-convention document linked above. ``XCVbitmanip`` - LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. + LLVM implements `version 1.0.0 of the CORE-V Bit Manipulation custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. ``XCVelw`` - LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V Event load custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. ``XCVmac`` - LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V Multiply-Accumulate (MAC) custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.mac` as described in the specification. These instructions are only available for riscv32 at this time. ``XCVmem`` - LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V Post-Increment load and stores custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. ``XCValu`` - LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification `_ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the Core-V ALU custom instructions specification `__ by Core-V. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. ``XCVsimd`` - LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. + LLVM implements `version 1.0.0 of the CORE-V SIMD custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. ``XCVbi`` - LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification `_ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. + LLVM implements `version 1.0.0 of the CORE-V immediate branching custom instructions specification `__ by OpenHW Group. All instructions are prefixed with `cv.` as described in the specification. These instructions are only available for riscv32 at this time. Experimental C Intrinsics ========================= diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 6ac83961d7cf01dab03b024717f91c9dd83a59ae..05d8eea3add41989a94cd4713ea41dfdc065defc 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -102,6 +102,7 @@ Changes to the RISC-V Backend names in the RISC-V profiles specification are now recognised. * Codegen support was added for the Zimop (May-Be-Operations) extension. * The experimental Ssnpm, Smnpm, Smmpm, Sspm, and Supm 0.8.1 Pointer Masking extensions are supported. +* The experimental Ssqosid extension is supported. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/docs/TableGen/BackEnds.rst b/llvm/docs/TableGen/BackEnds.rst index 742fea51bcf32be5a80dca4db64c09f6092634b5..901cb989a5edba3df3b07fc0d76bd86cd4c836c5 100644 --- a/llvm/docs/TableGen/BackEnds.rst +++ b/llvm/docs/TableGen/BackEnds.rst @@ -817,7 +817,9 @@ The table entries in ``ATable`` are sorted in order by ``Val1``, and within each of those values, by ``Val2``. This allows a binary search of the table, which is performed in the lookup function by ``std::lower_bound``. The lookup function returns a reference to the found table entry, or the null -pointer if no entry is found. +pointer if no entry is found. If the table has a single primary key field +which is integral and densely numbered, a direct lookup is generated rather +than a binary search. This example includes a field whose type TableGen cannot deduce. The ``Kind`` field uses the enumerated type ``CEnum`` defined above. To inform TableGen diff --git a/llvm/docs/UserGuides.rst b/llvm/docs/UserGuides.rst index 9ae0d360111542d34481c71c064d00dcc0f24f87..6fb61f2d3a25268d9bd0cd9ef9b1fd63553185a8 100644 --- a/llvm/docs/UserGuides.rst +++ b/llvm/docs/UserGuides.rst @@ -123,13 +123,14 @@ LLVM Builds and Distributions Optimizations ------------- -:doc:`WritingAnLLVMPass` - Information on how to write LLVM transformations and analyses. - :doc:`WritingAnLLVMNewPMPass` Information on how to write LLVM transformations under the new pass manager. +:doc:`WritingAnLLVMPass` + Information on how to write LLVM transformations and analyses under the + legacy pass manager. + :doc:`Passes` A list of optimizations and analyses implemented in LLVM. diff --git a/llvm/docs/WritingAnLLVMNewPMPass.rst b/llvm/docs/WritingAnLLVMNewPMPass.rst index 799863c7864ecc102ce6ac2a3de1eb9fa93dfa88..ea30d637347f16b46ce622c9d4c9a501f9d33951 100644 --- a/llvm/docs/WritingAnLLVMNewPMPass.rst +++ b/llvm/docs/WritingAnLLVMNewPMPass.rst @@ -10,6 +10,11 @@ Writing an LLVM Pass Introduction --- What is a pass? ================================ +.. warning:: + This document deals with the new pass manager. LLVM uses the legacy pass + manager for the codegen pipeline. For more details, see + :doc:`WritingAnLLVMPass` and :doc:`NewPassManager`. + The LLVM pass framework is an important part of the LLVM system, because LLVM passes are where most of the interesting parts of the compiler exist. Passes perform the transformations and optimizations that make up the compiler, they @@ -29,11 +34,6 @@ We start by showing you how to construct a pass, from setting up the build, creating the pass, to executing and testing it. Looking at existing passes is always a great way to learn details. -.. warning:: - This document deals with the new pass manager. LLVM uses the legacy pass - manager for the codegen pipeline. For more details, see - :doc:`WritingAnLLVMPass` and :doc:`NewPassManager`. - Quick Start --- Writing hello world =================================== diff --git a/llvm/docs/WritingAnLLVMPass.rst b/llvm/docs/WritingAnLLVMPass.rst index b94669917c9071119e2058268d32c8cd277f7f7c..a3602e7fbc31fda69aeb1c9d929806c094635419 100644 --- a/llvm/docs/WritingAnLLVMPass.rst +++ b/llvm/docs/WritingAnLLVMPass.rst @@ -1,6 +1,6 @@ -==================== -Writing an LLVM Pass -==================== +======================================== +Writing an LLVM Pass (legacy PM version) +======================================== .. program:: opt @@ -10,6 +10,13 @@ Writing an LLVM Pass Introduction --- What is a pass? ================================ +.. warning:: + This document deals with the legacy pass manager. LLVM uses the new pass + manager for the optimization pipeline (the codegen pipeline + still uses the legacy pass manager), which has its own way of defining + passes. For more details, see :doc:`WritingAnLLVMNewPMPass` and + :doc:`NewPassManager`. + The LLVM Pass Framework is an important part of the LLVM system, because LLVM passes are where most of the interesting parts of the compiler exist. Passes perform the transformations and optimizations that make up the compiler, they @@ -34,13 +41,6 @@ We start by showing you how to construct a pass, everything from setting up the code, to compiling, loading, and executing it. After the basics are down, more advanced features are discussed. -.. warning:: - This document deals with the legacy pass manager. LLVM uses the new pass - manager for the optimization pipeline (the codegen pipeline - still uses the legacy pass manager), which has its own way of defining - passes. For more details, see :doc:`WritingAnLLVMNewPMPass` and - :doc:`NewPassManager`. - Quick Start --- Writing hello world =================================== @@ -224,6 +224,13 @@ can have them) to be useful. Running a pass with ``opt`` --------------------------- +.. warning:: + This document deals with the legacy pass manager. The :program:`opt` tool no + longer supports running legacy passes (except for certain hardcoded backend + passes and when using bugpoint). So the examples below for loading and + running legacy passes using :program:`opt` are deprecated and no longer + guaranteed to work. + Now that you have a brand new shiny shared object file, we can use the :program:`opt` command to run an LLVM program through your pass. Because you registered your pass with ``RegisterPass``, you will be able to use the diff --git a/llvm/include/llvm/Analysis/TypeMetadataUtils.h b/llvm/include/llvm/Analysis/TypeMetadataUtils.h index dab67aad1ab0eb7f4f7dd8f48e6b1e6e1dbfaa2d..8894945c28d94790b92d108aee34c7d9b603e56d 100644 --- a/llvm/include/llvm/Analysis/TypeMetadataUtils.h +++ b/llvm/include/llvm/Analysis/TypeMetadataUtils.h @@ -15,6 +15,7 @@ #define LLVM_ANALYSIS_TYPEMETADATAUTILS_H #include +#include namespace llvm { @@ -24,6 +25,7 @@ class CallInst; class Constant; class Function; class DominatorTree; +class GlobalVariable; class Instruction; class Module; @@ -77,6 +79,13 @@ void findDevirtualizableCallsForTypeCheckedLoad( Constant *getPointerAtOffset(Constant *I, uint64_t Offset, Module &M, Constant *TopLevelGlobal = nullptr); +/// Given a vtable and a specified offset, returns the function and the trivial +/// pointer at the specified offset in pair iff the pointer at the specified +/// offset is a function or an alias to a function. Returns a pair of nullptr +/// otherwise. +std::pair +getFunctionAtVTableOffset(GlobalVariable *GV, uint64_t Offset, Module &M); + /// Finds the same "relative pointer" pattern as described above, where the /// target is `F`, and replaces the entire pattern with a constant zero. void replaceRelativePointerUsersWithZero(Function *F); diff --git a/llvm/include/llvm/BinaryFormat/XCOFF.h b/llvm/include/llvm/BinaryFormat/XCOFF.h index 19d44a5ac57f122cbd30f2b8dabcd0b7f3c75e95..bbcd8a4f29ae912e60764d448db305803d1545c2 100644 --- a/llvm/include/llvm/BinaryFormat/XCOFF.h +++ b/llvm/include/llvm/BinaryFormat/XCOFF.h @@ -27,6 +27,7 @@ namespace XCOFF { constexpr size_t FileNamePadSize = 6; constexpr size_t NameSize = 8; +constexpr size_t AuxFileEntNameSize = 14; constexpr size_t FileHeaderSize32 = 20; constexpr size_t FileHeaderSize64 = 24; constexpr size_t AuxFileHeaderSize32 = 72; diff --git a/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h b/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h new file mode 100644 index 0000000000000000000000000000000000000000..b9fe7cfccf9a390919844eea74c6ebdba743c433 --- /dev/null +++ b/llvm/include/llvm/CodeGen/DeadMachineInstructionElim.h @@ -0,0 +1,25 @@ +//===- llvm/CodeGen/DeadMachineInstructionElim.h ----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CODEGEN_DEADMACHINEINSTRUCTIONELIM_H +#define LLVM_CODEGEN_DEADMACHINEINSTRUCTIONELIM_H + +#include "llvm/CodeGen/MachinePassManager.h" + +namespace llvm { + +class DeadMachineInstructionElimPass + : public MachinePassInfoMixin { +public: + PreservedAnalyses run(MachineFunction &MF, + MachineFunctionAnalysisManager &MFAM); +}; + +} // namespace llvm + +#endif // LLVM_CODEGEN_DEADMACHINEINSTRUCTIONELIM_H diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index 90428a622b4176de043bfe90f41344ec20088391..10eeafdd09a8ee938740ddc572ea92af2a7cc257 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -814,6 +814,12 @@ public: /// Combine selects. bool matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo); + /// Combine ands, + bool matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo); + + /// Combine ors, + bool matchOr(MachineInstr &MI, BuildFnTy &MatchInfo); + private: /// Checks for legality of an indexed variant of \p LdSt. bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const; @@ -919,6 +925,12 @@ private: bool AllowUndefs); std::optional getConstantOrConstantSplatVector(Register Src); + + /// Fold (icmp Pred1 V1, C1) && (icmp Pred2 V2, C2) + /// or (icmp Pred1 V1, C1) || (icmp Pred2 V2, C2) + /// into a single comparison using range-based reasoning. + bool tryFoldAndOrOrICmpsUsingRanges(GLogicalBinOp *Logic, + BuildFnTy &MatchInfo); }; } // namespace llvm diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h index eabbe688a1c7643abd6a06be9a8c2d9fb36ae3bf..f5a6528d10a973db6c806a7005ee1ec5d6adf4ad 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GenericMachineInstrs.h @@ -592,6 +592,134 @@ public: } }; +/// Represents a binary operation, i.e, x = y op z. +class GBinOp : public GenericMachineInstr { +public: + Register getLHSReg() const { return getReg(1); } + Register getRHSReg() const { return getReg(2); } + + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + // Integer. + case TargetOpcode::G_ADD: + case TargetOpcode::G_SUB: + case TargetOpcode::G_MUL: + case TargetOpcode::G_SDIV: + case TargetOpcode::G_UDIV: + case TargetOpcode::G_SREM: + case TargetOpcode::G_UREM: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: + // Floating point. + case TargetOpcode::G_FMINNUM: + case TargetOpcode::G_FMAXNUM: + case TargetOpcode::G_FMINNUM_IEEE: + case TargetOpcode::G_FMAXNUM_IEEE: + case TargetOpcode::G_FMINIMUM: + case TargetOpcode::G_FMAXIMUM: + case TargetOpcode::G_FADD: + case TargetOpcode::G_FSUB: + case TargetOpcode::G_FMUL: + case TargetOpcode::G_FDIV: + case TargetOpcode::G_FPOW: + // Logical. + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: + return true; + default: + return false; + } + }; +}; + +/// Represents an integer binary operation. +class GIntBinOp : public GBinOp { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_ADD: + case TargetOpcode::G_SUB: + case TargetOpcode::G_MUL: + case TargetOpcode::G_SDIV: + case TargetOpcode::G_UDIV: + case TargetOpcode::G_SREM: + case TargetOpcode::G_UREM: + case TargetOpcode::G_SMIN: + case TargetOpcode::G_SMAX: + case TargetOpcode::G_UMIN: + case TargetOpcode::G_UMAX: + return true; + default: + return false; + } + }; +}; + +/// Represents a floating point binary operation. +class GFBinOp : public GBinOp { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_FMINNUM: + case TargetOpcode::G_FMAXNUM: + case TargetOpcode::G_FMINNUM_IEEE: + case TargetOpcode::G_FMAXNUM_IEEE: + case TargetOpcode::G_FMINIMUM: + case TargetOpcode::G_FMAXIMUM: + case TargetOpcode::G_FADD: + case TargetOpcode::G_FSUB: + case TargetOpcode::G_FMUL: + case TargetOpcode::G_FDIV: + case TargetOpcode::G_FPOW: + return true; + default: + return false; + } + }; +}; + +/// Represents a logical binary operation. +class GLogicalBinOp : public GBinOp { +public: + static bool classof(const MachineInstr *MI) { + switch (MI->getOpcode()) { + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: + return true; + default: + return false; + } + }; +}; + +/// Represents an integer addition. +class GAdd : public GIntBinOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_ADD; + }; +}; + +/// Represents a logical and. +class GAnd : public GLogicalBinOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_AND; + }; +}; + +/// Represents a logical or. +class GOr : public GLogicalBinOp { +public: + static bool classof(const MachineInstr *MI) { + return MI->getOpcode() == TargetOpcode::G_OR; + }; +}; + } // namespace llvm #endif // LLVM_CODEGEN_GLOBALISEL_GENERICMACHINEINSTRS_H diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index bf02911e19351dbabac77e70a1556dd42fc92444..f8900f3434ccaae3a4caa7060410b26d39b858f7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -343,10 +343,13 @@ Register getFunctionLiveInPhysReg(MachineFunction &MF, const TargetRegisterClass &RC, const DebugLoc &DL, LLT RegTy = LLT()); -/// Return the least common multiple type of \p OrigTy and \p TargetTy, by changing the -/// number of vector elements or scalar bitwidth. The intent is a +/// Return the least common multiple type of \p OrigTy and \p TargetTy, by +/// changing the number of vector elements or scalar bitwidth. The intent is a /// G_MERGE_VALUES, G_BUILD_VECTOR, or G_CONCAT_VECTORS can be constructed from -/// \p OrigTy elements, and unmerged into \p TargetTy +/// \p OrigTy elements, and unmerged into \p TargetTy. It is an error to call +/// this function where one argument is a fixed vector and the other is a +/// scalable vector, since it is illegal to build a G_{MERGE|UNMERGE}_VALUES +/// between fixed and scalable vectors. LLVM_READNONE LLT getLCMType(LLT OrigTy, LLT TargetTy); @@ -365,7 +368,10 @@ LLT getCoverTy(LLT OrigTy, LLT TargetTy); /// If these are vectors with different element types, this will try to produce /// a vector with a compatible total size, but the element type of \p OrigTy. If /// this can't be satisfied, this will produce a scalar smaller than the -/// original vector elements. +/// original vector elements. It is an error to call this function where +/// one argument is a fixed vector and the other is a scalable vector, since it +/// is illegal to build a G_{MERGE|UNMERGE}_VALUES between fixed and scalable +/// vectors. /// /// In the worst case, this returns LLT::scalar(1) LLVM_READNONE diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index 05c9b14a423cda1ab9156bcfd52310c59ba7589c..a2c90c9f42f38f63025d09eafb3d2f9bd73f1c9b 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -1423,9 +1423,7 @@ template <> struct GraphTraits> : } }; -class MachineFunctionAnalysisManager; -void verifyMachineFunction(MachineFunctionAnalysisManager *, - const std::string &Banner, +void verifyMachineFunction(const std::string &Banner, const MachineFunction &MF); } // end namespace llvm diff --git a/llvm/include/llvm/CodeGen/MachineModuleInfo.h b/llvm/include/llvm/CodeGen/MachineModuleInfo.h index 4f0ada3d7e17aa1944aaed0adc0a13d21e8b325e..5f66d1ada0d082d5207417fbf807b9cba5a21643 100644 --- a/llvm/include/llvm/CodeGen/MachineModuleInfo.h +++ b/llvm/include/llvm/CodeGen/MachineModuleInfo.h @@ -192,12 +192,6 @@ public: unsigned getCurrentCallSite() { return CurCallSite; } /// \} - - // MMI owes MCContext. It should never be invalidated. - bool invalidate(Module &, const PreservedAnalyses &, - ModuleAnalysisManager::Invalidator &) { - return false; - } }; // End class MachineModuleInfo class MachineModuleInfoWrapperPass : public ImmutablePass { @@ -218,21 +212,37 @@ public: const MachineModuleInfo &getMMI() const { return MMI; } }; -/// An analysis that produces \c MachineInfo for a module. +/// An analysis that produces \c MachineModuleInfo for a module. +/// This does not produce its own MachineModuleInfo because we need a consistent +/// MachineModuleInfo to keep ownership of MachineFunctions regardless of +/// analysis invalidation/clearing. So something outside the analysis +/// infrastructure must own the MachineModuleInfo. class MachineModuleAnalysis : public AnalysisInfoMixin { friend AnalysisInfoMixin; static AnalysisKey Key; - const LLVMTargetMachine *TM; + MachineModuleInfo &MMI; public: - /// Provide the result type for this analysis pass. - using Result = MachineModuleInfo; + class Result { + MachineModuleInfo &MMI; + Result(MachineModuleInfo &MMI) : MMI(MMI) {} + friend class MachineModuleAnalysis; + + public: + MachineModuleInfo &getMMI() { return MMI; } + + // MMI owes MCContext. It should never be invalidated. + bool invalidate(Module &, const PreservedAnalyses &, + ModuleAnalysisManager::Invalidator &) { + return false; + } + }; - MachineModuleAnalysis(const LLVMTargetMachine *TM) : TM(TM) {} + MachineModuleAnalysis(MachineModuleInfo &MMI) : MMI(MMI) {} /// Run the analysis pass and produce machine module information. - MachineModuleInfo run(Module &M, ModuleAnalysisManager &); + Result run(Module &M, ModuleAnalysisManager &); }; } // end namespace llvm diff --git a/llvm/include/llvm/CodeGen/Register.h b/llvm/include/llvm/CodeGen/Register.h index e1456f81d4670f9b3d4c9d15ca056a41738572e3..fb4e55121113270dd6df4f4cdcb7ddc2d511f9e8 100644 --- a/llvm/include/llvm/CodeGen/Register.h +++ b/llvm/include/llvm/CodeGen/Register.h @@ -36,7 +36,7 @@ public: static_assert(std::numeric_limits::max() >= 0xFFFFFFFF, "Reg isn't large enough to hold full range."); - /// isStackSlot - Sometimes it is useful the be able to store a non-negative + /// isStackSlot - Sometimes it is useful to be able to store a non-negative /// frame index in a variable that normally holds a register. isStackSlot() /// returns true if Reg is in the range used for stack slots. /// diff --git a/llvm/include/llvm/CodeGen/ValueTypes.td b/llvm/include/llvm/CodeGen/ValueTypes.td index 25f0d385259db491d46d55c8c2af65cc0b71f4f6..55baaf867e73256098912961a96109c1cc7d7fd7 100644 --- a/llvm/include/llvm/CodeGen/ValueTypes.td +++ b/llvm/include/llvm/CodeGen/ValueTypes.td @@ -6,9 +6,8 @@ // //===----------------------------------------------------------------------===// // -// Value types - These values correspond to the register types defined in the -// MachineValueTypes.h file. If you update anything here, you must update it -// there as well! +// ValueTypes.td - list of ValueType instances supported by the the +// CodeGen infrastructure. // //===----------------------------------------------------------------------===// diff --git a/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h b/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h index e3ded00b573f75eb9bdc4f732c066ad2e2245e80..79309251c3b6bdfaa6c8a177dccf61900ed8ab9a 100644 --- a/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h +++ b/llvm/include/llvm/Frontend/Offloading/OffloadWrapper.h @@ -20,10 +20,13 @@ using EntryArrayTy = std::pair; /// \param EntryArray Optional pair pointing to the `__start` and `__stop` /// symbols holding the `__tgt_offload_entry` array. /// \param Suffix An optional suffix appended to the emitted symbols. +/// \param Relocatable Indicate if we need to change the offloading section to +/// create a relocatable object. llvm::Error wrapOpenMPBinaries(llvm::Module &M, llvm::ArrayRef> Images, EntryArrayTy EntryArray, - llvm::StringRef Suffix = ""); + llvm::StringRef Suffix = "", + bool Relocatable = false); /// Wraps the input fatbinary image into the module \p M as global symbols and /// registers the images with the CUDA runtime. diff --git a/llvm/include/llvm/IR/Instruction.h b/llvm/include/llvm/IR/Instruction.h index a785a43a0f11a6e9bc694e84c865769eb1b275c9..cd814e21be1ae1e2bc1a2e909f5b387647528fc1 100644 --- a/llvm/include/llvm/IR/Instruction.h +++ b/llvm/include/llvm/IR/Instruction.h @@ -90,6 +90,12 @@ public: /// Returns true if any DPValues are attached to this instruction. bool hasDbgValues() const; + /// Transfer any DPValues on the position \p It onto this instruction, + /// by simply adopting the sequence of DPValues (which is efficient) if + /// possible, by merging two sequences otherwise. + void adoptDbgValues(BasicBlock *BB, InstListType::iterator It, + bool InsertAtHead); + /// Erase any DPValues attached to this instruction. void dropDbgValues(); diff --git a/llvm/include/llvm/IR/ModuleSummaryIndex.h b/llvm/include/llvm/IR/ModuleSummaryIndex.h index 395c9e332eb8f353a7b24bc50a43e8eea3641609..d5ff15063671d8376130f18bb9135a3881fdd688 100644 --- a/llvm/include/llvm/IR/ModuleSummaryIndex.h +++ b/llvm/include/llvm/IR/ModuleSummaryIndex.h @@ -1377,7 +1377,7 @@ private: // Temporary map while building StackIds list. Clear when index is completely // built via releaseTemporaryMemory. - std::map StackIdToIndex; + DenseMap StackIdToIndex; // YAML I/O support. friend yaml::MappingTraits; diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index 878079c4fe4e8eaf19313fb42b580fe45b006189..3155e7dc38b64a60093964440ed51b800da0a858 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -1711,6 +1711,34 @@ m_BitCast(const OpTy &Op) { return CastOperator_match(Op); } +template struct ElementWiseBitCast_match { + Op_t Op; + + ElementWiseBitCast_match(const Op_t &OpMatch) : Op(OpMatch) {} + + template bool match(OpTy *V) { + BitCastInst *I = dyn_cast(V); + if (!I) + return false; + Type *SrcType = I->getSrcTy(); + Type *DstType = I->getType(); + // Make sure the bitcast doesn't change between scalar and vector and + // doesn't change the number of vector elements. + if (SrcType->isVectorTy() != DstType->isVectorTy()) + return false; + if (VectorType *SrcVecTy = dyn_cast(SrcType); + SrcVecTy && SrcVecTy->getElementCount() != + cast(DstType)->getElementCount()) + return false; + return Op.match(I->getOperand(0)); + } +}; + +template +inline ElementWiseBitCast_match m_ElementWiseBitCast(const OpTy &Op) { + return ElementWiseBitCast_match(Op); +} + /// Matches PtrToInt. template inline CastOperator_match diff --git a/llvm/include/llvm/MC/MCAssembler.h b/llvm/include/llvm/MC/MCAssembler.h index 5ae5f6d7093858588195f2c147c53514fab31bca..3fa5f2fe655e86e5f0b98a35eb6a65366e415c02 100644 --- a/llvm/include/llvm/MC/MCAssembler.h +++ b/llvm/include/llvm/MC/MCAssembler.h @@ -133,6 +133,8 @@ private: /// List of declared file names std::vector> FileNames; + // Optional compiler version. + std::string CompilerVersion; MCDwarfLineTableParams LTParams; @@ -486,6 +488,12 @@ public: FileNames.emplace_back(std::string(FileName), Symbols.size()); } + void setCompilerVersion(std::string CompilerVers) { + if (CompilerVersion.empty()) + CompilerVersion = std::move(CompilerVers); + } + StringRef getCompilerVersion() { return CompilerVersion; } + /// Write the necessary bundle padding to \p OS. /// Expects a fragment \p F containing instructions and its size \p FSize. void writeFragmentPadding(raw_ostream &OS, const MCEncodedFragment &F, diff --git a/llvm/include/llvm/ObjCopy/CommonConfig.h b/llvm/include/llvm/ObjCopy/CommonConfig.h index 386c20aec184ded4738c4d79c230b111ddf8db95..0d9320ec2efd71b81901b8762325ee7d57f5f50d 100644 --- a/llvm/include/llvm/ObjCopy/CommonConfig.h +++ b/llvm/include/llvm/ObjCopy/CommonConfig.h @@ -218,6 +218,7 @@ struct CommonConfig { uint64_t PadTo = 0; StringRef SplitDWO; StringRef SymbolsPrefix; + StringRef SymbolsPrefixRemove; StringRef AllocSectionsPrefix; DiscardType DiscardMode = DiscardType::None; diff --git a/llvm/include/llvm/Object/COFFImportFile.h b/llvm/include/llvm/Object/COFFImportFile.h index edc836ff0348cb2f16d51459de01e0a5bd43f535..45a4a795fd19034b606b6490ab28c0e20f40812b 100644 --- a/llvm/include/llvm/Object/COFFImportFile.h +++ b/llvm/include/llvm/Object/COFFImportFile.h @@ -66,6 +66,7 @@ public: uint16_t getMachine() const { return getCOFFImportHeader()->Machine; } StringRef getFileFormatName() const; + StringRef getExportName() const; private: bool isData() const { diff --git a/llvm/include/llvm/Passes/CodeGenPassBuilder.h b/llvm/include/llvm/Passes/CodeGenPassBuilder.h index 2c8073ad551b74131a368289285703173f853723..fa6dbd4a49730eca4764496ae29caf384279c4c5 100644 --- a/llvm/include/llvm/Passes/CodeGenPassBuilder.h +++ b/llvm/include/llvm/Passes/CodeGenPassBuilder.h @@ -26,6 +26,7 @@ #include "llvm/CodeGen/AssignmentTrackingAnalysis.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/CodeGenPrepare.h" +#include "llvm/CodeGen/DeadMachineInstructionElim.h" #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandMemCmp.h" #include "llvm/CodeGen/ExpandReductions.h" @@ -78,14 +79,14 @@ namespace llvm { // FIXME: Dummy target independent passes definitions that have not yet been // ported to new pass manager. Once they do, remove these. -#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) \ struct PASS_NAME : public PassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ PreservedAnalyses run(Function &, FunctionAnalysisManager &) { \ return PreservedAnalyses::all(); \ } \ }; -#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) \ struct PASS_NAME : public MachinePassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ Error run(Module &, MachineFunctionAnalysisManager &) { \ @@ -96,7 +97,7 @@ namespace llvm { llvm_unreachable("this api is to make new PM api happy"); \ } \ }; -#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) \ struct PASS_NAME : public MachinePassInfoMixin { \ template PASS_NAME(Ts &&...) {} \ PreservedAnalyses run(MachineFunction &, \ @@ -104,17 +105,6 @@ namespace llvm { return PreservedAnalyses::all(); \ } \ }; -#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - struct PASS_NAME : public AnalysisInfoMixin { \ - template PASS_NAME(Ts &&...) {} \ - using Result = struct {}; \ - template \ - Result run(IRUnitT &, AnalysisManagerT &, ExtraArgTs &&...) { \ - return {}; \ - } \ - static AnalysisKey Key; \ - }; #include "llvm/Passes/MachinePassRegistry.def" /// This class provides access to building LLVM's passes. @@ -150,7 +140,6 @@ public: void registerModuleAnalyses(ModuleAnalysisManager &) const; void registerFunctionAnalyses(FunctionAnalysisManager &) const; void registerMachineFunctionAnalyses(MachineFunctionAnalysisManager &) const; - std::pair getPassNameFromLegacyName(StringRef) const; void registerAnalyses(MachineFunctionAnalysisManager &MFAM) const { registerModuleAnalyses(*MFAM.MAM); @@ -608,8 +597,8 @@ static inline AAManager registerAAAnalyses() { template void CodeGenPassBuilder::registerModuleAnalyses( ModuleAnalysisManager &MAM) const { -#define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - MAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); +#define MODULE_ANALYSIS(NAME, CREATE_PASS) \ + MAM.registerPass([&] { return CREATE_PASS; }); #include "MachinePassRegistry.def" derived().registerTargetAnalysis(MAM); } @@ -619,8 +608,8 @@ void CodeGenPassBuilder::registerFunctionAnalyses( FunctionAnalysisManager &FAM) const { FAM.registerPass([this] { return registerAAAnalyses(); }); -#define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - FAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); +#define FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + FAM.registerPass([&] { return CREATE_PASS; }); #include "MachinePassRegistry.def" derived().registerTargetAnalysis(FAM); } @@ -628,59 +617,12 @@ void CodeGenPassBuilder::registerFunctionAnalyses( template void CodeGenPassBuilder::registerMachineFunctionAnalyses( MachineFunctionAnalysisManager &MFAM) const { -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - MFAM.registerPass([&] { return PASS_NAME CONSTRUCTOR; }); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + MFAM.registerPass([&] { return CREATE_PASS; }); #include "MachinePassRegistry.def" derived().registerTargetAnalysis(MFAM); } -// FIXME: For new PM, use pass name directly in commandline seems good. -// Translate stringfied pass name to its old commandline name. Returns the -// matching legacy name and a boolean value indicating if the pass is a machine -// pass. -template -std::pair -CodeGenPassBuilder::getPassNameFromLegacyName(StringRef Name) const { - std::pair Ret; - if (Name.empty()) - return Ret; - -#define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define DUMMY_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, false}; -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - if (Name == NAME) \ - Ret = {#PASS_NAME, true}; -#include "llvm/Passes/MachinePassRegistry.def" - - if (Ret.first.empty()) - Ret = derived().getTargetPassNameFromLegacyName(Name); - - if (Ret.first.empty()) - report_fatal_error(Twine('\"') + Twine(Name) + - Twine("\" pass could not be found.")); - - return Ret; -} - template void CodeGenPassBuilder::addISelPasses(AddIRPass &addPass) const { derived().addGlobalMergePass(addPass); diff --git a/llvm/include/llvm/Passes/MachinePassRegistry.def b/llvm/include/llvm/Passes/MachinePassRegistry.def index e311682a56192e98ffa5b13fa9e42957898d82d7..d8972080beeb0d982769a9183a5dc9638c2810b1 100644 --- a/llvm/include/llvm/Passes/MachinePassRegistry.def +++ b/llvm/include/llvm/Passes/MachinePassRegistry.def @@ -14,84 +14,82 @@ // NOTE: NO INCLUDE GUARD DESIRED! #ifndef MODULE_ANALYSIS -#define MODULE_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) +#define MODULE_ANALYSIS(NAME, CREATE_PASS) #endif -MODULE_ANALYSIS("collector-metadata", CollectorMetadataAnalysis, ()) -MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) +MODULE_ANALYSIS("collector-metadata", CollectorMetadataAnalysis()) +MODULE_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) #undef MODULE_ANALYSIS #ifndef MODULE_PASS -#define MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define MODULE_PASS(NAME, CREATE_PASS) #endif -MODULE_PASS("global-merge", GlobalMergePass, (TM, GlobalMergeOptions())) -MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass, ()) -MODULE_PASS("lower-emutls", LowerEmuTLSPass, ()) -MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass, ()) -MODULE_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass, ()) +MODULE_PASS("global-merge", GlobalMergePass(TM, GlobalMergeOptions())) +MODULE_PASS("jmc-instrumenter", JMCInstrumenterPass()) +MODULE_PASS("lower-emutls", LowerEmuTLSPass()) +MODULE_PASS("pre-isel-intrinsic-lowering", PreISelIntrinsicLoweringPass()) +MODULE_PASS("shadow-stack-gc-lowering", ShadowStackGCLoweringPass()) #undef MODULE_PASS #ifndef FUNCTION_ANALYSIS -#define FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) +#define FUNCTION_ANALYSIS(NAME, CREATE_PASS) #endif -FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis, ()) -FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, (PIC)) -FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis, ()) -FUNCTION_ANALYSIS("target-ir", TargetIRAnalysis, - (std::move(TM.getTargetIRAnalysis()))) +FUNCTION_ANALYSIS("gc-function", GCFunctionAnalysis()) +FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) +FUNCTION_ANALYSIS("ssp-layout", SSPLayoutAnalysis()) +FUNCTION_ANALYSIS("target-ir", TargetIRAnalysis(std::move(TM.getTargetIRAnalysis()))) #undef FUNCTION_ANALYSIS #ifndef FUNCTION_PASS -#define FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define FUNCTION_PASS(NAME, CREATE_PASS) #endif -FUNCTION_PASS("callbr-prepare", CallBrPreparePass, ()) -FUNCTION_PASS("cfguard", CFGuardPass, ()) -FUNCTION_PASS("codegenprepare", CodeGenPreparePass, (TM)) -FUNCTION_PASS("consthoist", ConstantHoistingPass, ()) -FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass, (TM)) -FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass, (false)) -FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass, (TM)) -FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass, (TM)) -FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass, (TM)) -FUNCTION_PASS("expand-reductions", ExpandReductionsPass, ()) -FUNCTION_PASS("expandvp", ExpandVectorPredicationPass, ()) -FUNCTION_PASS("gc-lowering", GCLoweringPass, ()) -FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass, (TM)) -FUNCTION_PASS("interleaved-access", InterleavedAccessPass, (TM)) -FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass, (TM)) -FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass, ()) -FUNCTION_PASS("lower-invoke", LowerInvokePass, ()) -FUNCTION_PASS("mergeicmps", MergeICmpsPass, ()) -FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass, ()) -FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass, (true)) -FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib, ()) -FUNCTION_PASS("safe-stack", SafeStackPass, (TM)) -FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass, ()) -FUNCTION_PASS("select-optimize", SelectOptimizePass, (TM)) -FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass, (TM)) -FUNCTION_PASS("stack-protector", StackProtectorPass, (TM)) -FUNCTION_PASS("tlshoist", TLSVariableHoistPass, ()) -FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass, ()) -FUNCTION_PASS("verify", VerifierPass, ()) -FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass, ()) -FUNCTION_PASS("win-eh-prepare", WinEHPreparePass, ()) +FUNCTION_PASS("callbr-prepare", CallBrPreparePass()) +FUNCTION_PASS("cfguard", CFGuardPass()) +FUNCTION_PASS("codegenprepare", CodeGenPreparePass(TM)) +FUNCTION_PASS("consthoist", ConstantHoistingPass()) +FUNCTION_PASS("dwarf-eh-prepare", DwarfEHPreparePass(TM)) +FUNCTION_PASS("ee-instrument", EntryExitInstrumenterPass(false)) +FUNCTION_PASS("expand-large-div-rem", ExpandLargeDivRemPass(TM)) +FUNCTION_PASS("expand-large-fp-convert", ExpandLargeFpConvertPass(TM)) +FUNCTION_PASS("expand-memcmp", ExpandMemCmpPass(TM)) +FUNCTION_PASS("expand-reductions", ExpandReductionsPass()) +FUNCTION_PASS("expandvp", ExpandVectorPredicationPass()) +FUNCTION_PASS("gc-lowering", GCLoweringPass()) +FUNCTION_PASS("indirectbr-expand", IndirectBrExpandPass(TM)) +FUNCTION_PASS("interleaved-access", InterleavedAccessPass(TM)) +FUNCTION_PASS("interleaved-load-combine", InterleavedLoadCombinePass(TM)) +FUNCTION_PASS("lower-constant-intrinsics", LowerConstantIntrinsicsPass()) +FUNCTION_PASS("lower-invoke", LowerInvokePass()) +FUNCTION_PASS("mergeicmps", MergeICmpsPass()) +FUNCTION_PASS("partially-inline-libcalls", PartiallyInlineLibCallsPass()) +FUNCTION_PASS("post-inline-ee-instrument", EntryExitInstrumenterPass(true)) +FUNCTION_PASS("replace-with-veclib", ReplaceWithVeclib()) +FUNCTION_PASS("safe-stack", SafeStackPass(TM)) +FUNCTION_PASS("scalarize-masked-mem-intrin", ScalarizeMaskedMemIntrinPass()) +FUNCTION_PASS("select-optimize", SelectOptimizePass(TM)) +FUNCTION_PASS("sjlj-eh-prepare", SjLjEHPreparePass(TM)) +FUNCTION_PASS("stack-protector", StackProtectorPass(TM)) +FUNCTION_PASS("tlshoist", TLSVariableHoistPass()) +FUNCTION_PASS("unreachableblockelim", UnreachableBlockElimPass()) +FUNCTION_PASS("verify", VerifierPass()) +FUNCTION_PASS("wasm-eh-prepare", WasmEHPreparePass()) +FUNCTION_PASS("win-eh-prepare", WinEHPreparePass()) #undef FUNCTION_PASS #ifndef LOOP_PASS -#define LOOP_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define LOOP_PASS(NAME, CREATE_PASS) #endif -LOOP_PASS("loop-reduce", LoopStrengthReducePass, ()) +LOOP_PASS("loop-reduce", LoopStrengthReducePass()) #undef LOOP_PASS #ifndef MACHINE_MODULE_PASS -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define MACHINE_MODULE_PASS(NAME, CREATE_PASS) #endif #undef MACHINE_MODULE_PASS #ifndef MACHINE_FUNCTION_ANALYSIS -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) #endif -MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, - (PIC)) +MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis(PIC)) // LiveVariables currently requires pure SSA form. // FIXME: Once TwoAddressInstruction pass no longer uses kill flags, // LiveVariables can be removed completely, and LiveIntervals can be directly @@ -123,11 +121,12 @@ MACHINE_FUNCTION_ANALYSIS("pass-instrumentation", PassInstrumentationAnalysis, #undef MACHINE_FUNCTION_ANALYSIS #ifndef MACHINE_FUNCTION_PASS -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) #endif -// MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass, ()) -MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass, ()) -MACHINE_FUNCTION_PASS("print", PrintMIRPass, ()) +MACHINE_FUNCTION_PASS("dead-mi-elimination", DeadMachineInstructionElimPass()) +// MACHINE_FUNCTION_PASS("free-machine-function", FreeMachineFunctionPass()) +MACHINE_FUNCTION_PASS("no-op-machine-function", NoOpMachineFunctionPass()) +MACHINE_FUNCTION_PASS("print", PrintMIRPass()) #undef MACHINE_FUNCTION_PASS // After a pass is converted to new pass manager, its entry should be moved from @@ -135,130 +134,100 @@ MACHINE_FUNCTION_PASS("print", PrintMIRPass, ()) // DUMMY_MACHINE_FUNCTION_PASS to MACHINE_FUNCTION_PASS. #ifndef DUMMY_FUNCTION_PASS -#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define DUMMY_FUNCTION_PASS(NAME, PASS_NAME) #endif -DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass, ()) +DUMMY_FUNCTION_PASS("atomic-expand", AtomicExpandPass) #undef DUMMY_FUNCTION_PASS #ifndef DUMMY_MACHINE_MODULE_PASS -#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define DUMMY_MACHINE_MODULE_PASS(NAME, PASS_NAME) #endif -DUMMY_MACHINE_MODULE_PASS("machine-outliner", MachineOutlinerPass, ()) -DUMMY_MACHINE_MODULE_PASS("pseudo-probe-inserter", PseudoProbeInserterPass, ()) -DUMMY_MACHINE_MODULE_PASS("mir-debugify", DebugifyMachineModule, ()) -DUMMY_MACHINE_MODULE_PASS("mir-check-debugify", CheckDebugMachineModulePass, ()) -DUMMY_MACHINE_MODULE_PASS("mir-strip-debug", StripDebugMachineModulePass, - (OnlyDebugified)) +DUMMY_MACHINE_MODULE_PASS("machine-outliner", MachineOutlinerPass) +DUMMY_MACHINE_MODULE_PASS("pseudo-probe-inserter", PseudoProbeInserterPass) +DUMMY_MACHINE_MODULE_PASS("mir-debugify", DebugifyMachineModule) +DUMMY_MACHINE_MODULE_PASS("mir-check-debugify", CheckDebugMachineModulePass) +DUMMY_MACHINE_MODULE_PASS("mir-strip-debug", StripDebugMachineModulePass) #undef DUMMY_MACHINE_MODULE_PASS #ifndef DUMMY_MACHINE_FUNCTION_PASS -#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) +#define DUMMY_MACHINE_FUNCTION_PASS(NAME, PASS_NAME) #endif -DUMMY_MACHINE_FUNCTION_PASS("bbsections-prepare", BasicBlockSectionsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("bbsections-profile-reader", - BasicBlockSectionsProfileReaderPass, (Buf)) -DUMMY_MACHINE_FUNCTION_PASS("block-placement", MachineBlockPlacementPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("block-placement-stats", - MachineBlockPlacementStatsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("branch-folder", BranchFolderPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("dead-mi-elimination", - DeadMachineInstructionElimPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass, ()) -DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", - FixupStatepointCallerSavedPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass, - (File, ProfileFile, P, FS)) -DUMMY_MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("livedebugvalues", LiveDebugValuesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("liveintervals", LiveIntervalsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", - MachineFunctionSplitterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", - MachineUniformityInfoWrapperPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass, - (OS, Banner)) -DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("machineverifier", MachineVerifierPass, (Banner)) -DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass, - (P)) -DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", - MachineUniformityInfoPrinterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-fast", RAFastPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", - RegUsageInfoPropagationPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues", - RemoveRedundantDebugValuesPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", - RenameIndependentSubregsPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass, ()) -DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass, - ()) -DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass, - (Ftor)) -DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass, ()) -DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass, ()) +DUMMY_MACHINE_FUNCTION_PASS("bbsections-prepare", BasicBlockSectionsPass) +DUMMY_MACHINE_FUNCTION_PASS("bbsections-profile-reader", BasicBlockSectionsProfileReaderPass) +DUMMY_MACHINE_FUNCTION_PASS("block-placement", MachineBlockPlacementPass) +DUMMY_MACHINE_FUNCTION_PASS("block-placement-stats", MachineBlockPlacementStatsPass) +DUMMY_MACHINE_FUNCTION_PASS("branch-folder", BranchFolderPass) +DUMMY_MACHINE_FUNCTION_PASS("break-false-deps", BreakFalseDepsPass) +DUMMY_MACHINE_FUNCTION_PASS("cfguard-longjmp", CFGuardLongjmpPass) +DUMMY_MACHINE_FUNCTION_PASS("cfi-fixup", CFIFixupPass) +DUMMY_MACHINE_FUNCTION_PASS("cfi-instr-inserter", CFIInstrInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("detect-dead-lanes", DetectDeadLanesPass) +DUMMY_MACHINE_FUNCTION_PASS("dot-machine-cfg", MachineCFGPrinter) +DUMMY_MACHINE_FUNCTION_PASS("early-ifcvt", EarlyIfConverterPass) +DUMMY_MACHINE_FUNCTION_PASS("early-machinelicm", EarlyMachineLICMPass) +DUMMY_MACHINE_FUNCTION_PASS("early-tailduplication", EarlyTailDuplicatePass) +DUMMY_MACHINE_FUNCTION_PASS("fentry-insert", FEntryInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("finalize-isel", FinalizeISelPass) +DUMMY_MACHINE_FUNCTION_PASS("fixup-statepoint-caller-saved", FixupStatepointCallerSavedPass) +DUMMY_MACHINE_FUNCTION_PASS("fs-profile-loader", MIRProfileLoaderNewPass) +DUMMY_MACHINE_FUNCTION_PASS("funclet-layout", FuncletLayoutPass) +DUMMY_MACHINE_FUNCTION_PASS("gc-empty-basic-blocks", GCEmptyBasicBlocksPass) +DUMMY_MACHINE_FUNCTION_PASS("implicit-null-checks", ImplicitNullChecksPass) +DUMMY_MACHINE_FUNCTION_PASS("instruction-select", InstructionSelectPass) +DUMMY_MACHINE_FUNCTION_PASS("irtranslator", IRTranslatorPass) +DUMMY_MACHINE_FUNCTION_PASS("kcfi", MachineKCFIPass) +DUMMY_MACHINE_FUNCTION_PASS("legalizer", LegalizerPass) +DUMMY_MACHINE_FUNCTION_PASS("livedebugvalues", LiveDebugValuesPass) +DUMMY_MACHINE_FUNCTION_PASS("liveintervals", LiveIntervalsPass) +DUMMY_MACHINE_FUNCTION_PASS("localstackalloc", LocalStackSlotPass) +DUMMY_MACHINE_FUNCTION_PASS("lrshrink", LiveRangeShrinkPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-combiner", MachineCombinerPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-cp", MachineCopyPropagationPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-cse", MachineCSEPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-function-splitter", MachineFunctionSplitterPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-latecleanup", MachineLateInstrsCleanupPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-sanmd", MachineSanitizerBinaryMetadata) +DUMMY_MACHINE_FUNCTION_PASS("machine-scheduler", MachineSchedulerPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-sink", MachineSinkingPass) +DUMMY_MACHINE_FUNCTION_PASS("machine-uniformity", MachineUniformityInfoWrapperPass) +DUMMY_MACHINE_FUNCTION_PASS("machineinstr-printer", MachineFunctionPrinterPass) +DUMMY_MACHINE_FUNCTION_PASS("machinelicm", MachineLICMPass) +DUMMY_MACHINE_FUNCTION_PASS("machineverifier", MachineVerifierPass) +DUMMY_MACHINE_FUNCTION_PASS("mirfs-discriminators", MIRAddFSDiscriminatorsPass) +DUMMY_MACHINE_FUNCTION_PASS("opt-phis", OptimizePHIsPass) +DUMMY_MACHINE_FUNCTION_PASS("patchable-function", PatchableFunctionPass) +DUMMY_MACHINE_FUNCTION_PASS("peephole-opt", PeepholeOptimizerPass) +DUMMY_MACHINE_FUNCTION_PASS("phi-node-elimination", PHIEliminationPass) +DUMMY_MACHINE_FUNCTION_PASS("post-RA-sched", PostRASchedulerPass) +DUMMY_MACHINE_FUNCTION_PASS("postmisched", PostMachineSchedulerPass) +DUMMY_MACHINE_FUNCTION_PASS("postra-machine-sink", PostRAMachineSinkingPass) +DUMMY_MACHINE_FUNCTION_PASS("postrapseudos", ExpandPostRAPseudosPass) +DUMMY_MACHINE_FUNCTION_PASS("print-machine-cycles", MachineCycleInfoPrinterPass) +DUMMY_MACHINE_FUNCTION_PASS("print-machine-uniformity", MachineUniformityInfoPrinterPass) +DUMMY_MACHINE_FUNCTION_PASS("processimpdefs", ProcessImplicitDefsPass) +DUMMY_MACHINE_FUNCTION_PASS("prologepilog", PrologEpilogInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("prologepilog-code", PrologEpilogCodeInserterPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-basic", RABasicPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-fast", RAFastPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-greedy", RAGreedyPass) +DUMMY_MACHINE_FUNCTION_PASS("ra-pbqp", RAPBQPPass) +DUMMY_MACHINE_FUNCTION_PASS("reg-usage-collector", RegUsageInfoCollectorPass) +DUMMY_MACHINE_FUNCTION_PASS("reg-usage-propagation", RegUsageInfoPropagationPass) +DUMMY_MACHINE_FUNCTION_PASS("regalloc", RegAllocPass) +DUMMY_MACHINE_FUNCTION_PASS("regallocscoringpass", RegAllocScoringPass) +DUMMY_MACHINE_FUNCTION_PASS("regbankselect", RegBankSelectPass) +DUMMY_MACHINE_FUNCTION_PASS("removeredundantdebugvalues", RemoveRedundantDebugValuesPass) +DUMMY_MACHINE_FUNCTION_PASS("rename-independent-subregs", RenameIndependentSubregsPass) +DUMMY_MACHINE_FUNCTION_PASS("reset-machine-function", ResetMachineFunctionPass) +DUMMY_MACHINE_FUNCTION_PASS("shrink-wrap", ShrinkWrapPass) +DUMMY_MACHINE_FUNCTION_PASS("simple-register-coalescing", RegisterCoalescerPass) +DUMMY_MACHINE_FUNCTION_PASS("stack-coloring", StackColoringPass) +DUMMY_MACHINE_FUNCTION_PASS("stack-frame-layout", StackFrameLayoutAnalysisPass) +DUMMY_MACHINE_FUNCTION_PASS("stack-slot-coloring", StackSlotColoringPass) +DUMMY_MACHINE_FUNCTION_PASS("stackmap-liveness", StackMapLivenessPass) +DUMMY_MACHINE_FUNCTION_PASS("tailduplication", TailDuplicatePass) +DUMMY_MACHINE_FUNCTION_PASS("twoaddressinstruction", TwoAddressInstructionPass) +DUMMY_MACHINE_FUNCTION_PASS("unpack-mi-bundles", UnpackMachineBundlesPass) +DUMMY_MACHINE_FUNCTION_PASS("virtregrewriter", VirtRegRewriterPass) +DUMMY_MACHINE_FUNCTION_PASS("xray-instrumentation", XRayInstrumentationPass) #undef DUMMY_MACHINE_FUNCTION_PASS - -#ifndef DUMMY_MACHINE_FUNCTION_ANALYSIS -#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) -#endif -DUMMY_MACHINE_FUNCTION_ANALYSIS("gc-analysis", GCMachineCodeAnalysisPass, ()) -#undef DUMMY_MACHINE_FUNCTION_ANALYSIS diff --git a/llvm/include/llvm/ProfileData/InstrProf.h b/llvm/include/llvm/ProfileData/InstrProf.h index 6cdceae5eeb960186caedec77d1b31845d25bbe2..53108a093bf4dd65371c067f6291410abf4d1e96 100644 --- a/llvm/include/llvm/ProfileData/InstrProf.h +++ b/llvm/include/llvm/ProfileData/InstrProf.h @@ -200,7 +200,7 @@ std::string getIRPGOFuncName(const Function &F, bool InLTO = false); /// \return the filename and the function name parsed from the output of /// \c getIRPGOFuncName() -std::pair getParsedIRPGOFuncName(StringRef IRPGOFuncName); +std::pair getParsedIRPGOName(StringRef IRPGOName); /// Return the name of the global variable used to store a function /// name in PGO instrumentation. \c FuncName is the IRPGO function name diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index 6bda80681432a01f34f170bf01eb0a28b45db305..9b0e1b0d7c4f9e9bc2f40878382626b012f55064 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -1241,6 +1241,18 @@ def match_selects : GICombineRule< [{ return Helper.matchSelect(*${root}, ${matchinfo}); }]), (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; +def match_ands : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (wip_match_opcode G_AND):$root, + [{ return Helper.matchAnd(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + +def match_ors : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (wip_match_opcode G_OR):$root, + [{ return Helper.matchOr(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + // FIXME: These should use the custom predicate feature once it lands. def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero, undef_to_negative_one, @@ -1314,7 +1326,7 @@ def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines, intdiv_combines, mulh_combines, redundant_neg_operands, and_or_disjoint_mask, fma_combines, fold_binop_into_select, sub_add_reg, select_to_minmax, redundant_binop_in_equality, - fsub_to_fneg, commute_constant_to_rhs]>; + fsub_to_fneg, commute_constant_to_rhs, match_ands, match_ors]>; // A combine group used to for prelegalizer combiners at -O0. The combines in // this group have been selected based on experiments to balance code size and diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h index a522a12299bb0299285ef4fee059ca041fd2b947..7462f61d32b566ec7b57fb5879b55e2cc2f34005 100644 --- a/llvm/include/llvm/Target/TargetMachine.h +++ b/llvm/include/llvm/Target/TargetMachine.h @@ -465,11 +465,6 @@ public: inconvertibleErrorCode()); } - virtual std::pair getPassNameFromLegacyName(StringRef) { - llvm_unreachable( - "getPassNameFromLegacyName parseMIRPipeline is not overridden"); - } - /// Add passes to the specified pass manager to get machine code emitted with /// the MCJIT. This method returns true if machine code is not supported. It /// fills the MCContext Ctx pointer which can be used to build custom diff --git a/llvm/include/llvm/Target/TargetSchedule.td b/llvm/include/llvm/Target/TargetSchedule.td index 032de7285178277ec62da51bb7243182ff642f0c..e2781a5d1ea54a91a40c15862ac50c000dfb600f 100644 --- a/llvm/include/llvm/Target/TargetSchedule.td +++ b/llvm/include/llvm/Target/TargetSchedule.td @@ -192,15 +192,10 @@ class ProcResourceUnits { SchedMachineModel SchedModel = ?; } -// EponymousProcResourceKind helps implement ProcResourceUnits by -// allowing a ProcResourceUnits definition to reference itself. It -// should not be referenced anywhere else. -def EponymousProcResourceKind : ProcResourceKind; - // Subtargets typically define processor resource kind and number of // units in one place. class ProcResource : ProcResourceKind, - ProcResourceUnits; + ProcResourceUnits(NAME), num>; class ProcResGroup resources> : ProcResourceKind { list Resources = resources; diff --git a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h index eb10545ee149e4cfc119bdafb98fa995bd40d2ff..1b6b525b19caeff61da860c43807b88e79408136 100644 --- a/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h +++ b/llvm/include/llvm/Transforms/Utils/SimplifyLibCalls.h @@ -201,8 +201,9 @@ private: Value *optimizeFMinFMax(CallInst *CI, IRBuilderBase &B); Value *optimizeLog(CallInst *CI, IRBuilderBase &B); Value *optimizeSqrt(CallInst *CI, IRBuilderBase &B); + Value *mergeSqrtToExp(CallInst *CI, IRBuilderBase &B); Value *optimizeSinCosPi(CallInst *CI, bool IsSin, IRBuilderBase &B); - Value *optimizeTan(CallInst *CI, IRBuilderBase &B); + Value *optimizeTrigInversionPairs(CallInst *CI, IRBuilderBase &B); // Wrapper for all floating point library call optimizations Value *optimizeFloatingPointLibCall(CallInst *CI, LibFunc Func, IRBuilderBase &B); diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index 2793b798f35f36206e3755822318490f2191d68d..01b017142cfcb0f2b893be81840ad90eae59a6b2 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -3034,7 +3034,7 @@ static Value *simplifyICmpWithConstant(CmpInst::Predicate Pred, Value *LHS, // floating-point casts: // icmp slt (bitcast (uitofp X)), 0 --> false // icmp sgt (bitcast (uitofp X)), -1 --> true - if (match(LHS, m_BitCast(m_UIToFP(m_Value(X))))) { + if (match(LHS, m_ElementWiseBitCast(m_UIToFP(m_Value(X))))) { if (Pred == ICmpInst::ICMP_SLT && match(RHS, m_Zero())) return ConstantInt::getFalse(ITy); if (Pred == ICmpInst::ICMP_SGT && match(RHS, m_AllOnes())) diff --git a/llvm/lib/Analysis/TypeMetadataUtils.cpp b/llvm/lib/Analysis/TypeMetadataUtils.cpp index bbaee06ed8a552d97d7641dd0396902a721d82ad..b8dcc39e9223c925278d2933e87d717aa1857e90 100644 --- a/llvm/lib/Analysis/TypeMetadataUtils.cpp +++ b/llvm/lib/Analysis/TypeMetadataUtils.cpp @@ -201,6 +201,26 @@ Constant *llvm::getPointerAtOffset(Constant *I, uint64_t Offset, Module &M, return nullptr; } +std::pair +llvm::getFunctionAtVTableOffset(GlobalVariable *GV, uint64_t Offset, + Module &M) { + Constant *Ptr = getPointerAtOffset(GV->getInitializer(), Offset, M, GV); + if (!Ptr) + return std::pair(nullptr, nullptr); + + auto C = Ptr->stripPointerCasts(); + // Make sure this is a function or alias to a function. + auto Fn = dyn_cast(C); + auto A = dyn_cast(C); + if (!Fn && A) + Fn = dyn_cast(A->getAliasee()); + + if (!Fn) + return std::pair(nullptr, nullptr); + + return std::pair(Fn, C); +} + void llvm::replaceRelativePointerUsersWithZero(Function *F) { for (auto *U : F->users()) { auto *PtrExpr = dyn_cast(U); diff --git a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp index 5b233fb365fe27e0743c4c55f8d8d7e0998b8e59..515a1d0caa04151cc440483d2d892bfcf9a19795 100644 --- a/llvm/lib/Bitcode/Reader/BitcodeReader.cpp +++ b/llvm/lib/Bitcode/Reader/BitcodeReader.cpp @@ -6632,9 +6632,6 @@ Error BitcodeReader::materialize(GlobalValue *GV) { if (Error Err = materializeMetadata()) return Err; - bool NewDebugInfoRequested = F->IsNewDbgInfoFormat; - F->IsNewDbgInfoFormat = false; - // Move the bit stream to the saved position of the deferred function body. if (Error JumpFailed = Stream.JumpToBit(DFII->second)) return JumpFailed; @@ -6710,14 +6707,6 @@ Error BitcodeReader::materialize(GlobalValue *GV) { // Look for functions that rely on old function attribute behavior. UpgradeFunctionAttributes(*F); - // If we've materialized a function set up in "new" debug-info mode, the - // contents just loaded will still be in dbg.value mode. Switch to the new - // mode now. NB: we can add more complicated logic here in the future to - // correctly identify when we do and don't need to autoupgrade. - if (NewDebugInfoRequested) { - F->convertToNewDbgValues(); - } - // Bring in any functions that this function forward-referenced via // blockaddresses. return materializeForwardReferencedFunctions(); @@ -8042,14 +8031,6 @@ BitcodeModule::getModuleImpl(LLVMContext &Context, bool MaterializeAll, return std::move(Err); } - // If we are operating in a "new debug-info" context, upgrade the debug-info - // in the loaded module. This is a transitional approach as we enable "new" - // debug-info in LLVM, which will eventually be pushed down into the - // autoupgrade path once the bitcode-encoding is finalised. Non-materialised - // functions will be upgraded in the materialize method. - if (UseNewDbgInfoFormat && !M->IsNewDbgInfoFormat) - M->convertToNewDbgValues(); - return std::move(M); } diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp index ccf3e9ec64921052bbdacaef332a4f2944a4784d..faa3edb2b03c88caf5a2e7269d6eca7d092ea73a 100644 --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -322,16 +322,6 @@ bool AtomicExpand::runOnFunction(Function &F) { if (isIdempotentRMW(RMWI) && simplifyIdempotentRMW(RMWI)) { MadeChange = true; } else { - AtomicRMWInst::BinOp Op = RMWI->getOperation(); - unsigned MinCASSize = TLI->getMinCmpXchgSizeInBits() / 8; - unsigned ValueSize = getAtomicOpSize(RMWI); - if (ValueSize < MinCASSize && - (Op == AtomicRMWInst::Or || Op == AtomicRMWInst::Xor || - Op == AtomicRMWInst::And)) { - RMWI = widenPartwordAtomicRMW(RMWI); - MadeChange = true; - } - MadeChange |= tryExpandAtomicRMW(RMWI); } } else if (CASI) @@ -607,6 +597,17 @@ bool AtomicExpand::tryExpandAtomicRMW(AtomicRMWInst *AI) { return true; } case TargetLoweringBase::AtomicExpansionKind::MaskedIntrinsic: { + unsigned MinCASSize = TLI->getMinCmpXchgSizeInBits() / 8; + unsigned ValueSize = getAtomicOpSize(AI); + if (ValueSize < MinCASSize) { + AtomicRMWInst::BinOp Op = AI->getOperation(); + // Widen And/Or/Xor and give the target another chance at expanding it. + if (Op == AtomicRMWInst::Or || Op == AtomicRMWInst::Xor || + Op == AtomicRMWInst::And) { + tryExpandAtomicRMW(widenPartwordAtomicRMW(AI)); + return true; + } + } expandAtomicRMWToMaskedIntrinsic(AI); return true; } @@ -845,6 +846,14 @@ static Value *performMaskedAtomicOp(AtomicRMWInst::BinOp Op, /// part of the value. void AtomicExpand::expandPartwordAtomicRMW( AtomicRMWInst *AI, TargetLoweringBase::AtomicExpansionKind ExpansionKind) { + // Widen And/Or/Xor and give the target another chance at expanding it. + AtomicRMWInst::BinOp Op = AI->getOperation(); + if (Op == AtomicRMWInst::Or || Op == AtomicRMWInst::Xor || + Op == AtomicRMWInst::And) { + tryExpandAtomicRMW(widenPartwordAtomicRMW(AI)); + return; + } + AtomicOrdering MemOpOrder = AI->getOrdering(); SyncScope::ID SSID = AI->getSyncScopeID(); @@ -855,18 +864,16 @@ void AtomicExpand::expandPartwordAtomicRMW( AI->getAlign(), TLI->getMinCmpXchgSizeInBits() / 8); Value *ValOperand_Shifted = nullptr; - if (AI->getOperation() == AtomicRMWInst::Xchg || - AI->getOperation() == AtomicRMWInst::Add || - AI->getOperation() == AtomicRMWInst::Sub || - AI->getOperation() == AtomicRMWInst::Nand) { + if (Op == AtomicRMWInst::Xchg || Op == AtomicRMWInst::Add || + Op == AtomicRMWInst::Sub || Op == AtomicRMWInst::Nand) { ValOperand_Shifted = Builder.CreateShl(Builder.CreateZExt(AI->getValOperand(), PMV.WordType), PMV.ShiftAmt, "ValOperand_Shifted"); } auto PerformPartwordOp = [&](IRBuilderBase &Builder, Value *Loaded) { - return performMaskedAtomicOp(AI->getOperation(), Builder, Loaded, - ValOperand_Shifted, AI->getValOperand(), PMV); + return performMaskedAtomicOp(Op, Builder, Loaded, ValOperand_Shifted, + AI->getValOperand(), PMV); }; Value *OldResult; diff --git a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp index 6a7de3b241feeea62a56115091a731a5b24cc97b..facc01452d2f12b7f391ba8ecfc026dae5b20a5b 100644 --- a/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp +++ b/llvm/lib/CodeGen/DeadMachineInstructionElim.cpp @@ -10,6 +10,7 @@ // //===----------------------------------------------------------------------===// +#include "llvm/CodeGen/DeadMachineInstructionElim.h" #include "llvm/ADT/PostOrderIterator.h" #include "llvm/ADT/Statistic.h" #include "llvm/CodeGen/LiveRegUnits.h" @@ -28,37 +29,57 @@ using namespace llvm; STATISTIC(NumDeletes, "Number of dead instructions deleted"); namespace { - class DeadMachineInstructionElim : public MachineFunctionPass { - bool runOnMachineFunction(MachineFunction &MF) override; +class DeadMachineInstructionElimImpl { + const MachineRegisterInfo *MRI = nullptr; + const TargetInstrInfo *TII = nullptr; + LiveRegUnits LivePhysRegs; - const MachineRegisterInfo *MRI = nullptr; - const TargetInstrInfo *TII = nullptr; - LiveRegUnits LivePhysRegs; +public: + bool runImpl(MachineFunction &MF); - public: - static char ID; // Pass identification, replacement for typeid - DeadMachineInstructionElim() : MachineFunctionPass(ID) { - initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry()); - } +private: + bool isDead(const MachineInstr *MI) const; + bool eliminateDeadMI(MachineFunction &MF); +}; - void getAnalysisUsage(AnalysisUsage &AU) const override { - AU.setPreservesCFG(); - MachineFunctionPass::getAnalysisUsage(AU); - } +class DeadMachineInstructionElim : public MachineFunctionPass { +public: + static char ID; // Pass identification, replacement for typeid - private: - bool isDead(const MachineInstr *MI) const; + DeadMachineInstructionElim() : MachineFunctionPass(ID) { + initializeDeadMachineInstructionElimPass(*PassRegistry::getPassRegistry()); + } + + bool runOnMachineFunction(MachineFunction &MF) override { + if (skipFunction(MF.getFunction())) + return false; + return DeadMachineInstructionElimImpl().runImpl(MF); + } - bool eliminateDeadMI(MachineFunction &MF); - }; + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + MachineFunctionPass::getAnalysisUsage(AU); + } +}; +} // namespace + +PreservedAnalyses +DeadMachineInstructionElimPass::run(MachineFunction &MF, + MachineFunctionAnalysisManager &) { + if (!DeadMachineInstructionElimImpl().runImpl(MF)) + return PreservedAnalyses::all(); + PreservedAnalyses PA; + PA.preserveSet(); + return PA; } + char DeadMachineInstructionElim::ID = 0; char &llvm::DeadMachineInstructionElimID = DeadMachineInstructionElim::ID; INITIALIZE_PASS(DeadMachineInstructionElim, DEBUG_TYPE, "Remove dead machine instructions", false, false) -bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { +bool DeadMachineInstructionElimImpl::isDead(const MachineInstr *MI) const { // Technically speaking inline asm without side effects and no defs can still // be deleted. But there is so much bad inline asm code out there, we should // let them be. @@ -102,10 +123,7 @@ bool DeadMachineInstructionElim::isDead(const MachineInstr *MI) const { return true; } -bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { - if (skipFunction(MF.getFunction())) - return false; - +bool DeadMachineInstructionElimImpl::runImpl(MachineFunction &MF) { MRI = &MF.getRegInfo(); const TargetSubtargetInfo &ST = MF.getSubtarget(); @@ -118,7 +136,7 @@ bool DeadMachineInstructionElim::runOnMachineFunction(MachineFunction &MF) { return AnyChanges; } -bool DeadMachineInstructionElim::eliminateDeadMI(MachineFunction &MF) { +bool DeadMachineInstructionElimImpl::eliminateDeadMI(MachineFunction &MF) { bool AnyChanges = false; // Loop over all instructions in all blocks, from bottom to top, so that it's diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 772229215e798d4ad3fd3319bf90caf5d995355e..1b199cfd41d231b0d32d6f49f78bdef1ba46e236 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -28,10 +28,12 @@ #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetOpcodes.h" +#include "llvm/IR/ConstantRange.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/InstrTypes.h" #include "llvm/Support/Casting.h" #include "llvm/Support/DivisionByConstantInfo.h" +#include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" #include "llvm/Target/TargetMachine.h" #include @@ -6651,3 +6653,181 @@ bool CombinerHelper::matchSelect(MachineInstr &MI, BuildFnTy &MatchInfo) { return false; } + +/// Fold (icmp Pred1 V1, C1) && (icmp Pred2 V2, C2) +/// or (icmp Pred1 V1, C1) || (icmp Pred2 V2, C2) +/// into a single comparison using range-based reasoning. +/// see InstCombinerImpl::foldAndOrOfICmpsUsingRanges. +bool CombinerHelper::tryFoldAndOrOrICmpsUsingRanges(GLogicalBinOp *Logic, + BuildFnTy &MatchInfo) { + assert(Logic->getOpcode() != TargetOpcode::G_XOR && "unexpected xor"); + bool IsAnd = Logic->getOpcode() == TargetOpcode::G_AND; + Register DstReg = Logic->getReg(0); + Register LHS = Logic->getLHSReg(); + Register RHS = Logic->getRHSReg(); + unsigned Flags = Logic->getFlags(); + + // We need an G_ICMP on the LHS register. + GICmp *Cmp1 = getOpcodeDef(LHS, MRI); + if (!Cmp1) + return false; + + // We need an G_ICMP on the RHS register. + GICmp *Cmp2 = getOpcodeDef(RHS, MRI); + if (!Cmp2) + return false; + + // We want to fold the icmps. + if (!MRI.hasOneNonDBGUse(Cmp1->getReg(0)) || + !MRI.hasOneNonDBGUse(Cmp2->getReg(0))) + return false; + + APInt C1; + APInt C2; + std::optional MaybeC1 = + getIConstantVRegValWithLookThrough(Cmp1->getRHSReg(), MRI); + if (!MaybeC1) + return false; + C1 = MaybeC1->Value; + + std::optional MaybeC2 = + getIConstantVRegValWithLookThrough(Cmp2->getRHSReg(), MRI); + if (!MaybeC2) + return false; + C2 = MaybeC2->Value; + + Register R1 = Cmp1->getLHSReg(); + Register R2 = Cmp2->getLHSReg(); + CmpInst::Predicate Pred1 = Cmp1->getCond(); + CmpInst::Predicate Pred2 = Cmp2->getCond(); + LLT CmpTy = MRI.getType(Cmp1->getReg(0)); + LLT CmpOperandTy = MRI.getType(R1); + + // We build ands, adds, and constants of type CmpOperandTy. + // They must be legal to build. + if (!isLegalOrBeforeLegalizer({TargetOpcode::G_AND, CmpOperandTy}) || + !isLegalOrBeforeLegalizer({TargetOpcode::G_ADD, CmpOperandTy}) || + !isConstantLegalOrBeforeLegalizer(CmpOperandTy)) + return false; + + // Look through add of a constant offset on R1, R2, or both operands. This + // allows us to interpret the R + C' < C'' range idiom into a proper range. + std::optional Offset1; + std::optional Offset2; + if (R1 != R2) { + if (GAdd *Add = getOpcodeDef(R1, MRI)) { + std::optional MaybeOffset1 = + getIConstantVRegValWithLookThrough(Add->getRHSReg(), MRI); + if (MaybeOffset1) { + R1 = Add->getLHSReg(); + Offset1 = MaybeOffset1->Value; + } + } + if (GAdd *Add = getOpcodeDef(R2, MRI)) { + std::optional MaybeOffset2 = + getIConstantVRegValWithLookThrough(Add->getRHSReg(), MRI); + if (MaybeOffset2) { + R2 = Add->getLHSReg(); + Offset2 = MaybeOffset2->Value; + } + } + } + + if (R1 != R2) + return false; + + // We calculate the icmp ranges including maybe offsets. + ConstantRange CR1 = ConstantRange::makeExactICmpRegion( + IsAnd ? ICmpInst::getInversePredicate(Pred1) : Pred1, C1); + if (Offset1) + CR1 = CR1.subtract(*Offset1); + + ConstantRange CR2 = ConstantRange::makeExactICmpRegion( + IsAnd ? ICmpInst::getInversePredicate(Pred2) : Pred2, C2); + if (Offset2) + CR2 = CR2.subtract(*Offset2); + + bool CreateMask = false; + APInt LowerDiff; + std::optional CR = CR1.exactUnionWith(CR2); + if (!CR) { + // We need non-wrapping ranges. + if (CR1.isWrappedSet() || CR2.isWrappedSet()) + return false; + + // Check whether we have equal-size ranges that only differ by one bit. + // In that case we can apply a mask to map one range onto the other. + LowerDiff = CR1.getLower() ^ CR2.getLower(); + APInt UpperDiff = (CR1.getUpper() - 1) ^ (CR2.getUpper() - 1); + APInt CR1Size = CR1.getUpper() - CR1.getLower(); + if (!LowerDiff.isPowerOf2() || LowerDiff != UpperDiff || + CR1Size != CR2.getUpper() - CR2.getLower()) + return false; + + CR = CR1.getLower().ult(CR2.getLower()) ? CR1 : CR2; + CreateMask = true; + } + + if (IsAnd) + CR = CR->inverse(); + + CmpInst::Predicate NewPred; + APInt NewC, Offset; + CR->getEquivalentICmp(NewPred, NewC, Offset); + + // We take the result type of one of the original icmps, CmpTy, for + // the to be build icmp. The operand type, CmpOperandTy, is used for + // the other instructions and constants to be build. The types of + // the parameters and output are the same for add and and. CmpTy + // and the type of DstReg might differ. That is why we zext or trunc + // the icmp into the destination register. + + MatchInfo = [=](MachineIRBuilder &B) { + if (CreateMask && Offset != 0) { + auto TildeLowerDiff = B.buildConstant(CmpOperandTy, ~LowerDiff); + auto And = B.buildAnd(CmpOperandTy, R1, TildeLowerDiff); // the mask. + auto OffsetC = B.buildConstant(CmpOperandTy, Offset); + auto Add = B.buildAdd(CmpOperandTy, And, OffsetC, Flags); + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, Add, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else if (CreateMask && Offset == 0) { + auto TildeLowerDiff = B.buildConstant(CmpOperandTy, ~LowerDiff); + auto And = B.buildAnd(CmpOperandTy, R1, TildeLowerDiff); // the mask. + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, And, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else if (!CreateMask && Offset != 0) { + auto OffsetC = B.buildConstant(CmpOperandTy, Offset); + auto Add = B.buildAdd(CmpOperandTy, R1, OffsetC, Flags); + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, Add, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else if (!CreateMask && Offset == 0) { + auto NewCon = B.buildConstant(CmpOperandTy, NewC); + auto ICmp = B.buildICmp(NewPred, CmpTy, R1, NewCon); + B.buildZExtOrTrunc(DstReg, ICmp); + } else { + llvm_unreachable("unexpected configuration of CreateMask and Offset"); + } + }; + return true; +} + +bool CombinerHelper::matchAnd(MachineInstr &MI, BuildFnTy &MatchInfo) { + GAnd *And = cast(&MI); + + if (tryFoldAndOrOrICmpsUsingRanges(And, MatchInfo)) + return true; + + return false; +} + +bool CombinerHelper::matchOr(MachineInstr &MI, BuildFnTy &MatchInfo) { + GOr *Or = cast(&MI); + + if (tryFoldAndOrOrICmpsUsingRanges(Or, MatchInfo)) + return true; + + return false; +} diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index c9fe758821f96ca68b8763b8062010f10a8aa7f3..26fd12f9e51c4315a0f7830aa18156a42078dfc8 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -1071,49 +1071,70 @@ void llvm::getSelectionDAGFallbackAnalysisUsage(AnalysisUsage &AU) { } LLT llvm::getLCMType(LLT OrigTy, LLT TargetTy) { - const unsigned OrigSize = OrigTy.getSizeInBits(); - const unsigned TargetSize = TargetTy.getSizeInBits(); - - if (OrigSize == TargetSize) + if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits()) return OrigTy; - if (OrigTy.isVector()) { - const LLT OrigElt = OrigTy.getElementType(); - - if (TargetTy.isVector()) { - const LLT TargetElt = TargetTy.getElementType(); + if (OrigTy.isVector() && TargetTy.isVector()) { + LLT OrigElt = OrigTy.getElementType(); + LLT TargetElt = TargetTy.getElementType(); - if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { - int GCDElts = - std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements()); - // Prefer the original element type. - ElementCount Mul = OrigTy.getElementCount() * TargetTy.getNumElements(); - return LLT::vector(Mul.divideCoefficientBy(GCDElts), - OrigTy.getElementType()); - } - } else { - if (OrigElt.getSizeInBits() == TargetSize) - return OrigTy; + // TODO: The docstring for this function says the intention is to use this + // function to build MERGE/UNMERGE instructions. It won't be the case that + // we generate a MERGE/UNMERGE between fixed and scalable vector types. We + // could implement getLCMType between the two in the future if there was a + // need, but it is not worth it now as this function should not be used in + // that way. + assert(((OrigTy.isScalableVector() && !TargetTy.isFixedVector()) || + (OrigTy.isFixedVector() && !TargetTy.isScalableVector())) && + "getLCMType not implemented between fixed and scalable vectors."); + + if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { + int GCDMinElts = std::gcd(OrigTy.getElementCount().getKnownMinValue(), + TargetTy.getElementCount().getKnownMinValue()); + // Prefer the original element type. + ElementCount Mul = OrigTy.getElementCount().multiplyCoefficientBy( + TargetTy.getElementCount().getKnownMinValue()); + return LLT::vector(Mul.divideCoefficientBy(GCDMinElts), + OrigTy.getElementType()); } - - unsigned LCMSize = std::lcm(OrigSize, TargetSize); - return LLT::fixed_vector(LCMSize / OrigElt.getSizeInBits(), OrigElt); + unsigned LCM = std::lcm(OrigTy.getSizeInBits().getKnownMinValue(), + TargetTy.getSizeInBits().getKnownMinValue()); + return LLT::vector( + ElementCount::get(LCM / OrigElt.getSizeInBits(), OrigTy.isScalable()), + OrigElt); } - if (TargetTy.isVector()) { - unsigned LCMSize = std::lcm(OrigSize, TargetSize); - return LLT::fixed_vector(LCMSize / OrigSize, OrigTy); + // One type is scalar, one type is vector + if (OrigTy.isVector() || TargetTy.isVector()) { + LLT VecTy = OrigTy.isVector() ? OrigTy : TargetTy; + LLT ScalarTy = OrigTy.isVector() ? TargetTy : OrigTy; + LLT EltTy = VecTy.getElementType(); + LLT OrigEltTy = OrigTy.isVector() ? OrigTy.getElementType() : OrigTy; + + // Prefer scalar type from OrigTy. + if (EltTy.getSizeInBits() == ScalarTy.getSizeInBits()) + return LLT::vector(VecTy.getElementCount(), OrigEltTy); + + // Different size scalars. Create vector with the same total size. + // LCM will take fixed/scalable from VecTy. + unsigned LCM = std::lcm(EltTy.getSizeInBits().getFixedValue() * + VecTy.getElementCount().getKnownMinValue(), + ScalarTy.getSizeInBits().getFixedValue()); + // Prefer type from OrigTy + return LLT::vector(ElementCount::get(LCM / OrigEltTy.getSizeInBits(), + VecTy.getElementCount().isScalable()), + OrigEltTy); } - unsigned LCMSize = std::lcm(OrigSize, TargetSize); - + // At this point, both types are scalars of different size + unsigned LCM = std::lcm(OrigTy.getSizeInBits().getFixedValue(), + TargetTy.getSizeInBits().getFixedValue()); // Preserve pointer types. - if (LCMSize == OrigSize) + if (LCM == OrigTy.getSizeInBits()) return OrigTy; - if (LCMSize == TargetSize) + if (LCM == TargetTy.getSizeInBits()) return TargetTy; - - return LLT::scalar(LCMSize); + return LLT::scalar(LCM); } LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) { @@ -1138,45 +1159,56 @@ LLT llvm::getCoverTy(LLT OrigTy, LLT TargetTy) { } LLT llvm::getGCDType(LLT OrigTy, LLT TargetTy) { - const unsigned OrigSize = OrigTy.getSizeInBits(); - const unsigned TargetSize = TargetTy.getSizeInBits(); - - if (OrigSize == TargetSize) + if (OrigTy.getSizeInBits() == TargetTy.getSizeInBits()) return OrigTy; - if (OrigTy.isVector()) { + if (OrigTy.isVector() && TargetTy.isVector()) { LLT OrigElt = OrigTy.getElementType(); - if (TargetTy.isVector()) { - LLT TargetElt = TargetTy.getElementType(); - if (OrigElt.getSizeInBits() == TargetElt.getSizeInBits()) { - int GCD = std::gcd(OrigTy.getNumElements(), TargetTy.getNumElements()); - return LLT::scalarOrVector(ElementCount::getFixed(GCD), OrigElt); - } - } else { - // If the source is a vector of pointers, return a pointer element. - if (OrigElt.getSizeInBits() == TargetSize) - return OrigElt; - } - unsigned GCD = std::gcd(OrigSize, TargetSize); + // TODO: The docstring for this function says the intention is to use this + // function to build MERGE/UNMERGE instructions. It won't be the case that + // we generate a MERGE/UNMERGE between fixed and scalable vector types. We + // could implement getGCDType between the two in the future if there was a + // need, but it is not worth it now as this function should not be used in + // that way. + assert(((OrigTy.isScalableVector() && !TargetTy.isFixedVector()) || + (OrigTy.isFixedVector() && !TargetTy.isScalableVector())) && + "getGCDType not implemented between fixed and scalable vectors."); + + unsigned GCD = std::gcd(OrigTy.getSizeInBits().getKnownMinValue(), + TargetTy.getSizeInBits().getKnownMinValue()); if (GCD == OrigElt.getSizeInBits()) - return OrigElt; + return LLT::scalarOrVector(ElementCount::get(1, OrigTy.isScalable()), + OrigElt); - // If we can't produce the original element type, we have to use a smaller - // scalar. + // Cannot produce original element type, but both have vscale in common. if (GCD < OrigElt.getSizeInBits()) - return LLT::scalar(GCD); - return LLT::fixed_vector(GCD / OrigElt.getSizeInBits(), OrigElt); - } + return LLT::scalarOrVector(ElementCount::get(1, OrigTy.isScalable()), + GCD); - if (TargetTy.isVector()) { - // Try to preserve the original element type. - LLT TargetElt = TargetTy.getElementType(); - if (TargetElt.getSizeInBits() == OrigSize) - return OrigTy; + return LLT::vector( + ElementCount::get(GCD / OrigElt.getSizeInBits().getFixedValue(), + OrigTy.isScalable()), + OrigElt); } - unsigned GCD = std::gcd(OrigSize, TargetSize); + // If one type is vector and the element size matches the scalar size, then + // the gcd is the scalar type. + if (OrigTy.isVector() && + OrigTy.getElementType().getSizeInBits() == TargetTy.getSizeInBits()) + return OrigTy.getElementType(); + if (TargetTy.isVector() && + TargetTy.getElementType().getSizeInBits() == OrigTy.getSizeInBits()) + return OrigTy; + + // At this point, both types are either scalars of different type or one is a + // vector and one is a scalar. If both types are scalars, the GCD type is the + // GCD between the two scalar sizes. If one is vector and one is scalar, then + // the GCD type is the GCD between the scalar and the vector element size. + LLT OrigScalar = OrigTy.getScalarType(); + LLT TargetScalar = TargetTy.getScalarType(); + unsigned GCD = std::gcd(OrigScalar.getSizeInBits().getFixedValue(), + TargetScalar.getSizeInBits().getFixedValue()); return LLT::scalar(GCD); } diff --git a/llvm/lib/CodeGen/MachineModuleInfo.cpp b/llvm/lib/CodeGen/MachineModuleInfo.cpp index 921feb253d64226b9a02a4870b1fbbc45e7a0fa8..f24288bb69de00bd89503b21249d0deaad3faa53 100644 --- a/llvm/lib/CodeGen/MachineModuleInfo.cpp +++ b/llvm/lib/CodeGen/MachineModuleInfo.cpp @@ -237,11 +237,10 @@ bool MachineModuleInfoWrapperPass::doFinalization(Module &M) { AnalysisKey MachineModuleAnalysis::Key; -MachineModuleInfo MachineModuleAnalysis::run(Module &M, - ModuleAnalysisManager &) { - MachineModuleInfo MMI(TM); +MachineModuleAnalysis::Result +MachineModuleAnalysis::run(Module &M, ModuleAnalysisManager &) { MMI.TheModule = &M; - MMI.DbgInfoAvailable = !DisableDebugInfoPrinting && - !M.debug_compile_units().empty(); - return MMI; + MMI.DbgInfoAvailable = + !DisableDebugInfoPrinting && !M.debug_compile_units().empty(); + return Result(MMI); } diff --git a/llvm/lib/CodeGen/MachinePassManager.cpp b/llvm/lib/CodeGen/MachinePassManager.cpp index 0770eba660b45dea6229ab934d2d3c351a12e609..d42bbe239830f0877cb5b6053af8ba60fa426250 100644 --- a/llvm/lib/CodeGen/MachinePassManager.cpp +++ b/llvm/lib/CodeGen/MachinePassManager.cpp @@ -29,7 +29,7 @@ Error MachineFunctionPassManager::run(Module &M, // because we don't run any module pass in codegen pipeline. This is very // important because the codegen state is stored in MMI which is the analysis // result of MachineModuleAnalysis. MMI should not be recomputed. - auto &MMI = MFAM.getResult(M); + auto &MMI = MFAM.getResult(M).getMMI(); (void)RequireCodeGenSCCOrder; assert(!RequireCodeGenSCCOrder && "not implemented"); @@ -42,12 +42,12 @@ Error MachineFunctionPassManager::run(Module &M, // No need to pop this callback later since MIR pipeline is flat which means // current pipeline is the top-level pipeline. Callbacks are not used after // current pipeline. - PI.pushBeforeNonSkippedPassCallback([&MFAM](StringRef PassID, Any IR) { + PI.pushBeforeNonSkippedPassCallback([](StringRef PassID, Any IR) { assert(llvm::any_cast(&IR)); const MachineFunction *MF = llvm::any_cast(IR); assert(MF && "Machine function should be valid for printing"); std::string Banner = std::string("After ") + std::string(PassID); - verifyMachineFunction(&MFAM, Banner, *MF); + verifyMachineFunction(Banner, *MF); }); } diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp index c4b6bf3372139e74f430b17b4d7855966a449c34..750f739a559900bfe1e98e2b3c419471752a5a45 100644 --- a/llvm/lib/CodeGen/MachineScheduler.cpp +++ b/llvm/lib/CodeGen/MachineScheduler.cpp @@ -3804,6 +3804,12 @@ ScheduleDAGMILive *llvm::createGenericSchedLive(MachineSchedContext *C) { // data and pass it to later mutations. Have a single mutation that gathers // the interesting nodes in one pass. DAG->addMutation(createCopyConstrainDAGMutation(DAG->TII, DAG->TRI)); + + const TargetSubtargetInfo &STI = C->MF->getSubtarget(); + // Add MacroFusion mutation if fusions are not empty. + const auto &MacroFusions = STI.getMacroFusions(); + if (!MacroFusions.empty()) + DAG->addMutation(createMacroFusionDAGMutation(MacroFusions)); return DAG; } @@ -3953,8 +3959,15 @@ void PostGenericScheduler::schedNode(SUnit *SU, bool IsTopNode) { } ScheduleDAGMI *llvm::createGenericSchedPostRA(MachineSchedContext *C) { - return new ScheduleDAGMI(C, std::make_unique(C), - /*RemoveKillFlags=*/true); + ScheduleDAGMI *DAG = + new ScheduleDAGMI(C, std::make_unique(C), + /*RemoveKillFlags=*/true); + const TargetSubtargetInfo &STI = C->MF->getSubtarget(); + // Add MacroFusion mutation if fusions are not empty. + const auto &MacroFusions = STI.getMacroFusions(); + if (!MacroFusions.empty()) + DAG->addMutation(createMacroFusionDAGMutation(MacroFusions)); + return DAG; } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp index fe865ed6f8a0e5ea75d393949e4b240bd2cfeec0..c65e91741533c8f3b685387c9f6295dcf93f6687 100644 --- a/llvm/lib/CodeGen/MachineVerifier.cpp +++ b/llvm/lib/CodeGen/MachineVerifier.cpp @@ -339,8 +339,7 @@ FunctionPass *llvm::createMachineVerifierPass(const std::string &Banner) { return new MachineVerifierPass(Banner); } -void llvm::verifyMachineFunction(MachineFunctionAnalysisManager *, - const std::string &Banner, +void llvm::verifyMachineFunction(const std::string &Banner, const MachineFunction &MF) { // TODO: Use MFAM after porting below analyses. // LiveVariables *LiveVars; diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 7f91de12e10d0291ee417b5e019fb0453473ee41..4adea020011b82c13785439b261259e1f597c810 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -334,16 +334,11 @@ namespace { } bool SimplifyDemandedBits(SDValue Op, const APInt &DemandedBits) { - TargetLowering::TargetLoweringOpt TLO(DAG, LegalTypes, LegalOperations); - KnownBits Known; - if (!TLI.SimplifyDemandedBits(Op, DemandedBits, Known, TLO, 0, false)) - return false; - - // Revisit the node. - AddToWorklist(Op.getNode()); - - CommitTargetLoweringOpt(TLO); - return true; + EVT VT = Op.getValueType(); + APInt DemandedElts = VT.isFixedLengthVector() + ? APInt::getAllOnes(VT.getVectorNumElements()) + : APInt(1, 1); + return SimplifyDemandedBits(Op, DemandedBits, DemandedElts, false); } /// Check the specified vector node value to see if it can be simplified or @@ -11142,11 +11137,29 @@ SDValue DAGCombiner::visitCTTZ_ZERO_UNDEF(SDNode *N) { SDValue DAGCombiner::visitCTPOP(SDNode *N) { SDValue N0 = N->getOperand(0); EVT VT = N->getValueType(0); + unsigned NumBits = VT.getScalarSizeInBits(); SDLoc DL(N); // fold (ctpop c1) -> c2 if (SDValue C = DAG.FoldConstantArithmetic(ISD::CTPOP, DL, VT, {N0})) return C; + + // If the upper bits are known to be zero, then see if its profitable to + // only count the lower bits. + if (VT.isScalarInteger() && NumBits > 8 && (NumBits & 1) == 0) { + EVT HalfVT = EVT::getIntegerVT(*DAG.getContext(), NumBits / 2); + if (hasOperation(ISD::CTPOP, HalfVT) && + TLI.isTypeDesirableForOp(ISD::CTPOP, HalfVT) && + TLI.isTruncateFree(N0, HalfVT) && TLI.isZExtFree(HalfVT, VT)) { + APInt UpperBits = APInt::getHighBitsSet(NumBits, NumBits / 2); + if (DAG.MaskedValueIsZero(N0, UpperBits)) { + SDValue PopCnt = DAG.getNode(ISD::CTPOP, DL, HalfVT, + DAG.getZExtOrTrunc(N0, DL, HalfVT)); + return DAG.getZExtOrTrunc(PopCnt, DL, VT); + } + } + } + return SDValue(); } diff --git a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp index 5926a60581112fb55d510ed688beb83784521429..6cf54085915230ed418fa456f64941ca1a17e845 100644 --- a/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp @@ -431,7 +431,7 @@ void FunctionLoweringInfo::ComputePHILiveOutRegInfo(const PHINode *PN) { if (TLI->getNumRegisters(PN->getContext(), IntVT) != 1) return; - IntVT = TLI->getTypeToTransformTo(PN->getContext(), IntVT); + IntVT = TLI->getRegisterType(PN->getContext(), IntVT); unsigned BitWidth = IntVT.getSizeInBits(); auto It = ValueMap.find(PN); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp index 0c634ec9809d9c71de95f6c7f40833b40e6c148c..39b7e06155414121e74b6e5b1f1a563ba1d2b0f3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp @@ -2897,6 +2897,8 @@ void DAGTypeLegalizer::ExpandShiftByConstant(SDNode *N, const APInt &Amt, /// shift amount. bool DAGTypeLegalizer:: ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { + unsigned Opc = N->getOpcode(); + SDValue In = N->getOperand(0); SDValue Amt = N->getOperand(1); EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); EVT ShTy = Amt.getValueType(); @@ -2907,15 +2909,15 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { SDLoc dl(N); APInt HighBitMask = APInt::getHighBitsSet(ShBits, ShBits - Log2_32(NVTBits)); - KnownBits Known = DAG.computeKnownBits(N->getOperand(1)); + KnownBits Known = DAG.computeKnownBits(Amt); // If we don't know anything about the high bits, exit. - if (((Known.Zero|Known.One) & HighBitMask) == 0) + if (((Known.Zero | Known.One) & HighBitMask) == 0) return false; // Get the incoming operand to be shifted. SDValue InL, InH; - GetExpandedInteger(N->getOperand(0), InL, InH); + GetExpandedInteger(In, InL, InH); // If we know that any of the high bits of the shift amount are one, then we // can do this as a couple of simple shifts. @@ -2924,7 +2926,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { Amt = DAG.getNode(ISD::AND, dl, ShTy, Amt, DAG.getConstant(~HighBitMask, dl, ShTy)); - switch (N->getOpcode()) { + switch (Opc) { default: llvm_unreachable("Unknown shift"); case ISD::SHL: Lo = DAG.getConstant(0, dl, NVT); // Low part is zero. @@ -2952,7 +2954,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { DAG.getConstant(NVTBits - 1, dl, ShTy)); unsigned Op1, Op2; - switch (N->getOpcode()) { + switch (Opc) { default: llvm_unreachable("Unknown shift"); case ISD::SHL: Op1 = ISD::SHL; Op2 = ISD::SRL; break; case ISD::SRL: @@ -2960,7 +2962,7 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { } // When shifting right the arithmetic for Lo and Hi is swapped. - if (N->getOpcode() != ISD::SHL) + if (Opc != ISD::SHL) std::swap(InL, InH); // Use a little trick to get the bits that move from Lo to Hi. First @@ -2969,10 +2971,10 @@ ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) { // Then compute the remaining shift with amount-1. SDValue Sh2 = DAG.getNode(Op2, dl, NVT, Sh1, Amt2); - Lo = DAG.getNode(N->getOpcode(), dl, NVT, InL, Amt); + Lo = DAG.getNode(Opc, dl, NVT, InL, Amt); Hi = DAG.getNode(ISD::OR, dl, NVT, DAG.getNode(Op1, dl, NVT, InH, Amt),Sh2); - if (N->getOpcode() != ISD::SHL) + if (Opc != ISD::SHL) std::swap(Hi, Lo); return true; } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 3c1343836187a93f045beabc9c831b8884ef745e..55eee780d512c863acd5f6cb9426136f5513e9c3 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -3110,6 +3110,33 @@ KnownBits SelectionDAG::computeKnownBits(SDValue Op, const APInt &DemandedElts, } break; } + case ISD::STEP_VECTOR: { + const APInt &Step = Op.getConstantOperandAPInt(0); + + if (Step.isPowerOf2()) + Known.Zero.setLowBits(Step.logBase2()); + + const Function &F = getMachineFunction().getFunction(); + + if (!isUIntN(BitWidth, Op.getValueType().getVectorMinNumElements())) + break; + const APInt MinNumElts = + APInt(BitWidth, Op.getValueType().getVectorMinNumElements()); + + bool Overflow; + const APInt MaxNumElts = getVScaleRange(&F, BitWidth) + .getUnsignedMax() + .umul_ov(MinNumElts, Overflow); + if (Overflow) + break; + + const APInt MaxValue = (MaxNumElts - 1).umul_ov(Step, Overflow); + if (Overflow) + break; + + Known.Zero.setHighBits(MaxValue.countl_zero()); + break; + } case ISD::BUILD_VECTOR: assert(!Op.getValueType().isScalableVector()); // Collect the known bits that are shared by every demanded vector element. diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index b15f62bc3aae74436660563ea191f0335898c92f..a4987de43779afee027d105d007687710e098f8d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -4718,21 +4718,25 @@ SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1, DAG.getConstant(C1 & Imm, dl, ExtDstTy), Cond); } else if ((N1C->isZero() || N1C->isOne()) && (Cond == ISD::SETEQ || Cond == ISD::SETNE)) { - // SETCC (SETCC), [0|1], [EQ|NE] -> SETCC - if (N0.getOpcode() == ISD::SETCC && + // SETCC (X), [0|1], [EQ|NE] -> X if X is known 0/1. i1 types are + // excluded as they are handled below whilst checking for foldBooleans. + if ((N0.getOpcode() == ISD::SETCC || VT.getScalarType() != MVT::i1) && isTypeLegal(VT) && VT.bitsLE(N0.getValueType()) && (N0.getValueType() == MVT::i1 || - getBooleanContents(N0.getOperand(0).getValueType()) == - ZeroOrOneBooleanContent)) { + getBooleanContents(N0.getValueType()) == ZeroOrOneBooleanContent) && + DAG.MaskedValueIsZero( + N0, APInt::getBitsSetFrom(N0.getValueSizeInBits(), 1))) { bool TrueWhenTrue = (Cond == ISD::SETEQ) ^ (!N1C->isOne()); if (TrueWhenTrue) return DAG.getNode(ISD::TRUNCATE, dl, VT, N0); // Invert the condition. - ISD::CondCode CC = cast(N0.getOperand(2))->get(); - CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); - if (DCI.isBeforeLegalizeOps() || - isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) - return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); + if (N0.getOpcode() == ISD::SETCC) { + ISD::CondCode CC = cast(N0.getOperand(2))->get(); + CC = ISD::getSetCCInverse(CC, N0.getOperand(0).getValueType()); + if (DCI.isBeforeLegalizeOps() || + isCondCodeLegal(CC, N0.getOperand(0).getSimpleValueType())) + return DAG.getSetCC(dl, VT, N0.getOperand(0), N0.getOperand(1), CC); + } } if ((N0.getOpcode() == ISD::XOR || diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp index fe7bed760572ba126203c97c845ec4a9d3a08952..16cd14ba3de9bdef6dbdc39bb76e3ead9d9ef519 100644 --- a/llvm/lib/CodeGen/TargetLoweringBase.cpp +++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp @@ -1738,15 +1738,8 @@ void llvm::GetReturnInfo(CallingConv::ID CC, Type *ReturnType, else if (attr.hasRetAttr(Attribute::ZExt)) ExtendKind = ISD::ZERO_EXTEND; - // FIXME: C calling convention requires the return type to be promoted to - // at least 32-bit. But this is not necessary for non-C calling - // conventions. The frontend should mark functions whose return values - // require promoting with signext or zeroext attributes. - if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) { - MVT MinVT = TLI.getRegisterType(MVT::i32); - if (VT.bitsLT(MinVT)) - VT = MinVT; - } + if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) + VT = TLI.getTypeForExtReturn(ReturnType->getContext(), VT, ExtendKind); unsigned NumParts = TLI.getNumRegistersForCallingConv(ReturnType->getContext(), CC, VT); diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index 74d7904aee33a2d732b754d33b71a193f970807e..ebacbc420f8580a8189a083fc8fcdb206f154075 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -1929,21 +1929,27 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { Register DstReg = MI.getOperand(0).getReg(); SmallVector OrigRegs; + VNInfo *DefVN = nullptr; if (LIS) { OrigRegs.push_back(MI.getOperand(0).getReg()); for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) OrigRegs.push_back(MI.getOperand(i).getReg()); + if (LIS->hasInterval(DstReg)) { + DefVN = LIS->getInterval(DstReg) + .Query(LIS->getInstructionIndex(MI)) + .valueOut(); + } } + LaneBitmask UndefLanes = LaneBitmask::getNone(); bool DefEmitted = false; - bool DefIsPartial = false; for (unsigned i = 1, e = MI.getNumOperands(); i < e; i += 2) { MachineOperand &UseMO = MI.getOperand(i); Register SrcReg = UseMO.getReg(); unsigned SubIdx = MI.getOperand(i+1).getImm(); // Nothing needs to be inserted for undef operands. if (UseMO.isUndef()) { - DefIsPartial = true; + UndefLanes |= TRI->getSubRegIndexLaneMask(SubIdx); continue; } @@ -1991,11 +1997,25 @@ eliminateRegSequence(MachineBasicBlock::iterator &MBBI) { MI.removeOperand(j); } else { if (LIS) { - // Force interval recomputation if we moved from full definition - // of register to partial. - if (DefIsPartial && LIS->hasInterval(DstReg) && - MRI->shouldTrackSubRegLiveness(DstReg)) + // Force live interval recomputation if we moved to a partial definition + // of the register. Undef flags must be propagate to uses of undefined + // subregister for accurate interval computation. + if (UndefLanes.any() && DefVN && MRI->shouldTrackSubRegLiveness(DstReg)) { + auto &LI = LIS->getInterval(DstReg); + for (MachineOperand &UseOp : MRI->use_operands(DstReg)) { + unsigned SubReg = UseOp.getSubReg(); + if (UseOp.isUndef() || !SubReg) + continue; + auto *VN = + LI.getVNInfoAt(LIS->getInstructionIndex(*UseOp.getParent())); + if (DefVN != VN) + continue; + LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg); + if ((UndefLanes & LaneMask).any()) + UseOp.setIsUndef(true); + } LIS->removeInterval(DstReg); + } LIS->RemoveMachineInstrFromMaps(MI); } diff --git a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp index b5b76130c55eb91d53b94ec9ba44861b9f3c6d62..1250c0defd314a2019f09982585aed64a7cd3fa3 100644 --- a/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp +++ b/llvm/lib/ExecutionEngine/GDBRegistrationListener.cpp @@ -56,9 +56,9 @@ extern "C" { namespace { // FIXME: lli aims to provide both, RuntimeDyld and JITLink, as the dynamic -// loaders for it's JIT implementations. And they both offer debugging via the +// loaders for its JIT implementations. And they both offer debugging via the // GDB JIT interface, which builds on the two well-known symbol names below. -// As these symbols must be unique accross the linked executable, we can only +// As these symbols must be unique across the linked executable, we can only // define them in one of the libraries and make the other depend on it. // OrcTargetProcess is a minimal stub for embedding a JIT client in remote // executors. For the moment it seems reasonable to have the definition there diff --git a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp index d0701ba08bd91941ce39fd95ed736e5d1fd4eb1b..2fcdfcf9c0669e88cabf0d5861213902650322a9 100644 --- a/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp +++ b/llvm/lib/ExecutionEngine/JITLink/ELF_riscv.cpp @@ -525,7 +525,8 @@ static RelaxAux initRelaxAux(LinkGraph &G) { RelaxAux Aux; Aux.Config.IsRV32 = G.getTargetTriple().isRISCV32(); const auto &Features = G.getFeatures().getFeatures(); - Aux.Config.HasRVC = llvm::is_contained(Features, "+c"); + Aux.Config.HasRVC = llvm::is_contained(Features, "+c") || + llvm::is_contained(Features, "+zca"); for (auto &S : G.sections()) { if (!shouldRelax(S)) diff --git a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp index 76a8eebdb36222c2471516babf70fbcd5a7dff83..fec1bdbe9d8c7436dbb967b52a8c8d9180524832 100644 --- a/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp +++ b/llvm/lib/Frontend/Offloading/OffloadWrapper.cpp @@ -112,7 +112,8 @@ PointerType *getBinDescPtrTy(Module &M) { /// /// Global variable that represents BinDesc is returned. GlobalVariable *createBinDesc(Module &M, ArrayRef> Bufs, - EntryArrayTy EntryArray, StringRef Suffix) { + EntryArrayTy EntryArray, StringRef Suffix, + bool Relocatable) { LLVMContext &C = M.getContext(); auto [EntriesB, EntriesE] = EntryArray; @@ -129,7 +130,8 @@ GlobalVariable *createBinDesc(Module &M, ArrayRef> Bufs, GlobalVariable::InternalLinkage, Data, ".omp_offloading.device_image" + Suffix); Image->setUnnamedAddr(GlobalValue::UnnamedAddr::Global); - Image->setSection(".llvm.offloading"); + Image->setSection(Relocatable ? ".llvm.offloading.relocatable" + : ".llvm.offloading"); Image->setAlignment(Align(object::OffloadBinary::getAlignment())); StringRef Binary(Buf.data(), Buf.size()); @@ -582,8 +584,9 @@ void createRegisterFatbinFunction(Module &M, GlobalVariable *FatbinDesc, Error offloading::wrapOpenMPBinaries(Module &M, ArrayRef> Images, EntryArrayTy EntryArray, - llvm::StringRef Suffix) { - GlobalVariable *Desc = createBinDesc(M, Images, EntryArray, Suffix); + llvm::StringRef Suffix, bool Relocatable) { + GlobalVariable *Desc = + createBinDesc(M, Images, EntryArray, Suffix, Relocatable); if (!Desc) return createStringError(inconvertibleErrorCode(), "No binary descriptors created."); diff --git a/llvm/lib/IR/AsmWriter.cpp b/llvm/lib/IR/AsmWriter.cpp index 35a98767a8be307a23fd649c2c800040aba84ddc..c6ef332403fd6d018ca3b501b8966fd53a8e180e 100644 --- a/llvm/lib/IR/AsmWriter.cpp +++ b/llvm/lib/IR/AsmWriter.cpp @@ -1309,8 +1309,8 @@ void SlotTracker::CreateMetadataSlot(const MDNode *N) { ++mdnNext; // Recursively add any MDNodes referenced by operands. - for (const MDOperand &MDO : N->operands()) - if (const MDNode *Op = dyn_cast_or_null(MDO)) + for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) + if (const MDNode *Op = dyn_cast_or_null(N->getOperand(i))) CreateMetadataSlot(Op); } @@ -4092,12 +4092,6 @@ void AssemblyWriter::printInfoComment(const Value &V) { if (AnnotationWriter) { AnnotationWriter->printInfoComment(V, Out); - } else if (const Instruction *I = dyn_cast(&V)) { - if (I->DbgMarker) { - // In the new, experimental DPValue representation of debug-info, print - // out which instructions have DPMarkers and where they are. - Out << "; dbgmarker @ " << I->DbgMarker; - } } } diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 19d80eb9aec0b3aef6a4fa3c07706bb5fdf43b82..b90bbe71ac1896b63210a30e5b39131d73595f62 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -5209,8 +5209,8 @@ static Metadata *upgradeLoopArgument(Metadata *MD) { SmallVector Ops; Ops.reserve(T->getNumOperands()); Ops.push_back(upgradeLoopTag(T->getContext(), OldTag->getString())); - for (const MDOperand &MDO : llvm::drop_begin(T->operands())) - Ops.push_back(MDO); + for (unsigned I = 1, E = T->getNumOperands(); I != E; ++I) + Ops.push_back(T->getOperand(I)); return MDTuple::get(T->getContext(), Ops); } diff --git a/llvm/lib/IR/BasicBlock.cpp b/llvm/lib/IR/BasicBlock.cpp index dca5283283847017aee6f14033878eab3b1ce21a..bb55f48df4b314061f4593ffe158ba109325745f 100644 --- a/llvm/lib/IR/BasicBlock.cpp +++ b/llvm/lib/IR/BasicBlock.cpp @@ -81,8 +81,10 @@ void BasicBlock::convertToNewDbgValues() { continue; } - // Create a marker to store DPValues in. Technically we don't need to store - // one marker per instruction, but that's a future optimisation. + if (DPVals.empty()) + continue; + + // Create a marker to store DPValues in. createMarker(&I); DPMarker *Marker = I.DbgMarker; @@ -769,6 +771,7 @@ void BasicBlock::flushTerminatorDbgValues() { return; // Transfer DPValues from the trailing position onto the terminator. + createMarker(Term); Term->DbgMarker->absorbDebugValues(*TrailingDPValues, false); TrailingDPValues->eraseFromParent(); deleteTrailingDPValues(); @@ -812,10 +815,9 @@ void BasicBlock::spliceDebugInfoEmptyBlock(BasicBlock::iterator Dest, if (!SrcTrailingDPValues) return; - DPMarker *M = Dest->DbgMarker; - M->absorbDebugValues(*SrcTrailingDPValues, InsertAtHead); - SrcTrailingDPValues->eraseFromParent(); - Src->deleteTrailingDPValues(); + Dest->adoptDbgValues(Src, Src->end(), InsertAtHead); + // adoptDbgValues should have released the trailing DPValues. + assert(!Src->getTrailingDPValues()); return; } @@ -882,7 +884,6 @@ void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src, } if (First->hasDbgValues()) { - DPMarker *CurMarker = Src->getMarker(First); // Place them at the front, it would look like this: // Dest // | @@ -890,8 +891,7 @@ void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src, // Src-block: ~~~~~~~~++++B---B---B---B:::C // | | // First Last - CurMarker->absorbDebugValues(*OurTrailingDPValues, true); - OurTrailingDPValues->eraseFromParent(); + First->adoptDbgValues(this, end(), true); } else { // No current marker, create one and absorb in. (FIXME: we can avoid an // allocation in the future). @@ -911,7 +911,8 @@ void BasicBlock::spliceDebugInfo(BasicBlock::iterator Dest, BasicBlock *Src, if (!MoreDanglingDPValues) return; - // FIXME: we could avoid an allocation here sometimes. + // FIXME: we could avoid an allocation here sometimes. (adoptDbgValues + // requires an iterator). DPMarker *LastMarker = Src->createMarker(Last); LastMarker->absorbDebugValues(*MoreDanglingDPValues, true); MoreDanglingDPValues->eraseFromParent(); @@ -993,20 +994,22 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, // Detach the marker at Dest -- this lets us move the "====" DPValues around. DPMarker *DestMarker = nullptr; if (Dest != end()) { - DestMarker = getMarker(Dest); - DestMarker->removeFromParent(); - createMarker(&*Dest); + if ((DestMarker = getMarker(Dest))) + DestMarker->removeFromParent(); } // If we're moving the tail range of DPValues (":::"), absorb them into the // front of the DPValues at Dest. if (ReadFromTail && Src->getMarker(Last)) { - DPMarker *OntoDest = getMarker(Dest); DPMarker *FromLast = Src->getMarker(Last); - OntoDest->absorbDebugValues(*FromLast, true); if (LastIsEnd) { - FromLast->eraseFromParent(); - Src->deleteTrailingDPValues(); + Dest->adoptDbgValues(Src, Last, true); + // adoptDbgValues will release any trailers. + assert(!Src->getTrailingDPValues()); + } else { + // FIXME: can we use adoptDbgValues here to reduce allocations? + DPMarker *OntoDest = createMarker(Dest); + OntoDest->absorbDebugValues(*FromLast, true); } } @@ -1014,10 +1017,14 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, // move their markers onto Last. They remain in the Src block. No action // needed. if (!ReadFromHead && First->hasDbgValues()) { - DPMarker *OntoLast = Src->createMarker(Last); - DPMarker *FromFirst = Src->createMarker(First); - OntoLast->absorbDebugValues(*FromFirst, - true); // Always insert at head of it. + if (Last != Src->end()) { + Last->adoptDbgValues(Src, First, true); + } else { + DPMarker *OntoLast = Src->createMarker(Last); + DPMarker *FromFirst = Src->createMarker(First); + // Always insert at front of Last. + OntoLast->absorbDebugValues(*FromFirst, true); + } } // Finally, do something with the "====" DPValues we detached. @@ -1025,12 +1032,12 @@ void BasicBlock::spliceDebugInfoImpl(BasicBlock::iterator Dest, BasicBlock *Src, if (InsertAtHead) { // Insert them at the end of the DPValues at Dest. The "::::" DPValues // might be in front of them. - DPMarker *NewDestMarker = getMarker(Dest); + DPMarker *NewDestMarker = createMarker(Dest); NewDestMarker->absorbDebugValues(*DestMarker, false); } else { // Insert them right at the start of the range we moved, ahead of First // and the "++++" DPValues. - DPMarker *FirstMarker = getMarker(First); + DPMarker *FirstMarker = createMarker(First); FirstMarker->absorbDebugValues(*DestMarker, true); } DestMarker->eraseFromParent(); @@ -1082,9 +1089,7 @@ void BasicBlock::insertDPValueAfter(DPValue *DPV, Instruction *I) { assert(I->getParent() == this); iterator NextIt = std::next(I->getIterator()); - DPMarker *NextMarker = getMarker(NextIt); - if (!NextMarker) - NextMarker = createMarker(NextIt); + DPMarker *NextMarker = createMarker(NextIt); NextMarker->insertDPValue(DPV, true); } @@ -1097,6 +1102,7 @@ void BasicBlock::insertDPValueBefore(DPValue *DPV, if (!Where->DbgMarker) createMarker(Where); bool InsertAtHead = Where.getHeadBit(); + createMarker(&*Where); Where->DbgMarker->insertDPValue(DPV, InsertAtHead); } diff --git a/llvm/lib/IR/DebugInfo.cpp b/llvm/lib/IR/DebugInfo.cpp index 2cf88292b14ed6a8357b7a3ace00b73952ab41b6..d8c1b0d534f61580a000caaf26465c5f0723d497 100644 --- a/llvm/lib/IR/DebugInfo.cpp +++ b/llvm/lib/IR/DebugInfo.cpp @@ -400,8 +400,8 @@ static MDNode *updateLoopMetadataDebugLocationsImpl( // Save space for the self-referential LoopID. SmallVector MDs = {nullptr}; - for (const MDOperand &MDO : llvm::drop_begin(OrigLoopID->operands())) { - Metadata *MD = MDO; + for (unsigned i = 1; i < OrigLoopID->getNumOperands(); ++i) { + Metadata *MD = OrigLoopID->getOperand(i); if (!MD) MDs.push_back(nullptr); else if (Metadata *NewMD = Updater(MD)) diff --git a/llvm/lib/IR/DebugProgramInstruction.cpp b/llvm/lib/IR/DebugProgramInstruction.cpp index 03085b3bfd1279cf223777ff7205794e5e7798a5..a2640d59242ac2981d433cf347c8749bb9c0164c 100644 --- a/llvm/lib/IR/DebugProgramInstruction.cpp +++ b/llvm/lib/IR/DebugProgramInstruction.cpp @@ -286,6 +286,7 @@ DPValue::createDebugIntrinsic(Module *M, Instruction *InsertBefore) const { // Create the intrinsic from this DPValue's information, optionally insert // into the target location. DbgVariableIntrinsic *DVI; + assert(getRawLocation() && "DPValue's RawLocation should be non-null."); if (isDbgAssign()) { Value *AssignArgs[] = { MetadataAsValue::get(Context, getRawLocation()), @@ -434,13 +435,23 @@ void DPMarker::removeMarker() { // instruction. If there isn't a next instruction, put them on the // "trailing" list. DPMarker *NextMarker = Owner->getParent()->getNextMarker(Owner); - if (NextMarker == nullptr) { - NextMarker = new DPMarker(); - Owner->getParent()->setTrailingDPValues(NextMarker); + if (NextMarker) { + NextMarker->absorbDebugValues(*this, true); + eraseFromParent(); + } else { + // We can avoid a deallocation -- just store this marker onto the next + // instruction. Unless we're at the end of the block, in which case this + // marker becomes the trailing marker of a degenerate block. + BasicBlock::iterator NextIt = std::next(Owner->getIterator()); + if (NextIt == getParent()->end()) { + getParent()->setTrailingDPValues(this); + MarkedInstr = nullptr; + } else { + NextIt->DbgMarker = this; + MarkedInstr = &*NextIt; + } } - NextMarker->absorbDebugValues(*this, true); - - eraseFromParent(); + Owner->DbgMarker = nullptr; } void DPMarker::removeFromParent() { diff --git a/llvm/lib/IR/Function.cpp b/llvm/lib/IR/Function.cpp index d3e2ae0dede454410f9d270571801ea86e5f1e28..22e2455462bf445a10f0702d76069347511887c8 100644 --- a/llvm/lib/IR/Function.cpp +++ b/llvm/lib/IR/Function.cpp @@ -1976,9 +1976,10 @@ DenseSet Function::getImportGUIDs() const { if (MDNode *MD = getMetadata(LLVMContext::MD_prof)) if (MDString *MDS = dyn_cast(MD->getOperand(0))) if (MDS->getString().equals("function_entry_count")) - for (const MDOperand &MDO : llvm::drop_begin(MD->operands(), 2)) - R.insert( - mdconst::extract(MDO)->getValue().getZExtValue()); + for (unsigned i = 2; i < MD->getNumOperands(); i++) + R.insert(mdconst::extract(MD->getOperand(i)) + ->getValue() + .getZExtValue()); return R; } diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index 904ce17fb0e7c97439d2204c57b0ff3189314244..23a3e72da51d447eaf6a95a987cfe8717be61461 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -111,11 +111,6 @@ void Instruction::insertAfter(Instruction *InsertPos) { BasicBlock *DestParent = InsertPos->getParent(); DestParent->getInstList().insertAfter(InsertPos->getIterator(), this); - - // No need to manually update DPValues: if we insert after an instruction - // position, then we can never have any DPValues on "this". - if (DestParent->IsNewDbgInfoFormat) - DestParent->createMarker(this); } BasicBlock::iterator Instruction::insertInto(BasicBlock *ParentBB, @@ -138,17 +133,15 @@ void Instruction::insertBefore(BasicBlock &BB, if (!BB.IsNewDbgInfoFormat) return; - BB.createMarker(this); - // We've inserted "this": if InsertAtHead is set then it comes before any // DPValues attached to InsertPos. But if it's not set, then any DPValues // should now come before "this". bool InsertAtHead = InsertPos.getHeadBit(); if (!InsertAtHead) { DPMarker *SrcMarker = BB.getMarker(InsertPos); - // If there's no source marker, InsertPos is very likely end(). - if (SrcMarker) - DbgMarker->absorbDebugValues(*SrcMarker, false); + if (SrcMarker && !SrcMarker->empty()) { + adoptDbgValues(&BB, InsertPos, false); + } } // If we're inserting a terminator, check if we need to flush out @@ -212,14 +205,13 @@ void Instruction::moveBeforeImpl(BasicBlock &BB, InstListType::iterator I, BB.getInstList().splice(I, getParent()->getInstList(), getIterator()); if (BB.IsNewDbgInfoFormat && !Preserve) { - if (!DbgMarker) - BB.createMarker(this); DPMarker *NextMarker = getParent()->getNextMarker(this); // If we're inserting at point I, and not in front of the DPValues attached // there, then we should absorb the DPValues attached to I. - if (NextMarker && !InsertAtHead) - DbgMarker->absorbDebugValues(*NextMarker, false); + if (!InsertAtHead && NextMarker && !NextMarker->empty()) { + adoptDbgValues(&BB, I, false); + } } if (isTerminator()) @@ -258,6 +250,48 @@ std::optional Instruction::getDbgReinsertionPosition() { bool Instruction::hasDbgValues() const { return !getDbgValueRange().empty(); } +void Instruction::adoptDbgValues(BasicBlock *BB, BasicBlock::iterator It, + bool InsertAtHead) { + DPMarker *SrcMarker = BB->getMarker(It); + auto ReleaseTrailingDPValues = [BB, It, SrcMarker]() { + if (BB->end() == It) { + SrcMarker->eraseFromParent(); + BB->deleteTrailingDPValues(); + } + }; + + if (!SrcMarker || SrcMarker->StoredDPValues.empty()) { + ReleaseTrailingDPValues(); + return; + } + + // If we have DPMarkers attached to this instruction, we have to honour the + // ordering of DPValues between this and the other marker. Fall back to just + // absorbing from the source. + if (DbgMarker || It == BB->end()) { + // Ensure we _do_ have a marker. + getParent()->createMarker(this); + DbgMarker->absorbDebugValues(*SrcMarker, InsertAtHead); + + // Having transferred everything out of SrcMarker, we _could_ clean it up + // and free the marker now. However, that's a lot of heap-accounting for a + // small amount of memory with a good chance of re-use. Leave it for the + // moment. It will be released when the Instruction is freed in the worst + // case. + // However: if we transferred from a trailing marker off the end of the + // block, it's important to not leave the empty marker trailing. It will + // give a misleading impression that some debug records have been left + // trailing. + ReleaseTrailingDPValues(); + } else { + // Optimisation: we're transferring all the DPValues from the source marker + // onto this empty location: just adopt the other instructions marker. + DbgMarker = SrcMarker; + DbgMarker->MarkedInstr = this; + It->DbgMarker = nullptr; + } +} + void Instruction::dropDbgValues() { if (DbgMarker) DbgMarker->dropDPValues(); diff --git a/llvm/lib/IR/Metadata.cpp b/llvm/lib/IR/Metadata.cpp index 37017a222d4853daf0b876a931062016604890de..06db91fe4f8e74b00ac9631dd8113c4eaea6f6b5 100644 --- a/llvm/lib/IR/Metadata.cpp +++ b/llvm/lib/IR/Metadata.cpp @@ -158,6 +158,12 @@ void DebugValueUser::handleChangedValue(void *Old, Metadata *New) { // getOwner, if needed. auto OldMD = static_cast(Old); ptrdiff_t Idx = std::distance(&*DebugValues.begin(), OldMD); + // If replacing a ValueAsMetadata with a nullptr, replace it with a + // PoisonValue instead. + if (OldMD && isa(*OldMD) && !New) { + auto *OldVAM = cast(*OldMD); + New = ValueAsMetadata::get(PoisonValue::get(OldVAM->getValue()->getType())); + } resetDebugValue(Idx, New); } diff --git a/llvm/lib/IR/ProfDataUtils.cpp b/llvm/lib/IR/ProfDataUtils.cpp index dcb057c1b25fd86bbd2d9dbf6cd4616e36643507..b1a10d0ce5a522637c12f65395a1c737152fd0b2 100644 --- a/llvm/lib/IR/ProfDataUtils.cpp +++ b/llvm/lib/IR/ProfDataUtils.cpp @@ -162,8 +162,8 @@ bool extractProfTotalWeight(const MDNode *ProfileData, uint64_t &TotalVal) { return false; if (ProfDataName->getString().equals("branch_weights")) { - for (const MDOperand &MDO : llvm::drop_begin(ProfileData->operands())) { - auto *V = mdconst::dyn_extract(MDO); + for (unsigned Idx = 1; Idx < ProfileData->getNumOperands(); Idx++) { + auto *V = mdconst::dyn_extract(ProfileData->getOperand(Idx)); assert(V && "Malformed branch_weight in MD_prof node"); TotalVal += V->getValue().getZExtValue(); } diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index 8d992c232ca7cef5bb49efe53b63dd4ef3cd2538..b04d39c700a8f50262fcfe2f15013ae338ac181c 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -2913,8 +2913,8 @@ void Verifier::visitFunction(const Function &F) { VisitDebugLoc(I, I.getDebugLoc().getAsMDNode()); // The llvm.loop annotations also contain two DILocations. if (auto MD = I.getMetadata(LLVMContext::MD_loop)) - for (const MDOperand &MDO : llvm::drop_begin(MD->operands())) - VisitDebugLoc(I, dyn_cast_or_null(MDO)); + for (unsigned i = 1; i < MD->getNumOperands(); ++i) + VisitDebugLoc(I, dyn_cast_or_null(MD->getOperand(i))); if (BrokenDebugInfo) return; } @@ -4713,7 +4713,8 @@ void Verifier::visitProfMetadata(Instruction &I, MDNode *MD) { Check(MD->getNumOperands() == 1 + ExpectedNumOperands, "Wrong number of operands", MD); } - for (const MDOperand &MDO : llvm::drop_begin(MD->operands())) { + for (unsigned i = 1; i < MD->getNumOperands(); ++i) { + auto &MDO = MD->getOperand(i); Check(MDO, "second operand should not be null", MD); Check(mdconst::dyn_extract(MDO), "!prof brunch_weights operand is not a const int"); diff --git a/llvm/lib/Linker/IRMover.cpp b/llvm/lib/Linker/IRMover.cpp index 8cc0f7fb90991629426e55aa4a258e245a20591a..37d21119447b9ca03c167a43bb5493b810a4f786 100644 --- a/llvm/lib/Linker/IRMover.cpp +++ b/llvm/lib/Linker/IRMover.cpp @@ -1775,6 +1775,8 @@ IRMover::IRMover(Module &M) : Composite(M) { Error IRMover::move(std::unique_ptr Src, ArrayRef ValuesToLink, LazyCallback AddLazyFor, bool IsPerformingImport) { + if (getModule().IsNewDbgInfoFormat) + Src->convertToNewDbgValues(); IRLinker TheIRLinker(Composite, SharedMDs, IdentifiedStructTypes, std::move(Src), ValuesToLink, std::move(AddLazyFor), IsPerformingImport); diff --git a/llvm/lib/MC/MCAsmStreamer.cpp b/llvm/lib/MC/MCAsmStreamer.cpp index a4dbd8cc154462be3249f7ac4d44a22b8c73643c..3dc70a401589299a6a90aa9b9e0faac0637d997d 100644 --- a/llvm/lib/MC/MCAsmStreamer.cpp +++ b/llvm/lib/MC/MCAsmStreamer.cpp @@ -1590,17 +1590,22 @@ void MCAsmStreamer::emitFileDirective(StringRef Filename, assert(MAI->hasFourStringsDotFile()); OS << "\t.file\t"; PrintQuotedString(Filename, OS); - OS << ","; - if (!CompilerVersion.empty()) { - PrintQuotedString(CompilerVersion, OS); - } - if (!TimeStamp.empty()) { - OS << ","; - PrintQuotedString(TimeStamp, OS); - } - if (!Description.empty()) { + bool useTimeStamp = !TimeStamp.empty(); + bool useCompilerVersion = !CompilerVersion.empty(); + bool useDescription = !Description.empty(); + if (useTimeStamp || useCompilerVersion || useDescription) { OS << ","; - PrintQuotedString(Description, OS); + if (useTimeStamp) + PrintQuotedString(TimeStamp, OS); + if (useCompilerVersion || useDescription) { + OS << ","; + if (useCompilerVersion) + PrintQuotedString(CompilerVersion, OS); + if (useDescription) { + OS << ","; + PrintQuotedString(Description, OS); + } + } } EmitEOL(); } diff --git a/llvm/lib/MC/MCObjectStreamer.cpp b/llvm/lib/MC/MCObjectStreamer.cpp index bb4a92434a141ceb8f68dcaf4d92d1903328d76e..490e0a4dd404178742ef3c4f15161697cc0c869a 100644 --- a/llvm/lib/MC/MCObjectStreamer.cpp +++ b/llvm/lib/MC/MCObjectStreamer.cpp @@ -902,7 +902,9 @@ void MCObjectStreamer::emitFileDirective(StringRef Filename, StringRef TimeStamp, StringRef Description) { getAssembler().addFileName(Filename); - // TODO: add additional info to integrated assembler. + getAssembler().setCompilerVersion(CompilerVersion.str()); + // TODO: add TimeStamp and Description to .file symbol table entry + // with the integrated assembler. } void MCObjectStreamer::emitAddrsig() { diff --git a/llvm/lib/MC/XCOFFObjectWriter.cpp b/llvm/lib/MC/XCOFFObjectWriter.cpp index 11f8a72edeadafcfa87a0ed4f1efe63c69671047..8809af2e5e0c18f9fa12bf220067a46fb2460492 100644 --- a/llvm/lib/MC/XCOFFObjectWriter.cpp +++ b/llvm/lib/MC/XCOFFObjectWriter.cpp @@ -361,6 +361,8 @@ class XCOFFObjectWriter : public MCObjectWriter { bool is64Bit() const { return TargetObjectWriter->is64Bit(); } bool nameShouldBeInStringTable(const StringRef &); void writeSymbolName(const StringRef &); + bool auxFileSymNameShouldBeInStringTable(const StringRef &); + void writeAuxFileSymName(const StringRef &); void writeSymbolEntryForCsectMemberLabel(const Symbol &SymbolRef, const XCOFFSection &CSectionRef, @@ -391,7 +393,8 @@ class XCOFFObjectWriter : public MCObjectWriter { const MCAsmLayout &Layout, CInfoSymSectionEntry &CInfoSymEntry, uint64_t &CurrentAddressLocation); - void writeSymbolTable(const MCAsmLayout &Layout); + void writeSymbolTable(MCAssembler &Asm, const MCAsmLayout &Layout); + void writeSymbolAuxFileEntry(StringRef &Name, uint8_t ftype); void writeSymbolAuxDwarfEntry(uint64_t LengthOfSectionPortion, uint64_t NumberOfRelocEnt = 0); void writeSymbolAuxCsectEntry(uint64_t SectionOrLength, @@ -416,7 +419,7 @@ class XCOFFObjectWriter : public MCObjectWriter { // *) Assigns symbol table indices. // *) Builds up the section header table by adding any non-empty sections to // `Sections`. - void assignAddressesAndIndices(const MCAsmLayout &); + void assignAddressesAndIndices(MCAssembler &Asm, const MCAsmLayout &); // Called after relocations are recorded. void finalizeSectionInfo(); void finalizeRelocationInfo(SectionEntry *Sec, uint64_t RelCount); @@ -640,12 +643,20 @@ void XCOFFObjectWriter::executePostLayoutBinding(MCAssembler &Asm, if (FileNames.empty()) FileNames.emplace_back(".file", 0); for (const std::pair &F : FileNames) { - if (nameShouldBeInStringTable(F.first)) + if (auxFileSymNameShouldBeInStringTable(F.first)) Strings.add(F.first); } + // Always add ".file" to the symbol table. The actual file name will be in + // the AUX_FILE auxiliary entry. + if (nameShouldBeInStringTable(".file")) + Strings.add(".file"); + StringRef Vers = Asm.getCompilerVersion(); + if (auxFileSymNameShouldBeInStringTable(Vers)) + Strings.add(Vers); + Strings.finalize(); - assignAddressesAndIndices(Layout); + assignAddressesAndIndices(Asm, Layout); } void XCOFFObjectWriter::recordRelocation(MCAssembler &Asm, @@ -818,7 +829,7 @@ uint64_t XCOFFObjectWriter::writeObject(MCAssembler &Asm, writeSectionHeaderTable(); writeSections(Asm, Layout); writeRelocations(); - writeSymbolTable(Layout); + writeSymbolTable(Asm, Layout); // Write the string table. Strings.write(W.OS); @@ -878,6 +889,36 @@ void XCOFFObjectWriter::writeSymbolAuxCsectEntry(uint64_t SectionOrLength, } } +bool XCOFFObjectWriter::auxFileSymNameShouldBeInStringTable( + const StringRef &SymbolName) { + return SymbolName.size() > XCOFF::AuxFileEntNameSize; +} + +void XCOFFObjectWriter::writeAuxFileSymName(const StringRef &SymbolName) { + // Magic, Offset or SymbolName. + if (auxFileSymNameShouldBeInStringTable(SymbolName)) { + W.write(0); + W.write(Strings.getOffset(SymbolName)); + W.OS.write_zeros(XCOFF::FileNamePadSize); + } else { + char Name[XCOFF::AuxFileEntNameSize + 1]; + std::strncpy(Name, SymbolName.data(), XCOFF::AuxFileEntNameSize); + ArrayRef NameRef(Name, XCOFF::AuxFileEntNameSize); + W.write(NameRef); + } +} + +void XCOFFObjectWriter::writeSymbolAuxFileEntry(StringRef &Name, + uint8_t ftype) { + writeAuxFileSymName(Name); + W.write(ftype); + W.OS.write_zeros(2); + if (is64Bit()) + W.write(XCOFF::AUX_FILE); + else + W.OS.write_zeros(1); +} + void XCOFFObjectWriter::writeSymbolAuxDwarfEntry( uint64_t LengthOfSectionPortion, uint64_t NumberOfRelocEnt) { writeWord(LengthOfSectionPortion); @@ -1109,8 +1150,11 @@ void XCOFFObjectWriter::writeRelocations() { writeRelocation(Reloc, *DwarfSection.DwarfSect); } -void XCOFFObjectWriter::writeSymbolTable(const MCAsmLayout &Layout) { +void XCOFFObjectWriter::writeSymbolTable(MCAssembler &Asm, + const MCAsmLayout &Layout) { // Write C_FILE symbols. + StringRef Vers = Asm.getCompilerVersion(); + for (const std::pair &F : FileNames) { // The n_name of a C_FILE symbol is the source file's name when no auxiliary // entries are present. @@ -1139,9 +1183,15 @@ void XCOFFObjectWriter::writeSymbolTable(const MCAsmLayout &Layout) { else CpuID = XCOFF::TCPU_COM; - writeSymbolEntry(FileName, /*Value=*/0, XCOFF::ReservedSectionNum::N_DEBUG, + int NumberOfFileAuxEntries = 1; + if (!Vers.empty()) + ++NumberOfFileAuxEntries; + writeSymbolEntry(".file", /*Value=*/0, XCOFF::ReservedSectionNum::N_DEBUG, /*SymbolType=*/(LangID << 8) | CpuID, XCOFF::C_FILE, - /*NumberOfAuxEntries=*/0); + NumberOfFileAuxEntries); + writeSymbolAuxFileEntry(FileName, XCOFF::XFT_FN); + if (!Vers.empty()) + writeSymbolAuxFileEntry(Vers, XCOFF::XFT_CV); } if (CInfoSymSection.Entry) @@ -1357,9 +1407,12 @@ void XCOFFObjectWriter::addCInfoSymEntry(StringRef Name, StringRef Metadata) { std::make_unique(Name.str(), Metadata.str())); } -void XCOFFObjectWriter::assignAddressesAndIndices(const MCAsmLayout &Layout) { - // The symbol table starts with all the C_FILE symbols. - uint32_t SymbolTableIndex = FileNames.size(); +void XCOFFObjectWriter::assignAddressesAndIndices(MCAssembler &Asm, + const MCAsmLayout &Layout) { + // The symbol table starts with all the C_FILE symbols. Each C_FILE symbol + // requires 1 or 2 auxiliary entries. + uint32_t SymbolTableIndex = + (2 + (Asm.getCompilerVersion().empty() ? 0 : 1)) * FileNames.size(); if (CInfoSymSection.Entry) SymbolTableIndex++; diff --git a/llvm/lib/ObjCopy/ConfigManager.cpp b/llvm/lib/ObjCopy/ConfigManager.cpp index 10ece49028f21789f2ade68780cda20d74c43968..e46b595a56dc44c94f03e7686292c8d38a677ff2 100644 --- a/llvm/lib/ObjCopy/ConfigManager.cpp +++ b/llvm/lib/ObjCopy/ConfigManager.cpp @@ -15,6 +15,7 @@ namespace objcopy { Expected ConfigManager::getCOFFConfig() const { if (!Common.SplitDWO.empty() || !Common.SymbolsPrefix.empty() || + !Common.SymbolsPrefixRemove.empty() || !Common.AllocSectionsPrefix.empty() || !Common.KeepSection.empty() || !Common.SymbolsToGlobalize.empty() || !Common.SymbolsToKeep.empty() || !Common.SymbolsToLocalize.empty() || !Common.SymbolsToWeaken.empty() || @@ -33,6 +34,7 @@ Expected ConfigManager::getCOFFConfig() const { Expected ConfigManager::getMachOConfig() const { if (!Common.SplitDWO.empty() || !Common.SymbolsPrefix.empty() || + !Common.SymbolsPrefixRemove.empty() || !Common.AllocSectionsPrefix.empty() || !Common.KeepSection.empty() || !Common.SymbolsToGlobalize.empty() || !Common.SymbolsToKeep.empty() || !Common.SymbolsToLocalize.empty() || @@ -54,6 +56,7 @@ Expected ConfigManager::getMachOConfig() const { Expected ConfigManager::getWasmConfig() const { if (!Common.AddGnuDebugLink.empty() || Common.ExtractPartition || !Common.SplitDWO.empty() || !Common.SymbolsPrefix.empty() || + !Common.SymbolsPrefixRemove.empty() || !Common.AllocSectionsPrefix.empty() || Common.DiscardMode != DiscardType::None || !Common.SymbolsToAdd.empty() || !Common.SymbolsToGlobalize.empty() || !Common.SymbolsToLocalize.empty() || @@ -74,6 +77,7 @@ Expected ConfigManager::getWasmConfig() const { Expected ConfigManager::getXCOFFConfig() const { if (!Common.AddGnuDebugLink.empty() || Common.ExtractPartition || !Common.SplitDWO.empty() || !Common.SymbolsPrefix.empty() || + !Common.SymbolsPrefixRemove.empty() || !Common.AllocSectionsPrefix.empty() || Common.DiscardMode != DiscardType::None || !Common.AddSection.empty() || !Common.DumpSection.empty() || !Common.SymbolsToAdd.empty() || diff --git a/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp b/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp index b6d77d17bae36c5afdfb9ba704627b5bb9347bba..36f799446a04fda1f921481635029c0b51fc418e 100644 --- a/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp +++ b/llvm/lib/ObjCopy/ELF/ELFObjcopy.cpp @@ -329,6 +329,11 @@ static Error updateAndRemoveSymbols(const CommonConfig &Config, if (I != Config.SymbolsToRename.end()) Sym.Name = std::string(I->getValue()); + if (!Config.SymbolsPrefixRemove.empty() && Sym.Type != STT_SECTION) + if (Sym.Name.compare(0, Config.SymbolsPrefixRemove.size(), + Config.SymbolsPrefixRemove) == 0) + Sym.Name = Sym.Name.substr(Config.SymbolsPrefixRemove.size()); + if (!Config.SymbolsPrefix.empty() && Sym.Type != STT_SECTION) Sym.Name = (Config.SymbolsPrefix + Sym.Name).str(); }); diff --git a/llvm/lib/Object/COFFImportFile.cpp b/llvm/lib/Object/COFFImportFile.cpp index 60556c149bf735b49840e01130b986b5f9df8770..d7d26f4f4180c377b5e58b81306104190d7df07e 100644 --- a/llvm/lib/Object/COFFImportFile.cpp +++ b/llvm/lib/Object/COFFImportFile.cpp @@ -52,6 +52,32 @@ StringRef COFFImportFile::getFileFormatName() const { } } +StringRef COFFImportFile::getExportName() const { + const coff_import_header *hdr = getCOFFImportHeader(); + StringRef name = Data.getBuffer().substr(sizeof(*hdr)).split('\0').first; + + auto ltrim1 = [](StringRef s, StringRef chars) { + return !s.empty() && chars.contains(s[0]) ? s.substr(1) : s; + }; + + switch (hdr->getNameType()) { + case IMPORT_ORDINAL: + name = ""; + break; + case IMPORT_NAME_NOPREFIX: + name = ltrim1(name, "?@_"); + break; + case IMPORT_NAME_UNDECORATE: + name = ltrim1(name, "?@_"); + name = name.substr(0, name.find('@')); + break; + default: + break; + } + + return name; +} + static uint16_t getImgRelRelocation(MachineTypes Machine) { switch (Machine) { default: diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index 8f7eead02a66c5a171e2b24f64731ebf7e4bc746..38a9e0e99b6b733ef7fa2362bce57f472c33f70f 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -292,7 +292,7 @@ Expected ELFObjectFileBase::getRISCVFeatures() const { unsigned PlatformFlags = getPlatformFlags(); if (PlatformFlags & ELF::EF_RISCV_RVC) { - Features.AddFeature("c"); + Features.AddFeature("zca"); } RISCVAttributeParser Attributes; diff --git a/llvm/lib/Object/OffloadBinary.cpp b/llvm/lib/Object/OffloadBinary.cpp index bfc35e41fe6581cf5eedd1c498f6b575b96c3138..22d604b125c583c9b72f17db3c0c70a180d0cc16 100644 --- a/llvm/lib/Object/OffloadBinary.cpp +++ b/llvm/lib/Object/OffloadBinary.cpp @@ -83,7 +83,7 @@ Error extractFromObject(const ObjectFile &Obj, if (!NameOrErr) return NameOrErr.takeError(); - if (!NameOrErr->equals(".llvm.offloading")) + if (!NameOrErr->starts_with(".llvm.offloading")) continue; } diff --git a/llvm/lib/Object/WasmObjectFile.cpp b/llvm/lib/Object/WasmObjectFile.cpp index 4778562779bb7d2e36b1d01cc2fe2c2d87c0fe34..8c1bbe9c264593447bc496a477335fb7729a8db0 100644 --- a/llvm/lib/Object/WasmObjectFile.cpp +++ b/llvm/lib/Object/WasmObjectFile.cpp @@ -1906,7 +1906,13 @@ Expected WasmObjectFile::getSectionName(DataRefImpl Sec) const { return wasm::sectionTypeToString(S.Type); } -uint64_t WasmObjectFile::getSectionAddress(DataRefImpl Sec) const { return 0; } +uint64_t WasmObjectFile::getSectionAddress(DataRefImpl Sec) const { + // For object files, use 0 for section addresses, and section offsets for + // symbol addresses. For linked files, use file offsets. + // See also getSymbolAddress. + return isRelocatableObject() || isSharedObject() ? 0 + : Sections[Sec.d.a].Offset; +} uint64_t WasmObjectFile::getSectionIndex(DataRefImpl Sec) const { return Sec.d.a; diff --git a/llvm/lib/Passes/CodeGenPassBuilder.cpp b/llvm/lib/Passes/CodeGenPassBuilder.cpp index 927727cba6fc6c83fd7a4de1d92e69a5ccb295ac..16332200f9b4b83ebc4b133dbfc173585ee9c2af 100644 --- a/llvm/lib/Passes/CodeGenPassBuilder.cpp +++ b/llvm/lib/Passes/CodeGenPassBuilder.cpp @@ -16,7 +16,7 @@ using namespace llvm; namespace llvm { -#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define DUMMY_MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ AnalysisKey PASS_NAME::Key; #include "llvm/Passes/MachinePassRegistry.def" } // namespace llvm diff --git a/llvm/lib/Passes/PassBuilder.cpp b/llvm/lib/Passes/PassBuilder.cpp index 0f33af22dbd978215a56f93a765285d83612de96..7c306c4a21daf780dc1cbc533e33f75deaee59db 100644 --- a/llvm/lib/Passes/PassBuilder.cpp +++ b/llvm/lib/Passes/PassBuilder.cpp @@ -76,6 +76,7 @@ #include "llvm/CodeGen/BasicBlockSectionsProfileReader.h" #include "llvm/CodeGen/CallBrPrepare.h" #include "llvm/CodeGen/CodeGenPrepare.h" +#include "llvm/CodeGen/DeadMachineInstructionElim.h" #include "llvm/CodeGen/DwarfEHPrepare.h" #include "llvm/CodeGen/ExpandLargeDivRem.h" #include "llvm/CodeGen/ExpandLargeFpConvert.h" @@ -398,10 +399,10 @@ PassBuilder::PassBuilder(TargetMachine *TM, PipelineTuningOptions PTO, PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); #include "PassRegistry.def" -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - PIC->addClassToPassName(PASS_NAME::name(), NAME); -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - PIC->addClassToPassName(PASS_NAME::name(), NAME); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) \ + PIC->addClassToPassName(decltype(CREATE_PASS)::name(), NAME); #include "llvm/Passes/MachinePassRegistry.def" } } @@ -441,8 +442,8 @@ void PassBuilder::registerFunctionAnalyses(FunctionAnalysisManager &FAM) { void PassBuilder::registerMachineFunctionAnalyses( MachineFunctionAnalysisManager &MFAM) { -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - MFAM.registerPass([&] { return PASS_NAME(); }); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) \ + MFAM.registerPass([&] { return CREATE_PASS; }); #include "llvm/Passes/MachinePassRegistry.def" for (auto &C : MachineFunctionAnalysisRegistrationCallbacks) @@ -1860,14 +1861,14 @@ Error PassBuilder::parseMachinePass(MachineFunctionPassManager &MFPM, return make_error("invalid pipeline", inconvertibleErrorCode()); -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define MACHINE_MODULE_PASS(NAME, CREATE_PASS) \ if (Name == NAME) { \ - MFPM.addPass(PASS_NAME()); \ + MFPM.addPass(CREATE_PASS); \ return Error::success(); \ } -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) \ if (Name == NAME) { \ - MFPM.addPass(PASS_NAME()); \ + MFPM.addPass(CREATE_PASS); \ return Error::success(); \ } #include "llvm/Passes/MachinePassRegistry.def" @@ -2179,18 +2180,15 @@ void PassBuilder::printPassNames(raw_ostream &OS) { #include "PassRegistry.def" OS << "Machine module passes (WIP):\n"; -#define MACHINE_MODULE_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - printPassName(NAME, OS); +#define MACHINE_MODULE_PASS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "llvm/Passes/MachinePassRegistry.def" OS << "Machine function passes (WIP):\n"; -#define MACHINE_FUNCTION_PASS(NAME, PASS_NAME, CONSTRUCTOR) \ - printPassName(NAME, OS); +#define MACHINE_FUNCTION_PASS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "llvm/Passes/MachinePassRegistry.def" OS << "Machine function analyses (WIP):\n"; -#define MACHINE_FUNCTION_ANALYSIS(NAME, PASS_NAME, CONSTRUCTOR) \ - printPassName(NAME, OS); +#define MACHINE_FUNCTION_ANALYSIS(NAME, CREATE_PASS) printPassName(NAME, OS); #include "llvm/Passes/MachinePassRegistry.def" } diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp index 39e43f86eab5e9155e7ded0706ec1340ab763095..6b189c31463283cdfdd44bc64b0f8eca3f4d2795 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -223,6 +223,8 @@ Expected CounterMappingContext::evaluate(const Counter &C) const { return LastPoppedValue; } +namespace { + class MCDCRecordProcessor { /// A bitmap representing the executed test vectors for a boolean expression. /// Each index of the bitmap corresponds to a possible test vector. An index @@ -398,6 +400,8 @@ public: } }; +} // namespace + Expected CounterMappingContext::evaluateMCDCRegion( const CounterMappingRegion &Region, ArrayRef Branches) { @@ -491,20 +495,20 @@ static unsigned getMaxCounterID(const CounterMappingContext &Ctx, /// Returns the bit count static unsigned getMaxBitmapSize(const CounterMappingContext &Ctx, const CoverageMappingRecord &Record) { - unsigned MaxBitmapID = 0; + unsigned MaxBitmapIdx = 0; unsigned NumConditions = 0; // Scan max(BitmapIdx). // Note that `<=` is used insted of `<`, because `BitmapIdx == 0` is valid - // and `MaxBitmapID is `unsigned`. `BitmapIdx` is unique in the record. + // and `MaxBitmapIdx is `unsigned`. `BitmapIdx` is unique in the record. for (const auto &Region : reverse(Record.MappingRegions)) { if (Region.Kind == CounterMappingRegion::MCDCDecisionRegion && - MaxBitmapID <= Region.MCDCParams.BitmapIdx) { - MaxBitmapID = Region.MCDCParams.BitmapIdx; + MaxBitmapIdx <= Region.MCDCParams.BitmapIdx) { + MaxBitmapIdx = Region.MCDCParams.BitmapIdx; NumConditions = Region.MCDCParams.NumConditions; } } unsigned SizeInBits = llvm::alignTo(uint64_t(1) << NumConditions, CHAR_BIT); - return MaxBitmapID * CHAR_BIT + SizeInBits; + return MaxBitmapIdx * CHAR_BIT + SizeInBits; } namespace { diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp index 91e79e8b2e9add269d8c4173bbd9143c0a5753af..9ebcba10c860ff22cbc9ae2b1a0c217c159378df 100644 --- a/llvm/lib/ProfileData/InstrProf.cpp +++ b/llvm/lib/ProfileData/InstrProf.cpp @@ -391,13 +391,12 @@ std::string getPGOName(const GlobalVariable &V, bool InLTO) { return getIRPGOObjectName(V, InLTO, nullptr /* PGONameMetadata */); } -// See getIRPGOFuncName() for a discription of the format. -std::pair -getParsedIRPGOFuncName(StringRef IRPGOFuncName) { - auto [FileName, FuncName] = IRPGOFuncName.split(';'); - if (FuncName.empty()) - return std::make_pair(StringRef(), IRPGOFuncName); - return std::make_pair(FileName, FuncName); +// See getIRPGOObjectName() for a discription of the format. +std::pair getParsedIRPGOName(StringRef IRPGOName) { + auto [FileName, MangledName] = IRPGOName.split(kGlobalIdentifierDelimiter); + if (MangledName.empty()) + return std::make_pair(StringRef(), IRPGOName); + return std::make_pair(FileName, MangledName); } StringRef getFuncNameWithoutPrefix(StringRef PGOFuncName, StringRef FileName) { diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/Support/RISCVISAInfo.cpp index 6fe8eb62e2804059dbc0011adb914645974c76f0..d028302b8c4d94d1ef8031f0e46a95e1850d81b9 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/Support/RISCVISAInfo.cpp @@ -215,6 +215,7 @@ static const RISCVSupportedExtension SupportedExperimentalExtensions[] = { {"smnpm", {0, 8}}, {"ssnpm", {0, 8}}, {"sspm", {0, 8}}, + {"ssqosid", {1, 0}}, {"supm", {0, 8}}, {"zaamo", {0, 2}}, diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index b59f8d7306046315d3b278249098b9c39bcfa55e..8573939b04389fc14717783021bf3d8e1f1f07d7 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -18299,50 +18299,23 @@ static SDValue performConcatVectorsCombine(SDNode *N, if (DCI.isBeforeLegalizeOps()) return SDValue(); - // Optimise concat_vectors of two [us]avgceils or [us]avgfloors that use - // extracted subvectors from the same original vectors. Combine these into a - // single avg that operates on the two original vectors. - // avgceil is the target independant name for rhadd, avgfloor is a hadd. - // Example: - // (concat_vectors (v8i8 (avgceils (extract_subvector (v16i8 OpA, <0>), - // extract_subvector (v16i8 OpB, <0>))), - // (v8i8 (avgceils (extract_subvector (v16i8 OpA, <8>), - // extract_subvector (v16i8 OpB, <8>))))) - // -> - // (v16i8(avgceils(v16i8 OpA, v16i8 OpB))) - if (N->getNumOperands() == 2 && N0Opc == N1Opc && + // Optimise concat_vectors of two [us]avgceils or [us]avgfloors with a 128-bit + // destination size, combine into an avg of two contacts of the source + // vectors. eg: concat(uhadd(a,b), uhadd(c, d)) -> uhadd(concat(a, c), + // concat(b, d)) + if (N->getNumOperands() == 2 && N0Opc == N1Opc && VT.is128BitVector() && (N0Opc == ISD::AVGCEILU || N0Opc == ISD::AVGCEILS || - N0Opc == ISD::AVGFLOORU || N0Opc == ISD::AVGFLOORS)) { + N0Opc == ISD::AVGFLOORU || N0Opc == ISD::AVGFLOORS) && + N0->hasOneUse() && N1->hasOneUse()) { SDValue N00 = N0->getOperand(0); SDValue N01 = N0->getOperand(1); SDValue N10 = N1->getOperand(0); SDValue N11 = N1->getOperand(1); - EVT N00VT = N00.getValueType(); - EVT N10VT = N10.getValueType(); - - if (N00->getOpcode() == ISD::EXTRACT_SUBVECTOR && - N01->getOpcode() == ISD::EXTRACT_SUBVECTOR && - N10->getOpcode() == ISD::EXTRACT_SUBVECTOR && - N11->getOpcode() == ISD::EXTRACT_SUBVECTOR && N00VT == N10VT) { - SDValue N00Source = N00->getOperand(0); - SDValue N01Source = N01->getOperand(0); - SDValue N10Source = N10->getOperand(0); - SDValue N11Source = N11->getOperand(0); - - if (N00Source == N10Source && N01Source == N11Source && - N00Source.getValueType() == VT && N01Source.getValueType() == VT) { - assert(N0.getValueType() == N1.getValueType()); - - uint64_t N00Index = N00.getConstantOperandVal(1); - uint64_t N01Index = N01.getConstantOperandVal(1); - uint64_t N10Index = N10.getConstantOperandVal(1); - uint64_t N11Index = N11.getConstantOperandVal(1); - - if (N00Index == N01Index && N10Index == N11Index && N00Index == 0 && - N10Index == N00VT.getVectorNumElements()) - return DAG.getNode(N0Opc, dl, VT, N00Source, N01Source); - } + if (!N00.isUndef() && !N01.isUndef() && !N10.isUndef() && !N11.isUndef()) { + SDValue Concat0 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N00, N10); + SDValue Concat1 = DAG.getNode(ISD::CONCAT_VECTORS, dl, VT, N01, N11); + return DAG.getNode(N0Opc, dl, VT, Concat0, Concat1); } } diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index f5c5ff6d98aac2130d1991798523aac128568f0b..9add7d87017a73fe1bc67160c1133ddafe0a0fea 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -4206,6 +4206,21 @@ static bool canPairLdStOpc(unsigned FirstOpc, unsigned SecondOpc) { switch (FirstOpc) { default: return false; + case AArch64::STRSui: + case AArch64::STURSi: + return SecondOpc == AArch64::STRSui || SecondOpc == AArch64::STURSi; + case AArch64::STRDui: + case AArch64::STURDi: + return SecondOpc == AArch64::STRDui || SecondOpc == AArch64::STURDi; + case AArch64::STRQui: + case AArch64::STURQi: + return SecondOpc == AArch64::STRQui || SecondOpc == AArch64::STURQi; + case AArch64::STRWui: + case AArch64::STURWi: + return SecondOpc == AArch64::STRWui || SecondOpc == AArch64::STURWi; + case AArch64::STRXui: + case AArch64::STURXi: + return SecondOpc == AArch64::STRXui || SecondOpc == AArch64::STURXi; case AArch64::LDRSui: case AArch64::LDURSi: return SecondOpc == AArch64::LDRSui || SecondOpc == AArch64::LDURSi; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index c476617e679f3d9f9ea463d401bb42584ec6b92f..77fdb688d0422e301817580c9081e6e9093686fb 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -3532,6 +3532,7 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; +let Predicates = [HasFPARMv8] in { def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", @@ -3542,6 +3543,7 @@ def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"ldr $Rt, [$Rn, $offset]", (LDURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; +} // zextload -> i64 def : Pat<(i64 (zextloadi8 (am_unscaled8 GPR64sp:$Rn, simm9:$offset))), @@ -4175,6 +4177,7 @@ def : InstAlias<"str $Rt, [$Rn, $offset]", (STURXi GPR64:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURWi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb32:$offset), 0>; +let Predicates = [HasFPARMv8] in { def : InstAlias<"str $Rt, [$Rn, $offset]", (STURBi FPR8Op:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", @@ -4185,6 +4188,7 @@ def : InstAlias<"str $Rt, [$Rn, $offset]", (STURDi FPR64Op:$Rt, GPR64sp:$Rn, simm9_offset_fb64:$offset), 0>; def : InstAlias<"str $Rt, [$Rn, $offset]", (STURQi FPR128Op:$Rt, GPR64sp:$Rn, simm9_offset_fb128:$offset), 0>; +} def : InstAlias<"strb $Rt, [$Rn, $offset]", (STURBBi GPR32:$Rt, GPR64sp:$Rn, simm9_offset_fb8:$offset), 0>; @@ -4595,8 +4599,10 @@ def FMOVD0 : Pseudo<(outs FPR64:$Rd), (ins), [(set f64:$Rd, (fpimm0))]>, // Similarly add aliases def : InstAlias<"fmov $Rd, #0.0", (FMOVWHr FPR16:$Rd, WZR), 0>, Requires<[HasFullFP16]>; +let Predicates = [HasFPARMv8] in { def : InstAlias<"fmov $Rd, #0.0", (FMOVWSr FPR32:$Rd, WZR), 0>; def : InstAlias<"fmov $Rd, #0.0", (FMOVXDr FPR64:$Rd, XZR), 0>; +} def : Pat<(bf16 fpimm0), (FMOVH0)>; @@ -5040,10 +5046,12 @@ defm NEG : SIMDTwoVectorBHSD<1, 0b01011, "neg", UnOpFrag<(sub immAllZerosV, node:$LHS)> >; defm NOT : SIMDTwoVectorB<1, 0b00, 0b00101, "not", vnot>; // Aliases for MVN -> NOT. +let Predicates = [HasNEON] in { def : InstAlias<"mvn{ $Vd.8b, $Vn.8b|.8b $Vd, $Vn}", (NOTv8i8 V64:$Vd, V64:$Vn)>; def : InstAlias<"mvn{ $Vd.16b, $Vn.16b|.16b $Vd, $Vn}", (NOTv16i8 V128:$Vd, V128:$Vn)>; +} def : Pat<(vnot (v4i16 V64:$Rn)), (NOTv8i8 V64:$Rn)>; def : Pat<(vnot (v8i16 V128:$Rn)), (NOTv16i8 V128:$Rn)>; @@ -5318,6 +5326,7 @@ def : Pat<(AArch64bsp (v4i32 V128:$Rd), V128:$Rn, V128:$Rm), def : Pat<(AArch64bsp (v2i64 V128:$Rd), V128:$Rn, V128:$Rm), (BSPv16i8 V128:$Rd, V128:$Rn, V128:$Rm)>; +let Predicates = [HasNEON] in { def : InstAlias<"mov{\t$dst.16b, $src.16b|.16b\t$dst, $src}", (ORRv16i8 V128:$dst, V128:$src, V128:$src), 1>; def : InstAlias<"mov{\t$dst.8h, $src.8h|.8h\t$dst, $src}", @@ -5495,6 +5504,7 @@ def : InstAlias<"{faclt\t$dst.4s, $src1.4s, $src2.4s" # def : InstAlias<"{faclt\t$dst.2d, $src1.2d, $src2.2d" # "|faclt.2d\t$dst, $src1, $src2}", (FACGTv2f64 V128:$dst, V128:$src2, V128:$src1), 0>; +} //===----------------------------------------------------------------------===// // Advanced SIMD three scalar instructions. @@ -5557,6 +5567,7 @@ defm : FMULScalarFromIndexedLane0Patterns<"FMULX", "16", "32", "64", int_aarch64_neon_fmulx, [HasNEONorSME]>; +let Predicates = [HasNEON] in { def : InstAlias<"cmls $dst, $src1, $src2", (CMHSv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmle $dst, $src1, $src2", @@ -5565,6 +5576,8 @@ def : InstAlias<"cmlo $dst, $src1, $src2", (CMHIv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; def : InstAlias<"cmlt $dst, $src1, $src2", (CMGTv1i64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; +} +let Predicates = [HasFPARMv8] in { def : InstAlias<"fcmle $dst, $src1, $src2", (FCMGE32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"fcmle $dst, $src1, $src2", @@ -5581,6 +5594,7 @@ def : InstAlias<"faclt $dst, $src1, $src2", (FACGT32 FPR32:$dst, FPR32:$src2, FPR32:$src1), 0>; def : InstAlias<"faclt $dst, $src1, $src2", (FACGT64 FPR64:$dst, FPR64:$src2, FPR64:$src1), 0>; +} //===----------------------------------------------------------------------===// // Advanced SIMD three scalar instructions (mixed operands). @@ -7027,6 +7041,7 @@ defm BIC : SIMDModifiedImmVectorShiftTied<1, 0b11, 0b01, "bic", AArch64bici>; // AdvSIMD ORR defm ORR : SIMDModifiedImmVectorShiftTied<0, 0b11, 0b01, "orr", AArch64orri>; +let Predicates = [HasNEON] in { def : InstAlias<"bic $Vd.4h, $imm", (BICv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.8h, $imm", (BICv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"bic $Vd.2s, $imm", (BICv2i32 V64:$Vd, imm0_255:$imm, 0)>; @@ -7046,6 +7061,7 @@ def : InstAlias<"orr.4h $Vd, $imm", (ORRv4i16 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.8h $Vd, $imm", (ORRv8i16 V128:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.2s $Vd, $imm", (ORRv2i32 V64:$Vd, imm0_255:$imm, 0)>; def : InstAlias<"orr.4s $Vd, $imm", (ORRv4i32 V128:$Vd, imm0_255:$imm, 0)>; +} // AdvSIMD FMOV def FMOVv2f64_ns : SIMDModifiedImmVectorNoShift<1, 1, 0, 0b1111, V128, fpimm8, @@ -7129,6 +7145,7 @@ let Predicates = [HasNEON] in { ssub)>; } +let Predicates = [HasNEON] in { def : InstAlias<"movi $Vd.4h, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.8h, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi $Vd.2s, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; @@ -7138,6 +7155,7 @@ def : InstAlias<"movi.4h $Vd, $imm", (MOVIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.8h $Vd, $imm", (MOVIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.2s $Vd, $imm", (MOVIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"movi.4s $Vd, $imm", (MOVIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; +} def : Pat<(v2i32 (AArch64movi_shift imm0_255:$imm8, (i32 imm:$shift))), (MOVIv2i32 imm0_255:$imm8, imm:$shift)>; @@ -7173,6 +7191,7 @@ def MOVIv16b_ns : SIMDModifiedImmVectorNoShift<1, 0, 0, 0b1110, V128, imm0_255, let isReMaterializable = 1, isAsCheapAsAMove = 1 in defm MVNI : SIMDModifiedImmVectorShift<1, 0b10, 0b00, "mvni">; +let Predicates = [HasNEON] in { def : InstAlias<"mvni $Vd.4h, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.8h, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni $Vd.2s, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; @@ -7182,6 +7201,7 @@ def : InstAlias<"mvni.4h $Vd, $imm", (MVNIv4i16 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.8h $Vd, $imm", (MVNIv8i16 V128:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.2s $Vd, $imm", (MVNIv2i32 V64:$Vd, imm0_255:$imm, 0), 0>; def : InstAlias<"mvni.4s $Vd, $imm", (MVNIv4i32 V128:$Vd, imm0_255:$imm, 0), 0>; +} def : Pat<(v2i32 (AArch64mvni_shift imm0_255:$imm8, (i32 imm:$shift))), (MVNIv2i32 imm0_255:$imm8, imm:$shift)>; @@ -7669,6 +7689,7 @@ def : Pat<(v2i64 (zext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))), def : Pat<(v2i64 (sext (v2i32 (extract_high_v4i32 (v4i32 V128:$Rn)) ))), (SSHLLv4i32_shift V128:$Rn, (i32 0))>; +let Predicates = [HasNEON] in { // Vector shift sxtl aliases def : InstAlias<"sxtl.8h $dst, $src1", (SSHLLv8i8_shift V128:$dst, V64:$src1, 0)>; @@ -7724,6 +7745,7 @@ def : InstAlias<"uxtl2.2d $dst, $src1", (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; def : InstAlias<"uxtl2 $dst.2d, $src1.4s", (USHLLv4i32_shift V128:$dst, V128:$src1, 0)>; +} // If an integer is about to be converted to a floating point value, // just load it on the floating point unit. @@ -8172,7 +8194,7 @@ def AESIMCrr : AESInst< 0b0111, "aesimc", int_aarch64_crypto_aesimc>; // Pseudo instructions for AESMCrr/AESIMCrr with a register constraint required // for AES fusion on some CPUs. -let hasSideEffects = 0, mayStore = 0, mayLoad = 0 in { +let hasSideEffects = 0, mayStore = 0, mayLoad = 0, Predicates = [HasAES] in { def AESMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, Sched<[WriteVq]>; def AESIMCrrTied: Pseudo<(outs V128:$Rd), (ins V128:$Rn), [], "$Rn = $Rd">, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp index c4293f59204d0699b7fb20478c08803c476c4a67..1c75c5a47c9d274d4bc7ee57328953bd22d12dcc 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUCodeGenPrepare.cpp @@ -1213,7 +1213,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem24(IRBuilder<> &Builder, BinaryOperator &I, Value *Num, Value *Den, bool IsDiv, bool IsSigned) const { - int DivBits = getDivNumBits(I, Num, Den, 9, IsSigned); + unsigned SSBits = Num->getType()->getScalarSizeInBits(); + // If Num bits <= 24, assume 0 signbits. + unsigned AtLeast = (SSBits <= 24) ? 0 : (SSBits - 24 + IsSigned); + int DivBits = getDivNumBits(I, Num, Den, AtLeast, IsSigned); if (DivBits == -1) return nullptr; return expandDivRem24Impl(Builder, I, Num, Den, DivBits, IsDiv, IsSigned); @@ -1385,13 +1388,13 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder, Type *I32Ty = Builder.getInt32Ty(); Type *F32Ty = Builder.getFloatTy(); - if (Ty->getScalarSizeInBits() < 32) { + if (Ty->getScalarSizeInBits() != 32) { if (IsSigned) { - X = Builder.CreateSExt(X, I32Ty); - Y = Builder.CreateSExt(Y, I32Ty); + X = Builder.CreateSExtOrTrunc(X, I32Ty); + Y = Builder.CreateSExtOrTrunc(Y, I32Ty); } else { - X = Builder.CreateZExt(X, I32Ty); - Y = Builder.CreateZExt(Y, I32Ty); + X = Builder.CreateZExtOrTrunc(X, I32Ty); + Y = Builder.CreateZExtOrTrunc(Y, I32Ty); } } @@ -1482,10 +1485,10 @@ Value *AMDGPUCodeGenPrepareImpl::expandDivRem32(IRBuilder<> &Builder, if (IsSigned) { Res = Builder.CreateXor(Res, Sign); Res = Builder.CreateSub(Res, Sign); + Res = Builder.CreateSExtOrTrunc(Res, Ty); + } else { + Res = Builder.CreateZExtOrTrunc(Res, Ty); } - - Res = Builder.CreateTrunc(Res, Ty); - return Res; } diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 3d4adb16a27162e2ee2d8e8868f5a5d03ccdee28..a64a9e608f2173dd661922f0455dc4a513494651 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -11567,10 +11567,12 @@ calculateSrcByte(const SDValue Op, uint64_t DestByte, uint64_t SrcIndex = 0, if (Depth >= 6) return std::nullopt; - auto ValueSize = Op.getValueSizeInBits(); - if (ValueSize != 8 && ValueSize != 16 && ValueSize != 32) + if (Op.getValueSizeInBits() < 8) return std::nullopt; + if (Op.getValueType().isVector()) + return ByteProvider::getSrc(Op, DestByte, SrcIndex); + switch (Op->getOpcode()) { case ISD::TRUNCATE: { return calculateSrcByte(Op->getOperand(0), DestByte, SrcIndex, Depth + 1); @@ -11637,8 +11639,12 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, if (Index > BitWidth / 8 - 1) return std::nullopt; + bool IsVec = Op.getValueType().isVector(); switch (Op.getOpcode()) { case ISD::OR: { + if (IsVec) + return std::nullopt; + auto RHS = calculateByteProvider(Op.getOperand(1), Index, Depth + 1, StartingIndex); if (!RHS) @@ -11659,6 +11665,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } case ISD::AND: { + if (IsVec) + return std::nullopt; + auto BitMaskOp = dyn_cast(Op->getOperand(1)); if (!BitMaskOp) return std::nullopt; @@ -11679,6 +11688,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } case ISD::FSHR: { + if (IsVec) + return std::nullopt; + // fshr(X,Y,Z): (X << (BW - (Z % BW))) | (Y >> (Z % BW)) auto ShiftOp = dyn_cast(Op->getOperand(2)); if (!ShiftOp || Op.getValueType().isVector()) @@ -11704,6 +11716,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, case ISD::SRA: case ISD::SRL: { + if (IsVec) + return std::nullopt; + auto ShiftOp = dyn_cast(Op->getOperand(1)); if (!ShiftOp) return std::nullopt; @@ -11729,6 +11744,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } case ISD::SHL: { + if (IsVec) + return std::nullopt; + auto ShiftOp = dyn_cast(Op->getOperand(1)); if (!ShiftOp) return std::nullopt; @@ -11753,6 +11771,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, case ISD::SIGN_EXTEND_INREG: case ISD::AssertZext: case ISD::AssertSext: { + if (IsVec) + return std::nullopt; + SDValue NarrowOp = Op->getOperand(0); unsigned NarrowBitWidth = NarrowOp.getValueSizeInBits(); if (Op->getOpcode() == ISD::SIGN_EXTEND_INREG || @@ -11774,6 +11795,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } case ISD::TRUNCATE: { + if (IsVec) + return std::nullopt; + uint64_t NarrowByteWidth = BitWidth / 8; if (NarrowByteWidth >= Index) { @@ -11816,9 +11840,13 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, return std::nullopt; } - case ISD::BSWAP: + case ISD::BSWAP: { + if (IsVec) + return std::nullopt; + return calculateByteProvider(Op->getOperand(0), BitWidth / 8 - Index - 1, Depth + 1, StartingIndex); + } case ISD::EXTRACT_VECTOR_ELT: { auto IdxOp = dyn_cast(Op->getOperand(1)); @@ -11827,8 +11855,6 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, auto VecIdx = IdxOp->getZExtValue(); auto ScalarSize = Op.getScalarValueSizeInBits(); if (ScalarSize != 32) { - if ((VecIdx + 1) * ScalarSize > 32) - return std::nullopt; Index = ScalarSize == 8 ? VecIdx : VecIdx * 2 + Index; } @@ -11837,6 +11863,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth, } case AMDGPUISD::PERM: { + if (IsVec) + return std::nullopt; + auto PermMask = dyn_cast(Op->getOperand(2)); if (!PermMask) return std::nullopt; @@ -11913,9 +11942,6 @@ static bool hasNon16BitAccesses(uint64_t PermMask, SDValue &Op, int Low16 = PermMask & 0xffff; int Hi16 = (PermMask & 0xffff0000) >> 16; - assert(Op.getValueType().isByteSized()); - assert(OtherOp.getValueType().isByteSized()); - auto TempOp = peekThroughBitcasts(Op); auto TempOtherOp = peekThroughBitcasts(OtherOp); @@ -11933,15 +11959,68 @@ static bool hasNon16BitAccesses(uint64_t PermMask, SDValue &Op, return !addresses16Bits(Low16) || !addresses16Bits(Hi16); } +static SDValue getDWordFromOffset(SelectionDAG &DAG, SDLoc SL, SDValue Src, + unsigned DWordOffset) { + SDValue Ret; + + auto TypeSize = Src.getValueSizeInBits().getFixedValue(); + // ByteProvider must be at least 8 bits + assert(Src.getValueSizeInBits().isKnownMultipleOf(8)); + + if (TypeSize <= 32) + return DAG.getBitcastedAnyExtOrTrunc(Src, SL, MVT::i32); + + if (Src.getValueType().isVector()) { + auto ScalarTySize = Src.getScalarValueSizeInBits(); + auto ScalarTy = Src.getValueType().getScalarType(); + if (ScalarTySize == 32) { + return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Src, + DAG.getConstant(DWordOffset, SL, MVT::i32)); + } + if (ScalarTySize > 32) { + Ret = DAG.getNode( + ISD::EXTRACT_VECTOR_ELT, SL, ScalarTy, Src, + DAG.getConstant(DWordOffset / (ScalarTySize / 32), SL, MVT::i32)); + auto ShiftVal = 32 * (DWordOffset % (ScalarTySize / 32)); + if (ShiftVal) + Ret = DAG.getNode(ISD::SRL, SL, Ret.getValueType(), Ret, + DAG.getConstant(ShiftVal, SL, MVT::i32)); + return DAG.getBitcastedAnyExtOrTrunc(Ret, SL, MVT::i32); + } + + assert(ScalarTySize < 32); + auto NumElements = TypeSize / ScalarTySize; + auto Trunc32Elements = (ScalarTySize * NumElements) / 32; + auto NormalizedTrunc = Trunc32Elements * 32 / ScalarTySize; + auto NumElementsIn32 = 32 / ScalarTySize; + auto NumAvailElements = DWordOffset < Trunc32Elements + ? NumElementsIn32 + : NumElements - NormalizedTrunc; + + SmallVector VecSrcs; + DAG.ExtractVectorElements(Src, VecSrcs, DWordOffset * NumElementsIn32, + NumAvailElements); + + Ret = DAG.getBuildVector( + MVT::getVectorVT(MVT::getIntegerVT(ScalarTySize), NumAvailElements), SL, + VecSrcs); + return Ret = DAG.getBitcastedAnyExtOrTrunc(Ret, SL, MVT::i32); + } + + /// Scalar Type + auto ShiftVal = 32 * DWordOffset; + Ret = DAG.getNode(ISD::SRL, SL, Src.getValueType(), Src, + DAG.getConstant(ShiftVal, SL, MVT::i32)); + return DAG.getBitcastedAnyExtOrTrunc(Ret, SL, MVT::i32); +} + static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { SelectionDAG &DAG = DCI.DAG; - EVT VT = N->getValueType(0); - - if (VT != MVT::i32) - return SDValue(); + [[maybe_unused]] EVT VT = N->getValueType(0); + SmallVector, 8> PermNodes; // VT is known to be MVT::i32, so we need to provide 4 bytes. - SmallVector, 8> PermNodes; + assert(VT == MVT::i32); for (int i = 0; i < 4; i++) { // Find the ByteProvider that provides the ith byte of the result of OR std::optional> P = @@ -11955,8 +12034,8 @@ static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { if (PermNodes.size() != 4) return SDValue(); - int FirstSrc = 0; - std::optional SecondSrc; + std::pair FirstSrc(0, PermNodes[0].SrcOffset / 4); + std::optional> SecondSrc; uint64_t PermMask = 0x00000000; for (size_t i = 0; i < PermNodes.size(); i++) { auto PermOp = PermNodes[i]; @@ -11964,33 +12043,31 @@ static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { // by sizeof(Src2) = 4 int SrcByteAdjust = 4; - if (!PermOp.hasSameSrc(PermNodes[FirstSrc])) { - if (SecondSrc.has_value()) - if (!PermOp.hasSameSrc(PermNodes[*SecondSrc])) + // If the Src uses a byte from a different DWORD, then it corresponds + // with a difference source + if (!PermOp.hasSameSrc(PermNodes[FirstSrc.first]) || + ((PermOp.SrcOffset / 4) != FirstSrc.second)) { + if (SecondSrc) + if (!PermOp.hasSameSrc(PermNodes[SecondSrc->first]) || + ((PermOp.SrcOffset / 4) != SecondSrc->second)) return SDValue(); // Set the index of the second distinct Src node - SecondSrc = i; - assert(!(PermNodes[*SecondSrc].Src->getValueSizeInBits() % 8)); + SecondSrc = {i, PermNodes[i].SrcOffset / 4}; + assert(!(PermNodes[SecondSrc->first].Src->getValueSizeInBits() % 8)); SrcByteAdjust = 0; } - assert(PermOp.SrcOffset + SrcByteAdjust < 8); + assert((PermOp.SrcOffset % 4) + SrcByteAdjust < 8); assert(!DAG.getDataLayout().isBigEndian()); - PermMask |= (PermOp.SrcOffset + SrcByteAdjust) << (i * 8); + PermMask |= ((PermOp.SrcOffset % 4) + SrcByteAdjust) << (i * 8); } - - SDValue Op = *PermNodes[FirstSrc].Src; - SDValue OtherOp = SecondSrc.has_value() ? *PermNodes[*SecondSrc].Src - : *PermNodes[FirstSrc].Src; - - // Check that we haven't just recreated the same FSHR node. - if (N->getOpcode() == ISD::FSHR && - (N->getOperand(0) == Op || N->getOperand(0) == OtherOp) && - (N->getOperand(1) == Op || N->getOperand(1) == OtherOp)) - return SDValue(); + SDLoc DL(N); + SDValue Op = *PermNodes[FirstSrc.first].Src; + Op = getDWordFromOffset(DAG, DL, Op, FirstSrc.second); + assert(Op.getValueSizeInBits() == 32); // Check that we are not just extracting the bytes in order from an op - if (Op == OtherOp && Op.getValueSizeInBits() == 32) { + if (!SecondSrc) { int Low16 = PermMask & 0xffff; int Hi16 = (PermMask & 0xffff0000) >> 16; @@ -12002,8 +12079,15 @@ static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { return DAG.getBitcast(MVT::getIntegerVT(32), Op); } + SDValue OtherOp = SecondSrc ? *PermNodes[SecondSrc->first].Src : Op; + + if (SecondSrc) { + OtherOp = getDWordFromOffset(DAG, DL, OtherOp, SecondSrc->second); + assert(OtherOp.getValueSizeInBits() == 32); + } + if (hasNon16BitAccesses(PermMask, Op, OtherOp)) { - SDLoc DL(N); + assert(Op.getValueType().isByteSized() && OtherOp.getValueType().isByteSized()); @@ -12018,7 +12102,6 @@ static SDValue matchPERM(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { return DAG.getNode(AMDGPUISD::PERM, DL, MVT::i32, Op, OtherOp, DAG.getConstant(PermMask, DL, MVT::i32)); } - return SDValue(); } @@ -13530,17 +13613,24 @@ static unsigned addPermMasks(unsigned First, unsigned Second) { return (FirstNoCs | SecondNoCs) | (FirstCs & SecondCs); } +struct DotSrc { + SDValue SrcOp; + int64_t PermMask; + int64_t DWordOffset; +}; + static void placeSources(ByteProvider &Src0, ByteProvider &Src1, - SmallVectorImpl> &Src0s, - SmallVectorImpl> &Src1s, - int Step) { + SmallVectorImpl &Src0s, + SmallVectorImpl &Src1s, int Step) { assert(Src0.Src.has_value() && Src1.Src.has_value()); // Src0s and Src1s are empty, just place arbitrarily. if (Step == 0) { - Src0s.push_back({*Src0.Src, (Src0.SrcOffset << 24) + 0x0c0c0c}); - Src1s.push_back({*Src1.Src, (Src1.SrcOffset << 24) + 0x0c0c0c}); + Src0s.push_back({*Src0.Src, ((Src0.SrcOffset % 4) << 24) + 0x0c0c0c, + Src0.SrcOffset / 4}); + Src1s.push_back({*Src1.Src, ((Src1.SrcOffset % 4) << 24) + 0x0c0c0c, + Src1.SrcOffset / 4}); return; } @@ -13553,38 +13643,38 @@ static void placeSources(ByteProvider &Src0, unsigned FMask = 0xFF << (8 * (3 - Step)); unsigned FirstMask = - BPP.first.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask); + (BPP.first.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask); unsigned SecondMask = - BPP.second.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask); + (BPP.second.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask); // Attempt to find Src vector which contains our SDValue, if so, add our // perm mask to the existing one. If we are unable to find a match for the // first SDValue, attempt to find match for the second. int FirstGroup = -1; for (int I = 0; I < 2; I++) { - SmallVectorImpl> &Srcs = - I == 0 ? Src0s : Src1s; - auto MatchesFirst = [&BPP](std::pair IterElt) { - return IterElt.first == *BPP.first.Src; + SmallVectorImpl &Srcs = I == 0 ? Src0s : Src1s; + auto MatchesFirst = [&BPP](DotSrc &IterElt) { + return IterElt.SrcOp == *BPP.first.Src && + (IterElt.DWordOffset == (BPP.first.SrcOffset / 4)); }; auto Match = llvm::find_if(Srcs, MatchesFirst); if (Match != Srcs.end()) { - Match->second = addPermMasks(FirstMask, Match->second); + Match->PermMask = addPermMasks(FirstMask, Match->PermMask); FirstGroup = I; break; } } if (FirstGroup != -1) { - SmallVectorImpl> &Srcs = - FirstGroup == 1 ? Src0s : Src1s; - auto MatchesSecond = [&BPP](std::pair IterElt) { - return IterElt.first == *BPP.second.Src; + SmallVectorImpl &Srcs = FirstGroup == 1 ? Src0s : Src1s; + auto MatchesSecond = [&BPP](DotSrc &IterElt) { + return IterElt.SrcOp == *BPP.second.Src && + (IterElt.DWordOffset == (BPP.second.SrcOffset / 4)); }; auto Match = llvm::find_if(Srcs, MatchesSecond); if (Match != Srcs.end()) { - Match->second = addPermMasks(SecondMask, Match->second); + Match->PermMask = addPermMasks(SecondMask, Match->PermMask); } else - Srcs.push_back({*BPP.second.Src, SecondMask}); + Srcs.push_back({*BPP.second.Src, SecondMask, BPP.second.SrcOffset / 4}); return; } } @@ -13596,29 +13686,32 @@ static void placeSources(ByteProvider &Src0, unsigned FMask = 0xFF << (8 * (3 - Step)); Src0s.push_back( - {*Src0.Src, (Src0.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask))}); + {*Src0.Src, + ((Src0.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)), + Src1.SrcOffset / 4}); Src1s.push_back( - {*Src1.Src, (Src1.SrcOffset << (8 * (3 - Step)) | (ZeroMask & ~FMask))}); + {*Src1.Src, + ((Src1.SrcOffset % 4) << (8 * (3 - Step)) | (ZeroMask & ~FMask)), + Src1.SrcOffset / 4}); return; } -static SDValue -resolveSources(SelectionDAG &DAG, SDLoc SL, - SmallVectorImpl> &Srcs, - bool IsSigned, bool IsAny) { +static SDValue resolveSources(SelectionDAG &DAG, SDLoc SL, + SmallVectorImpl &Srcs, bool IsSigned, + bool IsAny) { // If we just have one source, just permute it accordingly. if (Srcs.size() == 1) { auto Elt = Srcs.begin(); - auto EltVal = DAG.getBitcastedAnyExtOrTrunc(Elt->first, SL, MVT::i32); + auto EltOp = getDWordFromOffset(DAG, SL, Elt->SrcOp, Elt->DWordOffset); - // v_perm will produce the original value. - if (Elt->second == 0x3020100) - return EltVal; + // v_perm will produce the original value + if (Elt->PermMask == 0x3020100) + return EltOp; - return DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, EltVal, EltVal, - DAG.getConstant(Elt->second, SL, MVT::i32)); + return DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, EltOp, EltOp, + DAG.getConstant(Elt->PermMask, SL, MVT::i32)); } auto FirstElt = Srcs.begin(); @@ -13629,8 +13722,8 @@ resolveSources(SelectionDAG &DAG, SDLoc SL, // If we have multiple sources in the chain, combine them via perms (using // calculated perm mask) and Ors. while (true) { - auto FirstMask = FirstElt->second; - auto SecondMask = SecondElt->second; + auto FirstMask = FirstElt->PermMask; + auto SecondMask = SecondElt->PermMask; unsigned FirstCs = FirstMask & 0x0c0c0c0c; unsigned FirstPlusFour = FirstMask | 0x04040404; @@ -13640,9 +13733,9 @@ resolveSources(SelectionDAG &DAG, SDLoc SL, auto PermMask = addPermMasks(FirstMask, SecondMask); auto FirstVal = - DAG.getBitcastedAnyExtOrTrunc(FirstElt->first, SL, MVT::i32); + getDWordFromOffset(DAG, SL, FirstElt->SrcOp, FirstElt->DWordOffset); auto SecondVal = - DAG.getBitcastedAnyExtOrTrunc(SecondElt->first, SL, MVT::i32); + getDWordFromOffset(DAG, SL, SecondElt->SrcOp, SecondElt->DWordOffset); Perms.push_back(DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, FirstVal, SecondVal, @@ -13656,12 +13749,12 @@ resolveSources(SelectionDAG &DAG, SDLoc SL, // If we only have a FirstElt, then just combine that into the cumulative // source node. if (SecondElt == Srcs.end()) { - auto EltVal = - DAG.getBitcastedAnyExtOrTrunc(FirstElt->first, SL, MVT::i32); + auto EltOp = + getDWordFromOffset(DAG, SL, FirstElt->SrcOp, FirstElt->DWordOffset); Perms.push_back( - DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, EltVal, EltVal, - DAG.getConstant(FirstElt->second, SL, MVT::i32))); + DAG.getNode(AMDGPUISD::PERM, SL, MVT::i32, EltOp, EltOp, + DAG.getConstant(FirstElt->PermMask, SL, MVT::i32))); break; } } @@ -13672,9 +13765,8 @@ resolveSources(SelectionDAG &DAG, SDLoc SL, : Perms[0]; } -static void fixMasks(SmallVectorImpl> &Srcs, - unsigned ChainLength) { - for (auto &[EntryVal, EntryMask] : Srcs) { +static void fixMasks(SmallVectorImpl &Srcs, unsigned ChainLength) { + for (auto &[EntryVal, EntryMask, EntryOffset] : Srcs) { EntryMask = EntryMask >> ((4 - ChainLength) * 8); auto ZeroMask = ChainLength == 2 ? 0x0c0c0000 : 0x0c000000; EntryMask += ZeroMask; @@ -13774,8 +13866,8 @@ SDValue SITargetLowering::performAddCombine(SDNode *N, (Subtarget->hasDot1Insts() || Subtarget->hasDot8Insts())) { SDValue TempNode(N, 0); std::optional IsSigned; - SmallVector, 4> Src0s; - SmallVector, 4> Src1s; + SmallVector Src0s; + SmallVector Src1s; SmallVector Src2s; // Match the v_dot4 tree, while collecting src nodes. @@ -13857,11 +13949,11 @@ SDValue SITargetLowering::performAddCombine(SDNode *N, // (commutation). bool UseOriginalSrc = false; if (ChainLength == 4 && Src0s.size() == 1 && Src1s.size() == 1 && - Src0s.begin()->second == Src1s.begin()->second && - Src0s.begin()->first.getValueSizeInBits() == 32 && - Src1s.begin()->first.getValueSizeInBits() == 32) { + Src0s.begin()->PermMask == Src1s.begin()->PermMask && + Src0s.begin()->SrcOp.getValueSizeInBits() >= 32 && + Src1s.begin()->SrcOp.getValueSizeInBits() >= 32) { SmallVector SrcBytes; - auto Src0Mask = Src0s.begin()->second; + auto Src0Mask = Src0s.begin()->PermMask; SrcBytes.push_back(Src0Mask & 0xFF000000); bool UniqueEntries = true; for (auto I = 1; I < 4; I++) { @@ -13876,11 +13968,19 @@ SDValue SITargetLowering::performAddCombine(SDNode *N, if (UniqueEntries) { UseOriginalSrc = true; - // Must be 32 bits to enter above conditional. - assert(Src0s.begin()->first.getValueSizeInBits() == 32); - assert(Src1s.begin()->first.getValueSizeInBits() == 32); - Src0 = DAG.getBitcast(MVT::getIntegerVT(32), Src0s.begin()->first); - Src1 = DAG.getBitcast(MVT::getIntegerVT(32), Src1s.begin()->first); + + auto FirstElt = Src0s.begin(); + auto FirstEltOp = + getDWordFromOffset(DAG, SL, FirstElt->SrcOp, FirstElt->DWordOffset); + + auto SecondElt = Src1s.begin(); + auto SecondEltOp = getDWordFromOffset(DAG, SL, SecondElt->SrcOp, + SecondElt->DWordOffset); + + Src0 = DAG.getBitcastedAnyExtOrTrunc(FirstEltOp, SL, + MVT::getIntegerVT(32)); + Src1 = DAG.getBitcastedAnyExtOrTrunc(SecondEltOp, SL, + MVT::getIntegerVT(32)); } } diff --git a/llvm/lib/Target/AMDGPU/SOPInstructions.td b/llvm/lib/Target/AMDGPU/SOPInstructions.td index 37f9a4a3d234f22108f028243ed9f297348f5de7..c8e8ad2034dc983ab8664c1e3d94bf1b2270561e 100644 --- a/llvm/lib/Target/AMDGPU/SOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/SOPInstructions.td @@ -547,9 +547,9 @@ class SOP2_Pseudo sdst = 0; } -class SOP2_Real : +class SOP2_Real : InstSI { + name # ps.AsmOperands> { let SALU = 1; let SOP2 = 1; let isPseudo = 0; @@ -573,8 +573,8 @@ class SOP2_Real : bits<32> imm; } -class SOP2_Real32 op, SOP_Pseudo ps, string real_name = ps.Mnemonic> : - SOP2_Real, Enc32 { +class SOP2_Real32 op, SOP_Pseudo ps, string name = ps.Mnemonic> : + SOP2_Real, Enc32 { let Inst{7-0} = src0; let Inst{15-8} = src1; let Inst{22-16} = !if(ps.has_sdst, sdst, ?); @@ -582,8 +582,8 @@ class SOP2_Real32 op, SOP_Pseudo ps, string real_name = ps.Mnemonic> : let Inst{31-30} = 0x2; // encoding } -class SOP2_Real64 op, SOP_Pseudo ps, string real_name = ps.Mnemonic> : - SOP2_Real, Enc64 { +class SOP2_Real64 op, SOP_Pseudo ps, string name = ps.Mnemonic> : + SOP2_Real, Enc64 { let Inst{7-0} = src0; let Inst{15-8} = src1; let Inst{22-16} = !if(ps.has_sdst, sdst, ?); @@ -958,9 +958,9 @@ class SOPK_Pseudo : +class SOPK_Real : InstSI { + name # ps.AsmOperands> { let SALU = 1; let SOPK = 1; let isPseudo = 0; @@ -984,8 +984,8 @@ class SOPK_Real : bits<32> imm; } -class SOPK_Real32 op, SOPK_Pseudo ps, string real_name = ps.Mnemonic> : - SOPK_Real , +class SOPK_Real32 op, SOPK_Pseudo ps, string name = ps.Mnemonic> : + SOPK_Real , Enc32 { let Inst{15-0} = simm16; let Inst{22-16} = !if(ps.has_sdst, sdst, ?); @@ -1412,9 +1412,9 @@ class SOPPRelaxTable { string KeyName = keyName # gfxip; } -class SOPP_Real : +class SOPP_Real : InstSI { + name # ps.AsmOperands> { let SALU = 1; let SOPP = 1; let isPseudo = 0; @@ -1432,14 +1432,14 @@ class SOPP_Real : bits <16> simm16; } -class SOPP_Real_32 op, SOPP_Pseudo ps, string real_name = ps.Mnemonic> : SOPP_Real, +class SOPP_Real_32 op, SOPP_Pseudo ps, string name = ps.Mnemonic> : SOPP_Real, Enc32 { let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16); let Inst{22-16} = op; let Inst{31-23} = 0x17f; } -class SOPP_Real_64 op, SOPP_Pseudo ps, string real_name = ps.Mnemonic> : SOPP_Real, +class SOPP_Real_64 op, SOPP_Pseudo ps, string name = ps.Mnemonic> : SOPP_Real, Enc64 { // encoding let Inst{15-0} = !if(ps.fixed_imm, ps.simm16, simm16); @@ -1953,9 +1953,20 @@ class Select_gfx6_gfx7 : SIMCInstr { // SOP1 - GFX11, GFX12 //===----------------------------------------------------------------------===// -multiclass SOP1_Real_gfx12 op> { - def _gfx12 : SOP1_Real(NAME)>, - Select_gfx12(NAME).Mnemonic>; +multiclass SOP1_Real_gfx11 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx11 : SOP1_Real, + Select_gfx11; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX11Only]>; +} + +multiclass SOP1_Real_gfx12 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx12 : SOP1_Real, + Select_gfx12; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX12Plus]>; } multiclass SOP1_M0_Real_gfx12 op> { @@ -1965,31 +1976,14 @@ multiclass SOP1_M0_Real_gfx12 op> { } } -multiclass SOP1_Real_gfx11 op> { - def _gfx11 : SOP1_Real(NAME)>, - Select_gfx11(NAME).Mnemonic>; -} - -multiclass SOP1_Real_Renamed_gfx12 op, SOP1_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx12 : SOP1_Real, - Select_gfx12, - MnemonicAlias, Requires<[isGFX12Plus]>; -} - -multiclass SOP1_Real_Renamed_gfx11 op, SOP1_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx11 : SOP1_Real, - Select_gfx11, - MnemonicAlias, Requires<[isGFX11Only]>; +multiclass SOP1_IMM_Real_gfx12 op> { + defvar ps = !cast(NAME); + def _gfx12 : SOP1_Real, + Select_gfx12; } -multiclass SOP1_Real_gfx11_gfx12 op> : - SOP1_Real_gfx11, SOP1_Real_gfx12; - -multiclass SOP1_Real_Renamed_gfx11_gfx12 op, SOP1_Pseudo backing_pseudo> : - SOP1_Real_Renamed_gfx11, - SOP1_Real_Renamed_gfx12; +multiclass SOP1_Real_gfx11_gfx12 op, string name = !tolower(NAME)> : + SOP1_Real_gfx11, SOP1_Real_gfx12; defm S_MOV_B32 : SOP1_Real_gfx11_gfx12<0x000>; defm S_MOV_B64 : SOP1_Real_gfx11_gfx12<0x001>; @@ -1997,12 +1991,12 @@ defm S_CMOV_B32 : SOP1_Real_gfx11_gfx12<0x002>; defm S_CMOV_B64 : SOP1_Real_gfx11_gfx12<0x003>; defm S_BREV_B32 : SOP1_Real_gfx11_gfx12<0x004>; defm S_BREV_B64 : SOP1_Real_gfx11_gfx12<0x005>; -defm S_CTZ_I32_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x008, S_FF1_I32_B32>; -defm S_CTZ_I32_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x009, S_FF1_I32_B64>; -defm S_CLZ_I32_U32 : SOP1_Real_Renamed_gfx11_gfx12<0x00a, S_FLBIT_I32_B32>; -defm S_CLZ_I32_U64 : SOP1_Real_Renamed_gfx11_gfx12<0x00b, S_FLBIT_I32_B64>; -defm S_CLS_I32 : SOP1_Real_Renamed_gfx11_gfx12<0x00c, S_FLBIT_I32>; -defm S_CLS_I32_I64 : SOP1_Real_Renamed_gfx11_gfx12<0x00d, S_FLBIT_I32_I64>; +defm S_FF1_I32_B32 : SOP1_Real_gfx11_gfx12<0x008, "s_ctz_i32_b32">; +defm S_FF1_I32_B64 : SOP1_Real_gfx11_gfx12<0x009, "s_ctz_i32_b64">; +defm S_FLBIT_I32_B32 : SOP1_Real_gfx11_gfx12<0x00a, "s_clz_i32_u32">; +defm S_FLBIT_I32_B64 : SOP1_Real_gfx11_gfx12<0x00b, "s_clz_i32_u64">; +defm S_FLBIT_I32 : SOP1_Real_gfx11_gfx12<0x00c, "s_cls_i32">; +defm S_FLBIT_I32_I64 : SOP1_Real_gfx11_gfx12<0x00d, "s_cls_i32_i64">; defm S_SEXT_I32_I8 : SOP1_Real_gfx11_gfx12<0x00e>; defm S_SEXT_I32_I16 : SOP1_Real_gfx11_gfx12<0x00f>; defm S_BITSET0_B32 : SOP1_Real_gfx11_gfx12<0x010>; @@ -2032,19 +2026,18 @@ defm S_NAND_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x027>; defm S_NOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x028>; defm S_NOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x029>; defm S_XNOR_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02a>; -/*defm S_XNOR_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02b>; //same as older arch, handled there*/ -defm S_AND_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02c, S_ANDN1_SAVEEXEC_B32>; -defm S_AND_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02d, S_ANDN1_SAVEEXEC_B64>; -defm S_OR_NOT0_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x02e, S_ORN1_SAVEEXEC_B32>; -defm S_OR_NOT0_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x02f, S_ORN1_SAVEEXEC_B64>; -defm S_AND_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x030, S_ANDN2_SAVEEXEC_B32>; -defm S_AND_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x031, S_ANDN2_SAVEEXEC_B64>; -defm S_OR_NOT1_SAVEEXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x032, S_ORN2_SAVEEXEC_B32>; -defm S_OR_NOT1_SAVEEXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x033, S_ORN2_SAVEEXEC_B64>; -defm S_AND_NOT0_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x034, S_ANDN1_WREXEC_B32>; -defm S_AND_NOT0_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x035, S_ANDN1_WREXEC_B64>; -defm S_AND_NOT1_WREXEC_B32 : SOP1_Real_Renamed_gfx11_gfx12<0x036, S_ANDN2_WREXEC_B32>; -defm S_AND_NOT1_WREXEC_B64 : SOP1_Real_Renamed_gfx11_gfx12<0x037, S_ANDN2_WREXEC_B64>; +defm S_ANDN1_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02c, "s_and_not0_saveexec_b32">; +defm S_ANDN1_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02d, "s_and_not0_saveexec_b64">; +defm S_ORN1_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x02e, "s_or_not0_saveexec_b32">; +defm S_ORN1_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x02f, "s_or_not0_saveexec_b64">; +defm S_ANDN2_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x030, "s_and_not1_saveexec_b32">; +defm S_ANDN2_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x031, "s_and_not1_saveexec_b64">; +defm S_ORN2_SAVEEXEC_B32 : SOP1_Real_gfx11_gfx12<0x032, "s_or_not1_saveexec_b32">; +defm S_ORN2_SAVEEXEC_B64 : SOP1_Real_gfx11_gfx12<0x033, "s_or_not1_saveexec_b64">; +defm S_ANDN1_WREXEC_B32 : SOP1_Real_gfx11_gfx12<0x034, "s_and_not0_wrexec_b32">; +defm S_ANDN1_WREXEC_B64 : SOP1_Real_gfx11_gfx12<0x035, "s_and_not0_wrexec_b64">; +defm S_ANDN2_WREXEC_B32 : SOP1_Real_gfx11_gfx12<0x036, "s_and_not1_wrexec_b32">; +defm S_ANDN2_WREXEC_B64 : SOP1_Real_gfx11_gfx12<0x037, "s_and_not1_wrexec_b64">; defm S_MOVRELS_B32 : SOP1_Real_gfx11_gfx12<0x040>; defm S_MOVRELS_B64 : SOP1_Real_gfx11_gfx12<0x041>; defm S_MOVRELD_B32 : SOP1_Real_gfx11_gfx12<0x042>; @@ -2062,13 +2055,13 @@ defm S_GET_BARRIER_STATE_M0 : SOP1_M0_Real_gfx12<0x050>; defm S_BARRIER_INIT_M0 : SOP1_M0_Real_gfx12<0x051>; defm S_BARRIER_JOIN_M0 : SOP1_M0_Real_gfx12<0x052>; defm S_WAKEUP_BARRIER_M0 : SOP1_M0_Real_gfx12<0x057>; -defm S_BARRIER_SIGNAL_IMM : SOP1_Real_gfx12<0x04e>; -defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_Real_gfx12<0x04f>; -defm S_GET_BARRIER_STATE_IMM : SOP1_Real_gfx12<0x050>; -defm S_BARRIER_INIT_IMM : SOP1_Real_gfx12<0x051>; -defm S_BARRIER_JOIN_IMM : SOP1_Real_gfx12<0x052>; -defm S_WAKEUP_BARRIER_IMM : SOP1_Real_gfx12<0x057>; -defm S_SLEEP_VAR : SOP1_Real_gfx12<0x058>; +defm S_BARRIER_SIGNAL_IMM : SOP1_IMM_Real_gfx12<0x04e>; +defm S_BARRIER_SIGNAL_ISFIRST_IMM : SOP1_IMM_Real_gfx12<0x04f>; +defm S_GET_BARRIER_STATE_IMM : SOP1_IMM_Real_gfx12<0x050>; +defm S_BARRIER_INIT_IMM : SOP1_IMM_Real_gfx12<0x051>; +defm S_BARRIER_JOIN_IMM : SOP1_IMM_Real_gfx12<0x052>; +defm S_WAKEUP_BARRIER_IMM : SOP1_IMM_Real_gfx12<0x057>; +defm S_SLEEP_VAR : SOP1_IMM_Real_gfx12<0x058>; //===----------------------------------------------------------------------===// // SOP1 - GFX1150, GFX12 @@ -2193,56 +2186,33 @@ defm S_ABS_I32 : SOP1_Real_gfx6_gfx7_gfx10<0x034>; // SOP2 - GFX12 //===----------------------------------------------------------------------===// -multiclass SOP2_Real_gfx12 op> { - def _gfx12 : SOP2_Real32(NAME)>, - Select_gfx12(NAME).Mnemonic>; -} - -multiclass SOP2_Real_Renamed_gfx12 op, SOP2_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx12 : SOP2_Real32, - Select_gfx12, - MnemonicAlias, Requires<[isGFX12Plus]>; +multiclass SOP2_Real_gfx12 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx12 : SOP2_Real32, + Select_gfx12; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX12Plus]>; } -defm S_MIN_NUM_F32 : SOP2_Real_Renamed_gfx12<0x042, S_MIN_F32>; -defm S_MAX_NUM_F32 : SOP2_Real_Renamed_gfx12<0x043, S_MAX_F32>; -defm S_MIN_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04b, S_MIN_F16>; -defm S_MAX_NUM_F16 : SOP2_Real_Renamed_gfx12<0x04c, S_MAX_F16>; defm S_MINIMUM_F32 : SOP2_Real_gfx12<0x04f>; defm S_MAXIMUM_F32 : SOP2_Real_gfx12<0x050>; defm S_MINIMUM_F16 : SOP2_Real_gfx12<0x051>; defm S_MAXIMUM_F16 : SOP2_Real_gfx12<0x052>; -defm S_ADD_CO_U32 : SOP2_Real_Renamed_gfx12<0x000, S_ADD_U32>; -defm S_SUB_CO_U32 : SOP2_Real_Renamed_gfx12<0x001, S_SUB_U32>; -defm S_ADD_CO_I32 : SOP2_Real_Renamed_gfx12<0x002, S_ADD_I32>; -defm S_SUB_CO_I32 : SOP2_Real_Renamed_gfx12<0x003, S_SUB_I32>; -defm S_ADD_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x004, S_ADDC_U32>; -defm S_SUB_CO_CI_U32 : SOP2_Real_Renamed_gfx12<0x005, S_SUBB_U32>; - //===----------------------------------------------------------------------===// // SOP2 - GFX11, GFX12. //===----------------------------------------------------------------------===// -multiclass SOP2_Real_gfx11 op> { - def _gfx11 : SOP2_Real32(NAME)>, - Select_gfx11(NAME).Mnemonic>; -} - -multiclass SOP2_Real_Renamed_gfx11 op, SOP2_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx11 : SOP2_Real32, - Select_gfx11, - MnemonicAlias, Requires<[isGFX11Only]>; +multiclass SOP2_Real_gfx11 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx11 : SOP2_Real32, + Select_gfx11; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX11Only]>; } -multiclass SOP2_Real_gfx11_gfx12 op> : - SOP2_Real_gfx11, SOP2_Real_gfx12; - -multiclass SOP2_Real_Renamed_gfx11_gfx12 op, SOP2_Pseudo backing_pseudo> : - SOP2_Real_Renamed_gfx11, - SOP2_Real_Renamed_gfx12; +multiclass SOP2_Real_gfx11_gfx12 op, string name = !tolower(NAME)> : + SOP2_Real_gfx11, SOP2_Real_gfx12; defm S_ABSDIFF_I32 : SOP2_Real_gfx11_gfx12<0x006>; defm S_LSHL_B32 : SOP2_Real_gfx11_gfx12<0x008>; @@ -2271,10 +2241,10 @@ defm S_NOR_B32 : SOP2_Real_gfx11_gfx12<0x01e>; defm S_NOR_B64 : SOP2_Real_gfx11_gfx12<0x01f>; defm S_XNOR_B32 : SOP2_Real_gfx11_gfx12<0x020>; defm S_XNOR_B64 : SOP2_Real_gfx11_gfx12<0x021>; -defm S_AND_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x022, S_ANDN2_B32>; -defm S_AND_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x023, S_ANDN2_B64>; -defm S_OR_NOT1_B32 : SOP2_Real_Renamed_gfx11_gfx12<0x024, S_ORN2_B32>; -defm S_OR_NOT1_B64 : SOP2_Real_Renamed_gfx11_gfx12<0x025, S_ORN2_B64>; +defm S_ANDN2_B32 : SOP2_Real_gfx11_gfx12<0x022, "s_and_not1_b32">; +defm S_ANDN2_B64 : SOP2_Real_gfx11_gfx12<0x023, "s_and_not1_b64">; +defm S_ORN2_B32 : SOP2_Real_gfx11_gfx12<0x024, "s_or_not1_b32">; +defm S_ORN2_B64 : SOP2_Real_gfx11_gfx12<0x025, "s_or_not1_b64">; defm S_BFE_U32 : SOP2_Real_gfx11_gfx12<0x026>; defm S_BFE_I32 : SOP2_Real_gfx11_gfx12<0x027>; defm S_BFE_U64 : SOP2_Real_gfx11_gfx12<0x028>; @@ -2287,8 +2257,8 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx11_gfx12<0x02e>; defm S_CSELECT_B32 : SOP2_Real_gfx11_gfx12<0x030>; defm S_CSELECT_B64 : SOP2_Real_gfx11_gfx12<0x031>; defm S_PACK_HL_B32_B16 : SOP2_Real_gfx11_gfx12<0x035>; -defm S_ADD_NC_U64 : SOP2_Real_Renamed_gfx12<0x053, S_ADD_U64>; -defm S_SUB_NC_U64 : SOP2_Real_Renamed_gfx12<0x054, S_SUB_U64>; +defm S_ADD_U64 : SOP2_Real_gfx12<0x053, "s_add_nc_u64">; +defm S_SUB_U64 : SOP2_Real_gfx12<0x054, "s_sub_nc_u64">; defm S_MUL_U64 : SOP2_Real_gfx12<0x055>; //===----------------------------------------------------------------------===// @@ -2324,10 +2294,13 @@ defm S_FMAC_F16 : SOP2_Real_gfx11_gfx12<0x04e>; // SOP2 - GFX1150 //===----------------------------------------------------------------------===// -defm S_MIN_F32 : SOP2_Real_gfx11<0x042>; -defm S_MAX_F32 : SOP2_Real_gfx11<0x043>; -defm S_MIN_F16 : SOP2_Real_gfx11<0x04b>; -defm S_MAX_F16 : SOP2_Real_gfx11<0x04c>; +multiclass SOP2_Real_gfx11_Renamed_gfx12 op, string gfx12_name> : + SOP2_Real_gfx11, SOP2_Real_gfx12; + +defm S_MIN_F32 : SOP2_Real_gfx11_Renamed_gfx12<0x042, "s_min_num_f32">; +defm S_MAX_F32 : SOP2_Real_gfx11_Renamed_gfx12<0x043, "s_max_num_f32">; +defm S_MIN_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04b, "s_min_num_f16">; +defm S_MAX_F16 : SOP2_Real_gfx11_Renamed_gfx12<0x04c, "s_max_num_f16">; //===----------------------------------------------------------------------===// // SOP2 - GFX10. @@ -2357,7 +2330,7 @@ defm S_MUL_HI_I32 : SOP2_Real_gfx10<0x036>; //===----------------------------------------------------------------------===// multiclass SOP2_Real_gfx6_gfx7 op> { - defvar ps = !cast(NAME); + defvar ps = !cast(NAME); def _gfx6_gfx7 : SOP2_Real32, Select_gfx6_gfx7; } @@ -2365,20 +2338,18 @@ multiclass SOP2_Real_gfx6_gfx7 op> { multiclass SOP2_Real_gfx6_gfx7_gfx10 op> : SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10; -multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11 op> : - SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10, SOP2_Real_gfx11; - -multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11_gfx12 op> : - SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10_gfx11_gfx12; +multiclass SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12 op, string gfx12_name> : + SOP2_Real_gfx6_gfx7, SOP2_Real_gfx10, SOP2_Real_gfx11, + SOP2_Real_gfx12; defm S_CBRANCH_G_FORK : SOP2_Real_gfx6_gfx7<0x02b>; -defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11<0x000>; -defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11<0x001>; -defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11<0x002>; -defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11<0x003>; -defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11<0x004>; -defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11<0x005>; +defm S_ADD_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x000, "s_add_co_u32">; +defm S_SUB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x001, "s_sub_co_u32">; +defm S_ADD_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x002, "s_add_co_i32">; +defm S_SUB_I32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x003, "s_sub_co_i32">; +defm S_ADDC_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x004, "s_add_co_ci_u32">; +defm S_SUBB_U32 : SOP2_Real_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x005, "s_sub_co_ci_u32">; defm S_MIN_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x006>; defm S_MIN_U32 : SOP2_Real_gfx6_gfx7_gfx10<0x007>; defm S_MAX_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x008>; @@ -2420,16 +2391,12 @@ defm S_ABSDIFF_I32 : SOP2_Real_gfx6_gfx7_gfx10<0x02c>; // SOPK - GFX11, GFX12. //===----------------------------------------------------------------------===// -multiclass SOPK_Real32_gfx12 op> { - def _gfx12 : SOPK_Real32(NAME)>, - Select_gfx12(NAME).Mnemonic>; -} - -multiclass SOPK_Real32_Renamed_gfx12 op, SOPK_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx12 : SOPK_Real32, - Select_gfx12, - MnemonicAlias, Requires<[isGFX12Plus]>; +multiclass SOPK_Real32_gfx12 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx12 : SOPK_Real32, + Select_gfx12; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX12Plus]>; } multiclass SOPK_Real32_gfx11 op> { @@ -2453,7 +2420,6 @@ multiclass SOPK_Real32_gfx11_gfx12 op> : multiclass SOPK_Real64_gfx11_gfx12 op> : SOPK_Real64_gfx11, SOPK_Real64_gfx12; -defm S_ADDK_CO_I32 : SOPK_Real32_Renamed_gfx12<0x00f, S_ADDK_I32>; defm S_GETREG_B32 : SOPK_Real32_gfx11_gfx12<0x011>; defm S_SETREG_B32 : SOPK_Real32_gfx11_gfx12<0x012>; defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx11_gfx12<0x013>; @@ -2524,6 +2490,10 @@ multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11 op> : multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12 op> : SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10_gfx11_gfx12; +multiclass SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12 op, string gfx12_name> : + SOPK_Real32_gfx6_gfx7, SOPK_Real32_gfx10, SOPK_Real32_gfx11, + SOPK_Real32_gfx12; + defm S_CBRANCH_I_FORK : SOPK_Real32_gfx6_gfx7<0x011>; defm S_MOVK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x000>; @@ -2540,7 +2510,7 @@ defm S_CMPK_GT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00b>; defm S_CMPK_GE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00c>; defm S_CMPK_LT_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00d>; defm S_CMPK_LE_U32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00e>; -defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11<0x00f>; +defm S_ADDK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_Renamed_gfx12<0x00f, "s_addk_co_i32">; defm S_MULK_I32 : SOPK_Real32_gfx6_gfx7_gfx10_gfx11_gfx12<0x010>; defm S_GETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x012>; defm S_SETREG_B32 : SOPK_Real32_gfx6_gfx7_gfx10<0x013>; @@ -2550,20 +2520,14 @@ defm S_SETREG_IMM32_B32 : SOPK_Real64_gfx6_gfx7_gfx10<0x015>; // SOPP - GFX12 only. //===----------------------------------------------------------------------===// -multiclass SOPP_Real_32_gfx12 op> { - def _gfx12 : SOPP_Real_32(NAME), !cast(NAME).Mnemonic>, - Select_gfx12(NAME).Mnemonic>, - SOPPRelaxTable<0, !cast(NAME).KeyName, "_gfx12">; -} - -multiclass SOPP_Real_32_Renamed_gfx12 op, SOPP_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx12 : SOPP_Real_32, - Select_gfx12, - MnemonicAlias, Requires<[isGFX12Plus]>; +multiclass SOPP_Real_32_gfx12 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx12 : SOPP_Real_32, + Select_gfx12; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX12Plus]>; } -defm S_WAIT_ALU : SOPP_Real_32_Renamed_gfx12<0x008, S_WAITCNT_DEPCTR>; defm S_BARRIER_WAIT : SOPP_Real_32_gfx12<0x014>; defm S_BARRIER_LEAVE : SOPP_Real_32_gfx12<0x015>; defm S_WAIT_LOADCNT : SOPP_Real_32_gfx12<0x040>; @@ -2581,10 +2545,13 @@ defm S_WAIT_STORECNT_DSCNT : SOPP_Real_32_gfx12<0x049>; //===----------------------------------------------------------------------===// -multiclass SOPP_Real_32_gfx11 op> { - def _gfx11 : SOPP_Real_32(NAME), !cast(NAME).Mnemonic>, - Select_gfx11(NAME).Mnemonic>, - SOPPRelaxTable<0, !cast(NAME).KeyName, "_gfx11">; +multiclass SOPP_Real_32_gfx11 op, string name = !tolower(NAME)> { + defvar ps = !cast(NAME); + def _gfx11 : SOPP_Real_32, + Select_gfx11, + SOPPRelaxTable<0, ps.KeyName, "_gfx11">; + if !ne(ps.Mnemonic, name) then + def : MnemonicAlias, Requires<[isGFX11Only]>; } multiclass SOPP_Real_64_gfx12 op> { @@ -2599,22 +2566,11 @@ multiclass SOPP_Real_64_gfx11 op> { SOPPRelaxTable<1, !cast(NAME).KeyName, "_gfx11">; } -multiclass SOPP_Real_32_Renamed_gfx11 op, SOPP_Pseudo backing_pseudo> { - defvar real_name = !tolower(NAME); - def _gfx11 : SOPP_Real_32, - Select_gfx11, - MnemonicAlias, Requires<[isGFX11Only]>; -} - multiclass SOPP_Real_32_gfx11_gfx12 op> : SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; -multiclass SOPP_Real_64_gfx11_gfx12 op> : - SOPP_Real_64_gfx11, SOPP_Real_64_gfx12; - -multiclass SOPP_Real_32_Renamed_gfx11_gfx12 op, SOPP_Pseudo backing_pseudo> : - SOPP_Real_32_Renamed_gfx11, - SOPP_Real_32_Renamed_gfx12; +multiclass SOPP_Real_32_gfx11_Renamed_gfx12 op, string gfx12_name> : + SOPP_Real_32_gfx11, SOPP_Real_32_gfx12; multiclass SOPP_Real_With_Relaxation_gfx12 op> { defm "" : SOPP_Real_32_gfx12; @@ -2632,10 +2588,10 @@ multiclass SOPP_Real_With_Relaxation_gfx11_gfx12op> : defm S_SETKILL : SOPP_Real_32_gfx11_gfx12<0x001>; defm S_SETHALT : SOPP_Real_32_gfx11_gfx12<0x002>; defm S_SLEEP : SOPP_Real_32_gfx11_gfx12<0x003>; -defm S_SET_INST_PREFETCH_DISTANCE : SOPP_Real_32_Renamed_gfx11<0x004, S_INST_PREFETCH>; +defm S_INST_PREFETCH : SOPP_Real_32_gfx11<0x004, "s_set_inst_prefetch_distance">; defm S_CLAUSE : SOPP_Real_32_gfx11_gfx12<0x005>; defm S_DELAY_ALU : SOPP_Real_32_gfx11_gfx12<0x007>; -defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11<0x008>; +defm S_WAITCNT_DEPCTR : SOPP_Real_32_gfx11_Renamed_gfx12<0x008, "s_wait_alu">; defm S_WAITCNT : SOPP_Real_32_gfx11_gfx12<0x009>; defm S_WAIT_IDLE : SOPP_Real_32_gfx11_gfx12<0x00a>; defm S_WAIT_EVENT : SOPP_Real_32_gfx11_gfx12<0x00b>; @@ -2734,18 +2690,12 @@ multiclass SOPP_Real_64_gfx10 op> { SOPPRelaxTable<1, ps.KeyName, "_gfx10">; } -multiclass SOPP_Real_64_gfx8_gfx9_gfx10 op> : - SOPP_Real_64_gfx8_gfx9, SOPP_Real_64_gfx10; - multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9 op> : SOPP_Real_64_gfx6_gfx7, SOPP_Real_64_gfx8_gfx9; multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10 op> : SOPP_Real_64_gfx6_gfx7_gfx8_gfx9, SOPP_Real_64_gfx10; -multiclass SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12 op> : - SOPP_Real_64_gfx6_gfx7_gfx8_gfx9_gfx10, SOPP_Real_64_gfx11_gfx12; - //relaxation for insts with no operands not implemented multiclass SOPP_Real_With_Relaxation_gfx6_gfx7_gfx8_gfx9_gfx10 op> { defm "" : SOPP_Real_32_gfx6_gfx7_gfx8_gfx9_gfx10; @@ -2812,24 +2762,8 @@ multiclass SOPC_Real_gfx11 op> { multiclass SOPC_Real_gfx11_gfx12 op> : SOPC_Real_gfx11, SOPC_Real_gfx12; -defm S_CMP_EQ_I32 : SOPC_Real_gfx11_gfx12<0x00>; -defm S_CMP_LG_I32 : SOPC_Real_gfx11_gfx12<0x01>; -defm S_CMP_GT_I32 : SOPC_Real_gfx11_gfx12<0x02>; -defm S_CMP_GE_I32 : SOPC_Real_gfx11_gfx12<0x03>; -defm S_CMP_LT_I32 : SOPC_Real_gfx11_gfx12<0x04>; -defm S_CMP_LE_I32 : SOPC_Real_gfx11_gfx12<0x05>; -defm S_CMP_EQ_U32 : SOPC_Real_gfx11_gfx12<0x06>; -defm S_CMP_LG_U32 : SOPC_Real_gfx11_gfx12<0x07>; -defm S_CMP_GT_U32 : SOPC_Real_gfx11_gfx12<0x08>; -defm S_CMP_GE_U32 : SOPC_Real_gfx11_gfx12<0x09>; -defm S_CMP_LT_U32 : SOPC_Real_gfx11_gfx12<0x0a>; -defm S_CMP_LE_U32 : SOPC_Real_gfx11_gfx12<0x0b>; -defm S_BITCMP0_B32 : SOPC_Real_gfx11_gfx12<0x0c>; -defm S_BITCMP1_B32 : SOPC_Real_gfx11_gfx12<0x0d>; -defm S_BITCMP0_B64 : SOPC_Real_gfx11_gfx12<0x0e>; -defm S_BITCMP1_B64 : SOPC_Real_gfx11_gfx12<0x0f>; -defm S_CMP_EQ_U64 : SOPC_Real_gfx11_gfx12<0x10>; -defm S_CMP_LG_U64 : SOPC_Real_gfx11_gfx12<0x11>; +defm S_CMP_EQ_U64 : SOPC_Real_gfx11_gfx12<0x10>; +defm S_CMP_LG_U64 : SOPC_Real_gfx11_gfx12<0x11>; //===----------------------------------------------------------------------===// // SOPC - GFX1150, GFX12 @@ -2893,25 +2827,26 @@ multiclass SOPC_Real_gfx8_gfx9_gfx10 op> : multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9 op> : SOPC_Real_gfx6_gfx7, SOPC_Real_gfx8_gfx9; -multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10 op> : - SOPC_Real_gfx6_gfx7_gfx8_gfx9, SOPC_Real_gfx10; - -defm S_CMP_EQ_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x00>; -defm S_CMP_LG_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x01>; -defm S_CMP_GT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x02>; -defm S_CMP_GE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x03>; -defm S_CMP_LT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x04>; -defm S_CMP_LE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x05>; -defm S_CMP_EQ_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x06>; -defm S_CMP_LG_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x07>; -defm S_CMP_GT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x08>; -defm S_CMP_GE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x09>; -defm S_CMP_LT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x0a>; -defm S_CMP_LE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x0b>; -defm S_BITCMP0_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x0c>; -defm S_BITCMP1_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x0d>; -defm S_BITCMP0_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x0e>; -defm S_BITCMP1_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10<0x0f>; +multiclass SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12 op> : + SOPC_Real_gfx6_gfx7_gfx8_gfx9, SOPC_Real_gfx10, SOPC_Real_gfx11, + SOPC_Real_gfx12; + +defm S_CMP_EQ_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x00>; +defm S_CMP_LG_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x01>; +defm S_CMP_GT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x02>; +defm S_CMP_GE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x03>; +defm S_CMP_LT_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x04>; +defm S_CMP_LE_I32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x05>; +defm S_CMP_EQ_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x06>; +defm S_CMP_LG_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x07>; +defm S_CMP_GT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x08>; +defm S_CMP_GE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x09>; +defm S_CMP_LT_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0a>; +defm S_CMP_LE_U32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0b>; +defm S_BITCMP0_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0c>; +defm S_BITCMP1_B32 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0d>; +defm S_BITCMP0_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0e>; +defm S_BITCMP1_B64 : SOPC_Real_gfx6_gfx7_gfx8_gfx9_gfx10_gfx11_gfx12<0x0f>; defm S_SETVSKIP : SOPC_Real_gfx6_gfx7_gfx8_gfx9<0x10>; defm S_SET_GPR_IDX_ON : SOPC_Real_gfx8_gfx9<0x11>; defm S_CMP_EQ_U64 : SOPC_Real_gfx8_gfx9_gfx10<0x12>; diff --git a/llvm/lib/Target/ARM/ARMInstrInfo.td b/llvm/lib/Target/ARM/ARMInstrInfo.td index 812b5730875d5d4c30dbcb12cbbe58ce861b107b..074dea36b64145fea966bac1df2eb9c2b93aae4b 100644 --- a/llvm/lib/Target/ARM/ARMInstrInfo.td +++ b/llvm/lib/Target/ARM/ARMInstrInfo.td @@ -379,6 +379,8 @@ def imm_neg_XFORM : SDNodeXFormgetTargetConstant(~(int)N->getZExtValue(), SDLoc(N), MVT::i32); }]>; +def gi_imm_not_XFORM : GICustomOperandRenderer<"renderInvertedImm">, + GISDNodeXFormEquiv; // asr_imm_XFORM - Returns a shift immediate with bit {5} set to 1 def asr_imm_XFORM : SDNodeXForm, ImmLeaf, PatLeaf<(imm), [{ - return ARM_AM::getSOImmVal(~(uint32_t)N->getZExtValue()) != -1; +def mod_imm_not : Operand, ImmLeaf { let ParserMatchClass = ModImmNotAsmOperand; } diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp index f391058a70514c3b5a7694cba16f2720364a4111..3b3c380e1e1b32a7770b8ff91e86ed51a9cfad24 100644 --- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp @@ -142,6 +142,8 @@ private: int OpIdx = -1) const; void renderVFPF64Imm(MachineInstrBuilder &New, const MachineInstr &Old, int OpIdx = -1) const; + void renderInvertedImm(MachineInstrBuilder &MIB, const MachineInstr &MI, + int OpIdx = -1) const; #define GET_GLOBALISEL_PREDICATES_DECL #include "ARMGenGlobalISel.inc" @@ -835,6 +837,15 @@ void ARMInstructionSelector::renderVFPF64Imm( NewInstBuilder.addImm(FPImmEncoding); } +void ARMInstructionSelector::renderInvertedImm(MachineInstrBuilder &MIB, + const MachineInstr &MI, + int OpIdx) const { + assert(MI.getOpcode() == TargetOpcode::G_CONSTANT && OpIdx == -1 && + "Expected G_CONSTANT"); + int64_t CVal = MI.getOperand(1).getCImm()->getSExtValue(); + MIB.addImm(~CVal); +} + bool ARMInstructionSelector::select(MachineInstr &I) { assert(I.getParent() && "Instruction should be in a basic block!"); assert(I.getParent()->getParent() && "Instruction should be in a function!"); diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp index 718844bc36ff93b6ffbb144bbdd50c4457b84d2c..66b2b0de8d52a35fcf3e6b22ddf503b710a85ffd 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.cpp @@ -471,45 +471,6 @@ void MipsAsmPrinter::emitBasicBlockEnd(const MachineBasicBlock &MBB) { TS.emitDirectiveInsn(); } -/// isBlockOnlyReachableByFallthough - Return true if the basic block has -/// exactly one predecessor and the control transfer mechanism between -/// the predecessor and this block is a fall-through. -bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock* - MBB) const { - // The predecessor has to be immediately before this block. - const MachineBasicBlock *Pred = *MBB->pred_begin(); - - // If the predecessor is a switch statement, assume a jump table - // implementation, so it is not a fall through. - if (const BasicBlock *bb = Pred->getBasicBlock()) - if (isa(bb->getTerminator())) - return false; - - // If this is a landing pad, it isn't a fall through. If it has no preds, - // then nothing falls through to it. - if (MBB->isEHPad() || MBB->pred_empty()) - return false; - - // If there isn't exactly one predecessor, it can't be a fall through. - if (MBB->pred_size() != 1) - return false; - - // The predecessor has to be immediately before this block. - if (!Pred->isLayoutSuccessor(MBB)) - return false; - - // If the block is completely empty, then it definitely does fall through. - if (Pred->empty()) - return true; - - // Otherwise, check the last instruction. - // Check if the last terminator is an unconditional branch. - MachineBasicBlock::const_iterator I = Pred->end(); - while (I != Pred->begin() && !(--I)->isTerminator()) ; - - return !I->isBarrier(); -} - // Print out an operand for an inline asm expression. bool MipsAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNum, const char *ExtraCode, raw_ostream &O) { diff --git a/llvm/lib/Target/Mips/MipsAsmPrinter.h b/llvm/lib/Target/Mips/MipsAsmPrinter.h index 64424b181504a7e6f1c88266fa2ccf5eedc1f6bf..0b55089385d79d4bc321ff249d5a7200bfd1fadd 100644 --- a/llvm/lib/Target/Mips/MipsAsmPrinter.h +++ b/llvm/lib/Target/Mips/MipsAsmPrinter.h @@ -142,8 +142,6 @@ public: void emitFunctionBodyStart() override; void emitFunctionBodyEnd() override; void emitBasicBlockEnd(const MachineBasicBlock &MBB) override; - bool isBlockOnlyReachableByFallthrough( - const MachineBasicBlock* MBB) const override; bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override; bool PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNum, diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp index 6a3710407bc4f533b700af76f6c3554a9d38ef93..9e5f0b36616d1b9af34eeaf8ba8d66dcb4f495cf 100644 --- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp +++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp @@ -1632,7 +1632,8 @@ class BitPermutationSelector { default: break; case ISD::ROTL: if (isa(V.getOperand(1))) { - unsigned RotAmt = V.getConstantOperandVal(1); + assert(isPowerOf2_32(NumBits) && "rotl bits should be power of 2!"); + unsigned RotAmt = V.getConstantOperandVal(1) & (NumBits - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; @@ -1645,15 +1646,20 @@ class BitPermutationSelector { case ISD::SHL: case PPCISD::SHL: if (isa(V.getOperand(1))) { - unsigned ShiftAmt = V.getConstantOperandVal(1); + // sld takes 7 bits, slw takes 6. + unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; - for (unsigned i = ShiftAmt; i < NumBits; ++i) - Bits[i] = LHSBits[i - ShiftAmt]; - - for (unsigned i = 0; i < ShiftAmt; ++i) - Bits[i] = ValueBit(ValueBit::ConstZero); + if (ShiftAmt >= NumBits) { + for (unsigned i = 0; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } else { + for (unsigned i = ShiftAmt; i < NumBits; ++i) + Bits[i] = LHSBits[i - ShiftAmt]; + for (unsigned i = 0; i < ShiftAmt; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } return std::make_pair(Interesting = true, &Bits); } @@ -1661,15 +1667,20 @@ class BitPermutationSelector { case ISD::SRL: case PPCISD::SRL: if (isa(V.getOperand(1))) { - unsigned ShiftAmt = V.getConstantOperandVal(1); + // srd takes lowest 7 bits, srw takes 6. + unsigned ShiftAmt = V.getConstantOperandVal(1) & ((NumBits << 1) - 1); const auto &LHSBits = *getValueBits(V.getOperand(0), NumBits).second; - for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) - Bits[i] = LHSBits[i + ShiftAmt]; - - for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) - Bits[i] = ValueBit(ValueBit::ConstZero); + if (ShiftAmt >= NumBits) { + for (unsigned i = 0; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } else { + for (unsigned i = 0; i < NumBits - ShiftAmt; ++i) + Bits[i] = LHSBits[i + ShiftAmt]; + for (unsigned i = NumBits - ShiftAmt; i < NumBits; ++i) + Bits[i] = ValueBit(ValueBit::ConstZero); + } return std::make_pair(Interesting = true, &Bits); } diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index f6e8386aff45100b3538b5cefcb748a7a6b87041..d83979a873f2a313c45982096efc005bbd26cc7f 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -1222,8 +1222,8 @@ public: int64_t Imm = 0; if (Kind == KindTy::Immediate) { RISCVMCExpr::VariantKind VK = RISCVMCExpr::VK_RISCV_None; - bool IsConstantImm = evaluateConstantImm(getImm(), Imm, VK); - (void)IsConstantImm; + [[maybe_unused]] bool IsConstantImm = + evaluateConstantImm(getImm(), Imm, VK); assert(IsConstantImm && "Invalid VTypeI Operand!"); } else { Imm = getVType(); @@ -2893,7 +2893,7 @@ bool RISCVAsmParser::parseDirectiveOption() { getTargetStreamer().emitDirectiveOptionNoRVC(); clearFeatureBits(RISCV::FeatureStdExtC, "c"); - clearFeatureBits(RISCV::FeatureStdExtZca, "+zca"); + clearFeatureBits(RISCV::FeatureStdExtZca, "zca"); return false; } diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 4dd039159e29dce6810fa3c7f9474f7f021fddd4..f1ca1212ec378e83a72886b02ab7224b13d7b61c 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -380,8 +380,8 @@ static DecodeStatus decodeRVCInstrRdRs1ImmZero(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { uint32_t Rd = fieldFromInstruction(Insn, 7, 5); - DecodeStatus Result = DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + DecodeGPRNoX0RegisterClass(Inst, Rd, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid register"); Inst.addOperand(Inst.getOperand(0)); Inst.addOperand(MCOperand::createImm(0)); @@ -392,8 +392,8 @@ static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder) { uint32_t Rs1 = fieldFromInstruction(Insn, 7, 5); - DecodeStatus Result = DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + DecodeGPRX1X5RegisterClass(Inst, Rs1, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid register"); return MCDisassembler::Success; } @@ -404,8 +404,8 @@ static DecodeStatus decodeRVCInstrRdSImm(MCInst &Inst, uint32_t Insn, Inst.addOperand(MCOperand::createReg(RISCV::X0)); uint32_t SImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); - DecodeStatus Result = decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + decodeSImmOperand<6>(Inst, SImm6, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); return MCDisassembler::Success; } @@ -417,8 +417,8 @@ static DecodeStatus decodeRVCInstrRdRs1UImm(MCInst &Inst, uint32_t Insn, Inst.addOperand(Inst.getOperand(0)); uint32_t UImm6 = fieldFromInstruction(Insn, 12, 1) << 5 | fieldFromInstruction(Insn, 2, 5); - DecodeStatus Result = decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + decodeUImmOperand<6>(Inst, UImm6, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); return MCDisassembler::Success; } @@ -454,8 +454,8 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, DecodeGPRRegisterClass(Inst, Rd1, Address, Decoder); DecodeGPRRegisterClass(Inst, Rd2, Address, Decoder); DecodeGPRRegisterClass(Inst, Rs1, Address, Decoder); - DecodeStatus Result = decodeUImmOperand<2>(Inst, UImm2, Address, Decoder); - (void)Result; + [[maybe_unused]] DecodeStatus Result = + decodeUImmOperand<2>(Inst, UImm2, Address, Decoder); assert(Result == MCDisassembler::Success && "Invalid immediate"); // Disassemble the final operand which is implicit. diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp index bd49875c9591d01e927fe3279f646ff4ebeee34d..182a9c1544fd251f3abf0c8c23ac5ff2930315a7 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp @@ -186,9 +186,8 @@ void RISCVAsmBackend::relaxInstruction(MCInst &Inst, case RISCV::C_BNEZ: case RISCV::C_J: case RISCV::C_JAL: { - bool Success = RISCVRVC::uncompress(Res, Inst, STI); + [[maybe_unused]] bool Success = RISCVRVC::uncompress(Res, Inst, STI); assert(Success && "Can't uncompress instruction"); - (void)Success; break; } case RISCV::BEQ: @@ -218,9 +217,9 @@ bool RISCVAsmBackend::relaxDwarfLineAddr(MCDwarfLineAddrFragment &DF, size_t OldSize = Data.size(); int64_t Value; - bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout); + [[maybe_unused]] bool IsAbsolute = + AddrDelta.evaluateKnownAbsolute(Value, Layout); assert(IsAbsolute && "CFA with invalid expression"); - (void)IsAbsolute; Data.clear(); Fixups.clear(); @@ -283,9 +282,9 @@ bool RISCVAsmBackend::relaxDwarfCFA(MCDwarfCallFrameFragment &DF, int64_t Value; if (AddrDelta.evaluateAsAbsolute(Value, Layout.getAssembler())) return false; - bool IsAbsolute = AddrDelta.evaluateKnownAbsolute(Value, Layout); + [[maybe_unused]] bool IsAbsolute = + AddrDelta.evaluateKnownAbsolute(Value, Layout); assert(IsAbsolute && "CFA with invalid expression"); - (void)IsAbsolute; Data.clear(); Fixups.clear(); diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp index 961b8f0afe2254b584a8901b8ccf28f597ad1f17..b375e8bb4b8fac026f0d83617ded5f406364d947 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp @@ -87,14 +87,14 @@ void RISCVTargetELFStreamer::finishAttributeSection() { void RISCVTargetELFStreamer::finish() { RISCVTargetStreamer::finish(); MCAssembler &MCA = getStreamer().getAssembler(); - const FeatureBitset &Features = STI.getFeatureBits(); RISCVABI::ABI ABI = getTargetABI(); unsigned EFlags = MCA.getELFHeaderEFlags(); - if (Features[RISCV::FeatureStdExtC]) + if (STI.hasFeature(RISCV::FeatureStdExtC) || + STI.hasFeature(RISCV::FeatureStdExtZca)) EFlags |= ELF::EF_RISCV_RVC; - if (Features[RISCV::FeatureStdExtZtso]) + if (STI.hasFeature(RISCV::FeatureStdExtZtso)) EFlags |= ELF::EF_RISCV_TSO; switch (ABI) { diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index b2e9cd87373b0f0ae02fb52f7ffa30903c9f703c..cb82e74b1efacd94ee37380ce73d314d610dafc3 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -110,7 +110,7 @@ private: void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) { - unsigned NOPBytes = STI->getFeatureBits()[RISCV::FeatureStdExtC] ? 2 : 4; + unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; unsigned NumNOPBytes = StackMapOpers(&MI).getNumPatchBytes(); auto &Ctx = OutStreamer.getContext(); @@ -143,7 +143,7 @@ void RISCVAsmPrinter::LowerSTACKMAP(MCStreamer &OutStreamer, StackMaps &SM, // [], , , , void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) { - unsigned NOPBytes = STI->getFeatureBits()[RISCV::FeatureStdExtC] ? 2 : 4; + unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; auto &Ctx = OutStreamer.getContext(); MCSymbol *MILabel = Ctx.createTempSymbol(); @@ -165,7 +165,7 @@ void RISCVAsmPrinter::LowerPATCHPOINT(MCStreamer &OutStreamer, StackMaps &SM, void RISCVAsmPrinter::LowerSTATEPOINT(MCStreamer &OutStreamer, StackMaps &SM, const MachineInstr &MI) { - unsigned NOPBytes = STI->getFeatureBits()[RISCV::FeatureStdExtC] ? 2 : 4; + unsigned NOPBytes = STI->hasStdExtCOrZca() ? 2 : 4; StatepointOpers SOpers(&MI); if (unsigned PatchBytes = SOpers.getNumPatchBytes()) { diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index 03ccda4561ed8b49ba857bc1ad1e008c39e30c0c..03e09804021072c89d845508b735513bf614cd27 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -828,6 +828,10 @@ def FeatureStdExtSstc : SubtargetFeature<"sstc", "HasStdExtSstc", "true", "'Sstc' (Supervisor-mode timer interrupts)", []>; +def FeaturesSsqosid + : SubtargetFeature<"experimental-ssqosid", "HasStdExtSsqosid", "true", + "'Ssqosid' (Quality-of-Service (QoS) Identifiers)", []>; + def FeatureStdExtShtvala : SubtargetFeature<"shtvala", "HasStdExtShtvala", "true", "'Shtvala' (htval provides all needed values)", []>; diff --git a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp index 6ee006525df560f20cb0ed031f0b209ab8709330..271d28f86a6707c6315f7f4726769799016ab8b5 100644 --- a/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp +++ b/llvm/lib/Target/RISCV/RISCVFoldMasks.cpp @@ -146,7 +146,8 @@ bool RISCVFoldMasks::convertToUnmasked(MachineInstr &MI, // everything else. See the comment on RISCVMaskedPseudo for details. const unsigned Opc = I->UnmaskedPseudo; const MCInstrDesc &MCID = TII->get(Opc); - const bool HasPolicyOp = RISCVII::hasVecPolicyOp(MCID.TSFlags); + [[maybe_unused]] const bool HasPolicyOp = + RISCVII::hasVecPolicyOp(MCID.TSFlags); const bool HasPassthru = RISCVII::isFirstDefTiedToFirstUse(MCID); #ifndef NDEBUG const MCInstrDesc &MaskedMCID = TII->get(MI.getOpcode()); diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp index d793c0b7377baf0bbd9bba23a4afea7e7ce248b3..e5b510349e3dd04dfe6e97709e056ef7fc9cc525 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp @@ -1172,7 +1172,7 @@ static unsigned estimateFunctionSizeInBytes(const MachineFunction &MF, if (MI.isConditionalBranch()) FnSize += TII.getInstSizeInBytes(MI); if (MI.isConditionalBranch() || MI.isUnconditionalBranch()) { - if (MF.getSubtarget().hasStdExtC()) + if (MF.getSubtarget().hasStdExtCOrZca()) FnSize += 2 + 8 + 2 + 2; else FnSize += 4 + 8 + 4 + 4; @@ -1252,6 +1252,30 @@ void RISCVFrameLowering::processFunctionBeforeFrameFinalized( RVFI->setCalleeSavedStackSize(Size); } +void RISCVFrameLowering::processFunctionBeforeFrameIndicesReplaced( + MachineFunction &MF, RegScavenger *RS) const { + // Remove CalleeSavedInfo for registers saved by Zcmp or save/restore + // libcalls. + MachineFrameInfo &MFI = MF.getFrameInfo(); + const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo(); + const auto *RVFI = MF.getInfo(); + if (!RVFI->isPushable(MF) && !RVFI->useSaveRestoreLibCalls(MF)) + return; + const std::vector &CSIs = MFI.getCalleeSavedInfo(); + std::vector NewCSIs; + for (const auto &CSI : CSIs) { + // Skip CSRs that have fake a frame index. + int ReservedFI = 0; + if (TRI->hasReservedSpillSlot(MF, CSI.getReg(), ReservedFI)) { + assert(CSI.getFrameIdx() == ReservedFI && + "Reserved CSR spill slot frame index mismatch in CSI"); + continue; + } + NewCSIs.push_back(CSI); + } + MFI.setCalleeSavedInfo(std::move(NewCSIs)); +} + // Not preserve stack space within prologue for outgoing variables when the // function contains variable size objects or there are vector objects accessed // by the frame pointer. diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.h b/llvm/lib/Target/RISCV/RISCVFrameLowering.h index 5c1c7317d24bc6a160f7f091cb6aa2b8f3209b1c..a784479f111b1158f0bf354905d7a2e2fd15709d 100644 --- a/llvm/lib/Target/RISCV/RISCVFrameLowering.h +++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.h @@ -37,6 +37,10 @@ public: void processFunctionBeforeFrameFinalized(MachineFunction &MF, RegScavenger *RS) const override; + void + processFunctionBeforeFrameIndicesReplaced(MachineFunction &MF, + RegScavenger *RS) const override; + bool hasFP(const MachineFunction &MF) const override; bool hasBP(const MachineFunction &MF) const; diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index 48ca7b74384c6140950ecd5e526347d17d631215..80797e36ad40fed9922e41f8708c2383cfc1796b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -2081,10 +2081,10 @@ void RISCVDAGToDAGISel::Select(SDNode *Node) { break; RISCVII::VLMUL SubVecLMUL = RISCVTargetLowering::getLMUL(SubVecContainerVT); - bool IsSubVecPartReg = SubVecLMUL == RISCVII::VLMUL::LMUL_F2 || - SubVecLMUL == RISCVII::VLMUL::LMUL_F4 || - SubVecLMUL == RISCVII::VLMUL::LMUL_F8; - (void)IsSubVecPartReg; // Silence unused variable warning without asserts. + [[maybe_unused]] bool IsSubVecPartReg = + SubVecLMUL == RISCVII::VLMUL::LMUL_F2 || + SubVecLMUL == RISCVII::VLMUL::LMUL_F4 || + SubVecLMUL == RISCVII::VLMUL::LMUL_F8; assert((!IsSubVecPartReg || V.isUndef()) && "Expecting lowering to have created legal INSERT_SUBVECTORs when " "the subvector is smaller than a full-sized register"); @@ -2263,9 +2263,8 @@ bool RISCVDAGToDAGISel::SelectInlineAsmMemoryOperand( case InlineAsm::ConstraintCode::o: case InlineAsm::ConstraintCode::m: { SDValue Op0, Op1; - bool Found = SelectAddrRegImm(Op, Op0, Op1); + [[maybe_unused]] bool Found = SelectAddrRegImm(Op, Op0, Op1); assert(Found && "SelectAddrRegImm should always succeed"); - (void)Found; OutOps.push_back(Op0); OutOps.push_back(Op1); return false; diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 9f501ea7425dede7bac6682e924b1183dcf3e317..27037f4d5c5c85743728a2f059ba42b5aa9abf0b 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -8512,12 +8512,12 @@ static SDValue lowerGetVectorLength(SDNode *N, SelectionDAG &DAG, // Determine the VF that corresponds to LMUL 1 for ElementWidth. unsigned LMul1VF = RISCV::RVVBitsPerBlock / ElementWidth; // We don't support VF==1 with ELEN==32. - unsigned MinVF = RISCV::RVVBitsPerBlock / Subtarget.getELen(); + [[maybe_unused]] unsigned MinVF = + RISCV::RVVBitsPerBlock / Subtarget.getELen(); - unsigned VF = N->getConstantOperandVal(2); + [[maybe_unused]] unsigned VF = N->getConstantOperandVal(2); assert(VF >= MinVF && VF <= (LMul1VF * 8) && isPowerOf2_32(VF) && "Unexpected VF"); - (void)MinVF; bool Fractional = VF < LMul1VF; unsigned LMulVal = Fractional ? LMul1VF / VF : VF / LMul1VF; @@ -11227,7 +11227,7 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op, SDValue Chain = MemSD->getChain(); SDValue BasePtr = MemSD->getBasePtr(); - ISD::LoadExtType LoadExtType; + [[maybe_unused]] ISD::LoadExtType LoadExtType; SDValue Index, Mask, PassThru, VL; if (auto *VPGN = dyn_cast(Op.getNode())) { @@ -11255,7 +11255,6 @@ SDValue RISCVTargetLowering::lowerMaskedGather(SDValue Op, // Targets have to explicitly opt-in for extending vector loads. assert(LoadExtType == ISD::NON_EXTLOAD && "Unexpected extending MGATHER/VP_GATHER"); - (void)LoadExtType; // If the mask is known to be all ones, optimize to an unmasked intrinsic; // the selection of the masked intrinsics doesn't do this for us. @@ -11325,7 +11324,7 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op, SDValue Chain = MemSD->getChain(); SDValue BasePtr = MemSD->getBasePtr(); - bool IsTruncatingStore = false; + [[maybe_unused]] bool IsTruncatingStore = false; SDValue Index, Mask, Val, VL; if (auto *VPSN = dyn_cast(Op.getNode())) { @@ -11354,7 +11353,6 @@ SDValue RISCVTargetLowering::lowerMaskedScatter(SDValue Op, // Targets have to explicitly opt-in for extending vector loads and // truncating vector stores. assert(!IsTruncatingStore && "Unexpected truncating MSCATTER/VP_SCATTER"); - (void)IsTruncatingStore; // If the mask is known to be all ones, optimize to an unmasked intrinsic; // the selection of the masked intrinsics doesn't do this for us. diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index df516d7cd5c09811180b65c0d41d375f2238e707..89eb71d917428e2b56cce40989aaa1a76485f8fc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -1172,7 +1172,6 @@ bool RISCVInstrInfo::optimizeCondBranch(MachineInstr &MI) const { SmallVector Cond; if (analyzeBranch(*MBB, TBB, FBB, Cond, /*AllowModify=*/false)) return false; - (void)FBB; RISCVCC::CondCode CC = static_cast(Cond[0].getImm()); assert(CC != RISCVCC::COND_INVALID); diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td index c00dfd8937da94a5aaac6b6c7ba844a738eb085c..518982441e7c0ab926848c86eb62852178295f7b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td @@ -1358,189 +1358,6 @@ def riscv_selectcc_frag : PatFrag<(ops node:$lhs, node:$rhs, node:$cc, node:$falsev), [{}], IntCCtoRISCVCC>; -let Predicates = [HasShortForwardBranchOpt], isSelect = 1, - Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in { -// This instruction moves $truev to $dst when the condition is true. It will -// be expanded to control flow in RISCVExpandPseudoInsts. -def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$truev), - [(set GPR:$dst, - (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), - GPR:$rhs, cond, - (XLenVT GPR:$truev), - GPR:$falsev))]>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU]>; -} - -// This should always expand to a branch+c.mv so the size is 6 or 4 if the -// branch is compressible. -let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], - Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in { -// This instruction moves $truev to $dst when the condition is true. It will -// be expanded to control flow in RISCVExpandPseudoInsts. -// We use GPRNoX0 because c.mv cannot encode X0. -def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPRNoX0:$falsev, GPRNoX0:$truev), - [(set GPRNoX0:$dst, - (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), - (XLenVT GPR:$rhs), - cond, (XLenVT GPRNoX0:$truev), - (XLenVT GPRNoX0:$falsev)))]>, - Sched<[]>; -} - -// Conditional binops, that updates update $dst to (op rs1, rs2) when condition -// is true. Returns $falsev otherwise. Selected by optimizeSelect. -// TODO: Can we use DefaultOperands on the regular binop to accomplish this more -// like how ARM does predication? -let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Size = 8, - Constraints = "$dst = $falsev" in { -def PseudoCCADD : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCSUB : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCSLL : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU, ReadSFBALU]>; -def PseudoCCSRL : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU, ReadSFBALU]>; -def PseudoCCSRA : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU, ReadSFBALU]>; -def PseudoCCAND : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCXOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; - -def PseudoCCADDI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCSLLI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCSRLI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCSRAI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCANDI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCORI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCXORI : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; - -// RV64I instructions -def PseudoCCADDW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCSUBW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCSLLW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU, ReadSFBALU]>; -def PseudoCCSRLW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU, ReadSFBALU]>; -def PseudoCCSRAW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU, ReadSFBALU]>; - -def PseudoCCADDIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCSLLIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCSRLIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; -def PseudoCCSRAIW : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, - ReadSFBALU]>; - -// Zbb/Zbkb instructions -def PseudoCCANDN : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCORN : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -def PseudoCCXNOR : Pseudo<(outs GPR:$dst), - (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, - GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, - Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, - ReadSFBALU, ReadSFBALU, ReadSFBALU]>; -} - multiclass SelectCC_GPR_rrirr { let usesCustomInserter = 1 in def _Using_CC_GPR : Pseudo<(outs valty:$dst), @@ -2057,15 +1874,6 @@ def : Pat<(binop_allwusers GPR:$rs1, (AddiPair:$rs2)), (AddiPairImmSmall AddiPair:$rs2))>; } -let Predicates = [HasShortForwardBranchOpt] in -def : Pat<(XLenVT (abs GPR:$rs1)), - (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2, - (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>; -let Predicates = [HasShortForwardBranchOpt, IsRV64] in -def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32), - (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2, - (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>; - //===----------------------------------------------------------------------===// // Experimental RV64 i32 legalization patterns. //===----------------------------------------------------------------------===// @@ -2182,6 +1990,7 @@ include "RISCVInstrInfoZicfiss.td" include "RISCVInstrInfoXVentana.td" include "RISCVInstrInfoXTHead.td" include "RISCVInstrInfoXSf.td" +include "RISCVInstrInfoSFB.td" include "RISCVInstrInfoXCV.td" //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td new file mode 100644 index 0000000000000000000000000000000000000000..f25dc7302608baf613c8b6eb9bcb1b86b0880b1a --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoSFB.td @@ -0,0 +1,203 @@ +//===-- RISCVInstrInfoSFB.td - Pseudos for SFB -------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file describes the pseudos for SFB (Short Forward Branch). +// +//===----------------------------------------------------------------------===// + +let Predicates = [HasShortForwardBranchOpt], isSelect = 1, + Constraints = "$dst = $falsev", isCommutable = 1, Size = 8 in { +// This instruction moves $truev to $dst when the condition is true. It will +// be expanded to control flow in RISCVExpandPseudoInsts. +def PseudoCCMOVGPR : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$truev), + [(set GPR:$dst, + (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), + GPR:$rhs, cond, + (XLenVT GPR:$truev), + GPR:$falsev))]>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU]>; +} + +// This should always expand to a branch+c.mv so the size is 6 or 4 if the +// branch is compressible. +let Predicates = [HasConditionalMoveFusion, NoShortForwardBranchOpt], + Constraints = "$dst = $falsev", isCommutable = 1, Size = 6 in { +// This instruction moves $truev to $dst when the condition is true. It will +// be expanded to control flow in RISCVExpandPseudoInsts. +// We use GPRNoX0 because c.mv cannot encode X0. +def PseudoCCMOVGPRNoX0 : Pseudo<(outs GPRNoX0:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPRNoX0:$falsev, GPRNoX0:$truev), + [(set GPRNoX0:$dst, + (riscv_selectcc_frag:$cc (XLenVT GPR:$lhs), + (XLenVT GPR:$rhs), + cond, (XLenVT GPRNoX0:$truev), + (XLenVT GPRNoX0:$falsev)))]>, + Sched<[]>; +} + +// Conditional binops, that updates update $dst to (op rs1, rs2) when condition +// is true. Returns $falsev otherwise. Selected by optimizeSelect. +// TODO: Can we use DefaultOperands on the regular binop to accomplish this more +// like how ARM does predication? +let Predicates = [HasShortForwardBranchOpt], hasSideEffects = 0, + mayLoad = 0, mayStore = 0, Size = 8, Constraints = "$dst = $falsev" in { +def PseudoCCADD : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCSUB : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCSLL : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU, ReadSFBALU]>; +def PseudoCCSRL : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU, ReadSFBALU]>; +def PseudoCCSRA : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU, ReadSFBALU]>; +def PseudoCCAND : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCOR : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCXOR : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; + +def PseudoCCADDI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCSLLI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCSRLI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCSRAI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCANDI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCORI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCXORI : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; + +// RV64I instructions +def PseudoCCADDW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCSUBW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCSLLW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU, ReadSFBALU]>; +def PseudoCCSRLW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU, ReadSFBALU]>; +def PseudoCCSRAW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU, ReadSFBALU]>; + +def PseudoCCADDIW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCSLLIW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCSRLIW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; +def PseudoCCSRAIW : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, simm12:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, ReadSFBALU, + ReadSFBALU]>; + +// Zbb/Zbkb instructions +def PseudoCCANDN : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCORN : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +def PseudoCCXNOR : Pseudo<(outs GPR:$dst), + (ins GPR:$lhs, GPR:$rhs, ixlenimm:$cc, + GPR:$falsev, GPR:$rs1, GPR:$rs2), []>, + Sched<[WriteSFB, ReadSFBJmp, ReadSFBJmp, + ReadSFBALU, ReadSFBALU, ReadSFBALU]>; +} + +let Predicates = [HasShortForwardBranchOpt] in +def : Pat<(XLenVT (abs GPR:$rs1)), + (PseudoCCSUB (XLenVT GPR:$rs1), (XLenVT X0), /* COND_LT */ 2, + (XLenVT GPR:$rs1), (XLenVT X0), (XLenVT GPR:$rs1))>; +let Predicates = [HasShortForwardBranchOpt, IsRV64] in +def : Pat<(sext_inreg (abs 33signbits_node:$rs1), i32), + (PseudoCCSUBW (i64 GPR:$rs1), (i64 X0), /* COND_LT */ 2, + (i64 GPR:$rs1), (i64 X0), (i64 GPR:$rs1))>; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td index 9fc9a29c210df2d3d23fe1f37d9757730e0ff68f..d2d824da9c7831788d10064cb4a850d6e7aea604 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoV.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoV.td @@ -861,9 +861,9 @@ multiclass VMSFS_MV_V funct6, bits<5> vs1> { SchedUnaryMC<"WriteVMSFSV", "ReadVMSFSV">; } -multiclass VMIOT_MV_V funct6, bits<5> vs1> { +multiclass VIOTA_MV_V funct6, bits<5> vs1> { def "" : VALUVs2, - SchedUnaryMC<"WriteVMIotV", "ReadVMIotV">; + SchedUnaryMC<"WriteVIotaV", "ReadVIotaV">; } multiclass VSHT_IV_V_X_I funct6> { @@ -1621,7 +1621,7 @@ defm VMSIF_M : VMSFS_MV_V<"vmsif.m", 0b010100, 0b00011>; // vmsof.m set-only-first mask bit defm VMSOF_M : VMSFS_MV_V<"vmsof.m", 0b010100, 0b00010>; // Vector Iota Instruction -defm VIOTA_M : VMIOT_MV_V<"viota.m", 0b010100, 0b10000>; +defm VIOTA_M : VIOTA_MV_V<"viota.m", 0b010100, 0b10000>; } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota @@ -1631,7 +1631,7 @@ let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in { let vs2 = 0 in def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd), (ins VMaskOp:$vm), "vid.v", "$vd$vm">, - SchedNullaryMC<"WriteVMIdxV">; + SchedNullaryMC<"WriteVIdxV">; // Integer Scalar Move Instructions let vm = 1, RVVConstraint = NoConstraint in { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index d3973f9b2edcf0d960afca2e2f00a04a59228659..48cf48e8af58fbeebf08d17c7be7f48a46b346b7 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2066,10 +2066,10 @@ multiclass VPseudoVID_V { defvar mx = m.MX; let VLMul = m.value in { def "_V_" # mx : VPseudoNullaryNoMask, - SchedNullary<"WriteVMIdxV", mx, forceMergeOpRead=true>; + SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>; def "_V_" # mx # "_MASK" : VPseudoNullaryMask, RISCVMaskedPseudo, - SchedNullary<"WriteVMIdxV", mx, + SchedNullary<"WriteVIdxV", mx, forceMergeOpRead=true>; } } @@ -2084,17 +2084,17 @@ multiclass VPseudoNullaryPseudoM { } } -multiclass VPseudoVIOT_M { +multiclass VPseudoVIOTA_M { defvar constraint = "@earlyclobber $rd"; foreach m = MxList in { defvar mx = m.MX; let VLMul = m.value in { def "_" # mx : VPseudoUnaryNoMask, - SchedUnary<"WriteVMIotV", "ReadVMIotV", mx, + SchedUnary<"WriteVIotaV", "ReadVIotaV", mx, forceMergeOpRead=true>; def "_" # mx # "_MASK" : VPseudoUnaryMask, RISCVMaskedPseudo, - SchedUnary<"WriteVMIotV", "ReadVMIotV", mx, + SchedUnary<"WriteVIotaV", "ReadVIotaV", mx, forceMergeOpRead=true>; } } @@ -6747,7 +6747,7 @@ defm PseudoVMSOF: VPseudoVSFS_M; //===----------------------------------------------------------------------===// // 15.8. Vector Iota Instruction //===----------------------------------------------------------------------===// -defm PseudoVIOTA_M: VPseudoVIOT_M; +defm PseudoVIOTA_M: VPseudoVIOTA_M; //===----------------------------------------------------------------------===// // 15.9. Vector Element Index Instruction diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td index 3506204d6c25536786c3f434a32d72958013fddb..a3ec2e5667ee5801561ff9c4672767120fd28ed3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZc.td @@ -190,16 +190,19 @@ def CM_MVSA01 : RVInst16CA<0b101011, 0b01, 0b10, (outs SR07:$rs1, SR07:$rs2), } // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]... let DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp] in { -let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in +let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Uses = [X2], Defs = [X2] in def CM_PUSH : RVInstZcCPPP<0b11000, "cm.push">; -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1, + Uses = [X2], Defs = [X2] in def CM_POPRET : RVInstZcCPPP<0b11110, "cm.popret">; -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, isReturn = 1, + Uses = [X2], Defs = [X2, X10] in def CM_POPRETZ : RVInstZcCPPP<0b11100, "cm.popretz">; -let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in +let hasSideEffects = 0, mayLoad = 1, mayStore = 0, + Uses = [X2], Defs = [X2] in def CM_POP : RVInstZcCPPP<0b11010, "cm.pop">; } // DecoderNamespace = "RVZcmp", Predicates = [HasStdExtZcmp]... diff --git a/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp index 009dcf57f46da425ded3badb52b65549a5fdd757..098e5bb5328bb3035877d1d505061cfd0f475f77 100644 --- a/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp +++ b/llvm/lib/Target/RISCV/RISCVPushPopOptimizer.cpp @@ -62,9 +62,19 @@ bool RISCVPushPopOpt::usePopRet(MachineBasicBlock::iterator &MBBI, // this will detect all ret instruction. DebugLoc DL = NextI->getDebugLoc(); unsigned Opc = IsReturnZero ? RISCV::CM_POPRETZ : RISCV::CM_POPRET; - BuildMI(*NextI->getParent(), NextI, DL, TII->get(Opc)) - .add(MBBI->getOperand(0)) - .add(MBBI->getOperand(1)); + MachineInstrBuilder PopRetBuilder = + BuildMI(*NextI->getParent(), NextI, DL, TII->get(Opc)) + .add(MBBI->getOperand(0)) + .add(MBBI->getOperand(1)); + + // Copy over the variable implicit uses and defs from the CM_POP. They depend + // on what register list has been picked during frame lowering. + const MCInstrDesc &PopDesc = MBBI->getDesc(); + unsigned FirstNonDeclaredOp = PopDesc.getNumOperands() + + PopDesc.NumImplicitUses + + PopDesc.NumImplicitDefs; + for (unsigned i = FirstNonDeclaredOp; i < MBBI->getNumOperands(); ++i) + PopRetBuilder.add(MBBI->getOperand(i)); MBBI->eraseFromParent(); NextI->eraseFromParent(); diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td index 976b88250e45e5adf06bee2d29de3abd50416cb7..040cec42674000800a1c80c897095a2cb2178110 100644 --- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td +++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td @@ -868,8 +868,8 @@ foreach mx = SchedMxList in { defvar Cycles = SiFive7GetCyclesDefault.c; defvar IsWorstCase = SiFive7IsWorstCaseMX.c; let Latency = 4, AcquireAtCycles = [0, 1], ReleaseAtCycles = [1, !add(1, Cycles)] in { - defm "" : LMULWriteResMX<"WriteVMIotV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; - defm "" : LMULWriteResMX<"WriteVMIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIotaV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; + defm "" : LMULWriteResMX<"WriteVIdxV", [SiFive7VCQ, SiFive7VA], mx, IsWorstCase>; } } @@ -1173,7 +1173,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>; defm "" : LMULReadAdvance<"ReadVMPopV", 0>; defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; -defm "" : LMULReadAdvance<"ReadVMIotV", 0>; +defm "" : LMULReadAdvance<"ReadVIotaV", 0>; // 17. Vector Permutation Instructions def : ReadAdvance; diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td index 29f2ceec25fa618871ed955fcc8415b2d0be5b73..d15cb611ae665efa45ab2fbec23c5e1ea3405173 100644 --- a/llvm/lib/Target/RISCV/RISCVScheduleV.td +++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td @@ -473,9 +473,9 @@ defm "" : LMULSchedWrites<"WriteVMFFSV">; // 15.6. Vector Set-only-First Mask Bit defm "" : LMULSchedWrites<"WriteVMSFSV">; // 15.8. Vector Iota Instruction -defm "" : LMULSchedWrites<"WriteVMIotV">; +defm "" : LMULSchedWrites<"WriteVIotaV">; // 15.9. Vector Element Index Instruction -defm "" : LMULSchedWrites<"WriteVMIdxV">; +defm "" : LMULSchedWrites<"WriteVIdxV">; // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions @@ -700,7 +700,7 @@ defm "" : LMULSchedReads<"ReadVMFFSV">; // 15.6. Vector Set-only-First Mask Bit defm "" : LMULSchedReads<"ReadVMSFSV">; // 15.8. Vector Iota Instruction -defm "" : LMULSchedReads<"ReadVMIotV">; +defm "" : LMULSchedReads<"ReadVIotaV">; // 16. Vector Permutation Instructions // 16.1. Integer Scalar Move Instructions @@ -912,8 +912,8 @@ defm "" : LMULWriteRes<"WriteVMALUV", []>; defm "" : LMULWriteRes<"WriteVMPopV", []>; defm "" : LMULWriteRes<"WriteVMFFSV", []>; defm "" : LMULWriteRes<"WriteVMSFSV", []>; -defm "" : LMULWriteRes<"WriteVMIotV", []>; -defm "" : LMULWriteRes<"WriteVMIdxV", []>; +defm "" : LMULWriteRes<"WriteVIotaV", []>; +defm "" : LMULWriteRes<"WriteVIdxV", []>; // 16. Vector Permutation Instructions def : WriteRes; @@ -1074,7 +1074,7 @@ defm "" : LMULReadAdvance<"ReadVMALUV", 0>; defm "" : LMULReadAdvance<"ReadVMPopV", 0>; defm "" : LMULReadAdvance<"ReadVMFFSV", 0>; defm "" : LMULReadAdvance<"ReadVMSFSV", 0>; -defm "" : LMULReadAdvance<"ReadVMIotV", 0>; +defm "" : LMULReadAdvance<"ReadVIotaV", 0>; // 16. Vector Permutation Instructions def : ReadAdvance; diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index 2285c99d79010076b83919abb85677901bc213f6..4c3da3ad3111687e0daa4768a1bc860156a7aa02 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -355,33 +355,15 @@ public: ScheduleDAGInstrs * createMachineScheduler(MachineSchedContext *C) const override { - const RISCVSubtarget &ST = C->MF->getSubtarget(); ScheduleDAGMILive *DAG = nullptr; if (EnableMISchedLoadClustering) { DAG = createGenericSchedLive(C); DAG->addMutation(createLoadClusterDAGMutation( DAG->TII, DAG->TRI, /*ReorderWhileClustering=*/true)); } - const auto &MacroFusions = ST.getMacroFusions(); - if (!MacroFusions.empty()) { - DAG = DAG ? DAG : createGenericSchedLive(C); - DAG->addMutation(createMacroFusionDAGMutation(MacroFusions)); - } return DAG; } - ScheduleDAGInstrs * - createPostMachineScheduler(MachineSchedContext *C) const override { - const RISCVSubtarget &ST = C->MF->getSubtarget(); - const auto &MacroFusions = ST.getMacroFusions(); - if (!MacroFusions.empty()) { - ScheduleDAGMI *DAG = createGenericSchedPostRA(C); - DAG->addMutation(createMacroFusionDAGMutation(MacroFusions)); - return DAG; - } - return nullptr; - } - void addIRPasses() override; bool addPreISel() override; bool addInstSelector() override; diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp index 243461c0316e53bcdabaa2515294cfd84a939804..81917706872676eb32af45d0a13c9ed26005d4a7 100644 --- a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp +++ b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp @@ -889,14 +889,18 @@ static void printFormattedRegName(const MCAsmInfo *MAI, unsigned RegNo, OS << '%' << RegName; } +static void printReg(unsigned Reg, const MCAsmInfo *MAI, raw_ostream &OS) { + if (!Reg) + OS << '0'; + else + printFormattedRegName(MAI, Reg, OS); +} + static void printOperand(const MCOperand &MCOp, const MCAsmInfo *MAI, raw_ostream &OS) { - if (MCOp.isReg()) { - if (!MCOp.getReg()) - OS << '0'; - else - printFormattedRegName(MAI, MCOp.getReg(), OS); - } else if (MCOp.isImm()) + if (MCOp.isReg()) + printReg(MCOp.getReg(), MAI, OS); + else if (MCOp.isImm()) OS << MCOp.getImm(); else if (MCOp.isExpr()) MCOp.getExpr()->print(OS, MAI); @@ -946,6 +950,21 @@ bool SystemZAsmPrinter::PrintAsmMemoryOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS) { + if (ExtraCode && ExtraCode[0] && !ExtraCode[1]) { + switch (ExtraCode[0]) { + case 'A': + // Unlike EmitMachineNode(), EmitSpecialNode(INLINEASM) does not call + // setMemRefs(), so MI->memoperands() is empty and the alignment + // information is not available. + return false; + case 'O': + OS << MI->getOperand(OpNo + 1).getImm(); + return false; + case 'R': + ::printReg(MI->getOperand(OpNo).getReg(), MAI, OS); + return false; + } + } printAddress(MAI, MI->getOperand(OpNo).getReg(), MCOperand::createImm(MI->getOperand(OpNo + 1).getImm()), MI->getOperand(OpNo + 2).getReg(), OS); diff --git a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp index ed7757be6615827c757d8813d825a42b25280f7c..861f9f8b5b1ba9f66f9b7e8af29298fff18393f9 100644 --- a/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp +++ b/llvm/lib/Target/WebAssembly/Disassembler/WebAssemblyDisassembler.cpp @@ -16,6 +16,7 @@ #include "MCTargetDesc/WebAssemblyMCTypeUtilities.h" #include "TargetInfo/WebAssemblyTargetInfo.h" +#include "llvm/BinaryFormat/Wasm.h" #include "llvm/MC/MCContext.h" #include "llvm/MC/MCDecoderOps.h" #include "llvm/MC/MCDisassembler/MCDisassembler.h" @@ -127,7 +128,7 @@ WebAssemblyDisassembler::onSymbolStart(SymbolInfoTy &Symbol, uint64_t &Size, uint64_t Address, raw_ostream &CStream) const { Size = 0; - if (Address == 0) { + if (Symbol.Type == wasm::WASM_SYMBOL_TYPE_SECTION) { // Start of a code section: we're parsing only the function count. int64_t FunctionCount; if (!nextLEB(FunctionCount, Bytes, Size, false)) diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp index 7f0140a5e8c66f38563b5b2ada53853d97a82ee4..1c62290704fe475d73e266858a7d694557bc31d9 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyFastISel.cpp @@ -559,6 +559,8 @@ unsigned WebAssemblyFastISel::getRegForUnsignedValue(const Value *V) { Register VReg = getRegForValue(V); if (VReg == 0) return 0; + if (From == To) + return VReg; return zeroExtend(VReg, V, From, To); } @@ -568,6 +570,8 @@ unsigned WebAssemblyFastISel::getRegForSignedValue(const Value *V) { Register VReg = getRegForValue(V); if (VReg == 0) return 0; + if (From == To) + return VReg; return signExtend(VReg, V, From, To); } diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index 981d28a739339474f32bb0f92828bd158ec03bf6..42043a7b8680a4e7934c2bb2c9de72c3ff541288 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -403,7 +403,7 @@ static void basicCheckForEHAndSjLj(TargetMachine *TM) { TM->Options.ExceptionModel == ExceptionHandling::Wasm) report_fatal_error( "-exception-model=wasm only allowed with at least one of " - "-wasm-enable-eh or -wasm-enable-sjj"); + "-wasm-enable-eh or -wasm-enable-sjlj"); // You can't enable two modes of EH at the same time if (WasmEnableEmEH && WasmEnableEH) diff --git a/llvm/lib/Target/X86/X86FastISel.cpp b/llvm/lib/Target/X86/X86FastISel.cpp index 1ce1e6f6a563552b16dc379d6b1a859d3cb3932e..9368de62817b3d570dbdcc904415c1dcbd25d3aa 100644 --- a/llvm/lib/Target/X86/X86FastISel.cpp +++ b/llvm/lib/Target/X86/X86FastISel.cpp @@ -1250,19 +1250,18 @@ bool X86FastISel::X86SelectRet(const Instruction *I) { if (!Outs[0].Flags.isZExt() && !Outs[0].Flags.isSExt()) return false; - assert(DstVT == MVT::i32 && "X86 should always ext to i32"); - if (SrcVT == MVT::i1) { if (Outs[0].Flags.isSExt()) return false; - // TODO SrcReg = fastEmitZExtFromI1(MVT::i8, SrcReg); SrcVT = MVT::i8; } - unsigned Op = Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : - ISD::SIGN_EXTEND; - // TODO - SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); + if (SrcVT != DstVT) { + unsigned Op = + Outs[0].Flags.isZExt() ? ISD::ZERO_EXTEND : ISD::SIGN_EXTEND; + SrcReg = + fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); + } } // Make the copy. diff --git a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp index f65fa5a2298ac87de00de05e0d04cce28f686af8..9c46cee572fc911189406c4d6b0406aa851765ba 100644 --- a/llvm/lib/Target/X86/X86FixupVectorConstants.cpp +++ b/llvm/lib/Target/X86/X86FixupVectorConstants.cpp @@ -8,9 +8,10 @@ // // This file examines all full size vector constant pool loads and attempts to // replace them with smaller constant pool entries, including: -// * Converting AVX512 memory-fold instructions to their broadcast-fold form +// * Converting AVX512 memory-fold instructions to their broadcast-fold form. +// * Using vzload scalar loads. // * Broadcasting of full width loads. -// * TODO: Zero extension of full width loads. +// * Sign/Zero extension of full width loads. // //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 9a9b0680acc2012035dc41c68b66826acd9de4c0..b5b76c66c2e49edb58354ecc11296036fbb2aea8 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -18710,16 +18710,18 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const { if (Subtarget.isTargetDarwin()) { // Darwin only has one model of TLS. Lower to that. unsigned char OpFlag = 0; - unsigned WrapperKind = Subtarget.isPICStyleRIPRel() ? - X86ISD::WrapperRIP : X86ISD::Wrapper; + unsigned WrapperKind = 0; // In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the // global base reg. bool PIC32 = PositionIndependent && !Subtarget.is64Bit(); - if (PIC32) + if (PIC32) { OpFlag = X86II::MO_TLVP_PIC_BASE; - else + WrapperKind = X86ISD::Wrapper; + } else { OpFlag = X86II::MO_TLVP; + WrapperKind = X86ISD::WrapperRIP; + } SDLoc DL(Op); SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL, GA->getValueType(0), diff --git a/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp b/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp index 40b57b5e40ea33a11213a6d90e08160bbe24e66c..25b9499d189577a6eb7d35fcf3dd4cfd3d074ffd 100644 --- a/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp +++ b/llvm/lib/TextAPI/BinaryReader/DylibReader.cpp @@ -408,6 +408,7 @@ Expected DylibReader::readFile(MemoryBufferRef Buffer, Results.emplace_back(std::make_shared(RecordsSlice({T}))); if (auto Err = load(&Obj, *Results.back(), Opt, Arch)) return std::move(Err); + Results.back()->getBinaryAttrs().Path = Buffer.getBufferIdentifier(); } break; } diff --git a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp index 7758b52abc204667da5d4b9a869f78fd708cdaa6..aed4cd027d033882862fd9116396a83192989b13 100644 --- a/llvm/lib/Transforms/Coroutines/CoroSplit.cpp +++ b/llvm/lib/Transforms/Coroutines/CoroSplit.cpp @@ -208,17 +208,12 @@ static bool replaceCoroEndAsync(AnyCoroEndInst *End) { // Insert the return instruction. Builder.SetInsertPoint(End); Builder.CreateRetVoid(); - InlineFunctionInfo FnInfo; // Remove the rest of the block, by splitting it into an unreachable block. auto *BB = End->getParent(); BB->splitBasicBlock(End); BB->getTerminator()->eraseFromParent(); - auto InlineRes = InlineFunction(*MustTailCall, FnInfo); - assert(InlineRes.isSuccess() && "Expected inlining to succeed"); - (void)InlineRes; - // We have cleaned up the coro.end block above. return false; } @@ -407,104 +402,6 @@ static void replaceCoroEnd(AnyCoroEndInst *End, const coro::Shape &Shape, End->eraseFromParent(); } -// Create an entry block for a resume function with a switch that will jump to -// suspend points. -static void createResumeEntryBlock(Function &F, coro::Shape &Shape) { - assert(Shape.ABI == coro::ABI::Switch); - LLVMContext &C = F.getContext(); - - // resume.entry: - // %index.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 0, - // i32 2 - // % index = load i32, i32* %index.addr - // switch i32 %index, label %unreachable [ - // i32 0, label %resume.0 - // i32 1, label %resume.1 - // ... - // ] - - auto *NewEntry = BasicBlock::Create(C, "resume.entry", &F); - auto *UnreachBB = BasicBlock::Create(C, "unreachable", &F); - - IRBuilder<> Builder(NewEntry); - auto *FramePtr = Shape.FramePtr; - auto *FrameTy = Shape.FrameTy; - auto *GepIndex = Builder.CreateStructGEP( - FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); - auto *Index = Builder.CreateLoad(Shape.getIndexType(), GepIndex, "index"); - auto *Switch = - Builder.CreateSwitch(Index, UnreachBB, Shape.CoroSuspends.size()); - Shape.SwitchLowering.ResumeSwitch = Switch; - - size_t SuspendIndex = 0; - for (auto *AnyS : Shape.CoroSuspends) { - auto *S = cast(AnyS); - ConstantInt *IndexVal = Shape.getIndex(SuspendIndex); - - // Replace CoroSave with a store to Index: - // %index.addr = getelementptr %f.frame... (index field number) - // store i32 %IndexVal, i32* %index.addr1 - auto *Save = S->getCoroSave(); - Builder.SetInsertPoint(Save); - if (S->isFinal()) { - // The coroutine should be marked done if it reaches the final suspend - // point. - markCoroutineAsDone(Builder, Shape, FramePtr); - } else { - auto *GepIndex = Builder.CreateStructGEP( - FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); - Builder.CreateStore(IndexVal, GepIndex); - } - - Save->replaceAllUsesWith(ConstantTokenNone::get(C)); - Save->eraseFromParent(); - - // Split block before and after coro.suspend and add a jump from an entry - // switch: - // - // whateverBB: - // whatever - // %0 = call i8 @llvm.coro.suspend(token none, i1 false) - // switch i8 %0, label %suspend[i8 0, label %resume - // i8 1, label %cleanup] - // becomes: - // - // whateverBB: - // whatever - // br label %resume.0.landing - // - // resume.0: ; <--- jump from the switch in the resume.entry - // %0 = tail call i8 @llvm.coro.suspend(token none, i1 false) - // br label %resume.0.landing - // - // resume.0.landing: - // %1 = phi i8[-1, %whateverBB], [%0, %resume.0] - // switch i8 % 1, label %suspend [i8 0, label %resume - // i8 1, label %cleanup] - - auto *SuspendBB = S->getParent(); - auto *ResumeBB = - SuspendBB->splitBasicBlock(S, "resume." + Twine(SuspendIndex)); - auto *LandingBB = ResumeBB->splitBasicBlock( - S->getNextNode(), ResumeBB->getName() + Twine(".landing")); - Switch->addCase(IndexVal, ResumeBB); - - cast(SuspendBB->getTerminator())->setSuccessor(0, LandingBB); - auto *PN = PHINode::Create(Builder.getInt8Ty(), 2, ""); - PN->insertBefore(LandingBB->begin()); - S->replaceAllUsesWith(PN); - PN->addIncoming(Builder.getInt8(-1), SuspendBB); - PN->addIncoming(S, ResumeBB); - - ++SuspendIndex; - } - - Builder.SetInsertPoint(UnreachBB); - Builder.CreateUnreachable(); - - Shape.SwitchLowering.ResumeEntryBlock = NewEntry; -} - // In the resume function, we remove the last case (when coro::Shape is built, // the final suspend point (if present) is always the last element of // CoroSuspends array) since it is an undefined behavior to resume a coroutine @@ -1161,16 +1058,6 @@ void CoroCloner::create() { /*Elide=*/ FKind == CoroCloner::Kind::SwitchCleanup); } -// Create a resume clone by cloning the body of the original function, setting -// new entry block and replacing coro.suspend an appropriate value to force -// resume or cleanup pass for every suspend point. -static Function *createClone(Function &F, const Twine &Suffix, - coro::Shape &Shape, CoroCloner::Kind FKind) { - CoroCloner Cloner(F, Suffix, Shape, FKind); - Cloner.create(); - return Cloner.getFunction(); -} - static void updateAsyncFuncPointerContextSize(coro::Shape &Shape) { assert(Shape.ABI == coro::ABI::Async); @@ -1212,67 +1099,6 @@ static void replaceFrameSizeAndAlignment(coro::Shape &Shape) { } } -// Create a global constant array containing pointers to functions provided and -// set Info parameter of CoroBegin to point at this constant. Example: -// -// @f.resumers = internal constant [2 x void(%f.frame*)*] -// [void(%f.frame*)* @f.resume, void(%f.frame*)* @f.destroy] -// define void @f() { -// ... -// call i8* @llvm.coro.begin(i8* null, i32 0, i8* null, -// i8* bitcast([2 x void(%f.frame*)*] * @f.resumers to i8*)) -// -// Assumes that all the functions have the same signature. -static void setCoroInfo(Function &F, coro::Shape &Shape, - ArrayRef Fns) { - // This only works under the switch-lowering ABI because coro elision - // only works on the switch-lowering ABI. - assert(Shape.ABI == coro::ABI::Switch); - - SmallVector Args(Fns.begin(), Fns.end()); - assert(!Args.empty()); - Function *Part = *Fns.begin(); - Module *M = Part->getParent(); - auto *ArrTy = ArrayType::get(Part->getType(), Args.size()); - - auto *ConstVal = ConstantArray::get(ArrTy, Args); - auto *GV = new GlobalVariable(*M, ConstVal->getType(), /*isConstant=*/true, - GlobalVariable::PrivateLinkage, ConstVal, - F.getName() + Twine(".resumers")); - - // Update coro.begin instruction to refer to this constant. - LLVMContext &C = F.getContext(); - auto *BC = ConstantExpr::getPointerCast(GV, PointerType::getUnqual(C)); - Shape.getSwitchCoroId()->setInfo(BC); -} - -// Store addresses of Resume/Destroy/Cleanup functions in the coroutine frame. -static void updateCoroFrame(coro::Shape &Shape, Function *ResumeFn, - Function *DestroyFn, Function *CleanupFn) { - assert(Shape.ABI == coro::ABI::Switch); - - IRBuilder<> Builder(&*Shape.getInsertPtAfterFramePtr()); - - auto *ResumeAddr = Builder.CreateStructGEP( - Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Resume, - "resume.addr"); - Builder.CreateStore(ResumeFn, ResumeAddr); - - Value *DestroyOrCleanupFn = DestroyFn; - - CoroIdInst *CoroId = Shape.getSwitchCoroId(); - if (CoroAllocInst *CA = CoroId->getCoroAlloc()) { - // If there is a CoroAlloc and it returns false (meaning we elide the - // allocation, use CleanupFn instead of DestroyFn). - DestroyOrCleanupFn = Builder.CreateSelect(CA, DestroyFn, CleanupFn); - } - - auto *DestroyAddr = Builder.CreateStructGEP( - Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Destroy, - "destroy.addr"); - Builder.CreateStore(DestroyOrCleanupFn, DestroyAddr); -} - static void postSplitCleanup(Function &F) { removeUnreachableBlocks(F); @@ -1447,34 +1273,6 @@ static bool shouldBeMustTail(const CallInst &CI, const Function &F) { return true; } -// Add musttail to any resume instructions that is immediately followed by a -// suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call -// for symmetrical coroutine control transfer (C++ Coroutines TS extension). -// This transformation is done only in the resume part of the coroutine that has -// identical signature and calling convention as the coro.resume call. -static void addMustTailToCoroResumes(Function &F, TargetTransformInfo &TTI) { - bool changed = false; - - // Collect potential resume instructions. - SmallVector Resumes; - for (auto &I : instructions(F)) - if (auto *Call = dyn_cast(&I)) - if (shouldBeMustTail(*Call, F)) - Resumes.push_back(Call); - - // Set musttail on those that are followed by a ret instruction. - for (CallInst *Call : Resumes) - // Skip targets which don't support tail call on the specific case. - if (TTI.supportsTailCallFor(Call) && - simplifyTerminatorLeadingToRet(Call->getNextNode())) { - Call->setTailCallKind(CallInst::TCK_MustTail); - changed = true; - } - - if (changed) - removeUnreachableBlocks(F); -} - // Coroutine has no suspend points. Remove heap allocation for the coroutine // frame if possible. static void handleNoSuspendCoroutine(coro::Shape &Shape) { @@ -1678,44 +1476,244 @@ static void simplifySuspendPoints(coro::Shape &Shape) { } } -static void splitSwitchCoroutine(Function &F, coro::Shape &Shape, - SmallVectorImpl &Clones, - TargetTransformInfo &TTI) { - assert(Shape.ABI == coro::ABI::Switch); - - createResumeEntryBlock(F, Shape); - auto ResumeClone = createClone(F, ".resume", Shape, - CoroCloner::Kind::SwitchResume); - auto DestroyClone = createClone(F, ".destroy", Shape, - CoroCloner::Kind::SwitchUnwind); - auto CleanupClone = createClone(F, ".cleanup", Shape, - CoroCloner::Kind::SwitchCleanup); - - postSplitCleanup(*ResumeClone); - postSplitCleanup(*DestroyClone); - postSplitCleanup(*CleanupClone); - - // Adding musttail call to support symmetric transfer. - // Skip targets which don't support tail call. - // - // FIXME: Could we support symmetric transfer effectively without musttail - // call? - if (TTI.supportsTailCalls()) - addMustTailToCoroResumes(*ResumeClone, TTI); +namespace { - // Store addresses resume/destroy/cleanup functions in the coroutine frame. - updateCoroFrame(Shape, ResumeClone, DestroyClone, CleanupClone); +struct SwitchCoroutineSplitter { + static void split(Function &F, coro::Shape &Shape, + SmallVectorImpl &Clones, + TargetTransformInfo &TTI) { + assert(Shape.ABI == coro::ABI::Switch); - assert(Clones.empty()); - Clones.push_back(ResumeClone); - Clones.push_back(DestroyClone); - Clones.push_back(CleanupClone); - - // Create a constant array referring to resume/destroy/clone functions pointed - // by the last argument of @llvm.coro.info, so that CoroElide pass can - // determined correct function to call. - setCoroInfo(F, Shape, Clones); -} + createResumeEntryBlock(F, Shape); + auto *ResumeClone = + createClone(F, ".resume", Shape, CoroCloner::Kind::SwitchResume); + auto *DestroyClone = + createClone(F, ".destroy", Shape, CoroCloner::Kind::SwitchUnwind); + auto *CleanupClone = + createClone(F, ".cleanup", Shape, CoroCloner::Kind::SwitchCleanup); + + postSplitCleanup(*ResumeClone); + postSplitCleanup(*DestroyClone); + postSplitCleanup(*CleanupClone); + + // Adding musttail call to support symmetric transfer. + // Skip targets which don't support tail call. + // + // FIXME: Could we support symmetric transfer effectively without musttail + // call? + if (TTI.supportsTailCalls()) + addMustTailToCoroResumes(*ResumeClone, TTI); + + // Store addresses resume/destroy/cleanup functions in the coroutine frame. + updateCoroFrame(Shape, ResumeClone, DestroyClone, CleanupClone); + + assert(Clones.empty()); + Clones.push_back(ResumeClone); + Clones.push_back(DestroyClone); + Clones.push_back(CleanupClone); + + // Create a constant array referring to resume/destroy/clone functions + // pointed by the last argument of @llvm.coro.info, so that CoroElide pass + // can determined correct function to call. + setCoroInfo(F, Shape, Clones); + } + +private: + // Create a resume clone by cloning the body of the original function, setting + // new entry block and replacing coro.suspend an appropriate value to force + // resume or cleanup pass for every suspend point. + static Function *createClone(Function &F, const Twine &Suffix, + coro::Shape &Shape, CoroCloner::Kind FKind) { + CoroCloner Cloner(F, Suffix, Shape, FKind); + Cloner.create(); + return Cloner.getFunction(); + } + + // Create an entry block for a resume function with a switch that will jump to + // suspend points. + static void createResumeEntryBlock(Function &F, coro::Shape &Shape) { + LLVMContext &C = F.getContext(); + + // resume.entry: + // %index.addr = getelementptr inbounds %f.Frame, %f.Frame* %FramePtr, i32 + // 0, i32 2 % index = load i32, i32* %index.addr switch i32 %index, label + // %unreachable [ + // i32 0, label %resume.0 + // i32 1, label %resume.1 + // ... + // ] + + auto *NewEntry = BasicBlock::Create(C, "resume.entry", &F); + auto *UnreachBB = BasicBlock::Create(C, "unreachable", &F); + + IRBuilder<> Builder(NewEntry); + auto *FramePtr = Shape.FramePtr; + auto *FrameTy = Shape.FrameTy; + auto *GepIndex = Builder.CreateStructGEP( + FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); + auto *Index = Builder.CreateLoad(Shape.getIndexType(), GepIndex, "index"); + auto *Switch = + Builder.CreateSwitch(Index, UnreachBB, Shape.CoroSuspends.size()); + Shape.SwitchLowering.ResumeSwitch = Switch; + + size_t SuspendIndex = 0; + for (auto *AnyS : Shape.CoroSuspends) { + auto *S = cast(AnyS); + ConstantInt *IndexVal = Shape.getIndex(SuspendIndex); + + // Replace CoroSave with a store to Index: + // %index.addr = getelementptr %f.frame... (index field number) + // store i32 %IndexVal, i32* %index.addr1 + auto *Save = S->getCoroSave(); + Builder.SetInsertPoint(Save); + if (S->isFinal()) { + // The coroutine should be marked done if it reaches the final suspend + // point. + markCoroutineAsDone(Builder, Shape, FramePtr); + } else { + auto *GepIndex = Builder.CreateStructGEP( + FrameTy, FramePtr, Shape.getSwitchIndexField(), "index.addr"); + Builder.CreateStore(IndexVal, GepIndex); + } + + Save->replaceAllUsesWith(ConstantTokenNone::get(C)); + Save->eraseFromParent(); + + // Split block before and after coro.suspend and add a jump from an entry + // switch: + // + // whateverBB: + // whatever + // %0 = call i8 @llvm.coro.suspend(token none, i1 false) + // switch i8 %0, label %suspend[i8 0, label %resume + // i8 1, label %cleanup] + // becomes: + // + // whateverBB: + // whatever + // br label %resume.0.landing + // + // resume.0: ; <--- jump from the switch in the resume.entry + // %0 = tail call i8 @llvm.coro.suspend(token none, i1 false) + // br label %resume.0.landing + // + // resume.0.landing: + // %1 = phi i8[-1, %whateverBB], [%0, %resume.0] + // switch i8 % 1, label %suspend [i8 0, label %resume + // i8 1, label %cleanup] + + auto *SuspendBB = S->getParent(); + auto *ResumeBB = + SuspendBB->splitBasicBlock(S, "resume." + Twine(SuspendIndex)); + auto *LandingBB = ResumeBB->splitBasicBlock( + S->getNextNode(), ResumeBB->getName() + Twine(".landing")); + Switch->addCase(IndexVal, ResumeBB); + + cast(SuspendBB->getTerminator())->setSuccessor(0, LandingBB); + auto *PN = PHINode::Create(Builder.getInt8Ty(), 2, ""); + PN->insertBefore(LandingBB->begin()); + S->replaceAllUsesWith(PN); + PN->addIncoming(Builder.getInt8(-1), SuspendBB); + PN->addIncoming(S, ResumeBB); + + ++SuspendIndex; + } + + Builder.SetInsertPoint(UnreachBB); + Builder.CreateUnreachable(); + + Shape.SwitchLowering.ResumeEntryBlock = NewEntry; + } + + // Add musttail to any resume instructions that is immediately followed by a + // suspend (i.e. ret). We do this even in -O0 to support guaranteed tail call + // for symmetrical coroutine control transfer (C++ Coroutines TS extension). + // This transformation is done only in the resume part of the coroutine that + // has identical signature and calling convention as the coro.resume call. + static void addMustTailToCoroResumes(Function &F, TargetTransformInfo &TTI) { + bool Changed = false; + + // Collect potential resume instructions. + SmallVector Resumes; + for (auto &I : instructions(F)) + if (auto *Call = dyn_cast(&I)) + if (shouldBeMustTail(*Call, F)) + Resumes.push_back(Call); + + // Set musttail on those that are followed by a ret instruction. + for (CallInst *Call : Resumes) + // Skip targets which don't support tail call on the specific case. + if (TTI.supportsTailCallFor(Call) && + simplifyTerminatorLeadingToRet(Call->getNextNode())) { + Call->setTailCallKind(CallInst::TCK_MustTail); + Changed = true; + } + + if (Changed) + removeUnreachableBlocks(F); + } + + // Store addresses of Resume/Destroy/Cleanup functions in the coroutine frame. + static void updateCoroFrame(coro::Shape &Shape, Function *ResumeFn, + Function *DestroyFn, Function *CleanupFn) { + IRBuilder<> Builder(&*Shape.getInsertPtAfterFramePtr()); + + auto *ResumeAddr = Builder.CreateStructGEP( + Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Resume, + "resume.addr"); + Builder.CreateStore(ResumeFn, ResumeAddr); + + Value *DestroyOrCleanupFn = DestroyFn; + + CoroIdInst *CoroId = Shape.getSwitchCoroId(); + if (CoroAllocInst *CA = CoroId->getCoroAlloc()) { + // If there is a CoroAlloc and it returns false (meaning we elide the + // allocation, use CleanupFn instead of DestroyFn). + DestroyOrCleanupFn = Builder.CreateSelect(CA, DestroyFn, CleanupFn); + } + + auto *DestroyAddr = Builder.CreateStructGEP( + Shape.FrameTy, Shape.FramePtr, coro::Shape::SwitchFieldIndex::Destroy, + "destroy.addr"); + Builder.CreateStore(DestroyOrCleanupFn, DestroyAddr); + } + + // Create a global constant array containing pointers to functions provided + // and set Info parameter of CoroBegin to point at this constant. Example: + // + // @f.resumers = internal constant [2 x void(%f.frame*)*] + // [void(%f.frame*)* @f.resume, void(%f.frame*)* + // @f.destroy] + // define void @f() { + // ... + // call i8* @llvm.coro.begin(i8* null, i32 0, i8* null, + // i8* bitcast([2 x void(%f.frame*)*] * @f.resumers to + // i8*)) + // + // Assumes that all the functions have the same signature. + static void setCoroInfo(Function &F, coro::Shape &Shape, + ArrayRef Fns) { + // This only works under the switch-lowering ABI because coro elision + // only works on the switch-lowering ABI. + SmallVector Args(Fns.begin(), Fns.end()); + assert(!Args.empty()); + Function *Part = *Fns.begin(); + Module *M = Part->getParent(); + auto *ArrTy = ArrayType::get(Part->getType(), Args.size()); + + auto *ConstVal = ConstantArray::get(ArrTy, Args); + auto *GV = new GlobalVariable(*M, ConstVal->getType(), /*isConstant=*/true, + GlobalVariable::PrivateLinkage, ConstVal, + F.getName() + Twine(".resumers")); + + // Update coro.begin instruction to refer to this constant. + LLVMContext &C = F.getContext(); + auto *BC = ConstantExpr::getPointerCast(GV, PointerType::getUnqual(C)); + Shape.getSwitchCoroId()->setInfo(BC); + } +}; + +} // namespace static void replaceAsyncResumeFunction(CoroSuspendAsyncInst *Suspend, Value *Continuation) { @@ -1839,13 +1837,8 @@ static void splitAsyncCoroutine(Function &F, coro::Shape &Shape, SmallVector Args(Suspend->args()); auto FnArgs = ArrayRef(Args).drop_front( CoroSuspendAsyncInst::MustTailCallFuncArg + 1); - auto *TailCall = - coro::createMustTailCall(Suspend->getDebugLoc(), Fn, FnArgs, Builder); + coro::createMustTailCall(Suspend->getDebugLoc(), Fn, FnArgs, Builder); Builder.CreateRetVoid(); - InlineFunctionInfo FnInfo; - auto InlineRes = InlineFunction(*TailCall, FnInfo); - assert(InlineRes.isSuccess() && "Expected inlining to succeed"); - (void)InlineRes; // Replace the lvm.coro.async.resume intrisic call. replaceAsyncResumeFunction(Suspend, Continuation); @@ -2027,7 +2020,7 @@ splitCoroutine(Function &F, SmallVectorImpl &Clones, } else { switch (Shape.ABI) { case coro::ABI::Switch: - splitSwitchCoroutine(F, Shape, Clones, TTI); + SwitchCoroutineSplitter::split(F, Shape, Clones, TTI); break; case coro::ABI::Async: splitAsyncCoroutine(F, Shape, Clones); diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp index 951372adcfa93e34feeeb0f88779202782dc38f8..42828b4f416800003738682791e5c92cbc3aae4e 100644 --- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp +++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp @@ -89,6 +89,8 @@ STATISTIC(NumAliasesRemoved, "Number of global aliases eliminated"); STATISTIC(NumCXXDtorsRemoved, "Number of global C++ destructors removed"); STATISTIC(NumInternalFunc, "Number of internal functions"); STATISTIC(NumColdCC, "Number of functions marked coldcc"); +STATISTIC(NumIFuncsResolved, "Number of statically resolved IFuncs"); +STATISTIC(NumIFuncsDeleted, "Number of IFuncs removed"); static cl::opt EnableColdCCStressTest("enable-coldcc-stress-test", @@ -2404,6 +2406,60 @@ static bool OptimizeEmptyGlobalCXXDtors(Function *CXAAtExitFn) { return Changed; } +static Function *hasSideeffectFreeStaticResolution(GlobalIFunc &IF) { + if (IF.isInterposable()) + return nullptr; + + Function *Resolver = IF.getResolverFunction(); + if (!Resolver) + return nullptr; + + if (Resolver->isInterposable()) + return nullptr; + + // Only handle functions that have been optimized into a single basic block. + auto It = Resolver->begin(); + if (++It != Resolver->end()) + return nullptr; + + BasicBlock &BB = Resolver->getEntryBlock(); + + if (any_of(BB, [](Instruction &I) { return I.mayHaveSideEffects(); })) + return nullptr; + + auto *Ret = dyn_cast(BB.getTerminator()); + if (!Ret) + return nullptr; + + return dyn_cast(Ret->getReturnValue()); +} + +/// Find IFuncs that have resolvers that always point at the same statically +/// known callee, and replace their callers with a direct call. +static bool OptimizeStaticIFuncs(Module &M) { + bool Changed = false; + for (GlobalIFunc &IF : M.ifuncs()) + if (Function *Callee = hasSideeffectFreeStaticResolution(IF)) + if (!IF.use_empty()) { + IF.replaceAllUsesWith(Callee); + NumIFuncsResolved++; + Changed = true; + } + return Changed; +} + +static bool +DeleteDeadIFuncs(Module &M, + SmallPtrSetImpl &NotDiscardableComdats) { + bool Changed = false; + for (GlobalIFunc &IF : make_early_inc_range(M.ifuncs())) + if (deleteIfDead(IF, NotDiscardableComdats)) { + NumIFuncsDeleted++; + Changed = true; + } + return Changed; +} + static bool optimizeGlobalsInModule(Module &M, const DataLayout &DL, function_ref GetTLI, @@ -2464,6 +2520,12 @@ optimizeGlobalsInModule(Module &M, const DataLayout &DL, if (CXAAtExitFn) LocalChange |= OptimizeEmptyGlobalCXXDtors(CXAAtExitFn); + // Optimize IFuncs whose callee's are statically known. + LocalChange |= OptimizeStaticIFuncs(M); + + // Remove any IFuncs that are now dead. + LocalChange |= DeleteDeadIFuncs(M, NotDiscardableComdats); + Changed |= LocalChange; } diff --git a/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp b/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp index d81239dd49e4cc3472a33a4069bd716db12e9aa5..323f33fcc862dc292ddd482b042e8f7b84163905 100644 --- a/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp +++ b/llvm/lib/Transforms/IPO/MemProfContextDisambiguation.cpp @@ -3475,7 +3475,11 @@ bool MemProfContextDisambiguation::applyImport(Module &M) { auto ContextIterBegin = StackContext.beginAfterSharedPrefix(CallsiteContext); // Skip the checking on the first iteration. - uint64_t LastStackContextId = *ContextIterBegin == 0 ? 1 : 0; + uint64_t LastStackContextId = + (ContextIterBegin != StackContext.end() && + *ContextIterBegin == 0) + ? 1 + : 0; for (auto ContextIter = ContextIterBegin; ContextIter != StackContext.end(); ++ContextIter) { // If this is a direct recursion, simply skip the duplicate diff --git a/llvm/lib/Transforms/IPO/MergeFunctions.cpp b/llvm/lib/Transforms/IPO/MergeFunctions.cpp index c8c011d94e4a3bf8e6717cd555ea637789537c74..4af9b2206745e2516961cb12b3b718e42ed68453 100644 --- a/llvm/lib/Transforms/IPO/MergeFunctions.cpp +++ b/llvm/lib/Transforms/IPO/MergeFunctions.cpp @@ -256,15 +256,20 @@ private: /// Fill PDIUnrelatedWL with instructions from the entry block that are /// unrelated to parameter related debug info. + /// \param PDPVUnrelatedWL The equivalent non-intrinsic debug records. void filterInstsUnrelatedToPDI(BasicBlock *GEntryBlock, - std::vector &PDIUnrelatedWL); + std::vector &PDIUnrelatedWL, + std::vector &PDPVUnrelatedWL); /// Erase the rest of the CFG (i.e. barring the entry block). void eraseTail(Function *G); /// Erase the instructions in PDIUnrelatedWL as they are unrelated to the /// parameter debug info, from the entry block. - void eraseInstsUnrelatedToPDI(std::vector &PDIUnrelatedWL); + /// \param PDPVUnrelatedWL contains the equivalent set of non-instruction + /// debug-info records. + void eraseInstsUnrelatedToPDI(std::vector &PDIUnrelatedWL, + std::vector &PDPVUnrelatedWL); /// Replace G with a simple tail call to bitcast(F). Also (unless /// MergeFunctionsPDI holds) replace direct uses of G with bitcast(F), @@ -506,7 +511,8 @@ static Value *createCast(IRBuilder<> &Builder, Value *V, Type *DestTy) { // Erase the instructions in PDIUnrelatedWL as they are unrelated to the // parameter debug info, from the entry block. void MergeFunctions::eraseInstsUnrelatedToPDI( - std::vector &PDIUnrelatedWL) { + std::vector &PDIUnrelatedWL, + std::vector &PDPVUnrelatedWL) { LLVM_DEBUG( dbgs() << " Erasing instructions (in reverse order of appearance in " "entry block) unrelated to parameter debug info from entry " @@ -519,6 +525,16 @@ void MergeFunctions::eraseInstsUnrelatedToPDI( I->eraseFromParent(); PDIUnrelatedWL.pop_back(); } + + while (!PDPVUnrelatedWL.empty()) { + DPValue *DPV = PDPVUnrelatedWL.back(); + LLVM_DEBUG(dbgs() << " Deleting DPValue "); + LLVM_DEBUG(DPV->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + DPV->eraseFromParent(); + PDPVUnrelatedWL.pop_back(); + } + LLVM_DEBUG(dbgs() << " } // Done erasing instructions unrelated to parameter " "debug info from entry block. \n"); } @@ -547,75 +563,99 @@ void MergeFunctions::eraseTail(Function *G) { // The rest are unrelated to debug info for the parameters; fill up // PDIUnrelatedWL with such instructions. void MergeFunctions::filterInstsUnrelatedToPDI( - BasicBlock *GEntryBlock, std::vector &PDIUnrelatedWL) { + BasicBlock *GEntryBlock, std::vector &PDIUnrelatedWL, + std::vector &PDPVUnrelatedWL) { std::set PDIRelated; - for (BasicBlock::iterator BI = GEntryBlock->begin(), BIE = GEntryBlock->end(); - BI != BIE; ++BI) { - if (auto *DVI = dyn_cast(&*BI)) { - LLVM_DEBUG(dbgs() << " Deciding: "); - LLVM_DEBUG(BI->print(dbgs())); + std::set PDPVRelated; + + // Work out whether a dbg.value intrinsic or an equivalent DPValue is a + // parameter to be preserved. + auto ExamineDbgValue = [](auto *DbgVal, auto &Container) { + LLVM_DEBUG(dbgs() << " Deciding: "); + LLVM_DEBUG(DbgVal->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + DILocalVariable *DILocVar = DbgVal->getVariable(); + if (DILocVar->isParameter()) { + LLVM_DEBUG(dbgs() << " Include (parameter): "); + LLVM_DEBUG(DbgVal->print(dbgs())); LLVM_DEBUG(dbgs() << "\n"); - DILocalVariable *DILocVar = DVI->getVariable(); - if (DILocVar->isParameter()) { - LLVM_DEBUG(dbgs() << " Include (parameter): "); - LLVM_DEBUG(BI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); - PDIRelated.insert(&*BI); - } else { - LLVM_DEBUG(dbgs() << " Delete (!parameter): "); - LLVM_DEBUG(BI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); - } - } else if (auto *DDI = dyn_cast(&*BI)) { - LLVM_DEBUG(dbgs() << " Deciding: "); - LLVM_DEBUG(BI->print(dbgs())); + Container.insert(DbgVal); + } else { + LLVM_DEBUG(dbgs() << " Delete (!parameter): "); + LLVM_DEBUG(DbgVal->print(dbgs())); LLVM_DEBUG(dbgs() << "\n"); - DILocalVariable *DILocVar = DDI->getVariable(); - if (DILocVar->isParameter()) { - LLVM_DEBUG(dbgs() << " Parameter: "); - LLVM_DEBUG(DILocVar->print(dbgs())); - AllocaInst *AI = dyn_cast_or_null(DDI->getAddress()); - if (AI) { - LLVM_DEBUG(dbgs() << " Processing alloca users: "); - LLVM_DEBUG(dbgs() << "\n"); - for (User *U : AI->users()) { - if (StoreInst *SI = dyn_cast(U)) { - if (Value *Arg = SI->getValueOperand()) { - if (isa(Arg)) { - LLVM_DEBUG(dbgs() << " Include: "); - LLVM_DEBUG(AI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); - PDIRelated.insert(AI); - LLVM_DEBUG(dbgs() << " Include (parameter): "); - LLVM_DEBUG(SI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); - PDIRelated.insert(SI); - LLVM_DEBUG(dbgs() << " Include: "); - LLVM_DEBUG(BI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); - PDIRelated.insert(&*BI); - } else { - LLVM_DEBUG(dbgs() << " Delete (!parameter): "); - LLVM_DEBUG(SI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); - } + } + }; + + auto ExamineDbgDeclare = [&PDIRelated](auto *DbgDecl, auto &Container) { + LLVM_DEBUG(dbgs() << " Deciding: "); + LLVM_DEBUG(DbgDecl->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + DILocalVariable *DILocVar = DbgDecl->getVariable(); + if (DILocVar->isParameter()) { + LLVM_DEBUG(dbgs() << " Parameter: "); + LLVM_DEBUG(DILocVar->print(dbgs())); + AllocaInst *AI = dyn_cast_or_null(DbgDecl->getAddress()); + if (AI) { + LLVM_DEBUG(dbgs() << " Processing alloca users: "); + LLVM_DEBUG(dbgs() << "\n"); + for (User *U : AI->users()) { + if (StoreInst *SI = dyn_cast(U)) { + if (Value *Arg = SI->getValueOperand()) { + if (isa(Arg)) { + LLVM_DEBUG(dbgs() << " Include: "); + LLVM_DEBUG(AI->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + PDIRelated.insert(AI); + LLVM_DEBUG(dbgs() << " Include (parameter): "); + LLVM_DEBUG(SI->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + PDIRelated.insert(SI); + LLVM_DEBUG(dbgs() << " Include: "); + LLVM_DEBUG(DbgDecl->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + Container.insert(DbgDecl); + } else { + LLVM_DEBUG(dbgs() << " Delete (!parameter): "); + LLVM_DEBUG(SI->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); } - } else { - LLVM_DEBUG(dbgs() << " Defer: "); - LLVM_DEBUG(U->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); } + } else { + LLVM_DEBUG(dbgs() << " Defer: "); + LLVM_DEBUG(U->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); } - } else { - LLVM_DEBUG(dbgs() << " Delete (alloca NULL): "); - LLVM_DEBUG(BI->print(dbgs())); - LLVM_DEBUG(dbgs() << "\n"); } } else { - LLVM_DEBUG(dbgs() << " Delete (!parameter): "); - LLVM_DEBUG(BI->print(dbgs())); + LLVM_DEBUG(dbgs() << " Delete (alloca NULL): "); + LLVM_DEBUG(DbgDecl->print(dbgs())); LLVM_DEBUG(dbgs() << "\n"); } + } else { + LLVM_DEBUG(dbgs() << " Delete (!parameter): "); + LLVM_DEBUG(DbgDecl->print(dbgs())); + LLVM_DEBUG(dbgs() << "\n"); + } + }; + + for (BasicBlock::iterator BI = GEntryBlock->begin(), BIE = GEntryBlock->end(); + BI != BIE; ++BI) { + // Examine DPValues as they happen "before" the instruction. Are they + // connected to parameters? + for (DPValue &DPV : BI->getDbgValueRange()) { + if (DPV.isDbgValue() || DPV.isDbgAssign()) { + ExamineDbgValue(&DPV, PDPVRelated); + } else { + assert(DPV.isDbgDeclare()); + ExamineDbgDeclare(&DPV, PDPVRelated); + } + } + + if (auto *DVI = dyn_cast(&*BI)) { + ExamineDbgValue(DVI, PDIRelated); + } else if (auto *DDI = dyn_cast(&*BI)) { + ExamineDbgDeclare(DDI, PDIRelated); } else if (BI->isTerminator() && &*BI == GEntryBlock->getTerminator()) { LLVM_DEBUG(dbgs() << " Will Include Terminator: "); LLVM_DEBUG(BI->print(dbgs())); @@ -630,17 +670,25 @@ void MergeFunctions::filterInstsUnrelatedToPDI( LLVM_DEBUG( dbgs() << " Report parameter debug info related/related instructions: {\n"); - for (Instruction &I : *GEntryBlock) { - if (PDIRelated.find(&I) == PDIRelated.end()) { + + auto IsPDIRelated = [](auto *Rec, auto &Container, auto &UnrelatedCont) { + if (Container.find(Rec) == Container.end()) { LLVM_DEBUG(dbgs() << " !PDIRelated: "); - LLVM_DEBUG(I.print(dbgs())); + LLVM_DEBUG(Rec->print(dbgs())); LLVM_DEBUG(dbgs() << "\n"); - PDIUnrelatedWL.push_back(&I); + UnrelatedCont.push_back(Rec); } else { LLVM_DEBUG(dbgs() << " PDIRelated: "); - LLVM_DEBUG(I.print(dbgs())); + LLVM_DEBUG(Rec->print(dbgs())); LLVM_DEBUG(dbgs() << "\n"); } + }; + + // Collect the set of unrelated instructions and debug records. + for (Instruction &I : *GEntryBlock) { + for (auto &DPV : I.getDbgValueRange()) + IsPDIRelated(&DPV, PDPVRelated, PDPVUnrelatedWL); + IsPDIRelated(&I, PDIRelated, PDIUnrelatedWL); } LLVM_DEBUG(dbgs() << " }\n"); } @@ -680,6 +728,7 @@ static void copyMetadataIfPresent(Function *From, Function *To, StringRef Key) { void MergeFunctions::writeThunk(Function *F, Function *G) { BasicBlock *GEntryBlock = nullptr; std::vector PDIUnrelatedWL; + std::vector PDPVUnrelatedWL; BasicBlock *BB = nullptr; Function *NewG = nullptr; if (MergeFunctionsPDI) { @@ -691,7 +740,7 @@ void MergeFunctions::writeThunk(Function *F, Function *G) { dbgs() << "writeThunk: (MergeFunctionsPDI) filter parameter related " "debug info for " << G->getName() << "() {\n"); - filterInstsUnrelatedToPDI(GEntryBlock, PDIUnrelatedWL); + filterInstsUnrelatedToPDI(GEntryBlock, PDIUnrelatedWL, PDPVUnrelatedWL); GEntryBlock->getTerminator()->eraseFromParent(); BB = GEntryBlock; } else { @@ -740,7 +789,7 @@ void MergeFunctions::writeThunk(Function *F, Function *G) { << G->getName() << "()\n"); } eraseTail(G); - eraseInstsUnrelatedToPDI(PDIUnrelatedWL); + eraseInstsUnrelatedToPDI(PDIUnrelatedWL, PDPVUnrelatedWL); LLVM_DEBUG( dbgs() << "} // End of parameter related debug info filtering for: " << G->getName() << "()\n"); diff --git a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp index 01aba47cdbffff01dadabf109e0980dad8cb7e0f..75f7de4290a742136dc48a503a5186909826b6a5 100644 --- a/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp +++ b/llvm/lib/Transforms/IPO/WholeProgramDevirt.cpp @@ -1066,17 +1066,10 @@ bool DevirtModule::tryFindVirtualCallTargets( GlobalObject::VCallVisibilityPublic) return false; - Constant *Ptr = getPointerAtOffset(TM.Bits->GV->getInitializer(), - TM.Offset + ByteOffset, M, TM.Bits->GV); - if (!Ptr) - return false; - - auto C = Ptr->stripPointerCasts(); - // Make sure this is a function or alias to a function. - auto Fn = dyn_cast(C); - auto A = dyn_cast(C); - if (!Fn && A) - Fn = dyn_cast(A->getAliasee()); + Function *Fn = nullptr; + Constant *C = nullptr; + std::tie(Fn, C) = + getFunctionAtVTableOffset(TM.Bits->GV, TM.Offset + ByteOffset, M); if (!Fn) return false; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 6ca4d6d673068ec2fa94a46aeb42e63c73fdd01f..aa3b9da924aa0b8cb50a91f30e4877a1d8583069 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -1419,6 +1419,44 @@ Value *InstCombinerImpl::foldLogicOfFCmps(FCmpInst *LHS, FCmpInst *RHS, } } + // Canonicalize the range check idiom: + // and (fcmp olt/ole/ult/ule x, C), (fcmp ogt/oge/ugt/uge x, -C) + // --> fabs(x) olt/ole/ult/ule C + // or (fcmp ogt/oge/ugt/uge x, C), (fcmp olt/ole/ult/ule x, -C) + // --> fabs(x) ogt/oge/ugt/uge C + // TODO: Generalize to handle a negated variable operand? + const APFloat *LHSC, *RHSC; + if (LHS0 == RHS0 && LHS->hasOneUse() && RHS->hasOneUse() && + FCmpInst::getSwappedPredicate(PredL) == PredR && + match(LHS1, m_APFloatAllowUndef(LHSC)) && + match(RHS1, m_APFloatAllowUndef(RHSC)) && + LHSC->bitwiseIsEqual(neg(*RHSC))) { + auto IsLessThanOrLessEqual = [](FCmpInst::Predicate Pred) { + switch (Pred) { + case FCmpInst::FCMP_OLT: + case FCmpInst::FCMP_OLE: + case FCmpInst::FCMP_ULT: + case FCmpInst::FCMP_ULE: + return true; + default: + return false; + } + }; + if (IsLessThanOrLessEqual(IsAnd ? PredR : PredL)) { + std::swap(LHSC, RHSC); + std::swap(PredL, PredR); + } + if (IsLessThanOrLessEqual(IsAnd ? PredL : PredR)) { + BuilderTy::FastMathFlagGuard Guard(Builder); + Builder.setFastMathFlags(LHS->getFastMathFlags() | + RHS->getFastMathFlags()); + + Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, LHS0); + return Builder.CreateFCmp(PredL, FAbs, + ConstantFP::get(LHS0->getType(), *LHSC)); + } + } + return nullptr; } @@ -2493,14 +2531,12 @@ Instruction *InstCombinerImpl::visitAnd(BinaryOperator &I) { // Assumes any IEEE-represented type has the sign bit in the high bit. // TODO: Unify with APInt matcher. This version allows undef unlike m_APInt Value *CastOp; - if (match(Op0, m_BitCast(m_Value(CastOp))) && + if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) && match(Op1, m_MaxSignedValue()) && !Builder.GetInsertBlock()->getParent()->hasFnAttribute( - Attribute::NoImplicitFloat)) { + Attribute::NoImplicitFloat)) { Type *EltTy = CastOp->getType()->getScalarType(); - if (EltTy->isFloatingPointTy() && EltTy->isIEEE() && - EltTy->getPrimitiveSizeInBits() == - I.getType()->getScalarType()->getPrimitiveSizeInBits()) { + if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) { Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp); return new BitCastInst(FAbs, I.getType()); } @@ -3574,14 +3610,6 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { if (match(Op1, m_c_Xor(m_c_And(m_Value(A), m_Specific(Op0)), m_Value(C)))) return BinaryOperator::CreateOr(Op0, C); - // ((B | C) & A) | B -> B | (A & C) - if (match(Op0, m_c_And(m_c_Or(m_Specific(Op1), m_Value(C)), m_Value(A)))) - return BinaryOperator::CreateOr(Op1, Builder.CreateAnd(A, C)); - - // B | ((B | C) & A) -> B | (A & C) - if (match(Op1, m_c_And(m_c_Or(m_Specific(Op0), m_Value(C)), m_Value(A)))) - return BinaryOperator::CreateOr(Op0, Builder.CreateAnd(A, C)); - if (Instruction *DeMorgan = matchDeMorgansLaws(I, *this)) return DeMorgan; @@ -3634,17 +3662,6 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { Value *Nand = Builder.CreateNot(Builder.CreateAnd(A, B), "nand"); return BinaryOperator::CreateOr(Nand, C); } - - // A | (~A ^ B) --> ~B | A - // B | (A ^ ~B) --> ~A | B - if (Op1->hasOneUse() && match(A, m_Not(m_Specific(Op0)))) { - Value *NotB = Builder.CreateNot(B, B->getName() + ".not"); - return BinaryOperator::CreateOr(NotB, Op0); - } - if (Op1->hasOneUse() && match(B, m_Not(m_Specific(Op0)))) { - Value *NotA = Builder.CreateNot(A, A->getName() + ".not"); - return BinaryOperator::CreateOr(NotA, Op0); - } } // A | ~(A | B) -> A | ~B @@ -3925,13 +3942,12 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { // This is generous interpretation of noimplicitfloat, this is not a true // floating-point operation. Value *CastOp; - if (match(Op0, m_BitCast(m_Value(CastOp))) && match(Op1, m_SignMask()) && + if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) && + match(Op1, m_SignMask()) && !Builder.GetInsertBlock()->getParent()->hasFnAttribute( Attribute::NoImplicitFloat)) { Type *EltTy = CastOp->getType()->getScalarType(); - if (EltTy->isFloatingPointTy() && EltTy->isIEEE() && - EltTy->getPrimitiveSizeInBits() == - I.getType()->getScalarType()->getPrimitiveSizeInBits()) { + if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) { Value *FAbs = Builder.CreateUnaryIntrinsic(Intrinsic::fabs, CastOp); Value *FNegFAbs = Builder.CreateFNeg(FAbs); return new BitCastInst(FNegFAbs, I.getType()); @@ -4701,13 +4717,12 @@ Instruction *InstCombinerImpl::visitXor(BinaryOperator &I) { // Assumes any IEEE-represented type has the sign bit in the high bit. // TODO: Unify with APInt matcher. This version allows undef unlike m_APInt Value *CastOp; - if (match(Op0, m_BitCast(m_Value(CastOp))) && match(Op1, m_SignMask()) && + if (match(Op0, m_ElementWiseBitCast(m_Value(CastOp))) && + match(Op1, m_SignMask()) && !Builder.GetInsertBlock()->getParent()->hasFnAttribute( Attribute::NoImplicitFloat)) { Type *EltTy = CastOp->getType()->getScalarType(); - if (EltTy->isFloatingPointTy() && EltTy->isIEEE() && - EltTy->getPrimitiveSizeInBits() == - I.getType()->getScalarType()->getPrimitiveSizeInBits()) { + if (EltTy->isFloatingPointTy() && EltTy->isIEEE()) { Value *FNeg = Builder.CreateFNeg(CastOp); return new BitCastInst(FNeg, I.getType()); } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp index 58f0763bb0c0cd63c5fd6ee89908e3dfbb260b02..ed47de287302ed1f26764822c46ab779b4bb4d99 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCasts.cpp @@ -182,9 +182,15 @@ Instruction *InstCombinerImpl::commonCastTransforms(CastInst &CI) { if (!Cmp || Cmp->getOperand(0)->getType() != Sel->getType() || (CI.getOpcode() == Instruction::Trunc && shouldChangeType(CI.getSrcTy(), CI.getType()))) { - if (Instruction *NV = FoldOpIntoSelect(CI, Sel)) { - replaceAllDbgUsesWith(*Sel, *NV, CI, DT); - return NV; + + // If it's a bitcast involving vectors, make sure it has the same number + // of elements on both sides. + if (CI.getOpcode() != Instruction::BitCast || + match(&CI, m_ElementWiseBitCast(m_Value()))) { + if (Instruction *NV = FoldOpIntoSelect(CI, Sel)) { + replaceAllDbgUsesWith(*Sel, *NV, CI, DT); + return NV; + } } } } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 380cb3504209d3155a6598f18ee39cf15195ab85..7aac13fd474b257b4f83c92183c0325ec9c79351 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -1334,7 +1334,6 @@ Instruction *InstCombinerImpl::foldICmpWithDominatingICmp(ICmpInst &Cmp) { // We already checked simple implication in InstSimplify, only handle complex // cases here. Value *X = Cmp.getOperand(0), *Y = Cmp.getOperand(1); - ICmpInst::Predicate DomPred; const APInt *C; if (!match(Y, m_APInt(C))) return nullptr; @@ -1342,10 +1341,8 @@ Instruction *InstCombinerImpl::foldICmpWithDominatingICmp(ICmpInst &Cmp) { CmpInst::Predicate Pred = Cmp.getPredicate(); ConstantRange CR = ConstantRange::makeExactICmpRegion(Pred, *C); - auto handleDomCond = [&](Value *DomCond, bool CondIsTrue) -> Instruction * { - const APInt *DomC; - if (!match(DomCond, m_ICmp(DomPred, m_Specific(X), m_APInt(DomC)))) - return nullptr; + auto handleDomCond = [&](ICmpInst::Predicate DomPred, + const APInt *DomC) -> Instruction * { // We have 2 compares of a variable with constants. Calculate the constant // ranges of those compares to see if we can transform the 2nd compare: // DomBB: @@ -1353,8 +1350,6 @@ Instruction *InstCombinerImpl::foldICmpWithDominatingICmp(ICmpInst &Cmp) { // br DomCond, CmpBB, FalseBB // CmpBB: // Cmp = icmp Pred X, C - if (!CondIsTrue) - DomPred = CmpInst::getInversePredicate(DomPred); ConstantRange DominatingCR = ConstantRange::makeExactICmpRegion(DomPred, *DomC); ConstantRange Intersection = DominatingCR.intersectWith(CR); @@ -1388,15 +1383,21 @@ Instruction *InstCombinerImpl::foldICmpWithDominatingICmp(ICmpInst &Cmp) { }; for (BranchInst *BI : DC.conditionsFor(X)) { - auto *Cond = BI->getCondition(); + ICmpInst::Predicate DomPred; + const APInt *DomC; + if (!match(BI->getCondition(), + m_ICmp(DomPred, m_Specific(X), m_APInt(DomC)))) + continue; + BasicBlockEdge Edge0(BI->getParent(), BI->getSuccessor(0)); if (DT.dominates(Edge0, Cmp.getParent())) { - if (auto *V = handleDomCond(Cond, true)) + if (auto *V = handleDomCond(DomPred, DomC)) return V; } else { BasicBlockEdge Edge1(BI->getParent(), BI->getSuccessor(1)); if (DT.dominates(Edge1, Cmp.getParent())) - if (auto *V = handleDomCond(Cond, false)) + if (auto *V = + handleDomCond(CmpInst::getInversePredicate(DomPred), DomC)) return V; } } @@ -1834,15 +1835,10 @@ Instruction *InstCombinerImpl::foldICmpAndConstConst(ICmpInst &Cmp, Value *V; if (!Cmp.getParent()->getParent()->hasFnAttribute( Attribute::NoImplicitFloat) && - Cmp.isEquality() && match(X, m_OneUse(m_BitCast(m_Value(V))))) { - Type *SrcType = V->getType(); - Type *DstType = X->getType(); - Type *FPType = SrcType->getScalarType(); - // Make sure the bitcast doesn't change between scalar and vector and - // doesn't change the number of vector elements. - if (SrcType->isVectorTy() == DstType->isVectorTy() && - SrcType->getScalarSizeInBits() == DstType->getScalarSizeInBits() && - FPType->isIEEELikeFPTy() && C1 == *C2) { + Cmp.isEquality() && + match(X, m_OneUse(m_ElementWiseBitCast(m_Value(V))))) { + Type *FPType = V->getType()->getScalarType(); + if (FPType->isIEEELikeFPTy() && C1 == *C2) { APInt ExponentMask = APFloat::getInf(FPType->getFltSemantics()).bitcastToAPInt(); if (C1 == ExponentMask) { @@ -7751,12 +7747,56 @@ Instruction *InstCombinerImpl::visitFCmpInst(FCmpInst &I) { if (match(Op1, m_AnyZeroFP()) && !match(Op1, m_PosZeroFP())) return replaceOperand(I, 1, ConstantFP::getZero(OpType)); + // Canonicalize: + // fcmp olt X, +inf -> fcmp one X, +inf + // fcmp ole X, +inf -> fcmp ord X, 0 + // fcmp ogt X, +inf -> false + // fcmp oge X, +inf -> fcmp oeq X, +inf + // fcmp ult X, +inf -> fcmp une X, +inf + // fcmp ule X, +inf -> true + // fcmp ugt X, +inf -> fcmp uno X, 0 + // fcmp uge X, +inf -> fcmp ueq X, +inf + // fcmp olt X, -inf -> false + // fcmp ole X, -inf -> fcmp oeq X, -inf + // fcmp ogt X, -inf -> fcmp one X, -inf + // fcmp oge X, -inf -> fcmp ord X, 0 + // fcmp ult X, -inf -> fcmp uno X, 0 + // fcmp ule X, -inf -> fcmp ueq X, -inf + // fcmp ugt X, -inf -> fcmp une X, -inf + // fcmp uge X, -inf -> true + const APFloat *C; + if (match(Op1, m_APFloat(C)) && C->isInfinity()) { + switch (C->isNegative() ? FCmpInst::getSwappedPredicate(Pred) : Pred) { + default: + break; + case FCmpInst::FCMP_ORD: + case FCmpInst::FCMP_UNO: + case FCmpInst::FCMP_TRUE: + case FCmpInst::FCMP_FALSE: + case FCmpInst::FCMP_OGT: + case FCmpInst::FCMP_ULE: + llvm_unreachable("Should be simplified by InstSimplify"); + case FCmpInst::FCMP_OLT: + return new FCmpInst(FCmpInst::FCMP_ONE, Op0, Op1, "", &I); + case FCmpInst::FCMP_OLE: + return new FCmpInst(FCmpInst::FCMP_ORD, Op0, ConstantFP::getZero(OpType), + "", &I); + case FCmpInst::FCMP_OGE: + return new FCmpInst(FCmpInst::FCMP_OEQ, Op0, Op1, "", &I); + case FCmpInst::FCMP_ULT: + return new FCmpInst(FCmpInst::FCMP_UNE, Op0, Op1, "", &I); + case FCmpInst::FCMP_UGT: + return new FCmpInst(FCmpInst::FCMP_UNO, Op0, ConstantFP::getZero(OpType), + "", &I); + case FCmpInst::FCMP_UGE: + return new FCmpInst(FCmpInst::FCMP_UEQ, Op0, Op1, "", &I); + } + } + // Ignore signbit of bitcasted int when comparing equality to FP 0.0: // fcmp oeq/une (bitcast X), 0.0 --> (and X, SignMaskC) ==/!= 0 if (match(Op1, m_PosZeroFP()) && - match(Op0, m_OneUse(m_BitCast(m_Value(X)))) && - X->getType()->isVectorTy() == OpType->isVectorTy() && - X->getType()->getScalarSizeInBits() == OpType->getScalarSizeInBits()) { + match(Op0, m_OneUse(m_ElementWiseBitCast(m_Value(X))))) { ICmpInst::Predicate IntPred = ICmpInst::BAD_ICMP_PREDICATE; if (Pred == FCmpInst::FCMP_OEQ) IntPred = ICmpInst::ICMP_EQ; @@ -7864,7 +7904,6 @@ Instruction *InstCombinerImpl::visitFCmpInst(FCmpInst &I) { // TODO: Simplify if the copysign constant is 0.0 or NaN. // TODO: Handle non-zero compare constants. // TODO: Handle other predicates. - const APFloat *C; if (match(Op0, m_OneUse(m_Intrinsic(m_APFloat(C), m_Value(X)))) && match(Op1, m_AnyZeroFP()) && !C->isZero() && !C->isNaN()) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 6c3adf00c189a8edd2dc5794b8fa0918160becc2..f9cee9dfcfadaedc15ae39b21f2719f4c7fc501b 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -1598,9 +1598,11 @@ Instruction *InstCombinerImpl::foldFDivConstantDivisor(BinaryOperator &I) { return BinaryOperator::CreateFDivFMF(X, NegC, &I); // nnan X / +0.0 -> copysign(inf, X) - if (I.hasNoNaNs() && match(I.getOperand(1), m_Zero())) { + // nnan nsz X / -0.0 -> copysign(inf, X) + if (I.hasNoNaNs() && + (match(I.getOperand(1), m_PosZeroFP()) || + (I.hasNoSignedZeros() && match(I.getOperand(1), m_AnyZeroFP())))) { IRBuilder<> B(&I); - // TODO: nnan nsz X / -0.0 -> copysign(inf, X) CallInst *CopySign = B.CreateIntrinsic( Intrinsic::copysign, {C->getType()}, {ConstantFP::getInfinity(I.getType()), I.getOperand(0)}, &I); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 2756f81ed9e6200705bf2eaad4ddad2d074da7df..527037881edb19906afbec3eecfcfa34e14adc4c 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -2365,9 +2365,6 @@ static Instruction *foldSelectToCopysign(SelectInst &Sel, Value *FVal = Sel.getFalseValue(); Type *SelType = Sel.getType(); - if (ICmpInst::makeCmpResultType(TVal->getType()) != Cond->getType()) - return nullptr; - // Match select ?, TC, FC where the constants are equal but negated. // TODO: Generalize to handle a negated variable operand? const APFloat *TC, *FC; @@ -2382,7 +2379,8 @@ static Instruction *foldSelectToCopysign(SelectInst &Sel, const APInt *C; bool IsTrueIfSignSet; ICmpInst::Predicate Pred; - if (!match(Cond, m_OneUse(m_ICmp(Pred, m_BitCast(m_Value(X)), m_APInt(C)))) || + if (!match(Cond, m_OneUse(m_ICmp(Pred, m_ElementWiseBitCast(m_Value(X)), + m_APInt(C)))) || !InstCombiner::isSignBitCheck(Pred, *C, IsTrueIfSignSet) || X->getType() != SelType) return nullptr; @@ -2770,8 +2768,6 @@ static Instruction *foldSelectWithFCmpToFabs(SelectInst &SI, // Match select with (icmp slt (bitcast X to int), 0) // or (icmp sgt (bitcast X to int), -1) - if (ICmpInst::makeCmpResultType(SI.getType()) != CondVal->getType()) - return ChangedFMF ? &SI : nullptr; for (bool Swap : {false, true}) { Value *TrueVal = SI.getTrueValue(); @@ -2783,7 +2779,8 @@ static Instruction *foldSelectWithFCmpToFabs(SelectInst &SI, CmpInst::Predicate Pred; const APInt *C; bool TrueIfSigned; - if (!match(CondVal, m_ICmp(Pred, m_BitCast(m_Specific(X)), m_APInt(C))) || + if (!match(CondVal, + m_ICmp(Pred, m_ElementWiseBitCast(m_Specific(X)), m_APInt(C))) || !IC.isSignBitCheck(Pred, *C, TrueIfSigned)) continue; if (!match(TrueVal, m_FNeg(m_Specific(X)))) diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index dd168917f4dc9cb74a20c77478c23ebca42e8726..9e8bcbc8e156e2737a2073fb5dac6351b07b37bf 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -1474,21 +1474,6 @@ Instruction *InstCombinerImpl::FoldOpIntoSelect(Instruction &Op, SelectInst *SI, if (SI->getType()->isIntOrIntVectorTy(1)) return nullptr; - // If it's a bitcast involving vectors, make sure it has the same number of - // elements on both sides. - if (auto *BC = dyn_cast(&Op)) { - VectorType *DestTy = dyn_cast(BC->getDestTy()); - VectorType *SrcTy = dyn_cast(BC->getSrcTy()); - - // Verify that either both or neither are vectors. - if ((SrcTy == nullptr) != (DestTy == nullptr)) - return nullptr; - - // If vectors, verify that they have the same number of elements. - if (SrcTy && SrcTy->getElementCount() != DestTy->getElementCount()) - return nullptr; - } - // Test if a FCmpInst instruction is used exclusively by a select as // part of a minimum or maximum operation. If so, refrain from doing // any other folding. This helps out other analyses which understand @@ -2375,6 +2360,33 @@ Value *InstCombiner::getFreelyInvertedImpl(Value *V, bool WillInvertAllUses, } } + if (PHINode *PN = dyn_cast(V)) { + SmallVector, 8> IncomingValues; + for (Use &U : PN->operands()) { + BasicBlock *IncomingBlock = PN->getIncomingBlock(U); + Value *NewIncomingVal = getFreelyInvertedImpl( + U.get(), /*WillInvertAllUses=*/false, + /*Builder=*/nullptr, DoesConsume, MaxAnalysisRecursionDepth - 1); + if (NewIncomingVal == nullptr) + return nullptr; + // Make sure that we can safely erase the original PHI node. + if (NewIncomingVal == V) + return nullptr; + if (Builder != nullptr) + IncomingValues.emplace_back(NewIncomingVal, IncomingBlock); + } + if (Builder != nullptr) { + IRBuilderBase::InsertPointGuard Guard(*Builder); + Builder->SetInsertPoint(PN); + PHINode *NewPN = + Builder->CreatePHI(PN->getType(), PN->getNumIncomingValues()); + for (auto [Val, Pred] : IncomingValues) + NewPN->addIncoming(Val, Pred); + return NewPN; + } + return NonNull; + } + return nullptr; } @@ -3459,6 +3471,17 @@ InstCombinerImpl::foldExtractOfOverflowIntrinsic(ExtractValueInst &EV) { WO->getLHS()->getType()->isIntOrIntVectorTy(1)) return BinaryOperator::CreateAnd(WO->getLHS(), WO->getRHS()); + // extractvalue (umul_with_overflow X, X), 1 -> X u> 2^(N/2)-1 + if (OvID == Intrinsic::umul_with_overflow && WO->getLHS() == WO->getRHS()) { + unsigned BitWidth = WO->getLHS()->getType()->getScalarSizeInBits(); + // Only handle even bitwidths for performance reasons. + if (BitWidth % 2 == 0) + return new ICmpInst( + ICmpInst::ICMP_UGT, WO->getLHS(), + ConstantInt::get(WO->getLHS()->getType(), + APInt::getLowBitsSet(BitWidth, BitWidth / 2))); + } + // If only the overflow result is used, and the right hand side is a // constant (or constant splat), we can remove the intrinsic by directly // checking for overflow. diff --git a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp index 97cf5ebe3ca064711304fa42cdbc699ce55f5ef9..db05c63f388fb1fcfd1e476a601724e670b4d632 100644 --- a/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp +++ b/llvm/lib/Transforms/Scalar/ConstraintElimination.cpp @@ -1755,7 +1755,10 @@ static bool eliminateConstraints(Function &F, DominatorTree &DT, LoopInfo &LI, if (!CB.isConditionFact()) { Value *X; if (match(CB.Inst, m_Intrinsic(m_Value(X)))) { - // TODO: Add CB.Inst >= 0 fact. + // If is_int_min_poison is true then we may assume llvm.abs >= 0. + if (cast(CB.Inst->getOperand(1))->isOne()) + AddFact(CmpInst::ICMP_SGE, CB.Inst, + ConstantInt::get(CB.Inst->getType(), 0)); AddFact(CmpInst::ICMP_SGE, CB.Inst, X); continue; } diff --git a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp index 7cfeb019af97232ec405ec83c8e7a2fb733cad71..75fb8765061edf7fb17f1f3f7b29079a753154f2 100644 --- a/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp +++ b/llvm/lib/Transforms/Scalar/LoopUnrollPass.cpp @@ -173,6 +173,10 @@ static cl::opt cl::desc("Default threshold (max size of unrolled " "loop), used in all but O3 optimizations")); +static cl::opt PragmaUnrollFullMaxIterations( + "pragma-unroll-full-max-iterations", cl::init(1'000'000), cl::Hidden, + cl::desc("Maximum allowed iterations to unroll under pragma unroll full.")); + /// A magic value for use with the Threshold parameter to indicate /// that the loop unroll should be performed regardless of how much /// code expansion would result. @@ -446,7 +450,15 @@ static std::optional analyzeLoopUnrollCost( // First accumulate the cost of this instruction. if (!Cost.IsFree) { - UnrolledCost += TTI.getInstructionCost(I, CostKind); + // Consider simplified operands in instruction cost. + SmallVector Operands; + transform(I->operands(), std::back_inserter(Operands), + [&](Value *Op) { + if (auto Res = SimplifiedValues.lookup(Op)) + return Res; + return Op; + }); + UnrolledCost += TTI.getInstructionCost(I, Operands, CostKind); LLVM_DEBUG(dbgs() << "Adding cost of instruction (iteration " << Iteration << "): "); LLVM_DEBUG(I->dump()); @@ -776,8 +788,17 @@ shouldPragmaUnroll(Loop *L, const PragmaInfo &PInfo, return PInfo.PragmaCount; } - if (PInfo.PragmaFullUnroll && TripCount != 0) + if (PInfo.PragmaFullUnroll && TripCount != 0) { + // Certain cases with UBSAN can cause trip count to be calculated as + // INT_MAX, Block full unrolling at a reasonable limit so that the compiler + // doesn't hang trying to unroll the loop. See PR77842 + if (TripCount > PragmaUnrollFullMaxIterations) { + LLVM_DEBUG(dbgs() << "Won't unroll; trip count is too large\n"); + return std::nullopt; + } + return TripCount; + } if (PInfo.PragmaEnableUnroll && !TripCount && MaxTripCount && MaxTripCount <= UP.MaxUpperBound) @@ -1282,7 +1303,7 @@ tryToUnrollLoop(Loop *L, DominatorTree &DT, LoopInfo *LI, ScalarEvolution &SE, } // Do not attempt partial/runtime unrolling in FullLoopUnrolling - if (OnlyFullUnroll && !(UP.Count >= MaxTripCount)) { + if (OnlyFullUnroll && (UP.Count < TripCount || UP.Count < MaxTripCount)) { LLVM_DEBUG( dbgs() << "Not attempting partial/runtime unroll in FullLoopUnroll.\n"); return LoopUnrollResult::Unmodified; diff --git a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp index 72b9db1e73d73dc64dd888b052594359ba38eabf..b528762b545659e1c0504e5d8e0977aa77922230 100644 --- a/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp +++ b/llvm/lib/Transforms/Scalar/LowerMatrixIntrinsics.cpp @@ -1332,8 +1332,8 @@ public: if (!IsIntVec && !FMF.allowReassoc()) return; - auto CanBeFlattened = [this](Value *Op) { - if (match(Op, m_BinOp()) && ShapeMap.find(Op) != ShapeMap.end()) + auto CanBeFlattened = [](Value *Op) { + if (match(Op, m_BinOp())) return true; return match( Op, m_OneUse(m_CombineOr( @@ -1346,6 +1346,9 @@ public: // the returned cost is < 0, the argument is cheaper to use in the // dot-product lowering. auto GetCostForArg = [this, &CanBeFlattened](Value *Op, unsigned N) { + if (ShapeMap.find(Op) == ShapeMap.end()) + return InstructionCost::getInvalid(); + if (!isa(Op)) return InstructionCost(0); @@ -1356,7 +1359,7 @@ public: InstructionCost EmbedCost(0); // Roughly estimate the cost for embedding the columns into a vector. for (unsigned I = 1; I < N; ++I) - EmbedCost -= + EmbedCost += TTI.getShuffleCost(TTI::SK_Splice, FixedVectorType::get(EltTy, 1), std::nullopt, TTI::TCK_RecipThroughput); return EmbedCost; @@ -1378,7 +1381,7 @@ public: // vector. InstructionCost EmbedCost(0); for (unsigned I = 1; I < N; ++I) - EmbedCost += + EmbedCost -= TTI.getShuffleCost(TTI::SK_Splice, FixedVectorType::get(EltTy, 1), std::nullopt, TTI::TCK_RecipThroughput); return EmbedCost; @@ -1391,7 +1394,29 @@ public: return TTI.getMemoryOpCost(Instruction::Load, VecTy, Align(1), 0) - N * TTI.getMemoryOpCost(Instruction::Load, EltTy, Align(1), 0); }; - auto LHSCost = GetCostForArg(LHS, LShape.NumColumns); + + // Iterate over LHS and operations feeding LHS and check if it is profitable + // to flatten the visited ops. For each op, we compute the difference + // between the flattened and matrix versions. + SmallPtrSet Seen; + SmallVector WorkList; + SmallVector ToFlatten; + WorkList.push_back(LHS); + InstructionCost LHSCost(0); + while (!WorkList.empty()) { + Value *Op = WorkList.pop_back_val(); + if (!Seen.insert(Op).second) + continue; + + InstructionCost OpCost = GetCostForArg(Op, LShape.NumColumns); + if (OpCost + LHSCost >= LHSCost) + continue; + + LHSCost += OpCost; + ToFlatten.push_back(Op); + if (auto *I = dyn_cast(Op)) + WorkList.append(I->op_begin(), I->op_end()); + } // We compare the costs of a vector.reduce.add to sequential add. int AddOpCode = IsIntVec ? Instruction::Add : Instruction::FAdd; @@ -1412,16 +1437,16 @@ public: FusedInsts.insert(MatMul); IRBuilder<> Builder(MatMul); auto FlattenArg = [&Builder, &FusedInsts, &CanBeFlattened, - this](Value *Op) -> Value * { + this](Value *Op) { // Matmul must be the only user of loads because we don't use LowerLoad // for row vectors (LowerLoad results in scalar loads and shufflevectors // instead of single vector load). if (!CanBeFlattened(Op)) - return Op; + return; if (match(Op, m_BinOp()) && ShapeMap.find(Op) != ShapeMap.end()) { ShapeMap[Op] = ShapeMap[Op].t(); - return Op; + return; } FusedInsts.insert(cast(Op)); @@ -1432,16 +1457,19 @@ public: auto *NewLoad = Builder.CreateLoad(Op->getType(), Arg); Op->replaceAllUsesWith(NewLoad); cast(Op)->eraseFromParent(); - return NewLoad; + return; } else if (match(Op, m_Intrinsic( m_Value(Arg)))) { ToRemove.push_back(cast(Op)); - return Arg; + Op->replaceAllUsesWith(Arg); + return; } - - return Op; }; - LHS = FlattenArg(LHS); + + for (auto *V : ToFlatten) + FlattenArg(V); + + LHS = MatMul->getArgOperand(0); // Insert mul/fmul and llvm.vector.reduce.fadd Value *Mul = diff --git a/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp b/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp index 7a5318d4404ca4b87f45f641fcffcab51541e0f7..87b0f50860e1b5dfd0616423cd08dc6e17123820 100644 --- a/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp +++ b/llvm/lib/Transforms/Scalar/SpeculativeExecution.cpp @@ -263,37 +263,39 @@ static InstructionCost ComputeSpeculationCost(const Instruction *I, bool SpeculativeExecutionPass::considerHoistingFromTo( BasicBlock &FromBlock, BasicBlock &ToBlock) { SmallPtrSet NotHoisted; - const auto AllPrecedingUsesFromBlockHoisted = [&NotHoisted](const User *U) { - // Debug variable has special operand to check it's not hoisted. - if (const auto *DVI = dyn_cast(U)) { - return all_of(DVI->location_ops(), [&NotHoisted](Value *V) { - if (const auto *I = dyn_cast_or_null(V)) { - if (!NotHoisted.contains(I)) - return true; - } - return false; - }); - } - - // Usially debug label intrinsic corresponds to label in LLVM IR. In these - // cases we should not move it here. - // TODO: Possible special processing needed to detect it is related to a - // hoisted instruction. - if (isa(U)) - return false; - - for (const Value *V : U->operand_values()) { - if (const Instruction *I = dyn_cast(V)) { + SmallDenseMap> DPValuesToHoist; + auto HasNoUnhoistedInstr = [&NotHoisted](auto Values) { + for (const Value *V : Values) { + if (const auto *I = dyn_cast_or_null(V)) if (NotHoisted.contains(I)) return false; - } } return true; }; + auto AllPrecedingUsesFromBlockHoisted = + [&HasNoUnhoistedInstr](const User *U) { + // Debug variable has special operand to check it's not hoisted. + if (const auto *DVI = dyn_cast(U)) + return HasNoUnhoistedInstr(DVI->location_ops()); + + // Usially debug label intrinsic corresponds to label in LLVM IR. In + // these cases we should not move it here. + // TODO: Possible special processing needed to detect it is related to a + // hoisted instruction. + if (isa(U)) + return false; + + return HasNoUnhoistedInstr(U->operand_values()); + }; InstructionCost TotalSpeculationCost = 0; unsigned NotHoistedInstCount = 0; for (const auto &I : FromBlock) { + // Make note of any DPValues that need hoisting. + for (DPValue &DPV : I.getDbgValueRange()) + if (HasNoUnhoistedInstr(DPV.location_ops())) + DPValuesToHoist[DPV.getInstruction()].push_back(&DPV); + const InstructionCost Cost = ComputeSpeculationCost(&I, *TTI); if (Cost.isValid() && isSafeToSpeculativelyExecute(&I) && AllPrecedingUsesFromBlockHoisted(&I)) { @@ -311,12 +313,22 @@ bool SpeculativeExecutionPass::considerHoistingFromTo( } for (auto I = FromBlock.begin(); I != FromBlock.end();) { + // If any DPValues attached to this instruction should be hoisted, hoist + // them now - they will end up attached to either the next hoisted + // instruction or the ToBlock terminator. + if (DPValuesToHoist.contains(&*I)) { + for (auto *DPV : DPValuesToHoist[&*I]) { + DPV->removeFromParent(); + ToBlock.insertDPValueBefore(DPV, + ToBlock.getTerminator()->getIterator()); + } + } // We have to increment I before moving Current as moving Current // changes the list that I is iterating through. auto Current = I; ++I; if (!NotHoisted.count(&*Current)) { - Current->moveBeforePreserving(ToBlock.getTerminator()); + Current->moveBefore(ToBlock.getTerminator()); } } return true; diff --git a/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp b/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp index e42cdab64446e2ba3055d8e2ecfc25c5e8e0811a..4e84927f1cfc90353cfa2ed6ea5708f46b673a9b 100644 --- a/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp +++ b/llvm/lib/Transforms/Utils/CallPromotionUtils.cpp @@ -597,16 +597,13 @@ bool llvm::tryPromoteCall(CallBase &CB) { // Not in the form of a global constant variable with an initializer. return false; - Constant *VTableGVInitializer = GV->getInitializer(); APInt VTableGVOffset = VTableOffsetGVBase + VTableOffset; if (!(VTableGVOffset.getActiveBits() <= 64)) return false; // Out of range. - Constant *Ptr = getPointerAtOffset(VTableGVInitializer, - VTableGVOffset.getZExtValue(), - *M); - if (!Ptr) - return false; // No constant (function) pointer found. - Function *DirectCallee = dyn_cast(Ptr->stripPointerCasts()); + + Function *DirectCallee = nullptr; + std::tie(DirectCallee, std::ignore) = + getFunctionAtVTableOffset(GV, VTableGVOffset.getZExtValue(), *M); if (!DirectCallee) return false; // No function pointer found. diff --git a/llvm/lib/Transforms/Utils/CodeExtractor.cpp b/llvm/lib/Transforms/Utils/CodeExtractor.cpp index 278111883459b37bfb246a190f9b9e9753bcb785..57d3926515993f0964a0de3915ffb712cbba9ff6 100644 --- a/llvm/lib/Transforms/Utils/CodeExtractor.cpp +++ b/llvm/lib/Transforms/Utils/CodeExtractor.cpp @@ -1769,6 +1769,10 @@ CodeExtractor::extractCodeRegion(const CodeExtractorAnalysisCache &CEAC, return any_of(*BB, [&BranchI](const Instruction &I) { if (!I.getDebugLoc()) return false; + // Don't use source locations attached to debug-intrinsics: they could + // be from completely unrelated scopes. + if (isa(I)) + return false; BranchI->setDebugLoc(I.getDebugLoc()); return true; }); diff --git a/llvm/lib/Transforms/Utils/Debugify.cpp b/llvm/lib/Transforms/Utils/Debugify.cpp index d0cc603426d2a77c4baf543319450768f6543a38..200bad22148f069cecf90118abdad820b6d20f64 100644 --- a/llvm/lib/Transforms/Utils/Debugify.cpp +++ b/llvm/lib/Transforms/Utils/Debugify.cpp @@ -87,6 +87,10 @@ bool llvm::applyDebugifyMetadata( return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + DIBuilder DIB(M); LLVMContext &Ctx = M.getContext(); auto *Int32Ty = Type::getInt32Ty(Ctx); @@ -210,6 +214,9 @@ bool llvm::applyDebugifyMetadata( if (!M.getModuleFlag(DIVersionKey)) M.addModuleFlag(Module::Warning, DIVersionKey, DEBUG_METADATA_VERSION); + if (NewDebugMode) + M.convertToNewDbgValues(); + return true; } @@ -304,6 +311,10 @@ bool llvm::collectDebugInfoMetadata(Module &M, return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + uint64_t FunctionsCnt = DebugInfoBeforePass.DIFunctions.size(); // Visit each instruction. for (Function &F : Functions) { @@ -368,6 +379,9 @@ bool llvm::collectDebugInfoMetadata(Module &M, } } + if (NewDebugMode) + M.convertToNewDbgValues(); + return true; } @@ -547,6 +561,10 @@ bool llvm::checkDebugInfoMetadata(Module &M, return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + // Map the debug info holding DIs after a pass. DebugInfoPerPass DebugInfoAfterPass; @@ -657,6 +675,9 @@ bool llvm::checkDebugInfoMetadata(Module &M, // the debugging information from the previous pass. DebugInfoBeforePass = DebugInfoAfterPass; + if (NewDebugMode) + M.convertToNewDbgValues(); + LLVM_DEBUG(dbgs() << "\n\n"); return Result; } @@ -714,6 +735,10 @@ bool checkDebugifyMetadata(Module &M, return false; } + bool NewDebugMode = M.IsNewDbgInfoFormat; + if (NewDebugMode) + M.convertFromNewDbgValues(); + auto getDebugifyOperand = [&](unsigned Idx) -> unsigned { return mdconst::extract(NMD->getOperand(Idx)->getOperand(0)) ->getZExtValue(); @@ -791,24 +816,22 @@ bool checkDebugifyMetadata(Module &M, dbg() << ": " << (HasErrors ? "FAIL" : "PASS") << '\n'; // Strip debugify metadata if required. + bool Ret = false; if (Strip) - return stripDebugifyMetadata(M); + Ret = stripDebugifyMetadata(M); + + if (NewDebugMode) + M.convertToNewDbgValues(); - return false; + return Ret; } /// ModulePass for attaching synthetic debug info to everything, used with the /// legacy module pass manager. struct DebugifyModulePass : public ModulePass { bool runOnModule(Module &M) override { - bool NewDebugMode = M.IsNewDbgInfoFormat; - if (NewDebugMode) - M.convertFromNewDbgValues(); - - bool Result = applyDebugify(M, Mode, DebugInfoBeforePass, NameOfWrappedPass); - - if (NewDebugMode) - M.convertToNewDbgValues(); + bool Result = + applyDebugify(M, Mode, DebugInfoBeforePass, NameOfWrappedPass); return Result; } @@ -834,14 +857,8 @@ private: /// single function, used with the legacy module pass manager. struct DebugifyFunctionPass : public FunctionPass { bool runOnFunction(Function &F) override { - bool NewDebugMode = F.IsNewDbgInfoFormat; - if (NewDebugMode) - F.convertFromNewDbgValues(); - - bool Result = applyDebugify(F, Mode, DebugInfoBeforePass, NameOfWrappedPass); - - if (NewDebugMode) - F.convertToNewDbgValues(); + bool Result = + applyDebugify(F, Mode, DebugInfoBeforePass, NameOfWrappedPass); return Result; } @@ -868,10 +885,6 @@ private: /// legacy module pass manager. struct CheckDebugifyModulePass : public ModulePass { bool runOnModule(Module &M) override { - bool NewDebugMode = M.IsNewDbgInfoFormat; - if (NewDebugMode) - M.convertFromNewDbgValues(); - bool Result; if (Mode == DebugifyMode::SyntheticDebugInfo) Result = checkDebugifyMetadata(M, M.functions(), NameOfWrappedPass, @@ -882,9 +895,6 @@ struct CheckDebugifyModulePass : public ModulePass { "CheckModuleDebugify (original debuginfo)", NameOfWrappedPass, OrigDIVerifyBugsReportFilePath); - if (NewDebugMode) - M.convertToNewDbgValues(); - return Result; } @@ -918,10 +928,6 @@ private: /// with the legacy module pass manager. struct CheckDebugifyFunctionPass : public FunctionPass { bool runOnFunction(Function &F) override { - bool NewDebugMode = F.IsNewDbgInfoFormat; - if (NewDebugMode) - F.convertFromNewDbgValues(); - Module &M = *F.getParent(); auto FuncIt = F.getIterator(); bool Result; @@ -935,8 +941,6 @@ struct CheckDebugifyFunctionPass : public FunctionPass { "CheckFunctionDebugify (original debuginfo)", NameOfWrappedPass, OrigDIVerifyBugsReportFilePath); - if (NewDebugMode) - F.convertToNewDbgValues(); return Result; } @@ -1009,10 +1013,6 @@ createDebugifyFunctionPass(enum DebugifyMode Mode, } PreservedAnalyses NewPMDebugifyPass::run(Module &M, ModuleAnalysisManager &) { - bool NewDebugMode = M.IsNewDbgInfoFormat; - if (NewDebugMode) - M.convertFromNewDbgValues(); - if (Mode == DebugifyMode::SyntheticDebugInfo) applyDebugifyMetadata(M, M.functions(), "ModuleDebugify: ", /*ApplyToMF*/ nullptr); @@ -1021,9 +1021,6 @@ PreservedAnalyses NewPMDebugifyPass::run(Module &M, ModuleAnalysisManager &) { "ModuleDebugify (original debuginfo)", NameOfWrappedPass); - if (NewDebugMode) - M.convertToNewDbgValues(); - PreservedAnalyses PA; PA.preserveSet(); return PA; diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 459e3d98059283340c027af5b98a84836f3b75d0..e4aa25f7ac6ad3129416756a88d0760d075467da 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -2044,7 +2044,7 @@ static void insertDPValuesForPHIs(BasicBlock *BB, auto InsertionPt = Parent->getFirstInsertionPt(); assert(InsertionPt != Parent->end() && "Ill-formed basic block"); - InsertionPt->DbgMarker->insertDPValue(NewDbgII, true); + Parent->insertDPValueBefore(NewDbgII, InsertionPt); } } diff --git a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp index 504f4430dc2ca66866e076e3dc7d956be090676d..ec59a0773020374e6246a7d707113ab7d523b21e 100644 --- a/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopRotationUtils.cpp @@ -596,7 +596,10 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { // on the next instruction, here labelled xyzzy, before we hoist %foo. // Later, we only only clone DPValues from that position (xyzzy) onwards, // which avoids cloning DPValue "blah" multiple times. - std::optional NextDbgInst = std::nullopt; + // (Stored as a range because it gives us a natural way of testing whether + // there were DPValues on the next instruction before we hoisted things). + iterator_range NextDbgInsts = + (I != E) ? I->getDbgValueRange() : DPMarker::getEmptyDPValueRange(); while (I != E) { Instruction *Inst = &*I++; @@ -611,9 +614,10 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { !Inst->mayWriteToMemory() && !Inst->isTerminator() && !isa(Inst) && !isa(Inst)) { - if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat) { + if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat && + !NextDbgInsts.empty()) { auto DbgValueRange = - LoopEntryBranch->cloneDebugInfoFrom(Inst, NextDbgInst); + LoopEntryBranch->cloneDebugInfoFrom(Inst, NextDbgInsts.begin()); RemapDPValueRange(M, DbgValueRange, ValueMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); // Erase anything we've seen before. @@ -622,7 +626,8 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { DPV.eraseFromParent(); } - NextDbgInst = I->getDbgValueRange().begin(); + NextDbgInsts = I->getDbgValueRange(); + Inst->moveBefore(LoopEntryBranch); ++NumInstrsHoisted; @@ -635,11 +640,12 @@ bool LoopRotate::rotateLoop(Loop *L, bool SimplifiedLatch) { ++NumInstrsDuplicated; - if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat) { - auto Range = C->cloneDebugInfoFrom(Inst, NextDbgInst); + if (LoopEntryBranch->getParent()->IsNewDbgInfoFormat && + !NextDbgInsts.empty()) { + auto Range = C->cloneDebugInfoFrom(Inst, NextDbgInsts.begin()); RemapDPValueRange(M, Range, ValueMap, RF_NoModuleLevelChanges | RF_IgnoreMissingLocals); - NextDbgInst = std::nullopt; + NextDbgInsts = DPMarker::getEmptyDPValueRange(); // Erase anything we've seen before. for (DPValue &DPV : make_early_inc_range(Range)) if (DbgIntrinsics.count(makeHash(&DPV))) diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp index 58dbac0e85fb04bdec60ddc4a0abbab7121f6775..3a28909473d95f67f837be496a0d09f6ad7109a2 100644 --- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp +++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp @@ -795,7 +795,8 @@ Value *SCEVExpander::expandIVInc(PHINode *PN, Value *StepV, const Loop *L, Value *IncV; // If the PHI is a pointer, use a GEP, otherwise use an add or sub. if (PN->getType()->isPointerTy()) { - IncV = expandAddToGEP(SE.getSCEV(StepV), PN); + // TODO: Change name to IVName.iv.next. + IncV = Builder.CreatePtrAdd(PN, StepV, "scevgep"); } else { IncV = useSubtract ? Builder.CreateSub(PN, StepV, Twine(IVName) + ".iv.next") : diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index f5b398cae04ed63c12d3b6f10b23180d17edd7bf..7424fe31945dc7021fcc62cc21862f10129cd812 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -1842,11 +1842,6 @@ bool SimplifyCFGOpt::hoistSuccIdenticalTerminatorToSwitchOrIf( Locs.push_back(I1->getDebugLoc()); for (auto *OtherSuccTI : OtherSuccTIs) Locs.push_back(OtherSuccTI->getDebugLoc()); - // Also clone DPValues from the existing terminator, and all others (to - // duplicate existing hoisting behaviour). - NT->cloneDebugInfoFrom(I1); - for (Instruction *OtherSuccTI : OtherSuccTIs) - NT->cloneDebugInfoFrom(OtherSuccTI); NT->setDebugLoc(DILocation::getMergedLocations(Locs)); // PHIs created below will adopt NT's merged DebugLoc. diff --git a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp index 9e9d09757e18331aded76b082dbc73789df23960..26a34aa99e1b8748650f641e76601ca067c09468 100644 --- a/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyLibCalls.cpp @@ -2545,6 +2545,70 @@ Value *LibCallSimplifier::optimizeLog(CallInst *Log, IRBuilderBase &B) { return Ret; } +// sqrt(exp(X)) -> exp(X * 0.5) +Value *LibCallSimplifier::mergeSqrtToExp(CallInst *CI, IRBuilderBase &B) { + if (!CI->hasAllowReassoc()) + return nullptr; + + Function *SqrtFn = CI->getCalledFunction(); + CallInst *Arg = dyn_cast(CI->getArgOperand(0)); + if (!Arg || !Arg->hasAllowReassoc() || !Arg->hasOneUse()) + return nullptr; + Intrinsic::ID ArgID = Arg->getIntrinsicID(); + LibFunc ArgLb = NotLibFunc; + TLI->getLibFunc(*Arg, ArgLb); + + LibFunc SqrtLb, ExpLb, Exp2Lb, Exp10Lb; + + if (TLI->getLibFunc(SqrtFn->getName(), SqrtLb)) + switch (SqrtLb) { + case LibFunc_sqrtf: + ExpLb = LibFunc_expf; + Exp2Lb = LibFunc_exp2f; + Exp10Lb = LibFunc_exp10f; + break; + case LibFunc_sqrt: + ExpLb = LibFunc_exp; + Exp2Lb = LibFunc_exp2; + Exp10Lb = LibFunc_exp10; + break; + case LibFunc_sqrtl: + ExpLb = LibFunc_expl; + Exp2Lb = LibFunc_exp2l; + Exp10Lb = LibFunc_exp10l; + break; + default: + return nullptr; + } + else if (SqrtFn->getIntrinsicID() == Intrinsic::sqrt) { + if (CI->getType()->getScalarType()->isFloatTy()) { + ExpLb = LibFunc_expf; + Exp2Lb = LibFunc_exp2f; + Exp10Lb = LibFunc_exp10f; + } else if (CI->getType()->getScalarType()->isDoubleTy()) { + ExpLb = LibFunc_exp; + Exp2Lb = LibFunc_exp2; + Exp10Lb = LibFunc_exp10; + } else + return nullptr; + } else + return nullptr; + + if (ArgLb != ExpLb && ArgLb != Exp2Lb && ArgLb != Exp10Lb && + ArgID != Intrinsic::exp && ArgID != Intrinsic::exp2) + return nullptr; + + IRBuilderBase::InsertPointGuard Guard(B); + B.SetInsertPoint(Arg); + auto *ExpOperand = Arg->getOperand(0); + auto *FMul = + B.CreateFMulFMF(ExpOperand, ConstantFP::get(ExpOperand->getType(), 0.5), + CI, "merged.sqrt"); + + Arg->setOperand(0, FMul); + return Arg; +} + Value *LibCallSimplifier::optimizeSqrt(CallInst *CI, IRBuilderBase &B) { Module *M = CI->getModule(); Function *Callee = CI->getCalledFunction(); @@ -2557,6 +2621,9 @@ Value *LibCallSimplifier::optimizeSqrt(CallInst *CI, IRBuilderBase &B) { Callee->getIntrinsicID() == Intrinsic::sqrt)) Ret = optimizeUnaryDoubleFP(CI, B, TLI, true); + if (Value *Opt = mergeSqrtToExp(CI, B)) + return Opt; + if (!CI->isFast()) return Ret; @@ -2614,13 +2681,16 @@ Value *LibCallSimplifier::optimizeSqrt(CallInst *CI, IRBuilderBase &B) { return copyFlags(*CI, FabsCall); } -// TODO: Generalize to handle any trig function and its inverse. -Value *LibCallSimplifier::optimizeTan(CallInst *CI, IRBuilderBase &B) { +Value *LibCallSimplifier::optimizeTrigInversionPairs(CallInst *CI, + IRBuilderBase &B) { Module *M = CI->getModule(); Function *Callee = CI->getCalledFunction(); Value *Ret = nullptr; StringRef Name = Callee->getName(); - if (UnsafeFPShrink && Name == "tan" && hasFloatVersion(M, Name)) + if (UnsafeFPShrink && + (Name == "tan" || Name == "atanh" || Name == "sinh" || Name == "cosh" || + Name == "asinh") && + hasFloatVersion(M, Name)) Ret = optimizeUnaryDoubleFP(CI, B, TLI, true); Value *Op1 = CI->getArgOperand(0); @@ -2633,16 +2703,34 @@ Value *LibCallSimplifier::optimizeTan(CallInst *CI, IRBuilderBase &B) { return Ret; // tan(atan(x)) -> x - // tanf(atanf(x)) -> x - // tanl(atanl(x)) -> x + // atanh(tanh(x)) -> x + // sinh(asinh(x)) -> x + // asinh(sinh(x)) -> x + // cosh(acosh(x)) -> x LibFunc Func; Function *F = OpC->getCalledFunction(); if (F && TLI->getLibFunc(F->getName(), Func) && - isLibFuncEmittable(M, TLI, Func) && - ((Func == LibFunc_atan && Callee->getName() == "tan") || - (Func == LibFunc_atanf && Callee->getName() == "tanf") || - (Func == LibFunc_atanl && Callee->getName() == "tanl"))) - Ret = OpC->getArgOperand(0); + isLibFuncEmittable(M, TLI, Func)) { + LibFunc inverseFunc = llvm::StringSwitch(Callee->getName()) + .Case("tan", LibFunc_atan) + .Case("atanh", LibFunc_tanh) + .Case("sinh", LibFunc_asinh) + .Case("cosh", LibFunc_acosh) + .Case("tanf", LibFunc_atanf) + .Case("atanhf", LibFunc_tanhf) + .Case("sinhf", LibFunc_asinhf) + .Case("coshf", LibFunc_acoshf) + .Case("tanl", LibFunc_atanl) + .Case("atanhl", LibFunc_tanhl) + .Case("sinhl", LibFunc_asinhl) + .Case("coshl", LibFunc_acoshl) + .Case("asinh", LibFunc_sinh) + .Case("asinhf", LibFunc_sinhf) + .Case("asinhl", LibFunc_sinhl) + .Default(NumLibFuncs); // Used as error value + if (Func == inverseFunc) + Ret = OpC->getArgOperand(0); + } return Ret; } @@ -3635,7 +3723,19 @@ Value *LibCallSimplifier::optimizeFloatingPointLibCall(CallInst *CI, case LibFunc_tan: case LibFunc_tanf: case LibFunc_tanl: - return optimizeTan(CI, Builder); + case LibFunc_sinh: + case LibFunc_sinhf: + case LibFunc_sinhl: + case LibFunc_asinh: + case LibFunc_asinhf: + case LibFunc_asinhl: + case LibFunc_cosh: + case LibFunc_coshf: + case LibFunc_coshl: + case LibFunc_atanh: + case LibFunc_atanhf: + case LibFunc_atanhl: + return optimizeTrigInversionPairs(CI, Builder); case LibFunc_ceil: return replaceUnaryCall(CI, Builder, Intrinsic::ceil); case LibFunc_floor: @@ -3653,17 +3753,13 @@ Value *LibCallSimplifier::optimizeFloatingPointLibCall(CallInst *CI, case LibFunc_acos: case LibFunc_acosh: case LibFunc_asin: - case LibFunc_asinh: case LibFunc_atan: - case LibFunc_atanh: case LibFunc_cbrt: - case LibFunc_cosh: case LibFunc_exp: case LibFunc_exp10: case LibFunc_expm1: case LibFunc_cos: case LibFunc_sin: - case LibFunc_sinh: case LibFunc_tanh: if (UnsafeFPShrink && hasFloatVersion(M, CI->getCalledFunction()->getName())) return optimizeUnaryDoubleFP(CI, Builder, TLI, true); diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 55466720aa11f90d867672edb5802b0ad2332922..1a7b301c35f2b8b7295059957d7ff677b4479510 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -267,11 +267,6 @@ static cl::opt EnableMaskedInterleavedMemAccesses( "enable-masked-interleaved-mem-accesses", cl::init(false), cl::Hidden, cl::desc("Enable vectorization on masked interleaved memory accesses in a loop")); -static cl::opt TinyTripCountInterleaveThreshold( - "tiny-trip-count-interleave-threshold", cl::init(128), cl::Hidden, - cl::desc("We don't interleave loops with a estimated constant trip count " - "below this number")); - static cl::opt ForceTargetNumScalarRegs( "force-target-num-scalar-regs", cl::init(0), cl::Hidden, cl::desc("A flag that overrides the target's number of scalar registers.")); @@ -5348,14 +5343,6 @@ LoopVectorizationCostModel::selectInterleaveCount(ElementCount VF, auto BestKnownTC = getSmallBestKnownTC(*PSE.getSE(), TheLoop); const bool HasReductions = !Legal->getReductionVars().empty(); - // Do not interleave loops with a relatively small known or estimated trip - // count. But we will interleave when InterleaveSmallLoopScalarReduction is - // enabled, and the code has scalar reductions(HasReductions && VF = 1), - // because with the above conditions interleaving can expose ILP and break - // cross iteration dependences for reductions. - if (BestKnownTC && (*BestKnownTC < TinyTripCountInterleaveThreshold) && - !(InterleaveSmallLoopScalarReduction && HasReductions && VF.isScalar())) - return 1; // If we did not calculate the cost for VF (because the user selected the VF) // then we calculate the cost of VF here. diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index b8d04322de298420b1145cf5d1cd004a2392e209..c0b7298f78005d31f65b92a65a64970115074f27 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -6954,6 +6954,82 @@ getShuffleCost(const TargetTransformInfo &TTI, TTI::ShuffleKind Kind, return TTI.getShuffleCost(Kind, Tp, Mask, CostKind, Index, SubTp, Args); } +/// Calculate the scalar and the vector costs from vectorizing set of GEPs. +static std::pair +getGEPCosts(const TargetTransformInfo &TTI, ArrayRef Ptrs, + Value *BasePtr, unsigned Opcode, TTI::TargetCostKind CostKind, + Type *ScalarTy, VectorType *VecTy) { + InstructionCost ScalarCost = 0; + InstructionCost VecCost = 0; + // Here we differentiate two cases: (1) when Ptrs represent a regular + // vectorization tree node (as they are pointer arguments of scattered + // loads) or (2) when Ptrs are the arguments of loads or stores being + // vectorized as plane wide unit-stride load/store since all the + // loads/stores are known to be from/to adjacent locations. + if (Opcode == Instruction::Load || Opcode == Instruction::Store) { + // Case 2: estimate costs for pointer related costs when vectorizing to + // a wide load/store. + // Scalar cost is estimated as a set of pointers with known relationship + // between them. + // For vector code we will use BasePtr as argument for the wide load/store + // but we also need to account all the instructions which are going to + // stay in vectorized code due to uses outside of these scalar + // loads/stores. + ScalarCost = TTI.getPointersChainCost( + Ptrs, BasePtr, TTI::PointersChainInfo::getUnitStride(), ScalarTy, + CostKind); + + SmallVector PtrsRetainedInVecCode; + for (Value *V : Ptrs) { + if (V == BasePtr) { + PtrsRetainedInVecCode.push_back(V); + continue; + } + auto *Ptr = dyn_cast(V); + // For simplicity assume Ptr to stay in vectorized code if it's not a + // GEP instruction. We don't care since it's cost considered free. + // TODO: We should check for any uses outside of vectorizable tree + // rather than just single use. + if (!Ptr || !Ptr->hasOneUse()) + PtrsRetainedInVecCode.push_back(V); + } + + if (PtrsRetainedInVecCode.size() == Ptrs.size()) { + // If all pointers stay in vectorized code then we don't have + // any savings on that. + return std::make_pair(TTI::TCC_Free, TTI::TCC_Free); + } + VecCost = TTI.getPointersChainCost(PtrsRetainedInVecCode, BasePtr, + TTI::PointersChainInfo::getKnownStride(), + VecTy, CostKind); + } else { + // Case 1: Ptrs are the arguments of loads that we are going to transform + // into masked gather load intrinsic. + // All the scalar GEPs will be removed as a result of vectorization. + // For any external uses of some lanes extract element instructions will + // be generated (which cost is estimated separately). + TTI::PointersChainInfo PtrsInfo = + all_of(Ptrs, + [](const Value *V) { + auto *Ptr = dyn_cast(V); + return Ptr && !Ptr->hasAllConstantIndices(); + }) + ? TTI::PointersChainInfo::getUnknownStride() + : TTI::PointersChainInfo::getKnownStride(); + + ScalarCost = + TTI.getPointersChainCost(Ptrs, BasePtr, PtrsInfo, ScalarTy, CostKind); + if (auto *BaseGEP = dyn_cast(BasePtr)) { + SmallVector Indices(BaseGEP->indices()); + VecCost = TTI.getGEPCost(BaseGEP->getSourceElementType(), + BaseGEP->getPointerOperand(), Indices, VecTy, + CostKind); + } + } + + return std::make_pair(ScalarCost, VecCost); +} + /// Merges shuffle masks and emits final shuffle instruction, if required. It /// supports shuffling of 2 input vectors. It implements lazy shuffles emission, /// when the actual shuffle instruction is generated only if this is actually @@ -7013,9 +7089,10 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { }))) && !all_of(Gathers, [&](Value *V) { return R.getTreeEntry(V); }) && !isSplat(Gathers)) { + InstructionCost BaseCost = R.getGatherCost(Gathers, !Root); SetVector VectorizedLoads; - SmallVector VectorizedStarts; - SmallVector> ScatterVectorized; + SmallVector VectorizedStarts; + SmallVector ScatterVectorized; unsigned StartIdx = 0; unsigned VF = VL.size() / 2; for (; VF >= MinVF; VF /= 2) { @@ -7043,9 +7120,9 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { // again. // TODO: better handling of loads with reorders. if (LS == LoadsState::Vectorize && CurrentOrder.empty()) - VectorizedStarts.push_back(cast(Slice.front())); + VectorizedStarts.push_back(Cnt); else - ScatterVectorized.emplace_back(Cnt, VF); + ScatterVectorized.push_back(Cnt); VectorizedLoads.insert(Slice.begin(), Slice.end()); // If we vectorized initial block, no need to try to vectorize // it again. @@ -7087,20 +7164,53 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { CostKind, TTI::OperandValueInfo(), LI); } auto *LoadTy = FixedVectorType::get(VL.front()->getType(), VF); - for (LoadInst *LI : VectorizedStarts) { + for (unsigned P : VectorizedStarts) { + auto *LI = cast(VL[P]); Align Alignment = LI->getAlign(); GatherCost += TTI.getMemoryOpCost(Instruction::Load, LoadTy, Alignment, LI->getPointerAddressSpace(), CostKind, TTI::OperandValueInfo(), LI); + // Estimate GEP cost. + SmallVector PointerOps(VF); + for (auto [I, V] : enumerate(VL.slice(P, VF))) + PointerOps[I] = cast(V)->getPointerOperand(); + auto [ScalarGEPCost, VectorGEPCost] = + getGEPCosts(TTI, PointerOps, LI->getPointerOperand(), + Instruction::Load, CostKind, LI->getType(), LoadTy); + GatherCost += VectorGEPCost - ScalarGEPCost; } - for (std::pair P : ScatterVectorized) { - auto *LI0 = cast(VL[P.first]); - Align CommonAlignment = - computeCommonAlignment(VL.slice(P.first + 1, VF - 1)); + for (unsigned P : ScatterVectorized) { + auto *LI0 = cast(VL[P]); + ArrayRef Slice = VL.slice(P, VF); + Align CommonAlignment = computeCommonAlignment(Slice); GatherCost += TTI.getGatherScatterOpCost( Instruction::Load, LoadTy, LI0->getPointerOperand(), /*VariableMask=*/false, CommonAlignment, CostKind, LI0); + // Estimate GEP cost. + SmallVector PointerOps(VF); + for (auto [I, V] : enumerate(Slice)) + PointerOps[I] = cast(V)->getPointerOperand(); + OrdersType Order; + if (sortPtrAccesses(PointerOps, LI0->getType(), *R.DL, *R.SE, + Order)) { + // TODO: improve checks if GEPs can be vectorized. + Value *Ptr0 = PointerOps.front(); + Type *ScalarTy = Ptr0->getType(); + auto *VecTy = FixedVectorType::get(ScalarTy, VF); + auto [ScalarGEPCost, VectorGEPCost] = + getGEPCosts(TTI, PointerOps, Ptr0, Instruction::GetElementPtr, + CostKind, ScalarTy, VecTy); + GatherCost += VectorGEPCost - ScalarGEPCost; + if (!Order.empty()) { + SmallVector Mask; + inversePermutation(Order, Mask); + GatherCost += ::getShuffleCost(TTI, TTI::SK_PermuteSingleSrc, + VecTy, Mask, CostKind); + } + } else { + GatherCost += R.getGatherCost(PointerOps, /*ForPoisonSrc=*/true); + } } if (NeedInsertSubvectorAnalysis) { // Add the cost for the subvectors insert. @@ -7110,6 +7220,7 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { } GatherCost -= ScalarsCost; } + GatherCost = std::min(BaseCost, GatherCost); } else if (!Root && isSplat(VL)) { // Found the broadcasting of the single scalar, calculate the cost as // the broadcast. @@ -7917,78 +8028,12 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, // Calculate cost difference from vectorizing set of GEPs. // Negative value means vectorizing is profitable. auto GetGEPCostDiff = [=](ArrayRef Ptrs, Value *BasePtr) { - InstructionCost ScalarCost = 0; - InstructionCost VecCost = 0; - // Here we differentiate two cases: (1) when Ptrs represent a regular - // vectorization tree node (as they are pointer arguments of scattered - // loads) or (2) when Ptrs are the arguments of loads or stores being - // vectorized as plane wide unit-stride load/store since all the - // loads/stores are known to be from/to adjacent locations. assert(E->State == TreeEntry::Vectorize && "Entry state expected to be Vectorize here."); - if (isa(VL0)) { - // Case 2: estimate costs for pointer related costs when vectorizing to - // a wide load/store. - // Scalar cost is estimated as a set of pointers with known relationship - // between them. - // For vector code we will use BasePtr as argument for the wide load/store - // but we also need to account all the instructions which are going to - // stay in vectorized code due to uses outside of these scalar - // loads/stores. - ScalarCost = TTI->getPointersChainCost( - Ptrs, BasePtr, TTI::PointersChainInfo::getUnitStride(), ScalarTy, - CostKind); - - SmallVector PtrsRetainedInVecCode; - for (Value *V : Ptrs) { - if (V == BasePtr) { - PtrsRetainedInVecCode.push_back(V); - continue; - } - auto *Ptr = dyn_cast(V); - // For simplicity assume Ptr to stay in vectorized code if it's not a - // GEP instruction. We don't care since it's cost considered free. - // TODO: We should check for any uses outside of vectorizable tree - // rather than just single use. - if (!Ptr || !Ptr->hasOneUse()) - PtrsRetainedInVecCode.push_back(V); - } - - if (PtrsRetainedInVecCode.size() == Ptrs.size()) { - // If all pointers stay in vectorized code then we don't have - // any savings on that. - LLVM_DEBUG(dumpTreeCosts(E, 0, ScalarCost, ScalarCost, - "Calculated GEPs cost for Tree")); - return InstructionCost{TTI::TCC_Free}; - } - VecCost = TTI->getPointersChainCost( - PtrsRetainedInVecCode, BasePtr, - TTI::PointersChainInfo::getKnownStride(), VecTy, CostKind); - } else { - // Case 1: Ptrs are the arguments of loads that we are going to transform - // into masked gather load intrinsic. - // All the scalar GEPs will be removed as a result of vectorization. - // For any external uses of some lanes extract element instructions will - // be generated (which cost is estimated separately). - TTI::PointersChainInfo PtrsInfo = - all_of(Ptrs, - [](const Value *V) { - auto *Ptr = dyn_cast(V); - return Ptr && !Ptr->hasAllConstantIndices(); - }) - ? TTI::PointersChainInfo::getUnknownStride() - : TTI::PointersChainInfo::getKnownStride(); - - ScalarCost = TTI->getPointersChainCost(Ptrs, BasePtr, PtrsInfo, ScalarTy, - CostKind); - if (auto *BaseGEP = dyn_cast(BasePtr)) { - SmallVector Indices(BaseGEP->indices()); - VecCost = TTI->getGEPCost(BaseGEP->getSourceElementType(), - BaseGEP->getPointerOperand(), Indices, VecTy, - CostKind); - } - } - + InstructionCost ScalarCost = 0; + InstructionCost VecCost = 0; + std::tie(ScalarCost, VecCost) = getGEPCosts( + *TTI, Ptrs, BasePtr, E->getOpcode(), CostKind, ScalarTy, VecTy); LLVM_DEBUG(dumpTreeCosts(E, 0, VecCost, ScalarCost, "Calculated GEPs cost for Tree")); diff --git a/llvm/test/Analysis/CostModel/X86/free-intrinsics.ll b/llvm/test/Analysis/CostModel/X86/free-intrinsics.ll index 3c39e456eed5f9939492278736f8ce7681b04f63..1e9fd0df789229444993836d773b9c410933c83c 100644 --- a/llvm/test/Analysis/CostModel/X86/free-intrinsics.ll +++ b/llvm/test/Analysis/CostModel/X86/free-intrinsics.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -mtriple=x86_64-- -passes="print" 2>&1 -disable-output -cost-kind=code-size %s -S -o - | FileCheck %s --check-prefix=CHECK-SIZE -; RUN: opt -mtriple=x86_64-- -passes="print" 2>&1 -disable-output -cost-kind=throughput %s -S -o - | FileCheck %s --check-prefix=CHECK-THROUGHPUT +;; Pin this test to not use "RemoveDIs" non-intrinsic debug-info. We get the +;; correct output in that mode, but it generates spurious test changes, so +;; avoid that for the moment. +; RUN: opt -mtriple=x86_64-- -passes="print" 2>&1 -disable-output -cost-kind=code-size %s -S -o - --experimental-debuginfo-iterators=false | FileCheck %s --check-prefix=CHECK-SIZE +; RUN: opt -mtriple=x86_64-- -passes="print" 2>&1 -disable-output -cost-kind=throughput %s -S -o - --experimental-debuginfo-iterators=false | FileCheck %s --check-prefix=CHECK-THROUGHPUT define i32 @trivially_free() { ; CHECK-SIZE-LABEL: 'trivially_free' diff --git a/llvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll b/llvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll index b5f204c2d9b26e49026f269f5f17690e7ca81bf7..4ebb1e314ba183509abb791ef7b774a2841acdb0 100644 --- a/llvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll +++ b/llvm/test/Analysis/CostModel/free-intrinsics-datalayout.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=code-size %s -S -o - | FileCheck %s --check-prefix=CHECK-SIZE -; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=throughput %s -S -o - | FileCheck %s --check-prefix=CHECK-THROUGHPUT +;; Pin this test to not use "RemoveDIs" non-intrinsic debug-info. We get the +;; correct output in that mode, but it generates spurious test changes, so +;; avoid that for the moment. +; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=code-size %s -S -o - --experimental-debuginfo-iterators=false | FileCheck %s --check-prefix=CHECK-SIZE +; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=throughput %s -S -o - --experimental-debuginfo-iterators=false | FileCheck %s --check-prefix=CHECK-THROUGHPUT target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" diff --git a/llvm/test/Analysis/CostModel/free-intrinsics-no_info.ll b/llvm/test/Analysis/CostModel/free-intrinsics-no_info.ll index 5d4dcaa7cbe2f3844651db933c6dc7b3600195ea..5d47e48944271fdc314a6b50cb6bba08d38dd08a 100644 --- a/llvm/test/Analysis/CostModel/free-intrinsics-no_info.ll +++ b/llvm/test/Analysis/CostModel/free-intrinsics-no_info.ll @@ -1,6 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=code-size %s -S -o - | FileCheck %s --check-prefix=CHECK-SIZE -; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=throughput %s -S -o - | FileCheck %s --check-prefix=CHECK-THROUGHPUT +;; Pin this test to not use "RemoveDIs" non-intrinsic debug-info. We get the +;; correct output in that mode, but it generates spurious test changes, so +;; avoid that for the moment. +; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=code-size %s -S -o - --experimental-debuginfo-iterators=false | FileCheck %s --check-prefix=CHECK-SIZE +; RUN: opt -passes="print" 2>&1 -disable-output -cost-kind=throughput %s -S -o - --experimental-debuginfo-iterators=false | FileCheck %s --check-prefix=CHECK-THROUGHPUT define i32 @trivially_free() { ; CHECK-SIZE-LABEL: 'trivially_free' diff --git a/llvm/test/Assembler/DIDefaultTemplateParam.ll b/llvm/test/Assembler/DIDefaultTemplateParam.ll index 4ebd45a2749ef17a9e3f534286883377e1e4e852..015da31629ad8bd928be0918f5ad33d75bbd3960 100644 --- a/llvm/test/Assembler/DIDefaultTemplateParam.ll +++ b/llvm/test/Assembler/DIDefaultTemplateParam.ll @@ -29,6 +29,19 @@ attributes #1 = { nounwind readnone speculatable willreturn } !llvm.module.flags = !{!3, !4, !5} !llvm.ident = !{!6} +;; Test that the templateParams for the DICompositeTypes are retained: +; CHECK: ![[COMPTAG:[0-9]+]] = distinct !DICompositeType(tag: DW_TAG_class_type, name: "foo", +; CHECK-SAME: templateParams: ![[PARAMLIST:[0-9]+]] +; CHECK: ![[PARAMLIST]] = !{![[PARAM1:[0-9]+]], ![[PARAM2:[0-9]+]]} +; CHECK: ![[PARAM1]] = !DITemplateTypeParameter(name: "T", type: !{{[0-9]*}}) +; CHECK: ![[PARAM2]] = !DITemplateValueParameter(name: "i", type: !{{[0-9]*}}, value: i32 6) + +; CHECK: ![[COMPTAG2:[0-9]+]] = distinct !DICompositeType(tag: DW_TAG_class_type, name: "foo", +; CHECK-SAME: templateParams: ![[PARAMLIST2:[0-9]+]] +; CHECK: ![[PARAMLIST2]] = !{![[PARAM3:[0-9]+]], ![[PARAM4:[0-9]+]]} +; CHECK: ![[PARAM3]] = !DITemplateTypeParameter({{.*}}, defaulted: true +; CHECK: ![[PARAM4]] = !DITemplateValueParameter({{.*}}, defaulted: true + !0 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus_14, file: !1, producer: "clang version 11.0.0", isOptimized: false, runtimeVersion: 0, emissionKind: FullDebug, enums: !2, splitDebugInlining: false, nameTableKind: None) !1 = !DIFile(filename: "test.cpp", directory: "/dir/", checksumkind: CSK_MD5, checksum: "863d08522c2300490dea873efc4b2369") !2 = !{} @@ -43,23 +56,14 @@ attributes #1 = { nounwind readnone speculatable willreturn } !11 = !DILocalVariable(name: "f1", scope: !7, file: !1, line: 30, type: !12) !12 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "foo", file: !1, line: 26, size: 8, flags: DIFlagTypePassByValue, elements: !2, templateParams: !13, identifier: "_ZTS3fooIiLi6EE") !13 = !{!14, !15} - -; CHECK: 14 = !DITemplateTypeParameter(name: "T", type: !{{[0-9]*}}) !14 = !DITemplateTypeParameter(name: "T", type: !10) - -; CHECK: 15 = !DITemplateValueParameter(name: "i", type: !{{[0-9]*}}, value: i32 6) !15 = !DITemplateValueParameter(name: "i", type: !10, value: i32 6) - !16 = !DILocation(line: 30, column: 14, scope: !7) !17 = !DILocalVariable(name: "f2", scope: !7, file: !1, line: 31, type: !18) !18 = distinct !DICompositeType(tag: DW_TAG_class_type, name: "foo", file: !1, line: 26, size: 8, flags: DIFlagTypePassByValue, elements: !2, templateParams: !19, identifier: "_ZTS3fooIcLi3EE") !19 = !{!20, !22} - -; CHECK: 20 = !DITemplateTypeParameter({{.*}}, defaulted: true !20 = !DITemplateTypeParameter(name: "T", type: !21, defaulted: true) !21 = !DIBasicType(name: "char", size: 8, encoding: DW_ATE_signed_char) - -; CHECK: 22 = !DITemplateValueParameter({{.*}}, defaulted: true !22 = !DITemplateValueParameter(name: "i", type: !10, defaulted: true, value: i32 3) !23 = !DILocation(line: 31, column: 9, scope: !7) !24 = !DILocation(line: 32, column: 3, scope: !7) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir new file mode 100644 index 0000000000000000000000000000000000000000..f667a83bf21a8b3deca1d32b8ca89cb74db1b0be --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-logic-of-compare.mir @@ -0,0 +1,262 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -debugify-and-strip-all-safe -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs -mtriple aarch64-unknown-unknown %s -o - | FileCheck %s +--- +# icmp (x, 1) && icmp (x, 2) -> x +name: test_icmp_and_icmp +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# multi use icmp (x, 1) && icmp (x, 2) -> x +name: multi_use_test_icmp_and_icmp +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: multi_use_test_icmp_and_icmp + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %two:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: %cmp1:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %cmp2:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), %two + ; CHECK-NEXT: %and:_(s1) = G_AND %cmp1, %cmp2 + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT %and(s1) + ; CHECK-NEXT: %cmp1zext:_(s64) = G_ZEXT %cmp1(s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + ; CHECK-NEXT: $x0 = COPY %cmp1zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + %cmp1zext:_(s64) = G_ZEXT %cmp1(s1) + $x0 = COPY %zext + $x0 = COPY %cmp1zext +... +--- +# icmp (x, 1) && icmp (x, add(x, 2)) -> x +name: test_icmp_and_icmp_with_add +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp_with_add + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 1 + ; CHECK-NEXT: %cmp1:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT %cmp1(s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 1 + %two:_(s64) = G_CONSTANT i64 2 + %add:_(s64) = G_ADD %0(s64), %two + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %add + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# icmp (x, 1) && icmp (x, add(x, 2000)) -> x +name: test_icmp_or_icmp_with_add_2000 +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp_with_add_2000 + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %one:_(s64) = G_CONSTANT i64 -100 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY]](s64), %one + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 -100 + %two:_(s64) = G_CONSTANT i64 2000 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %or:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %or(s1) + $x0 = COPY %zext +... +--- +# icmp (x, -100) || icmp (x, 2000) -> x +name: test_icmp_or_icmp +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: %two:_(s64) = G_CONSTANT i64 2000 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ne), [[COPY]](s64), %two + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 -100 + %two:_(s64) = G_CONSTANT i64 2000 + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(ne), %0(s64), %two + %or:_(s1) = G_OR %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %or(s1) + $x0 = COPY %zext +... +--- +# offset icmp (x, -100) || icmp (x, 2000) -> x +name: test_icmp_or_icmp_offset +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp_offset + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2001 + ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[C]] + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s64) = G_CONSTANT i64 -2101 + ; CHECK-NEXT: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[ADD]](s64), [[C1]] + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT [[ICMP]](s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %one:_(s64) = G_CONSTANT i64 -100 + %two:_(s64) = G_CONSTANT i64 2000 + %cmp1:_(s1) = G_ICMP intpred(slt), %0(s64), %one + %cmp2:_(s1) = G_ICMP intpred(sgt), %0(s64), %two + %or:_(s1) = G_OR %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %or(s1) + $x0 = COPY %zext +... +--- +# icmp (x, add(x, 9) || icmp (x, add(x, 2)) -> x +name: test_icmp_or_icmp_with_add_and_add +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_or_icmp_with_add_and_add + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: %two:_(s64) = G_CONSTANT i64 2 + ; CHECK-NEXT: %add2:_(s64) = G_ADD [[COPY]], %two + ; CHECK-NEXT: %cmp2:_(s1) = G_ICMP intpred(ne), [[COPY1]](s64), %add2 + ; CHECK-NEXT: %zext:_(s64) = G_ZEXT %cmp2(s1) + ; CHECK-NEXT: $x0 = COPY %zext(s64) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %nine:_(s64) = G_CONSTANT i64 9 + %two:_(s64) = G_CONSTANT i64 2 + %add1:_(s64) = G_ADD %0(s64), %nine + %add2:_(s64) = G_ADD %0(s64), %two + %cmp1:_(s1) = G_ICMP intpred(eq), %0(s64), %add1 + %cmp2:_(s1) = G_ICMP intpred(ne), %1(s64), %add2 + %and:_(s1) = G_OR %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# icmp (x, 9) && icmp (x, 2)) -> x +# buildConstant 0 +# buildICmp ult, R1, NewC +# buildZExtOrTrunc -> COPY +# erase G_AND +# x > 9 && x < 2 => false +name: test_icmp_and_icmp_9_2 +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp_9_2 + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: $x0 = COPY [[C]](s64) + %0:_(s64) = COPY $x0 + %nine:_(s64) = G_CONSTANT i64 9 + %two:_(s64) = G_CONSTANT i64 2 + %cmp1:_(s1) = G_ICMP intpred(sgt), %0(s64), %nine + %cmp2:_(s1) = G_ICMP intpred(slt), %0(s64), %two + %and:_(s1) = G_AND %cmp1, %cmp2 + %zext:_(s64) = G_ZEXT %and(s1) + $x0 = COPY %zext +... +--- +# icmp (x, v1) && icmp (x, v2)) -> x +name: test_icmp_and_icmp_with_vectors +body: | + bb.1: + liveins: $x0, $x1 + ; CHECK-LABEL: name: test_icmp_and_icmp_with_vectors + ; CHECK: liveins: $x0, $x1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s64) = COPY $x2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s64) = COPY $x3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:_(s64) = COPY $x4 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:_(s64) = COPY $x5 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:_(s64) = COPY $x6 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:_(s64) = COPY $x7 + ; CHECK-NEXT: %v1:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64) + ; CHECK-NEXT: %v2:_(<2 x s64>) = G_BUILD_VECTOR [[COPY2]](s64), [[COPY3]](s64) + ; CHECK-NEXT: %v3:_(<2 x s64>) = G_BUILD_VECTOR [[COPY4]](s64), [[COPY5]](s64) + ; CHECK-NEXT: %v4:_(<2 x s64>) = G_BUILD_VECTOR [[COPY6]](s64), [[COPY7]](s64) + ; CHECK-NEXT: %cmp1:_(<2 x s1>) = G_ICMP intpred(ne), %v1(<2 x s64>), %v2 + ; CHECK-NEXT: %cmp2:_(<2 x s1>) = G_ICMP intpred(eq), %v3(<2 x s64>), %v4 + ; CHECK-NEXT: %and:_(<2 x s1>) = G_AND %cmp1, %cmp2 + ; CHECK-NEXT: %zext:_(<2 x s64>) = G_ZEXT %and(<2 x s1>) + ; CHECK-NEXT: $q0 = COPY %zext(<2 x s64>) + %0:_(s64) = COPY $x0 + %1:_(s64) = COPY $x1 + %2:_(s64) = COPY $x2 + %3:_(s64) = COPY $x3 + %4:_(s64) = COPY $x4 + %5:_(s64) = COPY $x5 + %6:_(s64) = COPY $x6 + %7:_(s64) = COPY $x7 + %nine:_(s64) = G_CONSTANT i64 9 + %two:_(s64) = G_CONSTANT i64 2 + %v1:_(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64) + %v2:_(<2 x s64>) = G_BUILD_VECTOR %2(s64), %3(s64) + %v3:_(<2 x s64>) = G_BUILD_VECTOR %4(s64), %5(s64) + %v4:_(<2 x s64>) = G_BUILD_VECTOR %6(s64), %7(s64) + %cmp1:_(<2 x s1>) = G_ICMP intpred(ne), %v1(<2 x s64>), %v2 + %cmp2:_(<2 x s1>) = G_ICMP intpred(eq), %v3(<2 x s64>), %v4 + %and:_(<2 x s1>) = G_AND %cmp1, %cmp2 + %zext:_(<2 x s64>) = G_ZEXT %and(<2 x s1>) + $q0 = COPY %zext +... diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir index 13fd146f8744c4b0d56a29849c362fc5832fecea..d6618d440f42aafe28b825fd961dce6f6d19d0f0 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-insert-vector-elt.mir @@ -12,11 +12,12 @@ body: | ; CHECK-LABEL: name: v16s8_gpr ; CHECK: liveins: $q1, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]] - ; CHECK: $q0 = COPY [[INSvi8gpr]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[COPY1]], 1, [[COPY]] + ; CHECK-NEXT: $q0 = COPY [[INSvi8gpr]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s32) = COPY $w0 %trunc:gpr(s8) = G_TRUNC %0 %1:fpr(<16 x s8>) = COPY $q1 @@ -38,14 +39,15 @@ body: | ; CHECK-LABEL: name: v8s8_gpr ; CHECK: liveins: $d0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub - ; CHECK: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[INSERT_SUBREG]], 1, [[COPY]] - ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub - ; CHECK: $d0 = COPY [[COPY2]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSvi8gpr:%[0-9]+]]:fpr128 = INSvi8gpr [[INSERT_SUBREG]], 1, [[COPY]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi8gpr]].dsub + ; CHECK-NEXT: $d0 = COPY [[COPY2]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:gpr(s32) = COPY $w0 %trunc:gpr(s8) = G_TRUNC %0 %1:fpr(<8 x s8>) = COPY $d0 @@ -67,11 +69,12 @@ body: | ; CHECK-LABEL: name: v8s16_gpr ; CHECK: liveins: $q1, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]] - ; CHECK: $q0 = COPY [[INSvi16gpr]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]] + ; CHECK-NEXT: $q0 = COPY [[INSvi16gpr]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s32) = COPY $w0 %trunc:gpr(s16) = G_TRUNC %0 %1:fpr(<8 x s16>) = COPY $q1 @@ -93,13 +96,14 @@ body: | ; CHECK-LABEL: name: v8s16_fpr ; CHECK: liveins: $q1, $h0 - ; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub - ; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 - ; CHECK: $q0 = COPY [[INSvi16lane]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr16 = COPY $h0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub + ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 + ; CHECK-NEXT: $q0 = COPY [[INSvi16lane]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s16) = COPY $h0 %1:fpr(<8 x s16>) = COPY $q1 %3:gpr(s32) = G_CONSTANT i32 1 @@ -120,13 +124,14 @@ body: | ; CHECK-LABEL: name: v4s32_fpr ; CHECK: liveins: $q1, $s0 - ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub - ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 - ; CHECK: $q0 = COPY [[INSvi32lane]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub + ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 + ; CHECK-NEXT: $q0 = COPY [[INSvi32lane]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s32) = COPY $s0 %1:fpr(<4 x s32>) = COPY $q1 %3:gpr(s32) = G_CONSTANT i32 1 @@ -147,11 +152,12 @@ body: | ; CHECK-LABEL: name: v4s32_gpr ; CHECK: liveins: $q0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]] - ; CHECK: $q0 = COPY [[INSvi32gpr]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]] + ; CHECK-NEXT: $q0 = COPY [[INSvi32gpr]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s32) = COPY $w0 %1:fpr(<4 x s32>) = COPY $q0 %3:gpr(s32) = G_CONSTANT i32 1 @@ -172,14 +178,15 @@ body: | ; CHECK-LABEL: name: v4s16_gpr ; CHECK: liveins: $d0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub - ; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[INSERT_SUBREG]], 1, [[COPY]] - ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub - ; CHECK: $d0 = COPY [[COPY2]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[INSERT_SUBREG]], 1, [[COPY]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi16gpr]].dsub + ; CHECK-NEXT: $d0 = COPY [[COPY2]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:gpr(s32) = COPY $w0 %trunc:gpr(s16) = G_TRUNC %0 %1:fpr(<4 x s16>) = COPY $d0 @@ -201,13 +208,14 @@ body: | ; CHECK-LABEL: name: v2s64_fpr ; CHECK: liveins: $d0, $q1 - ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub - ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 - ; CHECK: $q0 = COPY [[INSvi64lane]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub + ; CHECK-NEXT: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0 + ; CHECK-NEXT: $q0 = COPY [[INSvi64lane]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:fpr(s64) = COPY $d0 %1:fpr(<2 x s64>) = COPY $q1 %3:gpr(s32) = G_CONSTANT i32 1 @@ -228,11 +236,12 @@ body: | ; CHECK-LABEL: name: v2s64_gpr ; CHECK: liveins: $q0, $x0 - ; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 - ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]] - ; CHECK: $q0 = COPY [[INSvi64gpr]] - ; CHECK: RET_ReallyLR implicit $q0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr64 = COPY $x0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0 + ; CHECK-NEXT: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]] + ; CHECK-NEXT: $q0 = COPY [[INSvi64gpr]] + ; CHECK-NEXT: RET_ReallyLR implicit $q0 %0:gpr(s64) = COPY $x0 %1:fpr(<2 x s64>) = COPY $q0 %3:gpr(s32) = G_CONSTANT i32 0 @@ -253,16 +262,17 @@ body: | ; CHECK-LABEL: name: v2s32_fpr ; CHECK: liveins: $d1, $s0 - ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub - ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub - ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 - ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub - ; CHECK: $d0 = COPY [[COPY2]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub + ; CHECK-NEXT: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub + ; CHECK-NEXT: $d0 = COPY [[COPY2]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:fpr(s32) = COPY $s0 %1:fpr(<2 x s32>) = COPY $d1 %3:gpr(s32) = G_CONSTANT i32 1 @@ -283,14 +293,15 @@ body: | ; CHECK-LABEL: name: v2s32_gpr ; CHECK: liveins: $d0, $w0 - ; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 - ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 - ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF - ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub - ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]] - ; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub - ; CHECK: $d0 = COPY [[COPY2]] - ; CHECK: RET_ReallyLR implicit $d0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr32 = COPY $w0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF + ; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub + ; CHECK-NEXT: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]] + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub + ; CHECK-NEXT: $d0 = COPY [[COPY2]] + ; CHECK-NEXT: RET_ReallyLR implicit $d0 %0:gpr(s32) = COPY $w0 %1:fpr(<2 x s32>) = COPY $d0 %3:gpr(s32) = G_CONSTANT i32 1 diff --git a/llvm/test/CodeGen/AArch64/arm64-ccmp.ll b/llvm/test/CodeGen/AArch64/arm64-ccmp.ll index 446526986b8837fc856232cf98d1faee20bce19c..5d3b2d3649e1b390657bd507f9ad8cccb7cc8aa7 100644 --- a/llvm/test/CodeGen/AArch64/arm64-ccmp.ll +++ b/llvm/test/CodeGen/AArch64/arm64-ccmp.ll @@ -635,19 +635,7 @@ define i64 @select_noccmp1(i64 %v1, i64 %v2, i64 %v3, i64 %r) { ; ; GISEL-LABEL: select_noccmp1: ; GISEL: ; %bb.0: -; GISEL-NEXT: cmp x0, #0 -; GISEL-NEXT: cset w8, lt -; GISEL-NEXT: cmp x0, #13 -; GISEL-NEXT: cset w9, gt -; GISEL-NEXT: cmp x2, #2 -; GISEL-NEXT: cset w10, lt -; GISEL-NEXT: cmp x2, #4 -; GISEL-NEXT: cset w11, gt -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: and w9, w10, w11 -; GISEL-NEXT: orr w8, w8, w9 -; GISEL-NEXT: tst w8, #0x1 -; GISEL-NEXT: csel x0, xzr, x3, ne +; GISEL-NEXT: mov x0, x3 ; GISEL-NEXT: ret %c0 = icmp slt i64 %v1, 0 %c1 = icmp sgt i64 %v1, 13 @@ -677,11 +665,8 @@ define i64 @select_noccmp2(i64 %v1, i64 %v2, i64 %v3, i64 %r) { ; ; GISEL-LABEL: select_noccmp2: ; GISEL: ; %bb.0: -; GISEL-NEXT: cmp x0, #0 -; GISEL-NEXT: cset w8, lt -; GISEL-NEXT: cmp x0, #13 -; GISEL-NEXT: cset w9, gt -; GISEL-NEXT: orr w8, w8, w9 +; GISEL-NEXT: cmp x0, #14 +; GISEL-NEXT: cset w8, hs ; GISEL-NEXT: tst w8, #0x1 ; GISEL-NEXT: csel x0, xzr, x3, ne ; GISEL-NEXT: sbfx w8, w8, #0, #1 @@ -719,25 +704,14 @@ define i32 @select_noccmp3(i32 %v0, i32 %v1, i32 %v2) { ; ; GISEL-LABEL: select_noccmp3: ; GISEL: ; %bb.0: -; GISEL-NEXT: cmp w0, #0 -; GISEL-NEXT: cset w8, lt -; GISEL-NEXT: cmp w0, #13 -; GISEL-NEXT: cset w9, gt -; GISEL-NEXT: cmp w0, #22 -; GISEL-NEXT: cset w10, lt -; GISEL-NEXT: cmp w0, #44 -; GISEL-NEXT: cset w11, gt -; GISEL-NEXT: cmp w0, #99 -; GISEL-NEXT: cset w12, eq +; GISEL-NEXT: mov w8, #99 ; =0x63 +; GISEL-NEXT: sub w9, w0, #45 +; GISEL-NEXT: mov w10, #-23 ; =0xffffffe9 ; GISEL-NEXT: cmp w0, #77 -; GISEL-NEXT: cset w13, eq -; GISEL-NEXT: orr w8, w8, w9 -; GISEL-NEXT: orr w9, w10, w11 -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: orr w9, w12, w13 -; GISEL-NEXT: and w8, w8, w9 -; GISEL-NEXT: tst w8, #0x1 -; GISEL-NEXT: csel w0, w1, w2, ne +; GISEL-NEXT: ccmp w0, w8, #4, ne +; GISEL-NEXT: ccmp w9, w10, #2, eq +; GISEL-NEXT: ccmp w0, #14, #0, lo +; GISEL-NEXT: csel w0, w1, w2, hs ; GISEL-NEXT: ret %c0 = icmp slt i32 %v0, 0 %c1 = icmp sgt i32 %v0, 13 diff --git a/llvm/test/CodeGen/AArch64/arm64-fminv.ll b/llvm/test/CodeGen/AArch64/arm64-fminv.ll index 90076a2b66f949e1f65a52a53146ff9b78f46e7a..ae55288f9159d350919cf73c68d4f21344b74e49 100644 --- a/llvm/test/CodeGen/AArch64/arm64-fminv.ll +++ b/llvm/test/CodeGen/AArch64/arm64-fminv.ll @@ -1,23 +1,30 @@ -; RUN: llc -mtriple=arm64-linux-gnu -o - %s | FileCheck %s -; RUN: llc -global-isel=1 -mtriple=arm64-linux-gnu -o - %s | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=arm64-linux-gnu | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -global-isel | FileCheck %s define float @test_fminv_v2f32(<2 x float> %in) { -; CHECK: test_fminv_v2f32: -; CHECK: fminp s0, v0.2s +; CHECK-LABEL: test_fminv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fminp s0, v0.2s +; CHECK-NEXT: ret %min = call float @llvm.aarch64.neon.fminv.f32.v2f32(<2 x float> %in) ret float %min } define float @test_fminv_v4f32(<4 x float> %in) { -; CHECK: test_fminv_v4f32: -; CHECK: fminv s0, v0.4s +; CHECK-LABEL: test_fminv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fminv s0, v0.4s +; CHECK-NEXT: ret %min = call float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float> %in) ret float %min } define double @test_fminv_v2f64(<2 x double> %in) { -; CHECK: test_fminv_v2f64: -; CHECK: fminp d0, v0.2d +; CHECK-LABEL: test_fminv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fminp d0, v0.2d +; CHECK-NEXT: ret %min = call double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double> %in) ret double %min } @@ -27,22 +34,28 @@ declare float @llvm.aarch64.neon.fminv.f32.v4f32(<4 x float>) declare double @llvm.aarch64.neon.fminv.f64.v2f64(<2 x double>) define float @test_fmaxv_v2f32(<2 x float> %in) { -; CHECK: test_fmaxv_v2f32: -; CHECK: fmaxp s0, v0.2s +; CHECK-LABEL: test_fmaxv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxp s0, v0.2s +; CHECK-NEXT: ret %max = call float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float> %in) ret float %max } define float @test_fmaxv_v4f32(<4 x float> %in) { -; CHECK: test_fmaxv_v4f32: -; CHECK: fmaxv s0, v0.4s +; CHECK-LABEL: test_fmaxv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxv s0, v0.4s +; CHECK-NEXT: ret %max = call float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float> %in) ret float %max } define double @test_fmaxv_v2f64(<2 x double> %in) { -; CHECK: test_fmaxv_v2f64: -; CHECK: fmaxp d0, v0.2d +; CHECK-LABEL: test_fmaxv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxp d0, v0.2d +; CHECK-NEXT: ret %max = call double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double> %in) ret double %max } @@ -52,22 +65,28 @@ declare float @llvm.aarch64.neon.fmaxv.f32.v4f32(<4 x float>) declare double @llvm.aarch64.neon.fmaxv.f64.v2f64(<2 x double>) define float @test_fminnmv_v2f32(<2 x float> %in) { -; CHECK: test_fminnmv_v2f32: -; CHECK: fminnmp s0, v0.2s +; CHECK-LABEL: test_fminnmv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnmp s0, v0.2s +; CHECK-NEXT: ret %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v2f32(<2 x float> %in) ret float %minnm } define float @test_fminnmv_v4f32(<4 x float> %in) { -; CHECK: test_fminnmv_v4f32: -; CHECK: fminnmv s0, v0.4s +; CHECK-LABEL: test_fminnmv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnmv s0, v0.4s +; CHECK-NEXT: ret %minnm = call float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float> %in) ret float %minnm } define double @test_fminnmv_v2f64(<2 x double> %in) { -; CHECK: test_fminnmv_v2f64: -; CHECK: fminnmp d0, v0.2d +; CHECK-LABEL: test_fminnmv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnmp d0, v0.2d +; CHECK-NEXT: ret %minnm = call double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double> %in) ret double %minnm } @@ -77,22 +96,28 @@ declare float @llvm.aarch64.neon.fminnmv.f32.v4f32(<4 x float>) declare double @llvm.aarch64.neon.fminnmv.f64.v2f64(<2 x double>) define float @test_fmaxnmv_v2f32(<2 x float> %in) { -; CHECK: test_fmaxnmv_v2f32: -; CHECK: fmaxnmp s0, v0.2s +; CHECK-LABEL: test_fmaxnmv_v2f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnmp s0, v0.2s +; CHECK-NEXT: ret %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v2f32(<2 x float> %in) ret float %maxnm } define float @test_fmaxnmv_v4f32(<4 x float> %in) { -; CHECK: test_fmaxnmv_v4f32: -; CHECK: fmaxnmv s0, v0.4s +; CHECK-LABEL: test_fmaxnmv_v4f32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnmv s0, v0.4s +; CHECK-NEXT: ret %maxnm = call float @llvm.aarch64.neon.fmaxnmv.f32.v4f32(<4 x float> %in) ret float %maxnm } define double @test_fmaxnmv_v2f64(<2 x double> %in) { -; CHECK: test_fmaxnmv_v2f64: -; CHECK: fmaxnmp d0, v0.2d +; CHECK-LABEL: test_fmaxnmv_v2f64: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnmp d0, v0.2d +; CHECK-NEXT: ret %maxnm = call double @llvm.aarch64.neon.fmaxnmv.f64.v2f64(<2 x double> %in) ret double %maxnm } diff --git a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll index 7493afd672d43782bb15b8380c56b752bcbea471..628fb550a0532b4a088809550ea7fba2a750e068 100644 --- a/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll +++ b/llvm/test/CodeGen/AArch64/arm64-indexed-vector-ldst.ll @@ -1,627 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefixes=CHECK,SDAG -; RUN: llc -global-isel=1 -global-isel-abort=2 -mtriple=arm64-apple-ios7.0 -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GISEL - -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_pre_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_pre_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_store -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st1_lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld2r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld3r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld4r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_ld4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st1x2 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st1x3 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st1x4 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st2lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st3lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1i64_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_imm_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v1f64_post_reg_st4lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld1r -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v16i8_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i8_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v8i16_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i32_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i32_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2i64_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f32_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_imm_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v2f64_post_reg_ld1lane -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4f32_post_reg_ld1lane_dep_vec_on_load -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_v4i16_post_reg_ld1lane_forced_narrow -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_ld1lane_build -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_ld1lane_build_i16 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_ld1lane_build_half -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_ld1lane_build_i8 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for test_inc_cycle -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i8 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i16 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_i32 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_masked_i32 -; CHECK-GISEL-NOT: warning: Instruction selection used fallback path for load_single_extract_variable_index_masked2_i32 +; RUN: llc -mtriple=arm64-apple-ios7.0 -o - %s | FileCheck %s --check-prefixes=CHECK,CHECK-SD +; RUN: llc -global-isel=1 -mtriple=arm64-apple-ios7.0 -o - %s 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI @ptr = global ptr null @@ -834,20 +213,20 @@ define void @test_v2f32_post_store(<2 x float> %in, ptr %addr) { } define <1 x i64> @test_v1i64_pre_load(ptr %addr) { -; SDAG-LABEL: test_v1i64_pre_load: -; SDAG: ; %bb.0: -; SDAG-NEXT: ldr d0, [x0, #40]! -; SDAG-NEXT: adrp x8, _ptr@PAGE -; SDAG-NEXT: str x0, [x8, _ptr@PAGEOFF] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_pre_load: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr x8, [x0, #40]! -; CHECK-GISEL-NEXT: adrp x9, _ptr@PAGE -; CHECK-GISEL-NEXT: str x0, [x9, _ptr@PAGEOFF] -; CHECK-GISEL-NEXT: fmov d0, x8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_pre_load: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ldr d0, [x0, #40]! +; CHECK-SD-NEXT: adrp x8, _ptr@PAGE +; CHECK-SD-NEXT: str x0, [x8, _ptr@PAGEOFF] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_pre_load: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr x8, [x0, #40]! +; CHECK-GI-NEXT: adrp x9, _ptr@PAGE +; CHECK-GI-NEXT: str x0, [x9, _ptr@PAGEOFF] +; CHECK-GI-NEXT: fmov d0, x8 +; CHECK-GI-NEXT: ret %newaddr = getelementptr <1 x i64>, ptr %addr, i32 5 %val = load <1 x i64>, ptr %newaddr, align 8 store ptr %newaddr, ptr @ptr @@ -855,20 +234,20 @@ define <1 x i64> @test_v1i64_pre_load(ptr %addr) { } define <1 x i64> @test_v1i64_post_load(ptr %addr) { -; SDAG-LABEL: test_v1i64_post_load: -; SDAG: ; %bb.0: -; SDAG-NEXT: ldr d0, [x0], #40 -; SDAG-NEXT: adrp x8, _ptr@PAGE -; SDAG-NEXT: str x0, [x8, _ptr@PAGEOFF] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_load: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr x8, [x0], #40 -; CHECK-GISEL-NEXT: adrp x9, _ptr@PAGE -; CHECK-GISEL-NEXT: str x0, [x9, _ptr@PAGEOFF] -; CHECK-GISEL-NEXT: fmov d0, x8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_load: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ldr d0, [x0], #40 +; CHECK-SD-NEXT: adrp x8, _ptr@PAGE +; CHECK-SD-NEXT: str x0, [x8, _ptr@PAGEOFF] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_load: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr x8, [x0], #40 +; CHECK-GI-NEXT: adrp x9, _ptr@PAGE +; CHECK-GI-NEXT: str x0, [x9, _ptr@PAGEOFF] +; CHECK-GI-NEXT: fmov d0, x8 +; CHECK-GI-NEXT: ret %newaddr = getelementptr <1 x i64>, ptr %addr, i32 5 %val = load <1 x i64>, ptr %addr, align 8 store ptr %newaddr, ptr @ptr @@ -1217,16 +596,16 @@ define void @test_v2f64_post_store(<2 x double> %in, ptr %addr) { } define ptr @test_v16i8_post_imm_st1_lane(<16 x i8> %in, ptr %addr) { -; SDAG-LABEL: test_v16i8_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: st1.b { v0 }[3], [x0], #1 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov b0, v0[3] -; CHECK-GISEL-NEXT: str b0, [x0], #1 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: st1.b { v0 }[3], [x0], #1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov b0, v0[3] +; CHECK-GI-NEXT: str b0, [x0], #1 +; CHECK-GI-NEXT: ret %elt = extractelement <16 x i8> %in, i32 3 store i8 %elt, ptr %addr @@ -1235,17 +614,17 @@ define ptr @test_v16i8_post_imm_st1_lane(<16 x i8> %in, ptr %addr) { } define ptr @test_v16i8_post_reg_st1_lane(<16 x i8> %in, ptr %addr) { -; SDAG-LABEL: test_v16i8_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #2 ; =0x2 -; SDAG-NEXT: st1.b { v0 }[3], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov b0, v0[3] -; CHECK-GISEL-NEXT: str b0, [x0], #2 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #2 ; =0x2 +; CHECK-SD-NEXT: st1.b { v0 }[3], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov b0, v0[3] +; CHECK-GI-NEXT: str b0, [x0], #2 +; CHECK-GI-NEXT: ret %elt = extractelement <16 x i8> %in, i32 3 store i8 %elt, ptr %addr @@ -1255,16 +634,16 @@ define ptr @test_v16i8_post_reg_st1_lane(<16 x i8> %in, ptr %addr) { define ptr @test_v8i16_post_imm_st1_lane(<8 x i16> %in, ptr %addr) { -; SDAG-LABEL: test_v8i16_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: st1.h { v0 }[3], [x0], #2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov h0, v0[3] -; CHECK-GISEL-NEXT: str h0, [x0], #2 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: st1.h { v0 }[3], [x0], #2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov h0, v0[3] +; CHECK-GI-NEXT: str h0, [x0], #2 +; CHECK-GI-NEXT: ret %elt = extractelement <8 x i16> %in, i32 3 store i16 %elt, ptr %addr @@ -1273,17 +652,17 @@ define ptr @test_v8i16_post_imm_st1_lane(<8 x i16> %in, ptr %addr) { } define ptr @test_v8i16_post_reg_st1_lane(<8 x i16> %in, ptr %addr) { -; SDAG-LABEL: test_v8i16_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #4 ; =0x4 -; SDAG-NEXT: st1.h { v0 }[3], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov h0, v0[3] -; CHECK-GISEL-NEXT: str h0, [x0], #4 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #4 ; =0x4 +; CHECK-SD-NEXT: st1.h { v0 }[3], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov h0, v0[3] +; CHECK-GI-NEXT: str h0, [x0], #4 +; CHECK-GI-NEXT: ret %elt = extractelement <8 x i16> %in, i32 3 store i16 %elt, ptr %addr @@ -1292,16 +671,16 @@ define ptr @test_v8i16_post_reg_st1_lane(<8 x i16> %in, ptr %addr) { } define ptr @test_v4i32_post_imm_st1_lane(<4 x i32> %in, ptr %addr) { -; SDAG-LABEL: test_v4i32_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: st1.s { v0 }[3], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov s0, v0[3] -; CHECK-GISEL-NEXT: str s0, [x0], #4 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: st1.s { v0 }[3], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov s0, v0[3] +; CHECK-GI-NEXT: str s0, [x0], #4 +; CHECK-GI-NEXT: ret %elt = extractelement <4 x i32> %in, i32 3 store i32 %elt, ptr %addr @@ -1310,17 +689,17 @@ define ptr @test_v4i32_post_imm_st1_lane(<4 x i32> %in, ptr %addr) { } define ptr @test_v4i32_post_reg_st1_lane(<4 x i32> %in, ptr %addr) { -; SDAG-LABEL: test_v4i32_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #8 ; =0x8 -; SDAG-NEXT: st1.s { v0 }[3], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov s0, v0[3] -; CHECK-GISEL-NEXT: str s0, [x0], #8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #8 ; =0x8 +; CHECK-SD-NEXT: st1.s { v0 }[3], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov s0, v0[3] +; CHECK-GI-NEXT: str s0, [x0], #8 +; CHECK-GI-NEXT: ret %elt = extractelement <4 x i32> %in, i32 3 store i32 %elt, ptr %addr @@ -1329,16 +708,16 @@ define ptr @test_v4i32_post_reg_st1_lane(<4 x i32> %in, ptr %addr) { } define ptr @test_v4f32_post_imm_st1_lane(<4 x float> %in, ptr %addr) { -; SDAG-LABEL: test_v4f32_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: st1.s { v0 }[3], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov s0, v0[3] -; CHECK-GISEL-NEXT: str s0, [x0], #4 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: st1.s { v0 }[3], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov s0, v0[3] +; CHECK-GI-NEXT: str s0, [x0], #4 +; CHECK-GI-NEXT: ret %elt = extractelement <4 x float> %in, i32 3 store float %elt, ptr %addr @@ -1347,17 +726,17 @@ define ptr @test_v4f32_post_imm_st1_lane(<4 x float> %in, ptr %addr) { } define ptr @test_v4f32_post_reg_st1_lane(<4 x float> %in, ptr %addr) { -; SDAG-LABEL: test_v4f32_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #8 ; =0x8 -; SDAG-NEXT: st1.s { v0 }[3], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov s0, v0[3] -; CHECK-GISEL-NEXT: str s0, [x0], #8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #8 ; =0x8 +; CHECK-SD-NEXT: st1.s { v0 }[3], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov s0, v0[3] +; CHECK-GI-NEXT: str s0, [x0], #8 +; CHECK-GI-NEXT: ret %elt = extractelement <4 x float> %in, i32 3 store float %elt, ptr %addr @@ -1366,16 +745,16 @@ define ptr @test_v4f32_post_reg_st1_lane(<4 x float> %in, ptr %addr) { } define ptr @test_v2i64_post_imm_st1_lane(<2 x i64> %in, ptr %addr) { -; SDAG-LABEL: test_v2i64_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: st1.d { v0 }[1], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov d0, v0[1] -; CHECK-GISEL-NEXT: str d0, [x0], #8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: st1.d { v0 }[1], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov d0, v0[1] +; CHECK-GI-NEXT: str d0, [x0], #8 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x i64> %in, i64 1 store i64 %elt, ptr %addr @@ -1384,17 +763,17 @@ define ptr @test_v2i64_post_imm_st1_lane(<2 x i64> %in, ptr %addr) { } define ptr @test_v2i64_post_reg_st1_lane(<2 x i64> %in, ptr %addr) { -; SDAG-LABEL: test_v2i64_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #16 ; =0x10 -; SDAG-NEXT: st1.d { v0 }[1], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov d0, v0[1] -; CHECK-GISEL-NEXT: str d0, [x0], #16 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #16 ; =0x10 +; CHECK-SD-NEXT: st1.d { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov d0, v0[1] +; CHECK-GI-NEXT: str d0, [x0], #16 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x i64> %in, i64 1 store i64 %elt, ptr %addr @@ -1403,16 +782,16 @@ define ptr @test_v2i64_post_reg_st1_lane(<2 x i64> %in, ptr %addr) { } define ptr @test_v2f64_post_imm_st1_lane(<2 x double> %in, ptr %addr) { -; SDAG-LABEL: test_v2f64_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: st1.d { v0 }[1], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov d0, v0[1] -; CHECK-GISEL-NEXT: str d0, [x0], #8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: st1.d { v0 }[1], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov d0, v0[1] +; CHECK-GI-NEXT: str d0, [x0], #8 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x double> %in, i32 1 store double %elt, ptr %addr @@ -1421,17 +800,17 @@ define ptr @test_v2f64_post_imm_st1_lane(<2 x double> %in, ptr %addr) { } define ptr @test_v2f64_post_reg_st1_lane(<2 x double> %in, ptr %addr) { -; SDAG-LABEL: test_v2f64_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #16 ; =0x10 -; SDAG-NEXT: st1.d { v0 }[1], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov d0, v0[1] -; CHECK-GISEL-NEXT: str d0, [x0], #16 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #16 ; =0x10 +; CHECK-SD-NEXT: st1.d { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov d0, v0[1] +; CHECK-GI-NEXT: str d0, [x0], #16 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x double> %in, i32 1 store double %elt, ptr %addr @@ -1440,18 +819,18 @@ define ptr @test_v2f64_post_reg_st1_lane(<2 x double> %in, ptr %addr) { } define ptr @test_v8i8_post_imm_st1_lane(<8 x i8> %in, ptr %addr) { -; SDAG-LABEL: test_v8i8_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.b { v0 }[3], [x0], #1 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov b0, v0[3] -; CHECK-GISEL-NEXT: str b0, [x0], #1 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.b { v0 }[3], [x0], #1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov b0, v0[3] +; CHECK-GI-NEXT: str b0, [x0], #1 +; CHECK-GI-NEXT: ret %elt = extractelement <8 x i8> %in, i32 3 store i8 %elt, ptr %addr @@ -1460,19 +839,19 @@ define ptr @test_v8i8_post_imm_st1_lane(<8 x i8> %in, ptr %addr) { } define ptr @test_v8i8_post_reg_st1_lane(<8 x i8> %in, ptr %addr) { -; SDAG-LABEL: test_v8i8_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #2 ; =0x2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.b { v0 }[3], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov b0, v0[3] -; CHECK-GISEL-NEXT: str b0, [x0], #2 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #2 ; =0x2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.b { v0 }[3], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov b0, v0[3] +; CHECK-GI-NEXT: str b0, [x0], #2 +; CHECK-GI-NEXT: ret %elt = extractelement <8 x i8> %in, i32 3 store i8 %elt, ptr %addr @@ -1481,18 +860,18 @@ define ptr @test_v8i8_post_reg_st1_lane(<8 x i8> %in, ptr %addr) { } define ptr @test_v4i16_post_imm_st1_lane(<4 x i16> %in, ptr %addr) { -; SDAG-LABEL: test_v4i16_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.h { v0 }[3], [x0], #2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov h0, v0[3] -; CHECK-GISEL-NEXT: str h0, [x0], #2 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.h { v0 }[3], [x0], #2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov h0, v0[3] +; CHECK-GI-NEXT: str h0, [x0], #2 +; CHECK-GI-NEXT: ret %elt = extractelement <4 x i16> %in, i32 3 store i16 %elt, ptr %addr @@ -1501,19 +880,19 @@ define ptr @test_v4i16_post_imm_st1_lane(<4 x i16> %in, ptr %addr) { } define ptr @test_v4i16_post_reg_st1_lane(<4 x i16> %in, ptr %addr) { -; SDAG-LABEL: test_v4i16_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #4 ; =0x4 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.h { v0 }[3], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov h0, v0[3] -; CHECK-GISEL-NEXT: str h0, [x0], #4 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #4 ; =0x4 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.h { v0 }[3], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov h0, v0[3] +; CHECK-GI-NEXT: str h0, [x0], #4 +; CHECK-GI-NEXT: ret %elt = extractelement <4 x i16> %in, i32 3 store i16 %elt, ptr %addr @@ -1522,18 +901,18 @@ define ptr @test_v4i16_post_reg_st1_lane(<4 x i16> %in, ptr %addr) { } define ptr @test_v2i32_post_imm_st1_lane(<2 x i32> %in, ptr %addr) { -; SDAG-LABEL: test_v2i32_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.s { v0 }[1], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov s0, v0[1] -; CHECK-GISEL-NEXT: str s0, [x0], #4 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.s { v0 }[1], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s0, v0[1] +; CHECK-GI-NEXT: str s0, [x0], #4 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x i32> %in, i32 1 store i32 %elt, ptr %addr @@ -1542,19 +921,19 @@ define ptr @test_v2i32_post_imm_st1_lane(<2 x i32> %in, ptr %addr) { } define ptr @test_v2i32_post_reg_st1_lane(<2 x i32> %in, ptr %addr) { -; SDAG-LABEL: test_v2i32_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #8 ; =0x8 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.s { v0 }[1], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov s0, v0[1] -; CHECK-GISEL-NEXT: str s0, [x0], #8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #8 ; =0x8 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.s { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s0, v0[1] +; CHECK-GI-NEXT: str s0, [x0], #8 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x i32> %in, i32 1 store i32 %elt, ptr %addr @@ -1563,18 +942,18 @@ define ptr @test_v2i32_post_reg_st1_lane(<2 x i32> %in, ptr %addr) { } define ptr @test_v2f32_post_imm_st1_lane(<2 x float> %in, ptr %addr) { -; SDAG-LABEL: test_v2f32_post_imm_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.s { v0 }[1], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov s0, v0[1] -; CHECK-GISEL-NEXT: str s0, [x0], #4 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.s { v0 }[1], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s0, v0[1] +; CHECK-GI-NEXT: str s0, [x0], #4 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x float> %in, i32 1 store float %elt, ptr %addr @@ -1583,19 +962,19 @@ define ptr @test_v2f32_post_imm_st1_lane(<2 x float> %in, ptr %addr) { } define ptr @test_v2f32_post_reg_st1_lane(<2 x float> %in, ptr %addr) { -; SDAG-LABEL: test_v2f32_post_reg_st1_lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: mov w8, #8 ; =0x8 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: st1.s { v0 }[1], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st1_lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: mov s0, v0[1] -; CHECK-GISEL-NEXT: str s0, [x0], #8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st1_lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: mov w8, #8 ; =0x8 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: st1.s { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st1_lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s0, v0[1] +; CHECK-GI-NEXT: str s0, [x0], #8 +; CHECK-GI-NEXT: ret %elt = extractelement <2 x float> %in, i32 1 store float %elt, ptr %addr @@ -1604,18 +983,18 @@ define ptr @test_v2f32_post_reg_st1_lane(<2 x float> %in, ptr %addr) { } define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.16b { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.16b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.16b { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.16b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 store ptr %tmp, ptr %ptr @@ -1623,18 +1002,18 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2(ptr %A, ptr %ptr) { } define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.16b { v0, v1 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.16b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.16b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.16b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1645,18 +1024,18 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2.v16i8.p0(ptr) define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.8b { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.8b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.8b { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.8b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -1664,18 +1043,18 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2(ptr %A, ptr %ptr) { } define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.8b { v0, v1 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.8b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.8b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.8b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1686,18 +1065,18 @@ declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2.v8i8.p0(ptr) define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.8h { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.8h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.8h { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.8h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -1705,19 +1084,19 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2(ptr %A, ptr %ptr) { } define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld2.8h { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.8h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld2.8h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.8h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1728,18 +1107,18 @@ declare { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2.v8i16.p0(ptr) define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.4h { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.4h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.4h { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.4h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -1747,19 +1126,19 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2(ptr %A, ptr %ptr) { } define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld2.4h { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.4h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld2.4h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.4h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1770,18 +1149,18 @@ declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2.v4i16.p0(ptr) define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -1789,19 +1168,19 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2(ptr %A, ptr %ptr) { } define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1812,18 +1191,18 @@ declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0(ptr) define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -1831,19 +1210,19 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2(ptr %A, ptr %ptr) { } define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1854,18 +1233,18 @@ declare { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0(ptr) define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -1873,19 +1252,19 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2(ptr %A, ptr %ptr) { } define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld2.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld2.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1896,18 +1275,18 @@ declare { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2.v2i64.p0(ptr) define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1i64_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -1915,19 +1294,19 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2(ptr %A, ptr %ptr) { } define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1i64_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1938,18 +1317,18 @@ declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2.v1i64.p0(ptr) define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -1957,19 +1336,19 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2(ptr %A, ptr %ptr) { } define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -1980,18 +1359,18 @@ declare { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2.v4f32.p0(ptr) define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -1999,19 +1378,19 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2(ptr %A, ptr %ptr) { } define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2022,18 +1401,18 @@ declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2.v2f32.p0(ptr) define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -2041,19 +1420,19 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2(ptr %A, ptr %ptr) } define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld2.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld2.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2064,18 +1443,18 @@ declare { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2.v2f64.p0(ptr) define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1f64_post_imm_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -2083,19 +1462,19 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2(ptr %A, ptr %ptr) } define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1f64_post_reg_ld2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2106,18 +1485,18 @@ declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2.v1f64.p0(ptr) define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.16b { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.16b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.16b { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.16b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 48 store ptr %tmp, ptr %ptr @@ -2125,18 +1504,18 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3(ptr %A, ptr } define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.16b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.16b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.16b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.16b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2147,18 +1526,18 @@ declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3.v16i8.p0(ptr) define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.8b { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.8b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.8b { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.8b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 24 store ptr %tmp, ptr %ptr @@ -2166,18 +1545,18 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3(ptr %A, ptr %ptr } define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.8b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.8b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.8b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.8b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2188,18 +1567,18 @@ declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3.v8i8.p0(ptr) define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.8h { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.8h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.8h { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.8h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 24 store ptr %tmp, ptr %ptr @@ -2207,19 +1586,19 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3(ptr %A, ptr } define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld3.8h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.8h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld3.8h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.8h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2230,18 +1609,18 @@ declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3.v8i16.p0(ptr) define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.4h { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.4h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.4h { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.4h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 12 store ptr %tmp, ptr %ptr @@ -2249,19 +1628,19 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3(ptr %A, ptr } define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld3.4h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.4h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld3.4h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.4h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2272,18 +1651,18 @@ declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0(ptr) define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 12 store ptr %tmp, ptr %ptr @@ -2291,19 +1670,19 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3(ptr %A, ptr } define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2314,18 +1693,18 @@ declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0(ptr) define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -2333,19 +1712,19 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3(ptr %A, ptr } define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2356,18 +1735,18 @@ declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3.v2i32.p0(ptr) define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -2375,19 +1754,19 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3(ptr %A, ptr } define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld3.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld3.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2398,18 +1777,18 @@ declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3.v2i64.p0(ptr) define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1i64_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -2417,19 +1796,19 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3(ptr %A, ptr } define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1i64_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2440,18 +1819,18 @@ declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3.v1i64.p0(ptr) define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 12 store ptr %tmp, ptr %ptr @@ -2459,19 +1838,19 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3(ptr %A } define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2482,18 +1861,18 @@ declare { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3.v4f32.p define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -2501,19 +1880,19 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3(ptr %A } define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2524,18 +1903,18 @@ declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3.v2f32.p define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -2543,19 +1922,19 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3(ptr } define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld3.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld3.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2566,18 +1945,18 @@ declare { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3.v2f6 define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1f64_post_imm_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -2585,19 +1964,19 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3(ptr } define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1f64_post_reg_ld3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2608,18 +1987,18 @@ declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3.v1f6 define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 64 store ptr %tmp, ptr %ptr @@ -2627,18 +2006,18 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4(p } define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.16b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2649,18 +2028,18 @@ declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4.v1 define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 store ptr %tmp, ptr %ptr @@ -2668,18 +2047,18 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4(ptr %A } define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.8b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2690,18 +2069,18 @@ declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4.v8i8.p define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 32 store ptr %tmp, ptr %ptr @@ -2709,19 +2088,19 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4(p } define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.8h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2732,18 +2111,18 @@ declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4.v8 define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -2751,19 +2130,19 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4(p } define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.4h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2774,18 +2153,18 @@ declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4 define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -2793,19 +2172,19 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4(p } define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2816,18 +2195,18 @@ declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4.v4 define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -2835,19 +2214,19 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4(p } define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2858,18 +2237,18 @@ declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4.v2 define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -2877,19 +2256,19 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4(p } define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2900,18 +2279,18 @@ declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4.v2 define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1i64_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -2919,19 +2298,19 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4(p } define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1i64_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2942,18 +2321,18 @@ declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4.v1 define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -2961,19 +2340,19 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i } define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -2984,18 +2363,18 @@ declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neo define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -3003,19 +2382,19 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i } define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3026,18 +2405,18 @@ declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neo define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -3045,19 +2424,19 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po } define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3068,18 +2447,18 @@ declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64 define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1f64_post_imm_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -3087,19 +2466,19 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po } define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1f64_post_reg_ld4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3109,18 +2488,18 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4.v1f64.p0(ptr) define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.16b { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.16b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.16b { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.16b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 store ptr %tmp, ptr %ptr @@ -3128,18 +2507,18 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.16b { v0, v1 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.16b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.16b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.16b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3150,18 +2529,18 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x2.v16i8.p0(ptr) define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8b { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8b { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -3169,18 +2548,18 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8b { v0, v1 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3191,18 +2570,18 @@ declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x2.v8i8.p0(ptr) define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8h { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8h { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -3210,19 +2589,19 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.8h { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.8h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3233,18 +2612,18 @@ declare { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x2.v8i16.p0(ptr) define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4h { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4h { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -3252,19 +2631,19 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.4h { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.4h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3275,18 +2654,18 @@ declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x2.v4i16.p0(ptr) define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -3294,19 +2673,19 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3317,18 +2696,18 @@ declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x2.v4i32.p0(ptr) define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -3336,19 +2715,19 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3359,18 +2738,18 @@ declare { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x2.v2i32.p0(ptr) define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -3378,19 +2757,19 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3401,18 +2780,18 @@ declare { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x2.v2i64.p0(ptr) define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1i64_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -3420,19 +2799,19 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x2(ptr %A, ptr %ptr) { } define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1i64_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3443,18 +2822,18 @@ declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x2.v1i64.p0(ptr) define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -3462,19 +2841,19 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x2(ptr %A, ptr %ptr) } define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3485,18 +2864,18 @@ declare { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x2.v4f32.p0(ptr) define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -3504,19 +2883,19 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x2(ptr %A, ptr %ptr) } define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3527,18 +2906,18 @@ declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x2.v2f32.p0(ptr) define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -3546,19 +2925,19 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x2(ptr %A, ptr %pt } define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3569,18 +2948,18 @@ declare { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x2.v2f64.p0(ptr) define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x2(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1f64_post_imm_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -3588,19 +2967,19 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x2(ptr %A, ptr %pt } define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x2(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1f64_post_reg_ld1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x2 = tail call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3611,18 +2990,18 @@ declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x2.v1f64.p0(ptr) define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.16b { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.16b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.16b { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.16b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 48 store ptr %tmp, ptr %ptr @@ -3630,18 +3009,18 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x3(ptr %A, pt } define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.16b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.16b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.16b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.16b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3652,18 +3031,18 @@ declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x3.v16i8.p0(pt define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8b { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8b { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 24 store ptr %tmp, ptr %ptr @@ -3671,18 +3050,18 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x3(ptr %A, ptr %p } define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3693,18 +3072,18 @@ declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x3.v8i8.p0(ptr) define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8h { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8h { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 24 store ptr %tmp, ptr %ptr @@ -3712,19 +3091,19 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x3(ptr %A, pt } define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.8h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.8h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3735,18 +3114,18 @@ declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x3.v8i16.p0(pt define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4h { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4h { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 12 store ptr %tmp, ptr %ptr @@ -3754,19 +3133,19 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x3(ptr %A, pt } define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.4h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.4h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3777,18 +3156,18 @@ declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x3.v4i16.p0(pt define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 12 store ptr %tmp, ptr %ptr @@ -3796,19 +3175,19 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x3(ptr %A, pt } define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3819,18 +3198,18 @@ declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x3.v4i32.p0(pt define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -3838,19 +3217,19 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x3(ptr %A, pt } define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3861,18 +3240,18 @@ declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x3.v2i32.p0(pt define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -3880,19 +3259,19 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x3(ptr %A, pt } define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3903,18 +3282,18 @@ declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x3.v2i64.p0(pt define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1i64_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -3922,19 +3301,19 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x3(ptr %A, pt } define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1i64_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3945,18 +3324,18 @@ declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x3.v1i64.p0(pt define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 12 store ptr %tmp, ptr %ptr @@ -3964,19 +3343,19 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x3(ptr } define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -3987,18 +3366,18 @@ declare { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x3.v4f32 define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -4006,19 +3385,19 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x3(ptr } define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4029,18 +3408,18 @@ declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x3.v2f32 define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #48 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #48 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 6 store ptr %tmp, ptr %ptr @@ -4048,19 +3427,19 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x3(p } define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4071,18 +3450,18 @@ declare { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x3.v2 define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x3(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1f64_post_imm_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -4090,19 +3469,19 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x3(p } define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x3(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1f64_post_reg_ld1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x3 = tail call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4113,18 +3492,18 @@ declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x3.v1 define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 64 store ptr %tmp, ptr %ptr @@ -4132,18 +3511,18 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld1x4 } define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.16b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4154,18 +3533,18 @@ declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld1x4. define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 store ptr %tmp, ptr %ptr @@ -4173,18 +3552,18 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld1x4(ptr } define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4195,18 +3574,18 @@ declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld1x4.v8i8 define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 32 store ptr %tmp, ptr %ptr @@ -4214,19 +3593,19 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld1x4 } define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.8h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4237,18 +3616,18 @@ declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld1x4. define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -4256,19 +3635,19 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld1x4 } define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4279,18 +3658,18 @@ declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld1x4. define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -4298,19 +3677,19 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld1x4 } define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4321,18 +3700,18 @@ declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld1x4. define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -4340,19 +3719,19 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld1x4 } define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4363,18 +3742,18 @@ declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld1x4. define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -4382,19 +3761,19 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld1x4 } define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4405,18 +3784,18 @@ declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld1x4. define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1i64_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -4424,19 +3803,19 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld1x4 } define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1i64_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4447,18 +3826,18 @@ declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld1x4. define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 16 store ptr %tmp, ptr %ptr @@ -4466,19 +3845,19 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i } define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld1x4.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4489,18 +3868,18 @@ declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neo define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -4508,19 +3887,19 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i } define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld1x4.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4531,18 +3910,18 @@ declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neo define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #64 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #64 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 8 store ptr %tmp, ptr %ptr @@ -4550,19 +3929,19 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po } define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld1x4.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4573,18 +3952,18 @@ declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64 define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld1x4(ptr %A, ptr %ptr) { -; SDAG-LABEL: test_v1f64_post_imm_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -4592,19 +3971,19 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po } define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld1x4(ptr %A, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v1f64_post_reg_ld1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld1x4 = tail call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld1x4.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4615,18 +3994,18 @@ declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.16b { v0, v1 }, [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.16b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.16b { v0, v1 }, [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.16b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4634,18 +4013,18 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.16b { v0, v1 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.16b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.16b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.16b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4656,18 +4035,18 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2r.v16i8.p0(ptr) nounwind define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.8b { v0, v1 }, [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.8b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.8b { v0, v1 }, [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.8b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4675,18 +4054,18 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2r(ptr %A, ptr %ptr) nounwin } define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.8b { v0, v1 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.8b { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.8b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.8b { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4697,18 +4076,18 @@ declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2r.v8i8.p0(ptr) nounwind rea define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.8h { v0, v1 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.8h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.8h { v0, v1 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.8h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4716,19 +4095,19 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld2r.8h { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.8h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld2r.8h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.8h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4739,18 +4118,18 @@ declare { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2r.v8i16.p0(ptr) nounwind define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.4h { v0, v1 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.4h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.4h { v0, v1 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.4h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4758,19 +4137,19 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld2r.4h { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.4h { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld2r.4h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.4h { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4781,18 +4160,18 @@ declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2r.v4i16.p0(ptr) nounwind define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.4s { v0, v1 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.4s { v0, v1 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4800,19 +4179,19 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2r.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2r.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4822,18 +4201,18 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2r(ptr %A, ptr %ptr, i64 declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2r.v4i32.p0(ptr) nounwind readonly define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.2s { v0, v1 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.2s { v0, v1 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4841,19 +4220,19 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2r.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2r.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4864,18 +4243,18 @@ declare { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2r.v2i32.p0(ptr) nounwind define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.2d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.2d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4883,19 +4262,19 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld2r.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld2r.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4905,18 +4284,18 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2r(ptr %A, ptr %ptr, i64 declare { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2r.v2i64.p0(ptr) nounwind readonly define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4924,19 +4303,19 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2r(ptr %A, ptr %ptr) noun } define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld2r.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld2r.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4947,18 +4326,18 @@ declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2r.v1i64.p0(ptr) nounwind define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.4s { v0, v1 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.4s { v0, v1 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -4966,19 +4345,19 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2r(ptr %A, ptr %ptr) } define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2r.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.4s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2r.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.4s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -4988,18 +4367,18 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2r(ptr %A, ptr %ptr, declare { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2r.v4f32.p0(ptr) nounwind readonly define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.2s { v0, v1 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.2s { v0, v1 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -5007,19 +4386,19 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2r(ptr %A, ptr %ptr) } define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld2r.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2s { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld2r.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2s { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5030,18 +4409,18 @@ declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2r.v2f32.p0(ptr) nounw define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.2d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.2d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -5049,19 +4428,19 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2r(ptr %A, ptr %ptr } define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld2r.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.2d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld2r.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.2d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5071,18 +4450,18 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2r(ptr %A, ptr %ptr declare { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2r.v2f64.p0(ptr) nounwind readonly define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld2r.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld2r.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -5090,19 +4469,19 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2r(ptr %A, ptr %ptr } define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_ld2r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld2r.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld2r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld2r.1d { v0, v1 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld2r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld2r.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld2r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld2r.1d { v0, v1 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5113,18 +4492,18 @@ declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2r.v1f64.p0(ptr) nou define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.16b { v0, v1, v2 }, [x0], #3 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.16b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.16b { v0, v1, v2 }, [x0], #3 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.16b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5132,18 +4511,18 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3r(ptr %A, ptr } define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.16b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.16b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.16b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.16b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5154,18 +4533,18 @@ declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3r.v16i8.p0(ptr define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.8b { v0, v1, v2 }, [x0], #3 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.8b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.8b { v0, v1, v2 }, [x0], #3 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.8b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5173,18 +4552,18 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3r(ptr %A, ptr %pt } define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.8b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.8b { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.8b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.8b { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5195,18 +4574,18 @@ declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3r.v8i8.p0(ptr) no define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.8h { v0, v1, v2 }, [x0], #6 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.8h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #6 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.8h { v0, v1, v2 }, [x0], #6 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.8h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #6 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5214,19 +4593,19 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3r(ptr %A, ptr } define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld3r.8h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.8h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld3r.8h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.8h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5237,18 +4616,18 @@ declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3r.v8i16.p0(ptr define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.4h { v0, v1, v2 }, [x0], #6 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.4h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #6 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.4h { v0, v1, v2 }, [x0], #6 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.4h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #6 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5256,19 +4635,19 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3r(ptr %A, ptr } define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld3r.4h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.4h { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld3r.4h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.4h { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5279,18 +4658,18 @@ declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3r.v4i16.p0(ptr define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.4s { v0, v1, v2 }, [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.4s { v0, v1, v2 }, [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5298,19 +4677,19 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3r(ptr %A, ptr } define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3r.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3r.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5320,18 +4699,18 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3r(ptr %A, ptr declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3r.v4i32.p0(ptr) nounwind readonly define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.2s { v0, v1, v2 }, [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.2s { v0, v1, v2 }, [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5339,19 +4718,19 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3r(ptr %A, ptr } define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3r.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3r.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5362,18 +4741,18 @@ declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3r.v2i32.p0(ptr define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.2d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.2d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5381,19 +4760,19 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3r(ptr %A, ptr } define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld3r.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld3r.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5403,18 +4782,18 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3r(ptr %A, ptr declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3r.v2i64.p0(ptr) nounwind readonly define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5422,19 +4801,19 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3r(ptr %A, ptr } define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld3r.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld3r.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5445,18 +4824,18 @@ declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3r.v1i64.p0(ptr define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.4s { v0, v1, v2 }, [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.4s { v0, v1, v2 }, [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5464,19 +4843,19 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3r(ptr % } define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3r.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.4s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3r.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.4s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5486,18 +4865,18 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3r(ptr % declare { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3r.v4f32.p0(ptr) nounwind readonly define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.2s { v0, v1, v2 }, [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.2s { v0, v1, v2 }, [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5505,19 +4884,19 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3r(ptr % } define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld3r.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2s { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld3r.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2s { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5528,18 +4907,18 @@ declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3r.v2f32. define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.2d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.2d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5547,19 +4926,19 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3r(pt } define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld3r.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.2d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld3r.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.2d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5569,18 +4948,18 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3r(pt declare { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3r.v2f64.p0(ptr) nounwind readonly define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld3r.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld3r.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -5588,19 +4967,19 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3r(pt } define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_ld3r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld3r.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld3r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld3r.1d { v0, v1, v2 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld3r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld3r.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld3r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld3r.1d { v0, v1, v2 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5611,18 +4990,18 @@ declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3r.v1f define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5630,18 +5009,18 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4r( } define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.16b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v16i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5652,18 +5031,18 @@ declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4r.v define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5671,18 +5050,18 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4r(ptr % } define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.8b { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8.p0(ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5693,18 +5072,18 @@ declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4r.v8i8. define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5712,19 +5091,19 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4r( } define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.8h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v8i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5735,18 +5114,18 @@ declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4r.v define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5754,19 +5133,19 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4r( } define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.4h { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v4i16.p0(ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5777,18 +5156,18 @@ declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4r.v define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5796,19 +5175,19 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4r( } define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5818,18 +5197,18 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4r( declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4r.v4i32.p0(ptr) nounwind readonly define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5837,19 +5216,19 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4r( } define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v2i32.p0(ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5860,18 +5239,18 @@ declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4r.v define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5879,19 +5258,19 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4r( } define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5901,18 +5280,18 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4r( declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4r.v2i64.p0(ptr) nounwind readonly define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5920,19 +5299,19 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4r( } define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v1i64.p0(ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5943,18 +5322,18 @@ declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4r.v define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -5962,19 +5341,19 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i } define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.4s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -5984,18 +5363,18 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_r declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4r.v4f32.p0(ptr) nounwind readonly define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -6003,19 +5382,19 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i } define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2s { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4r.v2f32.p0(ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6026,18 +5405,18 @@ declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neo define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -6045,19 +5424,19 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po } define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.2d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6067,18 +5446,18 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4r.v2f64.p0(ptr) nounwind readonly define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld4r(ptr %A, ptr %ptr) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4r.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -6086,19 +5465,19 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po } define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld4r(ptr %A, ptr %ptr, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_ld4r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld4r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld4r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld4r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld4r.1d { v0, v1, v2, v3 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4r.v1f64.p0(ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6109,22 +5488,22 @@ declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64 define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.b { v0, v1 }[0], [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.b { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.b { v0, v1 }[0], [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.b { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6132,22 +5511,22 @@ define { <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <16 x i8> %B, <16 x i8> %C) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.b { v0, v1 }[0], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.b { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.b { v0, v1 }[0], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.b { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6158,22 +5537,22 @@ declare { <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld2lane.v16i8.p0(<16 x i8>, define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.b { v0, v1 }[0], [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.b { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.b { v0, v1 }[0], [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.b { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6181,22 +5560,22 @@ define { <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld2lane(ptr %A, ptr %ptr, <8 x } define { <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <8 x i8> %B, <8 x i8> %C) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.b { v0, v1 }[0], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.b { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.b { v0, v1 }[0], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.b { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6207,22 +5586,22 @@ declare { <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld2lane.v8i8.p0(<8 x i8>, <8 x define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.h { v0, v1 }[0], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.h { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.h { v0, v1 }[0], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.h { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6230,23 +5609,23 @@ define { <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <8 x i16> %B, <8 x i16> %C) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.h { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.h { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.h { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.h { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6257,22 +5636,22 @@ declare { <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld2lane.v8i16.p0(<8 x i16>, define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.h { v0, v1 }[0], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.h { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.h { v0, v1 }[0], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.h { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6280,23 +5659,23 @@ define { <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <4 x i16> %B, <4 x i16> %C) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.h { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.h { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.h { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.h { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6307,22 +5686,22 @@ declare { <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld2lane.v4i16.p0(<4 x i16>, define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6330,23 +5709,23 @@ define { <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <4 x i32> %B, <4 x i32> %C) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6357,22 +5736,22 @@ declare { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0(<4 x i32>, define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6380,23 +5759,23 @@ define { <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <2 x i32> %B, <2 x i32> %C) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6407,22 +5786,22 @@ declare { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2lane.v2i32.p0(<2 x i32>, define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6430,23 +5809,23 @@ define { <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <2 x i64> %B, <2 x i64> %C) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6457,22 +5836,22 @@ declare { <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld2lane.v2i64.p0(<2 x i64>, define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6480,23 +5859,23 @@ define { <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld2lane(ptr %A, ptr %ptr, < } define { <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <1 x i64> %B, <1 x i64> %C) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6507,22 +5886,22 @@ declare { <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld2lane.v1i64.p0(<1 x i64>, define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0(<4 x float> %B, <4 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6530,23 +5909,23 @@ define { <4 x float>, <4 x float> } @test_v4f32_post_imm_ld2lane(ptr %A, ptr %pt } define { <4 x float>, <4 x float> } @test_v4f32_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <4 x float> %B, <4 x float> %C) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0(<4 x float> %B, <4 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6557,22 +5936,22 @@ declare { <4 x float>, <4 x float> } @llvm.aarch64.neon.ld2lane.v4f32.p0(<4 x fl define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x float> %B, <2 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6580,23 +5959,23 @@ define { <2 x float>, <2 x float> } @test_v2f32_post_imm_ld2lane(ptr %A, ptr %pt } define { <2 x float>, <2 x float> } @test_v2f32_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <2 x float> %B, <2 x float> %C) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.s { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.s { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x float> %B, <2 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6607,22 +5986,22 @@ declare { <2 x float>, <2 x float> } @llvm.aarch64.neon.ld2lane.v2f32.p0(<2 x fl define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0(<2 x double> %B, <2 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6630,23 +6009,23 @@ define { <2 x double>, <2 x double> } @test_v2f64_post_imm_ld2lane(ptr %A, ptr % } define { <2 x double>, <2 x double> } @test_v2f64_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <2 x double> %B, <2 x double> %C) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0(<2 x double> %B, <2 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6657,22 +6036,22 @@ declare { <2 x double>, <2 x double> } @llvm.aarch64.neon.ld2lane.v2f64.p0(<2 x define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0(<1 x double> %B, <1 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i32 2 store ptr %tmp, ptr %ptr @@ -6680,23 +6059,23 @@ define { <1 x double>, <1 x double> } @test_v1f64_post_imm_ld2lane(ptr %A, ptr % } define { <1 x double>, <1 x double> } @test_v1f64_post_reg_ld2lane(ptr %A, ptr %ptr, i64 %inc, <1 x double> %B, <1 x double> %C) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_ld2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ld2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ld2.d { v0, v1 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ld2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ld2.d { v0, v1 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld2 = call { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0(<1 x double> %B, <1 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6707,24 +6086,24 @@ declare { <1 x double>, <1 x double> } @llvm.aarch64.neon.ld2lane.v1f64.p0(<1 x define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.b { v0, v1, v2 }[0], [x0], #3 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.b { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.b { v0, v1, v2 }[0], [x0], #3 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.b { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -6732,24 +6111,24 @@ define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld3lane(ptr %A, } define { <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.b { v0, v1, v2 }[0], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.b { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.b { v0, v1, v2 }[0], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.b { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6760,24 +6139,24 @@ declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld3lane.v16i8.p0( define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.b { v0, v1, v2 }[0], [x0], #3 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.b { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.b { v0, v1, v2 }[0], [x0], #3 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.b { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -6785,24 +6164,24 @@ define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld3lane(ptr %A, ptr } define { <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.b { v0, v1, v2 }[0], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.b { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.b { v0, v1, v2 }[0], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.b { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6813,24 +6192,24 @@ declare { <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld3lane.v8i8.p0(<8 x define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.h { v0, v1, v2 }[0], [x0], #6 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #6 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.h { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.h { v0, v1, v2 }[0], [x0], #6 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #6 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.h { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -6838,25 +6217,25 @@ define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld3lane(ptr %A, } define { <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.h { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.h { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.h { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.h { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6867,24 +6246,24 @@ declare { <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld3lane.v8i16.p0( define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.h { v0, v1, v2 }[0], [x0], #6 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #6 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.h { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.h { v0, v1, v2 }[0], [x0], #6 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #6 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.h { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -6892,25 +6271,25 @@ define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld3lane(ptr %A, } define { <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.h { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.h { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.h { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.h { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6921,24 +6300,24 @@ declare { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3lane.v4i16.p0( define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -6946,25 +6325,25 @@ define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld3lane(ptr %A, } define { <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -6975,24 +6354,24 @@ declare { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0( define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7000,25 +6379,25 @@ define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld3lane(ptr %A, } define { <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7029,24 +6408,24 @@ declare { <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld3lane.v2i32.p0( define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7054,25 +6433,25 @@ define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld3lane(ptr %A, } define { <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7083,24 +6462,24 @@ declare { <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld3lane.v2i64.p0( define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7108,25 +6487,25 @@ define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld3lane(ptr %A, } define { <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7137,24 +6516,24 @@ declare { <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld3lane.v1i64.p0( define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7162,25 +6541,25 @@ define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld3lane(pt } define { <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7191,24 +6570,24 @@ declare { <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld3lane.v4f define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #12 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7216,25 +6595,25 @@ define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld3lane(pt } define { <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.s { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.s { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7245,24 +6624,24 @@ declare { <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld3lane.v2f define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7270,25 +6649,25 @@ define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld3lane } define { <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7299,24 +6678,24 @@ declare { <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld3lane. define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i32 3 store ptr %tmp, ptr %ptr @@ -7324,25 +6703,25 @@ define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld3lane } define { <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld3lane(ptr %A, ptr %ptr, i64 %inc, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_ld3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ld3.d { v0, v1, v2 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ld3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ld3.d { v0, v1, v2 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld3 = call { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7353,26 +6732,26 @@ declare { <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld3lane. define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7380,26 +6759,26 @@ define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_imm_ld4la } define { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @test_v16i8_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7410,26 +6789,26 @@ declare { <16 x i8>, <16 x i8>, <16 x i8>, <16 x i8> } @llvm.aarch64.neon.ld4lan define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #4 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7437,26 +6816,26 @@ define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_imm_ld4lane(pt } define { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @test_v8i8_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.b { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7467,26 +6846,26 @@ declare { <8 x i8>, <8 x i8>, <8 x i8>, <8 x i8> } @llvm.aarch64.neon.ld4lane.v8 define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7494,27 +6873,27 @@ define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_imm_ld4la } define { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @test_v8i16_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7525,26 +6904,26 @@ declare { <8 x i16>, <8 x i16>, <8 x i16>, <8 x i16> } @llvm.aarch64.neon.ld4lan define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #8 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7552,27 +6931,27 @@ define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_imm_ld4la } define { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @test_v4i16_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.h { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7583,26 +6962,26 @@ declare { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4lan define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7610,27 +6989,27 @@ define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_imm_ld4la } define { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @test_v4i32_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7641,26 +7020,26 @@ declare { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lan define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7668,27 +7047,27 @@ define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_imm_ld4la } define { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @test_v2i32_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7699,26 +7078,26 @@ declare { <2 x i32>, <2 x i32>, <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld4lan define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7726,27 +7105,27 @@ define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_imm_ld4la } define { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @test_v2i64_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7757,26 +7136,26 @@ declare { <2 x i64>, <2 x i64>, <2 x i64>, <2 x i64> } @llvm.aarch64.neon.ld4lan define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7784,27 +7163,27 @@ define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_imm_ld4la } define { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @test_v1i64_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7815,26 +7194,26 @@ declare { <1 x i64>, <1 x i64>, <1 x i64>, <1 x i64> } @llvm.aarch64.neon.ld4lan define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_imm_ld4lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7842,27 +7221,27 @@ define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_i } define { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @test_v4f32_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neon.ld4lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7873,26 +7252,26 @@ declare { <4 x float>, <4 x float>, <4 x float>, <4 x float> } @llvm.aarch64.neo define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_imm_ld4lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7900,27 +7279,27 @@ define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_i } define { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @test_v2f32_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.s { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neon.ld4lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7931,26 +7310,26 @@ declare { <2 x float>, <2 x float>, <2 x float>, <2 x float> } @llvm.aarch64.neo define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_imm_ld4lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -7958,27 +7337,27 @@ define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_po } define { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @test_v2f64_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64.neon.ld4lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -7989,26 +7368,26 @@ declare { <2 x double>, <2 x double>, <2 x double>, <2 x double> } @llvm.aarch64 define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_imm_ld4lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i32 4 store ptr %tmp, ptr %ptr @@ -8016,27 +7395,27 @@ define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_po } define { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @test_v1f64_post_reg_ld4lane(ptr %A, ptr %ptr, i64 %inc, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_ld4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_ld4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_ld4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_ld4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ld4.d { v0, v1, v2, v3 }[0], [x0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %ld4 = call { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64.neon.ld4lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc store ptr %tmp, ptr %ptr @@ -8047,42 +7426,42 @@ declare { <1 x double>, <1 x double>, <1 x double>, <1 x double> } @llvm.aarch64 define ptr @test_v16i8_post_imm_st2(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.16b { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.16b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.16b { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.16b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> %B, <16 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 ret ptr %tmp } define ptr @test_v16i8_post_reg_st2(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.16b { v0, v1 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.16b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.16b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.16b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8> %B, <16 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -8092,42 +7471,42 @@ declare void @llvm.aarch64.neon.st2.v16i8.p0(<16 x i8>, <16 x i8>, ptr) define ptr @test_v8i8_post_imm_st2(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.8b { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.8b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.8b { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.8b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %B, <8 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v8i8_post_reg_st2(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.8b { v0, v1 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.8b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.8b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.8b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8> %B, <8 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -8137,43 +7516,43 @@ declare void @llvm.aarch64.neon.st2.v8i8.p0(<8 x i8>, <8 x i8>, ptr) define ptr @test_v8i16_post_imm_st2(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.8h { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.8h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.8h { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.8h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> %B, <8 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v8i16_post_reg_st2(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.8h { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.8h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.8h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.8h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16> %B, <8 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -8183,43 +7562,43 @@ declare void @llvm.aarch64.neon.st2.v8i16.p0(<8 x i16>, <8 x i16>, ptr) define ptr @test_v4i16_post_imm_st2(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.4h { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.4h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.4h { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.4h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> %B, <4 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v4i16_post_reg_st2(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.4h { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.4h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.4h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.4h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16> %B, <4 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -8229,43 +7608,43 @@ declare void @llvm.aarch64.neon.st2.v4i16.p0(<4 x i16>, <4 x i16>, ptr) define ptr @test_v4i32_post_imm_st2(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %B, <4 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v4i32_post_reg_st2(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32> %B, <4 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -8275,43 +7654,43 @@ declare void @llvm.aarch64.neon.st2.v4i32.p0(<4 x i32>, <4 x i32>, ptr) define ptr @test_v2i32_post_imm_st2(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> %B, <2 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v2i32_post_reg_st2(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32> %B, <2 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -8321,43 +7700,43 @@ declare void @llvm.aarch64.neon.st2.v2i32.p0(<2 x i32>, <2 x i32>, ptr) define ptr @test_v2i64_post_imm_st2(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> %B, <2 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v2i64_post_reg_st2(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64> %B, <2 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -8367,43 +7746,43 @@ declare void @llvm.aarch64.neon.st2.v2i64.p0(<2 x i64>, <2 x i64>, ptr) define ptr @test_v1i64_post_imm_st2(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> %B, <1 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v1i64_post_reg_st2(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64> %B, <1 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -8413,43 +7792,43 @@ declare void @llvm.aarch64.neon.st2.v1i64.p0(<1 x i64>, <1 x i64>, ptr) define ptr @test_v4f32_post_imm_st2(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> %B, <4 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v4f32_post_reg_st2(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float> %B, <4 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -8459,43 +7838,43 @@ declare void @llvm.aarch64.neon.st2.v4f32.p0(<4 x float>, <4 x float>, ptr) define ptr @test_v2f32_post_imm_st2(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2f32.p0(<2 x float> %B, <2 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v2f32_post_reg_st2(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st2.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st2.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st2.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st2.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2f32.p0(<2 x float> %B, <2 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -8505,43 +7884,43 @@ declare void @llvm.aarch64.neon.st2.v2f32.p0(<2 x float>, <2 x float>, ptr) define ptr @test_v2f64_post_imm_st2(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2f64.p0(<2 x double> %B, <2 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v2f64_post_reg_st2(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v2f64.p0(<2 x double> %B, <2 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -8551,43 +7930,43 @@ declare void @llvm.aarch64.neon.st2.v2f64.p0(<2 x double>, <2 x double>, ptr) define ptr @test_v1f64_post_imm_st2(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v1f64.p0(<1 x double> %B, <1 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v1f64_post_reg_st2(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2.v1f64.p0(<1 x double> %B, <1 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -8597,46 +7976,46 @@ declare void @llvm.aarch64.neon.st2.v1f64.p0(<1 x double>, <1 x double>, ptr) define ptr @test_v16i8_post_imm_st3(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.16b { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.16b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.16b { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.16b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i32 48 ret ptr %tmp } define ptr @test_v16i8_post_reg_st3(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.16b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.16b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.16b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.16b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -8646,46 +8025,46 @@ declare void @llvm.aarch64.neon.st3.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, pt define ptr @test_v8i8_post_imm_st3(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.8b { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.8b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.8b { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.8b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i32 24 ret ptr %tmp } define ptr @test_v8i8_post_reg_st3(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.8b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.8b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.8b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.8b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -8695,47 +8074,47 @@ declare void @llvm.aarch64.neon.st3.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, ptr) define ptr @test_v8i16_post_imm_st3(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.8h { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.8h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.8h { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.8h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i32 24 ret ptr %tmp } define ptr @test_v8i16_post_reg_st3(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.8h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.8h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.8h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.8h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -8745,47 +8124,47 @@ declare void @llvm.aarch64.neon.st3.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, pt define ptr @test_v4i16_post_imm_st3(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.4h { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.4h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.4h { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.4h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i32 12 ret ptr %tmp } define ptr @test_v4i16_post_reg_st3(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.4h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.4h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.4h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.4h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -8795,47 +8174,47 @@ declare void @llvm.aarch64.neon.st3.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, pt define ptr @test_v4i32_post_imm_st3(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i32 12 ret ptr %tmp } define ptr @test_v4i32_post_reg_st3(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -8845,47 +8224,47 @@ declare void @llvm.aarch64.neon.st3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, pt define ptr @test_v2i32_post_imm_st3(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i32 6 ret ptr %tmp } define ptr @test_v2i32_post_reg_st3(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -8895,47 +8274,47 @@ declare void @llvm.aarch64.neon.st3.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, pt define ptr @test_v2i64_post_imm_st3(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 6 ret ptr %tmp } define ptr @test_v2i64_post_reg_st3(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -8945,47 +8324,47 @@ declare void @llvm.aarch64.neon.st3.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, pt define ptr @test_v1i64_post_imm_st3(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v1i64_post_reg_st3(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -8995,47 +8374,47 @@ declare void @llvm.aarch64.neon.st3.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, pt define ptr @test_v4f32_post_imm_st3(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i32 12 ret ptr %tmp } define ptr @test_v4f32_post_reg_st3(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -9045,47 +8424,47 @@ declare void @llvm.aarch64.neon.st3.v4f32.p0(<4 x float>, <4 x float>, <4 x floa define ptr @test_v2f32_post_imm_st3(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i32 6 ret ptr %tmp } define ptr @test_v2f32_post_reg_st3(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st3.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st3.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st3.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st3.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -9095,47 +8474,47 @@ declare void @llvm.aarch64.neon.st3.v2f32.p0(<2 x float>, <2 x float>, <2 x floa define ptr @test_v2f64_post_imm_st3(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 6 ret ptr %tmp } define ptr @test_v2f64_post_reg_st3(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -9145,47 +8524,47 @@ declare void @llvm.aarch64.neon.st3.v2f64.p0(<2 x double>, <2 x double>, <2 x do define ptr @test_v1f64_post_imm_st3(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v1f64_post_reg_st3(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -9195,50 +8574,50 @@ declare void @llvm.aarch64.neon.st3.v1f64.p0(<1 x double>, <1 x double>, <1 x do define ptr @test_v16i8_post_imm_st4(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.16b { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.16b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.16b { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.16b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i32 64 ret ptr %tmp } define ptr @test_v16i8_post_reg_st4(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.16b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.16b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.16b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.16b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -9248,50 +8627,50 @@ declare void @llvm.aarch64.neon.st4.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, <1 define ptr @test_v8i8_post_imm_st4(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.8b { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.8b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.8b { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.8b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 ret ptr %tmp } define ptr @test_v8i8_post_reg_st4(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.8b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.8b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.8b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.8b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -9301,51 +8680,51 @@ declare void @llvm.aarch64.neon.st4.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, <8 x i define ptr @test_v8i16_post_imm_st4(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.8h { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.8h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.8h { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.8h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i32 32 ret ptr %tmp } define ptr @test_v8i16_post_reg_st4(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.8h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.8h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.8h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.8h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -9355,51 +8734,51 @@ declare void @llvm.aarch64.neon.st4.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, <8 define ptr @test_v4i16_post_imm_st4(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.4h { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.4h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.4h { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.4h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v4i16_post_reg_st4(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.4h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.4h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.4h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.4h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -9409,51 +8788,51 @@ declare void @llvm.aarch64.neon.st4.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>,<4 define ptr @test_v4i32_post_imm_st4(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v4i32_post_reg_st4(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -9463,51 +8842,51 @@ declare void @llvm.aarch64.neon.st4.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>,<4 define ptr @test_v2i32_post_imm_st4(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v2i32_post_reg_st4(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -9517,51 +8896,51 @@ declare void @llvm.aarch64.neon.st4.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, <2 define ptr @test_v2i64_post_imm_st4(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 8 ret ptr %tmp } define ptr @test_v2i64_post_reg_st4(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -9571,51 +8950,51 @@ declare void @llvm.aarch64.neon.st4.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>,<2 define ptr @test_v1i64_post_imm_st4(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v1i64_post_reg_st4(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -9625,51 +9004,51 @@ declare void @llvm.aarch64.neon.st4.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>,<1 define ptr @test_v4f32_post_imm_st4(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v4f32_post_reg_st4(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -9679,51 +9058,51 @@ declare void @llvm.aarch64.neon.st4.v4f32.p0(<4 x float>, <4 x float>, <4 x floa define ptr @test_v2f32_post_imm_st4(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v2f32_post_reg_st4(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st4.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st4.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -9733,51 +9112,51 @@ declare void @llvm.aarch64.neon.st4.v2f32.p0(<2 x float>, <2 x float>, <2 x floa define ptr @test_v2f64_post_imm_st4(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 8 ret ptr %tmp } define ptr @test_v2f64_post_reg_st4(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -9787,51 +9166,51 @@ declare void @llvm.aarch64.neon.st4.v2f64.p0(<2 x double>, <2 x double>, <2 x do define ptr @test_v1f64_post_imm_st4(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v1f64_post_reg_st4(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -9841,42 +9220,42 @@ declare void @llvm.aarch64.neon.st4.v1f64.p0(<1 x double>, <1 x double>, <1 x do define ptr @test_v16i8_post_imm_st1x2(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.16b { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.16b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.16b { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.16b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> %B, <16 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 ret ptr %tmp } define ptr @test_v16i8_post_reg_st1x2(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.16b { v0, v1 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.16b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.16b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.16b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8> %B, <16 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -9886,42 +9265,42 @@ declare void @llvm.aarch64.neon.st1x2.v16i8.p0(<16 x i8>, <16 x i8>, ptr) define ptr @test_v8i8_post_imm_st1x2(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.8b { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.8b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.8b { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.8b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> %B, <8 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v8i8_post_reg_st1x2(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.8b { v0, v1 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.8b { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.8b { v0, v1 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.8b { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8> %B, <8 x i8> %C, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -9931,43 +9310,43 @@ declare void @llvm.aarch64.neon.st1x2.v8i8.p0(<8 x i8>, <8 x i8>, ptr) define ptr @test_v8i16_post_imm_st1x2(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.8h { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.8h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.8h { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.8h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> %B, <8 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v8i16_post_reg_st1x2(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.8h { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.8h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.8h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.8h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16> %B, <8 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -9977,43 +9356,43 @@ declare void @llvm.aarch64.neon.st1x2.v8i16.p0(<8 x i16>, <8 x i16>, ptr) define ptr @test_v4i16_post_imm_st1x2(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.4h { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.4h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.4h { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.4h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> %B, <4 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v4i16_post_reg_st1x2(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.4h { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.4h { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.4h { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.4h { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16> %B, <4 x i16> %C, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -10023,43 +9402,43 @@ declare void @llvm.aarch64.neon.st1x2.v4i16.p0(<4 x i16>, <4 x i16>, ptr) define ptr @test_v4i32_post_imm_st1x2(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32> %B, <4 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v4i32_post_reg_st1x2(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32> %B, <4 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -10069,43 +9448,43 @@ declare void @llvm.aarch64.neon.st1x2.v4i32.p0(<4 x i32>, <4 x i32>, ptr) define ptr @test_v2i32_post_imm_st1x2(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32> %B, <2 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v2i32_post_reg_st1x2(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32> %B, <2 x i32> %C, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -10115,43 +9494,43 @@ declare void @llvm.aarch64.neon.st1x2.v2i32.p0(<2 x i32>, <2 x i32>, ptr) define ptr @test_v2i64_post_imm_st1x2(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> %B, <2 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v2i64_post_reg_st1x2(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64> %B, <2 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -10161,43 +9540,43 @@ declare void @llvm.aarch64.neon.st1x2.v2i64.p0(<2 x i64>, <2 x i64>, ptr) define ptr @test_v1i64_post_imm_st1x2(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> %B, <1 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v1i64_post_reg_st1x2(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64> %B, <1 x i64> %C, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -10207,43 +9586,43 @@ declare void @llvm.aarch64.neon.st1x2.v1i64.p0(<1 x i64>, <1 x i64>, ptr) define ptr @test_v4f32_post_imm_st1x2(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.4s { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.4s { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float> %B, <4 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v4f32_post_reg_st1x2(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.4s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.4s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.4s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.4s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float> %B, <4 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -10253,43 +9632,43 @@ declare void @llvm.aarch64.neon.st1x2.v4f32.p0(<4 x float>, <4 x float>, ptr) define ptr @test_v2f32_post_imm_st1x2(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.2s { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.2s { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float> %B, <2 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v2f32_post_reg_st1x2(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.2s { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.2s { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.2s { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.2s { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float> %B, <2 x float> %C, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -10299,43 +9678,43 @@ declare void @llvm.aarch64.neon.st1x2.v2f32.p0(<2 x float>, <2 x float>, ptr) define ptr @test_v2f64_post_imm_st1x2(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.2d { v0, v1 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.2d { v0, v1 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double> %B, <2 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v2f64_post_reg_st1x2(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st1.2d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st1.2d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st1.2d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st1.2d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double> %B, <2 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -10345,43 +9724,43 @@ declare void @llvm.aarch64.neon.st1x2.v2f64.p0(<2 x double>, <2 x double>, ptr) define ptr @test_v1f64_post_imm_st1x2(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double> %B, <1 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v1f64_post_reg_st1x2(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st1x2: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; SDAG-NEXT: st1.1d { v0, v1 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st1x2: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 -; CHECK-GISEL-NEXT: st1.1d { v0, v1 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st1x2: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-SD-NEXT: st1.1d { v0, v1 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st1x2: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1 def $d0_d1 +; CHECK-GI-NEXT: st1.1d { v0, v1 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double> %B, <1 x double> %C, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -10391,46 +9770,46 @@ declare void @llvm.aarch64.neon.st1x2.v1f64.p0(<1 x double>, <1 x double>, ptr) define ptr @test_v16i8_post_imm_st1x3(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.16b { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.16b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.16b { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.16b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i32 48 ret ptr %tmp } define ptr @test_v16i8_post_reg_st1x3(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.16b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.16b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.16b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.16b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -10440,46 +9819,46 @@ declare void @llvm.aarch64.neon.st1x3.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, define ptr @test_v8i8_post_imm_st1x3(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.8b { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.8b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.8b { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.8b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i32 24 ret ptr %tmp } define ptr @test_v8i8_post_reg_st1x3(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.8b { v0, v1, v2 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.8b { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.8b { v0, v1, v2 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.8b { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -10489,47 +9868,47 @@ declare void @llvm.aarch64.neon.st1x3.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, ptr) define ptr @test_v8i16_post_imm_st1x3(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.8h { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.8h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.8h { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.8h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i32 24 ret ptr %tmp } define ptr @test_v8i16_post_reg_st1x3(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.8h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.8h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.8h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.8h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -10539,47 +9918,47 @@ declare void @llvm.aarch64.neon.st1x3.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, define ptr @test_v4i16_post_imm_st1x3(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.4h { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.4h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.4h { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.4h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i32 12 ret ptr %tmp } define ptr @test_v4i16_post_reg_st1x3(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.4h { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.4h { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.4h { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.4h { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -10589,47 +9968,47 @@ declare void @llvm.aarch64.neon.st1x3.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>, define ptr @test_v4i32_post_imm_st1x3(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i32 12 ret ptr %tmp } define ptr @test_v4i32_post_reg_st1x3(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -10639,47 +10018,47 @@ declare void @llvm.aarch64.neon.st1x3.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>, define ptr @test_v2i32_post_imm_st1x3(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i32 6 ret ptr %tmp } define ptr @test_v2i32_post_reg_st1x3(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -10689,47 +10068,47 @@ declare void @llvm.aarch64.neon.st1x3.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, define ptr @test_v2i64_post_imm_st1x3(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 6 ret ptr %tmp } define ptr @test_v2i64_post_reg_st1x3(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -10739,47 +10118,47 @@ declare void @llvm.aarch64.neon.st1x3.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>, define ptr @test_v1i64_post_imm_st1x3(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v1i64_post_reg_st1x3(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -10789,47 +10168,47 @@ declare void @llvm.aarch64.neon.st1x3.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>, define ptr @test_v4f32_post_imm_st1x3(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.4s { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i32 12 ret ptr %tmp } define ptr @test_v4f32_post_reg_st1x3(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.4s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -10839,47 +10218,47 @@ declare void @llvm.aarch64.neon.st1x3.v4f32.p0(<4 x float>, <4 x float>, <4 x fl define ptr @test_v2f32_post_imm_st1x3(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.2s { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i32 6 ret ptr %tmp } define ptr @test_v2f32_post_reg_st1x3(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.2s { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -10889,47 +10268,47 @@ declare void @llvm.aarch64.neon.st1x3.v2f32.p0(<2 x float>, <2 x float>, <2 x fl define ptr @test_v2f64_post_imm_st1x3(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.2d { v0, v1, v2 }, [x0], #48 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #48 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2 }, [x0], #48 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #48 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 6 ret ptr %tmp } define ptr @test_v2f64_post_reg_st1x3(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st1.2d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -10939,47 +10318,47 @@ declare void @llvm.aarch64.neon.st1x3.v2f64.p0(<2 x double>, <2 x double>, <2 x define ptr @test_v1f64_post_imm_st1x3(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v1f64_post_reg_st1x3(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st1x3: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; SDAG-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st1x3: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st1x3: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st1x3: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2 def $d0_d1_d2 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -10989,50 +10368,50 @@ declare void @llvm.aarch64.neon.st1x3.v1f64.p0(<1 x double>, <1 x double>, <1 x define ptr @test_v16i8_post_imm_st1x4(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.16b { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.16b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.16b { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.16b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i32 64 ret ptr %tmp } define ptr @test_v16i8_post_reg_st1x4(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.16b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.16b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.16b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.16b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -11042,50 +10421,50 @@ declare void @llvm.aarch64.neon.st1x4.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8>, define ptr @test_v8i8_post_imm_st1x4(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.8b { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.8b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.8b { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.8b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i32 32 ret ptr %tmp } define ptr @test_v8i8_post_reg_st1x4(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.8b { v0, v1, v2, v3 }, [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.8b { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.8b { v0, v1, v2, v3 }, [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.8b { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -11095,51 +10474,51 @@ declare void @llvm.aarch64.neon.st1x4.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, <8 x define ptr @test_v8i16_post_imm_st1x4(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.8h { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.8h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.8h { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.8h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i32 32 ret ptr %tmp } define ptr @test_v8i16_post_reg_st1x4(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.8h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.8h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.8h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.8h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -11149,51 +10528,51 @@ declare void @llvm.aarch64.neon.st1x4.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16>, define ptr @test_v4i16_post_imm_st1x4(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.4h { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.4h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.4h { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.4h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v4i16_post_reg_st1x4(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.4h { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.4h { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.4h { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.4h { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -11203,51 +10582,51 @@ declare void @llvm.aarch64.neon.st1x4.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16>,< define ptr @test_v4i32_post_imm_st1x4(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v4i32_post_reg_st1x4(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -11257,51 +10636,51 @@ declare void @llvm.aarch64.neon.st1x4.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32>,< define ptr @test_v2i32_post_imm_st1x4(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v2i32_post_reg_st1x4(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -11311,51 +10690,51 @@ declare void @llvm.aarch64.neon.st1x4.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32>, define ptr @test_v2i64_post_imm_st1x4(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 8 ret ptr %tmp } define ptr @test_v2i64_post_reg_st1x4(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -11365,51 +10744,51 @@ declare void @llvm.aarch64.neon.st1x4.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64>,< define ptr @test_v1i64_post_imm_st1x4(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v1i64_post_reg_st1x4(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -11419,51 +10798,51 @@ declare void @llvm.aarch64.neon.st1x4.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64>,< define ptr @test_v4f32_post_imm_st1x4(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i32 16 ret ptr %tmp } define ptr @test_v4f32_post_reg_st1x4(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.4s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.4s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -11473,51 +10852,51 @@ declare void @llvm.aarch64.neon.st1x4.v4f32.p0(<4 x float>, <4 x float>, <4 x fl define ptr @test_v2f32_post_imm_st1x4(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i32 8 ret ptr %tmp } define ptr @test_v2f32_post_reg_st1x4(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.2s { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.2s { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -11527,51 +10906,51 @@ declare void @llvm.aarch64.neon.st1x4.v2f32.p0(<2 x float>, <2 x float>, <2 x fl define ptr @test_v2f64_post_imm_st1x4(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], #64 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #64 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], #64 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #64 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 8 ret ptr %tmp } define ptr @test_v2f64_post_reg_st1x4(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st1.2d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st1.2d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -11581,51 +10960,51 @@ declare void @llvm.aarch64.neon.st1x4.v2f64.p0(<2 x double>, <2 x double>, <2 x define ptr @test_v1f64_post_imm_st1x4(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v1f64_post_reg_st1x4(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st1x4: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; SDAG-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st1x4: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 -; CHECK-GISEL-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st1x4: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-SD-NEXT: st1.1d { v0, v1, v2, v3 }, [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st1x4: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $d0_d1_d2_d3 def $d0_d1_d2_d3 +; CHECK-GI-NEXT: st1.1d { v0, v1, v2, v3 }, [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -11634,42 +11013,42 @@ define ptr @test_v1f64_post_reg_st1x4(ptr %A, ptr %ptr, <1 x double> %B, <1 x do declare void @llvm.aarch64.neon.st1x4.v1f64.p0(<1 x double>, <1 x double>, <1 x double>, <1 x double>, ptr) define ptr @test_v16i8_post_imm_st2lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.b { v0, v1 }[0], [x0], #2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.b { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.b { v0, v1 }[0], [x0], #2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.b { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v16i8_post_reg_st2lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.b { v0, v1 }[0], [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.b { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.b { v0, v1 }[0], [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.b { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -11679,42 +11058,42 @@ declare void @llvm.aarch64.neon.st2lane.v16i8.p0(<16 x i8>, <16 x i8>, i64, ptr) define ptr @test_v8i8_post_imm_st2lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.b { v0, v1 }[0], [x0], #2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.b { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.b { v0, v1 }[0], [x0], #2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.b { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v8i8_post_reg_st2lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.b { v0, v1 }[0], [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.b { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.b { v0, v1 }[0], [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.b { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -11724,43 +11103,43 @@ declare void @llvm.aarch64.neon.st2lane.v8i8.p0(<8 x i8>, <8 x i8>, i64, ptr) define ptr @test_v8i16_post_imm_st2lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.h { v0, v1 }[0], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.h { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.h { v0, v1 }[0], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #4 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.h { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v8i16_post_reg_st2lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.h { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.h { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.h { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.h { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -11770,43 +11149,43 @@ declare void @llvm.aarch64.neon.st2lane.v8i16.p0(<8 x i16>, <8 x i16>, i64, ptr) define ptr @test_v4i16_post_imm_st2lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.h { v0, v1 }[0], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.h { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.h { v0, v1 }[0], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #4 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.h { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v4i16_post_reg_st2lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.h { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.h { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.h { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.h { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -11816,43 +11195,43 @@ declare void @llvm.aarch64.neon.st2lane.v4i16.p0(<4 x i16>, <4 x i16>, i64, ptr) define ptr @test_v4i32_post_imm_st2lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #8 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v4i32_post_reg_st2lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -11862,43 +11241,43 @@ declare void @llvm.aarch64.neon.st2lane.v4i32.p0(<4 x i32>, <4 x i32>, i64, ptr) define ptr @test_v2i32_post_imm_st2lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #8 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v2i32_post_reg_st2lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -11908,43 +11287,43 @@ declare void @llvm.aarch64.neon.st2lane.v2i32.p0(<2 x i32>, <2 x i32>, i64, ptr) define ptr @test_v2i64_post_imm_st2lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v2i64_post_reg_st2lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -11954,43 +11333,43 @@ declare void @llvm.aarch64.neon.st2lane.v2i64.p0(<2 x i64>, <2 x i64>, i64, ptr) define ptr @test_v1i64_post_imm_st2lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v1i64_post_reg_st2lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -12000,43 +11379,43 @@ declare void @llvm.aarch64.neon.st2lane.v1i64.p0(<1 x i64>, <1 x i64>, i64, ptr) define ptr @test_v4f32_post_imm_st2lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #8 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float> %B, <4 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v4f32_post_reg_st2lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float> %B, <4 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -12046,43 +11425,43 @@ declare void @llvm.aarch64.neon.st2lane.v4f32.p0(<4 x float>, <4 x float>, i64, define ptr @test_v2f32_post_imm_st2lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #8 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2f32.p0(<2 x float> %B, <2 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 2 ret ptr %tmp } define ptr @test_v2f32_post_reg_st2lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.s { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.s { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.s { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.s { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2f32.p0(<2 x float> %B, <2 x float> %C, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -12092,43 +11471,43 @@ declare void @llvm.aarch64.neon.st2lane.v2f32.p0(<2 x float>, <2 x float>, i64, define ptr @test_v2f64_post_imm_st2lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2f64.p0(<2 x double> %B, <2 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v2f64_post_reg_st2lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v2f64.p0(<2 x double> %B, <2 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -12138,43 +11517,43 @@ declare void @llvm.aarch64.neon.st2lane.v2f64.p0(<2 x double>, <2 x double>, i64 define ptr @test_v1f64_post_imm_st2lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v1f64.p0(<1 x double> %B, <1 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 2 ret ptr %tmp } define ptr @test_v1f64_post_reg_st2lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st2lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; SDAG-NEXT: st2.d { v0, v1 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st2lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 -; CHECK-GISEL-NEXT: st2.d { v0, v1 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st2lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-SD-NEXT: st2.d { v0, v1 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st2lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: st2.d { v0, v1 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st2lane.v1f64.p0(<1 x double> %B, <1 x double> %C, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -12184,46 +11563,46 @@ declare void @llvm.aarch64.neon.st2lane.v1f64.p0(<1 x double>, <1 x double>, i64 define ptr @test_v16i8_post_imm_st3lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.b { v0, v1, v2 }[0], [x0], #3 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.b { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.b { v0, v1, v2 }[0], [x0], #3 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.b { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v16i8_post_reg_st3lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.b { v0, v1, v2 }[0], [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.b { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.b { v0, v1, v2 }[0], [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.b { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -12233,46 +11612,46 @@ declare void @llvm.aarch64.neon.st3lane.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8> define ptr @test_v8i8_post_imm_st3lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.b { v0, v1, v2 }[0], [x0], #3 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.b { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.b { v0, v1, v2 }[0], [x0], #3 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.b { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v8i8_post_reg_st3lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.b { v0, v1, v2 }[0], [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.b { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.b { v0, v1, v2 }[0], [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.b { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -12282,47 +11661,47 @@ declare void @llvm.aarch64.neon.st3lane.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, i6 define ptr @test_v8i16_post_imm_st3lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.h { v0, v1, v2 }[0], [x0], #6 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #6 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.h { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.h { v0, v1, v2 }[0], [x0], #6 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #6 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.h { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v8i16_post_reg_st3lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.h { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.h { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.h { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.h { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -12332,47 +11711,47 @@ declare void @llvm.aarch64.neon.st3lane.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16> define ptr @test_v4i16_post_imm_st3lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.h { v0, v1, v2 }[0], [x0], #6 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #6 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.h { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.h { v0, v1, v2 }[0], [x0], #6 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #6 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.h { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v4i16_post_reg_st3lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.h { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.h { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.h { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.h { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -12382,47 +11761,47 @@ declare void @llvm.aarch64.neon.st3lane.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16> define ptr @test_v4i32_post_imm_st3lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #12 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v4i32_post_reg_st3lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -12432,47 +11811,47 @@ declare void @llvm.aarch64.neon.st3lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32> define ptr @test_v2i32_post_imm_st3lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #12 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v2i32_post_reg_st3lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -12482,47 +11861,47 @@ declare void @llvm.aarch64.neon.st3lane.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32> define ptr @test_v2i64_post_imm_st3lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v2i64_post_reg_st3lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -12532,47 +11911,47 @@ declare void @llvm.aarch64.neon.st3lane.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64> define ptr @test_v1i64_post_imm_st3lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v1i64_post_reg_st3lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -12582,47 +11961,47 @@ declare void @llvm.aarch64.neon.st3lane.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64> define ptr @test_v4f32_post_imm_st3lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #12 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v4f32_post_reg_st3lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -12632,47 +12011,47 @@ declare void @llvm.aarch64.neon.st3lane.v4f32.p0(<4 x float>, <4 x float>, <4 x define ptr @test_v2f32_post_imm_st3lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #12 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], #12 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #12 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 3 ret ptr %tmp } define ptr @test_v2f32_post_reg_st3lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.s { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.s { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.s { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -12682,47 +12061,47 @@ declare void @llvm.aarch64.neon.st3lane.v2f32.p0(<2 x float>, <2 x float>, <2 x define ptr @test_v2f64_post_imm_st3lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v2f64_post_reg_st3lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -12732,47 +12111,47 @@ declare void @llvm.aarch64.neon.st3lane.v2f64.p0(<2 x double>, <2 x double>, <2 define ptr @test_v1f64_post_imm_st3lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #24 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], #24 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #24 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 3 ret ptr %tmp } define ptr @test_v1f64_post_reg_st3lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st3lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; SDAG-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st3lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 -; CHECK-GISEL-NEXT: st3.d { v0, v1, v2 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st3lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-SD-NEXT: st3.d { v0, v1, v2 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st3lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2 def $q0_q1_q2 +; CHECK-GI-NEXT: st3.d { v0, v1, v2 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st3lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -12782,50 +12161,50 @@ declare void @llvm.aarch64.neon.st3lane.v1f64.p0(<1 x double>, <1 x double>, <1 define ptr @test_v16i8_post_imm_st4lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E) nounwind { -; SDAG-LABEL: test_v16i8_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #4 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v16i8_post_reg_st4lane(ptr %A, ptr %ptr, <16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v16i8_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8> %B, <16 x i8> %C, <16 x i8> %D, <16 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -12835,50 +12214,50 @@ declare void @llvm.aarch64.neon.st4lane.v16i8.p0(<16 x i8>, <16 x i8>, <16 x i8> define ptr @test_v8i8_post_imm_st4lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E) nounwind { -; SDAG-LABEL: test_v8i8_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], #4 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #4 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], #4 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #4 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v8i8_post_reg_st4lane(ptr %A, ptr %ptr, <8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i8_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], x2 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.b { v0, v1, v2, v3 }[0], [x0], x2 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.b { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8> %B, <8 x i8> %C, <8 x i8> %D, <8 x i8> %E, i64 0, ptr %A) %tmp = getelementptr i8, ptr %A, i64 %inc ret ptr %tmp @@ -12888,51 +12267,51 @@ declare void @llvm.aarch64.neon.st4lane.v8i8.p0(<8 x i8>, <8 x i8>, <8 x i8>, <8 define ptr @test_v8i16_post_imm_st4lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E) nounwind { -; SDAG-LABEL: test_v8i16_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #8 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v8i16_post_reg_st4lane(ptr %A, ptr %ptr, <8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v8i16_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16> %B, <8 x i16> %C, <8 x i16> %D, <8 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -12942,51 +12321,51 @@ declare void @llvm.aarch64.neon.st4lane.v8i16.p0(<8 x i16>, <8 x i16>, <8 x i16> define ptr @test_v4i16_post_imm_st4lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E) nounwind { -; SDAG-LABEL: test_v4i16_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], #8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #8 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], #8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #8 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v4i16_post_reg_st4lane(ptr %A, ptr %ptr, <4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i16_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.h { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #1 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.h { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16> %B, <4 x i16> %C, <4 x i16> %D, <4 x i16> %E, i64 0, ptr %A) %tmp = getelementptr i16, ptr %A, i64 %inc ret ptr %tmp @@ -12996,51 +12375,51 @@ declare void @llvm.aarch64.neon.st4lane.v4i16.p0(<4 x i16>, <4 x i16>, <4 x i16> define ptr @test_v4i32_post_imm_st4lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E) nounwind { -; SDAG-LABEL: test_v4i32_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v4i32_post_reg_st4lane(ptr %A, ptr %ptr, <4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4i32_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32> %B, <4 x i32> %C, <4 x i32> %D, <4 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -13050,51 +12429,51 @@ declare void @llvm.aarch64.neon.st4lane.v4i32.p0(<4 x i32>, <4 x i32>, <4 x i32> define ptr @test_v2i32_post_imm_st4lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E) nounwind { -; SDAG-LABEL: test_v2i32_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v2i32_post_reg_st4lane(ptr %A, ptr %ptr, <2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i32_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32> %B, <2 x i32> %C, <2 x i32> %D, <2 x i32> %E, i64 0, ptr %A) %tmp = getelementptr i32, ptr %A, i64 %inc ret ptr %tmp @@ -13104,51 +12483,51 @@ declare void @llvm.aarch64.neon.st4lane.v2i32.p0(<2 x i32>, <2 x i32>, <2 x i32> define ptr @test_v2i64_post_imm_st4lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E) nounwind { -; SDAG-LABEL: test_v2i64_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v2i64_post_reg_st4lane(ptr %A, ptr %ptr, <2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2i64_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64> %B, <2 x i64> %C, <2 x i64> %D, <2 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -13158,51 +12537,51 @@ declare void @llvm.aarch64.neon.st4lane.v2i64.p0(<2 x i64>, <2 x i64>, <2 x i64> define ptr @test_v1i64_post_imm_st4lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E) nounwind { -; SDAG-LABEL: test_v1i64_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v1i64_post_reg_st4lane(ptr %A, ptr %ptr, <1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v1i64_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1i64_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1i64_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1i64_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64> %B, <1 x i64> %C, <1 x i64> %D, <1 x i64> %E, i64 0, ptr %A) %tmp = getelementptr i64, ptr %A, i64 %inc ret ptr %tmp @@ -13212,51 +12591,51 @@ declare void @llvm.aarch64.neon.st4lane.v1i64.p0(<1 x i64>, <1 x i64>, <1 x i64> define ptr @test_v4f32_post_imm_st4lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E) nounwind { -; SDAG-LABEL: test_v4f32_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v4f32_post_reg_st4lane(ptr %A, ptr %ptr, <4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v4f32_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float> %B, <4 x float> %C, <4 x float> %D, <4 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -13266,51 +12645,51 @@ declare void @llvm.aarch64.neon.st4lane.v4f32.p0(<4 x float>, <4 x float>, <4 x define ptr @test_v2f32_post_imm_st4lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E) nounwind { -; SDAG-LABEL: test_v2f32_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #16 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #16 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i32 4 ret ptr %tmp } define ptr @test_v2f32_post_reg_st4lane(ptr %A, ptr %ptr, <2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f32_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.s { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #2 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.s { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2f32.p0(<2 x float> %B, <2 x float> %C, <2 x float> %D, <2 x float> %E, i64 0, ptr %A) %tmp = getelementptr float, ptr %A, i64 %inc ret ptr %tmp @@ -13320,51 +12699,51 @@ declare void @llvm.aarch64.neon.st4lane.v2f32.p0(<2 x float>, <2 x float>, <2 x define ptr @test_v2f64_post_imm_st4lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E) nounwind { -; SDAG-LABEL: test_v2f64_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v2f64_post_reg_st4lane(ptr %A, ptr %ptr, <2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v2f64_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $q0 killed $q0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $q1 killed $q1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q2 killed $q2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $q3 killed $q3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v2f64.p0(<2 x double> %B, <2 x double> %C, <2 x double> %D, <2 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -13374,51 +12753,51 @@ declare void @llvm.aarch64.neon.st4lane.v2f64.p0(<2 x double>, <2 x double>, <2 define ptr @test_v1f64_post_imm_st4lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E) nounwind { -; SDAG-LABEL: test_v1f64_post_imm_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_imm_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, #32 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_imm_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], #32 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_imm_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, #32 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 4 ret ptr %tmp } define ptr @test_v1f64_post_reg_st4lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 %inc) nounwind { -; SDAG-LABEL: test_v1f64_post_reg_st4lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; SDAG-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v1f64_post_reg_st4lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: mov x8, x0 -; CHECK-GISEL-NEXT: add x0, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 -; CHECK-GISEL-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v1f64_post_reg_st4lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-SD-NEXT: st4.d { v0, v1, v2, v3 }[0], [x0], x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v1f64_post_reg_st4lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: mov x8, x0 +; CHECK-GI-NEXT: add x0, x0, x2, lsl #3 +; CHECK-GI-NEXT: ; kill: def $d1 killed $d1 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d2 killed $d2 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: ; kill: def $d3 killed $d3 killed $q0_q1_q2_q3 def $q0_q1_q2_q3 +; CHECK-GI-NEXT: st4.d { v0, v1, v2, v3 }[0], [x8] +; CHECK-GI-NEXT: ret call void @llvm.aarch64.neon.st4lane.v1f64.p0(<1 x double> %B, <1 x double> %C, <1 x double> %D, <1 x double> %E, i64 0, ptr %A) %tmp = getelementptr double, ptr %A, i64 %inc ret ptr %tmp @@ -13427,18 +12806,18 @@ define ptr @test_v1f64_post_reg_st4lane(ptr %A, ptr %ptr, <1 x double> %B, <1 x declare void @llvm.aarch64.neon.st4lane.v1f64.p0(<1 x double>, <1 x double>, <1 x double>, <1 x double>, i64, ptr) define <16 x i8> @test_v16i8_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v16i8_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.16b { v0 }, [x0], #1 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrb w8, [x0], #1 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.16b v0, w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.16b { v0 }, [x0], #1 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrb w8, [x0], #1 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.16b v0, w8 +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <16 x i8> , i8 %tmp1, i32 0 %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1 @@ -13462,18 +12841,18 @@ define <16 x i8> @test_v16i8_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <16 x i8> @test_v16i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v16i8_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.16b { v0 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.16b { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.16b { v0 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.16b { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <16 x i8> , i8 %tmp1, i32 0 %tmp3 = insertelement <16 x i8> %tmp2, i8 %tmp1, i32 1 @@ -13497,18 +12876,18 @@ define <16 x i8> @test_v16i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <8 x i8> @test_v8i8_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v8i8_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.8b { v0 }, [x0], #1 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrb w8, [x0], #1 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.8b v0, w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.8b { v0 }, [x0], #1 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrb w8, [x0], #1 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.8b v0, w8 +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <8 x i8> , i8 %tmp1, i32 0 %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1 @@ -13524,18 +12903,18 @@ define <8 x i8> @test_v8i8_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <8 x i8> @test_v8i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i8_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.8b { v0 }, [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.8b { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.8b { v0 }, [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.8b { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <8 x i8> , i8 %tmp1, i32 0 %tmp3 = insertelement <8 x i8> %tmp2, i8 %tmp1, i32 1 @@ -13551,18 +12930,18 @@ define <8 x i8> @test_v8i8_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <8 x i16> @test_v8i16_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v8i16_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.8h { v0 }, [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrh w8, [x0], #2 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.8h v0, w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.8h { v0 }, [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrh w8, [x0], #2 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.8h v0, w8 +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <8 x i16> , i16 %tmp1, i32 0 %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1 @@ -13578,19 +12957,19 @@ define <8 x i16> @test_v8i16_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <8 x i16> @test_v8i16_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v8i16_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1r.8h { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.8h { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1r.8h { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.8h { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <8 x i16> , i16 %tmp1, i32 0 %tmp3 = insertelement <8 x i16> %tmp2, i16 %tmp1, i32 1 @@ -13606,18 +12985,18 @@ define <8 x i16> @test_v8i16_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <4 x i16> @test_v4i16_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v4i16_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.4h { v0 }, [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrh w8, [x0], #2 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.4h v0, w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.4h { v0 }, [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrh w8, [x0], #2 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.4h v0, w8 +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <4 x i16> , i16 %tmp1, i32 0 %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1 @@ -13629,19 +13008,19 @@ define <4 x i16> @test_v4i16_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <4 x i16> @test_v4i16_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i16_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1r.4h { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.4h { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1r.4h { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.4h { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <4 x i16> , i16 %tmp1, i32 0 %tmp3 = insertelement <4 x i16> %tmp2, i16 %tmp1, i32 1 @@ -13653,18 +13032,18 @@ define <4 x i16> @test_v4i16_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <4 x i32> @test_v4i32_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v4i32_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.4s { v0 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr w8, [x0], #4 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.4s v0, w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.4s { v0 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr w8, [x0], #4 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.4s v0, w8 +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <4 x i32> , i32 %tmp1, i32 0 %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1 @@ -13676,19 +13055,19 @@ define <4 x i32> @test_v4i32_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <4 x i32> @test_v4i32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4i32_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1r.4s { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.4s { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1r.4s { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.4s { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <4 x i32> , i32 %tmp1, i32 0 %tmp3 = insertelement <4 x i32> %tmp2, i32 %tmp1, i32 1 @@ -13700,18 +13079,18 @@ define <4 x i32> @test_v4i32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <2 x i32> @test_v2i32_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v2i32_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.2s { v0 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr w8, [x0], #4 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.2s v0, w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.2s { v0 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr w8, [x0], #4 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.2s v0, w8 +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <2 x i32> , i32 %tmp1, i32 0 %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1 @@ -13721,19 +13100,19 @@ define <2 x i32> @test_v2i32_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <2 x i32> @test_v2i32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i32_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1r.2s { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.2s { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1r.2s { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.2s { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <2 x i32> , i32 %tmp1, i32 0 %tmp3 = insertelement <2 x i32> %tmp2, i32 %tmp1, i32 1 @@ -13743,18 +13122,18 @@ define <2 x i32> @test_v2i32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <2 x i64> @test_v2i64_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v2i64_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.2d { v0 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr x8, [x0], #8 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.2d v0, x8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.2d { v0 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr x8, [x0], #8 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.2d v0, x8 +; CHECK-GI-NEXT: ret %tmp1 = load i64, ptr %bar %tmp2 = insertelement <2 x i64> , i64 %tmp1, i32 0 %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1 @@ -13764,19 +13143,19 @@ define <2 x i64> @test_v2i64_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <2 x i64> @test_v2i64_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2i64_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1r.2d { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.2d { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1r.2d { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.2d { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i64, ptr %bar %tmp2 = insertelement <2 x i64> , i64 %tmp1, i32 0 %tmp3 = insertelement <2 x i64> %tmp2, i64 %tmp1, i32 1 @@ -13786,18 +13165,18 @@ define <2 x i64> @test_v2i64_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <4 x float> @test_v4f32_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v4f32_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.4s { v0 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s0, [x0], #4 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.4s v0, v0[0] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.4s { v0 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s0, [x0], #4 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.4s v0, v0[0] +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <4 x float> , float %tmp1, i32 0 %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1 @@ -13809,19 +13188,19 @@ define <4 x float> @test_v4f32_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <4 x float> @test_v4f32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v4f32_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1r.4s { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.4s { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1r.4s { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.4s { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <4 x float> , float %tmp1, i32 0 %tmp3 = insertelement <4 x float> %tmp2, float %tmp1, i32 1 @@ -13833,18 +13212,18 @@ define <4 x float> @test_v4f32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <2 x float> @test_v2f32_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v2f32_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.2s { v0 }, [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s0, [x0], #4 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.2s v0, v0[0] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.2s { v0 }, [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s0, [x0], #4 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.2s v0, v0[0] +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <2 x float> , float %tmp1, i32 0 %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1 @@ -13854,19 +13233,19 @@ define <2 x float> @test_v2f32_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <2 x float> @test_v2f32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f32_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1r.2s { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.2s { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1r.2s { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.2s { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <2 x float> , float %tmp1, i32 0 %tmp3 = insertelement <2 x float> %tmp2, float %tmp1, i32 1 @@ -13876,18 +13255,18 @@ define <2 x float> @test_v2f32_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <2 x double> @test_v2f64_post_imm_ld1r(ptr %bar, ptr %ptr) { -; SDAG-LABEL: test_v2f64_post_imm_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1r.2d { v0 }, [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr d0, [x0], #8 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: dup.2d v0, v0[0] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1r.2d { v0 }, [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr d0, [x0], #8 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: dup.2d v0, v0[0] +; CHECK-GI-NEXT: ret %tmp1 = load double, ptr %bar %tmp2 = insertelement <2 x double> , double %tmp1, i32 0 %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1 @@ -13897,19 +13276,19 @@ define <2 x double> @test_v2f64_post_imm_ld1r(ptr %bar, ptr %ptr) { } define <2 x double> @test_v2f64_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { -; SDAG-LABEL: test_v2f64_post_reg_ld1r: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1r.2d { v0 }, [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld1r: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ld1r.2d { v0 }, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld1r: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1r.2d { v0 }, [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld1r: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ld1r.2d { v0 }, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load double, ptr %bar %tmp2 = insertelement <2 x double> , double %tmp1, i32 0 %tmp3 = insertelement <2 x double> %tmp2, double %tmp1, i32 1 @@ -13919,18 +13298,18 @@ define <2 x double> @test_v2f64_post_reg_ld1r(ptr %bar, ptr %ptr, i64 %inc) { } define <16 x i8> @test_v16i8_post_imm_ld1lane(ptr %bar, ptr %ptr, <16 x i8> %A) { -; SDAG-LABEL: test_v16i8_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.b { v0 }[1], [x0], #1 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrb w8, [x0], #1 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.b v0[1], w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.b { v0 }[1], [x0], #1 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrb w8, [x0], #1 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.b v0[1], w8 +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1 %tmp3 = getelementptr i8, ptr %bar, i64 1 @@ -13939,19 +13318,19 @@ define <16 x i8> @test_v16i8_post_imm_ld1lane(ptr %bar, ptr %ptr, <16 x i8> %A) } define <16 x i8> @test_v16i8_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <16 x i8> %A) { -; SDAG-LABEL: test_v16i8_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.b { v0 }[1], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v16i8_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr b1, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: mov.b v0[1], v1[0] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v16i8_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.b { v0 }[1], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v16i8_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr b1, [x0] +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: mov.b v0[1], v1[0] +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <16 x i8> %A, i8 %tmp1, i32 1 %tmp3 = getelementptr i8, ptr %bar, i64 %inc @@ -13960,22 +13339,22 @@ define <16 x i8> @test_v16i8_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <16 } define <8 x i8> @test_v8i8_post_imm_ld1lane(ptr %bar, ptr %ptr, <8 x i8> %A) { -; SDAG-LABEL: test_v8i8_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.b { v0 }[1], [x0], #1 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrb w8, [x0], #1 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.b v0[1], w8 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.b { v0 }[1], [x0], #1 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrb w8, [x0], #1 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.b v0[1], w8 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1 %tmp3 = getelementptr i8, ptr %bar, i64 1 @@ -13984,23 +13363,23 @@ define <8 x i8> @test_v8i8_post_imm_ld1lane(ptr %bar, ptr %ptr, <8 x i8> %A) { } define <8 x i8> @test_v8i8_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <8 x i8> %A) { -; SDAG-LABEL: test_v8i8_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.b { v0 }[1], [x0], x2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i8_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr b1, [x0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: add x8, x0, x2 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: mov.b v0[1], v1[0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i8_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.b { v0 }[1], [x0], x2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i8_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr b1, [x0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: add x8, x0, x2 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: mov.b v0[1], v1[0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load i8, ptr %bar %tmp2 = insertelement <8 x i8> %A, i8 %tmp1, i32 1 %tmp3 = getelementptr i8, ptr %bar, i64 %inc @@ -14009,18 +13388,18 @@ define <8 x i8> @test_v8i8_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <8 x i } define <8 x i16> @test_v8i16_post_imm_ld1lane(ptr %bar, ptr %ptr, <8 x i16> %A) { -; SDAG-LABEL: test_v8i16_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.h { v0 }[1], [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrh w8, [x0], #2 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.h v0[1], w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.h { v0 }[1], [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrh w8, [x0], #2 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.h v0[1], w8 +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1 %tmp3 = getelementptr i16, ptr %bar, i64 1 @@ -14029,20 +13408,20 @@ define <8 x i16> @test_v8i16_post_imm_ld1lane(ptr %bar, ptr %ptr, <8 x i16> %A) } define <8 x i16> @test_v8i16_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <8 x i16> %A) { -; SDAG-LABEL: test_v8i16_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ld1.h { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v8i16_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr h1, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: mov.h v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v8i16_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ld1.h { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v8i16_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr h1, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: mov.h v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <8 x i16> %A, i16 %tmp1, i32 1 %tmp3 = getelementptr i16, ptr %bar, i64 %inc @@ -14051,22 +13430,22 @@ define <8 x i16> @test_v8i16_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <8 x } define <4 x i16> @test_v4i16_post_imm_ld1lane(ptr %bar, ptr %ptr, <4 x i16> %A) { -; SDAG-LABEL: test_v4i16_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.h { v0 }[1], [x0], #2 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldrh w8, [x0], #2 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.h v0[1], w8 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.h { v0 }[1], [x0], #2 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldrh w8, [x0], #2 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.h v0[1], w8 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1 %tmp3 = getelementptr i16, ptr %bar, i64 1 @@ -14075,24 +13454,24 @@ define <4 x i16> @test_v4i16_post_imm_ld1lane(ptr %bar, ptr %ptr, <4 x i16> %A) } define <4 x i16> @test_v4i16_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <4 x i16> %A) { -; SDAG-LABEL: test_v4i16_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.h { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr h1, [x0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: mov.h v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.h { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr h1, [x0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: mov.h v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1 %tmp3 = getelementptr i16, ptr %bar, i64 %inc @@ -14101,18 +13480,18 @@ define <4 x i16> @test_v4i16_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <4 x } define <4 x i32> @test_v4i32_post_imm_ld1lane(ptr %bar, ptr %ptr, <4 x i32> %A) { -; SDAG-LABEL: test_v4i32_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.s { v0 }[1], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr w8, [x0], #4 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.s v0[1], w8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr w8, [x0], #4 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.s v0[1], w8 +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1 %tmp3 = getelementptr i32, ptr %bar, i64 1 @@ -14121,20 +13500,20 @@ define <4 x i32> @test_v4i32_post_imm_ld1lane(ptr %bar, ptr %ptr, <4 x i32> %A) } define <4 x i32> @test_v4i32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <4 x i32> %A) { -; SDAG-LABEL: test_v4i32_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.s { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i32_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i32_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i32_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <4 x i32> %A, i32 %tmp1, i32 1 %tmp3 = getelementptr i32, ptr %bar, i64 %inc @@ -14143,22 +13522,22 @@ define <4 x i32> @test_v4i32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <4 x } define <2 x i32> @test_v2i32_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x i32> %A) { -; SDAG-LABEL: test_v2i32_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.s { v0 }[1], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr w8, [x0], #4 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.s v0[1], w8 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr w8, [x0], #4 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.s v0[1], w8 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1 %tmp3 = getelementptr i32, ptr %bar, i64 1 @@ -14167,24 +13546,24 @@ define <2 x i32> @test_v2i32_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x i32> %A) } define <2 x i32> @test_v2i32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 x i32> %A) { -; SDAG-LABEL: test_v2i32_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.s { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i32_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i32_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i32_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load i32, ptr %bar %tmp2 = insertelement <2 x i32> %A, i32 %tmp1, i32 1 %tmp3 = getelementptr i32, ptr %bar, i64 %inc @@ -14193,18 +13572,18 @@ define <2 x i32> @test_v2i32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 x } define <2 x i64> @test_v2i64_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x i64> %A) { -; SDAG-LABEL: test_v2i64_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.d { v0 }[1], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr x8, [x0], #8 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.d v0[1], x8 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.d { v0 }[1], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr x8, [x0], #8 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.d v0[1], x8 +; CHECK-GI-NEXT: ret %tmp1 = load i64, ptr %bar %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1 %tmp3 = getelementptr i64, ptr %bar, i64 1 @@ -14213,20 +13592,20 @@ define <2 x i64> @test_v2i64_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x i64> %A) } define <2 x i64> @test_v2i64_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 x i64> %A) { -; SDAG-LABEL: test_v2i64_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.d { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2i64_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr d1, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: mov.d v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2i64_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.d { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2i64_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr d1, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: mov.d v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load i64, ptr %bar %tmp2 = insertelement <2 x i64> %A, i64 %tmp1, i32 1 %tmp3 = getelementptr i64, ptr %bar, i64 %inc @@ -14235,18 +13614,18 @@ define <2 x i64> @test_v2i64_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 x } define <4 x float> @test_v4f32_post_imm_ld1lane(ptr %bar, ptr %ptr, <4 x float> %A) { -; SDAG-LABEL: test_v4f32_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.s { v0 }[1], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0], #4 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0], #4 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1 %tmp3 = getelementptr float, ptr %bar, i64 1 @@ -14255,20 +13634,20 @@ define <4 x float> @test_v4f32_post_imm_ld1lane(ptr %bar, ptr %ptr, <4 x float> } define <4 x float> @test_v4f32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <4 x float> %A) { -; SDAG-LABEL: test_v4f32_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ld1.s { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4f32_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4f32_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4f32_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <4 x float> %A, float %tmp1, i32 1 %tmp3 = getelementptr float, ptr %bar, i64 %inc @@ -14277,22 +13656,22 @@ define <4 x float> @test_v4f32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <4 } define <2 x float> @test_v2f32_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x float> %A) { -; SDAG-LABEL: test_v2f32_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.s { v0 }[1], [x0], #4 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0], #4 -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], #4 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0], #4 +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1 %tmp3 = getelementptr float, ptr %bar, i64 1 @@ -14301,24 +13680,24 @@ define <2 x float> @test_v2f32_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x float> } define <2 x float> @test_v2f32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 x float> %A) { -; SDAG-LABEL: test_v2f32_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #2 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.s { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f32_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #2 -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f32_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #2 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f32_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: add x8, x0, x2, lsl #2 +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp1 = load float, ptr %bar %tmp2 = insertelement <2 x float> %A, float %tmp1, i32 1 %tmp3 = getelementptr float, ptr %bar, i64 %inc @@ -14327,18 +13706,18 @@ define <2 x float> @test_v2f32_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 } define <2 x double> @test_v2f64_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x double> %A) { -; SDAG-LABEL: test_v2f64_post_imm_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.d { v0 }[1], [x0], #8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_imm_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr d1, [x0], #8 -; CHECK-GISEL-NEXT: str x0, [x1] -; CHECK-GISEL-NEXT: mov.d v0[1], v1[0] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_imm_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.d { v0 }[1], [x0], #8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_imm_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr d1, [x0], #8 +; CHECK-GI-NEXT: str x0, [x1] +; CHECK-GI-NEXT: mov.d v0[1], v1[0] +; CHECK-GI-NEXT: ret %tmp1 = load double, ptr %bar %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1 %tmp3 = getelementptr double, ptr %bar, i64 1 @@ -14347,20 +13726,20 @@ define <2 x double> @test_v2f64_post_imm_ld1lane(ptr %bar, ptr %ptr, <2 x double } define <2 x double> @test_v2f64_post_reg_ld1lane(ptr %bar, ptr %ptr, i64 %inc, <2 x double> %A) { -; SDAG-LABEL: test_v2f64_post_reg_ld1lane: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #3 -; SDAG-NEXT: ld1.d { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v2f64_post_reg_ld1lane: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr d1, [x0] -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #3 -; CHECK-GISEL-NEXT: mov.d v0[1], v1[0] -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v2f64_post_reg_ld1lane: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #3 +; CHECK-SD-NEXT: ld1.d { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v2f64_post_reg_ld1lane: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr d1, [x0] +; CHECK-GI-NEXT: add x8, x0, x2, lsl #3 +; CHECK-GI-NEXT: mov.d v0[1], v1[0] +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: ret %tmp1 = load double, ptr %bar %tmp2 = insertelement <2 x double> %A, double %tmp1, i32 1 %tmp3 = getelementptr double, ptr %bar, i64 %inc @@ -14396,34 +13775,34 @@ define <4 x float> @test_v4f32_post_reg_ld1lane_dep_vec_on_load(ptr %bar, ptr %p ; legalizer to run. We achieve that using the ctpop. ; PR23265 define <4 x i16> @test_v4i16_post_reg_ld1lane_forced_narrow(ptr %bar, ptr %ptr, i64 %inc, <4 x i16> %A, ptr %d) { -; SDAG-LABEL: test_v4i16_post_reg_ld1lane_forced_narrow: -; SDAG: ; %bb.0: -; SDAG-NEXT: lsl x8, x2, #1 -; SDAG-NEXT: ; kill: def $d0 killed $d0 def $q0 -; SDAG-NEXT: ld1.h { v0 }[1], [x0], x8 -; SDAG-NEXT: str x0, [x1] -; SDAG-NEXT: ldr d1, [x3] -; SDAG-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; SDAG-NEXT: cnt.8b v1, v1 -; SDAG-NEXT: uaddlp.4h v1, v1 -; SDAG-NEXT: uaddlp.2s v1, v1 -; SDAG-NEXT: str d1, [x3] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_v4i16_post_reg_ld1lane_forced_narrow: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: add x8, x0, x2, lsl #1 -; CHECK-GISEL-NEXT: ldr h1, [x0] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 def $q0 -; CHECK-GISEL-NEXT: str x8, [x1] -; CHECK-GISEL-NEXT: mov.h v0[1], v1[0] -; CHECK-GISEL-NEXT: ldr d2, [x3] -; CHECK-GISEL-NEXT: ; kill: def $d0 killed $d0 killed $q0 -; CHECK-GISEL-NEXT: cnt.8b v2, v2 -; CHECK-GISEL-NEXT: uaddlp.4h v2, v2 -; CHECK-GISEL-NEXT: uaddlp.2s v1, v2 -; CHECK-GISEL-NEXT: str d1, [x3] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_v4i16_post_reg_ld1lane_forced_narrow: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: lsl x8, x2, #1 +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: ld1.h { v0 }[1], [x0], x8 +; CHECK-SD-NEXT: str x0, [x1] +; CHECK-SD-NEXT: ldr d1, [x3] +; CHECK-SD-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: cnt.8b v1, v1 +; CHECK-SD-NEXT: uaddlp.4h v1, v1 +; CHECK-SD-NEXT: uaddlp.2s v1, v1 +; CHECK-SD-NEXT: str d1, [x3] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_v4i16_post_reg_ld1lane_forced_narrow: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: add x8, x0, x2, lsl #1 +; CHECK-GI-NEXT: ldr h1, [x0] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: str x8, [x1] +; CHECK-GI-NEXT: mov.h v0[1], v1[0] +; CHECK-GI-NEXT: ldr d2, [x3] +; CHECK-GI-NEXT: ; kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: cnt.8b v2, v2 +; CHECK-GI-NEXT: uaddlp.4h v2, v2 +; CHECK-GI-NEXT: uaddlp.2s v1, v2 +; CHECK-GI-NEXT: str d1, [x3] +; CHECK-GI-NEXT: ret %tmp1 = load i16, ptr %bar %tmp2 = insertelement <4 x i16> %A, i16 %tmp1, i32 1 %tmp3 = getelementptr i16, ptr %bar, i64 %inc @@ -14437,27 +13816,27 @@ define <4 x i16> @test_v4i16_post_reg_ld1lane_forced_narrow(ptr %bar, ptr %ptr, declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) define void @test_ld1lane_build(ptr %ptr0, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr %out) { -; SDAG-LABEL: test_ld1lane_build: -; SDAG: ; %bb.0: -; SDAG-NEXT: ldr s0, [x2] -; SDAG-NEXT: ldr s1, [x0] -; SDAG-NEXT: ld1.s { v0 }[1], [x3] -; SDAG-NEXT: ld1.s { v1 }[1], [x1] -; SDAG-NEXT: sub.2s v0, v1, v0 -; SDAG-NEXT: str d0, [x4] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_ld1lane_build: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s0, [x0] -; CHECK-GISEL-NEXT: ldr s1, [x1] -; CHECK-GISEL-NEXT: ldr s2, [x2] -; CHECK-GISEL-NEXT: ldr s3, [x3] -; CHECK-GISEL-NEXT: mov.s v0[1], v1[0] -; CHECK-GISEL-NEXT: mov.s v2[1], v3[0] -; CHECK-GISEL-NEXT: sub.2s v0, v0, v2 -; CHECK-GISEL-NEXT: str d0, [x4] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_ld1lane_build: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ldr s0, [x2] +; CHECK-SD-NEXT: ldr s1, [x0] +; CHECK-SD-NEXT: ld1.s { v0 }[1], [x3] +; CHECK-SD-NEXT: ld1.s { v1 }[1], [x1] +; CHECK-SD-NEXT: sub.2s v0, v1, v0 +; CHECK-SD-NEXT: str d0, [x4] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ld1lane_build: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s0, [x0] +; CHECK-GI-NEXT: ldr s1, [x1] +; CHECK-GI-NEXT: ldr s2, [x2] +; CHECK-GI-NEXT: ldr s3, [x3] +; CHECK-GI-NEXT: mov.s v0[1], v1[0] +; CHECK-GI-NEXT: mov.s v2[1], v3[0] +; CHECK-GI-NEXT: sub.2s v0, v0, v2 +; CHECK-GI-NEXT: str d0, [x4] +; CHECK-GI-NEXT: ret %load0 = load i32, ptr %ptr0, align 4 %load1 = load i32, ptr %ptr1, align 4 %vec0_0 = insertelement <2 x i32> undef, i32 %load0, i32 0 @@ -14474,28 +13853,28 @@ define void @test_ld1lane_build(ptr %ptr0, ptr %ptr1, ptr %ptr2, ptr %ptr3, ptr } define void @test_ld1lane_build_i16(ptr %a, ptr %b, ptr %c, ptr %d, <4 x i16> %e, ptr %p) { -; SDAG-LABEL: test_ld1lane_build_i16: -; SDAG: ; %bb.0: -; SDAG-NEXT: ldr h1, [x0] -; SDAG-NEXT: ld1.h { v1 }[1], [x1] -; SDAG-NEXT: ld1.h { v1 }[2], [x2] -; SDAG-NEXT: ld1.h { v1 }[3], [x3] -; SDAG-NEXT: sub.4h v0, v1, v0 -; SDAG-NEXT: str d0, [x4] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_ld1lane_build_i16: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr h1, [x0] -; CHECK-GISEL-NEXT: ldr h2, [x1] -; CHECK-GISEL-NEXT: mov.h v1[1], v2[0] -; CHECK-GISEL-NEXT: ldr h2, [x2] -; CHECK-GISEL-NEXT: mov.h v1[2], v2[0] -; CHECK-GISEL-NEXT: ldr h2, [x3] -; CHECK-GISEL-NEXT: mov.h v1[3], v2[0] -; CHECK-GISEL-NEXT: sub.4h v0, v1, v0 -; CHECK-GISEL-NEXT: str d0, [x4] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_ld1lane_build_i16: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ldr h1, [x0] +; CHECK-SD-NEXT: ld1.h { v1 }[1], [x1] +; CHECK-SD-NEXT: ld1.h { v1 }[2], [x2] +; CHECK-SD-NEXT: ld1.h { v1 }[3], [x3] +; CHECK-SD-NEXT: sub.4h v0, v1, v0 +; CHECK-SD-NEXT: str d0, [x4] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ld1lane_build_i16: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr h1, [x0] +; CHECK-GI-NEXT: ldr h2, [x1] +; CHECK-GI-NEXT: mov.h v1[1], v2[0] +; CHECK-GI-NEXT: ldr h2, [x2] +; CHECK-GI-NEXT: mov.h v1[2], v2[0] +; CHECK-GI-NEXT: ldr h2, [x3] +; CHECK-GI-NEXT: mov.h v1[3], v2[0] +; CHECK-GI-NEXT: sub.4h v0, v1, v0 +; CHECK-GI-NEXT: str d0, [x4] +; CHECK-GI-NEXT: ret %ld.a = load i16, ptr %a %ld.b = load i16, ptr %b %ld.c = load i16, ptr %c @@ -14510,34 +13889,34 @@ define void @test_ld1lane_build_i16(ptr %a, ptr %b, ptr %c, ptr %d, <4 x i16> % } define void @test_ld1lane_build_half(ptr %a, ptr %b, ptr %c, ptr %d, <4 x half> %e, ptr %p) { -; SDAG-LABEL: test_ld1lane_build_half: -; SDAG: ; %bb.0: -; SDAG-NEXT: ldr h1, [x0] -; SDAG-NEXT: fcvtl v0.4s, v0.4h -; SDAG-NEXT: ld1.h { v1 }[1], [x1] -; SDAG-NEXT: ld1.h { v1 }[2], [x2] -; SDAG-NEXT: ld1.h { v1 }[3], [x3] -; SDAG-NEXT: fcvtl v1.4s, v1.4h -; SDAG-NEXT: fsub.4s v0, v1, v0 -; SDAG-NEXT: fcvtn v0.4h, v0.4s -; SDAG-NEXT: str d0, [x4] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_ld1lane_build_half: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr h1, [x0] -; CHECK-GISEL-NEXT: ldr h2, [x1] -; CHECK-GISEL-NEXT: fcvtl v0.4s, v0.4h -; CHECK-GISEL-NEXT: mov.h v1[1], v2[0] -; CHECK-GISEL-NEXT: ldr h2, [x2] -; CHECK-GISEL-NEXT: mov.h v1[2], v2[0] -; CHECK-GISEL-NEXT: ldr h2, [x3] -; CHECK-GISEL-NEXT: mov.h v1[3], v2[0] -; CHECK-GISEL-NEXT: fcvtl v1.4s, v1.4h -; CHECK-GISEL-NEXT: fsub.4s v0, v1, v0 -; CHECK-GISEL-NEXT: fcvtn v0.4h, v0.4s -; CHECK-GISEL-NEXT: str d0, [x4] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_ld1lane_build_half: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ldr h1, [x0] +; CHECK-SD-NEXT: fcvtl v0.4s, v0.4h +; CHECK-SD-NEXT: ld1.h { v1 }[1], [x1] +; CHECK-SD-NEXT: ld1.h { v1 }[2], [x2] +; CHECK-SD-NEXT: ld1.h { v1 }[3], [x3] +; CHECK-SD-NEXT: fcvtl v1.4s, v1.4h +; CHECK-SD-NEXT: fsub.4s v0, v1, v0 +; CHECK-SD-NEXT: fcvtn v0.4h, v0.4s +; CHECK-SD-NEXT: str d0, [x4] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ld1lane_build_half: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr h1, [x0] +; CHECK-GI-NEXT: ldr h2, [x1] +; CHECK-GI-NEXT: fcvtl v0.4s, v0.4h +; CHECK-GI-NEXT: mov.h v1[1], v2[0] +; CHECK-GI-NEXT: ldr h2, [x2] +; CHECK-GI-NEXT: mov.h v1[2], v2[0] +; CHECK-GI-NEXT: ldr h2, [x3] +; CHECK-GI-NEXT: mov.h v1[3], v2[0] +; CHECK-GI-NEXT: fcvtl v1.4s, v1.4h +; CHECK-GI-NEXT: fsub.4s v0, v1, v0 +; CHECK-GI-NEXT: fcvtn v0.4h, v0.4s +; CHECK-GI-NEXT: str d0, [x4] +; CHECK-GI-NEXT: ret %ld.a = load half, ptr %a %ld.b = load half, ptr %b %ld.c = load half, ptr %c @@ -14552,42 +13931,42 @@ define void @test_ld1lane_build_half(ptr %a, ptr %b, ptr %c, ptr %d, <4 x half> } define void @test_ld1lane_build_i8(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr %f, ptr %g, ptr %h, <8 x i8> %v, ptr %p) { -; SDAG-LABEL: test_ld1lane_build_i8: -; SDAG: ; %bb.0: -; SDAG-NEXT: ldr b1, [x0] -; SDAG-NEXT: ldr x8, [sp] -; SDAG-NEXT: ld1.b { v1 }[1], [x1] -; SDAG-NEXT: ld1.b { v1 }[2], [x2] -; SDAG-NEXT: ld1.b { v1 }[3], [x3] -; SDAG-NEXT: ld1.b { v1 }[4], [x4] -; SDAG-NEXT: ld1.b { v1 }[5], [x5] -; SDAG-NEXT: ld1.b { v1 }[6], [x6] -; SDAG-NEXT: ld1.b { v1 }[7], [x7] -; SDAG-NEXT: sub.8b v0, v1, v0 -; SDAG-NEXT: str d0, [x8] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_ld1lane_build_i8: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr b1, [x0] -; CHECK-GISEL-NEXT: ldr b2, [x1] -; CHECK-GISEL-NEXT: ldr x8, [sp] -; CHECK-GISEL-NEXT: mov.b v1[1], v2[0] -; CHECK-GISEL-NEXT: ldr b2, [x2] -; CHECK-GISEL-NEXT: mov.b v1[2], v2[0] -; CHECK-GISEL-NEXT: ldr b2, [x3] -; CHECK-GISEL-NEXT: mov.b v1[3], v2[0] -; CHECK-GISEL-NEXT: ldr b2, [x4] -; CHECK-GISEL-NEXT: mov.b v1[4], v2[0] -; CHECK-GISEL-NEXT: ldr b2, [x5] -; CHECK-GISEL-NEXT: mov.b v1[5], v2[0] -; CHECK-GISEL-NEXT: ldr b2, [x6] -; CHECK-GISEL-NEXT: mov.b v1[6], v2[0] -; CHECK-GISEL-NEXT: ldr b2, [x7] -; CHECK-GISEL-NEXT: mov.b v1[7], v2[0] -; CHECK-GISEL-NEXT: sub.8b v0, v1, v0 -; CHECK-GISEL-NEXT: str d0, [x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_ld1lane_build_i8: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ldr b1, [x0] +; CHECK-SD-NEXT: ldr x8, [sp] +; CHECK-SD-NEXT: ld1.b { v1 }[1], [x1] +; CHECK-SD-NEXT: ld1.b { v1 }[2], [x2] +; CHECK-SD-NEXT: ld1.b { v1 }[3], [x3] +; CHECK-SD-NEXT: ld1.b { v1 }[4], [x4] +; CHECK-SD-NEXT: ld1.b { v1 }[5], [x5] +; CHECK-SD-NEXT: ld1.b { v1 }[6], [x6] +; CHECK-SD-NEXT: ld1.b { v1 }[7], [x7] +; CHECK-SD-NEXT: sub.8b v0, v1, v0 +; CHECK-SD-NEXT: str d0, [x8] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_ld1lane_build_i8: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr b1, [x0] +; CHECK-GI-NEXT: ldr b2, [x1] +; CHECK-GI-NEXT: ldr x8, [sp] +; CHECK-GI-NEXT: mov.b v1[1], v2[0] +; CHECK-GI-NEXT: ldr b2, [x2] +; CHECK-GI-NEXT: mov.b v1[2], v2[0] +; CHECK-GI-NEXT: ldr b2, [x3] +; CHECK-GI-NEXT: mov.b v1[3], v2[0] +; CHECK-GI-NEXT: ldr b2, [x4] +; CHECK-GI-NEXT: mov.b v1[4], v2[0] +; CHECK-GI-NEXT: ldr b2, [x5] +; CHECK-GI-NEXT: mov.b v1[5], v2[0] +; CHECK-GI-NEXT: ldr b2, [x6] +; CHECK-GI-NEXT: mov.b v1[6], v2[0] +; CHECK-GI-NEXT: ldr b2, [x7] +; CHECK-GI-NEXT: mov.b v1[7], v2[0] +; CHECK-GI-NEXT: sub.8b v0, v1, v0 +; CHECK-GI-NEXT: str d0, [x8] +; CHECK-GI-NEXT: ret %ld.a = load i8, ptr %a %ld.b = load i8, ptr %b %ld.c = load i8, ptr %c @@ -14610,24 +13989,24 @@ define void @test_ld1lane_build_i8(ptr %a, ptr %b, ptr %c, ptr %d, ptr %e, ptr } define <4 x i32> @test_inc_cycle(<4 x i32> %vec, ptr %in) { -; SDAG-LABEL: test_inc_cycle: -; SDAG: ; %bb.0: -; SDAG-NEXT: ld1.s { v0 }[0], [x0] -; SDAG-NEXT: adrp x9, _var@PAGE -; SDAG-NEXT: fmov x8, d0 -; SDAG-NEXT: add x8, x0, x8, lsl #2 -; SDAG-NEXT: str x8, [x9, _var@PAGEOFF] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: test_inc_cycle: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: ldr s1, [x0] -; CHECK-GISEL-NEXT: adrp x9, _var@PAGE -; CHECK-GISEL-NEXT: mov.s v0[0], v1[0] -; CHECK-GISEL-NEXT: fmov x8, d0 -; CHECK-GISEL-NEXT: add x8, x0, x8, lsl #2 -; CHECK-GISEL-NEXT: str x8, [x9, _var@PAGEOFF] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: test_inc_cycle: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ld1.s { v0 }[0], [x0] +; CHECK-SD-NEXT: adrp x9, _var@PAGE +; CHECK-SD-NEXT: fmov x8, d0 +; CHECK-SD-NEXT: add x8, x0, x8, lsl #2 +; CHECK-SD-NEXT: str x8, [x9, _var@PAGEOFF] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_inc_cycle: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: ldr s1, [x0] +; CHECK-GI-NEXT: adrp x9, _var@PAGE +; CHECK-GI-NEXT: mov.s v0[0], v1[0] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: add x8, x0, x8, lsl #2 +; CHECK-GI-NEXT: str x8, [x9, _var@PAGEOFF] +; CHECK-GI-NEXT: ret %elt = load i32, ptr %in %newvec = insertelement <4 x i32> %vec, i32 %elt, i32 0 @@ -14644,69 +14023,69 @@ define <4 x i32> @test_inc_cycle(<4 x i32> %vec, ptr %in) { @var = global ptr null define i8 @load_single_extract_variable_index_i8(ptr %A, i32 %idx) { -; SDAG-LABEL: load_single_extract_variable_index_i8: -; SDAG: ; %bb.0: -; SDAG-NEXT: sub sp, sp, #16 -; SDAG-NEXT: .cfi_def_cfa_offset 16 -; SDAG-NEXT: mov x8, sp -; SDAG-NEXT: ldr q0, [x0] -; SDAG-NEXT: ; kill: def $w1 killed $w1 def $x1 -; SDAG-NEXT: bfxil x8, x1, #0, #4 -; SDAG-NEXT: str q0, [sp] -; SDAG-NEXT: ldrb w0, [x8] -; SDAG-NEXT: add sp, sp, #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: load_single_extract_variable_index_i8: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov w8, w1 -; CHECK-GISEL-NEXT: and x8, x8, #0xf -; CHECK-GISEL-NEXT: ldrb w0, [x0, x8] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: load_single_extract_variable_index_i8: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: ldr q0, [x0] +; CHECK-SD-NEXT: ; kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: bfxil x8, x1, #0, #4 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: ldrb w0, [x8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: load_single_extract_variable_index_i8: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: and x8, x8, #0xf +; CHECK-GI-NEXT: ldrb w0, [x0, x8] +; CHECK-GI-NEXT: ret %lv = load <16 x i8>, ptr %A %e = extractelement <16 x i8> %lv, i32 %idx ret i8 %e } define i16 @load_single_extract_variable_index_i16(ptr %A, i32 %idx) { -; SDAG-LABEL: load_single_extract_variable_index_i16: -; SDAG: ; %bb.0: -; SDAG-NEXT: sub sp, sp, #16 -; SDAG-NEXT: .cfi_def_cfa_offset 16 -; SDAG-NEXT: mov x8, sp -; SDAG-NEXT: ldr q0, [x0] -; SDAG-NEXT: ; kill: def $w1 killed $w1 def $x1 -; SDAG-NEXT: bfi x8, x1, #1, #3 -; SDAG-NEXT: str q0, [sp] -; SDAG-NEXT: ldrh w0, [x8] -; SDAG-NEXT: add sp, sp, #16 -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: load_single_extract_variable_index_i16: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov w8, w1 -; CHECK-GISEL-NEXT: and x8, x8, #0x7 -; CHECK-GISEL-NEXT: ldrh w0, [x0, x8, lsl #1] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: load_single_extract_variable_index_i16: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: ldr q0, [x0] +; CHECK-SD-NEXT: ; kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: bfi x8, x1, #1, #3 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: ldrh w0, [x8] +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: load_single_extract_variable_index_i16: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: and x8, x8, #0x7 +; CHECK-GI-NEXT: ldrh w0, [x0, x8, lsl #1] +; CHECK-GI-NEXT: ret %lv = load <8 x i16>, ptr %A %e = extractelement <8 x i16> %lv, i32 %idx ret i16 %e } define i32 @load_single_extract_variable_index_i32(ptr %A, i32 %idx) { -; SDAG-LABEL: load_single_extract_variable_index_i32: -; SDAG: ; %bb.0: -; SDAG-NEXT: ; kill: def $w1 killed $w1 def $x1 -; SDAG-NEXT: and x8, x1, #0x3 -; SDAG-NEXT: ldr w0, [x0, x8, lsl #2] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: load_single_extract_variable_index_i32: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: mov w8, w1 -; CHECK-GISEL-NEXT: and x8, x8, #0x3 -; CHECK-GISEL-NEXT: ldr w0, [x0, x8, lsl #2] -; CHECK-GISEL-NEXT: ret +; CHECK-SD-LABEL: load_single_extract_variable_index_i32: +; CHECK-SD: ; %bb.0: +; CHECK-SD-NEXT: ; kill: def $w1 killed $w1 def $x1 +; CHECK-SD-NEXT: and x8, x1, #0x3 +; CHECK-SD-NEXT: ldr w0, [x0, x8, lsl #2] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: load_single_extract_variable_index_i32: +; CHECK-GI: ; %bb.0: +; CHECK-GI-NEXT: mov w8, w1 +; CHECK-GI-NEXT: and x8, x8, #0x3 +; CHECK-GI-NEXT: ldr w0, [x0, x8, lsl #2] +; CHECK-GI-NEXT: ret %lv = load <4 x i32>, ptr %A %e = extractelement <4 x i32> %lv, i32 %idx ret i32 %e @@ -14751,17 +14130,11 @@ define i32 @load_single_extract_valid_const_index_v3i32(ptr %A, i32 %idx) { } define i32 @load_single_extract_variable_index_masked_i32(ptr %A, i32 %idx) { -; SDAG-LABEL: load_single_extract_variable_index_masked_i32: -; SDAG: ; %bb.0: -; SDAG-NEXT: and w8, w1, #0x3 -; SDAG-NEXT: ldr w0, [x0, w8, uxtw #2] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: load_single_extract_variable_index_masked_i32: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: and w8, w1, #0x3 -; CHECK-GISEL-NEXT: ldr w0, [x0, w8, uxtw #2] -; CHECK-GISEL-NEXT: ret +; CHECK-LABEL: load_single_extract_variable_index_masked_i32: +; CHECK: ; %bb.0: +; CHECK-NEXT: and w8, w1, #0x3 +; CHECK-NEXT: ldr w0, [x0, w8, uxtw #2] +; CHECK-NEXT: ret %idx.x = and i32 %idx, 3 %lv = load <4 x i32>, ptr %A %e = extractelement <4 x i32> %lv, i32 %idx.x @@ -14769,17 +14142,11 @@ define i32 @load_single_extract_variable_index_masked_i32(ptr %A, i32 %idx) { } define i32 @load_single_extract_variable_index_masked2_i32(ptr %A, i32 %idx) { -; SDAG-LABEL: load_single_extract_variable_index_masked2_i32: -; SDAG: ; %bb.0: -; SDAG-NEXT: and w8, w1, #0x1 -; SDAG-NEXT: ldr w0, [x0, w8, uxtw #2] -; SDAG-NEXT: ret -; -; CHECK-GISEL-LABEL: load_single_extract_variable_index_masked2_i32: -; CHECK-GISEL: ; %bb.0: -; CHECK-GISEL-NEXT: and w8, w1, #0x1 -; CHECK-GISEL-NEXT: ldr w0, [x0, w8, uxtw #2] -; CHECK-GISEL-NEXT: ret +; CHECK-LABEL: load_single_extract_variable_index_masked2_i32: +; CHECK: ; %bb.0: +; CHECK-NEXT: and w8, w1, #0x1 +; CHECK-NEXT: ldr w0, [x0, w8, uxtw #2] +; CHECK-NEXT: ret %idx.x = and i32 %idx, 1 %lv = load <4 x i32>, ptr %A %e = extractelement <4 x i32> %lv, i32 %idx.x diff --git a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll index d1bce2fbfa9f2b3f75a12f767850e023e0db2172..8c7b31fd34c488b5c13ddbd6d8152ce318514019 100644 --- a/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll +++ b/llvm/test/CodeGen/AArch64/arm64-ldp-cluster.ll @@ -1,5 +1,5 @@ ; REQUIRES: asserts -; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s +; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=cortex-a57 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s --check-prefixes=CHECK,CHECK-A57 ; RUN: llc < %s -mtriple=arm64-linux-gnu -mcpu=exynos-m3 -verify-misched -debug-only=machine-scheduler -o - 2>&1 > /dev/null | FileCheck %s ; Test ldr clustering. @@ -227,3 +227,73 @@ entry: store i64 %r53, ptr %wb ret void } + +; CHECK: ********** MI Scheduling ********** +; CHECK: STURWi_STRWui:%bb.0 entry +; CHECK: Cluster ld/st SU(3) - SU(4) +; CHECK: SU(3): STURWi %{{[0-9]+}}:gpr32 +; CHECK: SU(4): STRWui %{{[0-9]+}}:gpr32 +; +define void @STURWi_STRWui(ptr nocapture readonly %arg, i32 %b, i32 %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -4 + store i32 %b, ptr %r51 + store i32 %c, ptr %arg + ret void +} + +; CHECK: ********** MI Scheduling ********** +; CHECK: STURXi_STRXui:%bb.0 entry +; CHECK: Cluster ld/st SU(3) - SU(4) +; CHECK: SU(3): STURXi %{{[0-9]+}}:gpr64 +; CHECK: SU(4): STRXui %{{[0-9]+}}:gpr64 +; +define void @STURXi_STRXui(ptr nocapture readonly %arg, i64 %b, i64 %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -8 + store i64 %b, ptr %r51 + store i64 %c, ptr %arg + ret void +} + +; CHECK-A57: ********** MI Scheduling ********** +; CHECK-A57: STURSi_STRSui:%bb.0 entry +; CHECK-A57: Cluster ld/st SU(3) - SU(4) +; CHECK-A57: SU(3): STURSi %{{[0-9]+}}:fpr32 +; CHECK-A57: SU(4): STRSui %{{[0-9]+}}:fpr32 +; +define void @STURSi_STRSui(ptr nocapture readonly %arg, float %b, float %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -4 + store float %b, ptr %r51 + store float %c, ptr %arg + ret void +} + +; CHECK-A57: ********** MI Scheduling ********** +; CHECK-A57: STURDi_STRDui:%bb.0 entry +; CHECK-A57: Cluster ld/st SU(3) - SU(4) +; CHECK-A57: SU(3): STURDi %{{[0-9]+}}:fpr64 +; CHECK-A57: SU(4): STRDui %{{[0-9]+}}:fpr64 +; +define void @STURDi_STRDui(ptr nocapture readonly %arg, <2 x float> %b, <2 x float> %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -8 + store <2 x float> %b, ptr %r51 + store <2 x float> %c, ptr %arg + ret void +} + +; CHECK-A57: ********** MI Scheduling ********** +; CHECK-A57: STURQi_STRQui:%bb.0 entry +; CHECK-A57: Cluster ld/st SU(3) - SU(4) +; CHECK-A57: SU(3): STURQi %{{[0-9]+}}:fpr128 +; CHECK-A57: SU(4): STRQui %{{[0-9]+}}:fpr128 +; +define void @STURQi_STRQui(ptr nocapture readonly %arg, <2 x double> %b, <2 x double> %c) { +entry: + %r51 = getelementptr i8, ptr %arg, i64 -16 + store <2 x double> %b, ptr %r51 + store <2 x double> %c, ptr %arg + ret void +} diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll index 8f322ab1c3623300f3af957872f56565617ea2f9..328b782c14956c987ac880d572ab38ba618866a4 100644 --- a/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll +++ b/llvm/test/CodeGen/AArch64/arm64-neon-copy.ll @@ -1,5 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -fp-contract=fast | FileCheck %s +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s --check-prefixes=CHECK,CHECK-SD +; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI + +; CHECK-GI: warning: Instruction selection used fallback path for test_bitcastv2f32tov1f64 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_bitcastv1f64tov2f32 +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_extracts_inserts_varidx_insert +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_v1i32_undef +; CHECK-GI-NEXT: warning: Instruction selection used fallback path for test_concat_diff_v1i32_v1i32 define <16 x i8> @ins16bw(<16 x i8> %tmp1, i8 %tmp2) { ; CHECK-LABEL: ins16bw: @@ -71,33 +78,54 @@ define <2 x i32> @ins2sw(<2 x i32> %tmp1, i32 %tmp2) { } define <16 x i8> @ins16b16(<16 x i8> %tmp1, <16 x i8> %tmp2) { -; CHECK-LABEL: ins16b16: -; CHECK: // %bb.0: -; CHECK-NEXT: mov v1.b[15], v0.b[2] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins16b16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov v1.b[15], v0.b[2] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins16b16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov b2, v0.b[2] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.b[15], v2.b[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <16 x i8> %tmp1, i32 2 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15 ret <16 x i8> %tmp4 } define <8 x i16> @ins8h8(<8 x i16> %tmp1, <8 x i16> %tmp2) { -; CHECK-LABEL: ins8h8: -; CHECK: // %bb.0: -; CHECK-NEXT: mov v1.h[7], v0.h[2] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins8h8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov v1.h[7], v0.h[2] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins8h8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov h2, v0.h[2] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.h[7], v2.h[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <8 x i16> %tmp1, i32 2 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7 ret <8 x i16> %tmp4 } define <4 x i32> @ins4s4(<4 x i32> %tmp1, <4 x i32> %tmp2) { -; CHECK-LABEL: ins4s4: -; CHECK: // %bb.0: -; CHECK-NEXT: mov v1.s[1], v0.s[2] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins4s4: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins4s4: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov s2, v0.s[2] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1 ret <4 x i32> %tmp4 @@ -115,11 +143,18 @@ define <2 x i64> @ins2d2(<2 x i64> %tmp1, <2 x i64> %tmp2) { } define <4 x float> @ins4f4(<4 x float> %tmp1, <4 x float> %tmp2) { -; CHECK-LABEL: ins4f4: -; CHECK: // %bb.0: -; CHECK-NEXT: mov v1.s[1], v0.s[2] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins4f4: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins4f4: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov s2, v0.s[2] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x float> %tmp1, i32 2 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1 ret <4 x float> %tmp4 @@ -137,36 +172,60 @@ define <2 x double> @ins2df2(<2 x double> %tmp1, <2 x double> %tmp2) { } define <16 x i8> @ins8b16(<8 x i8> %tmp1, <16 x i8> %tmp2) { -; CHECK-LABEL: ins8b16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v1.b[15], v0.b[2] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins8b16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v1.b[15], v0.b[2] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins8b16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov b2, v0.b[2] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.b[15], v2.b[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <8 x i8> %tmp1, i32 2 %tmp4 = insertelement <16 x i8> %tmp2, i8 %tmp3, i32 15 ret <16 x i8> %tmp4 } define <8 x i16> @ins4h8(<4 x i16> %tmp1, <8 x i16> %tmp2) { -; CHECK-LABEL: ins4h8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v1.h[7], v0.h[2] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins4h8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v1.h[7], v0.h[2] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins4h8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov h2, v0.h[2] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.h[7], v2.h[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x i16> %tmp1, i32 2 %tmp4 = insertelement <8 x i16> %tmp2, i16 %tmp3, i32 7 ret <8 x i16> %tmp4 } define <4 x i32> @ins2s4(<2 x i32> %tmp1, <4 x i32> %tmp2) { -; CHECK-LABEL: ins2s4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v1.s[1], v0.s[1] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins2s4: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v1.s[1], v0.s[1] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins2s4: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s2, v0.s[1] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <2 x i32> %tmp1, i32 1 %tmp4 = insertelement <4 x i32> %tmp2, i32 %tmp3, i32 1 ret <4 x i32> %tmp4 @@ -185,12 +244,20 @@ define <2 x i64> @ins1d2(<1 x i64> %tmp1, <2 x i64> %tmp2) { } define <4 x float> @ins2f4(<2 x float> %tmp1, <4 x float> %tmp2) { -; CHECK-LABEL: ins2f4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v1.s[1], v0.s[1] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins2f4: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v1.s[1], v0.s[1] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins2f4: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s2, v0.s[1] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <2 x float> %tmp1, i32 1 %tmp4 = insertelement <4 x float> %tmp2, float %tmp3, i32 1 ret <4 x float> %tmp4 @@ -220,36 +287,60 @@ define <2 x double> @ins1f2_args_flipped(<2 x double> %tmp2, <1 x double> %tmp1) } define <8 x i8> @ins16b8(<16 x i8> %tmp1, <8 x i8> %tmp2) { -; CHECK-LABEL: ins16b8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v1.b[7], v0.b[2] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins16b8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v1.b[7], v0.b[2] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins16b8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov b2, v0.b[2] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: mov v0.b[7], v2.b[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <16 x i8> %tmp1, i32 2 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 7 ret <8 x i8> %tmp4 } define <4 x i16> @ins8h4(<8 x i16> %tmp1, <4 x i16> %tmp2) { -; CHECK-LABEL: ins8h4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v1.h[3], v0.h[2] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins8h4: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v1.h[3], v0.h[2] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins8h4: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov h2, v0.h[2] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: mov v0.h[3], v2.h[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <8 x i16> %tmp1, i32 2 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3 ret <4 x i16> %tmp4 } define <2 x i32> @ins4s2(<4 x i32> %tmp1, <2 x i32> %tmp2) { -; CHECK-LABEL: ins4s2: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v1.s[1], v0.s[2] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins4s2: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins4s2: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov s2, v0.s[2] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 %tmp4 = insertelement <2 x i32> %tmp2, i32 %tmp3, i32 1 ret <2 x i32> %tmp4 @@ -266,49 +357,80 @@ define <1 x i64> @ins2d1(<2 x i64> %tmp1, <1 x i64> %tmp2) { } define <2 x float> @ins4f2(<4 x float> %tmp1, <2 x float> %tmp2) { -; CHECK-LABEL: ins4f2: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v1.s[1], v0.s[2] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins4f2: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v1.s[1], v0.s[2] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins4f2: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov s2, v0.s[2] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x float> %tmp1, i32 2 %tmp4 = insertelement <2 x float> %tmp2, float %tmp3, i32 1 ret <2 x float> %tmp4 } define <1 x double> @ins2f1(<2 x double> %tmp1, <1 x double> %tmp2) { -; CHECK-LABEL: ins2f1: -; CHECK: // %bb.0: -; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins2f1: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: ext v0.16b, v0.16b, v0.16b, #8 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins2f1: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov d0, v0.d[1] +; CHECK-GI-NEXT: ret %tmp3 = extractelement <2 x double> %tmp1, i32 1 %tmp4 = insertelement <1 x double> %tmp2, double %tmp3, i32 0 ret <1 x double> %tmp4 } define <8 x i8> @ins8b8(<8 x i8> %tmp1, <8 x i8> %tmp2) { -; CHECK-LABEL: ins8b8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v1.b[4], v0.b[2] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins8b8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v1.b[4], v0.b[2] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins8b8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov b2, v0.b[2] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: mov v0.b[4], v2.b[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <8 x i8> %tmp1, i32 2 %tmp4 = insertelement <8 x i8> %tmp2, i8 %tmp3, i32 4 ret <8 x i8> %tmp4 } define <4 x i16> @ins4h4(<4 x i16> %tmp1, <4 x i16> %tmp2) { -; CHECK-LABEL: ins4h4: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v1.h[3], v0.h[2] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: ins4h4: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v1.h[3], v0.h[2] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: ins4h4: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov h2, v0.h[2] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: mov v0.h[3], v2.h[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x i16> %tmp1, i32 2 %tmp4 = insertelement <4 x i16> %tmp2, i16 %tmp3, i32 3 ret <4 x i16> %tmp4 @@ -379,19 +501,31 @@ define i32 @umovw8h(<8 x i16> %tmp1) { } define i32 @umovw4s(<4 x i32> %tmp1) { -; CHECK-LABEL: umovw4s: -; CHECK: // %bb.0: -; CHECK-NEXT: mov w0, v0.s[2] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: umovw4s: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov w0, v0.s[2] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: umovw4s: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov s0, v0.s[2] +; CHECK-GI-NEXT: fmov w0, s0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <4 x i32> %tmp1, i32 2 ret i32 %tmp3 } define i64 @umovx2d(<2 x i64> %tmp1) { -; CHECK-LABEL: umovx2d: -; CHECK: // %bb.0: -; CHECK-NEXT: mov x0, v0.d[1] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: umovx2d: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov x0, v0.d[1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: umovx2d: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov d0, v0.d[1] +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <2 x i64> %tmp1, i32 1 ret i64 %tmp3 } @@ -419,21 +553,33 @@ define i32 @umovw4h(<4 x i16> %tmp1) { } define i32 @umovw2s(<2 x i32> %tmp1) { -; CHECK-LABEL: umovw2s: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov w0, v0.s[1] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: umovw2s: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov w0, v0.s[1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: umovw2s: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s0, v0.s[1] +; CHECK-GI-NEXT: fmov w0, s0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <2 x i32> %tmp1, i32 1 ret i32 %tmp3 } define i64 @umovx1d(<1 x i64> %tmp1) { -; CHECK-LABEL: umovx1d: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: fmov x0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: umovx1d: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: fmov x0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: umovx1d: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x0, d0 +; CHECK-GI-NEXT: ret %tmp3 = extractelement <1 x i64> %tmp1, i32 0 ret i64 %tmp3 } @@ -552,22 +698,37 @@ define i64 @smovx2s(<2 x i32> %tmp1) { } define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) { -; CHECK-LABEL: test_vcopy_lane_s8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.b[5], v1.b[3] -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_vcopy_lane_s8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.b[5], v1.b[3] +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_vcopy_lane_s8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov b1, v1.b[3] +; CHECK-GI-NEXT: mov v0.b[5], v1.b[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> ret <8 x i8> %vset_lane } define <16 x i8> @test_vcopyq_laneq_s8(<16 x i8> %v1, <16 x i8> %v2) { -; CHECK-LABEL: test_vcopyq_laneq_s8: -; CHECK: // %bb.0: -; CHECK-NEXT: mov v0.b[14], v1.b[6] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_vcopyq_laneq_s8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov v0.b[14], v1.b[6] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_vcopyq_laneq_s8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov b1, v1.b[6] +; CHECK-GI-NEXT: mov v0.b[14], v1.b[0] +; CHECK-GI-NEXT: ret %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> ret <16 x i8> %vset_lane } @@ -585,11 +746,18 @@ define <8 x i8> @test_vcopy_lane_swap_s8(<8 x i8> %v1, <8 x i8> %v2) { } define <16 x i8> @test_vcopyq_laneq_swap_s8(<16 x i8> %v1, <16 x i8> %v2) { -; CHECK-LABEL: test_vcopyq_laneq_swap_s8: -; CHECK: // %bb.0: -; CHECK-NEXT: mov v1.b[0], v0.b[15] -; CHECK-NEXT: mov v0.16b, v1.16b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_vcopyq_laneq_swap_s8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: mov v1.b[0], v0.b[15] +; CHECK-SD-NEXT: mov v0.16b, v1.16b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_vcopyq_laneq_swap_s8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov b2, v0.b[15] +; CHECK-GI-NEXT: mov v0.16b, v1.16b +; CHECK-GI-NEXT: mov v0.b[0], v2.b[0] +; CHECK-GI-NEXT: ret %vset_lane = shufflevector <16 x i8> %v1, <16 x i8> %v2, <16 x i32> ret <16 x i8> %vset_lane } @@ -774,28 +942,46 @@ define <2 x i64> @test_vdupq_lane_s64(<1 x i64> %v1) #0 { } define <8 x i8> @test_vdup_laneq_s8(<16 x i8> %v1) #0 { -; CHECK-LABEL: test_vdup_laneq_s8: -; CHECK: // %bb.0: -; CHECK-NEXT: dup v0.8b, v0.b[5] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_vdup_laneq_s8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: dup v0.8b, v0.b[5] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_vdup_laneq_s8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: dup v0.16b, v0.b[5] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %shuffle = shufflevector <16 x i8> %v1, <16 x i8> undef, <8 x i32> ret <8 x i8> %shuffle } define <4 x i16> @test_vdup_laneq_s16(<8 x i16> %v1) #0 { -; CHECK-LABEL: test_vdup_laneq_s16: -; CHECK: // %bb.0: -; CHECK-NEXT: dup v0.4h, v0.h[2] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_vdup_laneq_s16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: dup v0.4h, v0.h[2] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_vdup_laneq_s16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: dup v0.8h, v0.h[2] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %shuffle = shufflevector <8 x i16> %v1, <8 x i16> undef, <4 x i32> ret <4 x i16> %shuffle } define <2 x i32> @test_vdup_laneq_s32(<4 x i32> %v1) #0 { -; CHECK-LABEL: test_vdup_laneq_s32: -; CHECK: // %bb.0: -; CHECK-NEXT: dup v0.2s, v0.s[1] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_vdup_laneq_s32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: dup v0.2s, v0.s[1] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_vdup_laneq_s32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: dup v0.4s, v0.s[1] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %shuffle = shufflevector <4 x i32> %v1, <4 x i32> undef, <2 x i32> ret <2 x i32> %shuffle } @@ -984,12 +1170,21 @@ define <1 x i64> @test_bitcastv2i32tov1f64(<2 x i32> %a) #0 { } define <1 x i64> @test_bitcastv1i64tov1f64(<1 x i64> %a) #0 { -; CHECK-LABEL: test_bitcastv1i64tov1f64: -; CHECK: // %bb.0: -; CHECK-NEXT: neg d0, d0 -; CHECK-NEXT: fcvtzs x8, d0 -; CHECK-NEXT: fmov d0, x8 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bitcastv1i64tov1f64: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: neg d0, d0 +; CHECK-SD-NEXT: fcvtzs x8, d0 +; CHECK-SD-NEXT: fmov d0, x8 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bitcastv1i64tov1f64: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: neg x8, x8 +; CHECK-GI-NEXT: fmov d0, x8 +; CHECK-GI-NEXT: fcvtzs x8, d0 +; CHECK-GI-NEXT: fmov d0, x8 +; CHECK-GI-NEXT: ret %sub.i = sub <1 x i64> zeroinitializer, %a %1 = bitcast <1 x i64> %sub.i to <1 x double> %vcvt.i = fptosi <1 x double> %1 to <1 x i64> @@ -1010,13 +1205,19 @@ define <1 x i64> @test_bitcastv2f32tov1f64(<2 x float> %a) #0 { } define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 { -; CHECK-LABEL: test_bitcastv1f64tov8i8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: fmov x8, d0 -; CHECK-NEXT: scvtf d0, x8 -; CHECK-NEXT: neg v0.8b, v0.8b -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bitcastv1f64tov8i8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: fmov x8, d0 +; CHECK-SD-NEXT: scvtf d0, x8 +; CHECK-SD-NEXT: neg v0.8b, v0.8b +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bitcastv1f64tov8i8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: scvtf d0, d0 +; CHECK-GI-NEXT: neg v0.8b, v0.8b +; CHECK-GI-NEXT: ret %vcvt.i = sitofp <1 x i64> %a to <1 x double> %1 = bitcast <1 x double> %vcvt.i to <8 x i8> %sub.i = sub <8 x i8> zeroinitializer, %1 @@ -1024,13 +1225,19 @@ define <8 x i8> @test_bitcastv1f64tov8i8(<1 x i64> %a) #0 { } define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 { -; CHECK-LABEL: test_bitcastv1f64tov4i16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: fmov x8, d0 -; CHECK-NEXT: scvtf d0, x8 -; CHECK-NEXT: neg v0.4h, v0.4h -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bitcastv1f64tov4i16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: fmov x8, d0 +; CHECK-SD-NEXT: scvtf d0, x8 +; CHECK-SD-NEXT: neg v0.4h, v0.4h +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bitcastv1f64tov4i16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: scvtf d0, d0 +; CHECK-GI-NEXT: neg v0.4h, v0.4h +; CHECK-GI-NEXT: ret %vcvt.i = sitofp <1 x i64> %a to <1 x double> %1 = bitcast <1 x double> %vcvt.i to <4 x i16> %sub.i = sub <4 x i16> zeroinitializer, %1 @@ -1038,13 +1245,19 @@ define <4 x i16> @test_bitcastv1f64tov4i16(<1 x i64> %a) #0 { } define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 { -; CHECK-LABEL: test_bitcastv1f64tov2i32: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: fmov x8, d0 -; CHECK-NEXT: scvtf d0, x8 -; CHECK-NEXT: neg v0.2s, v0.2s -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bitcastv1f64tov2i32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: fmov x8, d0 +; CHECK-SD-NEXT: scvtf d0, x8 +; CHECK-SD-NEXT: neg v0.2s, v0.2s +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bitcastv1f64tov2i32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: scvtf d0, d0 +; CHECK-GI-NEXT: neg v0.2s, v0.2s +; CHECK-GI-NEXT: ret %vcvt.i = sitofp <1 x i64> %a to <1 x double> %1 = bitcast <1 x double> %vcvt.i to <2 x i32> %sub.i = sub <2 x i32> zeroinitializer, %1 @@ -1052,13 +1265,21 @@ define <2 x i32> @test_bitcastv1f64tov2i32(<1 x i64> %a) #0 { } define <1 x i64> @test_bitcastv1f64tov1i64(<1 x i64> %a) #0 { -; CHECK-LABEL: test_bitcastv1f64tov1i64: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: fmov x8, d0 -; CHECK-NEXT: scvtf d0, x8 -; CHECK-NEXT: neg d0, d0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_bitcastv1f64tov1i64: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: fmov x8, d0 +; CHECK-SD-NEXT: scvtf d0, x8 +; CHECK-SD-NEXT: neg d0, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_bitcastv1f64tov1i64: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: scvtf d0, d0 +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: neg x8, x8 +; CHECK-GI-NEXT: fmov d0, x8 +; CHECK-GI-NEXT: ret %vcvt.i = sitofp <1 x i64> %a to <1 x double> %1 = bitcast <1 x double> %vcvt.i to <1 x i64> %sub.i = sub <1 x i64> zeroinitializer, %1 @@ -1117,38 +1338,65 @@ define <8 x i16> @scalar_to_vector.v8i16(i16 %a) { } define <2 x i32> @scalar_to_vector.v2i32(i32 %a) { -; CHECK-LABEL: scalar_to_vector.v2i32: -; CHECK: // %bb.0: -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: scalar_to_vector.v2i32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: fmov s0, w0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: scalar_to_vector.v2i32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov s0, w0 +; CHECK-GI-NEXT: mov v0.s[1], w8 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %b = insertelement <2 x i32> undef, i32 %a, i32 0 ret <2 x i32> %b } define <4 x i32> @scalar_to_vector.v4i32(i32 %a) { -; CHECK-LABEL: scalar_to_vector.v4i32: -; CHECK: // %bb.0: -; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: scalar_to_vector.v4i32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: fmov s0, w0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: scalar_to_vector.v4i32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov s0, w0 +; CHECK-GI-NEXT: mov v0.s[1], w8 +; CHECK-GI-NEXT: mov v0.s[2], w8 +; CHECK-GI-NEXT: mov v0.s[3], w8 +; CHECK-GI-NEXT: ret %b = insertelement <4 x i32> undef, i32 %a, i32 0 ret <4 x i32> %b } define <2 x i64> @scalar_to_vector.v2i64(i64 %a) { -; CHECK-LABEL: scalar_to_vector.v2i64: -; CHECK: // %bb.0: -; CHECK-NEXT: fmov d0, x0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: scalar_to_vector.v2i64: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: fmov d0, x0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: scalar_to_vector.v2i64: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov d0, x0 +; CHECK-GI-NEXT: mov v0.d[1], x8 +; CHECK-GI-NEXT: ret %b = insertelement <2 x i64> undef, i64 %a, i32 0 ret <2 x i64> %b } define <8 x i8> @testDUP.v1i8(<1 x i8> %a) { -; CHECK-LABEL: testDUP.v1i8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.8b, v0.b[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: testDUP.v1i8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.8b, v0.b[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: testDUP.v1i8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.8b, w8 +; CHECK-GI-NEXT: ret %b = extractelement <1 x i8> %a, i32 0 %c = insertelement <8 x i8> undef, i8 %b, i32 0 %d = insertelement <8 x i8> %c, i8 %b, i32 1 @@ -1162,11 +1410,17 @@ define <8 x i8> @testDUP.v1i8(<1 x i8> %a) { } define <8 x i16> @testDUP.v1i16(<1 x i16> %a) { -; CHECK-LABEL: testDUP.v1i16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.8h, v0.h[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: testDUP.v1i16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.8h, v0.h[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: testDUP.v1i16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.8h, w8 +; CHECK-GI-NEXT: ret %b = extractelement <1 x i16> %a, i32 0 %c = insertelement <8 x i16> undef, i16 %b, i32 0 %d = insertelement <8 x i16> %c, i16 %b, i32 1 @@ -1180,11 +1434,17 @@ define <8 x i16> @testDUP.v1i16(<1 x i16> %a) { } define <4 x i32> @testDUP.v1i32(<1 x i32> %a) { -; CHECK-LABEL: testDUP.v1i32: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.4s, v0.s[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: testDUP.v1i32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.4s, v0.s[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: testDUP.v1i32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.4s, w8 +; CHECK-GI-NEXT: ret %b = extractelement <1 x i32> %a, i32 0 %c = insertelement <4 x i32> undef, i32 %b, i32 0 %d = insertelement <4 x i32> %c, i32 %b, i32 1 @@ -1194,10 +1454,29 @@ define <4 x i32> @testDUP.v1i32(<1 x i32> %a) { } define <8 x i8> @getl(<16 x i8> %x) #0 { -; CHECK-LABEL: getl: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: getl: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: getl: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: mov b1, v0.b[1] +; CHECK-GI-NEXT: mov b2, v0.b[2] +; CHECK-GI-NEXT: mov b3, v0.b[3] +; CHECK-GI-NEXT: mov b4, v0.b[4] +; CHECK-GI-NEXT: mov b5, v0.b[5] +; CHECK-GI-NEXT: mov b6, v0.b[6] +; CHECK-GI-NEXT: mov b7, v0.b[7] +; CHECK-GI-NEXT: mov v0.b[1], v1.b[0] +; CHECK-GI-NEXT: mov v0.b[2], v2.b[0] +; CHECK-GI-NEXT: mov v0.b[3], v3.b[0] +; CHECK-GI-NEXT: mov v0.b[4], v4.b[0] +; CHECK-GI-NEXT: mov v0.b[5], v5.b[0] +; CHECK-GI-NEXT: mov v0.b[6], v6.b[0] +; CHECK-GI-NEXT: mov v0.b[7], v7.b[0] +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret %vecext = extractelement <16 x i8> %x, i32 0 %vecinit = insertelement <8 x i8> undef, i8 %vecext, i32 0 %vecext1 = extractelement <16 x i8> %x, i32 1 @@ -1218,21 +1497,40 @@ define <8 x i8> @getl(<16 x i8> %x) #0 { } define <4 x i16> @test_extracts_inserts_varidx_extract(<8 x i16> %x, i32 %idx) { -; CHECK-LABEL: test_extracts_inserts_varidx_extract: -; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: mov x8, sp -; CHECK-NEXT: // kill: def $w0 killed $w0 def $x0 -; CHECK-NEXT: str q0, [sp] -; CHECK-NEXT: bfi x8, x0, #1, #3 -; CHECK-NEXT: ldr h1, [x8] -; CHECK-NEXT: mov v1.h[1], v0.h[1] -; CHECK-NEXT: mov v1.h[2], v0.h[2] -; CHECK-NEXT: mov v1.h[3], v0.h[3] -; CHECK-NEXT: fmov d0, d1 -; CHECK-NEXT: add sp, sp, #16 -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_extracts_inserts_varidx_extract: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: sub sp, sp, #16 +; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 +; CHECK-SD-NEXT: mov x8, sp +; CHECK-SD-NEXT: // kill: def $w0 killed $w0 def $x0 +; CHECK-SD-NEXT: str q0, [sp] +; CHECK-SD-NEXT: bfi x8, x0, #1, #3 +; CHECK-SD-NEXT: ldr h1, [x8] +; CHECK-SD-NEXT: mov v1.h[1], v0.h[1] +; CHECK-SD-NEXT: mov v1.h[2], v0.h[2] +; CHECK-SD-NEXT: mov v1.h[3], v0.h[3] +; CHECK-SD-NEXT: fmov d0, d1 +; CHECK-SD-NEXT: add sp, sp, #16 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_extracts_inserts_varidx_extract: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: sub sp, sp, #16 +; CHECK-GI-NEXT: .cfi_def_cfa_offset 16 +; CHECK-GI-NEXT: mov w9, w0 +; CHECK-GI-NEXT: mov h2, v0.h[1] +; CHECK-GI-NEXT: mov x8, sp +; CHECK-GI-NEXT: str q0, [sp] +; CHECK-GI-NEXT: and x9, x9, #0x7 +; CHECK-GI-NEXT: mov h3, v0.h[2] +; CHECK-GI-NEXT: ldr h1, [x8, x9, lsl #1] +; CHECK-GI-NEXT: mov h0, v0.h[3] +; CHECK-GI-NEXT: mov v1.h[1], v2.h[0] +; CHECK-GI-NEXT: mov v1.h[2], v3.h[0] +; CHECK-GI-NEXT: mov v1.h[3], v0.h[0] +; CHECK-GI-NEXT: fmov d0, d1 +; CHECK-GI-NEXT: add sp, sp, #16 +; CHECK-GI-NEXT: ret %tmp = extractelement <8 x i16> %x, i32 %idx %tmp2 = insertelement <4 x i16> undef, i16 %tmp, i32 0 %tmp3 = extractelement <8 x i16> %x, i32 1 @@ -1272,11 +1570,19 @@ define <4 x i16> @test_extracts_inserts_varidx_insert(<8 x i16> %x, i32 %idx) { } define <4 x i16> @test_dup_v2i32_v4i16(<2 x i32> %a) { -; CHECK-LABEL: test_dup_v2i32_v4i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.4h, v0.h[2] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v2i32_v4i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.4h, v0.h[2] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v2i32_v4i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov s0, v0.s[1] +; CHECK-GI-NEXT: fmov w8, s0 +; CHECK-GI-NEXT: dup v0.4h, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <2 x i32> %a, i32 1 %vget_lane = trunc i32 %x to i16 @@ -1288,10 +1594,17 @@ entry: } define <8 x i16> @test_dup_v4i32_v8i16(<4 x i32> %a) { -; CHECK-LABEL: test_dup_v4i32_v8i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: dup v0.8h, v0.h[6] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v4i32_v8i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: dup v0.8h, v0.h[6] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v4i32_v8i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov s0, v0.s[3] +; CHECK-GI-NEXT: fmov w8, s0 +; CHECK-GI-NEXT: dup v0.8h, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <4 x i32> %a, i32 3 %vget_lane = trunc i32 %x to i16 @@ -1307,11 +1620,17 @@ entry: } define <4 x i16> @test_dup_v1i64_v4i16(<1 x i64> %a) { -; CHECK-LABEL: test_dup_v1i64_v4i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.4h, v0.h[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v1i64_v4i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.4h, v0.h[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v1i64_v4i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.4h, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <1 x i64> %a, i32 0 %vget_lane = trunc i64 %x to i16 @@ -1323,11 +1642,17 @@ entry: } define <2 x i32> @test_dup_v1i64_v2i32(<1 x i64> %a) { -; CHECK-LABEL: test_dup_v1i64_v2i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.2s, v0.s[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v1i64_v2i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.2s, v0.s[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v1i64_v2i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.2s, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <1 x i64> %a, i32 0 %vget_lane = trunc i64 %x to i32 @@ -1337,10 +1662,17 @@ entry: } define <8 x i16> @test_dup_v2i64_v8i16(<2 x i64> %a) { -; CHECK-LABEL: test_dup_v2i64_v8i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: dup v0.8h, v0.h[4] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v2i64_v8i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: dup v0.8h, v0.h[4] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v2i64_v8i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov d0, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.8h, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <2 x i64> %a, i32 1 %vget_lane = trunc i64 %x to i16 @@ -1356,10 +1688,17 @@ entry: } define <4 x i32> @test_dup_v2i64_v4i32(<2 x i64> %a) { -; CHECK-LABEL: test_dup_v2i64_v4i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: dup v0.4s, v0.s[2] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v2i64_v4i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: dup v0.4s, v0.s[2] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v2i64_v4i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov d0, v0.d[1] +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.4s, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <2 x i64> %a, i32 1 %vget_lane = trunc i64 %x to i32 @@ -1371,10 +1710,17 @@ entry: } define <4 x i16> @test_dup_v4i32_v4i16(<4 x i32> %a) { -; CHECK-LABEL: test_dup_v4i32_v4i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: dup v0.4h, v0.h[2] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v4i32_v4i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: dup v0.4h, v0.h[2] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v4i32_v4i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov s0, v0.s[1] +; CHECK-GI-NEXT: fmov w8, s0 +; CHECK-GI-NEXT: dup v0.4h, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <4 x i32> %a, i32 1 %vget_lane = trunc i32 %x to i16 @@ -1386,10 +1732,16 @@ entry: } define <4 x i16> @test_dup_v2i64_v4i16(<2 x i64> %a) { -; CHECK-LABEL: test_dup_v2i64_v4i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: dup v0.4h, v0.h[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v2i64_v4i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: dup v0.4h, v0.h[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v2i64_v4i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.4h, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <2 x i64> %a, i32 0 %vget_lane = trunc i64 %x to i16 @@ -1401,10 +1753,16 @@ entry: } define <2 x i32> @test_dup_v2i64_v2i32(<2 x i64> %a) { -; CHECK-LABEL: test_dup_v2i64_v2i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: dup v0.2s, v0.s[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_dup_v2i64_v2i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: dup v0.2s, v0.s[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_dup_v2i64_v2i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.2s, w8 +; CHECK-GI-NEXT: ret entry: %x = extractelement <2 x i64> %a, i32 0 %vget_lane = trunc i64 %x to i32 @@ -1443,11 +1801,18 @@ entry: declare float @llvm.aarch64.neon.fmaxv.f32.v2f32(<2 x float>) define <2 x i32> @test_concat_undef_v1i32(<2 x i32> %a) { -; CHECK-LABEL: test_concat_undef_v1i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.2s, v0.s[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_undef_v1i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.2s, v0.s[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_undef_v1i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov w8, s0 +; CHECK-GI-NEXT: mov v0.s[1], w8 +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-GI-NEXT: ret entry: %0 = extractelement <2 x i32> %a, i32 0 %vecinit1.i = insertelement <2 x i32> undef, i32 %0, i32 1 @@ -1502,21 +1867,61 @@ entry: } define <16 x i8> @test_concat_v16i8_v16i8_v16i8(<16 x i8> %x, <16 x i8> %y) #0 { -; CHECK-LABEL: test_concat_v16i8_v16i8_v16i8: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v16i8_v16i8_v16i8: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v16i8_v16i8_v16i8: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: adrp x8, .LCPI126_0 +; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI126_0] +; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-GI-NEXT: ret entry: %vecinit30 = shufflevector <16 x i8> %x, <16 x i8> %y, <16 x i32> ret <16 x i8> %vecinit30 } define <16 x i8> @test_concat_v16i8_v8i8_v16i8(<8 x i8> %x, <16 x i8> %y) #0 { -; CHECK-LABEL: test_concat_v16i8_v8i8_v16i8: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v16i8_v8i8_v16i8: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v16i8: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: adrp x8, .LCPI127_0 +; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: mov b2, v0.b[1] +; CHECK-GI-NEXT: mov b3, v0.b[2] +; CHECK-GI-NEXT: mov b4, v0.b[3] +; CHECK-GI-NEXT: mov b5, v0.b[4] +; CHECK-GI-NEXT: mov b6, v0.b[5] +; CHECK-GI-NEXT: mov b7, v0.b[6] +; CHECK-GI-NEXT: mov b16, v0.b[7] +; CHECK-GI-NEXT: mov v0.b[1], v2.b[0] +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI127_0] +; CHECK-GI-NEXT: mov v0.b[2], v3.b[0] +; CHECK-GI-NEXT: mov v0.b[3], v4.b[0] +; CHECK-GI-NEXT: mov v0.b[4], v5.b[0] +; CHECK-GI-NEXT: mov v0.b[5], v6.b[0] +; CHECK-GI-NEXT: mov v0.b[6], v7.b[0] +; CHECK-GI-NEXT: mov v0.b[7], v16.b[0] +; CHECK-GI-NEXT: mov v0.b[8], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[9], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[10], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[11], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[12], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[13], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[14], v0.b[0] +; CHECK-GI-NEXT: mov v0.b[15], v0.b[0] +; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <8 x i8> %x, i32 0 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0 @@ -1539,11 +1944,45 @@ entry: } define <16 x i8> @test_concat_v16i8_v16i8_v8i8(<16 x i8> %x, <8 x i8> %y) #0 { -; CHECK-LABEL: test_concat_v16i8_v16i8_v8i8: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v16i8_v16i8_v8i8: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v16i8_v16i8_v8i8: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov b2, v0.b[1] +; CHECK-GI-NEXT: mov b3, v0.b[2] +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov b4, v0.b[3] +; CHECK-GI-NEXT: mov b5, v0.b[4] +; CHECK-GI-NEXT: mov b6, v0.b[5] +; CHECK-GI-NEXT: mov b7, v0.b[6] +; CHECK-GI-NEXT: mov b16, v0.b[7] +; CHECK-GI-NEXT: mov v0.b[1], v2.b[0] +; CHECK-GI-NEXT: mov b2, v1.b[1] +; CHECK-GI-NEXT: mov v0.b[2], v3.b[0] +; CHECK-GI-NEXT: mov b3, v1.b[2] +; CHECK-GI-NEXT: mov v0.b[3], v4.b[0] +; CHECK-GI-NEXT: mov v0.b[4], v5.b[0] +; CHECK-GI-NEXT: mov v0.b[5], v6.b[0] +; CHECK-GI-NEXT: mov v0.b[6], v7.b[0] +; CHECK-GI-NEXT: mov v0.b[7], v16.b[0] +; CHECK-GI-NEXT: mov v0.b[8], v1.b[0] +; CHECK-GI-NEXT: mov v0.b[9], v2.b[0] +; CHECK-GI-NEXT: mov b2, v1.b[3] +; CHECK-GI-NEXT: mov v0.b[10], v3.b[0] +; CHECK-GI-NEXT: mov b3, v1.b[4] +; CHECK-GI-NEXT: mov v0.b[11], v2.b[0] +; CHECK-GI-NEXT: mov b2, v1.b[5] +; CHECK-GI-NEXT: mov v0.b[12], v3.b[0] +; CHECK-GI-NEXT: mov b3, v1.b[6] +; CHECK-GI-NEXT: mov b1, v1.b[7] +; CHECK-GI-NEXT: mov v0.b[13], v2.b[0] +; CHECK-GI-NEXT: mov v0.b[14], v3.b[0] +; CHECK-GI-NEXT: mov v0.b[15], v1.b[0] +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <16 x i8> %x, i32 0 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0 @@ -1581,12 +2020,47 @@ entry: } define <16 x i8> @test_concat_v16i8_v8i8_v8i8(<8 x i8> %x, <8 x i8> %y) #0 { -; CHECK-LABEL: test_concat_v16i8_v8i8_v8i8: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v16i8_v8i8_v8i8: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v16i8_v8i8_v8i8: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov b2, v0.b[1] +; CHECK-GI-NEXT: mov b3, v0.b[2] +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov b4, v0.b[3] +; CHECK-GI-NEXT: mov b5, v0.b[4] +; CHECK-GI-NEXT: mov b6, v0.b[5] +; CHECK-GI-NEXT: mov b7, v0.b[6] +; CHECK-GI-NEXT: mov b16, v0.b[7] +; CHECK-GI-NEXT: mov v0.b[1], v2.b[0] +; CHECK-GI-NEXT: mov b2, v1.b[1] +; CHECK-GI-NEXT: mov v0.b[2], v3.b[0] +; CHECK-GI-NEXT: mov b3, v1.b[2] +; CHECK-GI-NEXT: mov v0.b[3], v4.b[0] +; CHECK-GI-NEXT: mov v0.b[4], v5.b[0] +; CHECK-GI-NEXT: mov v0.b[5], v6.b[0] +; CHECK-GI-NEXT: mov v0.b[6], v7.b[0] +; CHECK-GI-NEXT: mov v0.b[7], v16.b[0] +; CHECK-GI-NEXT: mov v0.b[8], v1.b[0] +; CHECK-GI-NEXT: mov v0.b[9], v2.b[0] +; CHECK-GI-NEXT: mov b2, v1.b[3] +; CHECK-GI-NEXT: mov v0.b[10], v3.b[0] +; CHECK-GI-NEXT: mov b3, v1.b[4] +; CHECK-GI-NEXT: mov v0.b[11], v2.b[0] +; CHECK-GI-NEXT: mov b2, v1.b[5] +; CHECK-GI-NEXT: mov v0.b[12], v3.b[0] +; CHECK-GI-NEXT: mov b3, v1.b[6] +; CHECK-GI-NEXT: mov b1, v1.b[7] +; CHECK-GI-NEXT: mov v0.b[13], v2.b[0] +; CHECK-GI-NEXT: mov v0.b[14], v3.b[0] +; CHECK-GI-NEXT: mov v0.b[15], v1.b[0] +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <8 x i8> %x, i32 0 %vecinit = insertelement <16 x i8> undef, i8 %vecext, i32 0 @@ -1624,21 +2098,49 @@ entry: } define <8 x i16> @test_concat_v8i16_v8i16_v8i16(<8 x i16> %x, <8 x i16> %y) #0 { -; CHECK-LABEL: test_concat_v8i16_v8i16_v8i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v8i16_v8i16_v8i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v8i16_v8i16_v8i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: adrp x8, .LCPI130_0 +; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI130_0] +; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-GI-NEXT: ret entry: %vecinit14 = shufflevector <8 x i16> %x, <8 x i16> %y, <8 x i32> ret <8 x i16> %vecinit14 } define <8 x i16> @test_concat_v8i16_v4i16_v8i16(<4 x i16> %x, <8 x i16> %y) #0 { -; CHECK-LABEL: test_concat_v8i16_v4i16_v8i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v8i16_v4i16_v8i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v8i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: adrp x8, .LCPI131_0 +; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: mov h2, v0.h[1] +; CHECK-GI-NEXT: mov h3, v0.h[2] +; CHECK-GI-NEXT: mov h4, v0.h[3] +; CHECK-GI-NEXT: mov v0.h[1], v2.h[0] +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI131_0] +; CHECK-GI-NEXT: mov v0.h[2], v3.h[0] +; CHECK-GI-NEXT: mov v0.h[3], v4.h[0] +; CHECK-GI-NEXT: mov v0.h[4], v0.h[0] +; CHECK-GI-NEXT: mov v0.h[5], v0.h[0] +; CHECK-GI-NEXT: mov v0.h[6], v0.h[0] +; CHECK-GI-NEXT: mov v0.h[7], v0.h[0] +; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <4 x i16> %x, i32 0 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0 @@ -1653,11 +2155,29 @@ entry: } define <8 x i16> @test_concat_v8i16_v8i16_v4i16(<8 x i16> %x, <4 x i16> %y) #0 { -; CHECK-LABEL: test_concat_v8i16_v8i16_v4i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v8i16_v8i16_v4i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v8i16_v8i16_v4i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov h2, v0.h[1] +; CHECK-GI-NEXT: mov h3, v0.h[2] +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov h4, v0.h[3] +; CHECK-GI-NEXT: mov v0.h[1], v2.h[0] +; CHECK-GI-NEXT: mov h2, v1.h[1] +; CHECK-GI-NEXT: mov v0.h[2], v3.h[0] +; CHECK-GI-NEXT: mov h3, v1.h[2] +; CHECK-GI-NEXT: mov v0.h[3], v4.h[0] +; CHECK-GI-NEXT: mov v0.h[4], v1.h[0] +; CHECK-GI-NEXT: mov h1, v1.h[3] +; CHECK-GI-NEXT: mov v0.h[5], v2.h[0] +; CHECK-GI-NEXT: mov v0.h[6], v3.h[0] +; CHECK-GI-NEXT: mov v0.h[7], v1.h[0] +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <8 x i16> %x, i32 0 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0 @@ -1679,12 +2199,31 @@ entry: } define <8 x i16> @test_concat_v8i16_v4i16_v4i16(<4 x i16> %x, <4 x i16> %y) #0 { -; CHECK-LABEL: test_concat_v8i16_v4i16_v4i16: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v8i16_v4i16_v4i16: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v8i16_v4i16_v4i16: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-GI-NEXT: mov h2, v0.h[1] +; CHECK-GI-NEXT: mov h3, v0.h[2] +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov h4, v0.h[3] +; CHECK-GI-NEXT: mov v0.h[1], v2.h[0] +; CHECK-GI-NEXT: mov h2, v1.h[1] +; CHECK-GI-NEXT: mov v0.h[2], v3.h[0] +; CHECK-GI-NEXT: mov h3, v1.h[2] +; CHECK-GI-NEXT: mov v0.h[3], v4.h[0] +; CHECK-GI-NEXT: mov v0.h[4], v1.h[0] +; CHECK-GI-NEXT: mov h1, v1.h[3] +; CHECK-GI-NEXT: mov v0.h[5], v2.h[0] +; CHECK-GI-NEXT: mov v0.h[6], v3.h[0] +; CHECK-GI-NEXT: mov v0.h[7], v1.h[0] +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <4 x i16> %x, i32 0 %vecinit = insertelement <8 x i16> undef, i16 %vecext, i32 0 @@ -1706,21 +2245,43 @@ entry: } define <4 x i32> @test_concat_v4i32_v4i32_v4i32(<4 x i32> %x, <4 x i32> %y) #0 { -; CHECK-LABEL: test_concat_v4i32_v4i32_v4i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v4i32_v4i32_v4i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v4i32_v4i32_v4i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: adrp x8, .LCPI134_0 +; CHECK-GI-NEXT: // kill: def $q0 killed $q0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI134_0] +; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-GI-NEXT: ret entry: %vecinit6 = shufflevector <4 x i32> %x, <4 x i32> %y, <4 x i32> ret <4 x i32> %vecinit6 } define <4 x i32> @test_concat_v4i32_v2i32_v4i32(<2 x i32> %x, <4 x i32> %y) #0 { -; CHECK-LABEL: test_concat_v4i32_v2i32_v4i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v4i32_v2i32_v4i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v4i32_v2i32_v4i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: // kill: def $d0 killed $d0 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: adrp x8, .LCPI135_0 +; CHECK-GI-NEXT: // kill: def $q1 killed $q1 killed $q0_q1 def $q0_q1 +; CHECK-GI-NEXT: mov s2, v0.s[1] +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: ldr q2, [x8, :lo12:.LCPI135_0] +; CHECK-GI-NEXT: mov v0.s[2], v0.s[0] +; CHECK-GI-NEXT: mov v0.s[3], v0.s[0] +; CHECK-GI-NEXT: tbl v0.16b, { v0.16b, v1.16b }, v2.16b +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <2 x i32> %x, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0 @@ -1731,11 +2292,21 @@ entry: } define <4 x i32> @test_concat_v4i32_v4i32_v2i32(<4 x i32> %x, <2 x i32> %y) #0 { -; CHECK-LABEL: test_concat_v4i32_v4i32_v2i32: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: // kill: def $d1 killed $d1 def $q1 -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: test_concat_v4i32_v4i32_v2i32: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-SD-NEXT: mov v0.d[1], v1.d[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: test_concat_v4i32_v4i32_v2i32: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov s2, v0.s[1] +; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 +; CHECK-GI-NEXT: mov v0.s[1], v2.s[0] +; CHECK-GI-NEXT: mov s2, v1.s[1] +; CHECK-GI-NEXT: mov v0.s[2], v1.s[0] +; CHECK-GI-NEXT: mov v0.s[3], v2.s[0] +; CHECK-GI-NEXT: ret entry: %vecext = extractelement <4 x i32> %x, i32 0 %vecinit = insertelement <4 x i32> undef, i32 %vecext, i32 0 @@ -1877,51 +2448,81 @@ define <16 x i8> @concat_vector_v16i8_const() { } define <4 x i16> @concat_vector_v4i16(<1 x i16> %a) { -; CHECK-LABEL: concat_vector_v4i16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.4h, v0.h[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: concat_vector_v4i16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.4h, v0.h[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: concat_vector_v4i16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.4h, w8 +; CHECK-GI-NEXT: ret %r = shufflevector <1 x i16> %a, <1 x i16> undef, <4 x i32> zeroinitializer ret <4 x i16> %r } define <4 x i32> @concat_vector_v4i32(<1 x i32> %a) { -; CHECK-LABEL: concat_vector_v4i32: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.4s, v0.s[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: concat_vector_v4i32: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.4s, v0.s[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: concat_vector_v4i32: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.4s, w8 +; CHECK-GI-NEXT: ret %r = shufflevector <1 x i32> %a, <1 x i32> undef, <4 x i32> zeroinitializer ret <4 x i32> %r } define <8 x i8> @concat_vector_v8i8(<1 x i8> %a) { -; CHECK-LABEL: concat_vector_v8i8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.8b, v0.b[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: concat_vector_v8i8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.8b, v0.b[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: concat_vector_v8i8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.8b, w8 +; CHECK-GI-NEXT: ret %r = shufflevector <1 x i8> %a, <1 x i8> undef, <8 x i32> zeroinitializer ret <8 x i8> %r } define <8 x i16> @concat_vector_v8i16(<1 x i16> %a) { -; CHECK-LABEL: concat_vector_v8i16: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.8h, v0.h[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: concat_vector_v8i16: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.8h, v0.h[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: concat_vector_v8i16: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.8h, w8 +; CHECK-GI-NEXT: ret %r = shufflevector <1 x i16> %a, <1 x i16> undef, <8 x i32> zeroinitializer ret <8 x i16> %r } define <16 x i8> @concat_vector_v16i8(<1 x i8> %a) { -; CHECK-LABEL: concat_vector_v16i8: -; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 -; CHECK-NEXT: dup v0.16b, v0.b[0] -; CHECK-NEXT: ret +; CHECK-SD-LABEL: concat_vector_v16i8: +; CHECK-SD: // %bb.0: +; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-SD-NEXT: dup v0.16b, v0.b[0] +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: concat_vector_v16i8: +; CHECK-GI: // %bb.0: +; CHECK-GI-NEXT: fmov x8, d0 +; CHECK-GI-NEXT: dup v0.16b, w8 +; CHECK-GI-NEXT: ret %r = shufflevector <1 x i8> %a, <1 x i8> undef, <16 x i32> zeroinitializer ret <16 x i8> %r } diff --git a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll index 04e19dce9ad75a5ff1d8afc1fabeb8bf99d941fc..adfe28ea95893bd189b2b0716a2e4dc10f419695 100644 --- a/llvm/test/CodeGen/AArch64/arm64-vaddv.ll +++ b/llvm/test/CodeGen/AArch64/arm64-vaddv.ll @@ -1,11 +1,13 @@ -; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -mcpu=cyclone | FileCheck %s -; RUN: llc < %s -global-isel -mtriple=arm64-eabi -aarch64-neon-syntax=apple -asm-verbose=false -mcpu=cyclone | FileCheck %s +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s +; RUN: llc < %s -mtriple=arm64-eabi -global-isel | FileCheck %s define signext i8 @test_vaddv_s8(<8 x i8> %a1) { ; CHECK-LABEL: test_vaddv_s8: -; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: smov.b w0, v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b0, v0.8b +; CHECK-NEXT: smov w0, v0.b[0] +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a1) %0 = trunc i32 %vaddv.i to i8 @@ -14,9 +16,12 @@ entry: define <8 x i8> @test_vaddv_s8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { ; CHECK-LABEL: test_vaddv_s8_used_by_laneop: -; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b1, v1.8b +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.b[3], v1.b[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i8(<8 x i8> %a2) %1 = trunc i32 %0 to i8 @@ -26,9 +31,10 @@ entry: define signext i16 @test_vaddv_s16(<4 x i16> %a1) { ; CHECK-LABEL: test_vaddv_s16: -; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: smov.h w0, v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h0, v0.4h +; CHECK-NEXT: smov w0, v0.h[0] +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a1) %0 = trunc i32 %vaddv.i to i16 @@ -37,9 +43,12 @@ entry: define <4 x i16> @test_vaddv_s16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { ; CHECK-LABEL: test_vaddv_s16_used_by_laneop: -; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h1, v1.4h +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.h[3], v1.h[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i16(<4 x i16> %a2) %1 = trunc i32 %0 to i16 @@ -49,10 +58,11 @@ entry: define i32 @test_vaddv_s32(<2 x i32> %a1) { ; CHECK-LABEL: test_vaddv_s32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret ; 2 x i32 is not supported by the ISA, thus, this is a special case -; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a1) ret i32 %vaddv.i @@ -60,9 +70,12 @@ entry: define <2 x i32> @test_vaddv_s32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { ; CHECK-LABEL: test_vaddv_s32_used_by_laneop: -; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1 -; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp v1.2s, v1.2s, v1.2s +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.s[1], v1.s[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v2i32(<2 x i32> %a2) %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 @@ -71,9 +84,10 @@ entry: define i64 @test_vaddv_s64(<2 x i64> %a1) { ; CHECK-LABEL: test_vaddv_s64: -; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0 -; CHECK-NEXT: fmov x0, [[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp d0, v0.2d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a1) ret i64 %vaddv.i @@ -81,9 +95,10 @@ entry: define <2 x i64> @test_vaddv_s64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) { ; CHECK-LABEL: test_vaddv_s64_used_by_laneop: -; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp d1, v1.2d +; CHECK-NEXT: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.aarch64.neon.saddv.i64.v2i64(<2 x i64> %a2) %1 = insertelement <2 x i64> %a1, i64 %0, i64 1 @@ -92,9 +107,10 @@ entry: define zeroext i8 @test_vaddv_u8(<8 x i8> %a1) { ; CHECK-LABEL: test_vaddv_u8: -; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b0, v0.8b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1) %0 = trunc i32 %vaddv.i to i8 @@ -103,9 +119,12 @@ entry: define <8 x i8> @test_vaddv_u8_used_by_laneop(<8 x i8> %a1, <8 x i8> %a2) { ; CHECK-LABEL: test_vaddv_u8_used_by_laneop: -; CHECK: addv.8b b[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b1, v1.8b +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.b[3], v1.b[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a2) %1 = trunc i32 %0 to i8 @@ -115,9 +134,10 @@ entry: define i32 @test_vaddv_u8_masked(<8 x i8> %a1) { ; CHECK-LABEL: test_vaddv_u8_masked: -; CHECK: addv.8b b[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b0, v0.8b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i8(<8 x i8> %a1) %0 = and i32 %vaddv.i, 511 ; 0x1ff @@ -126,9 +146,10 @@ entry: define zeroext i16 @test_vaddv_u16(<4 x i16> %a1) { ; CHECK-LABEL: test_vaddv_u16: -; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h0, v0.4h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1) %0 = trunc i32 %vaddv.i to i16 @@ -137,9 +158,12 @@ entry: define <4 x i16> @test_vaddv_u16_used_by_laneop(<4 x i16> %a1, <4 x i16> %a2) { ; CHECK-LABEL: test_vaddv_u16_used_by_laneop: -; CHECK: addv.4h h[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h1, v1.4h +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.h[3], v1.h[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a2) %1 = trunc i32 %0 to i16 @@ -149,9 +173,10 @@ entry: define i32 @test_vaddv_u16_masked(<4 x i16> %a1) { ; CHECK-LABEL: test_vaddv_u16_masked: -; CHECK: addv.4h h[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h0, v0.4h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i16(<4 x i16> %a1) %0 = and i32 %vaddv.i, 3276799 ; 0x31ffff @@ -160,10 +185,11 @@ entry: define i32 @test_vaddv_u32(<2 x i32> %a1) { ; CHECK-LABEL: test_vaddv_u32: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp v0.2s, v0.2s, v0.2s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret ; 2 x i32 is not supported by the ISA, thus, this is a special case -; CHECK: addp.2s v[[REGNUM:[0-9]+]], v0, v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a1) ret i32 %vaddv.i @@ -171,9 +197,12 @@ entry: define <2 x i32> @test_vaddv_u32_used_by_laneop(<2 x i32> %a1, <2 x i32> %a2) { ; CHECK-LABEL: test_vaddv_u32_used_by_laneop: -; CHECK: addp.2s v[[REGNUM:[0-9]+]], v1, v1 -; CHECK-NEXT: mov.s v0[1], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp v1.2s, v1.2s, v1.2s +; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0 +; CHECK-NEXT: mov v0.s[1], v1.s[0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v2i32(<2 x i32> %a2) %1 = insertelement <2 x i32> %a1, i32 %0, i32 1 @@ -182,8 +211,9 @@ entry: define float @test_vaddv_f32(<2 x float> %a1) { ; CHECK-LABEL: test_vaddv_f32: -; CHECK: faddp.2s s0, v0 -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: faddp s0, v0.2s +; CHECK-NEXT: ret entry: %vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v2f32(<2 x float> %a1) ret float %vaddv.i @@ -191,9 +221,10 @@ entry: define float @test_vaddv_v4f32(<4 x float> %a1) { ; CHECK-LABEL: test_vaddv_v4f32: -; CHECK: faddp.4s [[REGNUM:v[0-9]+]], v0, v0 -; CHECK: faddp.2s s0, [[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: faddp v0.4s, v0.4s, v0.4s +; CHECK-NEXT: faddp s0, v0.2s +; CHECK-NEXT: ret entry: %vaddv.i = tail call float @llvm.aarch64.neon.faddv.f32.v4f32(<4 x float> %a1) ret float %vaddv.i @@ -201,8 +232,9 @@ entry: define double @test_vaddv_f64(<2 x double> %a1) { ; CHECK-LABEL: test_vaddv_f64: -; CHECK: faddp.2d d0, v0 -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: faddp d0, v0.2d +; CHECK-NEXT: ret entry: %vaddv.i = tail call double @llvm.aarch64.neon.faddv.f64.v2f64(<2 x double> %a1) ret double %vaddv.i @@ -210,9 +242,10 @@ entry: define i64 @test_vaddv_u64(<2 x i64> %a1) { ; CHECK-LABEL: test_vaddv_u64: -; CHECK: addp.2d [[REGNUM:d[0-9]+]], v0 -; CHECK-NEXT: fmov x0, [[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp d0, v0.2d +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1) ret i64 %vaddv.i @@ -220,9 +253,10 @@ entry: define <2 x i64> @test_vaddv_u64_used_by_laneop(<2 x i64> %a1, <2 x i64> %a2) { ; CHECK-LABEL: test_vaddv_u64_used_by_laneop: -; CHECK: addp.2d d[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.d v0[1], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp d1, v1.2d +; CHECK-NEXT: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret entry: %0 = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a2) %1 = insertelement <2 x i64> %a1, i64 %0, i64 1 @@ -231,10 +265,10 @@ entry: define <1 x i64> @test_vaddv_u64_to_vec(<2 x i64> %a1) { ; CHECK-LABEL: test_vaddv_u64_to_vec: -; CHECK: addp.2d d0, v0 -; CHECK-NOT: fmov -; CHECK-NOT: ins -; CHECK: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addp d0, v0.2d +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $q0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i64 @llvm.aarch64.neon.uaddv.i64.v2i64(<2 x i64> %a1) %vec = insertelement <1 x i64> undef, i64 %vaddv.i, i32 0 @@ -243,9 +277,10 @@ entry: define signext i8 @test_vaddvq_s8(<16 x i8> %a1) { ; CHECK-LABEL: test_vaddvq_s8: -; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: smov.b w0, v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b0, v0.16b +; CHECK-NEXT: smov w0, v0.b[0] +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a1) %0 = trunc i32 %vaddv.i to i8 @@ -254,9 +289,10 @@ entry: define <16 x i8> @test_vaddvq_s8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { ; CHECK-LABEL: test_vaddvq_s8_used_by_laneop: -; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b1, v1.16b +; CHECK-NEXT: mov v0.b[3], v1.b[0] +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v16i8(<16 x i8> %a2) %1 = trunc i32 %0 to i8 @@ -266,9 +302,10 @@ entry: define signext i16 @test_vaddvq_s16(<8 x i16> %a1) { ; CHECK-LABEL: test_vaddvq_s16: -; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: smov.h w0, v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h0, v0.8h +; CHECK-NEXT: smov w0, v0.h[0] +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a1) %0 = trunc i32 %vaddv.i to i16 @@ -277,9 +314,10 @@ entry: define <8 x i16> @test_vaddvq_s16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { ; CHECK-LABEL: test_vaddvq_s16_used_by_laneop: -; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h1, v1.8h +; CHECK-NEXT: mov v0.h[3], v1.h[0] +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v8i16(<8 x i16> %a2) %1 = trunc i32 %0 to i16 @@ -289,9 +327,10 @@ entry: define i32 @test_vaddvq_s32(<4 x i32> %a1) { ; CHECK-LABEL: test_vaddvq_s32: -; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0 -; CHECK-NEXT: fmov w0, [[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv s0, v0.4s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a1) ret i32 %vaddv.i @@ -299,9 +338,10 @@ entry: define <4 x i32> @test_vaddvq_s32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { ; CHECK-LABEL: test_vaddvq_s32_used_by_laneop: -; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv s1, v1.4s +; CHECK-NEXT: mov v0.s[3], v1.s[0] +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.saddv.i32.v4i32(<4 x i32> %a2) %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 @@ -310,9 +350,10 @@ entry: define zeroext i8 @test_vaddvq_u8(<16 x i8> %a1) { ; CHECK-LABEL: test_vaddvq_u8: -; CHECK: addv.16b b[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b0, v0.16b +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a1) %0 = trunc i32 %vaddv.i to i8 @@ -321,9 +362,10 @@ entry: define <16 x i8> @test_vaddvq_u8_used_by_laneop(<16 x i8> %a1, <16 x i8> %a2) { ; CHECK-LABEL: test_vaddvq_u8_used_by_laneop: -; CHECK: addv.16b b[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.b v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv b1, v1.16b +; CHECK-NEXT: mov v0.b[3], v1.b[0] +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v16i8(<16 x i8> %a2) %1 = trunc i32 %0 to i8 @@ -333,9 +375,10 @@ entry: define zeroext i16 @test_vaddvq_u16(<8 x i16> %a1) { ; CHECK-LABEL: test_vaddvq_u16: -; CHECK: addv.8h h[[REGNUM:[0-9]+]], v0 -; CHECK-NEXT: fmov w0, s[[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h0, v0.8h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a1) %0 = trunc i32 %vaddv.i to i16 @@ -344,9 +387,10 @@ entry: define <8 x i16> @test_vaddvq_u16_used_by_laneop(<8 x i16> %a1, <8 x i16> %a2) { ; CHECK-LABEL: test_vaddvq_u16_used_by_laneop: -; CHECK: addv.8h h[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.h v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv h1, v1.8h +; CHECK-NEXT: mov v0.h[3], v1.h[0] +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v8i16(<8 x i16> %a2) %1 = trunc i32 %0 to i16 @@ -356,9 +400,10 @@ entry: define i32 @test_vaddvq_u32(<4 x i32> %a1) { ; CHECK-LABEL: test_vaddvq_u32: -; CHECK: addv.4s [[REGNUM:s[0-9]+]], v0 -; CHECK-NEXT: fmov [[FMOVRES:w[0-9]+]], [[REGNUM]] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv s0, v0.4s +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret entry: %vaddv.i = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a1) ret i32 %vaddv.i @@ -366,9 +411,10 @@ entry: define <4 x i32> @test_vaddvq_u32_used_by_laneop(<4 x i32> %a1, <4 x i32> %a2) { ; CHECK-LABEL: test_vaddvq_u32_used_by_laneop: -; CHECK: addv.4s s[[REGNUM:[0-9]+]], v1 -; CHECK-NEXT: mov.s v0[3], v[[REGNUM]][0] -; CHECK-NEXT: ret +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: addv s1, v1.4s +; CHECK-NEXT: mov v0.s[3], v1.s[0] +; CHECK-NEXT: ret entry: %0 = tail call i32 @llvm.aarch64.neon.uaddv.i32.v4i32(<4 x i32> %a2) %1 = insertelement <4 x i32> %a1, i32 %0, i32 3 diff --git a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll index 24cce9a2b26b589884cd2f177bf53887a83f496a..c4de177176e330baf6925db42c298230c0abf804 100644 --- a/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll +++ b/llvm/test/CodeGen/AArch64/avoid-pre-trunc.ll @@ -1,75 +1,36 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc -mtriple=aarch64 < %s | FileCheck %s -define i32 @lower_lshr(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d, <4 x i32> %e, <4 x i32> %f, <4 x i32> %g, <4 x i32> %h) { -; CHECK-LABEL: lower_lshr: -; CHECK: // %bb.0: -; CHECK-NEXT: addv s0, v0.4s -; CHECK-NEXT: addv s1, v1.4s -; CHECK-NEXT: addv s4, v4.4s -; CHECK-NEXT: addv s5, v5.4s -; CHECK-NEXT: addv s2, v2.4s -; CHECK-NEXT: addv s6, v6.4s -; CHECK-NEXT: mov v0.s[1], v1.s[0] -; CHECK-NEXT: addv s1, v3.4s -; CHECK-NEXT: addv s3, v7.4s -; CHECK-NEXT: mov v4.s[1], v5.s[0] -; CHECK-NEXT: mov v0.s[2], v2.s[0] -; CHECK-NEXT: mov v4.s[2], v6.s[0] -; CHECK-NEXT: mov v0.s[3], v1.s[0] -; CHECK-NEXT: mov v4.s[3], v3.s[0] -; CHECK-NEXT: xtn v1.4h, v0.4s -; CHECK-NEXT: shrn v0.4h, v0.4s, #16 -; CHECK-NEXT: xtn v2.4h, v4.4s -; CHECK-NEXT: shrn v3.4h, v4.4s, #16 -; CHECK-NEXT: uhadd v0.4h, v1.4h, v0.4h -; CHECK-NEXT: uhadd v1.4h, v2.4h, v3.4h -; CHECK-NEXT: mov v0.d[1], v1.d[0] -; CHECK-NEXT: uaddlv s0, v0.8h -; CHECK-NEXT: fmov w0, s0 -; CHECK-NEXT: ret - %l87 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %a) - %l174 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %b) - %l257 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %c) - %l340 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %d) - %l427 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %e) - %l514 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %f) - %l597 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %g) - %l680 = tail call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %h) - %l681 = insertelement <8 x i32> poison, i32 %l87, i32 0 - %l682 = insertelement <8 x i32> %l681, i32 %l174, i32 1 - %l683 = insertelement <8 x i32> %l682, i32 %l257, i32 2 - %l684 = insertelement <8 x i32> %l683, i32 %l340, i32 3 - %l685 = insertelement <8 x i32> %l684, i32 %l427, i32 4 - %l686 = insertelement <8 x i32> %l685, i32 %l514, i32 5 - %l687 = insertelement <8 x i32> %l686, i32 %l597, i32 6 - %l688 = insertelement <8 x i32> %l687, i32 %l680, i32 7 - %l689 = and <8 x i32> %l688, - %l690 = lshr <8 x i32> %l688, - %l691 = add nuw nsw <8 x i32> %l689, %l690 - %l692 = lshr <8 x i32> %l691, - %l693 = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %l692) - ret i32 %l693 -} -declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) -declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) - define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) { ; CHECK-LABEL: lower_trunc_16xi8: ; CHECK: // %bb.0: ; CHECK-NEXT: fmov s0, w0 -; CHECK-NEXT: add x8, sp, #56 -; CHECK-NEXT: ld1r { v1.8h }, [x8] +; CHECK-NEXT: ldr h1, [sp] +; CHECK-NEXT: add x8, sp, #8 +; CHECK-NEXT: ld1 { v1.h }[1], [x8] +; CHECK-NEXT: add x8, sp, #16 ; CHECK-NEXT: mov v0.h[1], w1 -; CHECK-NEXT: add v3.8h, v1.8h, v1.8h +; CHECK-NEXT: ld1 { v1.h }[2], [x8] +; CHECK-NEXT: add x8, sp, #24 ; CHECK-NEXT: mov v0.h[2], w2 +; CHECK-NEXT: ld1 { v1.h }[3], [x8] +; CHECK-NEXT: add x8, sp, #32 ; CHECK-NEXT: mov v0.h[3], w3 +; CHECK-NEXT: ld1 { v1.h }[4], [x8] +; CHECK-NEXT: add x8, sp, #40 +; CHECK-NEXT: ld1 { v1.h }[5], [x8] +; CHECK-NEXT: add x8, sp, #48 ; CHECK-NEXT: mov v0.h[4], w4 +; CHECK-NEXT: ld1 { v1.h }[6], [x8] +; CHECK-NEXT: add x8, sp, #56 ; CHECK-NEXT: mov v0.h[5], w5 +; CHECK-NEXT: ld1 { v1.h }[7], [x8] ; CHECK-NEXT: mov v0.h[6], w6 -; CHECK-NEXT: add v2.8h, v0.8h, v0.8h +; CHECK-NEXT: add v2.8h, v1.8h, v1.8h +; CHECK-NEXT: mov v0.h[7], w7 +; CHECK-NEXT: add v3.8h, v0.8h, v0.8h ; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b -; CHECK-NEXT: uzp1 v1.16b, v2.16b, v3.16b +; CHECK-NEXT: uzp1 v1.16b, v3.16b, v2.16b ; CHECK-NEXT: eor v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret %a1 = insertelement <16 x i16> poison, i16 %a, i16 0 @@ -80,14 +41,14 @@ define <16 x i8> @lower_trunc_16xi8(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f1 = insertelement <16 x i16> %e1, i16 %f, i16 5 %g1 = insertelement <16 x i16> %f1, i16 %g, i16 6 %h1 = insertelement <16 x i16> %g1, i16 %h, i16 7 - %i1 = insertelement <16 x i16> %f1, i16 %i, i16 8 - %j1 = insertelement <16 x i16> %g1, i16 %j, i16 9 - %k1 = insertelement <16 x i16> %f1, i16 %k, i16 10 - %l1 = insertelement <16 x i16> %g1, i16 %l, i16 11 - %m1 = insertelement <16 x i16> %f1, i16 %m, i16 12 - %n1 = insertelement <16 x i16> %g1, i16 %n, i16 13 - %o1 = insertelement <16 x i16> %f1, i16 %o, i16 14 - %p1 = insertelement <16 x i16> %g1, i16 %p, i16 15 + %i1 = insertelement <16 x i16> %h1, i16 %i, i16 8 + %j1 = insertelement <16 x i16> %i1, i16 %j, i16 9 + %k1 = insertelement <16 x i16> %j1, i16 %k, i16 10 + %l1 = insertelement <16 x i16> %k1, i16 %l, i16 11 + %m1 = insertelement <16 x i16> %l1, i16 %m, i16 12 + %n1 = insertelement <16 x i16> %m1, i16 %n, i16 13 + %o1 = insertelement <16 x i16> %n1, i16 %o, i16 14 + %p1 = insertelement <16 x i16> %o1, i16 %p, i16 15 %t = trunc <16 x i16> %p1 to <16 x i8> %s = add <16 x i16> %p1, %p1 %t2 = trunc <16 x i16> %s to <16 x i8> diff --git a/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll b/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll new file mode 100644 index 0000000000000000000000000000000000000000..34899cb47dba3b3ba53ecd9122744e07dc562596 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/concat-vector-add-combine.ll @@ -0,0 +1,152 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=aarch64 < %s | FileCheck %s + +define i16 @combine_add_16xi16(i16 %a, i16 %b, i16 %c, i16 %d, i16 %e, i16 %f, i16 %g, i16 %h, i16 %i, i16 %j, i16 %k, i16 %l, i16 %m, i16 %n, i16 %o, i16 %p) { +; CHECK-LABEL: combine_add_16xi16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s0, w0 +; CHECK-NEXT: ldr h1, [sp] +; CHECK-NEXT: add x8, sp, #8 +; CHECK-NEXT: ld1 { v1.h }[1], [x8] +; CHECK-NEXT: add x8, sp, #16 +; CHECK-NEXT: mov v0.h[1], w1 +; CHECK-NEXT: ld1 { v1.h }[2], [x8] +; CHECK-NEXT: add x8, sp, #24 +; CHECK-NEXT: mov v0.h[2], w2 +; CHECK-NEXT: ld1 { v1.h }[3], [x8] +; CHECK-NEXT: add x8, sp, #32 +; CHECK-NEXT: mov v0.h[3], w3 +; CHECK-NEXT: ld1 { v1.h }[4], [x8] +; CHECK-NEXT: add x8, sp, #40 +; CHECK-NEXT: ld1 { v1.h }[5], [x8] +; CHECK-NEXT: add x8, sp, #48 +; CHECK-NEXT: mov v0.h[4], w4 +; CHECK-NEXT: ld1 { v1.h }[6], [x8] +; CHECK-NEXT: add x8, sp, #56 +; CHECK-NEXT: mov v0.h[5], w5 +; CHECK-NEXT: ld1 { v1.h }[7], [x8] +; CHECK-NEXT: mov v0.h[6], w6 +; CHECK-NEXT: mov v0.h[7], w7 +; CHECK-NEXT: uzp2 v2.16b, v0.16b, v1.16b +; CHECK-NEXT: uzp1 v0.16b, v0.16b, v1.16b +; CHECK-NEXT: uhadd v0.16b, v0.16b, v2.16b +; CHECK-NEXT: uaddlv h0, v0.16b +; CHECK-NEXT: umov w0, v0.h[0] +; CHECK-NEXT: ret + %a1 = insertelement <16 x i16> poison, i16 %a, i16 0 + %b1 = insertelement <16 x i16> %a1, i16 %b, i16 1 + %c1 = insertelement <16 x i16> %b1, i16 %c, i16 2 + %d1 = insertelement <16 x i16> %c1, i16 %d, i16 3 + %e1 = insertelement <16 x i16> %d1, i16 %e, i16 4 + %f1 = insertelement <16 x i16> %e1, i16 %f, i16 5 + %g1 = insertelement <16 x i16> %f1, i16 %g, i16 6 + %h1 = insertelement <16 x i16> %g1, i16 %h, i16 7 + %i1 = insertelement <16 x i16> %h1, i16 %i, i16 8 + %j1 = insertelement <16 x i16> %i1, i16 %j, i16 9 + %k1 = insertelement <16 x i16> %j1, i16 %k, i16 10 + %l1 = insertelement <16 x i16> %k1, i16 %l, i16 11 + %m1 = insertelement <16 x i16> %l1, i16 %m, i16 12 + %n1 = insertelement <16 x i16> %m1, i16 %n, i16 13 + %o1 = insertelement <16 x i16> %n1, i16 %o, i16 14 + %p1 = insertelement <16 x i16> %o1, i16 %p, i16 15 + %x = and <16 x i16> %p1, + %sh1 = lshr <16 x i16> %p1, + %s = add nuw nsw <16 x i16> %x, %sh1 + %sh2 = lshr <16 x i16> %s, + %res = call i16 @llvm.vector.reduce.add.v16i16(<16 x i16> %sh2) + ret i16 %res +} + +define i32 @combine_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d, i32 %e, i32 %f, i32 %g, i32 %h) local_unnamed_addr #0 { +; CHECK-LABEL: combine_add_8xi32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s0, w4 +; CHECK-NEXT: fmov s1, w0 +; CHECK-NEXT: mov v0.s[1], w5 +; CHECK-NEXT: mov v1.s[1], w1 +; CHECK-NEXT: mov v0.s[2], w6 +; CHECK-NEXT: mov v1.s[2], w2 +; CHECK-NEXT: mov v0.s[3], w7 +; CHECK-NEXT: mov v1.s[3], w3 +; CHECK-NEXT: uzp2 v2.8h, v1.8h, v0.8h +; CHECK-NEXT: uzp1 v0.8h, v1.8h, v0.8h +; CHECK-NEXT: uhadd v0.8h, v0.8h, v2.8h +; CHECK-NEXT: uaddlv s0, v0.8h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %a1 = insertelement <8 x i32> poison, i32 %a, i32 0 + %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1 + %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2 + %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3 + %e1 = insertelement <8 x i32> %d1, i32 %e, i32 4 + %f1 = insertelement <8 x i32> %e1, i32 %f, i32 5 + %g1 = insertelement <8 x i32> %f1, i32 %g, i32 6 + %h1 = insertelement <8 x i32> %g1, i32 %h, i32 7 + %x = and <8 x i32> %h1, + %sh1 = lshr <8 x i32> %h1, + %s = add nuw nsw <8 x i32> %x, %sh1 + %sh2 = lshr <8 x i32> %s, + %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2) + ret i32 %res +} + +define i32 @combine_undef_add_8xi32(i32 %a, i32 %b, i32 %c, i32 %d) local_unnamed_addr #0 { +; CHECK-LABEL: combine_undef_add_8xi32: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov s1, w0 +; CHECK-NEXT: movi v0.2d, #0000000000000000 +; CHECK-NEXT: mov v1.s[1], w1 +; CHECK-NEXT: uhadd v0.4h, v0.4h, v0.4h +; CHECK-NEXT: mov v1.s[2], w2 +; CHECK-NEXT: mov v1.s[3], w3 +; CHECK-NEXT: xtn v2.4h, v1.4s +; CHECK-NEXT: shrn v1.4h, v1.4s, #16 +; CHECK-NEXT: uhadd v1.4h, v2.4h, v1.4h +; CHECK-NEXT: mov v1.d[1], v0.d[0] +; CHECK-NEXT: uaddlv s0, v1.8h +; CHECK-NEXT: fmov w0, s0 +; CHECK-NEXT: ret + %a1 = insertelement <8 x i32> poison, i32 %a, i32 0 + %b1 = insertelement <8 x i32> %a1, i32 %b, i32 1 + %c1 = insertelement <8 x i32> %b1, i32 %c, i32 2 + %d1 = insertelement <8 x i32> %c1, i32 %d, i32 3 + %e1 = insertelement <8 x i32> %d1, i32 undef, i32 4 + %f1 = insertelement <8 x i32> %e1, i32 undef, i32 5 + %g1 = insertelement <8 x i32> %f1, i32 undef, i32 6 + %h1 = insertelement <8 x i32> %g1, i32 undef, i32 7 + %x = and <8 x i32> %h1, + %sh1 = lshr <8 x i32> %h1, + %s = add nuw nsw <8 x i32> %x, %sh1 + %sh2 = lshr <8 x i32> %s, + %res = call i32 @llvm.vector.reduce.add.v8i32(<8 x i32> %sh2) + ret i32 %res +} + +define i64 @combine_add_4xi64(i64 %a, i64 %b, i64 %c, i64 %d) local_unnamed_addr #0 { +; CHECK-LABEL: combine_add_4xi64: +; CHECK: // %bb.0: +; CHECK-NEXT: fmov d0, x2 +; CHECK-NEXT: fmov d1, x0 +; CHECK-NEXT: mov v0.d[1], x3 +; CHECK-NEXT: mov v1.d[1], x1 +; CHECK-NEXT: uzp2 v2.4s, v1.4s, v0.4s +; CHECK-NEXT: uzp1 v0.4s, v1.4s, v0.4s +; CHECK-NEXT: uhadd v0.4s, v0.4s, v2.4s +; CHECK-NEXT: uaddlv d0, v0.4s +; CHECK-NEXT: fmov x0, d0 +; CHECK-NEXT: ret + %a1 = insertelement <4 x i64> poison, i64 %a, i64 0 + %b1 = insertelement <4 x i64> %a1, i64 %b, i64 1 + %c1 = insertelement <4 x i64> %b1, i64 %c, i64 2 + %d1 = insertelement <4 x i64> %c1, i64 %d, i64 3 + %x = and <4 x i64> %d1, + %sh1 = lshr <4 x i64> %d1, + %s = add nuw nsw <4 x i64> %x, %sh1 + %sh2 = lshr <4 x i64> %s, + %res = call i64 @llvm.vector.reduce.add.v4i64(<4 x i64> %sh2) + ret i64 %res +} + +declare i16 @llvm.vector.reduce.add.v16i16(<16 x i16>) +declare i32 @llvm.vector.reduce.add.v8i32(<8 x i32>) +declare i64 @llvm.vector.reduce.add.v4i64(<4 x i64>) diff --git a/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll b/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll index 57153d04b8bca91954b147535c49cd55affc4fb1..4649fad5b2c2a49c5747feb69712955418f9c480 100644 --- a/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll +++ b/llvm/test/CodeGen/AArch64/dbg-value-swift-async.ll @@ -2,8 +2,7 @@ ; RUN: llc --mtriple="aarch64-" -O0 -fast-isel=false -global-isel=false -stop-after=finalize-isel %s -o - | FileCheck %s --check-prefix=AARCH ; RUN: llc --mtriple="aarch64-" -O0 -fast-isel -stop-after=finalize-isel %s -o - | FileCheck %s --check-prefix=AARCH -;; run: llc --mtriple="aarch64-" -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - --try-experimental-debuginfo-iterators | FileCheck %s --check-prefix=AARCH -;; ^^ Disabled while the global-isel patch for RemoveDIs lands +; RUN: llc --mtriple="aarch64-" -O0 -global-isel -stop-after=irtranslator -verify-machineinstrs %s -o - --try-experimental-debuginfo-iterators | FileCheck %s --check-prefix=AARCH ; RUN: llc --mtriple="aarch64-" -O0 -fast-isel=false -global-isel=false -stop-after=finalize-isel %s -o - --try-experimental-debuginfo-iterators | FileCheck %s --check-prefix=AARCH ; RUN: llc --mtriple="aarch64-" -O0 -fast-isel -stop-after=finalize-isel %s -o - --try-experimental-debuginfo-iterators | FileCheck %s --check-prefix=AARCH diff --git a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir index 0542b46f2e3931063aa5fc9f4159256056a6faed..9612f3269f162b334b9adaf4b74a8d2d58ded3bb 100644 --- a/llvm/test/CodeGen/AArch64/elim-dead-mi.mir +++ b/llvm/test/CodeGen/AArch64/elim-dead-mi.mir @@ -1,5 +1,6 @@ # RUN: llc -mtriple=aarch64 -o - %s \ # RUN: -run-pass dead-mi-elimination | FileCheck %s +# RUN: llc -mtriple=aarch64 -o - %s -p dead-mi-elimination | FileCheck %s --- | @c = internal unnamed_addr global [3 x i8] zeroinitializer, align 4 @d = common dso_local local_unnamed_addr global i32 0, align 4 diff --git a/llvm/test/CodeGen/AArch64/setcc_knownbits.ll b/llvm/test/CodeGen/AArch64/setcc_knownbits.ll index af5c1586a4c6712e234b930bba5beb00d647663c..9e9c814be0266ef73e3565e515ff4f35d9029760 100644 --- a/llvm/test/CodeGen/AArch64/setcc_knownbits.ll +++ b/llvm/test/CodeGen/AArch64/setcc_knownbits.ll @@ -49,9 +49,8 @@ define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) { ; CHECK-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; CHECK: // %bb.0: ; CHECK-NEXT: clz x8, x0 -; CHECK-NEXT: lsr x8, x8, #6 -; CHECK-NEXT: cmp x8, #1 -; CHECK-NEXT: cset w0, eq +; CHECK-NEXT: lsr x0, x8, #6 +; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0 ; CHECK-NEXT: ret %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1) %lshr = lshr i64 %ctlz, 6 diff --git a/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll b/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll index 8b6c0c86bb4e23544e71c2f327cbb2493a478c29..ba8c76348b9b54c1165a8d3f613269d5bead6eac 100644 --- a/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll +++ b/llvm/test/CodeGen/AArch64/stack-tagging-dbg.ll @@ -1,4 +1,5 @@ ; RUN: opt < %s -aarch64-stack-tagging -S -o - | FileCheck %s +; RUN: opt < %s -aarch64-stack-tagging -S -o - --try-experimental-debuginfo-iterators | FileCheck %s target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android" diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll index 51e1fee0db249e960a8723986461baf3bcf85776..1d5cc1e1ec0463641519029f9ac8d9429e5d6518 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.trig.preop.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s -; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,CI %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,VI %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX10 %s +; RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GFX10PLUS,GFX11 %s define double @v_trig_preop_f64(double %a, i32 %b) { ; GCN-LABEL: v_trig_preop_f64: @@ -45,7 +45,13 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { ; CI-NEXT: s_waitcnt lgkmcnt(0) ; CI-NEXT: v_mov_b32_e32 v0, s2 ; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 -; CI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; CI-NEXT: s_add_u32 s0, s0, 4 +; CI-NEXT: s_addc_u32 s1, s1, 0 +; CI-NEXT: v_mov_b32_e32 v3, s1 +; CI-NEXT: v_mov_b32_e32 v2, s0 +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: flat_store_dword v[2:3], v1 ; CI-NEXT: s_waitcnt vmcnt(0) ; CI-NEXT: s_endpgm ; @@ -56,7 +62,13 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: v_mov_b32_e32 v0, s2 ; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], v0 -; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; VI-NEXT: s_add_u32 s0, s0, 4 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dword v[0:1], v0 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dword v[2:3], v1 ; VI-NEXT: s_waitcnt vmcnt(0) ; VI-NEXT: s_endpgm ; @@ -98,14 +110,44 @@ define amdgpu_kernel void @s_trig_preop_f64(double %a, i32 %b) { } define amdgpu_kernel void @s_trig_preop_f64_imm(double %a, i32 %b) { -; GCN-LABEL: s_trig_preop_f64_imm: -; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 -; GCN-NEXT: flat_store_dwordx2 v[0:1], v[0:1] -; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: s_endpgm +; CI-LABEL: s_trig_preop_f64_imm: +; CI: ; %bb.0: +; CI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; CI-NEXT: s_waitcnt lgkmcnt(0) +; CI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 +; CI-NEXT: s_add_u32 s0, s0, 4 +; CI-NEXT: s_addc_u32 s1, s1, 0 +; CI-NEXT: v_mov_b32_e32 v3, s1 +; CI-NEXT: v_mov_b32_e32 v2, s0 +; CI-NEXT: flat_store_dword v[0:1], v0 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: flat_store_dword v[2:3], v1 +; CI-NEXT: s_waitcnt vmcnt(0) +; CI-NEXT: s_endpgm +; +; VI-LABEL: s_trig_preop_f64_imm: +; VI: ; %bb.0: +; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; VI-NEXT: s_waitcnt lgkmcnt(0) +; VI-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 +; VI-NEXT: s_add_u32 s0, s0, 4 +; VI-NEXT: s_addc_u32 s1, s1, 0 +; VI-NEXT: v_mov_b32_e32 v3, s1 +; VI-NEXT: v_mov_b32_e32 v2, s0 +; VI-NEXT: flat_store_dword v[0:1], v0 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: flat_store_dword v[2:3], v1 +; VI-NEXT: s_waitcnt vmcnt(0) +; VI-NEXT: s_endpgm +; +; GFX9-LABEL: s_trig_preop_f64_imm: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0 +; GFX9-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NEXT: v_trig_preop_f64 v[0:1], s[0:1], 7 +; GFX9-NEXT: flat_store_dwordx2 v[0:1], v[0:1] +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_endpgm ; ; GFX10-LABEL: s_trig_preop_f64_imm: ; GFX10: ; %bb.0: diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll index 3eb6f1eced0957f9b9c47fe81695cb82155f3127..0a6b7af2f78d4c44a81e3adb279fb03837ece1cd 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll @@ -3055,19 +3055,29 @@ define i64 @v_sdiv_i64_24bit(i64 %num, i64 %den) { ; CGP-LABEL: v_sdiv_i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2 -; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0 -; CGP-NEXT: v_rcp_f32_e32 v2, v1 -; CGP-NEXT: v_mul_f32_e32 v2, v0, v2 -; CGP-NEXT: v_trunc_f32_e32 v2, v2 -; CGP-NEXT: v_mad_f32 v0, -v2, v1, v0 -; CGP-NEXT: v_cvt_i32_f32_e32 v2, v2 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1| -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0 -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 +; CGP-NEXT: v_and_b32_e32 v5, 0xffffff, v0 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v4, v1 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v3 +; CGP-NEXT: v_mul_lo_u32 v1, v1, v4 +; CGP-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v1, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v2 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v0, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_mul_lo_u32 v1, v0, v3 +; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v5, v1 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; CGP-NEXT: v_sub_i32_e64 v2, s[4:5], v1, v3 +; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CGP-NEXT: v_add_i32_e32 v2, vcc, 1, v0 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i64 %num, 16777215 @@ -3335,32 +3345,52 @@ define <2 x i64> @v_sdiv_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; CGP-LABEL: v_sdiv_v2i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4 -; CGP-NEXT: v_cvt_f32_i32_e32 v1, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v0, v0 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 ; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6 -; CGP-NEXT: v_rcp_f32_e32 v3, v1 -; CGP-NEXT: v_cvt_f32_i32_e32 v4, v4 +; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v3 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_and_b32_e32 v7, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; CGP-NEXT: v_cvt_f32_i32_e32 v2, v2 -; CGP-NEXT: v_mul_f32_e32 v3, v0, v3 -; CGP-NEXT: v_trunc_f32_e32 v3, v3 -; CGP-NEXT: v_mad_f32 v0, -v3, v1, v0 -; CGP-NEXT: v_cvt_i32_f32_e32 v3, v3 -; CGP-NEXT: v_rcp_f32_e32 v5, v4 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, |v1| -; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v0, vcc, v3, v0 -; CGP-NEXT: v_mul_f32_e32 v3, v2, v5 -; CGP-NEXT: v_trunc_f32_e32 v3, v3 -; CGP-NEXT: v_mad_f32 v2, -v3, v4, v2 -; CGP-NEXT: v_cvt_i32_f32_e32 v3, v3 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, |v4| -; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v3, v2 -; CGP-NEXT: v_bfe_i32 v2, v2, 0, 25 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v5, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v4 +; CGP-NEXT: v_mul_lo_u32 v6, v6, v5 +; CGP-NEXT: v_rcp_f32_e32 v8, v1 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, 0 +; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v8 +; CGP-NEXT: v_cvt_u32_f32_e32 v6, v0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, 0, v4 +; CGP-NEXT: v_mov_b32_e32 v5, v1 +; CGP-NEXT: v_mul_lo_u32 v0, v0, v6 +; CGP-NEXT: v_mul_lo_u32 v1, v5, v3 +; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v5 +; CGP-NEXT: v_sub_i32_e32 v7, vcc, v7, v1 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v0, 0 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v7, v3 +; CGP-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e64 v0, s[4:5], v6, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0 +; CGP-NEXT: v_sub_i32_e64 v8, s[4:5], v7, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v8, vcc +; CGP-NEXT: v_mov_b32_e32 v7, v1 +; CGP-NEXT: v_mul_lo_u32 v8, v7, v4 +; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v5 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v6, vcc +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 +; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v7 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v3, v7, v3, vcc +; CGP-NEXT: v_sub_i32_e64 v5, s[4:5], v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc +; CGP-NEXT: v_add_i32_e32 v5, vcc, 1, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v3, v5, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; CGP-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll index 0b22b3b3a4ba7c6215c5beaf3d80c8a7ca664859..c455b24313ddc277fbcb9a423e4f91f48b4ea48d 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll @@ -3000,21 +3000,27 @@ define i64 @v_srem_i64_24bit(i64 %num, i64 %den) { ; CGP-LABEL: v_srem_i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v2 -; CGP-NEXT: v_cvt_f32_i32_e32 v2, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v3, v0 -; CGP-NEXT: v_rcp_f32_e32 v4, v2 -; CGP-NEXT: v_mul_f32_e32 v4, v3, v4 -; CGP-NEXT: v_trunc_f32_e32 v4, v4 -; CGP-NEXT: v_mad_f32 v3, -v4, v2, v3 -; CGP-NEXT: v_cvt_i32_f32_e32 v4, v4 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v2| -; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2 -; CGP-NEXT: v_mul_lo_u32 v1, v2, v1 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 +; CGP-NEXT: v_and_b32_e32 v5, 0xffffff, v0 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v4, v1 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, 0, v3 +; CGP-NEXT: v_mul_lo_u32 v1, v1, v4 +; CGP-NEXT: v_mad_u64_u32 v[1:2], s[4:5], v4, v1, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v2 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v0, 0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_mul_lo_u32 v0, v0, v3 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v5, v0 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v0, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i64 %num, 16777215 @@ -3282,37 +3288,47 @@ define <2 x i64> @v_srem_v2i64_24bit(<2 x i64> %num, <2 x i64> %den) { ; CGP-LABEL: v_srem_v2i64_24bit: ; CGP: ; %bb.0: ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v4 -; CGP-NEXT: v_cvt_f32_i32_e32 v3, v1 -; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; CGP-NEXT: v_cvt_f32_i32_e32 v4, v0 -; CGP-NEXT: v_and_b32_e32 v6, 0xffffff, v6 -; CGP-NEXT: v_rcp_f32_e32 v5, v3 +; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v4 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v3 +; CGP-NEXT: v_and_b32_e32 v4, 0xffffff, v6 +; CGP-NEXT: v_sub_i32_e32 v6, vcc, 0, v3 +; CGP-NEXT: v_rcp_f32_e32 v1, v1 +; CGP-NEXT: v_and_b32_e32 v7, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 -; CGP-NEXT: v_mul_f32_e32 v5, v4, v5 -; CGP-NEXT: v_trunc_f32_e32 v5, v5 -; CGP-NEXT: v_mad_f32 v4, -v5, v3, v4 -; CGP-NEXT: v_cvt_i32_f32_e32 v5, v5 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, |v3| -; CGP-NEXT: v_cvt_f32_i32_e32 v4, v6 -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5] -; CGP-NEXT: v_add_i32_e32 v3, vcc, v5, v3 -; CGP-NEXT: v_mul_lo_u32 v1, v3, v1 -; CGP-NEXT: v_cvt_f32_i32_e32 v3, v2 -; CGP-NEXT: v_rcp_f32_e32 v5, v4 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 -; CGP-NEXT: v_mul_f32_e32 v1, v3, v5 -; CGP-NEXT: v_trunc_f32_e32 v1, v1 -; CGP-NEXT: v_mad_f32 v3, -v1, v4, v3 -; CGP-NEXT: v_cvt_i32_f32_e32 v1, v1 -; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v3|, |v4| -; CGP-NEXT: v_cndmask_b32_e64 v3, 0, 1, s[4:5] -; CGP-NEXT: v_bfe_i32 v0, v0, 0, 25 -; CGP-NEXT: v_add_i32_e32 v1, vcc, v1, v3 -; CGP-NEXT: v_mul_lo_u32 v3, v1, v6 +; CGP-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v5, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v4 +; CGP-NEXT: v_mul_lo_u32 v6, v6, v5 +; CGP-NEXT: v_rcp_f32_e32 v8, v1 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v5, v6, 0 +; CGP-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v8 +; CGP-NEXT: v_cvt_u32_f32_e32 v6, v0 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v5, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v7, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, 0, v4 +; CGP-NEXT: v_mul_lo_u32 v0, v0, v6 +; CGP-NEXT: v_mul_lo_u32 v5, v1, v3 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v6, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v5, vcc, v7, v5 +; CGP-NEXT: v_mov_b32_e32 v0, v1 +; CGP-NEXT: v_add_i32_e32 v0, vcc, v6, v0 +; CGP-NEXT: v_mad_u64_u32 v[0:1], s[4:5], v2, v0, 0 +; CGP-NEXT: v_sub_i32_e32 v7, vcc, v5, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v5, v3 +; CGP-NEXT: v_mul_lo_u32 v6, v1, v4 +; CGP-NEXT: v_cndmask_b32_e32 v0, v5, v7, vcc +; CGP-NEXT: v_sub_i32_e32 v5, vcc, v0, v3 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v3 +; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v5, vcc +; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 +; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v4 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc +; CGP-NEXT: v_sub_i32_e32 v3, vcc, v2, v4 +; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v2, v4 +; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc ; CGP-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 -; CGP-NEXT: v_bfe_i32 v2, v2, 0, 25 ; CGP-NEXT: v_ashrrev_i32_e32 v3, 31, v2 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and <2 x i64> %num, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir new file mode 100644 index 0000000000000000000000000000000000000000..6c13756ab1c690447588e696188b87bdd389466b --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/twoaddr-extract-dyn-v7f64.mir @@ -0,0 +1,125 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -early-live-intervals -run-pass=liveintervals -run-pass=twoaddressinstruction -verify-machineinstrs -o - %s | FileCheck %s + +--- +name: dyn_extract_v7f64_v_v +legalized: true +regBankSelected: true +selected: true +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14 + + ; CHECK-LABEL: name: dyn_extract_v7f64_v_v + ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8, $vgpr9, $vgpr10, $vgpr11, $vgpr12, $vgpr13, $vgpr14 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY $vgpr4 + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY $vgpr5 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY $vgpr6 + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY $vgpr7 + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:vgpr_32 = COPY $vgpr8 + ; CHECK-NEXT: [[COPY9:%[0-9]+]]:vgpr_32 = COPY $vgpr9 + ; CHECK-NEXT: [[COPY10:%[0-9]+]]:vgpr_32 = COPY $vgpr10 + ; CHECK-NEXT: [[COPY11:%[0-9]+]]:vgpr_32 = COPY $vgpr11 + ; CHECK-NEXT: [[COPY12:%[0-9]+]]:vgpr_32 = COPY $vgpr12 + ; CHECK-NEXT: [[COPY13:%[0-9]+]]:vgpr_32 = COPY $vgpr13 + ; CHECK-NEXT: undef [[COPY14:%[0-9]+]].sub0:vreg_64 = COPY [[COPY]] + ; CHECK-NEXT: [[COPY14:%[0-9]+]].sub1:vreg_64 = COPY [[COPY1]] + ; CHECK-NEXT: undef [[COPY15:%[0-9]+]].sub0:vreg_64 = COPY [[COPY2]] + ; CHECK-NEXT: [[COPY15:%[0-9]+]].sub1:vreg_64 = COPY [[COPY3]] + ; CHECK-NEXT: undef [[COPY16:%[0-9]+]].sub0:vreg_64 = COPY [[COPY4]] + ; CHECK-NEXT: [[COPY16:%[0-9]+]].sub1:vreg_64 = COPY [[COPY5]] + ; CHECK-NEXT: undef [[COPY17:%[0-9]+]].sub0:vreg_64 = COPY [[COPY6]] + ; CHECK-NEXT: [[COPY17:%[0-9]+]].sub1:vreg_64 = COPY [[COPY7]] + ; CHECK-NEXT: undef [[COPY18:%[0-9]+]].sub0:vreg_64 = COPY [[COPY8]] + ; CHECK-NEXT: [[COPY18:%[0-9]+]].sub1:vreg_64 = COPY [[COPY9]] + ; CHECK-NEXT: undef [[COPY19:%[0-9]+]].sub0:vreg_64 = COPY [[COPY10]] + ; CHECK-NEXT: [[COPY19:%[0-9]+]].sub1:vreg_64 = COPY [[COPY11]] + ; CHECK-NEXT: undef [[COPY20:%[0-9]+]].sub0:vreg_64 = COPY [[COPY12]] + ; CHECK-NEXT: [[COPY20:%[0-9]+]].sub1:vreg_64 = COPY [[COPY13]] + ; CHECK-NEXT: [[COPY21:%[0-9]+]]:vgpr_32 = COPY $vgpr14 + ; CHECK-NEXT: undef [[COPY22:%[0-9]+]].sub0_sub1:vreg_512 = COPY [[COPY14]] + ; CHECK-NEXT: [[COPY22:%[0-9]+]].sub2_sub3:vreg_512 = COPY [[COPY15]] + ; CHECK-NEXT: [[COPY22:%[0-9]+]].sub4_sub5:vreg_512 = COPY [[COPY16]] + ; CHECK-NEXT: [[COPY22:%[0-9]+]].sub6_sub7:vreg_512 = COPY [[COPY17]] + ; CHECK-NEXT: [[COPY22:%[0-9]+]].sub8_sub9:vreg_512 = COPY [[COPY18]] + ; CHECK-NEXT: [[COPY22:%[0-9]+]].sub10_sub11:vreg_512 = COPY [[COPY19]] + ; CHECK-NEXT: [[COPY22:%[0-9]+]].sub12_sub13:vreg_512 = COPY [[COPY20]] + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 1, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY22]].sub0, 0, [[COPY22]].sub2, [[V_CMP_EQ_U32_e64_]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[COPY22]].sub1, 0, [[COPY22]].sub3, [[V_CMP_EQ_U32_e64_]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 2, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_2:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_]], 0, [[COPY22]].sub4, [[V_CMP_EQ_U32_e64_1]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_3:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_1]], 0, [[COPY22]].sub5, [[V_CMP_EQ_U32_e64_1]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_2:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 3, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_4:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_2]], 0, [[COPY22]].sub6, [[V_CMP_EQ_U32_e64_2]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_5:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_3]], 0, [[COPY22]].sub7, [[V_CMP_EQ_U32_e64_2]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_3:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 4, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_6:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_4]], 0, [[COPY22]].sub8, [[V_CMP_EQ_U32_e64_3]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_7:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_5]], 0, [[COPY22]].sub9, [[V_CMP_EQ_U32_e64_3]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_4:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 5, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_8:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_6]], 0, [[COPY22]].sub10, [[V_CMP_EQ_U32_e64_4]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_9:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_7]], 0, [[COPY22]].sub11, [[V_CMP_EQ_U32_e64_4]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_5:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 6, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_10:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_8]], 0, [[COPY22]].sub12, [[V_CMP_EQ_U32_e64_5]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_11:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_9]], 0, [[COPY22]].sub13, [[V_CMP_EQ_U32_e64_5]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_6:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 7, [[COPY21]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_12:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_10]], 0, undef [[COPY22]].sub14, [[V_CMP_EQ_U32_e64_6]], implicit $exec + ; CHECK-NEXT: [[V_CNDMASK_B32_e64_13:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, [[V_CNDMASK_B32_e64_11]], 0, undef [[COPY22]].sub15, [[V_CMP_EQ_U32_e64_6]], implicit $exec + ; CHECK-NEXT: $vgpr0 = COPY [[V_CNDMASK_B32_e64_12]] + ; CHECK-NEXT: $vgpr1 = COPY [[V_CNDMASK_B32_e64_13]] + ; CHECK-NEXT: SI_RETURN implicit $vgpr0, implicit $vgpr1 + %2:vgpr_32 = COPY $vgpr0 + %3:vgpr_32 = COPY $vgpr1 + %4:vgpr_32 = COPY $vgpr2 + %5:vgpr_32 = COPY $vgpr3 + %6:vgpr_32 = COPY $vgpr4 + %7:vgpr_32 = COPY $vgpr5 + %8:vgpr_32 = COPY $vgpr6 + %9:vgpr_32 = COPY $vgpr7 + %10:vgpr_32 = COPY $vgpr8 + %11:vgpr_32 = COPY $vgpr9 + %12:vgpr_32 = COPY $vgpr10 + %13:vgpr_32 = COPY $vgpr11 + %14:vgpr_32 = COPY $vgpr12 + %15:vgpr_32 = COPY $vgpr13 + %16:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1 + %17:vreg_64 = REG_SEQUENCE %4, %subreg.sub0, %5, %subreg.sub1 + %18:vreg_64 = REG_SEQUENCE %6, %subreg.sub0, %7, %subreg.sub1 + %19:vreg_64 = REG_SEQUENCE %8, %subreg.sub0, %9, %subreg.sub1 + %20:vreg_64 = REG_SEQUENCE %10, %subreg.sub0, %11, %subreg.sub1 + %21:vreg_64 = REG_SEQUENCE %12, %subreg.sub0, %13, %subreg.sub1 + %22:vreg_64 = REG_SEQUENCE %14, %subreg.sub0, %15, %subreg.sub1 + %1:vgpr_32 = COPY $vgpr14 + %34:vreg_512 = REG_SEQUENCE %16, %subreg.sub0_sub1, %17, %subreg.sub2_sub3, %18, %subreg.sub4_sub5, %19, %subreg.sub6_sub7, %20, %subreg.sub8_sub9, %21, %subreg.sub10_sub11, %22, %subreg.sub12_sub13, undef %35:vreg_64, %subreg.sub14_sub15 + %55:sreg_64_xexec = V_CMP_EQ_U32_e64 1, %1, implicit $exec + %56:vgpr_32 = V_CNDMASK_B32_e64 0, %34.sub0, 0, %34.sub2, %55, implicit $exec + %57:vgpr_32 = V_CNDMASK_B32_e64 0, %34.sub1, 0, %34.sub3, %55, implicit $exec + %59:sreg_64_xexec = V_CMP_EQ_U32_e64 2, %1, implicit $exec + %60:vgpr_32 = V_CNDMASK_B32_e64 0, %56, 0, %34.sub4, %59, implicit $exec + %61:vgpr_32 = V_CNDMASK_B32_e64 0, %57, 0, %34.sub5, %59, implicit $exec + %63:sreg_64_xexec = V_CMP_EQ_U32_e64 3, %1, implicit $exec + %64:vgpr_32 = V_CNDMASK_B32_e64 0, %60, 0, %34.sub6, %63, implicit $exec + %65:vgpr_32 = V_CNDMASK_B32_e64 0, %61, 0, %34.sub7, %63, implicit $exec + %67:sreg_64_xexec = V_CMP_EQ_U32_e64 4, %1, implicit $exec + %68:vgpr_32 = V_CNDMASK_B32_e64 0, %64, 0, %34.sub8, %67, implicit $exec + %69:vgpr_32 = V_CNDMASK_B32_e64 0, %65, 0, %34.sub9, %67, implicit $exec + %71:sreg_64_xexec = V_CMP_EQ_U32_e64 5, %1, implicit $exec + %72:vgpr_32 = V_CNDMASK_B32_e64 0, %68, 0, %34.sub10, %71, implicit $exec + %73:vgpr_32 = V_CNDMASK_B32_e64 0, %69, 0, %34.sub11, %71, implicit $exec + %75:sreg_64_xexec = V_CMP_EQ_U32_e64 6, %1, implicit $exec + %76:vgpr_32 = V_CNDMASK_B32_e64 0, %72, 0, %34.sub12, %75, implicit $exec + %77:vgpr_32 = V_CNDMASK_B32_e64 0, %73, 0, %34.sub13, %75, implicit $exec + %79:sreg_64_xexec = V_CMP_EQ_U32_e64 7, %1, implicit $exec + %80:vgpr_32 = V_CNDMASK_B32_e64 0, %76, 0, %34.sub14, %79, implicit $exec + %81:vgpr_32 = V_CNDMASK_B32_e64 0, %77, 0, %34.sub15, %79, implicit $exec + $vgpr0 = COPY %80 + $vgpr1 = COPY %81 + SI_RETURN implicit $vgpr0, implicit $vgpr1 + +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll index 6588112973f4c9417a712b678fd81581f4b07e08..cd01148fa7dd77ce6add56f81936a8a00775df5b 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i32.ll @@ -415,25 +415,17 @@ define i32 @v_udiv_i32_24bit(i32 %num, i32 %den) { ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1 -; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; CGP-NEXT: v_rcp_f32_e32 v2, v2 -; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1 +; CGP-NEXT: v_rcp_f32_e32 v2, v1 +; CGP-NEXT: v_mul_f32_e32 v2, v0, v2 +; CGP-NEXT: v_trunc_f32_e32 v2, v2 +; CGP-NEXT: v_fma_f32 v0, -v2, v1, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 -; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CGP-NEXT: v_mul_hi_u32 v2, v0, v2 -; CGP-NEXT: v_mul_lo_u32 v3, v2, v1 -; CGP-NEXT: v_add_i32_e32 v4, vcc, 1, v2 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v3 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc -; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc -; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v2 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v1 +; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v0, vcc, v2, v0 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i32 %num, 16777215 %den.mask = and i32 %den, 16777215 @@ -496,44 +488,28 @@ define <2 x i32> @v_udiv_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) { ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2 -; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3 -; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 -; CGP-NEXT: v_rcp_f32_e32 v4, v4 -; CGP-NEXT: v_rcp_f32_e32 v6, v6 -; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4 -; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 +; CGP-NEXT: v_cvt_f32_u32_e32 v0, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v2, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v1, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v3, v3 +; CGP-NEXT: v_rcp_f32_e32 v4, v2 +; CGP-NEXT: v_rcp_f32_e32 v5, v3 +; CGP-NEXT: v_mul_f32_e32 v4, v0, v4 +; CGP-NEXT: v_mul_f32_e32 v5, v1, v5 +; CGP-NEXT: v_trunc_f32_e32 v4, v4 +; CGP-NEXT: v_trunc_f32_e32 v5, v5 +; CGP-NEXT: v_fma_f32 v0, -v4, v2, v0 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 -; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 -; CGP-NEXT: v_mul_lo_u32 v5, v5, v4 -; CGP-NEXT: v_mul_lo_u32 v7, v7, v6 -; CGP-NEXT: v_mul_hi_u32 v5, v4, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v6, v7 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7 -; CGP-NEXT: v_mul_hi_u32 v4, v0, v4 -; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v6, v4, v2 -; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v4 -; CGP-NEXT: v_mul_lo_u32 v8, v5, v3 -; CGP-NEXT: v_add_i32_e32 v9, vcc, 1, v5 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v6 -; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v8 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc -; CGP-NEXT: v_sub_i32_e64 v6, s[4:5], v0, v2 -; CGP-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v3 -; CGP-NEXT: v_cndmask_b32_e64 v5, v5, v9, s[4:5] -; CGP-NEXT: v_sub_i32_e64 v7, s[6:7], v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v6, vcc -; CGP-NEXT: v_add_i32_e32 v6, vcc, 1, v4 -; CGP-NEXT: v_cndmask_b32_e64 v1, v1, v7, s[4:5] -; CGP-NEXT: v_add_i32_e32 v7, vcc, 1, v5 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v0, v4, v6, vcc -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v1, v5, v7, vcc +; CGP-NEXT: v_fma_f32 v1, -v5, v3, v1 +; CGP-NEXT: v_cvt_u32_f32_e32 v5, v5 +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v0|, v2 +; CGP-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, v3 +; CGP-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v0, vcc, v4, v0 +; CGP-NEXT: v_add_i32_e32 v1, vcc, v5, v1 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and <2 x i32> %num, %den.mask = and <2 x i32> %den, diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll index 158403644607abe2d7c3da0320d14dbf6e160867..31f61b9968b8bf7484eaf368ab53679532dcfc11 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i32.ll @@ -445,23 +445,19 @@ define i32 @v_urem_i32_24bit(i32 %num, i32 %den) { ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 -; CGP-NEXT: v_cvt_f32_u32_e32 v2, v1 -; CGP-NEXT: v_sub_i32_e32 v3, vcc, 0, v1 -; CGP-NEXT: v_rcp_f32_e32 v2, v2 -; CGP-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 -; CGP-NEXT: v_cvt_u32_f32_e32 v2, v2 -; CGP-NEXT: v_mul_lo_u32 v3, v3, v2 -; CGP-NEXT: v_mul_hi_u32 v3, v2, v3 -; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v3 -; CGP-NEXT: v_mul_hi_u32 v2, v0, v2 -; CGP-NEXT: v_mul_lo_u32 v2, v2, v1 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc -; CGP-NEXT: v_sub_i32_e32 v2, vcc, v0, v1 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc +; CGP-NEXT: v_cvt_f32_u32_e32 v2, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v3, v1 +; CGP-NEXT: v_rcp_f32_e32 v4, v3 +; CGP-NEXT: v_mul_f32_e32 v4, v2, v4 +; CGP-NEXT: v_trunc_f32_e32 v4, v4 +; CGP-NEXT: v_fma_f32 v2, -v4, v3, v2 +; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v2|, v3 +; CGP-NEXT: v_cndmask_b32_e64 v2, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v2, vcc, v4, v2 +; CGP-NEXT: v_mul_lo_u32 v1, v2, v1 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v1 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and i32 %num, 16777215 %den.mask = and i32 %den, 16777215 @@ -520,40 +516,32 @@ define <2 x i32> @v_urem_v2i32_24bit(<2 x i32> %num, <2 x i32> %den) { ; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; CGP-NEXT: v_and_b32_e32 v3, 0xffffff, v3 -; CGP-NEXT: v_cvt_f32_u32_e32 v4, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, 0, v2 -; CGP-NEXT: v_cvt_f32_u32_e32 v6, v3 -; CGP-NEXT: v_sub_i32_e32 v7, vcc, 0, v3 -; CGP-NEXT: v_rcp_f32_e32 v4, v4 -; CGP-NEXT: v_rcp_f32_e32 v6, v6 -; CGP-NEXT: v_mul_f32_e32 v4, 0x4f7ffffe, v4 -; CGP-NEXT: v_mul_f32_e32 v6, 0x4f7ffffe, v6 -; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 -; CGP-NEXT: v_cvt_u32_f32_e32 v6, v6 -; CGP-NEXT: v_mul_lo_u32 v5, v5, v4 -; CGP-NEXT: v_mul_lo_u32 v7, v7, v6 -; CGP-NEXT: v_mul_hi_u32 v5, v4, v5 -; CGP-NEXT: v_mul_hi_u32 v7, v6, v7 -; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 -; CGP-NEXT: v_add_i32_e32 v5, vcc, v6, v7 -; CGP-NEXT: v_mul_hi_u32 v4, v0, v4 -; CGP-NEXT: v_mul_hi_u32 v5, v1, v5 -; CGP-NEXT: v_mul_lo_u32 v4, v4, v2 -; CGP-NEXT: v_mul_lo_u32 v5, v5, v3 -; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v4 -; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v5 -; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc -; CGP-NEXT: v_sub_i32_e32 v4, vcc, v0, v2 -; CGP-NEXT: v_sub_i32_e32 v5, vcc, v1, v3 -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 -; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc -; CGP-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 -; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v5, vcc +; CGP-NEXT: v_cvt_f32_u32_e32 v4, v0 +; CGP-NEXT: v_cvt_f32_u32_e32 v5, v2 +; CGP-NEXT: v_cvt_f32_u32_e32 v6, v1 +; CGP-NEXT: v_cvt_f32_u32_e32 v7, v3 +; CGP-NEXT: v_rcp_f32_e32 v8, v5 +; CGP-NEXT: v_rcp_f32_e32 v9, v7 +; CGP-NEXT: v_mul_f32_e32 v8, v4, v8 +; CGP-NEXT: v_mul_f32_e32 v9, v6, v9 +; CGP-NEXT: v_trunc_f32_e32 v8, v8 +; CGP-NEXT: v_trunc_f32_e32 v9, v9 +; CGP-NEXT: v_fma_f32 v4, -v8, v5, v4 +; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 +; CGP-NEXT: v_fma_f32 v6, -v9, v7, v6 +; CGP-NEXT: v_cvt_u32_f32_e32 v9, v9 +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v4|, v5 +; CGP-NEXT: v_cndmask_b32_e64 v4, 0, 1, s[4:5] +; CGP-NEXT: v_cmp_ge_f32_e64 s[4:5], |v6|, v7 +; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] +; CGP-NEXT: v_add_i32_e32 v4, vcc, v8, v4 +; CGP-NEXT: v_add_i32_e32 v5, vcc, v9, v5 +; CGP-NEXT: v_mul_lo_u32 v2, v4, v2 +; CGP-NEXT: v_mul_lo_u32 v3, v5, v3 +; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v2 +; CGP-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; CGP-NEXT: v_and_b32_e32 v0, 0xffffff, v0 +; CGP-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; CGP-NEXT: s_setpc_b64 s[30:31] %num.mask = and <2 x i32> %num, %den.mask = and <2 x i32> %den, diff --git a/llvm/test/CodeGen/AMDGPU/bypass-div.ll b/llvm/test/CodeGen/AMDGPU/bypass-div.ll index cb1b664549c9a3047c500cd0c134bb86abcb0d71..4d8687b141a79af005d73fba3226dad234baed1d 100644 --- a/llvm/test/CodeGen/AMDGPU/bypass-div.ll +++ b/llvm/test/CodeGen/AMDGPU/bypass-div.ll @@ -1024,16 +1024,25 @@ define i64 @sdiv64_known32(i64 %a, i64 %b) { ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v3 -; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v1 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GFX9-NEXT: v_mul_f32_e32 v2, v1, v2 -; GFX9-NEXT: v_trunc_f32_e32 v2, v2 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GFX9-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GFX9-NEXT: v_sub_u32_e32 v2, 0, v3 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GFX9-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GFX9-NEXT: v_mul_lo_u32 v2, v2, v0 +; GFX9-NEXT: v_mul_hi_u32 v2, v0, v2 +; GFX9-NEXT: v_add_u32_e32 v0, v0, v2 +; GFX9-NEXT: v_mul_hi_u32 v0, v1, v0 +; GFX9-NEXT: v_mul_lo_u32 v2, v0, v3 +; GFX9-NEXT: v_add_u32_e32 v4, 1, v0 +; GFX9-NEXT: v_sub_u32_e32 v1, v1, v2 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GFX9-NEXT: v_sub_u32_e32 v2, v1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; GFX9-NEXT: v_add_u32_e32 v2, 1, v0 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v1, v3 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc -; GFX9-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GFX9-NEXT: s_setpc_b64 s[30:31] %a.ext = ashr i64 %a, 32 %b.ext = ashr i64 %b, 32 @@ -1046,15 +1055,25 @@ define i64 @udiv64_known32(i64 %a, i64 %b) { ; GFX9: ; %bb.0: ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: v_cvt_f32_u32_e32 v1, v2 -; GFX9-NEXT: v_cvt_f32_u32_e32 v0, v0 -; GFX9-NEXT: v_rcp_iflag_f32_e32 v2, v1 -; GFX9-NEXT: v_mul_f32_e32 v2, v0, v2 -; GFX9-NEXT: v_trunc_f32_e32 v2, v2 -; GFX9-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GFX9-NEXT: v_mad_f32 v0, -v2, v1, v0 -; GFX9-NEXT: v_cmp_ge_f32_e64 vcc, |v0|, v1 +; GFX9-NEXT: v_sub_u32_e32 v3, 0, v2 +; GFX9-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GFX9-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 +; GFX9-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GFX9-NEXT: v_mul_lo_u32 v3, v3, v1 +; GFX9-NEXT: v_mul_hi_u32 v3, v1, v3 +; GFX9-NEXT: v_add_u32_e32 v1, v1, v3 +; GFX9-NEXT: v_mul_hi_u32 v1, v0, v1 +; GFX9-NEXT: v_mul_lo_u32 v3, v1, v2 +; GFX9-NEXT: v_add_u32_e32 v4, 1, v1 +; GFX9-NEXT: v_sub_u32_e32 v0, v0, v3 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GFX9-NEXT: v_sub_u32_e32 v3, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc +; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc +; GFX9-NEXT: v_add_u32_e32 v3, 1, v1 +; GFX9-NEXT: v_cmp_ge_u32_e32 vcc, v0, v2 +; GFX9-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc ; GFX9-NEXT: v_mov_b32_e32 v1, 0 -; GFX9-NEXT: v_addc_co_u32_e32 v0, vcc, 0, v3, vcc ; GFX9-NEXT: s_setpc_b64 s[30:31] %a.mask = and i64 %a, 4294967295 %b.mask = and i64 %b, 4294967295 diff --git a/llvm/test/CodeGen/AMDGPU/ctpop64.ll b/llvm/test/CodeGen/AMDGPU/ctpop64.ll index 1346678e51e3dd33171ff4b37a11002c79d48309..3b9c3e3ba1752346736f8db6f4a5bef5e82a7397 100644 --- a/llvm/test/CodeGen/AMDGPU/ctpop64.ll +++ b/llvm/test/CodeGen/AMDGPU/ctpop64.ll @@ -452,12 +452,11 @@ define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val) ; SI-NEXT: s_mov_b32 s2, -1 ; SI-NEXT: s_waitcnt lgkmcnt(0) ; SI-NEXT: s_mov_b32 s0, s4 +; SI-NEXT: s_and_b32 s4, s8, 0xff ; SI-NEXT: s_mov_b32 s1, s5 -; SI-NEXT: s_and_b32 s4, s8, 1 -; SI-NEXT: s_mov_b32 s5, 0 -; SI-NEXT: s_bcnt1_i32_b64 s6, s[6:7] -; SI-NEXT: s_bcnt1_i32_b64 s4, s[4:5] -; SI-NEXT: s_add_i32 s4, s6, s4 +; SI-NEXT: s_bcnt1_i32_b32 s4, s4 +; SI-NEXT: s_bcnt1_i32_b64 s5, s[6:7] +; SI-NEXT: s_add_i32 s4, s5, s4 ; SI-NEXT: v_mov_b32_e32 v0, s4 ; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; SI-NEXT: s_endpgm @@ -470,12 +469,11 @@ define amdgpu_kernel void @s_ctpop_i65(ptr addrspace(1) noalias %out, i65 %val) ; VI-NEXT: s_mov_b32 s2, -1 ; VI-NEXT: s_waitcnt lgkmcnt(0) ; VI-NEXT: s_mov_b32 s0, s4 +; VI-NEXT: s_and_b32 s4, s8, 0xff ; VI-NEXT: s_mov_b32 s1, s5 -; VI-NEXT: s_and_b32 s4, s8, 1 -; VI-NEXT: s_mov_b32 s5, 0 -; VI-NEXT: s_bcnt1_i32_b64 s6, s[6:7] -; VI-NEXT: s_bcnt1_i32_b64 s4, s[4:5] -; VI-NEXT: s_add_i32 s4, s6, s4 +; VI-NEXT: s_bcnt1_i32_b32 s4, s4 +; VI-NEXT: s_bcnt1_i32_b64 s5, s[6:7] +; VI-NEXT: s_add_i32 s4, s5, s4 ; VI-NEXT: v_mov_b32_e32 v0, s4 ; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 ; VI-NEXT: s_endpgm diff --git a/llvm/test/CodeGen/AMDGPU/idot4u.ll b/llvm/test/CodeGen/AMDGPU/idot4u.ll index ba9ccb4c636f948108c3bea4c3eed6f49f4eaac8..9a1de74034cd8353de71787c6f47aedf759f31fa 100644 --- a/llvm/test/CodeGen/AMDGPU/idot4u.ll +++ b/llvm/test/CodeGen/AMDGPU/idot4u.ll @@ -4884,6 +4884,1093 @@ entry: ret void } +define amdgpu_kernel void @idot4_acc32_hilo(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_hilo: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, 0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11] +; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64 offset:4 +; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8 +; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2 +; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v0 +; GFX7-NEXT: v_mul_u32_u24_e32 v4, v4, v5 +; GFX7-NEXT: v_bfe_u32 v6, v2, 16, 8 +; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8 +; GFX7-NEXT: v_mad_u32_u24 v1, v1, v3, v4 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0 +; GFX7-NEXT: v_mad_u32_u24 v1, v6, v7, v1 +; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_hilo: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s4, v0 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s7 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v4, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_dword v2, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v4 +; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 8 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_and_b32_e32 v6, 0xff, v2 +; GFX8-NEXT: v_mul_u32_u24_sdwa v7, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX8-NEXT: v_bfe_u32 v8, v2, 16, 8 +; GFX8-NEXT: v_mad_u32_u24 v3, v6, v3, v7 +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 24, v4 +; GFX8-NEXT: v_mad_u32_u24 v3, v8, v5, v3 +; GFX8-NEXT: v_mad_u32_u24 v2, v2, v4, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_hilo: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5] offset:4 +; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, v5 +; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v6, v1 +; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_hilo: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dword v1, v0, s[4:5] offset:4 +; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, 0 +; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_hilo: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: s_clause 0x1 +; GFX10-DL-NEXT: global_load_dword v1, v0, s[4:5] offset:4 +; GFX10-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX10-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_dot4_u32_u8 v1, v1, v2, 0 +; GFX10-DL-NEXT: global_store_dword v0, v1, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_hilo: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: s_clause 0x1 +; GFX11-DL-NEXT: global_load_b32 v1, v0, s[4:5] offset:4 +; GFX11-DL-NEXT: global_load_b32 v0, v0, s[6:7] +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <8 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <8 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <8 x i8> %vec1, i64 4 + %cv1e0 = zext i8 %v1e0 to i32 + %v2e0 = extractelement <8 x i8> %vec2, i64 0 + %cv2e0 = zext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i8> %vec1, i64 5 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <8 x i8> %vec2, i64 1 + %cv2e1 = zext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i8> %vec1, i64 6 + %cv1e2 = zext i8 %v1e2 to i32 + %v2e2 = extractelement <8 x i8> %vec2, i64 2 + %cv2e2 = zext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i8> %vec1, i64 7 + %cv1e3 = zext i8 %v1e3 to i32 + %v2e3 = extractelement <8 x i8> %vec2, i64 3 + %cv2e3 = zext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %add1 = add i32 %mul1, 0 + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, ptr addrspace(1) %dst, align 4 + ret void +} + +define amdgpu_kernel void @idot4_acc32_lohi(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_lohi: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, 0 +; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 +; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 offset:4 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_bfe_u32 v3, v2, 8, 8 +; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_bfe_u32 v6, v0, 16, 8 +; GFX7-NEXT: v_lshrrev_b32_e32 v5, 24, v0 +; GFX7-NEXT: v_mul_u32_u24_e32 v3, v3, v6 +; GFX7-NEXT: v_bfe_u32 v4, v2, 16, 8 +; GFX7-NEXT: v_bfe_u32 v7, v0, 8, 8 +; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, v3 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX7-NEXT: v_and_b32_e32 v0, 0xff, v0 +; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1 +; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_lohi: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v2, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s6, v2 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_dword v4, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_dword v2, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v4 +; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 8 +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 24, v4 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v7, 24, v2 +; GFX8-NEXT: v_mul_u32_u24_sdwa v4, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_2 +; GFX8-NEXT: v_bfe_u32 v8, v2, 8, 8 +; GFX8-NEXT: v_mad_u32_u24 v3, v3, v7, v4 +; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v2 +; GFX8-NEXT: v_mad_u32_u24 v3, v5, v8, v3 +; GFX8-NEXT: v_mad_u32_u24 v2, v6, v2, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_lohi: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5] +; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7] offset:4 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v4, 24, v2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_0 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, v5 +; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v6, v1 +; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_lohi: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-DL-NEXT: s_mov_b32 s0, 0x10302 +; GFX9-DL-NEXT: s_mov_b32 s1, 0x3020001 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7] offset:4 +; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5] +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(1) +; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1 +; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, 0 +; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_lohi: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: s_clause 0x1 +; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7] offset:4 +; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] +; GFX10-DL-NEXT: s_waitcnt vmcnt(1) +; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0x10302 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0x3020001 +; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0 +; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_lohi: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: s_clause 0x1 +; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7] offset:4 +; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5] +; GFX11-DL-NEXT: s_waitcnt vmcnt(1) +; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0x10302 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0x3020001 +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, 0 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <8 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <8 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <8 x i8> %vec1, i64 0 + %cv1e0 = zext i8 %v1e0 to i32 + %v2e0 = extractelement <8 x i8> %vec2, i64 7 + %cv2e0 = zext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i8> %vec1, i64 1 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <8 x i8> %vec2, i64 6 + %cv2e1 = zext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i8> %vec1, i64 2 + %cv1e2 = zext i8 %v1e2 to i32 + %v2e2 = extractelement <8 x i8> %vec2, i64 5 + %cv2e2 = zext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i8> %vec1, i64 3 + %cv1e3 = zext i8 %v1e3 to i32 + %v2e3 = extractelement <8 x i8> %vec2, i64 4 + %cv2e3 = zext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %add1 = add i32 %mul1, 0 + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, ptr addrspace(1) %dst, align 4 + ret void +} + +define amdgpu_kernel void @idot4_acc32_hihi(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_hihi: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, 0 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX7-NEXT: buffer_load_dword v2, v[0:1], s[8:11], 0 addr64 offset:4 +; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX7-NEXT: buffer_load_dword v0, v[0:1], s[8:11], 0 addr64 offset:4 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_bfe_u32 v3, v2, 16, 8 +; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0 +; GFX7-NEXT: v_bfe_u32 v5, v0, 16, 8 +; GFX7-NEXT: v_mul_u32_u24_e32 v3, v3, v6 +; GFX7-NEXT: v_bfe_u32 v4, v2, 8, 8 +; GFX7-NEXT: v_lshrrev_b32_e32 v7, 24, v0 +; GFX7-NEXT: v_mad_u32_u24 v1, v1, v5, v3 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 +; GFX7-NEXT: v_mad_u32_u24 v1, v4, v7, v1 +; GFX7-NEXT: v_mad_u32_u24 v0, v2, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_hihi: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s5 +; GFX8-NEXT: v_add_u32_e32 v2, vcc, s4, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_add_u32_e32 v4, vcc, s6, v0 +; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v2 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v2, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, 4, v4 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_dword v3, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_and_b32_e32 v4, 0xff, v2 +; GFX8-NEXT: v_bfe_u32 v7, v2, 8, 8 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_bfe_u32 v5, v3, 16, 8 +; GFX8-NEXT: v_mul_u32_u24_sdwa v6, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_0 +; GFX8-NEXT: v_lshrrev_b32_e32 v8, 24, v3 +; GFX8-NEXT: v_mad_u32_u24 v4, v4, v5, v6 +; GFX8-NEXT: v_lshrrev_b32_e32 v2, 24, v2 +; GFX8-NEXT: v_bfe_u32 v3, v3, 8, 8 +; GFX8-NEXT: v_mad_u32_u24 v4, v7, v8, v4 +; GFX8-NEXT: v_mad_u32_u24 v2, v2, v3, v4 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_hihi: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dword v1, v0, s[4:5] offset:4 +; GFX9-NODL-NEXT: global_load_dword v2, v0, s[6:7] offset:4 +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v1 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_bfe_u32 v4, v2, 16, 8 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_0 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_3 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v3, v4, v5 +; GFX9-NODL-NEXT: v_add3_u32 v1, v2, v6, v1 +; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_hihi: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-DL-NEXT: s_mov_b32 s0, 0x1030200 +; GFX9-DL-NEXT: s_mov_b32 s1, 0x3010002 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dword v1, v0, s[6:7] offset:4 +; GFX9-DL-NEXT: global_load_dword v2, v0, s[4:5] offset:4 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(1) +; GFX9-DL-NEXT: v_perm_b32 v1, v1, v1, s0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_perm_b32 v2, v2, v2, s1 +; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, 0 +; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_hihi: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: s_clause 0x1 +; GFX10-DL-NEXT: global_load_dword v1, v0, s[6:7] offset:4 +; GFX10-DL-NEXT: global_load_dword v2, v0, s[4:5] offset:4 +; GFX10-DL-NEXT: s_waitcnt vmcnt(1) +; GFX10-DL-NEXT: v_perm_b32 v0, v1, v1, 0x1030200 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_perm_b32 v1, v2, v2, 0x3010002 +; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0 +; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_hihi: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: s_clause 0x1 +; GFX11-DL-NEXT: global_load_b32 v1, v0, s[6:7] offset:4 +; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5] offset:4 +; GFX11-DL-NEXT: s_waitcnt vmcnt(1) +; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0x1030200 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0x3010002 +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, 0 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <8 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <8 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <8 x i8> %vec1, i64 4 + %cv1e0 = zext i8 %v1e0 to i32 + %v2e0 = extractelement <8 x i8> %vec2, i64 6 + %cv2e0 = zext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i8> %vec1, i64 6 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <8 x i8> %vec2, i64 4 + %cv2e1 = zext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i8> %vec1, i64 5 + %cv1e2 = zext i8 %v1e2 to i32 + %v2e2 = extractelement <8 x i8> %vec2, i64 7 + %cv2e2 = zext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i8> %vec1, i64 7 + %cv1e3 = zext i8 %v1e3 to i32 + %v2e3 = extractelement <8 x i8> %vec2, i64 5 + %cv2e3 = zext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %add1 = add i32 %mul1, 0 + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, ptr addrspace(1) %dst, align 4 + ret void +} + +define amdgpu_kernel void @idot4_acc32_v8i8(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_v8i8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s6, 0 +; GFX7-NEXT: s_mov_b32 s7, s3 +; GFX7-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX7-NEXT: v_mov_b32_e32 v1, 0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: buffer_load_dwordx2 v[0:1], v[0:1], s[4:7], 0 addr64 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_bfe_u32 v4, v0, 8, 8 +; GFX7-NEXT: v_bfe_u32 v5, v1, 8, 8 +; GFX7-NEXT: v_and_b32_e32 v2, 0xff, v0 +; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v1 +; GFX7-NEXT: v_mul_u32_u24_e32 v4, v4, v5 +; GFX7-NEXT: v_bfe_u32 v6, v0, 16, 8 +; GFX7-NEXT: v_bfe_u32 v7, v1, 16, 8 +; GFX7-NEXT: v_mad_u32_u24 v2, v2, v3, v4 +; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0 +; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX7-NEXT: v_mad_u32_u24 v2, v6, v7, v2 +; GFX7-NEXT: v_mad_u32_u24 v0, v0, v1, v2 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_v8i8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v1, s3 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dwordx2 v[0:1], v[0:1] +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_and_b32_e32 v2, 0xff, v0 +; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v1 +; GFX8-NEXT: v_mul_u32_u24_sdwa v4, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX8-NEXT: v_bfe_u32 v5, v0, 16, 8 +; GFX8-NEXT: v_bfe_u32 v6, v1, 16, 8 +; GFX8-NEXT: v_mad_u32_u24 v2, v2, v3, v4 +; GFX8-NEXT: v_lshrrev_b32_e32 v0, 24, v0 +; GFX8-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX8-NEXT: v_mad_u32_u24 v2, v5, v6, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v0, v1, v2 +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_v8i8: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-NODL-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_and_b32_e32 v3, 0xff, v0 +; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v1 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 +; GFX9-NODL-NEXT: v_mad_u32_u24 v1, v3, v4, v5 +; GFX9-NODL-NEXT: v_add3_u32 v0, v1, v6, v0 +; GFX9-NODL-NEXT: global_store_dword v2, v0, s[4:5] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_v8i8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, 0 +; GFX9-DL-NEXT: global_store_dword v2, v0, s[4:5] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_v8i8: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: global_load_dwordx2 v[0:1], v0, s[2:3] +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, 0 +; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_v8i8: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b64 s[2:3], s[0:1], 0x24 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: global_load_b64 v[0:1], v0, s[2:3] +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, 0 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <8 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <8 x i8>, ptr addrspace(1) %gep1 + + + %v1e0 = extractelement <8 x i8> %vec1, i64 0 + %cv1e0 = zext i8 %v1e0 to i32 + %v2e0 = extractelement <8 x i8> %vec1, i64 4 + %cv2e0 = zext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <8 x i8> %vec1, i64 1 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <8 x i8> %vec1, i64 5 + %cv2e1 = zext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <8 x i8> %vec1, i64 2 + %cv1e2 = zext i8 %v1e2 to i32 + %v2e2 = extractelement <8 x i8> %vec1, i64 6 + %cv2e2 = zext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <8 x i8> %vec1, i64 3 + %cv1e3 = zext i8 %v1e3 to i32 + %v2e3 = extractelement <8 x i8> %vec1, i64 7 + %cv2e3 = zext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %add1 = add i32 %mul1, 0 + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, ptr addrspace(1) %dst, align 4 + ret void +} + +define amdgpu_kernel void @idot4_acc32_v16i8(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_v16i8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[4:5] +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 4, v0 +; GFX7-NEXT: v_mov_b32_e32 v2, 0 +; GFX7-NEXT: s_mov_b64 s[4:5], s[6:7] +; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11] +; GFX7-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; GFX7-NEXT: v_mov_b32_e32 v5, v2 +; GFX7-NEXT: buffer_load_dwordx4 v[0:3], v[1:2], s[8:11], 0 addr64 +; GFX7-NEXT: buffer_load_dword v0, v[4:5], s[4:7], 0 addr64 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_and_b32_e32 v1, 0xff, v2 +; GFX7-NEXT: v_bfe_u32 v2, v2, 16, 8 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_bfe_u32 v5, v0, 8, 8 +; GFX7-NEXT: v_and_b32_e32 v4, 0xff, v0 +; GFX7-NEXT: v_mul_u32_u24_e32 v2, v2, v5 +; GFX7-NEXT: v_bfe_u32 v6, v3, 8, 8 +; GFX7-NEXT: v_bfe_u32 v7, v0, 16, 8 +; GFX7-NEXT: v_mad_u32_u24 v1, v1, v4, v2 +; GFX7-NEXT: v_lshrrev_b32_e32 v3, 24, v3 +; GFX7-NEXT: v_lshrrev_b32_e32 v0, 24, v0 +; GFX7-NEXT: v_mad_u32_u24 v1, v6, v7, v1 +; GFX7-NEXT: v_mad_u32_u24 v0, v3, v0, v1 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_v16i8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 4, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_add_u32_e32 v1, vcc, s4, v1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v3, s7 +; GFX8-NEXT: v_add_u32_e32 v4, vcc, s6, v0 +; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v3, vcc +; GFX8-NEXT: flat_load_dwordx4 v[0:3], v[1:2] +; GFX8-NEXT: flat_load_dword v4, v[4:5] +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: v_and_b32_e32 v5, 0xff, v2 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_and_b32_e32 v6, 0xff, v4 +; GFX8-NEXT: v_mul_u32_u24_sdwa v2, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_1 +; GFX8-NEXT: v_bfe_u32 v7, v3, 8, 8 +; GFX8-NEXT: v_bfe_u32 v8, v4, 16, 8 +; GFX8-NEXT: v_mad_u32_u24 v2, v5, v6, v2 +; GFX8-NEXT: v_lshrrev_b32_e32 v3, 24, v3 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 24, v4 +; GFX8-NEXT: v_mad_u32_u24 v2, v7, v8, v2 +; GFX8-NEXT: v_mad_u32_u24 v2, v3, v4, v2 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_v16i8: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v4, 4, v0 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v5, 3, v0 +; GFX9-NODL-NEXT: ; kill: killed $vgpr5 +; GFX9-NODL-NEXT: ; kill: killed $vgpr4 +; GFX9-NODL-NEXT: ; kill: killed $sgpr4_sgpr5_sgpr6 killed $sgpr7 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dwordx4 v[0:3], v4, s[4:5] +; GFX9-NODL-NEXT: global_load_dword v0, v5, s[6:7] +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v2 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_and_b32_e32 v5, 0xff, v0 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v2, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v0, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_3 src1_sel:BYTE_3 +; GFX9-NODL-NEXT: v_mad_u32_u24 v2, v4, v5, v2 +; GFX9-NODL-NEXT: v_add3_u32 v0, v2, v6, v0 +; GFX9-NODL-NEXT: global_store_dword v1, v0, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_v16i8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v4, 4, v0 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v5, 3, v0 +; GFX9-DL-NEXT: s_mov_b32 s0, 0x7050002 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dwordx4 v[0:3], v4, s[4:5] +; GFX9-DL-NEXT: global_load_dword v0, v5, s[6:7] +; GFX9-DL-NEXT: s_mov_b32 s1, 0x3020001 +; GFX9-DL-NEXT: s_waitcnt vmcnt(1) +; GFX9-DL-NEXT: v_mov_b32_e32 v1, 0 +; GFX9-DL-NEXT: ; kill: killed $vgpr5 +; GFX9-DL-NEXT: ; kill: killed $vgpr4 +; GFX9-DL-NEXT: ; kill: killed $sgpr4_sgpr5_sgpr6 killed $sgpr7 +; GFX9-DL-NEXT: v_perm_b32 v2, v3, v2, s0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_perm_b32 v0, v0, v0, s1 +; GFX9-DL-NEXT: v_dot4_u32_u8 v0, v2, v0, 0 +; GFX9-DL-NEXT: global_store_dword v1, v0, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_v16i8: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v4, 4, v0 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v5, 3, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: ; kill: killed $vgpr5 +; GFX10-DL-NEXT: ; kill: killed $vgpr4 +; GFX10-DL-NEXT: ; kill: killed $sgpr4_sgpr5_sgpr6 killed $sgpr7 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: global_load_dwordx4 v[0:3], v4, s[4:5] +; GFX10-DL-NEXT: global_load_dword v0, v5, s[6:7] +; GFX10-DL-NEXT: s_waitcnt vmcnt(1) +; GFX10-DL-NEXT: v_perm_b32 v1, v3, v2, 0x7050002 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_perm_b32 v0, v0, v0, 0x3020001 +; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0 +; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_v16i8: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v1, 4, v0 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v4, 3, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: global_load_b128 v[0:3], v1, s[4:5] +; GFX11-DL-NEXT: global_load_b32 v0, v4, s[6:7] +; GFX11-DL-NEXT: s_waitcnt vmcnt(1) +; GFX11-DL-NEXT: v_perm_b32 v1, v3, v2, 0x7050002 +; GFX11-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0x3020001 +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <16 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <16 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <8 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <16 x i8> %vec1, i64 8 + %cv1e0 = zext i8 %v1e0 to i32 + %v2e0 = extractelement <8 x i8> %vec2, i64 0 + %cv2e0 = zext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <16 x i8> %vec1, i64 10 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <8 x i8> %vec2, i64 1 + %cv2e1 = zext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <16 x i8> %vec1, i64 13 + %cv1e2 = zext i8 %v1e2 to i32 + %v2e2 = extractelement <8 x i8> %vec2, i64 2 + %cv2e2 = zext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <16 x i8> %vec1, i64 15 + %cv1e3 = zext i8 %v1e3 to i32 + %v2e3 = extractelement <8 x i8> %vec2, i64 3 + %cv2e3 = zext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %add1 = add i32 %mul1, 0 + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, ptr addrspace(1) %dst, align 4 + ret void +} + +define amdgpu_kernel void @idot4_acc32_v256i8(ptr addrspace(1) %src1, +; GFX7-LABEL: idot4_acc32_v256i8: +; GFX7: ; %bb.0: ; %entry +; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 +; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd +; GFX7-NEXT: s_mov_b32 s3, 0xf000 +; GFX7-NEXT: s_mov_b32 s10, 0 +; GFX7-NEXT: s_mov_b32 s11, s3 +; GFX7-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; GFX7-NEXT: v_mov_b32_e32 v2, 0 +; GFX7-NEXT: s_waitcnt lgkmcnt(0) +; GFX7-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX7-NEXT: s_mov_b64 s[6:7], s[10:11] +; GFX7-NEXT: v_lshlrev_b32_e32 v3, 3, v0 +; GFX7-NEXT: v_mov_b32_e32 v4, v2 +; GFX7-NEXT: buffer_load_dword v0, v[1:2], s[4:7], 0 addr64 offset:252 +; GFX7-NEXT: buffer_load_dword v1, v[3:4], s[8:11], 0 addr64 +; GFX7-NEXT: s_mov_b32 s2, -1 +; GFX7-NEXT: s_waitcnt vmcnt(1) +; GFX7-NEXT: v_bfe_u32 v4, v0, 16, 8 +; GFX7-NEXT: s_waitcnt vmcnt(0) +; GFX7-NEXT: v_bfe_u32 v5, v1, 8, 8 +; GFX7-NEXT: v_lshrrev_b32_e32 v2, 24, v0 +; GFX7-NEXT: v_and_b32_e32 v3, 0xff, v1 +; GFX7-NEXT: v_mul_u32_u24_e32 v4, v4, v5 +; GFX7-NEXT: v_and_b32_e32 v6, 0xff, v0 +; GFX7-NEXT: v_bfe_u32 v7, v1, 16, 8 +; GFX7-NEXT: v_mad_u32_u24 v2, v2, v3, v4 +; GFX7-NEXT: v_bfe_u32 v0, v0, 8, 8 +; GFX7-NEXT: v_lshrrev_b32_e32 v1, 24, v1 +; GFX7-NEXT: v_mad_u32_u24 v2, v6, v7, v2 +; GFX7-NEXT: v_mad_u32_u24 v0, v0, v1, v2 +; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; GFX7-NEXT: s_endpgm +; +; GFX8-LABEL: idot4_acc32_v256i8: +; GFX8: ; %bb.0: ; %entry +; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX8-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; GFX8-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX8-NEXT: s_movk_i32 s2, 0xfc +; GFX8-NEXT: s_waitcnt lgkmcnt(0) +; GFX8-NEXT: v_mov_b32_e32 v2, s5 +; GFX8-NEXT: v_add_u32_e32 v3, vcc, s4, v1 +; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc +; GFX8-NEXT: v_mov_b32_e32 v1, s7 +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s6, v0 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc +; GFX8-NEXT: flat_load_dword v4, v[0:1] +; GFX8-NEXT: v_add_u32_e32 v0, vcc, s2, v3 +; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v2, vcc +; GFX8-NEXT: flat_load_dword v2, v[0:1] +; GFX8-NEXT: v_mov_b32_e32 v0, s0 +; GFX8-NEXT: v_mov_b32_e32 v1, s1 +; GFX8-NEXT: s_waitcnt vmcnt(1) +; GFX8-NEXT: v_and_b32_e32 v3, 0xff, v4 +; GFX8-NEXT: v_bfe_u32 v5, v4, 16, 8 +; GFX8-NEXT: s_waitcnt vmcnt(0) +; GFX8-NEXT: v_lshrrev_b32_e32 v6, 24, v2 +; GFX8-NEXT: v_mul_u32_u24_sdwa v7, v2, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_1 +; GFX8-NEXT: v_and_b32_e32 v8, 0xff, v2 +; GFX8-NEXT: v_mad_u32_u24 v3, v6, v3, v7 +; GFX8-NEXT: v_bfe_u32 v2, v2, 8, 8 +; GFX8-NEXT: v_lshrrev_b32_e32 v4, 24, v4 +; GFX8-NEXT: v_mad_u32_u24 v3, v8, v5, v3 +; GFX8-NEXT: v_mad_u32_u24 v2, v2, v4, v3 +; GFX8-NEXT: flat_store_dword v[0:1], v2 +; GFX8-NEXT: s_endpgm +; +; GFX9-NODL-LABEL: idot4_acc32_v256i8: +; GFX9-NODL: ; %bb.0: ; %entry +; GFX9-NODL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-NODL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; GFX9-NODL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-NODL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-NODL-NEXT: global_load_dword v2, v1, s[4:5] offset:252 +; GFX9-NODL-NEXT: global_load_dword v3, v0, s[6:7] +; GFX9-NODL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(1) +; GFX9-NODL-NEXT: v_lshrrev_b32_e32 v1, 24, v2 +; GFX9-NODL-NEXT: s_waitcnt vmcnt(0) +; GFX9-NODL-NEXT: v_and_b32_e32 v4, 0xff, v3 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v5, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_2 src1_sel:BYTE_1 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v6, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_0 src1_sel:BYTE_2 +; GFX9-NODL-NEXT: v_mul_u32_u24_sdwa v2, v2, v3 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:BYTE_1 src1_sel:BYTE_3 +; GFX9-NODL-NEXT: v_mad_u32_u24 v1, v1, v4, v5 +; GFX9-NODL-NEXT: v_add3_u32 v1, v1, v6, v2 +; GFX9-NODL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-NODL-NEXT: s_endpgm +; +; GFX9-DL-LABEL: idot4_acc32_v256i8: +; GFX9-DL: ; %bb.0: ; %entry +; GFX9-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX9-DL-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v1, 8, v0 +; GFX9-DL-NEXT: v_lshlrev_b32_e32 v0, 3, v0 +; GFX9-DL-NEXT: s_mov_b32 s0, 0x3020001 +; GFX9-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX9-DL-NEXT: global_load_dword v2, v0, s[6:7] +; GFX9-DL-NEXT: global_load_dword v3, v1, s[4:5] offset:252 +; GFX9-DL-NEXT: s_mov_b32 s1, 0x1000302 +; GFX9-DL-NEXT: v_mov_b32_e32 v0, 0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(1) +; GFX9-DL-NEXT: v_perm_b32 v1, v2, v2, s0 +; GFX9-DL-NEXT: s_waitcnt vmcnt(0) +; GFX9-DL-NEXT: v_perm_b32 v2, v3, v3, s1 +; GFX9-DL-NEXT: v_dot4_u32_u8 v1, v2, v1, 0 +; GFX9-DL-NEXT: global_store_dword v0, v1, s[2:3] +; GFX9-DL-NEXT: s_endpgm +; +; GFX10-DL-LABEL: idot4_acc32_v256i8: +; GFX10-DL: ; %bb.0: ; %entry +; GFX10-DL-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v1, 3, v0 +; GFX10-DL-NEXT: v_lshlrev_b32_e32 v0, 8, v0 +; GFX10-DL-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34 +; GFX10-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX10-DL-NEXT: global_load_dword v2, v1, s[6:7] +; GFX10-DL-NEXT: global_load_dword v3, v0, s[4:5] offset:252 +; GFX10-DL-NEXT: s_waitcnt vmcnt(1) +; GFX10-DL-NEXT: v_perm_b32 v0, v2, v2, 0x3020001 +; GFX10-DL-NEXT: s_waitcnt vmcnt(0) +; GFX10-DL-NEXT: v_perm_b32 v1, v3, v3, 0x1000302 +; GFX10-DL-NEXT: v_mov_b32_e32 v2, 0 +; GFX10-DL-NEXT: v_dot4_u32_u8 v0, v1, v0, 0 +; GFX10-DL-NEXT: global_store_dword v2, v0, s[0:1] +; GFX10-DL-NEXT: s_endpgm +; +; GFX11-DL-LABEL: idot4_acc32_v256i8: +; GFX11-DL: ; %bb.0: ; %entry +; GFX11-DL-NEXT: s_load_b128 s[4:7], s[0:1], 0x24 +; GFX11-DL-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_lshlrev_b32 v1, 3, v0 +; GFX11-DL-NEXT: v_lshlrev_b32_e32 v0, 8, v0 +; GFX11-DL-NEXT: s_load_b64 s[0:1], s[0:1], 0x34 +; GFX11-DL-NEXT: s_waitcnt lgkmcnt(0) +; GFX11-DL-NEXT: global_load_b32 v1, v1, s[6:7] +; GFX11-DL-NEXT: global_load_b32 v0, v0, s[4:5] offset:252 +; GFX11-DL-NEXT: s_waitcnt vmcnt(1) +; GFX11-DL-NEXT: v_perm_b32 v1, v1, v1, 0x3020001 +; GFX11-DL-NEXT: s_waitcnt vmcnt(0) +; GFX11-DL-NEXT: v_perm_b32 v0, v0, v0, 0x1000302 +; GFX11-DL-NEXT: s_delay_alu instid0(VALU_DEP_1) +; GFX11-DL-NEXT: v_dot4_u32_u8 v0, v0, v1, 0 +; GFX11-DL-NEXT: global_store_b32 v2, v0, s[0:1] +; GFX11-DL-NEXT: s_nop 0 +; GFX11-DL-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; GFX11-DL-NEXT: s_endpgm + ptr addrspace(1) %src2, + ptr addrspace(1) nocapture %dst) { +entry: + %idx = call i32 @llvm.amdgcn.workitem.id.x() + %gep1 = getelementptr <256 x i8>, ptr addrspace(1) %src1, i32 %idx + %vec1 = load <256 x i8>, ptr addrspace(1) %gep1 + %gep2 = getelementptr <8 x i8>, ptr addrspace(1) %src2, i32 %idx + %vec2 = load <8 x i8>, ptr addrspace(1) %gep2 + + %v1e0 = extractelement <256 x i8> %vec1, i64 255 + %cv1e0 = zext i8 %v1e0 to i32 + %v2e0 = extractelement <8 x i8> %vec2, i64 0 + %cv2e0 = zext i8 %v2e0 to i32 + %mul1 = mul nuw nsw i32 %cv1e0, %cv2e0 + + %v1e1 = extractelement <256 x i8> %vec1, i64 254 + %cv1e1 = zext i8 %v1e1 to i32 + %v2e1 = extractelement <8 x i8> %vec2, i64 1 + %cv2e1 = zext i8 %v2e1 to i32 + %mul2 = mul nuw nsw i32 %cv1e1, %cv2e1 + + %v1e2 = extractelement <256 x i8> %vec1, i64 252 + %cv1e2 = zext i8 %v1e2 to i32 + %v2e2 = extractelement <8 x i8> %vec2, i64 2 + %cv2e2 = zext i8 %v2e2 to i32 + %mul3 = mul nuw nsw i32 %cv1e2, %cv2e2 + + %v1e3 = extractelement <256 x i8> %vec1, i64 253 + %cv1e3 = zext i8 %v1e3 to i32 + %v2e3 = extractelement <8 x i8> %vec2, i64 3 + %cv2e3 = zext i8 %v2e3 to i32 + %mul4 = mul nuw nsw i32 %cv1e3, %cv2e3 + + %add1 = add i32 %mul1, 0 + %add2 = add i32 %add1, %mul2 + %add3 = add i32 %add2, %mul3 + %add4 = add i32 %add3, %mul4 + store i32 %add4, ptr addrspace(1) %dst, align 4 + ret void +} + define amdgpu_kernel void @idot4_acc32_anyext(ptr addrspace(1) %src1, ; GFX7-LABEL: idot4_acc32_anyext: ; GFX7: ; %bb.0: ; %entry diff --git a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll index 47f7943e076a4a0875e90670475537d1c21314da..1ba2491d2210ec231d4904b47225750684443d09 100644 --- a/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll +++ b/llvm/test/CodeGen/AMDGPU/insert_vector_elt.v2i16.ll @@ -2220,14 +2220,12 @@ define amdgpu_kernel void @v_insertelement_v8f16_3(ptr addrspace(1) %out, ptr ad ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] -; VI-NEXT: v_mov_b32_e32 v5, s1 -; VI-NEXT: s_lshl_b32 s1, s4, 16 -; VI-NEXT: s_mov_b32 s2, 0xffff ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 -; VI-NEXT: v_mov_b32_e32 v6, s1 +; VI-NEXT: s_lshl_b32 s0, s4, 16 +; VI-NEXT: v_mov_b32_e32 v5, s1 +; VI-NEXT: v_mov_b32_e32 v6, s0 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_bfi_b32 v3, s2, v3, v3 ; VI-NEXT: v_or_b32_sdwa v1, v1, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: s_endpgm @@ -2302,14 +2300,13 @@ define amdgpu_kernel void @v_insertelement_v8i16_6(ptr addrspace(1) %out, ptr ad ; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v4 ; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; VI-NEXT: flat_load_dwordx4 v[0:3], v[0:1] -; VI-NEXT: s_mov_b32 s2, 0xffff ; VI-NEXT: v_mov_b32_e32 v5, s1 -; VI-NEXT: v_mov_b32_e32 v6, s4 ; VI-NEXT: v_add_u32_e32 v4, vcc, s0, v4 +; VI-NEXT: s_mov_b32 s0, 0xffff +; VI-NEXT: v_mov_b32_e32 v6, s4 ; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_bfi_b32 v3, s2, v6, v3 -; VI-NEXT: v_bfi_b32 v1, s2, v1, v1 +; VI-NEXT: v_bfi_b32 v3, s0, v6, v3 ; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3] ; VI-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll index b4a8193d2377a031ee504026447b77b3621ec4f6..ec3c08ec7952354df9044687774bb90e9c58e389 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.is.fpclass.f16.ll @@ -183,12 +183,10 @@ define i1 @snan_f16(half %x) nounwind { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x1ff +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: snan_f16: @@ -894,11 +892,9 @@ define i1 @not_isnan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c01 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: not_isnan_f16: @@ -1542,10 +1538,8 @@ define i1 @not_issubnormal_or_zero_f16(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v1, v2 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v1, v2 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0 +; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v1, v2 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 @@ -2103,11 +2097,9 @@ define i1 @ispositive_f16(half %x) { ; GFX7GLISEL: ; %bb.0: ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c01 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: ispositive_f16: @@ -2294,13 +2286,12 @@ define i1 @not_isnegative_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c01 ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v2 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v0, v2 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v1 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 +; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v0, v2 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2355,11 +2346,10 @@ define i1 @iszero_or_nan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_nan_f16: @@ -2414,11 +2404,10 @@ define i1 @iszero_or_nan_f_daz(half %x) #0 { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_nan_f_daz: @@ -2473,11 +2462,10 @@ define i1 @iszero_or_nan_f_maybe_daz(half %x) #1 { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8400 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_nan_f_maybe_daz: @@ -2733,11 +2721,10 @@ define i1 @iszero_or_qnan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: v_cmp_ge_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff8200, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0xffff8201 +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: iszero_or_qnan_f16: @@ -2795,13 +2782,11 @@ define i1 @iszero_or_snan_f16(half %x) { ; GFX7GLISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[6:7], v0, v1 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, 0, v0 -; GFX7GLISEL-NEXT: s_and_b64 s[4:5], s[4:5], s[6:7] -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v0 +; GFX7GLISEL-NEXT: v_add_i32_e32 v0, vcc, 0xffff83ff, v0 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x1ff +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; @@ -2875,15 +2860,14 @@ define i1 @not_iszero_or_qnan_f16(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v1, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7c00 ; GFX7GLISEL-NEXT: v_cmp_eq_u32_e64 s[4:5], v1, v2 -; GFX7GLISEL-NEXT: s_or_b64 s[6:7], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e32 vcc, v1, v2 -; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x7e00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e64 s[4:5], v1, v2 -; GFX7GLISEL-NEXT: s_and_b64 s[4:5], vcc, s[4:5] +; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] +; GFX7GLISEL-NEXT: v_add_i32_e32 v1, vcc, 0xffff83ff, v1 +; GFX7GLISEL-NEXT: v_mov_b32_e32 v2, 0x1ff +; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v1, v2 +; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_subrev_i32_e32 v0, vcc, 0x400, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7800 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[4:5] ; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 ; GFX7GLISEL-NEXT: s_or_b64 s[4:5], s[4:5], vcc ; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] @@ -3020,10 +3004,8 @@ define i1 @isinf_or_nan_f16(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_eq_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cmp_ge_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: isinf_or_nan_f16: @@ -3132,10 +3114,8 @@ define i1 @isfinite_or_nan_f(half %x) { ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0x7fff, v0 ; GFX7GLISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 ; GFX7GLISEL-NEXT: v_mov_b32_e32 v1, 0x7c00 -; GFX7GLISEL-NEXT: v_cmp_lt_u32_e32 vcc, v0, v1 -; GFX7GLISEL-NEXT: v_cmp_gt_u32_e64 s[4:5], v0, v1 -; GFX7GLISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5] -; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5] +; GFX7GLISEL-NEXT: v_cmp_ne_u32_e32 vcc, v0, v1 +; GFX7GLISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc ; GFX7GLISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX8CHECK-LABEL: isfinite_or_nan_f: diff --git a/llvm/test/CodeGen/AMDGPU/load-hi16.ll b/llvm/test/CodeGen/AMDGPU/load-hi16.ll index 64c96c8edf5ee9cadc8e1d8276d8dc74f40634be..0c61c58ef061923c5273fa5788547298c60ac2d0 100644 --- a/llvm/test/CodeGen/AMDGPU/load-hi16.ll +++ b/llvm/test/CodeGen/AMDGPU/load-hi16.ll @@ -266,9 +266,9 @@ define <2 x i16> @load_local_hi_v2i16_reglo(ptr addrspace(3) %in, i16 %reg) #0 { ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_mov_b32 m0, -1 ; GFX803-NEXT: ds_read_u16 v0, v0 -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt lgkmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: s_setpc_b64 s[30:31] ; ; GFX900-FLATSCR-LABEL: load_local_hi_v2i16_reglo: @@ -311,9 +311,9 @@ define void @load_local_hi_v2i16_reglo_vreg(ptr addrspace(3) %in, i16 %reg) #0 { ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_mov_b32 m0, -1 ; GFX803-NEXT: ds_read_u16 v0, v0 -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt lgkmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX803-NEXT: v_or_b32_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -696,9 +696,9 @@ define void @load_global_hi_v2i16_reglo_vreg(ptr addrspace(1) %in, i16 %reg) #0 ; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0 ; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc ; GFX803-NEXT: flat_load_ushort v0, v[0:1] -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt vmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v2, v0, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX803-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -1006,9 +1006,9 @@ define void @load_flat_hi_v2i16_reglo_vreg(ptr %in, i16 %reg) #0 { ; GFX803: ; %bb.0: ; %entry ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: flat_load_ushort v0, v[0:1] -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v2, v0, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX803-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -1300,9 +1300,9 @@ define void @load_private_hi_v2i16_reglo_vreg(ptr addrspace(5) byval(i16) %in, i ; GFX803: ; %bb.0: ; %entry ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4094 -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt vmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -1399,8 +1399,8 @@ define void @load_private_hi_v2i16_reglo_vreg_nooff(ptr addrspace(5) byval(i16) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], 0 offset:4094 glc ; GFX803-NEXT: s_waitcnt vmcnt(0) -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 -; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -1851,9 +1851,9 @@ define void @load_constant_hi_v2i16_reglo_vreg(ptr addrspace(4) %in, i16 %reg) # ; GFX803-NEXT: v_add_u32_e32 v0, vcc, 0xfffff002, v0 ; GFX803-NEXT: v_addc_u32_e32 v1, vcc, -1, v1, vcc ; GFX803-NEXT: flat_load_ushort v0, v[0:1] -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt vmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v2, v0, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v0, 16, v0 +; GFX803-NEXT: v_or_b32_sdwa v0, v2, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -2069,9 +2069,9 @@ define void @load_private_hi_v2i16_reglo_vreg_to_offset(i16 %reg, ptr addrspace( ; GFX803-NEXT: buffer_store_dword v2, v1, s[0:3], 0 offen ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: buffer_load_ushort v1, off, s[0:3], s32 offset:4058 -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: s_waitcnt vmcnt(0) -; GFX803-NEXT: v_perm_b32 v0, v0, v1, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v1, 16, v1 +; GFX803-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: flat_store_dword v[0:1], v0 ; GFX803-NEXT: s_waitcnt vmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] @@ -2678,10 +2678,10 @@ define <2 x i16> @load_local_hi_v2i16_store_local_lo(i16 %reg, ptr addrspace(3) ; GFX803-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX803-NEXT: s_mov_b32 m0, -1 ; GFX803-NEXT: ds_read_u16 v2, v1 -; GFX803-NEXT: s_mov_b32 s4, 0x1000504 ; GFX803-NEXT: ds_write_b16 v1, v0 ; GFX803-NEXT: s_waitcnt lgkmcnt(1) -; GFX803-NEXT: v_perm_b32 v2, v0, v2, s4 +; GFX803-NEXT: v_lshlrev_b32_e32 v2, 16, v2 +; GFX803-NEXT: v_or_b32_sdwa v2, v0, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD ; GFX803-NEXT: v_mov_b32_e32 v0, v2 ; GFX803-NEXT: s_waitcnt lgkmcnt(0) ; GFX803-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/AMDGPU/permute.ll b/llvm/test/CodeGen/AMDGPU/permute.ll index 330e5be6d531f717174407912cbfef086a489e70..6cab2b18393070edddaf45aa0ab023c9e9bf101f 100644 --- a/llvm/test/CodeGen/AMDGPU/permute.ll +++ b/llvm/test/CodeGen/AMDGPU/permute.ll @@ -111,19 +111,21 @@ bb: ret void } +; FIXME: produce v_alignbit_b32 v2, v2, s0, 24 instead of v_perm define amdgpu_kernel void @lsh8_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) { ; GCN-LABEL: lsh8_or_lsr24: ; GCN: ; %bb.0: ; %bb ; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24 ; GCN-NEXT: s_load_dword s0, s[0:1], 0x2c ; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0 +; GCN-NEXT: v_mov_b32_e32 v3, 0x2010007 ; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: v_mov_b32_e32 v1, s3 ; GCN-NEXT: v_add_u32_e32 v0, vcc, s2, v0 ; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GCN-NEXT: flat_load_dword v2, v[0:1] ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_alignbit_b32 v2, v2, s0, 24 +; GCN-NEXT: v_perm_b32 v2, s0, v2, v3 ; GCN-NEXT: flat_store_dword v[0:1], v2 ; GCN-NEXT: s_endpgm bb: diff --git a/llvm/test/CodeGen/AMDGPU/permute_i8.ll b/llvm/test/CodeGen/AMDGPU/permute_i8.ll index 5f896f92de0f4241290cf15588822ace353a7af2..8ac332197215f5bca74297cbd91fa5a132ef3083 100644 --- a/llvm/test/CodeGen/AMDGPU/permute_i8.ll +++ b/llvm/test/CodeGen/AMDGPU/permute_i8.ll @@ -3404,3 +3404,499 @@ define hidden void @extractbase(ptr addrspace(1) %in0, ptr addrspace(1) %in1, pt store i32 %res, ptr addrspace(1) %out0, align 4 ret void } + +define hidden void @extract_hilo(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0) { +; GFX10-LABEL: extract_hilo: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dword v6, v[2:3], off +; GFX10-NEXT: global_load_dword v7, v[0:1], off offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_perm_b32 v0, v7, v6, 0x3060505 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_hilo: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v6, v[2:3], off +; GFX9-NEXT: global_load_dword v7, v[0:1], off offset:4 +; GFX9-NEXT: s_mov_b32 s4, 0x3060505 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v0, v7, v6, s4 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec1 = load <8 x i8>, ptr addrspace(1) %in0, align 4 + %vec2 = load <8 x i8>, ptr addrspace(1) %in1, align 4 + %v1e5 = extractelement <8 x i8> %vec1, i64 5 + %zv1e5 = zext i8 %v1e5 to i32 + %byte1 = shl i32 %zv1e5, 8 + + %v1e6 = extractelement <8 x i8> %vec1, i64 6 + %zv1e6 = zext i8 %v1e6 to i32 + %byte2 = shl i32 %zv1e6, 16 + %v2e3 = extractelement <8 x i8> %vec2, i64 3 + %zv2e3 = zext i8 %v2e3 to i32 + %byte3 = shl i32 %zv2e3, 24 + + %tmp0 = or i32 %zv1e5, %byte1 + %tmp1 = or i32 %tmp0, %byte2 + %res = or i32 %tmp1, %byte3 + store i32 %res, ptr addrspace(1) %out0, align 4 + ret void +} + +define hidden void @extract_lohi(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0) { +; GFX10-LABEL: extract_lohi: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dword v6, v[2:3], off offset:4 +; GFX10-NEXT: global_load_dword v7, v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_perm_b32 v0, v7, v6, 0x70404 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_lohi: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v6, v[2:3], off offset:4 +; GFX9-NEXT: global_load_dword v7, v[0:1], off +; GFX9-NEXT: s_mov_b32 s4, 0x70404 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v0, v7, v6, s4 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec1 = load <8 x i8>, ptr addrspace(1) %in0, align 4 + %vec2 = load <8 x i8>, ptr addrspace(1) %in1, align 4 + %v1e0 = extractelement <8 x i8> %vec1, i64 0 + %zv1e0 = zext i8 %v1e0 to i32 + %byte1 = shl i32 %zv1e0, 8 + + %v1e3 = extractelement <8 x i8> %vec1, i64 3 + %zv1e3 = zext i8 %v1e3 to i32 + %byte2 = shl i32 %zv1e3, 16 + %v2e4 = extractelement <8 x i8> %vec2, i64 4 + %zv2e4 = zext i8 %v2e4 to i32 + %byte3 = shl i32 %zv2e4, 24 + + %tmp0 = or i32 %zv1e0, %byte1 + %tmp1 = or i32 %tmp0, %byte2 + %res = or i32 %tmp1, %byte3 + store i32 %res, ptr addrspace(1) %out0, align 4 + ret void +} + +define hidden void @extract_hihi(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0) { +; GFX10-LABEL: extract_hihi: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dword v6, v[2:3], off offset:4 +; GFX10-NEXT: global_load_dword v7, v[0:1], off offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_perm_b32 v0, v7, v6, 0x2070505 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_hihi: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v6, v[2:3], off offset:4 +; GFX9-NEXT: global_load_dword v7, v[0:1], off offset:4 +; GFX9-NEXT: s_mov_b32 s4, 0x2070505 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v0, v7, v6, s4 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec1 = load <8 x i8>, ptr addrspace(1) %in0, align 4 + %vec2 = load <8 x i8>, ptr addrspace(1) %in1, align 4 + %v1e5 = extractelement <8 x i8> %vec1, i64 5 + %zv1e5 = zext i8 %v1e5 to i32 + %byte1 = shl i32 %zv1e5, 8 + + %v1e7 = extractelement <8 x i8> %vec1, i64 7 + %zv1e7 = zext i8 %v1e7 to i32 + %byte2 = shl i32 %zv1e7, 16 + %v2e6 = extractelement <8 x i8> %vec2, i64 6 + %zv2e6 = zext i8 %v2e6 to i32 + %byte3 = shl i32 %zv2e6, 24 + + %tmp0 = or i32 %zv1e5, %byte1 + %tmp1 = or i32 %tmp0, %byte2 + %res = or i32 %tmp1, %byte3 + store i32 %res, ptr addrspace(1) %out0, align 4 + ret void +} + +define hidden void @extract_v8i8(ptr addrspace(1) %in0, ptr addrspace(1) %out0) { +; GFX10-LABEL: extract_v8i8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_perm_b32 v0, v1, v0, 0x1070404 +; GFX10-NEXT: global_store_dword v[2:3], v0, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_v8i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_mov_b32 s4, 0x1070404 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v0, v1, v0, s4 +; GFX9-NEXT: global_store_dword v[2:3], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec1 = load <8 x i8>, ptr addrspace(1) %in0, align 4 + %v1e4 = extractelement <8 x i8> %vec1, i64 4 + %zv1e4 = zext i8 %v1e4 to i32 + %byte1 = shl i32 %zv1e4, 8 + + %v1e7 = extractelement <8 x i8> %vec1, i64 7 + %zv1e7 = zext i8 %v1e7 to i32 + %byte2 = shl i32 %zv1e7, 16 + %v2e1 = extractelement <8 x i8> %vec1, i64 1 + %zv2e1 = zext i8 %v2e1 to i32 + %byte3 = shl i32 %zv2e1, 24 + + %tmp0 = or i32 %zv1e4, %byte1 + %tmp1 = or i32 %tmp0, %byte2 + %res = or i32 %tmp1, %byte3 + store i32 %res, ptr addrspace(1) %out0, align 4 + ret void +} + +define hidden void @extract_v256i8(ptr addrspace(1) %in0, ptr addrspace(1) %out0) { +; GFX10-LABEL: extract_v256i8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dword v0, v[0:1], off offset:252 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_perm_b32 v0, v0, v0, 0x6050707 +; GFX10-NEXT: global_store_dword v[2:3], v0, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_v256i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dword v0, v[0:1], off offset:252 +; GFX9-NEXT: s_mov_b32 s4, 0x6050707 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v0, v0, v0, s4 +; GFX9-NEXT: global_store_dword v[2:3], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec1 = load <256 x i8>, ptr addrspace(1) %in0, align 4 + %v1e4 = extractelement <256 x i8> %vec1, i64 255 + %zv1e4 = zext i8 %v1e4 to i32 + %byte1 = shl i32 %zv1e4, 8 + + %v1e7 = extractelement <256 x i8> %vec1, i64 253 + %zv1e7 = zext i8 %v1e7 to i32 + %byte2 = shl i32 %zv1e7, 16 + %v2e1 = extractelement <256 x i8> %vec1, i64 254 + %zv2e1 = zext i8 %v2e1 to i32 + %byte3 = shl i32 %zv2e1, 24 + + %tmp0 = or i32 %zv1e4, %byte1 + %tmp1 = or i32 %tmp0, %byte2 + %res = or i32 %tmp1, %byte3 + store i32 %res, ptr addrspace(1) %out0, align 4 + ret void +} + +; TODO : support this pattern +define hidden void @extract_3src(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0) { +; GFX10-LABEL: extract_3src: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX10-NEXT: global_load_dword v8, v[2:3], off offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_lshlrev_b32_e32 v0, 8, v7 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_lshlrev_b32_e32 v1, 8, v8 +; GFX10-NEXT: v_and_b32_e32 v2, 0xff, v6 +; GFX10-NEXT: v_and_b32_e32 v0, 0xff0000, v0 +; GFX10-NEXT: v_and_b32_e32 v1, 0xff000000, v1 +; GFX10-NEXT: v_lshl_or_b32 v2, v2, 8, v2 +; GFX10-NEXT: v_or3_b32 v0, v2, v0, v1 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_3src: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx2 v[6:7], v[0:1], off +; GFX9-NEXT: global_load_dword v8, v[2:3], off offset:4 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_and_b32_e32 v0, 0xff, v6 +; GFX9-NEXT: v_lshlrev_b32_e32 v1, 8, v7 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshlrev_b32_e32 v2, 8, v8 +; GFX9-NEXT: v_and_b32_e32 v1, 0xff0000, v1 +; GFX9-NEXT: v_and_b32_e32 v2, 0xff000000, v2 +; GFX9-NEXT: v_lshl_or_b32 v0, v0, 8, v0 +; GFX9-NEXT: v_or3_b32 v0, v0, v1, v2 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec1 = load <8 x i8>, ptr addrspace(1) %in0, align 4 + %vec2 = load <8 x i8>, ptr addrspace(1) %in1, align 4 + %v1e0 = extractelement <8 x i8> %vec1, i64 0 + %zv1e0 = zext i8 %v1e0 to i32 + %byte1 = shl i32 %zv1e0, 8 + + %v1e5 = extractelement <8 x i8> %vec1, i64 5 + %zv1e5 = zext i8 %v1e5 to i32 + %byte2 = shl i32 %zv1e5, 16 + %v2e6 = extractelement <8 x i8> %vec2, i64 6 + %zv2e6 = zext i8 %v2e6 to i32 + %byte3 = shl i32 %zv2e6, 24 + + %tmp0 = or i32 %zv1e0, %byte1 + %tmp1 = or i32 %tmp0, %byte2 + %res = or i32 %tmp1, %byte3 + store i32 %res, ptr addrspace(1) %out0, align 4 + ret void +} + +; Should not result in crash +define hidden void @extract_v6i16(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0, ptr addrspace(1) %out1) { +; GFX10-LABEL: extract_v6i16: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_clause 0x3 +; GFX10-NEXT: global_load_ushort v2, v[0:1], off offset:6 +; GFX10-NEXT: global_load_ushort v3, v[0:1], off +; GFX10-NEXT: global_load_ushort v8, v[0:1], off offset:2 +; GFX10-NEXT: global_load_ushort v9, v[0:1], off offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_lshl_or_b32 v0, v8, 16, v3 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_lshl_or_b32 v1, v2, 16, v9 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: global_store_dword v[6:7], v1, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_v6i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v2, v[0:1], off offset:6 +; GFX9-NEXT: global_load_ushort v3, v[0:1], off +; GFX9-NEXT: global_load_ushort v8, v[0:1], off offset:4 +; GFX9-NEXT: global_load_ushort v9, v[0:1], off offset:2 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_lshl_or_b32 v0, v2, 16, v8 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_lshl_or_b32 v1, v9, 16, v3 +; GFX9-NEXT: global_store_dword v[4:5], v1, off +; GFX9-NEXT: global_store_dword v[6:7], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec = load <6 x i16>, ptr addrspace(1) %in0, align 2 + %el0 = extractelement <6 x i16> %vec, i32 0 + %el1 = extractelement <6 x i16> %vec, i32 1 + %el2 = extractelement <6 x i16> %vec, i32 2 + %el3 = extractelement <6 x i16> %vec, i32 3 + %z0 = zext i16 %el0 to i32 + %z1 = zext i16 %el1 to i32 + %s1 = shl nuw i32 %z1, 16 + %o0 = or i32 %s1, %z0 + %z2 = zext i16 %el2 to i32 + %z3 = zext i16 %el3 to i32 + %s3 = shl nuw i32 %z3, 16 + %o1 = or i32 %z2, %s3 + + store i32 %o0, ptr addrspace(1) %out0, align 4 + store i32 %o1, ptr addrspace(1) %out1, align 4 + ret void +} + + +; Should not result in crash +define hidden void @extract_v7i16(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0, ptr addrspace(1) %out1) { +; GFX10-LABEL: extract_v7i16: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: global_store_dword v[6:7], v1, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_v7i16: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx2 v[0:1], v[0:1], off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: global_store_dword v[6:7], v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec = load <7 x i16>, ptr addrspace(1) %in0, align 2 + %el0 = extractelement <7 x i16> %vec, i32 0 + %el1 = extractelement <7 x i16> %vec, i32 1 + %el2 = extractelement <7 x i16> %vec, i32 2 + %el3 = extractelement <7 x i16> %vec, i32 3 + %z0 = zext i16 %el0 to i32 + %z1 = zext i16 %el1 to i32 + %s1 = shl nuw i32 %z1, 16 + %o0 = or i32 %s1, %z0 + %z2 = zext i16 %el2 to i32 + %z3 = zext i16 %el3 to i32 + %s3 = shl nuw i32 %z3, 16 + %o1 = or i32 %z2, %s3 + + store i32 %o0, ptr addrspace(1) %out0, align 4 + store i32 %o1, ptr addrspace(1) %out1, align 4 + ret void +} + +; Should not result in crash +define hidden void @extract_v13i8(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0, ptr addrspace(1) %out1) { +; GFX10-LABEL: extract_v13i8: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX10-NEXT: global_load_ushort v8, v[0:1], off offset:8 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_bfe_u32 v0, v2, 8, 8 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_and_b32_e32 v1, 0xff, v8 +; GFX10-NEXT: v_perm_b32 v0, v0, v2, 0x5040c00 +; GFX10-NEXT: v_perm_b32 v1, v1, v3, 0x5040c03 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: global_store_dword v[6:7], v1, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_v13i8: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx2 v[2:3], v[0:1], off +; GFX9-NEXT: global_load_ushort v8, v[0:1], off offset:8 +; GFX9-NEXT: s_mov_b32 s4, 0x5040c00 +; GFX9-NEXT: s_mov_b32 s5, 0x5040c03 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_bfe_u32 v0, v2, 8, 8 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_and_b32_e32 v1, 0xff, v8 +; GFX9-NEXT: v_perm_b32 v0, v0, v2, s4 +; GFX9-NEXT: v_perm_b32 v1, v1, v3, s5 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: global_store_dword v[6:7], v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec = load <13 x i8>, ptr addrspace(1) %in0, align 2 + %el0 = extractelement <13 x i8> %vec, i32 0 + %el1 = extractelement <13 x i8> %vec, i32 1 + %el2 = extractelement <13 x i8> %vec, i32 7 + %el3 = extractelement <13 x i8> %vec, i32 8 + %z0 = zext i8 %el0 to i32 + %z1 = zext i8 %el1 to i32 + %s1 = shl nuw i32 %z1, 16 + %o0 = or i32 %s1, %z0 + %z2 = zext i8 %el2 to i32 + %z3 = zext i8 %el3 to i32 + %s3 = shl nuw i32 %z3, 16 + %o1 = or i32 %z2, %s3 + + store i32 %o0, ptr addrspace(1) %out0, align 4 + store i32 %o1, ptr addrspace(1) %out1, align 4 + ret void +} + +; Should not result in crash +define hidden void @extract_v13i64(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0, ptr addrspace(1) %out1) { +; GFX10-LABEL: extract_v13i64: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_dwordx4 v[8:11], v[0:1], off +; GFX10-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16 +; GFX10-NEXT: s_waitcnt vmcnt(1) +; GFX10-NEXT: v_perm_b32 v0, v9, v8, 0x3020504 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: v_perm_b32 v1, v11, v12, 0x1000706 +; GFX10-NEXT: global_store_dword v[4:5], v0, off +; GFX10-NEXT: global_store_dword v[6:7], v1, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: extract_v13i64: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_dwordx4 v[8:11], v[0:1], off +; GFX9-NEXT: global_load_dwordx4 v[12:15], v[0:1], off offset:16 +; GFX9-NEXT: s_mov_b32 s4, 0x3020504 +; GFX9-NEXT: s_mov_b32 s5, 0x1000706 +; GFX9-NEXT: s_waitcnt vmcnt(1) +; GFX9-NEXT: v_perm_b32 v0, v9, v8, s4 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v1, v11, v12, s5 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: global_store_dword v[6:7], v1, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec = load <13 x i64>, ptr addrspace(1) %in0, align 2 + %el0 = extractelement <13 x i64> %vec, i32 0 + %el1 = extractelement <13 x i64> %vec, i32 1 + %el2 = extractelement <13 x i64> %vec, i32 7 + %el3 = extractelement <13 x i64> %vec, i32 8 + %el00 = lshr i64 %el0, 32 + %t0 = trunc i64 %el00 to i16 + %z0 = zext i16 %t0 to i32 + %z1 = trunc i64 %el1 to i32 + %s1 = shl nuw i32 %z1, 16 + %o0 = or i32 %s1, %z0 + %t2 = trunc i64 %el2 to i16 + %z2 = zext i16 %t2 to i32 + %z3 = trunc i64 %el3 to i32 + %s3 = shl nuw i32 %z3, 16 + %o1 = or i32 %z2, %s3 + + store i32 %o0, ptr addrspace(1) %out0, align 4 + store i32 %o1, ptr addrspace(1) %out1, align 4 + ret void +} + + +; Should combine the lower 16 bits from each i32 in load +define hidden void @trunc_vector(ptr addrspace(1) %in0, ptr addrspace(1) %in1, ptr addrspace(1) %out0) { +; GFX10-LABEL: trunc_vector: +; GFX10: ; %bb.0: +; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX10-NEXT: s_clause 0x1 +; GFX10-NEXT: global_load_ushort v2, v[0:1], off +; GFX10-NEXT: global_load_short_d16_hi v2, v[0:1], off offset:4 +; GFX10-NEXT: s_waitcnt vmcnt(0) +; GFX10-NEXT: global_store_dword v[4:5], v2, off +; GFX10-NEXT: s_setpc_b64 s[30:31] +; +; GFX9-LABEL: trunc_vector: +; GFX9: ; %bb.0: +; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9-NEXT: global_load_ushort v2, v[0:1], off +; GFX9-NEXT: global_load_ushort v3, v[0:1], off offset:4 +; GFX9-NEXT: s_mov_b32 s4, 0x5040100 +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: v_perm_b32 v0, v3, v2, s4 +; GFX9-NEXT: global_store_dword v[4:5], v0, off +; GFX9-NEXT: s_waitcnt vmcnt(0) +; GFX9-NEXT: s_setpc_b64 s[30:31] + %vec = load <2 x i32>, ptr addrspace(1) %in0, align 2 + %tvec = trunc <2 x i32> %vec to <2 x i16> + %el0 = extractelement <2 x i16> %tvec, i32 0 + %el1 = extractelement <2 x i16> %tvec, i32 1 + %z0 = zext i16 %el0 to i32 + %z1 = zext i16 %el1 to i32 + %s1 = shl nuw i32 %z1, 16 + %o0 = or i32 %s1, %z0 + + store i32 %o0, ptr addrspace(1) %out0, align 4 + ret void +} diff --git a/llvm/test/CodeGen/AMDGPU/sdiv64.ll b/llvm/test/CodeGen/AMDGPU/sdiv64.ll index f37d681ab965ed6c20ae4f623d47af21f5a43e03..b086640c72f80471c3c1fdf06ea11ae106087253 100644 --- a/llvm/test/CodeGen/AMDGPU/sdiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/sdiv64.ll @@ -529,17 +529,26 @@ define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { ; GCN: ; %bb.0: ; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-NEXT: v_lshrrev_b32_e32 v0, 8, v3 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, v0 +; GCN-NEXT: v_sub_i32_e32 v3, vcc, 0, v0 ; GCN-NEXT: v_lshrrev_b32_e32 v1, 8, v1 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_i32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-NEXT: v_mul_lo_u32 v3, v3, v2 +; GCN-NEXT: v_mul_hi_u32 v3, v2, v3 +; GCN-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-NEXT: v_mul_hi_u32 v2, v1, v2 +; GCN-NEXT: v_mul_u32_u24_e32 v3, v2, v0 +; GCN-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GCN-NEXT: v_add_i32_e32 v3, vcc, 1, v2 +; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-NEXT: s_setpc_b64 s[30:31] ; @@ -547,17 +556,26 @@ define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GCN-IR-NEXT: v_lshrrev_b32_e32 v0, 8, v3 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, v0 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, v0 +; GCN-IR-NEXT: v_sub_i32_e32 v3, vcc, 0, v0 ; GCN-IR-NEXT: v_lshrrev_b32_e32 v1, 8, v1 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, v1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, |v0| -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v2, 0x4f7ffffe, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_lo_u32 v3, v3, v2 +; GCN-IR-NEXT: v_mul_hi_u32 v3, v2, v3 +; GCN-IR-NEXT: v_add_i32_e32 v2, vcc, v2, v3 +; GCN-IR-NEXT: v_mul_hi_u32 v2, v1, v2 +; GCN-IR-NEXT: v_mul_u32_u24_e32 v3, v2, v0 +; GCN-IR-NEXT: v_add_i32_e32 v4, vcc, 1, v2 +; GCN-IR-NEXT: v_sub_i32_e32 v1, vcc, v1, v3 +; GCN-IR-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc +; GCN-IR-NEXT: v_sub_i32_e64 v3, s[4:5], v1, v0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc +; GCN-IR-NEXT: v_add_i32_e32 v3, vcc, 1, v2 +; GCN-IR-NEXT: v_cmp_ge_u32_e32 vcc, v1, v0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc ; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 ; GCN-IR-NEXT: s_setpc_b64 s[30:31] %1 = lshr i64 %x, 40 @@ -569,55 +587,91 @@ define i64 @v_test_sdiv24_64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv32_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: s_xor_b32 s0, s3, s8 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s8 +; GCN-NEXT: s_xor_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: s_or_b32 s2, s0, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[0:1], s[0:1], exec -; GCN-NEXT: s_cselect_b32 s0, s2, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s0, v2 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-NEXT: s_add_i32 s3, s3, s2 +; GCN-NEXT: s_xor_b32 s3, s3, s2 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s0, s2, s8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_mul_i32 s2, s1, s9 +; GCN-NEXT: s_sub_i32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s8, s1, 1 +; GCN-NEXT: s_sub_i32 s3, s2, s9 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s3, s1, 1 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-NEXT: s_xor_b32 s1, s1, s0 +; GCN-NEXT: s_sub_i32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv32_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: s_xor_b32 s0, s3, s8 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_ashr_i32 s0, s0, 30 +; GCN-IR-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s8 +; GCN-IR-NEXT: s_xor_b32 s9, s2, s8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: s_or_b32 s2, s0, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[0:1], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[0:1], s[0:1], exec -; GCN-IR-NEXT: s_cselect_b32 s0, s2, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s0, v2 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-IR-NEXT: s_add_i32 s3, s3, s2 +; GCN-IR-NEXT: s_xor_b32 s3, s3, s2 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s0, s2, s8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-IR-NEXT: s_mul_i32 s2, s1, s9 +; GCN-IR-NEXT: s_sub_i32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s8, s1, 1 +; GCN-IR-NEXT: s_sub_i32 s3, s2, s9 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-IR-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s3, s1, 1 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-IR-NEXT: s_xor_b32 s1, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s0, s1, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 32 @@ -630,62 +684,96 @@ define amdgpu_kernel void @s_test_sdiv32_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_sdiv31_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv31_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s4, s4, s8 -; GCN-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-NEXT: s_or_b32 s6, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 31 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s8 +; GCN-NEXT: s_xor_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s0, s3, s8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_mul_i32 s3, s1, s9 +; GCN-NEXT: s_sub_i32 s2, s2, s3 +; GCN-NEXT: s_add_i32 s8, s1, 1 +; GCN-NEXT: s_sub_i32 s3, s2, s9 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s3, s1, 1 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-NEXT: s_xor_b32 s1, s1, s0 +; GCN-NEXT: s_sub_i32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv31_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-IR-NEXT: s_or_b32 s6, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 31 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s8 +; GCN-IR-NEXT: s_xor_b32 s9, s2, s8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s0, s3, s8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-IR-NEXT: s_mul_i32 s3, s1, s9 +; GCN-IR-NEXT: s_sub_i32 s2, s2, s3 +; GCN-IR-NEXT: s_add_i32 s8, s1, 1 +; GCN-IR-NEXT: s_sub_i32 s3, s2, s9 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-IR-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s3, s1, 1 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-IR-NEXT: s_xor_b32 s1, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s0, s1, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 33 %2 = ashr i64 %y, 33 @@ -764,62 +852,96 @@ define amdgpu_kernel void @s_test_sdiv23_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_sdiv25_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_sdiv25_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s4, s4, s8 -; GCN-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-NEXT: s_or_b32 s6, s4, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-NEXT: v_bfe_i32 v0, v0, 0, 25 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s8 +; GCN-NEXT: s_xor_b32 s9, s2, s8 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s9 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s0, s3, s8 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-NEXT: s_mul_i32 s3, s1, s9 +; GCN-NEXT: s_sub_i32 s2, s2, s3 +; GCN-NEXT: s_add_i32 s8, s1, 1 +; GCN-NEXT: s_sub_i32 s3, s2, s9 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-NEXT: s_add_i32 s3, s1, 1 +; GCN-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-NEXT: s_xor_b32 s1, s1, s0 +; GCN-NEXT: s_sub_i32 s0, s1, s0 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_sdiv25_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s4, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s4, s4, 30 -; GCN-IR-NEXT: s_or_b32 s6, s4, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-IR-NEXT: s_cselect_b32 s4, s6, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s4, v2 -; GCN-IR-NEXT: v_bfe_i32 v0, v0, 0, 25 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s8, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s8 +; GCN-IR-NEXT: s_xor_b32 s9, s2, s8 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s9 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s9 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s0, s3, s8 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s1, v0 +; GCN-IR-NEXT: s_mul_i32 s3, s1, s9 +; GCN-IR-NEXT: s_sub_i32 s2, s2, s3 +; GCN-IR-NEXT: s_add_i32 s8, s1, 1 +; GCN-IR-NEXT: s_sub_i32 s3, s2, s9 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s8, s1 +; GCN-IR-NEXT: s_cselect_b32 s2, s3, s2 +; GCN-IR-NEXT: s_add_i32 s3, s1, 1 +; GCN-IR-NEXT: s_cmp_ge_u32 s2, s9 +; GCN-IR-NEXT: s_cselect_b32 s1, s3, s1 +; GCN-IR-NEXT: s_xor_b32 s1, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s0, s1, s0 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 39 %2 = ashr i64 %y, 39 diff --git a/llvm/test/CodeGen/AMDGPU/srem64.ll b/llvm/test/CodeGen/AMDGPU/srem64.ll index e10be23a71770d53a1b8337b1a098668a6236359..ed7f27b367fdaff4d39a24c7a03d3d792f29a2f4 100644 --- a/llvm/test/CodeGen/AMDGPU/srem64.ll +++ b/llvm/test/CodeGen/AMDGPU/srem64.ll @@ -650,72 +650,90 @@ define i64 @v_test_srem24_64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem25_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s5, s4, s8 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-NEXT: s_add_i32 s5, s6, s5 -; GCN-NEXT: s_mul_i32 s5, s5, s8 -; GCN-NEXT: s_sub_i32 s4, s4, s5 -; GCN-NEXT: s_bfe_i32 s4, s4, 0x190000 -; GCN-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s8, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s3 +; GCN-NEXT: s_sub_i32 s0, s0, s3 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem25_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 39 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-IR-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-IR-NEXT: s_add_i32 s5, s6, s5 -; GCN-IR-NEXT: s_mul_i32 s5, s5, s8 -; GCN-IR-NEXT: s_sub_i32 s4, s4, s5 -; GCN-IR-NEXT: s_bfe_i32 s4, s4, 0x190000 -; GCN-IR-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s8, s2, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 39 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_xor_b32 s0, s0, s3 +; GCN-IR-NEXT: s_sub_i32 s0, s0, s3 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 39 %2 = ashr i64 %y, 39 @@ -727,72 +745,90 @@ define amdgpu_kernel void @s_test_srem25_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem31_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: s_mov_b32 s2, -1 +; GCN-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s0, s4 -; GCN-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: s_mov_b32 s1, s5 -; GCN-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_xor_b32 s5, s4, s8 -; GCN-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-NEXT: s_or_b32 s5, s5, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-NEXT: s_add_i32 s5, s6, s5 -; GCN-NEXT: s_mul_i32 s5, s5, s8 -; GCN-NEXT: s_sub_i32 s4, s4, s5 -; GCN-NEXT: s_bfe_i32 s4, s4, 0x1f0000 -; GCN-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-NEXT: v_mov_b32_e32 v0, s4 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s8, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: s_mov_b32 s5, s1 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_xor_b32 s2, s2, s3 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s3 +; GCN-NEXT: s_sub_i32 s0, s0, s3 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem31_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; GCN-IR-NEXT: s_load_dword s1, s[0:1], 0xe -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: s_mov_b32 s2, -1 +; GCN-IR-NEXT: s_load_dword s3, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s0, s4 -; GCN-IR-NEXT: s_ashr_i64 s[8:9], s[0:1], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: s_mov_b32 s1, s5 -; GCN-IR-NEXT: s_ashr_i64 s[4:5], s[6:7], 33 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s4 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_xor_b32 s5, s4, s8 -; GCN-IR-NEXT: s_ashr_i32 s5, s5, 30 -; GCN-IR-NEXT: s_or_b32 s5, s5, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[6:7], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[6:7], s[6:7], exec -; GCN-IR-NEXT: s_cselect_b32 s5, s5, 0 -; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 -; GCN-IR-NEXT: s_add_i32 s5, s6, s5 -; GCN-IR-NEXT: s_mul_i32 s5, s5, s8 -; GCN-IR-NEXT: s_sub_i32 s4, s4, s5 -; GCN-IR-NEXT: s_bfe_i32 s4, s4, 0x1f0000 -; GCN-IR-NEXT: s_ashr_i32 s5, s4, 31 -; GCN-IR-NEXT: v_mov_b32_e32 v0, s4 -; GCN-IR-NEXT: v_mov_b32_e32 v1, s5 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s8, s2, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i64 s[2:3], s[2:3], 33 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_xor_b32 s2, s2, s3 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_xor_b32 s0, s0, s3 +; GCN-IR-NEXT: s_sub_i32 s0, s0, s3 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 33 %2 = ashr i64 %y, 33 @@ -805,59 +841,85 @@ define amdgpu_kernel void @s_test_srem31_64(ptr addrspace(1) %out, i64 %x, i64 % define amdgpu_kernel void @s_test_srem32_64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_srem32_64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-NEXT: s_xor_b32 s2, s3, s8 -; GCN-NEXT: s_ashr_i32 s2, s2, 30 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: s_or_b32 s2, s2, 1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-NEXT: s_cselect_b32 s2, s2, 0 -; GCN-NEXT: v_add_i32_e32 v0, vcc, s2, v2 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-NEXT: s_add_i32 s2, s2, s3 +; GCN-NEXT: s_xor_b32 s8, s2, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s3, v0 -; GCN-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-NEXT: s_add_i32 s3, s3, s2 +; GCN-NEXT: s_xor_b32 s3, s3, s2 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s3, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_xor_b32 s0, s0, s2 +; GCN-NEXT: s_sub_i32 s0, s0, s2 +; GCN-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: v_mov_b32_e32 v1, s1 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_srem32_64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v0, s8 -; GCN-IR-NEXT: v_cvt_f32_i32_e32 v1, s3 -; GCN-IR-NEXT: s_xor_b32 s2, s3, s8 -; GCN-IR-NEXT: s_ashr_i32 s2, s2, 30 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: s_or_b32 s2, s2, 1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cvt_i32_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 s[4:5], |v1|, |v0| -; GCN-IR-NEXT: s_and_b64 s[4:5], s[4:5], exec -; GCN-IR-NEXT: s_cselect_b32 s2, s2, 0 -; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, s2, v2 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s8 +; GCN-IR-NEXT: s_ashr_i32 s3, s2, 31 +; GCN-IR-NEXT: s_add_i32 s2, s2, s3 +; GCN-IR-NEXT: s_xor_b32 s8, s2, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 ; GCN-IR-NEXT: s_mov_b32 s4, s0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s3, v0 -; GCN-IR-NEXT: v_ashrrev_i32_e32 v1, 31, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_ashr_i32 s2, s3, 31 +; GCN-IR-NEXT: s_add_i32 s3, s3, s2 +; GCN-IR-NEXT: s_xor_b32 s3, s3, s2 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s3, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_xor_b32 s0, s0, s2 +; GCN-IR-NEXT: s_sub_i32 s0, s0, s2 +; GCN-IR-NEXT: s_ashr_i32 s1, s0, 31 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v1, s1 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = ashr i64 %x, 32 diff --git a/llvm/test/CodeGen/AMDGPU/udiv.ll b/llvm/test/CodeGen/AMDGPU/udiv.ll index fbfaf3cff080680ac3943fcf733cc4184422ef53..f686aad0cefc25b5e4b80a0ea18859206b55581c 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv.ll @@ -1848,96 +1848,76 @@ define amdgpu_kernel void @v_udiv_i23(ptr addrspace(1) %out, ptr addrspace(1) %i define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %in) { ; SI-LABEL: v_udiv_i24: ; SI: ; %bb.0: -; SI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9 -; SI-NEXT: s_mov_b32 s3, 0xf000 -; SI-NEXT: s_mov_b32 s2, -1 -; SI-NEXT: s_mov_b32 s10, s2 -; SI-NEXT: s_mov_b32 s11, s3 +; SI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; SI-NEXT: s_mov_b32 s7, 0xf000 +; SI-NEXT: s_mov_b32 s6, -1 +; SI-NEXT: s_mov_b32 s10, s6 +; SI-NEXT: s_mov_b32 s11, s7 ; SI-NEXT: s_waitcnt lgkmcnt(0) -; SI-NEXT: s_mov_b32 s8, s6 -; SI-NEXT: s_mov_b32 s9, s7 +; SI-NEXT: s_mov_b32 s8, s2 +; SI-NEXT: s_mov_b32 s9, s3 ; SI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6 ; SI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4 ; SI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2 ; SI-NEXT: buffer_load_ushort v3, off, s[8:11], 0 -; SI-NEXT: s_mov_b32 s0, s4 -; SI-NEXT: s_mov_b32 s1, s5 +; SI-NEXT: s_mov_b32 s4, s0 +; SI-NEXT: s_mov_b32 s5, s1 ; SI-NEXT: s_waitcnt vmcnt(3) ; SI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; SI-NEXT: s_waitcnt vmcnt(2) ; SI-NEXT: v_or_b32_e32 v0, v1, v0 -; SI-NEXT: v_cvt_f32_u32_e32 v1, v0 -; SI-NEXT: v_sub_i32_e32 v4, vcc, 0, v0 +; SI-NEXT: v_cvt_f32_u32_e32 v0, v0 ; SI-NEXT: s_waitcnt vmcnt(1) -; SI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; SI-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; SI-NEXT: s_waitcnt vmcnt(0) -; SI-NEXT: v_or_b32_e32 v2, v3, v2 -; SI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; SI-NEXT: v_cvt_u32_f32_e32 v1, v1 -; SI-NEXT: v_mul_lo_u32 v4, v4, v1 -; SI-NEXT: v_mul_hi_u32 v4, v1, v4 -; SI-NEXT: v_add_i32_e32 v1, vcc, v1, v4 -; SI-NEXT: v_mul_hi_u32 v1, v2, v1 -; SI-NEXT: v_mul_lo_u32 v3, v1, v0 -; SI-NEXT: v_add_i32_e32 v4, vcc, 1, v1 -; SI-NEXT: v_sub_i32_e32 v2, vcc, v2, v3 -; SI-NEXT: v_sub_i32_e32 v3, vcc, v2, v0 -; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; SI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; SI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; SI-NEXT: v_add_i32_e32 v3, vcc, 1, v1 -; SI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; SI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; SI-NEXT: v_or_b32_e32 v1, v3, v1 +; SI-NEXT: v_cvt_f32_u32_e32 v1, v1 +; SI-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; SI-NEXT: v_mul_f32_e32 v2, v1, v2 +; SI-NEXT: v_trunc_f32_e32 v2, v2 +; SI-NEXT: v_cvt_u32_f32_e32 v3, v2 +; SI-NEXT: v_mad_f32 v1, -v2, v0, v1 +; SI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; SI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; SI-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; SI-NEXT: s_endpgm ; ; VI-LABEL: v_udiv_i24: ; VI: ; %bb.0: -; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24 -; VI-NEXT: s_mov_b32 s3, 0xf000 -; VI-NEXT: s_mov_b32 s2, -1 -; VI-NEXT: s_mov_b32 s10, s2 -; VI-NEXT: s_mov_b32 s11, s3 +; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24 +; VI-NEXT: s_mov_b32 s7, 0xf000 +; VI-NEXT: s_mov_b32 s6, -1 +; VI-NEXT: s_mov_b32 s10, s6 +; VI-NEXT: s_mov_b32 s11, s7 ; VI-NEXT: s_waitcnt lgkmcnt(0) -; VI-NEXT: s_mov_b32 s8, s6 -; VI-NEXT: s_mov_b32 s9, s7 +; VI-NEXT: s_mov_b32 s8, s2 +; VI-NEXT: s_mov_b32 s9, s3 ; VI-NEXT: buffer_load_ubyte v0, off, s[8:11], 0 offset:6 ; VI-NEXT: buffer_load_ushort v1, off, s[8:11], 0 offset:4 ; VI-NEXT: buffer_load_ubyte v2, off, s[8:11], 0 offset:2 ; VI-NEXT: buffer_load_ushort v3, off, s[8:11], 0 -; VI-NEXT: s_mov_b32 s0, s4 -; VI-NEXT: s_mov_b32 s1, s5 +; VI-NEXT: s_mov_b32 s4, s0 +; VI-NEXT: s_mov_b32 s5, s1 ; VI-NEXT: s_waitcnt vmcnt(3) ; VI-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; VI-NEXT: s_waitcnt vmcnt(2) ; VI-NEXT: v_or_b32_e32 v0, v1, v0 -; VI-NEXT: v_cvt_f32_u32_e32 v1, v0 -; VI-NEXT: v_sub_u32_e32 v4, vcc, 0, v0 +; VI-NEXT: v_cvt_f32_u32_e32 v0, v0 ; VI-NEXT: s_waitcnt vmcnt(1) -; VI-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; VI-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; VI-NEXT: v_lshlrev_b32_e32 v1, 16, v2 ; VI-NEXT: s_waitcnt vmcnt(0) -; VI-NEXT: v_or_b32_e32 v2, v3, v2 -; VI-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; VI-NEXT: v_cvt_u32_f32_e32 v1, v1 -; VI-NEXT: v_mul_lo_u32 v4, v4, v1 -; VI-NEXT: v_mul_hi_u32 v4, v1, v4 -; VI-NEXT: v_add_u32_e32 v1, vcc, v1, v4 -; VI-NEXT: v_mul_hi_u32 v1, v2, v1 -; VI-NEXT: v_mul_lo_u32 v3, v1, v0 -; VI-NEXT: v_add_u32_e32 v4, vcc, 1, v1 -; VI-NEXT: v_sub_u32_e32 v2, vcc, v2, v3 -; VI-NEXT: v_sub_u32_e32 v3, vcc, v2, v0 -; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; VI-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc -; VI-NEXT: v_cndmask_b32_e32 v2, v2, v3, vcc -; VI-NEXT: v_add_u32_e32 v3, vcc, 1, v1 -; VI-NEXT: v_cmp_ge_u32_e32 vcc, v2, v0 -; VI-NEXT: v_cndmask_b32_e32 v0, v1, v3, vcc +; VI-NEXT: v_or_b32_e32 v1, v3, v1 +; VI-NEXT: v_cvt_f32_u32_e32 v1, v1 +; VI-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; VI-NEXT: v_mul_f32_e32 v2, v1, v2 +; VI-NEXT: v_trunc_f32_e32 v2, v2 +; VI-NEXT: v_cvt_u32_f32_e32 v3, v2 +; VI-NEXT: v_mad_f32 v1, -v2, v0, v1 +; VI-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; VI-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; VI-NEXT: v_and_b32_e32 v0, 0xffffff, v0 -; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0 +; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0 ; VI-NEXT: s_endpgm ; ; GCN-LABEL: v_udiv_i24: @@ -1947,50 +1927,40 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i ; GCN-NEXT: s_add_u32 s4, s2, 4 ; GCN-NEXT: s_addc_u32 s5, s3, 0 ; GCN-NEXT: s_add_u32 s6, s2, 2 -; GCN-NEXT: v_mov_b32_e32 v0, s4 ; GCN-NEXT: s_addc_u32 s7, s3, 0 -; GCN-NEXT: v_mov_b32_e32 v1, s5 -; GCN-NEXT: s_add_u32 s4, s2, 6 -; GCN-NEXT: s_addc_u32 s5, s3, 0 -; GCN-NEXT: v_mov_b32_e32 v2, s4 -; GCN-NEXT: v_mov_b32_e32 v3, s5 -; GCN-NEXT: flat_load_ubyte v4, v[2:3] -; GCN-NEXT: flat_load_ushort v5, v[0:1] +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, s7 +; GCN-NEXT: s_add_u32 s6, s2, 6 +; GCN-NEXT: s_addc_u32 s7, s3, 0 ; GCN-NEXT: v_mov_b32_e32 v2, s6 -; GCN-NEXT: v_mov_b32_e32 v0, s2 ; GCN-NEXT: v_mov_b32_e32 v3, s7 -; GCN-NEXT: v_mov_b32_e32 v1, s3 -; GCN-NEXT: flat_load_ubyte v2, v[2:3] -; GCN-NEXT: flat_load_ushort v0, v[0:1] +; GCN-NEXT: v_mov_b32_e32 v4, s4 +; GCN-NEXT: v_mov_b32_e32 v5, s5 +; GCN-NEXT: flat_load_ubyte v6, v[2:3] +; GCN-NEXT: flat_load_ushort v4, v[4:5] +; GCN-NEXT: v_mov_b32_e32 v2, s2 +; GCN-NEXT: v_mov_b32_e32 v3, s3 +; GCN-NEXT: flat_load_ubyte v0, v[0:1] +; GCN-NEXT: flat_load_ushort v1, v[2:3] ; GCN-NEXT: s_waitcnt vmcnt(3) -; GCN-NEXT: v_lshlrev_b32_e32 v1, 16, v4 +; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v6 ; GCN-NEXT: s_waitcnt vmcnt(2) -; GCN-NEXT: v_or_b32_e32 v3, v5, v1 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, v3 -; GCN-NEXT: v_sub_u32_e32 v4, vcc, 0, v3 +; GCN-NEXT: v_or_b32_e32 v2, v4, v2 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, v2 ; GCN-NEXT: s_waitcnt vmcnt(1) -; GCN-NEXT: v_lshlrev_b32_e32 v2, 16, v2 -; GCN-NEXT: v_rcp_iflag_f32_e32 v1, v1 +; GCN-NEXT: v_lshlrev_b32_e32 v0, 16, v0 ; GCN-NEXT: s_waitcnt vmcnt(0) -; GCN-NEXT: v_or_b32_e32 v2, v0, v2 -; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GCN-NEXT: v_mul_lo_u32 v4, v4, v1 -; GCN-NEXT: v_mul_hi_u32 v4, v1, v4 -; GCN-NEXT: v_add_u32_e32 v0, vcc, v1, v4 -; GCN-NEXT: v_mul_hi_u32 v4, v2, v0 +; GCN-NEXT: v_or_b32_e32 v0, v1, v0 +; GCN-NEXT: v_cvt_f32_u32_e32 v3, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v4, v2 ; GCN-NEXT: v_mov_b32_e32 v0, s0 ; GCN-NEXT: v_mov_b32_e32 v1, s1 -; GCN-NEXT: v_mul_lo_u32 v5, v4, v3 -; GCN-NEXT: v_add_u32_e32 v6, vcc, 1, v4 -; GCN-NEXT: v_sub_u32_e32 v2, vcc, v2, v5 -; GCN-NEXT: v_sub_u32_e32 v5, vcc, v2, v3 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3 -; GCN-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc -; GCN-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc -; GCN-NEXT: v_add_u32_e32 v5, vcc, 1, v4 -; GCN-NEXT: v_cmp_ge_u32_e32 vcc, v2, v3 -; GCN-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; GCN-NEXT: v_mul_f32_e32 v4, v3, v4 +; GCN-NEXT: v_trunc_f32_e32 v4, v4 +; GCN-NEXT: v_cvt_u32_f32_e32 v5, v4 +; GCN-NEXT: v_mad_f32 v3, -v4, v2, v3 +; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v3|, v2 +; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v5, vcc ; GCN-NEXT: v_and_b32_e32 v2, 0xffffff, v2 ; GCN-NEXT: flat_store_dword v[0:1], v2 ; GCN-NEXT: s_endpgm @@ -2006,39 +1976,23 @@ define amdgpu_kernel void @v_udiv_i24(ptr addrspace(1) %out, ptr addrspace(1) %i ; GFX1030-NEXT: global_load_ubyte v3, v0, s[2:3] offset:2 ; GFX1030-NEXT: global_load_ushort v4, v0, s[2:3] ; GFX1030-NEXT: s_waitcnt vmcnt(3) -; GFX1030-NEXT: v_readfirstlane_b32 s2, v1 +; GFX1030-NEXT: v_lshlrev_b32_e32 v1, 16, v1 ; GFX1030-NEXT: s_waitcnt vmcnt(2) -; GFX1030-NEXT: v_readfirstlane_b32 s3, v2 +; GFX1030-NEXT: v_or_b32_e32 v1, v2, v1 ; GFX1030-NEXT: s_waitcnt vmcnt(1) -; GFX1030-NEXT: v_readfirstlane_b32 s4, v3 +; GFX1030-NEXT: v_lshlrev_b32_e32 v2, 16, v3 +; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, v1 ; GFX1030-NEXT: s_waitcnt vmcnt(0) -; GFX1030-NEXT: v_readfirstlane_b32 s5, v4 -; GFX1030-NEXT: s_lshl_b32 s2, s2, 16 -; GFX1030-NEXT: s_or_b32 s2, s3, s2 -; GFX1030-NEXT: s_lshl_b32 s4, s4, 16 -; GFX1030-NEXT: v_cvt_f32_u32_e32 v1, s2 -; GFX1030-NEXT: s_sub_i32 s6, 0, s2 -; GFX1030-NEXT: s_or_b32 s4, s5, s4 -; GFX1030-NEXT: v_rcp_iflag_f32_e32 v1, v1 -; GFX1030-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v1 -; GFX1030-NEXT: v_cvt_u32_f32_e32 v1, v1 -; GFX1030-NEXT: v_readfirstlane_b32 s3, v1 -; GFX1030-NEXT: s_mul_i32 s6, s6, s3 -; GFX1030-NEXT: s_mul_hi_u32 s6, s3, s6 -; GFX1030-NEXT: s_add_i32 s3, s3, s6 -; GFX1030-NEXT: s_mul_hi_u32 s3, s4, s3 -; GFX1030-NEXT: s_mul_i32 s5, s3, s2 -; GFX1030-NEXT: s_sub_i32 s4, s4, s5 -; GFX1030-NEXT: s_add_i32 s5, s3, 1 -; GFX1030-NEXT: s_sub_i32 s6, s4, s2 -; GFX1030-NEXT: s_cmp_ge_u32 s4, s2 -; GFX1030-NEXT: s_cselect_b32 s3, s5, s3 -; GFX1030-NEXT: s_cselect_b32 s4, s6, s4 -; GFX1030-NEXT: s_add_i32 s5, s3, 1 -; GFX1030-NEXT: s_cmp_ge_u32 s4, s2 -; GFX1030-NEXT: s_cselect_b32 s2, s5, s3 -; GFX1030-NEXT: s_and_b32 s2, s2, 0xffffff -; GFX1030-NEXT: v_mov_b32_e32 v1, s2 +; GFX1030-NEXT: v_or_b32_e32 v2, v4, v2 +; GFX1030-NEXT: v_rcp_iflag_f32_e32 v3, v1 +; GFX1030-NEXT: v_cvt_f32_u32_e32 v2, v2 +; GFX1030-NEXT: v_mul_f32_e32 v3, v2, v3 +; GFX1030-NEXT: v_trunc_f32_e32 v3, v3 +; GFX1030-NEXT: v_fma_f32 v2, -v3, v1, v2 +; GFX1030-NEXT: v_cvt_u32_f32_e32 v3, v3 +; GFX1030-NEXT: v_cmp_ge_f32_e64 vcc_lo, |v2|, v1 +; GFX1030-NEXT: v_add_co_ci_u32_e32 v1, vcc_lo, 0, v3, vcc_lo +; GFX1030-NEXT: v_and_b32_e32 v1, 0xffffff, v1 ; GFX1030-NEXT: global_store_dword v0, v1, s[0:1] ; GFX1030-NEXT: s_endpgm ; diff --git a/llvm/test/CodeGen/AMDGPU/udiv64.ll b/llvm/test/CodeGen/AMDGPU/udiv64.ll index bde3415c9d1038852acca6e09c57c8d6a15c6f5e..48b9c72ea6892265d2ae2bf587df8d84f5b46f03 100644 --- a/llvm/test/CodeGen/AMDGPU/udiv64.ll +++ b/llvm/test/CodeGen/AMDGPU/udiv64.ll @@ -497,45 +497,73 @@ define i64 @v_test_udiv24_i64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_udiv32_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s8, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_mov_b32 s4, s0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s3, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv32_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s8, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s3 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_mov_b32 s4, s0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s3, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 32 @@ -548,51 +576,77 @@ define amdgpu_kernel void @s_test_udiv32_i64(ptr addrspace(1) %out, i64 %x, i64 define amdgpu_kernel void @s_test_udiv31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_udiv31_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-NEXT: s_mov_b32 s7, 0xf000 ; GCN-NEXT: s_mov_b32 s6, -1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s2, s4, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) ; GCN-NEXT: s_lshr_b32 s2, s3, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s2 ; GCN-NEXT: s_mov_b32 s4, s0 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-NEXT: s_mov_b32 s5, s1 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_udiv31_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe -; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe ; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s6, -1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s2, s4, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 +; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) ; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s2 ; GCN-IR-NEXT: s_mov_b32 s4, s0 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 ; GCN-IR-NEXT: s_mov_b32 s5, s1 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: v_add_i32_e32 v1, vcc, 1, v0 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b64 vcc, -1, 0 +; GCN-IR-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 ; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 33 diff --git a/llvm/test/CodeGen/AMDGPU/urem64.ll b/llvm/test/CodeGen/AMDGPU/urem64.ll index 56cd594fced7f38a87114d19ff6dc5557fc8503e..f35589853393c5d11f18ab9f7aac27dfd80bd6b4 100644 --- a/llvm/test/CodeGen/AMDGPU/urem64.ll +++ b/llvm/test/CodeGen/AMDGPU/urem64.ll @@ -413,52 +413,72 @@ define i64 @v_test_urem_i64(i64 %x, i64 %y) { define amdgpu_kernel void @s_test_urem31_i64(ptr addrspace(1) %out, i64 %x, i64 %y) { ; GCN-LABEL: s_test_urem31_i64: ; GCN: ; %bb.0: -; GCN-NEXT: s_load_dword s4, s[0:1], 0xe +; GCN-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-NEXT: s_mov_b32 s7, 0xf000 +; GCN-NEXT: s_mov_b32 s6, -1 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-NEXT: s_sub_i32 s2, 0, s8 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s2, v0 ; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 ; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_mov_b32 s2, -1 -; GCN-NEXT: s_lshr_b32 s4, s4, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_lshr_b32 s5, s3, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-NEXT: s_mov_b32 s3, 0xf000 -; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-NEXT: s_lshr_b32 s2, s3, 1 +; GCN-NEXT: s_mov_b32 s4, s0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-NEXT: s_mov_b32 s5, s1 ; GCN-NEXT: v_mov_b32_e32 v1, 0 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-NEXT: s_mul_i32 s0, s0, s8 +; GCN-NEXT: s_sub_i32 s0, s2, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: s_sub_i32 s1, s0, s8 +; GCN-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-NEXT: v_mov_b32_e32 v0, s0 +; GCN-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-NEXT: s_endpgm ; ; GCN-IR-LABEL: s_test_urem31_i64: ; GCN-IR: ; %bb.0: -; GCN-IR-NEXT: s_load_dword s4, s[0:1], 0xe +; GCN-IR-NEXT: s_load_dword s2, s[0:1], 0xe +; GCN-IR-NEXT: s_mov_b32 s7, 0xf000 +; GCN-IR-NEXT: s_mov_b32 s6, -1 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_lshr_b32 s8, s2, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s8 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s8 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s2, v0 ; GCN-IR-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 ; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_lshr_b32 s4, s4, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: s_lshr_b32 s5, s3, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v1, s5 -; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v1, v2 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v1, -v2, v0, v1 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v1|, v0 +; GCN-IR-NEXT: s_lshr_b32 s2, s3, 1 +; GCN-IR-NEXT: s_mov_b32 s4, s0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s2, v0 +; GCN-IR-NEXT: s_mov_b32 s5, s1 ; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0 +; GCN-IR-NEXT: v_readfirstlane_b32 s0, v0 +; GCN-IR-NEXT: s_mul_i32 s0, s0, s8 +; GCN-IR-NEXT: s_sub_i32 s0, s2, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: s_sub_i32 s1, s0, s8 +; GCN-IR-NEXT: s_cmp_ge_u32 s0, s8 +; GCN-IR-NEXT: s_cselect_b32 s0, s1, s0 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s0 +; GCN-IR-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr i64 %x, 33 %2 = lshr i64 %y, 33 @@ -472,39 +492,53 @@ define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64> ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 +; GCN-NEXT: s_lshr_b32 s4, s11, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-NEXT: s_lshr_b32 s5, s7, 1 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_sub_i32 s3, s3, s6 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-NEXT: s_sub_i32 s2, 0, s4 +; GCN-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-NEXT: s_lshr_b32 s6, s7, 1 -; GCN-NEXT: s_lshr_b32 s7, s11, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v3, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-NEXT: s_mul_i32 s6, s6, s4 +; GCN-NEXT: s_sub_i32 s5, s5, s6 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; @@ -512,39 +546,53 @@ define amdgpu_kernel void @s_test_urem31_v2i64(ptr addrspace(1) %out, <2 x i64> ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_sub_i32 s3, 0, s2 +; GCN-IR-NEXT: s_lshr_b32 s4, s11, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-IR-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-IR-NEXT: s_lshr_b32 s5, s7, 1 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s2 +; GCN-IR-NEXT: s_sub_i32 s3, s3, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-IR-NEXT: s_lshr_b32 s6, s7, 1 -; GCN-IR-NEXT: s_lshr_b32 s7, s11, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-IR-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s4 +; GCN-IR-NEXT: s_sub_i32 s5, s5, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s4 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr <2 x i64> %x, @@ -616,39 +664,53 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6 ; GCN: ; %bb.0: ; GCN-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-NEXT: v_mov_b32_e32 v1, 0 +; GCN-NEXT: s_waitcnt lgkmcnt(0) +; GCN-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-NEXT: s_sub_i32 s3, 0, s2 +; GCN-NEXT: s_lshr_b32 s4, s11, 9 +; GCN-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-NEXT: s_lshr_b32 s5, s7, 9 +; GCN-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-NEXT: s_mul_i32 s6, s6, s2 +; GCN-NEXT: s_sub_i32 s3, s3, s6 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-NEXT: s_sub_i32 s6, s3, s2 +; GCN-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-NEXT: s_sub_i32 s2, 0, s4 +; GCN-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-NEXT: s_mov_b32 s3, 0xf000 ; GCN-NEXT: s_mov_b32 s2, -1 -; GCN-NEXT: s_waitcnt lgkmcnt(0) -; GCN-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-NEXT: s_lshr_b32 s6, s7, 9 -; GCN-NEXT: s_lshr_b32 s7, s11, 9 -; GCN-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-NEXT: v_mov_b32_e32 v0, s6 +; GCN-NEXT: v_mov_b32_e32 v1, 0 ; GCN-NEXT: v_mov_b32_e32 v3, v1 +; GCN-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-NEXT: s_mul_i32 s6, s6, s4 +; GCN-NEXT: s_sub_i32 s5, s5, s6 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-NEXT: s_sub_i32 s6, s5, s4 +; GCN-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-NEXT: v_mov_b32_e32 v2, s4 ; GCN-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-NEXT: s_endpgm ; @@ -656,39 +718,53 @@ define amdgpu_kernel void @s_test_urem23_64_v2i64(ptr addrspace(1) %out, <2 x i6 ; GCN-IR: ; %bb.0: ; GCN-IR-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0xd ; GCN-IR-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9 -; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 +; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) +; GCN-IR-NEXT: s_lshr_b32 s2, s9, 1 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s2 +; GCN-IR-NEXT: s_sub_i32 s3, 0, s2 +; GCN-IR-NEXT: s_lshr_b32 s4, s11, 9 +; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s4 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v0, v0 +; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v2, v2 +; GCN-IR-NEXT: v_mul_f32_e32 v0, 0x4f7ffffe, v0 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v0, v0 +; GCN-IR-NEXT: v_mul_lo_u32 v1, s3, v0 +; GCN-IR-NEXT: s_lshr_b32 s3, s5, 1 +; GCN-IR-NEXT: s_lshr_b32 s5, s7, 9 +; GCN-IR-NEXT: v_mul_hi_u32 v1, v0, v1 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v0, v1 +; GCN-IR-NEXT: v_mul_hi_u32 v0, s3, v0 +; GCN-IR-NEXT: v_mul_f32_e32 v1, 0x4f7ffffe, v2 +; GCN-IR-NEXT: v_cvt_u32_f32_e32 v1, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v0 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s2 +; GCN-IR-NEXT: s_sub_i32 s3, s3, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s3, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s6, s3, s2 +; GCN-IR-NEXT: s_cmp_ge_u32 s3, s2 +; GCN-IR-NEXT: s_cselect_b32 s6, s6, s3 +; GCN-IR-NEXT: s_sub_i32 s2, 0, s4 +; GCN-IR-NEXT: v_mul_lo_u32 v0, s2, v1 ; GCN-IR-NEXT: s_mov_b32 s3, 0xf000 ; GCN-IR-NEXT: s_mov_b32 s2, -1 -; GCN-IR-NEXT: s_waitcnt lgkmcnt(0) -; GCN-IR-NEXT: s_lshr_b32 s4, s9, 1 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v0, s4 -; GCN-IR-NEXT: s_lshr_b32 s5, s5, 1 -; GCN-IR-NEXT: s_lshr_b32 s6, s7, 9 -; GCN-IR-NEXT: s_lshr_b32 s7, s11, 9 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v2, s5 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v3, v0 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v4, s7 -; GCN-IR-NEXT: v_cvt_f32_u32_e32 v5, s6 -; GCN-IR-NEXT: v_mul_f32_e32 v3, v2, v3 -; GCN-IR-NEXT: v_rcp_iflag_f32_e32 v6, v4 -; GCN-IR-NEXT: v_trunc_f32_e32 v3, v3 -; GCN-IR-NEXT: v_mad_f32 v2, -v3, v0, v2 -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v3 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v0 -; GCN-IR-NEXT: v_mul_f32_e32 v2, v5, v6 -; GCN-IR-NEXT: v_trunc_f32_e32 v2, v2 -; GCN-IR-NEXT: v_addc_u32_e32 v0, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_cvt_u32_f32_e32 v3, v2 -; GCN-IR-NEXT: v_mad_f32 v2, -v2, v4, v5 -; GCN-IR-NEXT: v_cmp_ge_f32_e64 vcc, |v2|, v4 -; GCN-IR-NEXT: v_mul_lo_u32 v0, v0, s4 -; GCN-IR-NEXT: v_addc_u32_e32 v2, vcc, 0, v3, vcc -; GCN-IR-NEXT: v_mul_lo_u32 v2, v2, s7 -; GCN-IR-NEXT: v_sub_i32_e32 v0, vcc, s5, v0 -; GCN-IR-NEXT: v_and_b32_e32 v0, 0x7fffffff, v0 -; GCN-IR-NEXT: v_sub_i32_e32 v2, vcc, s6, v2 -; GCN-IR-NEXT: v_and_b32_e32 v2, 0x7fffffff, v2 +; GCN-IR-NEXT: v_mul_hi_u32 v0, v1, v0 +; GCN-IR-NEXT: v_add_i32_e32 v0, vcc, v1, v0 +; GCN-IR-NEXT: v_mul_hi_u32 v2, s5, v0 +; GCN-IR-NEXT: v_mov_b32_e32 v0, s6 +; GCN-IR-NEXT: v_mov_b32_e32 v1, 0 ; GCN-IR-NEXT: v_mov_b32_e32 v3, v1 +; GCN-IR-NEXT: v_readfirstlane_b32 s6, v2 +; GCN-IR-NEXT: s_mul_i32 s6, s6, s4 +; GCN-IR-NEXT: s_sub_i32 s5, s5, s6 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s5, s6, s5 +; GCN-IR-NEXT: s_sub_i32 s6, s5, s4 +; GCN-IR-NEXT: s_cmp_ge_u32 s5, s4 +; GCN-IR-NEXT: s_cselect_b32 s4, s6, s5 +; GCN-IR-NEXT: v_mov_b32_e32 v2, s4 ; GCN-IR-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0 ; GCN-IR-NEXT: s_endpgm %1 = lshr <2 x i64> %x, diff --git a/llvm/test/CodeGen/ARC/addrmode.ll b/llvm/test/CodeGen/ARC/addrmode.ll index 8ca3749025e908472e4bfd3526b6618cb80f4c70..248ec7d4238f1ab7ba3efee40e0506d27fe5036c 100644 --- a/llvm/test/CodeGen/ARC/addrmode.ll +++ b/llvm/test/CodeGen/ARC/addrmode.ll @@ -2,17 +2,17 @@ ; CHECK-LABEL: copy ; CHECK-NOT: add -define void @copy(i8* inreg nocapture %p, i8* inreg nocapture readonly %q) { +define void @copy(ptr inreg nocapture %p, ptr inreg nocapture readonly %q) { entry: br label %while.cond while.cond: ; preds = %while.cond, %entry - %p.addr.0 = phi i8* [ %p, %entry ], [ %incdec.ptr1, %while.cond ] - %q.addr.0 = phi i8* [ %q, %entry ], [ %incdec.ptr, %while.cond ] - %incdec.ptr = getelementptr inbounds i8, i8* %q.addr.0, i32 1 - %0 = load i8, i8* %q.addr.0, align 1 - %incdec.ptr1 = getelementptr inbounds i8, i8* %p.addr.0, i32 1 - store i8 %0, i8* %p.addr.0, align 1 + %p.addr.0 = phi ptr [ %p, %entry ], [ %incdec.ptr1, %while.cond ] + %q.addr.0 = phi ptr [ %q, %entry ], [ %incdec.ptr, %while.cond ] + %incdec.ptr = getelementptr inbounds i8, ptr %q.addr.0, i32 1 + %0 = load i8, ptr %q.addr.0, align 1 + %incdec.ptr1 = getelementptr inbounds i8, ptr %p.addr.0, i32 1 + store i8 %0, ptr %p.addr.0, align 1 %tobool = icmp eq i8 %0, 0 br i1 %tobool, label %while.end, label %while.cond @@ -21,11 +21,11 @@ while.end: ; preds = %while.cond } -%struct._llist = type { %struct._llist*, %struct._llist*, i32 } +%struct._llist = type { ptr, ptr, i32 } ; CHECK-LABEL: neg1 ; CHECK-NOT: std.ab -define void @neg1(i8* inreg nocapture %a, i8* inreg nocapture readonly %b, i32 inreg %n) { +define void @neg1(ptr inreg nocapture %a, ptr inreg nocapture readonly %b, i32 inreg %n) { entry: %cmp6 = icmp sgt i32 %n, 0 br i1 %cmp6, label %for.body, label %for.cond.cleanup @@ -35,11 +35,11 @@ for.cond.cleanup: for.body: %i.07 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds i8, i8* %b, i32 %i.07 - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %b, i32 %i.07 + %0 = load i8, ptr %arrayidx, align 1 %mul = mul nuw nsw i32 %i.07, 257 - %arrayidx1 = getelementptr inbounds i8, i8* %a, i32 %mul - store i8 %0, i8* %arrayidx1, align 1 + %arrayidx1 = getelementptr inbounds i8, ptr %a, i32 %mul + store i8 %0, ptr %arrayidx1, align 1 %inc = add nuw nsw i32 %i.07, 1 %exitcond = icmp eq i32 %inc, %n br i1 %exitcond, label %for.cond.cleanup, label %for.body @@ -47,7 +47,7 @@ for.body: ; CHECK-LABEL: neg2 ; CHECK-NOT: st.ab -define void @neg2(%struct._llist* inreg %a, i32 inreg %n) { +define void @neg2(ptr inreg %a, i32 inreg %n) { entry: %cmp13 = icmp sgt i32 %n, 0 br i1 %cmp13, label %for.body, label %for.cond.cleanup @@ -57,11 +57,11 @@ for.cond.cleanup: for.body: %i.014 = phi i32 [ %inc, %for.body ], [ 0, %entry ] - %arrayidx = getelementptr inbounds %struct._llist, %struct._llist* %a, i32 %i.014 - %next = getelementptr inbounds %struct._llist, %struct._llist* %arrayidx, i32 0, i32 0 - store %struct._llist* %arrayidx, %struct._llist** %next, align 4 - %prev = getelementptr inbounds %struct._llist, %struct._llist* %a, i32 %i.014, i32 1 - store %struct._llist* %arrayidx, %struct._llist** %prev, align 4 + %arrayidx = getelementptr inbounds %struct._llist, ptr %a, i32 %i.014 + %next = getelementptr inbounds %struct._llist, ptr %arrayidx, i32 0, i32 0 + store ptr %arrayidx, ptr %next, align 4 + %prev = getelementptr inbounds %struct._llist, ptr %a, i32 %i.014, i32 1 + store ptr %arrayidx, ptr %prev, align 4 %inc = add nuw nsw i32 %i.014, 1 %exitcond = icmp eq i32 %inc, %n br i1 %exitcond, label %for.cond.cleanup, label %for.body diff --git a/llvm/test/CodeGen/ARC/call.ll b/llvm/test/CodeGen/ARC/call.ll index 2985439b5f10d5544c79480438c1943f65da436a..d74b35a35f65ef2297139fa5a93b1edd974cefef 100644 --- a/llvm/test/CodeGen/ARC/call.ll +++ b/llvm/test/CodeGen/ARC/call.ll @@ -73,14 +73,14 @@ define i64 @ret1() nounwind { ret i64 281470698455295 } -@funcptr = external global i32 (i32)*, align 4 +@funcptr = external global ptr, align 4 ; Indirect calls use JL ; CHECK-LABEL: call_indirect ; CHECK-DAG: ld %r[[REG:[0-9]+]], [@funcptr] ; CHECK-DAG: mov %r0, 12 ; CHECK: jl [%r[[REG]]] define i32 @call_indirect(i32 %x) nounwind { - %f = load i32 (i32)*, i32 (i32)** @funcptr, align 4 + %f = load ptr, ptr @funcptr, align 4 %call = call i32 %f(i32 12) %add = add nsw i32 %call, %x ret i32 %add diff --git a/llvm/test/CodeGen/ARC/ldst.ll b/llvm/test/CodeGen/ARC/ldst.ll index dd1529875a667b75fd5eaec0919e88a9cfcbbafe..99b43de71cb4d5b2124cc0bea8061d72c98b7df7 100644 --- a/llvm/test/CodeGen/ARC/ldst.ll +++ b/llvm/test/CodeGen/ARC/ldst.ll @@ -3,40 +3,40 @@ ; CHECK-LABEL: load32 ; CHECK: ld %r0, [%r0,16000] -define i32 @load32(i32* %bp) nounwind { +define i32 @load32(ptr %bp) nounwind { entry: - %gep = getelementptr i32, i32* %bp, i32 4000 - %v = load i32, i32* %gep, align 4 + %gep = getelementptr i32, ptr %bp, i32 4000 + %v = load i32, ptr %gep, align 4 ret i32 %v } ; CHECK-LABEL: load16 ; CHECK: ldh %r0, [%r0,8000] -define i16 @load16(i16* %bp) nounwind { +define i16 @load16(ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 4000 - %v = load i16, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 4000 + %v = load i16, ptr %gep, align 2 ret i16 %v } ; CHECK-LABEL: load8 ; CHECK: ldb %r0, [%r0,4000] -define i8 @load8(i8* %bp) nounwind { +define i8 @load8(ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 4000 - %v = load i8, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 4000 + %v = load i8, ptr %gep, align 1 ret i8 %v } ; CHECK-LABEL: sextload16 ; CHECK: ldh.x %r0, [%r0,8000] -define i32 @sextload16(i16* %bp) nounwind { +define i32 @sextload16(ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 4000 - %vl = load i16, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 4000 + %vl = load i16, ptr %gep, align 2 %v = sext i16 %vl to i32 ret i32 %v } @@ -44,10 +44,10 @@ entry: ; CHECK-LABEL: sextload8 ; CHECK: ldb.x %r0, [%r0,4000] -define i32 @sextload8(i8* %bp) nounwind { +define i32 @sextload8(ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 4000 - %vl = load i8, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 4000 + %vl = load i8, ptr %gep, align 1 %v = sext i8 %vl to i32 ret i32 %v } @@ -55,10 +55,10 @@ entry: ; CHECK-LABEL: s_sextload16 ; CHECK: ldh.x %r0, [%r0,32] -define i32 @s_sextload16(i16* %bp) nounwind { +define i32 @s_sextload16(ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 16 - %vl = load i16, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 16 + %vl = load i16, ptr %gep, align 2 %v = sext i16 %vl to i32 ret i32 %v } @@ -66,10 +66,10 @@ entry: ; CHECK-LABEL: s_sextload8 ; CHECK: ldb.x %r0, [%r0,16] -define i32 @s_sextload8(i8* %bp) nounwind { +define i32 @s_sextload8(ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 16 - %vl = load i8, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 16 + %vl = load i8, ptr %gep, align 1 %v = sext i8 %vl to i32 ret i32 %v } @@ -79,10 +79,10 @@ entry: ; CHECK: st %r0, [%r[[REG]],0] ; Long range stores (offset does not fit in s9) must be add followed by st. -define void @store32(i32 %val, i32* %bp) nounwind { +define void @store32(i32 %val, ptr %bp) nounwind { entry: - %gep = getelementptr i32, i32* %bp, i32 4000 - store i32 %val, i32* %gep, align 4 + %gep = getelementptr i32, ptr %bp, i32 4000 + store i32 %val, ptr %gep, align 4 ret void } @@ -90,10 +90,10 @@ entry: ; CHECK: add %r[[REG:[0-9]+]], %r1, 8000 ; CHECK: sth %r0, [%r[[REG]],0] -define void @store16(i16 zeroext %val, i16* %bp) nounwind { +define void @store16(i16 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 4000 - store i16 %val, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 4000 + store i16 %val, ptr %gep, align 2 ret void } @@ -101,10 +101,10 @@ entry: ; CHECK: add %r[[REG:[0-9]+]], %r1, 4000 ; CHECK: stb %r0, [%r[[REG]],0] -define void @store8(i8 zeroext %val, i8* %bp) nounwind { +define void @store8(i8 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 4000 - store i8 %val, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 4000 + store i8 %val, ptr %gep, align 1 ret void } @@ -112,30 +112,30 @@ entry: ; CHECK-LABEL: s_store32 ; CHECK-NOT: add ; CHECK: st %r0, [%r1,64] -define void @s_store32(i32 %val, i32* %bp) nounwind { +define void @s_store32(i32 %val, ptr %bp) nounwind { entry: - %gep = getelementptr i32, i32* %bp, i32 16 - store i32 %val, i32* %gep, align 4 + %gep = getelementptr i32, ptr %bp, i32 16 + store i32 %val, ptr %gep, align 4 ret void } ; CHECK-LABEL: s_store16 ; CHECK-NOT: add ; CHECK: sth %r0, [%r1,32] -define void @s_store16(i16 zeroext %val, i16* %bp) nounwind { +define void @s_store16(i16 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i16, i16* %bp, i32 16 - store i16 %val, i16* %gep, align 2 + %gep = getelementptr i16, ptr %bp, i32 16 + store i16 %val, ptr %gep, align 2 ret void } ; CHECK-LABEL: s_store8 ; CHECK-NOT: add ; CHECK: stb %r0, [%r1,16] -define void @s_store8(i8 zeroext %val, i8* %bp) nounwind { +define void @s_store8(i8 zeroext %val, ptr %bp) nounwind { entry: - %gep = getelementptr i8, i8* %bp, i32 16 - store i8 %val, i8* %gep, align 1 + %gep = getelementptr i8, ptr %bp, i32 16 + store i8 %val, ptr %gep, align 1 ret void } @@ -149,7 +149,7 @@ entry: ; CHECK: st %r0, [@aaaa+64] define void @g_store32(i32 %val) nounwind { entry: - store i32 %val, i32* getelementptr inbounds ([128 x i32], [128 x i32]* @aaaa, i32 0, i32 16), align 4 + store i32 %val, ptr getelementptr inbounds ([128 x i32], ptr @aaaa, i32 0, i32 16), align 4 ret void } @@ -157,8 +157,8 @@ entry: ; CHECK-NOT: add ; CHECK: ld %r0, [@aaaa+64] define i32 @g_load32() nounwind { - %gep = getelementptr inbounds [128 x i32], [128 x i32]* @aaaa, i32 0, i32 16 - %v = load i32, i32* %gep, align 4 + %gep = getelementptr inbounds [128 x i32], ptr @aaaa, i32 0, i32 16 + %v = load i32, ptr %gep, align 4 ret i32 %v } @@ -167,7 +167,7 @@ define i32 @g_load32() nounwind { ; CHECK: sth %r0, [@bbbb+32] define void @g_store16(i16 %val) nounwind { entry: - store i16 %val, i16* getelementptr inbounds ([128 x i16], [128 x i16]* @bbbb, i16 0, i16 16), align 2 + store i16 %val, ptr getelementptr inbounds ([128 x i16], ptr @bbbb, i16 0, i16 16), align 2 ret void } @@ -175,8 +175,8 @@ entry: ; CHECK-NOT: add ; CHECK: ldh %r0, [@bbbb+32] define i16 @g_load16() nounwind { - %gep = getelementptr inbounds [128 x i16], [128 x i16]* @bbbb, i16 0, i16 16 - %v = load i16, i16* %gep, align 2 + %gep = getelementptr inbounds [128 x i16], ptr @bbbb, i16 0, i16 16 + %v = load i16, ptr %gep, align 2 ret i16 %v } @@ -185,7 +185,7 @@ define i16 @g_load16() nounwind { ; CHECK: stb %r0, [@cccc+16] define void @g_store8(i8 %val) nounwind { entry: - store i8 %val, i8* getelementptr inbounds ([128 x i8], [128 x i8]* @cccc, i8 0, i8 16), align 1 + store i8 %val, ptr getelementptr inbounds ([128 x i8], ptr @cccc, i8 0, i8 16), align 1 ret void } @@ -193,8 +193,8 @@ entry: ; CHECK-NOT: add ; CHECK: ldb %r0, [@cccc+16] define i8 @g_load8() nounwind { - %gep = getelementptr inbounds [128 x i8], [128 x i8]* @cccc, i8 0, i8 16 - %v = load i8, i8* %gep, align 1 + %gep = getelementptr inbounds [128 x i8], ptr @cccc, i8 0, i8 16 + %v = load i8, ptr %gep, align 1 ret i8 %v } @@ -202,10 +202,10 @@ define i8 @g_load8() nounwind { ; CHECK-DAG: ldh %r[[REG0:[0-9]+]], [%r0,0] ; CHECK-DAG: ldh %r[[REG1:[0-9]+]], [%r0,2] ; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 16 -define i32 @align2_load32(i8* %p) nounwind { +define i32 @align2_load32(ptr %p) nounwind { entry: - %bp = bitcast i8* %p to i32* - %v = load i32, i32* %bp, align 2 + %bp = bitcast ptr %p to ptr + %v = load i32, ptr %bp, align 2 ret i32 %v } @@ -220,10 +220,10 @@ entry: ; CHECK-DAG: or %r[[AREG01:[0-9]+]], %r[[AREG1]], %r[[REG0]] ; CHECK-DAG: or %r[[AREG23:[0-9]+]], %r[[AREG3]], %r[[AREG2]] ; CHECK-DAG: or %r0, %r[[AREG23]], %r[[AREG01]] -define i32 @align1_load32(i8* %p) nounwind { +define i32 @align1_load32(ptr %p) nounwind { entry: - %bp = bitcast i8* %p to i32* - %v = load i32, i32* %bp, align 1 + %bp = bitcast ptr %p to ptr + %v = load i32, ptr %bp, align 1 ret i32 %v } @@ -231,10 +231,10 @@ entry: ; CHECK-DAG: ldb %r[[REG0:[0-9]+]], [%r0,0] ; CHECK-DAG: ldb %r[[REG1:[0-9]+]], [%r0,1] ; CHECK-DAG: asl %r[[REG2:[0-9]+]], %r[[REG1]], 8 -define i16 @align1_load16(i8* %p) nounwind { +define i16 @align1_load16(ptr %p) nounwind { entry: - %bp = bitcast i8* %p to i16* - %v = load i16, i16* %bp, align 1 + %bp = bitcast ptr %p to ptr + %v = load i16, ptr %bp, align 1 ret i16 %v } @@ -242,10 +242,10 @@ entry: ; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 16 ; CHECK-DAG: sth %r1, [%r0,0] ; CHECK-DAG: sth %r[[REG:[0-9]+]], [%r0,2] -define void @align2_store32(i8* %p, i32 %v) nounwind { +define void @align2_store32(ptr %p, i32 %v) nounwind { entry: - %bp = bitcast i8* %p to i32* - store i32 %v, i32* %bp, align 2 + %bp = bitcast ptr %p to ptr + store i32 %v, ptr %bp, align 2 ret void } @@ -253,10 +253,10 @@ entry: ; CHECK-DAG: lsr %r[[REG:[0-9]+]], %r1, 8 ; CHECK-DAG: stb %r1, [%r0,0] ; CHECK-DAG: stb %r[[REG:[0-9]+]], [%r0,1] -define void @align1_store16(i8* %p, i16 %v) nounwind { +define void @align1_store16(ptr %p, i16 %v) nounwind { entry: - %bp = bitcast i8* %p to i16* - store i16 %v, i16* %bp, align 1 + %bp = bitcast ptr %p to ptr + store i16 %v, ptr %bp, align 1 ret void } @@ -268,9 +268,9 @@ entry: ; CHECK-DAG: stb %r[[REG0]], [%r0,1] ; CHECK-DAG: stb %r[[REG1]], [%r0,2] ; CHECK-DAG: stb %r[[REG2]], [%r0,3] -define void @align1_store32(i8* %p, i32 %v) nounwind { +define void @align1_store32(ptr %p, i32 %v) nounwind { entry: - %bp = bitcast i8* %p to i32* - store i32 %v, i32* %bp, align 1 + %bp = bitcast ptr %p to ptr + store i32 %v, ptr %bp, align 1 ret void } diff --git a/llvm/test/CodeGen/ARM/GlobalISel/select-const.mir b/llvm/test/CodeGen/ARM/GlobalISel/select-const.mir new file mode 100644 index 0000000000000000000000000000000000000000..5a1ea32a91c9efa30b0868edb7922d92579aec27 --- /dev/null +++ b/llvm/test/CodeGen/ARM/GlobalISel/select-const.mir @@ -0,0 +1,25 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple arm-- -mattr=+v6 -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s + +--- +name: get_inverted +legalized: true +regBankSelected: true +selected: false +tracksRegLiveness: true +registers: + - { id: 0, class: gprb } +body: | + bb.0: + liveins: $r0 + ; CHECK-LABEL: name: get_inverted + ; CHECK: liveins: $r0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[MVNi:%[0-9]+]]:gpr = MVNi 0, 14 /* CC::al */, $noreg, $noreg + ; CHECK-NEXT: $r0 = COPY [[MVNi]] + ; CHECK-NEXT: MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 + %0:gprb(s32) = G_CONSTANT i32 -1 + $r0 = COPY %0(s32) + MOVPCLR 14 /* CC::al */, $noreg, implicit $r0 + +... diff --git a/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll b/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll index 8b2c28701adbd798f1bf000ba437e3f617f44861..bd74e4608645a63fdcd35dd0a9a2c703d65b3afe 100644 --- a/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll +++ b/llvm/test/CodeGen/CSKY/atomic-cmpxchg-flag.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp, +define i1 @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 signext %cmp, i32 signext %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; CSKY: # %bb.0: # %entry @@ -26,7 +26,7 @@ define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp, ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; entry: - %0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst + %0 = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst %1 = extractvalue { i32, i1 } %0, 1 ret i1 %1 } diff --git a/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll b/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll index fc0c08b27234bf24fc717bf43befd6bdd079fa6c..a257a0444d8b9d212027d59a48fed99d735dcf1a 100644 --- a/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll +++ b/llvm/test/CodeGen/CSKY/atomic-cmpxchg.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_monotonic_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -24,11 +24,11 @@ define void @cmpxchg_i8_monotonic_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val monotonic monotonic ret void } -define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acquire_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -50,11 +50,11 @@ define void @cmpxchg_i8_acquire_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire monotonic ret void } -define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acquire_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -76,11 +76,11 @@ define void @cmpxchg_i8_acquire_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acquire acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acquire acquire ret void } -define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_release_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -102,11 +102,11 @@ define void @cmpxchg_i8_release_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release monotonic ret void } -define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_release_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -128,11 +128,11 @@ define void @cmpxchg_i8_release_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val release acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val release acquire ret void } -define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acq_rel_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -154,11 +154,11 @@ define void @cmpxchg_i8_acq_rel_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel monotonic ret void } -define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_acq_rel_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -180,11 +180,11 @@ define void @cmpxchg_i8_acq_rel_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI6_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val acq_rel acquire ret void } -define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_seq_cst_monotonic(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -206,11 +206,11 @@ define void @cmpxchg_i8_seq_cst_monotonic(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI7_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst monotonic ret void } -define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_seq_cst_acquire(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -232,11 +232,11 @@ define void @cmpxchg_i8_seq_cst_acquire(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI8_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst acquire ret void } -define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { +define void @cmpxchg_i8_seq_cst_seq_cst(ptr %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-LABEL: cmpxchg_i8_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -258,11 +258,11 @@ define void @cmpxchg_i8_seq_cst_seq_cst(i8* %ptr, i8 %cmp, i8 %val) nounwind { ; CSKY-NEXT: .LCPI9_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 ; - %res = cmpxchg i8* %ptr, i8 %cmp, i8 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i8 %cmp, i8 %val seq_cst seq_cst ret void } -define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_monotonic_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -284,11 +284,11 @@ define void @cmpxchg_i16_monotonic_monotonic(i16* %ptr, i16 %cmp, i16 %val) noun ; CSKY-NEXT: .LCPI10_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val monotonic monotonic ret void } -define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acquire_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -310,11 +310,11 @@ define void @cmpxchg_i16_acquire_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI11_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire monotonic ret void } -define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acquire_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -336,11 +336,11 @@ define void @cmpxchg_i16_acquire_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI12_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acquire acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acquire acquire ret void } -define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_release_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -362,11 +362,11 @@ define void @cmpxchg_i16_release_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI13_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release monotonic ret void } -define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_release_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -388,11 +388,11 @@ define void @cmpxchg_i16_release_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI14_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val release acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val release acquire ret void } -define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acq_rel_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -414,11 +414,11 @@ define void @cmpxchg_i16_acq_rel_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI15_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel monotonic ret void } -define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_acq_rel_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -440,11 +440,11 @@ define void @cmpxchg_i16_acq_rel_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI16_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val acq_rel acquire ret void } -define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_seq_cst_monotonic(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -466,11 +466,11 @@ define void @cmpxchg_i16_seq_cst_monotonic(i16* %ptr, i16 %cmp, i16 %val) nounwi ; CSKY-NEXT: .LCPI17_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst monotonic ret void } -define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_seq_cst_acquire(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -492,11 +492,11 @@ define void @cmpxchg_i16_seq_cst_acquire(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI18_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst acquire ret void } -define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind { +define void @cmpxchg_i16_seq_cst_seq_cst(ptr %ptr, i16 %cmp, i16 %val) nounwind { ; CSKY-LABEL: cmpxchg_i16_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -518,11 +518,11 @@ define void @cmpxchg_i16_seq_cst_seq_cst(i16* %ptr, i16 %cmp, i16 %val) nounwind ; CSKY-NEXT: .LCPI19_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 ; - %res = cmpxchg i16* %ptr, i16 %cmp, i16 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i16 %cmp, i16 %val seq_cst seq_cst ret void } -define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_monotonic_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -544,11 +544,11 @@ define void @cmpxchg_i32_monotonic_monotonic(i32* %ptr, i32 %cmp, i32 %val) noun ; CSKY-NEXT: .LCPI20_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val monotonic monotonic ret void } -define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acquire_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -570,11 +570,11 @@ define void @cmpxchg_i32_acquire_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI21_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire monotonic ret void } -define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acquire_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -596,11 +596,11 @@ define void @cmpxchg_i32_acquire_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI22_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acquire acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acquire acquire ret void } -define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_release_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -622,11 +622,11 @@ define void @cmpxchg_i32_release_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI23_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release monotonic ret void } -define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_release_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -648,11 +648,11 @@ define void @cmpxchg_i32_release_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI24_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val release acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val release acquire ret void } -define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acq_rel_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -674,11 +674,11 @@ define void @cmpxchg_i32_acq_rel_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI25_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel monotonic ret void } -define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_acq_rel_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -700,11 +700,11 @@ define void @cmpxchg_i32_acq_rel_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI26_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val acq_rel acquire ret void } -define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_seq_cst_monotonic(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -726,11 +726,11 @@ define void @cmpxchg_i32_seq_cst_monotonic(i32* %ptr, i32 %cmp, i32 %val) nounwi ; CSKY-NEXT: .LCPI27_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst monotonic ret void } -define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_seq_cst_acquire(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -752,11 +752,11 @@ define void @cmpxchg_i32_seq_cst_acquire(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI28_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst acquire ret void } -define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind { +define void @cmpxchg_i32_seq_cst_seq_cst(ptr %ptr, i32 %cmp, i32 %val) nounwind { ; CSKY-LABEL: cmpxchg_i32_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -778,11 +778,11 @@ define void @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 %cmp, i32 %val) nounwind ; CSKY-NEXT: .LCPI29_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 ; - %res = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i32 %cmp, i32 %val seq_cst seq_cst ret void } -define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_monotonic_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_monotonic_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -808,11 +808,11 @@ define void @cmpxchg_i64_monotonic_monotonic(i64* %ptr, i64 %cmp, i64 %val) noun ; CSKY-NEXT: .LCPI30_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val monotonic monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val monotonic monotonic ret void } -define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acquire_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acquire_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -839,11 +839,11 @@ define void @cmpxchg_i64_acquire_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI31_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire monotonic ret void } -define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acquire_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acquire_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -869,11 +869,11 @@ define void @cmpxchg_i64_acquire_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI32_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acquire acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acquire acquire ret void } -define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_release_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_release_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -900,11 +900,11 @@ define void @cmpxchg_i64_release_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI33_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release monotonic ret void } -define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_release_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_release_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -931,11 +931,11 @@ define void @cmpxchg_i64_release_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI34_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val release acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val release acquire ret void } -define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acq_rel_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acq_rel_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -962,11 +962,11 @@ define void @cmpxchg_i64_acq_rel_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI35_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel monotonic ret void } -define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_acq_rel_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_acq_rel_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -993,11 +993,11 @@ define void @cmpxchg_i64_acq_rel_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI36_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val acq_rel acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val acq_rel acquire ret void } -define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_seq_cst_monotonic(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_seq_cst_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1024,11 +1024,11 @@ define void @cmpxchg_i64_seq_cst_monotonic(i64* %ptr, i64 %cmp, i64 %val) nounwi ; CSKY-NEXT: .LCPI37_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst monotonic + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst monotonic ret void } -define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_seq_cst_acquire(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_seq_cst_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1055,11 +1055,11 @@ define void @cmpxchg_i64_seq_cst_acquire(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI38_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst acquire + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst acquire ret void } -define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind { +define void @cmpxchg_i64_seq_cst_seq_cst(ptr %ptr, i64 %cmp, i64 %val) nounwind { ; CSKY-LABEL: cmpxchg_i64_seq_cst_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1085,6 +1085,6 @@ define void @cmpxchg_i64_seq_cst_seq_cst(i64* %ptr, i64 %cmp, i64 %val) nounwind ; CSKY-NEXT: .LCPI39_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 ; - %res = cmpxchg i64* %ptr, i64 %cmp, i64 %val seq_cst seq_cst + %res = cmpxchg ptr %ptr, i64 %cmp, i64 %val seq_cst seq_cst ret void } diff --git a/llvm/test/CodeGen/CSKY/atomic-load-store.ll b/llvm/test/CodeGen/CSKY/atomic-load-store.ll index 064f05b326938c90b72ef41efd533cab0d0e178e..553e8ffb1ff21130a5ef35ab64e4c2d8b46be788 100644 --- a/llvm/test/CodeGen/CSKY/atomic-load-store.ll +++ b/llvm/test/CodeGen/CSKY/atomic-load-store.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { +define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -18,11 +18,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a unordered, align 1 + %1 = load atomic i8, ptr %a unordered, align 1 ret i8 %1 } -define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { +define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -38,11 +38,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a monotonic, align 1 + %1 = load atomic i8, ptr %a monotonic, align 1 ret i8 %1 } -define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { +define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -58,11 +58,11 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a acquire, align 1 + %1 = load atomic i8, ptr %a acquire, align 1 ret i8 %1 } -define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { +define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -78,11 +78,11 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long __atomic_load_1 ; - %1 = load atomic i8, i8* %a seq_cst, align 1 + %1 = load atomic i8, ptr %a seq_cst, align 1 ret i8 %1 } -define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { +define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -98,11 +98,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a unordered, align 2 + %1 = load atomic i16, ptr %a unordered, align 2 ret i16 %1 } -define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { +define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -118,11 +118,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a monotonic, align 2 + %1 = load atomic i16, ptr %a monotonic, align 2 ret i16 %1 } -define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { +define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -138,11 +138,11 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI6_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a acquire, align 2 + %1 = load atomic i16, ptr %a acquire, align 2 ret i16 %1 } -define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { +define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -158,11 +158,11 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { ; CSKY-NEXT: .LCPI7_0: ; CSKY-NEXT: .long __atomic_load_2 ; - %1 = load atomic i16, i16* %a seq_cst, align 2 + %1 = load atomic i16, ptr %a seq_cst, align 2 ret i16 %1 } -define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { +define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -178,11 +178,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI8_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a unordered, align 4 + %1 = load atomic i32, ptr %a unordered, align 4 ret i32 %1 } -define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { +define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -198,11 +198,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI9_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a monotonic, align 4 + %1 = load atomic i32, ptr %a monotonic, align 4 ret i32 %1 } -define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { +define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -218,11 +218,11 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI10_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a acquire, align 4 + %1 = load atomic i32, ptr %a acquire, align 4 ret i32 %1 } -define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { +define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -238,11 +238,11 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { ; CSKY-NEXT: .LCPI11_0: ; CSKY-NEXT: .long __atomic_load_4 ; - %1 = load atomic i32, i32* %a seq_cst, align 4 + %1 = load atomic i32, ptr %a seq_cst, align 4 ret i32 %1 } -define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { +define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -258,11 +258,11 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI12_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a unordered, align 8 + %1 = load atomic i64, ptr %a unordered, align 8 ret i64 %1 } -define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { +define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -278,11 +278,11 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI13_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a monotonic, align 8 + %1 = load atomic i64, ptr %a monotonic, align 8 ret i64 %1 } -define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { +define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -298,11 +298,11 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI14_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a acquire, align 8 + %1 = load atomic i64, ptr %a acquire, align 8 ret i64 %1 } -define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { +define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; CSKY-LABEL: atomic_load_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -318,11 +318,11 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { ; CSKY-NEXT: .LCPI15_0: ; CSKY-NEXT: .long __atomic_load_8 ; - %1 = load atomic i64, i64* %a seq_cst, align 8 + %1 = load atomic i64, ptr %a seq_cst, align 8 ret i64 %1 } -define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_unordered(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -338,11 +338,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI16_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a unordered, align 1 + store atomic i8 %b, ptr %a unordered, align 1 ret void } -define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -358,11 +358,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI17_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a monotonic, align 1 + store atomic i8 %b, ptr %a monotonic, align 1 ret void } -define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -378,11 +378,11 @@ define void @atomic_store_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI18_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a release, align 1 + store atomic i8 %b, ptr %a release, align 1 ret void } -define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define void @atomic_store_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomic_store_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -398,11 +398,11 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .LCPI19_0: ; CSKY-NEXT: .long __atomic_store_1 ; - store atomic i8 %b, i8* %a seq_cst, align 1 + store atomic i8 %b, ptr %a seq_cst, align 1 ret void } -define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_unordered(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -418,11 +418,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI20_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a unordered, align 2 + store atomic i16 %b, ptr %a unordered, align 2 ret void } -define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -438,11 +438,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI21_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a monotonic, align 2 + store atomic i16 %b, ptr %a monotonic, align 2 ret void } -define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -458,11 +458,11 @@ define void @atomic_store_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI22_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a release, align 2 + store atomic i16 %b, ptr %a release, align 2 ret void } -define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define void @atomic_store_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomic_store_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -478,11 +478,11 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .LCPI23_0: ; CSKY-NEXT: .long __atomic_store_2 ; - store atomic i16 %b, i16* %a seq_cst, align 2 + store atomic i16 %b, ptr %a seq_cst, align 2 ret void } -define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_unordered(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -498,11 +498,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI24_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a unordered, align 4 + store atomic i32 %b, ptr %a unordered, align 4 ret void } -define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -518,11 +518,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI25_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a monotonic, align 4 + store atomic i32 %b, ptr %a monotonic, align 4 ret void } -define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -538,11 +538,11 @@ define void @atomic_store_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI26_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a release, align 4 + store atomic i32 %b, ptr %a release, align 4 ret void } -define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define void @atomic_store_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomic_store_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -558,11 +558,11 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .LCPI27_0: ; CSKY-NEXT: .long __atomic_store_4 ; - store atomic i32 %b, i32* %a seq_cst, align 4 + store atomic i32 %b, ptr %a seq_cst, align 4 ret void } -define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_unordered(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_unordered: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -578,11 +578,11 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI28_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a unordered, align 8 + store atomic i64 %b, ptr %a unordered, align 8 ret void } -define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -598,11 +598,11 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI29_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a monotonic, align 8 + store atomic i64 %b, ptr %a monotonic, align 8 ret void } -define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -618,11 +618,11 @@ define void @atomic_store_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI30_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a release, align 8 + store atomic i64 %b, ptr %a release, align 8 ret void } -define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define void @atomic_store_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomic_store_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -638,6 +638,6 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .LCPI31_0: ; CSKY-NEXT: .long __atomic_store_8 ; - store atomic i64 %b, i64* %a seq_cst, align 8 + store atomic i64 %b, ptr %a seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/CSKY/atomic-rmw.ll b/llvm/test/CodeGen/CSKY/atomic-rmw.ll index c9fd90bb8c3478ffab88677c904d5ee5e964ce50..ee1c8194cd35951c4f483c0ac4336418ccb59eff 100644 --- a/llvm/test/CodeGen/CSKY/atomic-rmw.ll +++ b/llvm/test/CodeGen/CSKY/atomic-rmw.ll @@ -2,7 +2,7 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck -check-prefix=CSKY %s -define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -17,11 +17,11 @@ define i8 @atomicrmw_xchg_i8_monotonic(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b monotonic + %1 = atomicrmw xchg ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -36,11 +36,11 @@ define i8 @atomicrmw_xchg_i8_acquire(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b acquire + %1 = atomicrmw xchg ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -55,11 +55,11 @@ define i8 @atomicrmw_xchg_i8_release(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b release + %1 = atomicrmw xchg ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -74,11 +74,11 @@ define i8 @atomicrmw_xchg_i8_acq_rel(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b acq_rel + %1 = atomicrmw xchg ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_xchg_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -93,11 +93,11 @@ define i8 @atomicrmw_xchg_i8_seq_cst(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long __atomic_exchange_1 - %1 = atomicrmw xchg i8* %a, i8 %b seq_cst + %1 = atomicrmw xchg ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -112,11 +112,11 @@ define i8 @atomicrmw_add_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b monotonic + %1 = atomicrmw add ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -131,11 +131,11 @@ define i8 @atomicrmw_add_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI6_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b acquire + %1 = atomicrmw add ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -150,11 +150,11 @@ define i8 @atomicrmw_add_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI7_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b release + %1 = atomicrmw add ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -169,11 +169,11 @@ define i8 @atomicrmw_add_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI8_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b acq_rel + %1 = atomicrmw add ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_add_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -188,11 +188,11 @@ define i8 @atomicrmw_add_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI9_0: ; CSKY-NEXT: .long __atomic_fetch_add_1 - %1 = atomicrmw add i8* %a, i8 %b seq_cst + %1 = atomicrmw add ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -207,11 +207,11 @@ define i8 @atomicrmw_sub_i8_monotonic(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI10_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b monotonic + %1 = atomicrmw sub ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -226,11 +226,11 @@ define i8 @atomicrmw_sub_i8_acquire(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI11_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b acquire + %1 = atomicrmw sub ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -245,11 +245,11 @@ define i8 @atomicrmw_sub_i8_release(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI12_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b release + %1 = atomicrmw sub ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -264,11 +264,11 @@ define i8 @atomicrmw_sub_i8_acq_rel(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI13_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b acq_rel + %1 = atomicrmw sub ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_sub_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -283,11 +283,11 @@ define i8 @atomicrmw_sub_i8_seq_cst(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI14_0: ; CSKY-NEXT: .long __atomic_fetch_sub_1 - %1 = atomicrmw sub i8* %a, i8 %b seq_cst + %1 = atomicrmw sub ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -302,11 +302,11 @@ define i8 @atomicrmw_and_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI15_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b monotonic + %1 = atomicrmw and ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -321,11 +321,11 @@ define i8 @atomicrmw_and_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI16_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b acquire + %1 = atomicrmw and ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -340,11 +340,11 @@ define i8 @atomicrmw_and_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI17_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b release + %1 = atomicrmw and ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -359,11 +359,11 @@ define i8 @atomicrmw_and_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI18_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b acq_rel + %1 = atomicrmw and ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_and_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -378,11 +378,11 @@ define i8 @atomicrmw_and_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI19_0: ; CSKY-NEXT: .long __atomic_fetch_and_1 - %1 = atomicrmw and i8* %a, i8 %b seq_cst + %1 = atomicrmw and ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -397,11 +397,11 @@ define i8 @atomicrmw_nand_i8_monotonic(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI20_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b monotonic + %1 = atomicrmw nand ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -416,11 +416,11 @@ define i8 @atomicrmw_nand_i8_acquire(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI21_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b acquire + %1 = atomicrmw nand ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -435,11 +435,11 @@ define i8 @atomicrmw_nand_i8_release(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI22_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b release + %1 = atomicrmw nand ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -454,11 +454,11 @@ define i8 @atomicrmw_nand_i8_acq_rel(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI23_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b acq_rel + %1 = atomicrmw nand ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { +define i8 @atomicrmw_nand_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -473,11 +473,11 @@ define i8 @atomicrmw_nand_i8_seq_cst(i8* %a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI24_0: ; CSKY-NEXT: .long __atomic_fetch_nand_1 - %1 = atomicrmw nand i8* %a, i8 %b seq_cst + %1 = atomicrmw nand ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -492,11 +492,11 @@ define i8 @atomicrmw_or_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI25_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b monotonic + %1 = atomicrmw or ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -511,11 +511,11 @@ define i8 @atomicrmw_or_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI26_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b acquire + %1 = atomicrmw or ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -530,11 +530,11 @@ define i8 @atomicrmw_or_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI27_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b release + %1 = atomicrmw or ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -549,11 +549,11 @@ define i8 @atomicrmw_or_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI28_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b acq_rel + %1 = atomicrmw or ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_or_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -568,11 +568,11 @@ define i8 @atomicrmw_or_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI29_0: ; CSKY-NEXT: .long __atomic_fetch_or_1 - %1 = atomicrmw or i8* %a, i8 %b seq_cst + %1 = atomicrmw or ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -587,11 +587,11 @@ define i8 @atomicrmw_xor_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI30_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b monotonic + %1 = atomicrmw xor ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -606,11 +606,11 @@ define i8 @atomicrmw_xor_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI31_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b acquire + %1 = atomicrmw xor ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -625,11 +625,11 @@ define i8 @atomicrmw_xor_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI32_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b release + %1 = atomicrmw xor ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -644,11 +644,11 @@ define i8 @atomicrmw_xor_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI33_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b acq_rel + %1 = atomicrmw xor ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_xor_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -663,11 +663,11 @@ define i8 @atomicrmw_xor_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI34_0: ; CSKY-NEXT: .long __atomic_fetch_xor_1 - %1 = atomicrmw xor i8* %a, i8 %b seq_cst + %1 = atomicrmw xor ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -711,11 +711,11 @@ define i8 @atomicrmw_max_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI35_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b monotonic + %1 = atomicrmw max ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -759,11 +759,11 @@ define i8 @atomicrmw_max_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI36_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b acquire + %1 = atomicrmw max ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -807,11 +807,11 @@ define i8 @atomicrmw_max_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI37_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b release + %1 = atomicrmw max ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -855,11 +855,11 @@ define i8 @atomicrmw_max_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI38_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b acq_rel + %1 = atomicrmw max ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_max_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -903,11 +903,11 @@ define i8 @atomicrmw_max_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI39_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw max i8* %a, i8 %b seq_cst + %1 = atomicrmw max ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -951,11 +951,11 @@ define i8 @atomicrmw_min_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI40_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b monotonic + %1 = atomicrmw min ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -999,11 +999,11 @@ define i8 @atomicrmw_min_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI41_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b acquire + %1 = atomicrmw min ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1047,11 +1047,11 @@ define i8 @atomicrmw_min_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI42_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b release + %1 = atomicrmw min ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1095,11 +1095,11 @@ define i8 @atomicrmw_min_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI43_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b acq_rel + %1 = atomicrmw min ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_min_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1143,11 +1143,11 @@ define i8 @atomicrmw_min_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI44_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw min i8* %a, i8 %b seq_cst + %1 = atomicrmw min ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1191,11 +1191,11 @@ define i8 @atomicrmw_umax_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI45_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b monotonic + %1 = atomicrmw umax ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1239,11 +1239,11 @@ define i8 @atomicrmw_umax_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI46_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b acquire + %1 = atomicrmw umax ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1287,11 +1287,11 @@ define i8 @atomicrmw_umax_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI47_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b release + %1 = atomicrmw umax ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1335,11 +1335,11 @@ define i8 @atomicrmw_umax_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI48_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b acq_rel + %1 = atomicrmw umax ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umax_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1383,11 +1383,11 @@ define i8 @atomicrmw_umax_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI49_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umax i8* %a, i8 %b seq_cst + %1 = atomicrmw umax ptr %a, i8 %b seq_cst ret i8 %1 } -define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_monotonic(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1431,11 +1431,11 @@ define i8 @atomicrmw_umin_i8_monotonic(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI50_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b monotonic + %1 = atomicrmw umin ptr %a, i8 %b monotonic ret i8 %1 } -define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_acquire(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1479,11 +1479,11 @@ define i8 @atomicrmw_umin_i8_acquire(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI51_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b acquire + %1 = atomicrmw umin ptr %a, i8 %b acquire ret i8 %1 } -define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_release(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1527,11 +1527,11 @@ define i8 @atomicrmw_umin_i8_release(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI52_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b release + %1 = atomicrmw umin ptr %a, i8 %b release ret i8 %1 } -define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_acq_rel(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1575,11 +1575,11 @@ define i8 @atomicrmw_umin_i8_acq_rel(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI53_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b acq_rel + %1 = atomicrmw umin ptr %a, i8 %b acq_rel ret i8 %1 } -define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { +define i8 @atomicrmw_umin_i8_seq_cst(ptr %a, i8 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i8_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -1623,11 +1623,11 @@ define i8 @atomicrmw_umin_i8_seq_cst(i8 *%a, i8 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI54_0: ; CSKY-NEXT: .long __atomic_compare_exchange_1 - %1 = atomicrmw umin i8* %a, i8 %b seq_cst + %1 = atomicrmw umin ptr %a, i8 %b seq_cst ret i8 %1 } -define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1642,11 +1642,11 @@ define i16 @atomicrmw_xchg_i16_monotonic(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI55_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b monotonic + %1 = atomicrmw xchg ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1661,11 +1661,11 @@ define i16 @atomicrmw_xchg_i16_acquire(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI56_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b acquire + %1 = atomicrmw xchg ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1680,11 +1680,11 @@ define i16 @atomicrmw_xchg_i16_release(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI57_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b release + %1 = atomicrmw xchg ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1699,11 +1699,11 @@ define i16 @atomicrmw_xchg_i16_acq_rel(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI58_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b acq_rel + %1 = atomicrmw xchg ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_xchg_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1718,11 +1718,11 @@ define i16 @atomicrmw_xchg_i16_seq_cst(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI59_0: ; CSKY-NEXT: .long __atomic_exchange_2 - %1 = atomicrmw xchg i16* %a, i16 %b seq_cst + %1 = atomicrmw xchg ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1737,11 +1737,11 @@ define i16 @atomicrmw_add_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI60_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b monotonic + %1 = atomicrmw add ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1756,11 +1756,11 @@ define i16 @atomicrmw_add_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI61_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b acquire + %1 = atomicrmw add ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1775,11 +1775,11 @@ define i16 @atomicrmw_add_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI62_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b release + %1 = atomicrmw add ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1794,11 +1794,11 @@ define i16 @atomicrmw_add_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI63_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b acq_rel + %1 = atomicrmw add ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_add_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1813,11 +1813,11 @@ define i16 @atomicrmw_add_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI64_0: ; CSKY-NEXT: .long __atomic_fetch_add_2 - %1 = atomicrmw add i16* %a, i16 %b seq_cst + %1 = atomicrmw add ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1832,11 +1832,11 @@ define i16 @atomicrmw_sub_i16_monotonic(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI65_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b monotonic + %1 = atomicrmw sub ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1851,11 +1851,11 @@ define i16 @atomicrmw_sub_i16_acquire(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI66_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b acquire + %1 = atomicrmw sub ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1870,11 +1870,11 @@ define i16 @atomicrmw_sub_i16_release(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI67_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b release + %1 = atomicrmw sub ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1889,11 +1889,11 @@ define i16 @atomicrmw_sub_i16_acq_rel(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI68_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b acq_rel + %1 = atomicrmw sub ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_sub_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1908,11 +1908,11 @@ define i16 @atomicrmw_sub_i16_seq_cst(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI69_0: ; CSKY-NEXT: .long __atomic_fetch_sub_2 - %1 = atomicrmw sub i16* %a, i16 %b seq_cst + %1 = atomicrmw sub ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1927,11 +1927,11 @@ define i16 @atomicrmw_and_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI70_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b monotonic + %1 = atomicrmw and ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1946,11 +1946,11 @@ define i16 @atomicrmw_and_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI71_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b acquire + %1 = atomicrmw and ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1965,11 +1965,11 @@ define i16 @atomicrmw_and_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI72_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b release + %1 = atomicrmw and ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -1984,11 +1984,11 @@ define i16 @atomicrmw_and_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI73_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b acq_rel + %1 = atomicrmw and ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_and_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2003,11 +2003,11 @@ define i16 @atomicrmw_and_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI74_0: ; CSKY-NEXT: .long __atomic_fetch_and_2 - %1 = atomicrmw and i16* %a, i16 %b seq_cst + %1 = atomicrmw and ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2022,11 +2022,11 @@ define i16 @atomicrmw_nand_i16_monotonic(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI75_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b monotonic + %1 = atomicrmw nand ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2041,11 +2041,11 @@ define i16 @atomicrmw_nand_i16_acquire(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI76_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b acquire + %1 = atomicrmw nand ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2060,11 +2060,11 @@ define i16 @atomicrmw_nand_i16_release(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI77_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b release + %1 = atomicrmw nand ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2079,11 +2079,11 @@ define i16 @atomicrmw_nand_i16_acq_rel(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI78_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b acq_rel + %1 = atomicrmw nand ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { +define i16 @atomicrmw_nand_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2098,11 +2098,11 @@ define i16 @atomicrmw_nand_i16_seq_cst(i16* %a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI79_0: ; CSKY-NEXT: .long __atomic_fetch_nand_2 - %1 = atomicrmw nand i16* %a, i16 %b seq_cst + %1 = atomicrmw nand ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2117,11 +2117,11 @@ define i16 @atomicrmw_or_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI80_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b monotonic + %1 = atomicrmw or ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2136,11 +2136,11 @@ define i16 @atomicrmw_or_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI81_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b acquire + %1 = atomicrmw or ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2155,11 +2155,11 @@ define i16 @atomicrmw_or_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI82_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b release + %1 = atomicrmw or ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2174,11 +2174,11 @@ define i16 @atomicrmw_or_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI83_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b acq_rel + %1 = atomicrmw or ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_or_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2193,11 +2193,11 @@ define i16 @atomicrmw_or_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI84_0: ; CSKY-NEXT: .long __atomic_fetch_or_2 - %1 = atomicrmw or i16* %a, i16 %b seq_cst + %1 = atomicrmw or ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2212,11 +2212,11 @@ define i16 @atomicrmw_xor_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI85_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b monotonic + %1 = atomicrmw xor ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2231,11 +2231,11 @@ define i16 @atomicrmw_xor_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI86_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b acquire + %1 = atomicrmw xor ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2250,11 +2250,11 @@ define i16 @atomicrmw_xor_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI87_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b release + %1 = atomicrmw xor ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2269,11 +2269,11 @@ define i16 @atomicrmw_xor_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI88_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b acq_rel + %1 = atomicrmw xor ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_xor_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -2288,11 +2288,11 @@ define i16 @atomicrmw_xor_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI89_0: ; CSKY-NEXT: .long __atomic_fetch_xor_2 - %1 = atomicrmw xor i16* %a, i16 %b seq_cst + %1 = atomicrmw xor ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2336,11 +2336,11 @@ define i16 @atomicrmw_max_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI90_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b monotonic + %1 = atomicrmw max ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2384,11 +2384,11 @@ define i16 @atomicrmw_max_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI91_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b acquire + %1 = atomicrmw max ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2432,11 +2432,11 @@ define i16 @atomicrmw_max_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI92_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b release + %1 = atomicrmw max ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2480,11 +2480,11 @@ define i16 @atomicrmw_max_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI93_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b acq_rel + %1 = atomicrmw max ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_max_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2528,11 +2528,11 @@ define i16 @atomicrmw_max_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI94_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw max i16* %a, i16 %b seq_cst + %1 = atomicrmw max ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2576,11 +2576,11 @@ define i16 @atomicrmw_min_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI95_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b monotonic + %1 = atomicrmw min ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2624,11 +2624,11 @@ define i16 @atomicrmw_min_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI96_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b acquire + %1 = atomicrmw min ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2672,11 +2672,11 @@ define i16 @atomicrmw_min_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI97_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b release + %1 = atomicrmw min ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2720,11 +2720,11 @@ define i16 @atomicrmw_min_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI98_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b acq_rel + %1 = atomicrmw min ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_min_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2768,11 +2768,11 @@ define i16 @atomicrmw_min_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI99_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw min i16* %a, i16 %b seq_cst + %1 = atomicrmw min ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2816,11 +2816,11 @@ define i16 @atomicrmw_umax_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI100_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b monotonic + %1 = atomicrmw umax ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2864,11 +2864,11 @@ define i16 @atomicrmw_umax_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI101_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b acquire + %1 = atomicrmw umax ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2912,11 +2912,11 @@ define i16 @atomicrmw_umax_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI102_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b release + %1 = atomicrmw umax ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -2960,11 +2960,11 @@ define i16 @atomicrmw_umax_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI103_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b acq_rel + %1 = atomicrmw umax ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umax_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3008,11 +3008,11 @@ define i16 @atomicrmw_umax_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI104_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umax i16* %a, i16 %b seq_cst + %1 = atomicrmw umax ptr %a, i16 %b seq_cst ret i16 %1 } -define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_monotonic(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3056,11 +3056,11 @@ define i16 @atomicrmw_umin_i16_monotonic(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI105_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b monotonic + %1 = atomicrmw umin ptr %a, i16 %b monotonic ret i16 %1 } -define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_acquire(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3104,11 +3104,11 @@ define i16 @atomicrmw_umin_i16_acquire(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI106_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b acquire + %1 = atomicrmw umin ptr %a, i16 %b acquire ret i16 %1 } -define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_release(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3152,11 +3152,11 @@ define i16 @atomicrmw_umin_i16_release(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI107_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b release + %1 = atomicrmw umin ptr %a, i16 %b release ret i16 %1 } -define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_acq_rel(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3200,11 +3200,11 @@ define i16 @atomicrmw_umin_i16_acq_rel(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI108_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b acq_rel + %1 = atomicrmw umin ptr %a, i16 %b acq_rel ret i16 %1 } -define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { +define i16 @atomicrmw_umin_i16_seq_cst(ptr %a, i16 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i16_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -3248,11 +3248,11 @@ define i16 @atomicrmw_umin_i16_seq_cst(i16 *%a, i16 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI109_0: ; CSKY-NEXT: .long __atomic_compare_exchange_2 - %1 = atomicrmw umin i16* %a, i16 %b seq_cst + %1 = atomicrmw umin ptr %a, i16 %b seq_cst ret i16 %1 } -define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3267,11 +3267,11 @@ define i32 @atomicrmw_xchg_i32_monotonic(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI110_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b monotonic + %1 = atomicrmw xchg ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3286,11 +3286,11 @@ define i32 @atomicrmw_xchg_i32_acquire(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI111_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b acquire + %1 = atomicrmw xchg ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3305,11 +3305,11 @@ define i32 @atomicrmw_xchg_i32_release(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI112_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b release + %1 = atomicrmw xchg ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3324,11 +3324,11 @@ define i32 @atomicrmw_xchg_i32_acq_rel(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI113_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b acq_rel + %1 = atomicrmw xchg ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_xchg_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3343,11 +3343,11 @@ define i32 @atomicrmw_xchg_i32_seq_cst(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI114_0: ; CSKY-NEXT: .long __atomic_exchange_4 - %1 = atomicrmw xchg i32* %a, i32 %b seq_cst + %1 = atomicrmw xchg ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3362,11 +3362,11 @@ define i32 @atomicrmw_add_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI115_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b monotonic + %1 = atomicrmw add ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3381,11 +3381,11 @@ define i32 @atomicrmw_add_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI116_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b acquire + %1 = atomicrmw add ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3400,11 +3400,11 @@ define i32 @atomicrmw_add_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI117_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b release + %1 = atomicrmw add ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3419,11 +3419,11 @@ define i32 @atomicrmw_add_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI118_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b acq_rel + %1 = atomicrmw add ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_add_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3438,11 +3438,11 @@ define i32 @atomicrmw_add_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI119_0: ; CSKY-NEXT: .long __atomic_fetch_add_4 - %1 = atomicrmw add i32* %a, i32 %b seq_cst + %1 = atomicrmw add ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3457,11 +3457,11 @@ define i32 @atomicrmw_sub_i32_monotonic(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI120_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b monotonic + %1 = atomicrmw sub ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3476,11 +3476,11 @@ define i32 @atomicrmw_sub_i32_acquire(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI121_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b acquire + %1 = atomicrmw sub ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3495,11 +3495,11 @@ define i32 @atomicrmw_sub_i32_release(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI122_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b release + %1 = atomicrmw sub ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3514,11 +3514,11 @@ define i32 @atomicrmw_sub_i32_acq_rel(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI123_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b acq_rel + %1 = atomicrmw sub ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_sub_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3533,11 +3533,11 @@ define i32 @atomicrmw_sub_i32_seq_cst(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI124_0: ; CSKY-NEXT: .long __atomic_fetch_sub_4 - %1 = atomicrmw sub i32* %a, i32 %b seq_cst + %1 = atomicrmw sub ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3552,11 +3552,11 @@ define i32 @atomicrmw_and_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI125_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b monotonic + %1 = atomicrmw and ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3571,11 +3571,11 @@ define i32 @atomicrmw_and_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI126_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b acquire + %1 = atomicrmw and ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3590,11 +3590,11 @@ define i32 @atomicrmw_and_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI127_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b release + %1 = atomicrmw and ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3609,11 +3609,11 @@ define i32 @atomicrmw_and_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI128_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b acq_rel + %1 = atomicrmw and ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_and_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3628,11 +3628,11 @@ define i32 @atomicrmw_and_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI129_0: ; CSKY-NEXT: .long __atomic_fetch_and_4 - %1 = atomicrmw and i32* %a, i32 %b seq_cst + %1 = atomicrmw and ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3647,11 +3647,11 @@ define i32 @atomicrmw_nand_i32_monotonic(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI130_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b monotonic + %1 = atomicrmw nand ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3666,11 +3666,11 @@ define i32 @atomicrmw_nand_i32_acquire(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI131_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b acquire + %1 = atomicrmw nand ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3685,11 +3685,11 @@ define i32 @atomicrmw_nand_i32_release(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI132_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b release + %1 = atomicrmw nand ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3704,11 +3704,11 @@ define i32 @atomicrmw_nand_i32_acq_rel(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI133_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b acq_rel + %1 = atomicrmw nand ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { +define i32 @atomicrmw_nand_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3723,11 +3723,11 @@ define i32 @atomicrmw_nand_i32_seq_cst(i32* %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI134_0: ; CSKY-NEXT: .long __atomic_fetch_nand_4 - %1 = atomicrmw nand i32* %a, i32 %b seq_cst + %1 = atomicrmw nand ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3742,11 +3742,11 @@ define i32 @atomicrmw_or_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI135_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b monotonic + %1 = atomicrmw or ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3761,11 +3761,11 @@ define i32 @atomicrmw_or_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI136_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b acquire + %1 = atomicrmw or ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3780,11 +3780,11 @@ define i32 @atomicrmw_or_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI137_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b release + %1 = atomicrmw or ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3799,11 +3799,11 @@ define i32 @atomicrmw_or_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI138_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b acq_rel + %1 = atomicrmw or ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_or_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3818,11 +3818,11 @@ define i32 @atomicrmw_or_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI139_0: ; CSKY-NEXT: .long __atomic_fetch_or_4 - %1 = atomicrmw or i32* %a, i32 %b seq_cst + %1 = atomicrmw or ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3837,11 +3837,11 @@ define i32 @atomicrmw_xor_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI140_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b monotonic + %1 = atomicrmw xor ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3856,11 +3856,11 @@ define i32 @atomicrmw_xor_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI141_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b acquire + %1 = atomicrmw xor ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3875,11 +3875,11 @@ define i32 @atomicrmw_xor_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI142_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b release + %1 = atomicrmw xor ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3894,11 +3894,11 @@ define i32 @atomicrmw_xor_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI143_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b acq_rel + %1 = atomicrmw xor ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_xor_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -3913,11 +3913,11 @@ define i32 @atomicrmw_xor_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI144_0: ; CSKY-NEXT: .long __atomic_fetch_xor_4 - %1 = atomicrmw xor i32* %a, i32 %b seq_cst + %1 = atomicrmw xor ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -3957,11 +3957,11 @@ define i32 @atomicrmw_max_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI145_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b monotonic + %1 = atomicrmw max ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4001,11 +4001,11 @@ define i32 @atomicrmw_max_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI146_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b acquire + %1 = atomicrmw max ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4045,11 +4045,11 @@ define i32 @atomicrmw_max_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI147_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b release + %1 = atomicrmw max ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4089,11 +4089,11 @@ define i32 @atomicrmw_max_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI148_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b acq_rel + %1 = atomicrmw max ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_max_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4133,11 +4133,11 @@ define i32 @atomicrmw_max_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI149_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw max i32* %a, i32 %b seq_cst + %1 = atomicrmw max ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4177,11 +4177,11 @@ define i32 @atomicrmw_min_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI150_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b monotonic + %1 = atomicrmw min ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4221,11 +4221,11 @@ define i32 @atomicrmw_min_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI151_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b acquire + %1 = atomicrmw min ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4265,11 +4265,11 @@ define i32 @atomicrmw_min_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI152_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b release + %1 = atomicrmw min ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4309,11 +4309,11 @@ define i32 @atomicrmw_min_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI153_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b acq_rel + %1 = atomicrmw min ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_min_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4353,11 +4353,11 @@ define i32 @atomicrmw_min_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI154_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw min i32* %a, i32 %b seq_cst + %1 = atomicrmw min ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4397,11 +4397,11 @@ define i32 @atomicrmw_umax_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI155_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b monotonic + %1 = atomicrmw umax ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4441,11 +4441,11 @@ define i32 @atomicrmw_umax_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI156_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b acquire + %1 = atomicrmw umax ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4485,11 +4485,11 @@ define i32 @atomicrmw_umax_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI157_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b release + %1 = atomicrmw umax ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4529,11 +4529,11 @@ define i32 @atomicrmw_umax_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI158_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b acq_rel + %1 = atomicrmw umax ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umax_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4573,11 +4573,11 @@ define i32 @atomicrmw_umax_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI159_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umax i32* %a, i32 %b seq_cst + %1 = atomicrmw umax ptr %a, i32 %b seq_cst ret i32 %1 } -define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_monotonic(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4617,11 +4617,11 @@ define i32 @atomicrmw_umin_i32_monotonic(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI160_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b monotonic + %1 = atomicrmw umin ptr %a, i32 %b monotonic ret i32 %1 } -define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_acquire(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4661,11 +4661,11 @@ define i32 @atomicrmw_umin_i32_acquire(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI161_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b acquire + %1 = atomicrmw umin ptr %a, i32 %b acquire ret i32 %1 } -define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_release(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4705,11 +4705,11 @@ define i32 @atomicrmw_umin_i32_release(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI162_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b release + %1 = atomicrmw umin ptr %a, i32 %b release ret i32 %1 } -define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_acq_rel(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4749,11 +4749,11 @@ define i32 @atomicrmw_umin_i32_acq_rel(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI163_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b acq_rel + %1 = atomicrmw umin ptr %a, i32 %b acq_rel ret i32 %1 } -define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { +define i32 @atomicrmw_umin_i32_seq_cst(ptr %a, i32 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i32_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 16 @@ -4793,11 +4793,11 @@ define i32 @atomicrmw_umin_i32_seq_cst(i32 *%a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI164_0: ; CSKY-NEXT: .long __atomic_compare_exchange_4 - %1 = atomicrmw umin i32* %a, i32 %b seq_cst + %1 = atomicrmw umin ptr %a, i32 %b seq_cst ret i32 %1 } -define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4812,11 +4812,11 @@ define i64 @atomicrmw_xchg_i64_monotonic(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI165_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b monotonic + %1 = atomicrmw xchg ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4831,11 +4831,11 @@ define i64 @atomicrmw_xchg_i64_acquire(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI166_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b acquire + %1 = atomicrmw xchg ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4850,11 +4850,11 @@ define i64 @atomicrmw_xchg_i64_release(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI167_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b release + %1 = atomicrmw xchg ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4869,11 +4869,11 @@ define i64 @atomicrmw_xchg_i64_acq_rel(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI168_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b acq_rel + %1 = atomicrmw xchg ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_xchg_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xchg_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4888,11 +4888,11 @@ define i64 @atomicrmw_xchg_i64_seq_cst(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI169_0: ; CSKY-NEXT: .long __atomic_exchange_8 - %1 = atomicrmw xchg i64* %a, i64 %b seq_cst + %1 = atomicrmw xchg ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4907,11 +4907,11 @@ define i64 @atomicrmw_add_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI170_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b monotonic + %1 = atomicrmw add ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4926,11 +4926,11 @@ define i64 @atomicrmw_add_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI171_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b acquire + %1 = atomicrmw add ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4945,11 +4945,11 @@ define i64 @atomicrmw_add_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI172_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b release + %1 = atomicrmw add ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4964,11 +4964,11 @@ define i64 @atomicrmw_add_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI173_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b acq_rel + %1 = atomicrmw add ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_add_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_add_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -4983,11 +4983,11 @@ define i64 @atomicrmw_add_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI174_0: ; CSKY-NEXT: .long __atomic_fetch_add_8 - %1 = atomicrmw add i64* %a, i64 %b seq_cst + %1 = atomicrmw add ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5002,11 +5002,11 @@ define i64 @atomicrmw_sub_i64_monotonic(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI175_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b monotonic + %1 = atomicrmw sub ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5021,11 +5021,11 @@ define i64 @atomicrmw_sub_i64_acquire(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI176_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b acquire + %1 = atomicrmw sub ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5040,11 +5040,11 @@ define i64 @atomicrmw_sub_i64_release(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI177_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b release + %1 = atomicrmw sub ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5059,11 +5059,11 @@ define i64 @atomicrmw_sub_i64_acq_rel(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI178_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b acq_rel + %1 = atomicrmw sub ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_sub_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_sub_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5078,11 +5078,11 @@ define i64 @atomicrmw_sub_i64_seq_cst(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI179_0: ; CSKY-NEXT: .long __atomic_fetch_sub_8 - %1 = atomicrmw sub i64* %a, i64 %b seq_cst + %1 = atomicrmw sub ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5097,11 +5097,11 @@ define i64 @atomicrmw_and_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI180_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b monotonic + %1 = atomicrmw and ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5116,11 +5116,11 @@ define i64 @atomicrmw_and_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI181_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b acquire + %1 = atomicrmw and ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5135,11 +5135,11 @@ define i64 @atomicrmw_and_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI182_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b release + %1 = atomicrmw and ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5154,11 +5154,11 @@ define i64 @atomicrmw_and_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI183_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b acq_rel + %1 = atomicrmw and ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_and_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_and_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5173,11 +5173,11 @@ define i64 @atomicrmw_and_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI184_0: ; CSKY-NEXT: .long __atomic_fetch_and_8 - %1 = atomicrmw and i64* %a, i64 %b seq_cst + %1 = atomicrmw and ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5192,11 +5192,11 @@ define i64 @atomicrmw_nand_i64_monotonic(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI185_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b monotonic + %1 = atomicrmw nand ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5211,11 +5211,11 @@ define i64 @atomicrmw_nand_i64_acquire(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI186_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b acquire + %1 = atomicrmw nand ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5230,11 +5230,11 @@ define i64 @atomicrmw_nand_i64_release(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI187_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b release + %1 = atomicrmw nand ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5249,11 +5249,11 @@ define i64 @atomicrmw_nand_i64_acq_rel(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI188_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b acq_rel + %1 = atomicrmw nand ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { +define i64 @atomicrmw_nand_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_nand_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5268,11 +5268,11 @@ define i64 @atomicrmw_nand_i64_seq_cst(i64* %a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI189_0: ; CSKY-NEXT: .long __atomic_fetch_nand_8 - %1 = atomicrmw nand i64* %a, i64 %b seq_cst + %1 = atomicrmw nand ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5287,11 +5287,11 @@ define i64 @atomicrmw_or_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI190_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b monotonic + %1 = atomicrmw or ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5306,11 +5306,11 @@ define i64 @atomicrmw_or_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI191_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b acquire + %1 = atomicrmw or ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5325,11 +5325,11 @@ define i64 @atomicrmw_or_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI192_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b release + %1 = atomicrmw or ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5344,11 +5344,11 @@ define i64 @atomicrmw_or_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI193_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b acq_rel + %1 = atomicrmw or ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_or_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_or_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5363,11 +5363,11 @@ define i64 @atomicrmw_or_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI194_0: ; CSKY-NEXT: .long __atomic_fetch_or_8 - %1 = atomicrmw or i64* %a, i64 %b seq_cst + %1 = atomicrmw or ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5382,11 +5382,11 @@ define i64 @atomicrmw_xor_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI195_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b monotonic + %1 = atomicrmw xor ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5401,11 +5401,11 @@ define i64 @atomicrmw_xor_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI196_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b acquire + %1 = atomicrmw xor ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5420,11 +5420,11 @@ define i64 @atomicrmw_xor_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI197_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b release + %1 = atomicrmw xor ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5439,11 +5439,11 @@ define i64 @atomicrmw_xor_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI198_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b acq_rel + %1 = atomicrmw xor ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_xor_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_xor_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -5458,11 +5458,11 @@ define i64 @atomicrmw_xor_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI199_0: ; CSKY-NEXT: .long __atomic_fetch_xor_8 - %1 = atomicrmw xor i64* %a, i64 %b seq_cst + %1 = atomicrmw xor ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5524,11 +5524,11 @@ define i64 @atomicrmw_max_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI200_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b monotonic + %1 = atomicrmw max ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5590,11 +5590,11 @@ define i64 @atomicrmw_max_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI201_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b acquire + %1 = atomicrmw max ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -5659,11 +5659,11 @@ define i64 @atomicrmw_max_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI202_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b release + %1 = atomicrmw max ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -5728,11 +5728,11 @@ define i64 @atomicrmw_max_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI203_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b acq_rel + %1 = atomicrmw max ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_max_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_max_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5794,11 +5794,11 @@ define i64 @atomicrmw_max_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI204_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw max i64* %a, i64 %b seq_cst + %1 = atomicrmw max ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5860,11 +5860,11 @@ define i64 @atomicrmw_min_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI205_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b monotonic + %1 = atomicrmw min ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -5926,11 +5926,11 @@ define i64 @atomicrmw_min_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI206_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b acquire + %1 = atomicrmw min ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -5995,11 +5995,11 @@ define i64 @atomicrmw_min_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI207_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b release + %1 = atomicrmw min ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6064,11 +6064,11 @@ define i64 @atomicrmw_min_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI208_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b acq_rel + %1 = atomicrmw min ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_min_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_min_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6130,11 +6130,11 @@ define i64 @atomicrmw_min_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI209_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw min i64* %a, i64 %b seq_cst + %1 = atomicrmw min ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6192,11 +6192,11 @@ define i64 @atomicrmw_umax_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI210_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b monotonic + %1 = atomicrmw umax ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6254,11 +6254,11 @@ define i64 @atomicrmw_umax_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI211_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b acquire + %1 = atomicrmw umax ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6319,11 +6319,11 @@ define i64 @atomicrmw_umax_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI212_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b release + %1 = atomicrmw umax ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6384,11 +6384,11 @@ define i64 @atomicrmw_umax_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI213_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b acq_rel + %1 = atomicrmw umax ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umax_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umax_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6446,11 +6446,11 @@ define i64 @atomicrmw_umax_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI214_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umax i64* %a, i64 %b seq_cst + %1 = atomicrmw umax ptr %a, i64 %b seq_cst ret i64 %1 } -define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_monotonic(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_monotonic: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6516,11 +6516,11 @@ define i64 @atomicrmw_umin_i64_monotonic(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI215_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b monotonic + %1 = atomicrmw umin ptr %a, i64 %b monotonic ret i64 %1 } -define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_acquire(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_acquire: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6586,11 +6586,11 @@ define i64 @atomicrmw_umin_i64_acquire(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI216_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b acquire + %1 = atomicrmw umin ptr %a, i64 %b acquire ret i64 %1 } -define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_release(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_release: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6659,11 +6659,11 @@ define i64 @atomicrmw_umin_i64_release(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI217_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b release + %1 = atomicrmw umin ptr %a, i64 %b release ret i64 %1 } -define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_acq_rel(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_acq_rel: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 24 @@ -6732,11 +6732,11 @@ define i64 @atomicrmw_umin_i64_acq_rel(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI218_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b acq_rel + %1 = atomicrmw umin ptr %a, i64 %b acq_rel ret i64 %1 } -define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { +define i64 @atomicrmw_umin_i64_seq_cst(ptr %a, i64 %b) nounwind { ; CSKY-LABEL: atomicrmw_umin_i64_seq_cst: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 20 @@ -6802,6 +6802,6 @@ define i64 @atomicrmw_umin_i64_seq_cst(i64 *%a, i64 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI219_0: ; CSKY-NEXT: .long __atomic_compare_exchange_8 - %1 = atomicrmw umin i64* %a, i64 %b seq_cst + %1 = atomicrmw umin ptr %a, i64 %b seq_cst ret i64 %1 } diff --git a/llvm/test/CodeGen/CSKY/call-16bit.ll b/llvm/test/CodeGen/CSKY/call-16bit.ll index e7f169a9df12090fb1ef2387c2c988bb658302d7..f30c0285985c3da6d7ad352b969bbd9db6a95cbd 100644 --- a/llvm/test/CodeGen/CSKY/call-16bit.ll +++ b/llvm/test/CodeGen/CSKY/call-16bit.ll @@ -1,11 +1,11 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s -@p_fun = global void (i32, i32)* @bar, align 8 +@p_fun = global ptr @bar, align 8 declare void @bar(i32, i32) -define void @foo(i32 %a, i32* %ptr){ +define void @foo(i32 %a, ptr %ptr){ ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -28,12 +28,12 @@ define void @foo(i32 %a, i32* %ptr){ ; CHECK-NEXT: .long bar ; entry: - %0 = load i32, i32* %ptr + %0 = load i32, ptr %ptr tail call void (i32, i32) @bar(i32 %a, i32 %0) ret void } -define void @foo_indirect(i32 %a, i32* %ptr) { +define void @foo_indirect(i32 %a, ptr %ptr) { ; CHECK-LABEL: foo_indirect: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -57,8 +57,8 @@ define void @foo_indirect(i32 %a, i32* %ptr) { ; CHECK-NEXT: .long p_fun ; entry: - %0 = load void (i32, i32)*, void (i32, i32)** @p_fun, align 8 - %1 = load i32, i32* %ptr + %0 = load ptr, ptr @p_fun, align 8 + %1 = load i32, ptr %ptr tail call void (i32, i32) %0(i32 %a, i32 %1) ret void } diff --git a/llvm/test/CodeGen/CSKY/call.ll b/llvm/test/CodeGen/CSKY/call.ll index 8804756802fc92629e0509fea72e79db0c9d9caf..c6621c9da964ee68c7688b5195095da0b61bf55f 100644 --- a/llvm/test/CodeGen/CSKY/call.ll +++ b/llvm/test/CodeGen/CSKY/call.ll @@ -3,11 +3,11 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=small -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-SMALL ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=large -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-LARGE -@p_fun = global void (i32, i32)* @bar, align 8 +@p_fun = global ptr @bar, align 8 declare void @bar(i32, i32) -define void @foo(i32 %a, i32* %ptr){ +define void @foo(i32 %a, ptr %ptr){ ; CHECK-LABEL: foo: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -63,12 +63,12 @@ define void @foo(i32 %a, i32* %ptr){ ; CHECK-PIC-NEXT: ld32.w a1, a1, 0 ; CHECK-PIC-NEXT: br32 bar entry: - %0 = load i32, i32* %ptr + %0 = load i32, ptr %ptr tail call void (i32, i32) @bar(i32 %a, i32 %0) ret void } -define void @foo_indirect(i32 %a, i32* %ptr) { +define void @foo_indirect(i32 %a, ptr %ptr) { ; CHECK-LABEL: foo_indirect: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: subi16 sp, sp, 4 @@ -132,8 +132,8 @@ define void @foo_indirect(i32 %a, i32* %ptr) { ; CHECK-PIC-NEXT: ld32.w a1, a1, 0 ; CHECK-PIC-NEXT: jmp32 a2 entry: - %0 = load void (i32, i32)*, void (i32, i32)** @p_fun, align 8 - %1 = load i32, i32* %ptr + %0 = load ptr, ptr @p_fun, align 8 + %1 = load i32, ptr %ptr tail call void (i32, i32) %0(i32 %a, i32 %1) ret void } diff --git a/llvm/test/CodeGen/CSKY/constantpool.ll b/llvm/test/CodeGen/CSKY/constantpool.ll index d7741f2e1a1bbe81cb14f3810c1ce4281c89bb8d..b333968e9a438fde4eef5151eebff3d1628a1099 100644 --- a/llvm/test/CodeGen/CSKY/constantpool.ll +++ b/llvm/test/CodeGen/CSKY/constantpool.ll @@ -4,7 +4,7 @@ declare i32 @llvm.cttz.i32(i32, i1) -define void @cttztest(i32 %C, i32* %CP) { +define void @cttztest(i32 %C, ptr %CP) { ; GENERIC-LABEL: cttztest: ; GENERIC: # %bb.0: ; GENERIC-NEXT: .cfi_def_cfa_offset 0 @@ -39,6 +39,6 @@ define void @cttztest(i32 %C, i32* %CP) { ; GENERIC-NEXT: .LCPI0_0: ; GENERIC-NEXT: .ascii "\000\001\034\002\035\016\030\003\036\026\024\017\031\021\004\b\037\033\r\027\025\023\020\007\032\f\022\006\013\005\n\t" %c = call i32 @llvm.cttz.i32( i32 %C, i1 true ) - store i32 %c, i32* %CP + store i32 %c, ptr %CP ret void } diff --git a/llvm/test/CodeGen/CSKY/dwarf-eh.ll b/llvm/test/CodeGen/CSKY/dwarf-eh.ll index 706db07c3036ceb2eb046362a9e3a07d0e6371d7..c38b894d53a1be3c8007d8a808d2ca8cb12cea36 100644 --- a/llvm/test/CodeGen/CSKY/dwarf-eh.ll +++ b/llvm/test/CodeGen/CSKY/dwarf-eh.ll @@ -12,7 +12,7 @@ declare void @throw_exception() declare i32 @__gxx_personality_v0(...) -declare i8* @__cxa_begin_catch(i8*) +declare ptr @__cxa_begin_catch(ptr) declare void @__cxa_end_catch() @@ -22,7 +22,7 @@ declare void @__cxa_end_catch() ; LSDAEncoding = DW_EH_PE_pcrel | DW_EH_PE_sdata4 ; CHECK-NEXT: .cfi_lsda 27, .Lexception0 -define void @test1() personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { +define void @test1() personality ptr @__gxx_personality_v0 { ; SMALL: # %bb.0: # %entry ; SMALL-NEXT: subi16 sp, sp, 4 ; SMALL-NEXT: .cfi_def_cfa_offset 4 @@ -162,10 +162,10 @@ entry: invoke void @throw_exception() to label %try.cont unwind label %lpad lpad: - %0 = landingpad { i8*, i32 } - catch i8* null - %1 = extractvalue { i8*, i32 } %0, 0 - %2 = tail call i8* @__cxa_begin_catch(i8* %1) + %0 = landingpad { ptr, i32 } + catch ptr null + %1 = extractvalue { ptr, i32 } %0, 0 + %2 = tail call ptr @__cxa_begin_catch(ptr %1) tail call void @__cxa_end_catch() br label %try.cont diff --git a/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll b/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll index e31fd409d277507b6bb935cd5c120e9504b5d26a..612cecb2b4d7a56c25be4a48fe612ad2be74d8f3 100644 --- a/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll +++ b/llvm/test/CodeGen/CSKY/fpu/ldst-d.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf -mattr=+fpuv2_df | FileCheck %s --check-prefix=CHECK-DF ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf -mattr=+fpuv3_df | FileCheck %s --check-prefix=CHECK-DF2 -define double @load_I_d(double* nocapture readonly %a) local_unnamed_addr #0 { +define double @load_I_d(ptr nocapture readonly %a) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: load_I_d: @@ -16,14 +16,14 @@ define double @load_I_d(double* nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-DF2-NEXT: fld.64 vr0, (a0, 24) ; CHECK-DF2-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds double, double* %a, i64 3 - %0 = load double, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 3 + %0 = load double, ptr %arrayidx, align 4 ret double %0 } -define double @load_R_d(double* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define double @load_R_d(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: load_R_d: @@ -37,12 +37,12 @@ define double @load_R_d(double* nocapture readonly %a, i32 %b) local_unnamed_add ; CHECK-DF2-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom - %0 = load double, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 %idxprom + %0 = load double, ptr %arrayidx, align 4 ret double %0 } -define double @store_I_d(double* %a, double %b) local_unnamed_addr #0 { +define double @store_I_d(ptr %a, double %b) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: store_I_d: @@ -68,12 +68,12 @@ define double @store_I_d(double* %a, double %b) local_unnamed_addr #0 { ; CHECK-DF2-NEXT: .LCPI2_0: ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: - %arrayidx = getelementptr inbounds double, double* %a, i64 3 - store double %b, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 3 + store double %b, ptr %arrayidx, align 4 ret double 0.0 } -define double @store_R_d(double* %a, i32 %b, double %c) local_unnamed_addr #0 { +define double @store_R_d(ptr %a, i32 %b, double %c) local_unnamed_addr #0 { ; ; ; CHECK-DF-LABEL: store_R_d: @@ -100,7 +100,7 @@ define double @store_R_d(double* %a, i32 %b, double %c) local_unnamed_addr #0 { ; CHECK-DF2-NEXT: .quad 0x0000000000000000 # double 0 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds double, double* %a, i64 %idxprom - store double %c, double* %arrayidx, align 4 + %arrayidx = getelementptr inbounds double, ptr %a, i64 %idxprom + store double %c, ptr %arrayidx, align 4 ret double 0.0 } diff --git a/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll b/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll index bbcde8e6430a9df854e2805cfb7e517750dcf1ad..e22541fb37989bd165d6158be5e38c0f9437a49e 100644 --- a/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll +++ b/llvm/test/CodeGen/CSKY/fpu/ldst-f.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv2_sf | FileCheck %s --check-prefix=CHECK-SF ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -float-abi=hard -mattr=+hard-float -mattr=+2e3 -mattr=+fpuv3_sf | FileCheck %s --check-prefix=CHECK-SF2 -define float @load_I_w(float* nocapture readonly %a) local_unnamed_addr #0 { +define float @load_I_w(ptr nocapture readonly %a) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: load_I_w: ; CHECK-SF: # %bb.0: # %entry @@ -15,12 +15,12 @@ define float @load_I_w(float* nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-SF2-NEXT: fld.32 vr0, (a0, 12) ; CHECK-SF2-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds float, float* %a, i64 3 - %0 = load float, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 3 + %0 = load float, ptr %arrayidx, align 4 ret float %0 } -define float @load_R_w(float* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define float @load_R_w(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: load_R_w: ; CHECK-SF: # %bb.0: # %entry @@ -33,13 +33,13 @@ define float @load_R_w(float* nocapture readonly %a, i32 %b) local_unnamed_addr ; CHECK-SF2-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom - %0 = load float, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 %idxprom + %0 = load float, ptr %arrayidx, align 4 ret float %0 } -define float @store_I_w(float* %a, float %b) local_unnamed_addr #0 { +define float @store_I_w(ptr %a, float %b) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: store_I_w: ; CHECK-SF: # %bb.0: # %entry @@ -55,12 +55,12 @@ define float @store_I_w(float* %a, float %b) local_unnamed_addr #0 { ; CHECK-SF2-NEXT: fmtvr.32.1 vr0, a0 ; CHECK-SF2-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds float, float* %a, i64 3 - store float %b, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 3 + store float %b, ptr %arrayidx, align 4 ret float 0.0 } -define float @store_R_w(float* %a, i32 %b, float %c) local_unnamed_addr #0 { +define float @store_R_w(ptr %a, i32 %b, float %c) local_unnamed_addr #0 { ; ; CHECK-SF-LABEL: store_R_w: ; CHECK-SF: # %bb.0: # %entry @@ -77,7 +77,7 @@ define float @store_R_w(float* %a, i32 %b, float %c) local_unnamed_addr #0 { ; CHECK-SF2-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds float, float* %a, i64 %idxprom - store float %c, float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, ptr %a, i64 %idxprom + store float %c, ptr %arrayidx, align 4 ret float 0.0 } diff --git a/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll b/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll index e8878cfa325471cafaf4f1030ae9295662580c17..1718bbb3a68bb67ebbc0e961de4c539c227d0fb9 100644 --- a/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll +++ b/llvm/test/CodeGen/CSKY/frameaddr-returnaddr.ll @@ -2,11 +2,11 @@ ; RUN: llc -mtriple=csky -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s \ ; RUN: | FileCheck %s -declare void @notdead(i8*) -declare i8* @llvm.frameaddress(i32) -declare i8* @llvm.returnaddress(i32) +declare void @notdead(ptr) +declare ptr @llvm.frameaddress(i32) +declare ptr @llvm.returnaddress(i32) -define i8* @test_frameaddress_0() nounwind { +define ptr @test_frameaddress_0() nounwind { ; CHECK-LABEL: test_frameaddress_0: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 4 @@ -17,11 +17,11 @@ define i8* @test_frameaddress_0() nounwind { ; CHECK-NEXT: ld32.w l4, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: addi16 sp, sp, 4 ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.frameaddress(i32 0) - ret i8* %1 + %1 = call ptr @llvm.frameaddress(i32 0) + ret ptr %1 } -define i8* @test_frameaddress_2() nounwind { +define ptr @test_frameaddress_2() nounwind { ; CHECK-LABEL: test_frameaddress_2: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 4 @@ -33,11 +33,11 @@ define i8* @test_frameaddress_2() nounwind { ; CHECK-NEXT: ld32.w l4, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: addi16 sp, sp, 4 ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.frameaddress(i32 2) - ret i8* %1 + %1 = call ptr @llvm.frameaddress(i32 2) + ret ptr %1 } -define i8* @test_frameaddress_3_alloca() nounwind { +define ptr @test_frameaddress_3_alloca() nounwind { ; CHECK-LABEL: test_frameaddress_3_alloca: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 8 @@ -57,22 +57,22 @@ define i8* @test_frameaddress_3_alloca() nounwind { ; CHECK-NEXT: addi16 sp, sp, 8 ; CHECK-NEXT: rts16 %1 = alloca [100 x i8] - %2 = bitcast [100 x i8]* %1 to i8* - call void @notdead(i8* %2) - %3 = call i8* @llvm.frameaddress(i32 3) - ret i8* %3 + %2 = bitcast ptr %1 to ptr + call void @notdead(ptr %2) + %3 = call ptr @llvm.frameaddress(i32 3) + ret ptr %3 } -define i8* @test_returnaddress_0() nounwind { +define ptr @test_returnaddress_0() nounwind { ; CHECK-LABEL: test_returnaddress_0: ; CHECK: # %bb.0: ; CHECK-NEXT: mov16 a0, lr ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.returnaddress(i32 0) - ret i8* %1 + %1 = call ptr @llvm.returnaddress(i32 0) + ret ptr %1 } -define i8* @test_returnaddress_2() nounwind { +define ptr @test_returnaddress_2() nounwind { ; CHECK-LABEL: test_returnaddress_2: ; CHECK: # %bb.0: ; CHECK-NEXT: subi16 sp, sp, 4 @@ -85,6 +85,6 @@ define i8* @test_returnaddress_2() nounwind { ; CHECK-NEXT: ld32.w l4, (sp, 0) # 4-byte Folded Reload ; CHECK-NEXT: addi16 sp, sp, 4 ; CHECK-NEXT: rts16 - %1 = call i8* @llvm.returnaddress(i32 2) - ret i8* %1 + %1 = call ptr @llvm.returnaddress(i32 2) + ret ptr %1 } diff --git a/llvm/test/CodeGen/CSKY/indirectbr.ll b/llvm/test/CodeGen/CSKY/indirectbr.ll index 431d3201dc8955b24dfe7904526b25c466b7d821..71a30fb597c371254e47fb94839c039e175b0221 100644 --- a/llvm/test/CodeGen/CSKY/indirectbr.ll +++ b/llvm/test/CodeGen/CSKY/indirectbr.ll @@ -3,7 +3,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=small -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-SMALL ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky -relocation-model=pic -code-model=large -mattr=+2e3 | FileCheck %s --check-prefix=CHECK-PIC-LARGE -@f.a = private unnamed_addr constant [2 x i8*] [i8* blockaddress(@f, %return), i8* blockaddress(@f, %l2)], align 16 +@f.a = private unnamed_addr constant [2 x ptr] [ptr blockaddress(@f, %return), ptr blockaddress(@f, %l2)], align 16 define i32 @f(i32 %x) #0 { ; CHECK-LABEL: f: @@ -88,9 +88,9 @@ define i32 @f(i32 %x) #0 { ; CHECK-PIC-LARGE-NEXT: .long .Lf.a@GOTOFF entry: %idxprom = sext i32 %x to i64 - %arrayidx = getelementptr inbounds [2 x i8*], [2 x i8*]* @f.a, i64 0, i64 %idxprom - %0 = load i8*, i8** %arrayidx, align 8 - indirectbr i8* %0, [label %return, label %l2] + %arrayidx = getelementptr inbounds [2 x ptr], ptr @f.a, i64 0, i64 %idxprom + %0 = load ptr, ptr %arrayidx, align 8 + indirectbr ptr %0, [label %return, label %l2] l2: ; preds = %entry br label %return diff --git a/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll b/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll index 09efc7cf804c571425249e2f2ba97bf2cc0e3ea4..313c8db610921a700d2480bcd653aaa3d1f2a4ac 100644 --- a/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll +++ b/llvm/test/CodeGen/CSKY/inline-asm-d-constraint-f.ll @@ -21,7 +21,7 @@ define double @constraint_f_double(double %a) nounwind { ; CSKYF-NEXT: .LCPI0_0: ; CSKYF-NEXT: .long gd - %1 = load double, double* @gd + %1 = load double, ptr @gd %2 = tail call double asm "faddd $0, $1, $2", "=v,v,v"(double %a, double %1) ret double %2 } @@ -45,7 +45,7 @@ define double @constraint_f_double_abi_name(double %a) nounwind { ; CSKYF-NEXT: .LCPI1_0: ; CSKYF-NEXT: .long gd - %1 = load double, double* @gd + %1 = load double, ptr @gd %2 = tail call double asm "faddd $0, $1, $2", "={fr1},{fr2},{fr3}"(double %a, double %1) ret double %2 } diff --git a/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll b/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll index cf97a8477bd4eb19321d3bb7cd88b609a2581a50..d6d5b9b2489cb83e0072c3181621756dfcd07031 100644 --- a/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll +++ b/llvm/test/CodeGen/CSKY/inline-asm-f-constraint-f.ll @@ -20,7 +20,7 @@ define float @constraint_f_float(float %a) nounwind { ; CSKYF-NEXT: .p2align 2 ; CSKYF-NEXT: .LCPI0_0: ; CSKYF-NEXT: .long gf - %1 = load float, float* @gf + %1 = load float, ptr @gf %2 = tail call float asm "fadds $0, $1, $2", "=v,v,v"(float %a, float %1) ret float %2 } @@ -43,7 +43,7 @@ define float @constraint_f_float_abi_name(float %a) nounwind { ; CSKYF-NEXT: .LCPI1_0: ; CSKYF-NEXT: .long gf - %1 = load float, float* @gf + %1 = load float, ptr @gf %2 = tail call float asm "fadds $0, $1, $2", "={fr0},{fr1},{fr2}"(float %a, float %1) ret float %2 } diff --git a/llvm/test/CodeGen/CSKY/inline-asm.ll b/llvm/test/CodeGen/CSKY/inline-asm.ll index 4e7cb8e98e7482ef4800c53481d095464f67ab44..b955e43ce30d5dbcc729ed6f51bd759acfeca91b 100644 --- a/llvm/test/CodeGen/CSKY/inline-asm.ll +++ b/llvm/test/CodeGen/CSKY/inline-asm.ll @@ -21,7 +21,7 @@ define i32 @constraint_r(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI0_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=r,r,r"(i32 %a, i32 %1) ret i32 %2 } @@ -45,7 +45,7 @@ define i64 @constraint_r_i64(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI1_0: ; CSKY-NEXT: .long mi - %1 = load i64, i64* @mi + %1 = load i64, ptr @mi %2 = call i64 asm "mula.s32 $0, $1, $2", "=r,r,r,0"(i32 %a, i32 %a, i64 %1) ret i64 %2 } @@ -66,7 +66,7 @@ define i32 @constraint_a(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI2_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=a,a,a"(i32 %a, i32 %1) ret i32 %2 } @@ -87,7 +87,7 @@ define i32 @constraint_b(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI3_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=b,b,b"(i32 %a, i32 %1) ret i32 %2 } @@ -109,7 +109,7 @@ define i32 @constraint_z(i32 %a) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI4_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "add $0, $1, $2", "=r,z,r"(i32 %a, i32 %1) ret i32 %2 } @@ -130,7 +130,7 @@ define i32 @constraint_c(i32 %a, i32 %b) nounwind { ; CSKY-NEXT: .p2align 2 ; CSKY-NEXT: .LCPI5_0: ; CSKY-NEXT: .long gi - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "addc $0, $1, $2", "=r,r,r,~{c}"(i32 %a, i32 %1) ret i32 %2 } @@ -145,12 +145,12 @@ define i32 @constraint_i(i32 %a) nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - %1 = load i32, i32* @gi + %1 = load i32, ptr @gi %2 = tail call i32 asm "addi $0, $1, $2", "=r,r,i"(i32 %a, i32 113) ret i32 %2 } -define void @constraint_m(i32* %a) nounwind { +define void @constraint_m(ptr %a) nounwind { ; CSKY-LABEL: constraint_m: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -159,11 +159,11 @@ define void @constraint_m(i32* %a) nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - call void asm sideeffect "", "=*m"(i32* elementtype(i32) %a) + call void asm sideeffect "", "=*m"(ptr elementtype(i32) %a) ret void } -define i32 @constraint_m2(i32* %a) nounwind { +define i32 @constraint_m2(ptr %a) nounwind { ; CSKY-LABEL: constraint_m2: ; CSKY: # %bb.0: ; CSKY-NEXT: subi16 sp, sp, 4 @@ -173,7 +173,7 @@ define i32 @constraint_m2(i32* %a) nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - %1 = tail call i32 asm "ld.w $0, $1", "=r,*m"(i32* elementtype(i32) %a) + %1 = tail call i32 asm "ld.w $0, $1", "=r,*m"(ptr elementtype(i32) %a) ret i32 %1 } @@ -200,7 +200,7 @@ define void @operand_global() nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - tail call void asm sideeffect ".4byte $0", "i"(i32* @gi) + tail call void asm sideeffect ".4byte $0", "i"(ptr @gi) ret void } @@ -216,7 +216,7 @@ define void @operand_block_address() nounwind { ; CSKY-NEXT: addi16 sp, sp, 4 ; CSKY-NEXT: rts16 - call void asm sideeffect "br32 $0", "i"(i8* blockaddress(@operand_block_address, %bb)) + call void asm sideeffect "br32 $0", "i"(ptr blockaddress(@operand_block_address, %bb)) br label %bb bb: ret void diff --git a/llvm/test/CodeGen/CSKY/ldst-i.ll b/llvm/test/CodeGen/CSKY/ldst-i.ll index 06cfc9bde655f9e885d4726653ecf690a4f788cb..c8f2683f0c330b8f3fe91c01e41fac93bf3cb22f 100644 --- a/llvm/test/CodeGen/CSKY/ldst-i.ll +++ b/llvm/test/CodeGen/CSKY/ldst-i.ll @@ -2,7 +2,7 @@ ; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+2e3 < %s -mtriple=csky | FileCheck %s ; RUN: llc -verify-machineinstrs -csky-no-aliases < %s -mtriple=csky | FileCheck %s --check-prefix=GENERIC -define signext i1 @load_I_bits(i1* nocapture readonly %a) local_unnamed_addr #0 { +define signext i1 @load_I_bits(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 3) @@ -20,12 +20,12 @@ define signext i1 @load_I_bits(i1* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define zeroext i1 @load_I_bit_(i1* nocapture readonly %a) local_unnamed_addr #0 { +define zeroext i1 @load_I_bit_(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 3) @@ -40,12 +40,12 @@ define zeroext i1 @load_I_bit_(i1* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define signext i8 @load_I_bs(i8* nocapture readonly %a) local_unnamed_addr #0 { +define signext i8 @load_I_bs(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld32.bs a0, (a0, 3) @@ -61,12 +61,12 @@ define signext i8 @load_I_bs(i8* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define zeroext i8 @load_I_b_(i8* nocapture readonly %a) local_unnamed_addr #0 { +define zeroext i8 @load_I_b_(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 3) @@ -81,12 +81,12 @@ define zeroext i8 @load_I_b_(i8* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define signext i16 @load_I_hs(i16* nocapture readonly %a) local_unnamed_addr #0 { +define signext i16 @load_I_hs(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld32.hs a0, (a0, 6) @@ -102,12 +102,12 @@ define signext i16 @load_I_hs(i16* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define zeroext i16 @load_I_h_(i16* nocapture readonly %a) local_unnamed_addr #0 { +define zeroext i16 @load_I_h_(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.h a0, (a0, 6) @@ -122,12 +122,12 @@ define zeroext i16 @load_I_h_(i16* nocapture readonly %a) local_unnamed_addr #0 ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define i32 @load_I_w(i32* nocapture readonly %a) local_unnamed_addr #0 { +define i32 @load_I_w(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.w a0, (a0, 12) @@ -142,12 +142,12 @@ define i32 @load_I_w(i32* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i32, i32* %a, i64 3 - %0 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 3 + %0 = load i32, ptr %arrayidx, align 4 ret i32 %0 } -define i64 @load_I_d(i64* nocapture readonly %a) local_unnamed_addr #0 { +define i64 @load_I_d(ptr nocapture readonly %a) local_unnamed_addr #0 { ; CHECK-LABEL: load_I_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.w a2, (a0, 24) @@ -166,12 +166,12 @@ define i64 @load_I_d(i64* nocapture readonly %a) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i64, i64* %a, i64 3 - %0 = load i64, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 3 + %0 = load i64, ptr %arrayidx, align 4 ret i64 %0 } -define i8 @load_I_i8_anyext(i8* %p) { +define i8 @load_I_i8_anyext(ptr %p) { ; CHECK-LABEL: load_I_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ld16.b a0, (a0, 0) @@ -186,11 +186,11 @@ define i8 @load_I_i8_anyext(i8* %p) { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %ret = load i8, i8* %p, align 1 + %ret = load i8, ptr %p, align 1 ret i8 %ret } -define signext i1 @load_R_bits(i1* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define signext i1 @load_R_bits(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.bs a0, (a0, a1 << 0) @@ -210,12 +210,12 @@ define signext i1 @load_R_bits(i1* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define zeroext i1 @load_R_bit_(i1* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define zeroext i1 @load_R_bit_(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.b a0, (a0, a1 << 0) @@ -232,13 +232,13 @@ define zeroext i1 @load_R_bit_(i1* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - %0 = load i1, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + %0 = load i1, ptr %arrayidx, align 1 ret i1 %0 } -define signext i8 @load_R_bs(i8* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define signext i8 @load_R_bs(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.bs a0, (a0, a1 << 0) @@ -256,12 +256,12 @@ define signext i8 @load_R_bs(i8* nocapture readonly %a, i32 %b) local_unnamed_ad ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define zeroext i8 @load_R_b_(i8* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define zeroext i8 @load_R_b_(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.b a0, (a0, a1 << 0) @@ -278,12 +278,12 @@ define zeroext i8 @load_R_b_(i8* nocapture readonly %a, i32 %b) local_unnamed_ad ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define signext i16 @load_R_hs(i16* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define signext i16 @load_R_hs(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.hs a0, (a0, a1 << 1) @@ -302,12 +302,12 @@ define signext i16 @load_R_hs(i16* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define zeroext i16 @load_R_h_(i16* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define zeroext i16 @load_R_h_(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.h a0, (a0, a1 << 1) @@ -325,12 +325,12 @@ define zeroext i16 @load_R_h_(i16* nocapture readonly %a, i32 %b) local_unnamed_ ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - %0 = load i16, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + %0 = load i16, ptr %arrayidx, align 2 ret i16 %0 } -define i32 @load_R_w(i32* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define i32 @load_R_w(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.w a0, (a0, a1 << 2) @@ -348,12 +348,12 @@ define i32 @load_R_w(i32* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom - %0 = load i32, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 %idxprom + %0 = load i32, ptr %arrayidx, align 4 ret i32 %0 } -define i64 @load_R_d(i64* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { +define i64 @load_R_d(ptr nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: load_R_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ixd32 a2, a0, a1 @@ -374,12 +374,12 @@ define i64 @load_R_d(i64* nocapture readonly %a, i32 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i64, i64* %a, i64 %idxprom - %0 = load i64, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 %idxprom + %0 = load i64, ptr %arrayidx, align 4 ret i64 %0 } -define i8 @loadR_i8_anyext(i8* %c, i32 %a) { +define i8 @loadR_i8_anyext(ptr %c, i32 %a) { ; CHECK-LABEL: loadR_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ldr32.bs a0, (a0, a1 << 0) @@ -396,12 +396,12 @@ define i8 @loadR_i8_anyext(i8* %c, i32 %a) { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %a to i64 - %arrayidx = getelementptr inbounds i8, i8* %c, i64 %idxprom - %0 = load i8, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %c, i64 %idxprom + %0 = load i8, ptr %arrayidx, align 1 ret i8 %0 } -define signext i1 @store_I_bits(i1* %a, i1 %b) local_unnamed_addr #0 { +define signext i1 @store_I_bits(ptr %a, i1 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a1, a1, 1 @@ -421,12 +421,12 @@ define signext i1 @store_I_bits(i1* %a, i1 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - store i1 %b, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + store i1 %b, ptr %arrayidx, align 1 ret i1 0 } -define zeroext i1 @store_I_bit_(i1* %a, i1 %b) local_unnamed_addr #0 { +define zeroext i1 @store_I_bit_(ptr %a, i1 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a1, a1, 1 @@ -446,12 +446,12 @@ define zeroext i1 @store_I_bit_(i1* %a, i1 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i1, i1* %a, i64 3 - store i1 %b, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 3 + store i1 %b, ptr %arrayidx, align 1 ret i1 0 } -define signext i8 @store_I_bs(i8* %a, i8 %b) local_unnamed_addr #0 { +define signext i8 @store_I_bs(ptr %a, i8 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.b a1, (a0, 3) @@ -468,12 +468,12 @@ define signext i8 @store_I_bs(i8* %a, i8 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - store i8 %b, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + store i8 %b, ptr %arrayidx, align 1 ret i8 0 } -define zeroext i8 @store_I_b_(i8* %a, i8 %b) local_unnamed_addr #0 { +define zeroext i8 @store_I_b_(ptr %a, i8 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.b a1, (a0, 3) @@ -490,12 +490,12 @@ define zeroext i8 @store_I_b_(i8* %a, i8 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i8, i8* %a, i64 3 - store i8 %b, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 3 + store i8 %b, ptr %arrayidx, align 1 ret i8 0 } -define signext i16 @store_I_hs(i16* %a, i16 %b) local_unnamed_addr #0 { +define signext i16 @store_I_hs(ptr %a, i16 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.h a1, (a0, 6) @@ -512,12 +512,12 @@ define signext i16 @store_I_hs(i16* %a, i16 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - store i16 %b, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + store i16 %b, ptr %arrayidx, align 2 ret i16 0 } -define zeroext i16 @store_I_h_(i16* %a, i16 %b) local_unnamed_addr #0 { +define zeroext i16 @store_I_h_(ptr %a, i16 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.h a1, (a0, 6) @@ -534,12 +534,12 @@ define zeroext i16 @store_I_h_(i16* %a, i16 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i16, i16* %a, i64 3 - store i16 %b, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 3 + store i16 %b, ptr %arrayidx, align 2 ret i16 0 } -define i32 @store_I_w(i32* %a, i32 %b) local_unnamed_addr #0 { +define i32 @store_I_w(ptr %a, i32 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.w a1, (a0, 12) @@ -556,12 +556,12 @@ define i32 @store_I_w(i32* %a, i32 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i32, i32* %a, i64 3 - store i32 %b, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 3 + store i32 %b, ptr %arrayidx, align 4 ret i32 0 } -define i64 @store_I_d(i64* %a, i64 %b) local_unnamed_addr #0 { +define i64 @store_I_d(ptr %a, i64 %b) local_unnamed_addr #0 { ; CHECK-LABEL: store_I_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.w a2, (a0, 28) @@ -582,12 +582,12 @@ define i64 @store_I_d(i64* %a, i64 %b) local_unnamed_addr #0 { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - %arrayidx = getelementptr inbounds i64, i64* %a, i64 3 - store i64 %b, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 3 + store i64 %b, ptr %arrayidx, align 4 ret i64 0 } -define i8 @store_I_i8_anyext(i8* %p, i8 %b) { +define i8 @store_I_i8_anyext(ptr %p, i8 %b) { ; CHECK-LABEL: store_I_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: st16.b a1, (a0, 0) @@ -604,11 +604,11 @@ define i8 @store_I_i8_anyext(i8* %p, i8 %b) { ; GENERIC-NEXT: addi16 sp, sp, 4 ; GENERIC-NEXT: rts16 entry: - store i8 %b, i8* %p, align 1 + store i8 %b, ptr %p, align 1 ret i8 0 } -define signext i1 @store_R_bits(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { +define signext i1 @store_R_bits(ptr %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_bits: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a2, a2, 1 @@ -630,12 +630,12 @@ define signext i1 @store_R_bits(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - store i1 %c, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + store i1 %c, ptr %arrayidx, align 1 ret i1 0 } -define zeroext i1 @store_R_bit_(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { +define zeroext i1 @store_R_bit_(ptr %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_bit_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi32 a2, a2, 1 @@ -657,13 +657,13 @@ define zeroext i1 @store_R_bit_(i1* %a, i32 %b, i1 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i1, i1* %a, i64 %idxprom - store i1 %c, i1* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i1, ptr %a, i64 %idxprom + store i1 %c, ptr %arrayidx, align 1 ret i1 0 } -define signext i8 @store_R_bs(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { +define signext i8 @store_R_bs(ptr %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_bs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.b a2, (a0, a1 << 0) @@ -682,12 +682,12 @@ define signext i8 @store_R_bs(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - store i8 %c, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + store i8 %c, ptr %arrayidx, align 1 ret i8 0 } -define zeroext i8 @store_R_b_(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { +define zeroext i8 @store_R_b_(ptr %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_b_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.b a2, (a0, a1 << 0) @@ -706,12 +706,12 @@ define zeroext i8 @store_R_b_(i8* %a, i32 %b, i8 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i8, i8* %a, i64 %idxprom - store i8 %c, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %a, i64 %idxprom + store i8 %c, ptr %arrayidx, align 1 ret i8 0 } -define signext i16 @store_R_hs(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { +define signext i16 @store_R_hs(ptr %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_hs: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.h a2, (a0, a1 << 1) @@ -731,12 +731,12 @@ define signext i16 @store_R_hs(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - store i16 %c, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + store i16 %c, ptr %arrayidx, align 2 ret i16 0 } -define zeroext i16 @store_R_h_(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { +define zeroext i16 @store_R_h_(ptr %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_h_: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.h a2, (a0, a1 << 1) @@ -756,12 +756,12 @@ define zeroext i16 @store_R_h_(i16* %a, i32 %b, i16 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i16, i16* %a, i64 %idxprom - store i16 %c, i16* %arrayidx, align 2 + %arrayidx = getelementptr inbounds i16, ptr %a, i64 %idxprom + store i16 %c, ptr %arrayidx, align 2 ret i16 0 } -define i32 @store_R_w(i32* %a, i32 %b, i32 %c) local_unnamed_addr #0 { +define i32 @store_R_w(ptr %a, i32 %b, i32 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_w: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.w a2, (a0, a1 << 2) @@ -781,12 +781,12 @@ define i32 @store_R_w(i32* %a, i32 %b, i32 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i32, i32* %a, i64 %idxprom - store i32 %c, i32* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i32, ptr %a, i64 %idxprom + store i32 %c, ptr %arrayidx, align 4 ret i32 0 } -define i64 @store_R_d(i64* %a, i32 %b, i64 %c) local_unnamed_addr #0 { +define i64 @store_R_d(ptr %a, i32 %b, i64 %c) local_unnamed_addr #0 { ; CHECK-LABEL: store_R_d: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: ixd32 t0, a0, a1 @@ -811,12 +811,12 @@ define i64 @store_R_d(i64* %a, i32 %b, i64 %c) local_unnamed_addr #0 { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %b to i64 - %arrayidx = getelementptr inbounds i64, i64* %a, i64 %idxprom - store i64 %c, i64* %arrayidx, align 4 + %arrayidx = getelementptr inbounds i64, ptr %a, i64 %idxprom + store i64 %c, ptr %arrayidx, align 4 ret i64 0 } -define i8 @storeR_i8_anyext(i8* %c, i32 %a, i8 %d) { +define i8 @storeR_i8_anyext(ptr %c, i32 %a, i8 %d) { ; CHECK-LABEL: storeR_i8_anyext: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: str32.b a2, (a0, a1 << 0) @@ -835,7 +835,7 @@ define i8 @storeR_i8_anyext(i8* %c, i32 %a, i8 %d) { ; GENERIC-NEXT: rts16 entry: %idxprom = sext i32 %a to i64 - %arrayidx = getelementptr inbounds i8, i8* %c, i64 %idxprom - store i8 %d, i8* %arrayidx, align 1 + %arrayidx = getelementptr inbounds i8, ptr %c, i64 %idxprom + store i8 %d, ptr %arrayidx, align 1 ret i8 0 } diff --git a/llvm/test/CodeGen/CSKY/tls-models.ll b/llvm/test/CodeGen/CSKY/tls-models.ll index 35dca36f515b2dabca0f18f2dd26a619bead0cc8..d520e247c9a3bf77381ca32f73abdde5dcf135bb 100644 --- a/llvm/test/CodeGen/CSKY/tls-models.ll +++ b/llvm/test/CodeGen/CSKY/tls-models.ll @@ -15,7 +15,7 @@ ; No model specified -define i32* @f1() nounwind { +define ptr @f1() nounwind { ; CSKY-PIC-LABEL: f1: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: subi16 sp, sp, 8 @@ -59,13 +59,13 @@ define i32* @f1() nounwind { ; CSKY-NOPIC-NEXT: .Ltmp0: ; CSKY-NOPIC-NEXT: .long unspecified-(.LPC0_1-.Ltmp0)@GOTTPOFF entry: - ret i32* @unspecified + ret ptr @unspecified } ; localdynamic specified -define i32* @f2() nounwind { +define ptr @f2() nounwind { ; CSKY-PIC-LABEL: f2: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: subi16 sp, sp, 8 @@ -109,13 +109,13 @@ define i32* @f2() nounwind { ; CSKY-NOPIC-NEXT: .Ltmp1: ; CSKY-NOPIC-NEXT: .long ld-(.LPC1_1-.Ltmp1)@GOTTPOFF entry: - ret i32* @ld + ret ptr @ld } ; initialexec specified -define i32* @f3() nounwind { +define ptr @f3() nounwind { ; CSKY-PIC-LABEL: f3: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: .LPC2_1: @@ -146,13 +146,13 @@ define i32* @f3() nounwind { ; CSKY-NOPIC-NEXT: .Ltmp2: ; CSKY-NOPIC-NEXT: .long ie-(.LPC2_1-.Ltmp2)@GOTTPOFF entry: - ret i32* @ie + ret ptr @ie } ; localexec specified -define i32* @f4() nounwind { +define ptr @f4() nounwind { ; CSKY-PIC-LABEL: f4: ; CSKY-PIC: # %bb.0: # %entry ; CSKY-PIC-NEXT: lrw32 a0, [.LCPI3_0] @@ -175,5 +175,5 @@ define i32* @f4() nounwind { ; CSKY-NOPIC-NEXT: .LCPI3_0: ; CSKY-NOPIC-NEXT: .long le@TPOFF entry: - ret i32* @le + ret ptr @le } diff --git a/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll b/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll index ff361b6268221dfc4f992322e3aa22ee59d2e27e..c8cf34dbe7f2af0bba192d3be3df00653313805f 100644 --- a/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll +++ b/llvm/test/CodeGen/M68k/Alloc/dyn_alloca_aligned.ll @@ -24,6 +24,6 @@ define i32 @A(i32 %Size) { ; CHECK-NEXT: unlk %a6 ; CHECK-NEXT: rts %A = alloca i8, i32 %Size, align 128 - %A_addr = ptrtoint i8* %A to i32 + %A_addr = ptrtoint ptr %A to i32 ret i32 %A_addr } diff --git a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll index 0fd32b6c12adfe2f943ccf4cedb529b14e6724d5..bd5e593edb33d8ecadb8f4c73bf1068aedab0d5b 100644 --- a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll @@ -4,7 +4,7 @@ declare {i32, i1} @llvm.sadd.with.overflow.i32(i32, i32) declare {i32, i1} @llvm.uadd.with.overflow.i32(i32, i32) -define fastcc i32 @test5(i32 %v1, i32 %v2, i32* %X) nounwind { +define fastcc i32 @test5(i32 %v1, i32 %v2, ptr %X) nounwind { ; CHECK-LABEL: test5: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: add.l %d1, %d0 @@ -20,14 +20,14 @@ entry: br i1 %obit, label %overflow, label %normal normal: - store i32 0, i32* %X + store i32 0, ptr %X br label %overflow overflow: ret i32 %sum } -define fastcc i1 @test6(i32 %v1, i32 %v2, i32* %X) nounwind { +define fastcc i1 @test6(i32 %v1, i32 %v2, ptr %X) nounwind { ; CHECK-LABEL: test6: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: add.l %d1, %d0 @@ -44,7 +44,7 @@ entry: br i1 %obit, label %carry, label %normal normal: - store i32 0, i32* %X + store i32 0, ptr %X br label %carry carry: diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll index 19d8d619083c9d6f995e43c09d177906b0c0b87a..281751e3e183c7ab55161bac600f2d9ecc0b7dde 100644 --- a/llvm/test/CodeGen/M68k/Arith/add.ll +++ b/llvm/test/CodeGen/M68k/Arith/add.ll @@ -14,30 +14,30 @@ define i64 @test1(i64 %A, i32 %B) nounwind { ret i64 %tmp5 } -define void @test2(i32* inreg %a) nounwind { +define void @test2(ptr inreg %a) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l %d0, %a0 ; CHECK-NEXT: add.l #128, (%a0) ; CHECK-NEXT: rts - %aa = load i32, i32* %a + %aa = load i32, ptr %a %b = add i32 %aa, 128 - store i32 %b, i32* %a + store i32 %b, ptr %a ret void } -define fastcc void @test2_fast(i32* inreg %a) nounwind { +define fastcc void @test2_fast(ptr inreg %a) nounwind { ; CHECK-LABEL: test2_fast: ; CHECK: ; %bb.0: ; CHECK-NEXT: add.l #128, (%a0) ; CHECK-NEXT: rts - %aa = load i32, i32* %a + %aa = load i32, ptr %a %b = add i32 %aa, 128 - store i32 %b, i32* %a + store i32 %b, ptr %a ret void } -define fastcc void @test3(i64* inreg %a) nounwind { +define fastcc void @test3(ptr inreg %a) nounwind { ; CHECK-LABEL: test3: ; CHECK: ; %bb.0: ; CHECK-NEXT: suba.l #4, %sp @@ -52,13 +52,13 @@ define fastcc void @test3(i64* inreg %a) nounwind { ; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts - %aa = load i64, i64* %a + %aa = load i64, ptr %a %b = add i64 %aa, 2147483648 - store i64 %b, i64* %a + store i64 %b, ptr %a ret void } -define fastcc void @test4(i64* inreg %a) nounwind { +define fastcc void @test4(ptr inreg %a) nounwind { ; CHECK-LABEL: test4: ; CHECK: ; %bb.0: ; CHECK-NEXT: suba.l #4, %sp @@ -73,9 +73,9 @@ define fastcc void @test4(i64* inreg %a) nounwind { ; CHECK-NEXT: movem.l (0,%sp), %d2 ; 8-byte Folded Reload ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts - %aa = load i64, i64* %a + %aa = load i64, ptr %a %b = add i64 %aa, 128 - store i64 %b, i64* %a + store i64 %b, ptr %a ret void } diff --git a/llvm/test/CodeGen/M68k/Arith/bitwise.ll b/llvm/test/CodeGen/M68k/Arith/bitwise.ll index fa8ea1370f8666d095ac46393f9bdbf432847f3e..70e4dd42bfb6deafa9a763b7786ab67a218039df 100644 --- a/llvm/test/CodeGen/M68k/Arith/bitwise.ll +++ b/llvm/test/CodeGen/M68k/Arith/bitwise.ll @@ -117,7 +117,7 @@ define i32 @eorl(i32 %a, i32 %b) nounwind { ; op reg, imm ; For type i8 and i16, value is loaded from memory to avoid optimizing it to *.l -define void @andib(i8* %a) nounwind { +define void @andib(ptr %a) nounwind { ; CHECK-LABEL: andib: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -125,13 +125,13 @@ define void @andib(i8* %a) nounwind { ; CHECK-NEXT: and.b #18, %d0 ; CHECK-NEXT: move.b %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i8, i8* %a + %1 = load i8, ptr %a %2 = and i8 %1, 18 - store i8 %2, i8* %a + store i8 %2, ptr %a ret void } -define void @andiw(i16* %a) nounwind { +define void @andiw(ptr %a) nounwind { ; CHECK-LABEL: andiw: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -139,9 +139,9 @@ define void @andiw(i16* %a) nounwind { ; CHECK-NEXT: and.w #4660, %d0 ; CHECK-NEXT: move.w %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i16, i16* %a + %1 = load i16, ptr %a %2 = and i16 %1, 4660 - store i16 %2, i16* %a + store i16 %2, ptr %a ret void } @@ -155,7 +155,7 @@ define i32 @andil(i32 %a) nounwind { ret i32 %1 } -define void @orib(i8* %a) nounwind { +define void @orib(ptr %a) nounwind { ; CHECK-LABEL: orib: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -163,13 +163,13 @@ define void @orib(i8* %a) nounwind { ; CHECK-NEXT: or.b #18, %d0 ; CHECK-NEXT: move.b %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i8, i8* %a + %1 = load i8, ptr %a %2 = or i8 %1, 18 - store i8 %2, i8* %a + store i8 %2, ptr %a ret void } -define void @oriw(i16* %a) nounwind { +define void @oriw(ptr %a) nounwind { ; CHECK-LABEL: oriw: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -177,9 +177,9 @@ define void @oriw(i16* %a) nounwind { ; CHECK-NEXT: or.w #4660, %d0 ; CHECK-NEXT: move.w %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i16, i16* %a + %1 = load i16, ptr %a %2 = or i16 %1, 4660 - store i16 %2, i16* %a + store i16 %2, ptr %a ret void } @@ -193,7 +193,7 @@ define i32 @oril(i32 %a) nounwind { ret i32 %1 } -define void @eorib(i8* %a) nounwind { +define void @eorib(ptr %a) nounwind { ; CHECK-LABEL: eorib: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -201,13 +201,13 @@ define void @eorib(i8* %a) nounwind { ; CHECK-NEXT: eori.b #18, %d0 ; CHECK-NEXT: move.b %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i8, i8* %a + %1 = load i8, ptr %a %2 = xor i8 %1, 18 - store i8 %2, i8* %a + store i8 %2, ptr %a ret void } -define void @eoriw(i16* %a) nounwind { +define void @eoriw(ptr %a) nounwind { ; CHECK-LABEL: eoriw: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -215,9 +215,9 @@ define void @eoriw(i16* %a) nounwind { ; CHECK-NEXT: eori.w #4660, %d0 ; CHECK-NEXT: move.w %d0, (%a0) ; CHECK-NEXT: rts - %1 = load i16, i16* %a + %1 = load i16, ptr %a %2 = xor i16 %1, 4660 - store i16 %2, i16* %a + store i16 %2, ptr %a ret void } diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll index b649b2ba161478b7b515f4b3ae1c92c8155ecdda..5bd4d5d48bc85927a1821951df5eecc15e552d7d 100644 --- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll @@ -54,7 +54,7 @@ entry: declare { i16, i1 } @llvm.smul.with.overflow.i16(i16, i16) nounwind readnone -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(ptr, ...) nounwind declare {i32, i1} @llvm.smul.with.overflow.i32(i32, i32) @ok = internal constant [4 x i8] c"%d\0A\00" @@ -88,11 +88,11 @@ entry: br i1 %obit, label %overflow, label %normal normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true overflow: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false } @@ -126,11 +126,11 @@ entry: br i1 %obit, label %overflow, label %normal overflow: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true } diff --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll index da6d78a492882480942319b67808bf8d2d8333b2..8d47c7ebf7e56f70d8e4aace2e4269f4f505b878 100644 --- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s -declare i32 @printf(i8*, ...) nounwind +declare i32 @printf(ptr, ...) nounwind declare {i32, i1} @llvm.ssub.with.overflow.i32(i32, i32) declare {i32, i1} @llvm.usub.with.overflow.i32(i32, i32) @@ -37,11 +37,11 @@ entry: br i1 %obit, label %overflow, label %normal normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true overflow: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false } @@ -74,11 +74,11 @@ entry: br i1 %obit, label %carry, label %normal normal: - %t1 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @ok, i32 0, i32 0), i32 %sum ) nounwind + %t1 = tail call i32 (ptr, ...) @printf( ptr @ok, i32 %sum ) nounwind ret i1 true carry: - %t2 = tail call i32 (i8*, ...) @printf( i8* getelementptr ([4 x i8], [4 x i8]* @no, i32 0, i32 0) ) nounwind + %t2 = tail call i32 (ptr, ...) @printf( ptr @no ) nounwind ret i1 false } diff --git a/llvm/test/CodeGen/M68k/Atomics/load-store.ll b/llvm/test/CodeGen/M68k/Atomics/load-store.ll index 7608edb220d3c9042b2384f2213682b1e274c91f..b238172c2f12c059345bf69c444cade67e72898c 100644 --- a/llvm/test/CodeGen/M68k/Atomics/load-store.ll +++ b/llvm/test/CodeGen/M68k/Atomics/load-store.ll @@ -5,7 +5,7 @@ ; RUN: llc %s -o - -mtriple=m68k -mcpu=M68030 | FileCheck %s --check-prefix=ATOMIC ; RUN: llc %s -o - -mtriple=m68k -mcpu=M68040 | FileCheck %s --check-prefix=ATOMIC -define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { +define i8 @atomic_load_i8_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -17,11 +17,11 @@ define i8 @atomic_load_i8_unordered(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a unordered, align 1 + %1 = load atomic i8, ptr %a unordered, align 1 ret i8 %1 } -define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { +define i8 @atomic_load_i8_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -33,11 +33,11 @@ define i8 @atomic_load_i8_monotonic(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a monotonic, align 1 + %1 = load atomic i8, ptr %a monotonic, align 1 ret i8 %1 } -define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { +define i8 @atomic_load_i8_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -49,11 +49,11 @@ define i8 @atomic_load_i8_acquire(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a acquire, align 1 + %1 = load atomic i8, ptr %a acquire, align 1 ret i8 %1 } -define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { +define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i8_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -65,11 +65,11 @@ define i8 @atomic_load_i8_seq_cst(i8 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i8, i8* %a seq_cst, align 1 + %1 = load atomic i8, ptr %a seq_cst, align 1 ret i8 %1 } -define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { +define i16 @atomic_load_i16_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -81,11 +81,11 @@ define i16 @atomic_load_i16_unordered(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a unordered, align 2 + %1 = load atomic i16, ptr %a unordered, align 2 ret i16 %1 } -define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { +define i16 @atomic_load_i16_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -97,11 +97,11 @@ define i16 @atomic_load_i16_monotonic(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a monotonic, align 2 + %1 = load atomic i16, ptr %a monotonic, align 2 ret i16 %1 } -define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { +define i16 @atomic_load_i16_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -113,11 +113,11 @@ define i16 @atomic_load_i16_acquire(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a acquire, align 2 + %1 = load atomic i16, ptr %a acquire, align 2 ret i16 %1 } -define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { +define i16 @atomic_load_i16_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i16_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -129,11 +129,11 @@ define i16 @atomic_load_i16_seq_cst(i16 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i16, i16* %a seq_cst, align 2 + %1 = load atomic i16, ptr %a seq_cst, align 2 ret i16 %1 } -define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { +define i32 @atomic_load_i32_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -145,11 +145,11 @@ define i32 @atomic_load_i32_unordered(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a unordered, align 4 + %1 = load atomic i32, ptr %a unordered, align 4 ret i32 %1 } -define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { +define i32 @atomic_load_i32_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -161,11 +161,11 @@ define i32 @atomic_load_i32_monotonic(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a monotonic, align 4 + %1 = load atomic i32, ptr %a monotonic, align 4 ret i32 %1 } -define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { +define i32 @atomic_load_i32_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -177,11 +177,11 @@ define i32 @atomic_load_i32_acquire(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a acquire, align 4 + %1 = load atomic i32, ptr %a acquire, align 4 ret i32 %1 } -define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { +define i32 @atomic_load_i32_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i32_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (4,%sp), %a0 @@ -193,11 +193,11 @@ define i32 @atomic_load_i32_seq_cst(i32 *%a) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l (%a0), %d0 ; ATOMIC-NEXT: rts - %1 = load atomic i32, i32* %a seq_cst, align 4 + %1 = load atomic i32, ptr %a seq_cst, align 4 ret i32 %1 } -define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { +define i64 @atomic_load_i64_unordered(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -215,11 +215,11 @@ define i64 @atomic_load_i64_unordered(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a unordered, align 8 + %1 = load atomic i64, ptr %a unordered, align 8 ret i64 %1 } -define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { +define i64 @atomic_load_i64_monotonic(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -237,11 +237,11 @@ define i64 @atomic_load_i64_monotonic(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a monotonic, align 8 + %1 = load atomic i64, ptr %a monotonic, align 8 ret i64 %1 } -define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { +define i64 @atomic_load_i64_acquire(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_acquire: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -259,11 +259,11 @@ define i64 @atomic_load_i64_acquire(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a acquire, align 8 + %1 = load atomic i64, ptr %a acquire, align 8 ret i64 %1 } -define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { +define i64 @atomic_load_i64_seq_cst(ptr %a) nounwind { ; NO-ATOMIC-LABEL: atomic_load_i64_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #12, %sp @@ -281,11 +281,11 @@ define i64 @atomic_load_i64_seq_cst(i64 *%a) nounwind { ; ATOMIC-NEXT: jsr __atomic_load_8@PLT ; ATOMIC-NEXT: adda.l #12, %sp ; ATOMIC-NEXT: rts - %1 = load atomic i64, i64* %a seq_cst, align 8 + %1 = load atomic i64, ptr %a seq_cst, align 8 ret i64 %1 } -define void @atomic_store_i8_unordered(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_unordered(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -299,11 +299,11 @@ define void @atomic_store_i8_unordered(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a unordered, align 1 + store atomic i8 %val, ptr %a unordered, align 1 ret void } -define void @atomic_store_i8_monotonic(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_monotonic(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -317,11 +317,11 @@ define void @atomic_store_i8_monotonic(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a monotonic, align 1 + store atomic i8 %val, ptr %a monotonic, align 1 ret void } -define void @atomic_store_i8_release(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_release(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -335,11 +335,11 @@ define void @atomic_store_i8_release(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a release, align 1 + store atomic i8 %val, ptr %a release, align 1 ret void } -define void @atomic_store_i8_seq_cst(i8 *%a, i8 %val) nounwind { +define void @atomic_store_i8_seq_cst(ptr %a, i8 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i8_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.b (11,%sp), %d0 @@ -353,11 +353,11 @@ define void @atomic_store_i8_seq_cst(i8 *%a, i8 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.b %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i8 %val, i8* %a seq_cst, align 1 + store atomic i8 %val, ptr %a seq_cst, align 1 ret void } -define void @atomic_store_i16_unordered(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_unordered(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -371,11 +371,11 @@ define void @atomic_store_i16_unordered(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a unordered, align 2 + store atomic i16 %val, ptr %a unordered, align 2 ret void } -define void @atomic_store_i16_monotonic(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_monotonic(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -389,11 +389,11 @@ define void @atomic_store_i16_monotonic(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a monotonic, align 2 + store atomic i16 %val, ptr %a monotonic, align 2 ret void } -define void @atomic_store_i16_release(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_release(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -407,11 +407,11 @@ define void @atomic_store_i16_release(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a release, align 2 + store atomic i16 %val, ptr %a release, align 2 ret void } -define void @atomic_store_i16_seq_cst(i16 *%a, i16 %val) nounwind { +define void @atomic_store_i16_seq_cst(ptr %a, i16 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i16_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.w (10,%sp), %d0 @@ -425,11 +425,11 @@ define void @atomic_store_i16_seq_cst(i16 *%a, i16 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.w %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i16 %val, i16* %a seq_cst, align 2 + store atomic i16 %val, ptr %a seq_cst, align 2 ret void } -define void @atomic_store_i32_unordered(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_unordered(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -443,11 +443,11 @@ define void @atomic_store_i32_unordered(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a unordered, align 4 + store atomic i32 %val, ptr %a unordered, align 4 ret void } -define void @atomic_store_i32_monotonic(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_monotonic(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -461,11 +461,11 @@ define void @atomic_store_i32_monotonic(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a monotonic, align 4 + store atomic i32 %val, ptr %a monotonic, align 4 ret void } -define void @atomic_store_i32_release(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_release(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -479,11 +479,11 @@ define void @atomic_store_i32_release(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a release, align 4 + store atomic i32 %val, ptr %a release, align 4 ret void } -define void @atomic_store_i32_seq_cst(i32 *%a, i32 %val) nounwind { +define void @atomic_store_i32_seq_cst(ptr %a, i32 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i32_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: move.l (8,%sp), %d0 @@ -497,11 +497,11 @@ define void @atomic_store_i32_seq_cst(i32 *%a, i32 %val) nounwind { ; ATOMIC-NEXT: move.l (4,%sp), %a0 ; ATOMIC-NEXT: move.l %d0, (%a0) ; ATOMIC-NEXT: rts - store atomic i32 %val, i32* %a seq_cst, align 4 + store atomic i32 %val, ptr %a seq_cst, align 4 ret void } -define void @atomic_store_i64_unordered(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_unordered(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_unordered: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -523,11 +523,11 @@ define void @atomic_store_i64_unordered(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a unordered, align 8 + store atomic i64 %val, ptr %a unordered, align 8 ret void } -define void @atomic_store_i64_monotonic(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_monotonic(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_monotonic: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -549,11 +549,11 @@ define void @atomic_store_i64_monotonic(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a monotonic, align 8 + store atomic i64 %val, ptr %a monotonic, align 8 ret void } -define void @atomic_store_i64_release(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_release(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_release: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -575,11 +575,11 @@ define void @atomic_store_i64_release(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a release, align 8 + store atomic i64 %val, ptr %a release, align 8 ret void } -define void @atomic_store_i64_seq_cst(i64 *%a, i64 %val) nounwind { +define void @atomic_store_i64_seq_cst(ptr %a, i64 %val) nounwind { ; NO-ATOMIC-LABEL: atomic_store_i64_seq_cst: ; NO-ATOMIC: ; %bb.0: ; NO-ATOMIC-NEXT: suba.l #20, %sp @@ -601,6 +601,6 @@ define void @atomic_store_i64_seq_cst(i64 *%a, i64 %val) nounwind { ; ATOMIC-NEXT: jsr __atomic_store_8@PLT ; ATOMIC-NEXT: adda.l #20, %sp ; ATOMIC-NEXT: rts - store atomic i64 %val, i64* %a seq_cst, align 8 + store atomic i64 %val, ptr %a seq_cst, align 8 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll b/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll index 5eee426462cfa4d02e5d4c77fb7ed0251b7e5468..f0ccd8c09e535cf3542bcb103911210a21dbdb8f 100644 --- a/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll +++ b/llvm/test/CodeGen/M68k/CConv/c-args-inreg.ll @@ -4,18 +4,18 @@ ; ; Pass first two arguments in registers %d0 and %d1 -define void @foo_inreg(i32* nocapture inreg %out, i32 inreg %in) nounwind { +define void @foo_inreg(ptr nocapture inreg %out, i32 inreg %in) nounwind { ; CHECK-LABEL: foo_inreg: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l %d0, %a0 ; CHECK-NEXT: move.l %d1, (%a0) ; CHECK-NEXT: rts entry: - store i32 %in, i32* %out, align 4 + store i32 %in, ptr %out, align 4 ret void } -define void @bar_inreg(i32* nocapture inreg %pOut, i32* nocapture inreg %pIn) nounwind { +define void @bar_inreg(ptr nocapture inreg %pOut, ptr nocapture inreg %pIn) nounwind { ; CHECK-LABEL: bar_inreg: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l %d1, %a0 @@ -23,7 +23,7 @@ define void @bar_inreg(i32* nocapture inreg %pOut, i32* nocapture inreg %pIn) no ; CHECK-NEXT: move.l (%a0), (%a1) ; CHECK-NEXT: rts entry: - %0 = load i32, i32* %pIn, align 4 - store i32 %0, i32* %pOut, align 4 + %0 = load i32, ptr %pIn, align 4 + store i32 %0, ptr %pOut, align 4 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/c-args.ll b/llvm/test/CodeGen/M68k/CConv/c-args.ll index c5477e2812ca11815d00652743ce41fa27a5ed2c..c7e356ef349b66eab33caa9b104caa12f8b1c491 100644 --- a/llvm/test/CodeGen/M68k/CConv/c-args.ll +++ b/llvm/test/CodeGen/M68k/CConv/c-args.ll @@ -4,18 +4,18 @@ ; ; C Call passes all arguments on stack ... -define void @test1(i32* nocapture %out, i32 %in) nounwind { +define void @test1(ptr nocapture %out, i32 %in) nounwind { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (4,%sp), %a0 ; CHECK-NEXT: move.l (8,%sp), (%a0) ; CHECK-NEXT: rts entry: - store i32 %in, i32* %out, align 4 + store i32 %in, ptr %out, align 4 ret void } -define void @test2(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { +define void @test2(ptr nocapture %pOut, ptr nocapture %pIn) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (8,%sp), %a0 @@ -23,30 +23,30 @@ define void @test2(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { ; CHECK-NEXT: move.l (%a0), (%a1) ; CHECK-NEXT: rts entry: - %0 = load i32, i32* %pIn, align 4 - store i32 %0, i32* %pOut, align 4 + %0 = load i32, ptr %pIn, align 4 + store i32 %0, ptr %pOut, align 4 ret void } -define void @test3(i8* nocapture %out, i8 %in) nounwind { +define void @test3(ptr nocapture %out, i8 %in) nounwind { ; CHECK-LABEL: test3: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (4,%sp), %a0 ; CHECK-NEXT: move.b (11,%sp), (%a0) ; CHECK-NEXT: rts entry: - store i8 %in, i8* %out, align 1 + store i8 %in, ptr %out, align 1 ret void } -define void @test4(i16* nocapture %out, i16 %in) nounwind { +define void @test4(ptr nocapture %out, i16 %in) nounwind { ; CHECK-LABEL: test4: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (4,%sp), %a0 ; CHECK-NEXT: move.w (10,%sp), (%a0) ; CHECK-NEXT: rts entry: - store i16 %in, i16* %out, align 2 + store i16 %in, ptr %out, align 2 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll index 55c0b9f449e796a029d59ce6528b78226c29d927..12ba97e261787d686ec36043333e957da56dbec8 100644 --- a/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll +++ b/llvm/test/CodeGen/M68k/CConv/fastcc-args.ll @@ -3,24 +3,24 @@ ; ; C Call passes all arguments on stack ... -define fastcc void @test1(i32* nocapture %out, i32 %in) nounwind { +define fastcc void @test1(ptr nocapture %out, i32 %in) nounwind { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l %d0, (%a0) ; CHECK-NEXT: rts entry: - store i32 %in, i32* %out, align 4 + store i32 %in, ptr %out, align 4 ret void } -define fastcc void @test2(i32* nocapture %pOut, i32* nocapture %pIn) nounwind { +define fastcc void @test2(ptr nocapture %pOut, ptr nocapture %pIn) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - %0 = load i32, i32* %pIn, align 4 - store i32 %0, i32* %pOut, align 4 + %0 = load i32, ptr %pIn, align 4 + store i32 %0, ptr %pOut, align 4 ret void } diff --git a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll index 5931f76d70b19d660762e65c4601564d239bd709..4b0f8ed254a5e69fc6d4ae84ae415577eaf238c8 100644 --- a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll +++ b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll @@ -44,8 +44,8 @@ define i32 @foo2() nounwind uwtable { entry: %a = alloca i32, align 4 %b = alloca i32, align 4 - call fastcc void @bar2(i32* %a, i32 2, i32* %b, i32 4) nounwind + call fastcc void @bar2(ptr %a, i32 2, ptr %b, i32 4) nounwind ret i32 0 } -declare fastcc void @bar2(i32* %a, i32 %b, i32* %c, i32 %d); +declare fastcc void @bar2(ptr %a, i32 %b, ptr %c, i32 %d); diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll index 2ab3115f87f502960c2f304ac11bfa13a434b842..407bbd48bc7f892c7b5ba00cbfad2019fde26064 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pic.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=medium -relocation-model=pic \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -17,13 +17,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -37,13 +37,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -54,12 +54,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { ; CHECK-LABEL: test3: @@ -72,9 +72,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -93,7 +93,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -110,9 +110,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l (0,%a0,%d0), (0,%a0,%d1) ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll index aca79f001737479aa480209ecfdb21771fa79820..ce8f2d0a6ba760da3a10d09908ca88d09507653d 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll @@ -14,7 +14,7 @@ define i32 @my_access_global_a() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @a, align 4 + %0 = load i32, ptr @a, align 4 ret i32 %0 } @@ -29,7 +29,7 @@ define i32 @my_access_global_b() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @b, align 4 + %0 = load i32, ptr @b, align 4 ret i32 %0 } @@ -45,7 +45,7 @@ define i32 @my_access_global_c() #0 { ; CHECK-NEXT: move.l (0,%a0,%d0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @c, align 4 + %0 = load i32, ptr @c, align 4 ret i32 %0 } @@ -60,7 +60,7 @@ define i32 @my_access_global_load_d() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @d, align 4 + %0 = load i32, ptr @d, align 4 ret i32 %0 } @@ -74,12 +74,12 @@ define i32 @my_access_global_store_d() #0 { ; CHECK-NEXT: move.l #0, %d0 ; CHECK-NEXT: rts entry: - store i32 2, i32* @d, align 4 + store i32 2, ptr @d, align 4 ret i32 0 } ; External Linkage, function pointer access. -declare i32 @access_fp(i32 ()*) +declare i32 @access_fp(ptr) declare i32 @foo() define i32 @my_access_fp_foo() #0 { @@ -93,7 +93,7 @@ define i32 @my_access_fp_foo() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @foo) + %call = call i32 @access_fp(ptr @foo) ret i32 %call } @@ -122,7 +122,7 @@ define i32 @my_access_fp_bar() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @bar) + %call = call i32 @access_fp(ptr @bar) ret i32 %call } diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll index 1a544a971d266d22cdd621d34d2dc784441752b5..87d8380d6cc9c5f464ee1fd30ad7b08e0f490dcd 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-static.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=medium -relocation-model=static \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -14,13 +14,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l src, dst ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -31,13 +31,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l src2, dst2 ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -48,12 +48,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { @@ -66,9 +66,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -87,7 +87,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -98,9 +98,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l src6, dst6 ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll index 1f39ec82db326e5ba65a7c74f5a17bda7171f8e4..37115953e5be38d059c150c86b7895b859d61bee 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-pic.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=small -relocation-model=pic \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -17,13 +17,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -37,13 +37,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l (%a1), (%a0) ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -54,12 +54,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { ; CHECK-LABEL: test3: @@ -72,9 +72,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -93,7 +93,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -105,9 +105,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l (src6,%pc), (dst6,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll index de6e1227e72a32c2fc7f2bb3eff887b5061c657e..668f8a96ac6f955d72756ecd26445c8a82cffb3b 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll @@ -14,7 +14,7 @@ define i32 @my_access_global_a() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @a, align 4 + %0 = load i32, ptr @a, align 4 ret i32 %0 } @@ -29,7 +29,7 @@ define i32 @my_access_global_b() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @b, align 4 + %0 = load i32, ptr @b, align 4 ret i32 %0 } @@ -43,7 +43,7 @@ define i32 @my_access_global_c() #0 { ; CHECK-NEXT: move.l (c,%pc), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @c, align 4 + %0 = load i32, ptr @c, align 4 ret i32 %0 } @@ -58,7 +58,7 @@ define i32 @my_access_global_load_d() #0 { ; CHECK-NEXT: move.l (%a0), %d0 ; CHECK-NEXT: rts entry: - %0 = load i32, i32* @d, align 4 + %0 = load i32, ptr @d, align 4 ret i32 %0 } @@ -72,12 +72,12 @@ define i32 @my_access_global_store_d() #0 { ; CHECK-NEXT: move.l #0, %d0 ; CHECK-NEXT: rts entry: - store i32 2, i32* @d, align 4 + store i32 2, ptr @d, align 4 ret i32 0 } ; External Linkage, function pointer access. -declare i32 @access_fp(i32 ()*) +declare i32 @access_fp(ptr) declare i32 @foo() define i32 @my_access_fp_foo() #0 { @@ -91,7 +91,7 @@ define i32 @my_access_fp_foo() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @foo) + %call = call i32 @access_fp(ptr @foo) ret i32 %call } @@ -120,7 +120,7 @@ define i32 @my_access_fp_bar() #0 { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %call = call i32 @access_fp(i32 ()* @bar) + %call = call i32 @access_fp(ptr @bar) ret i32 %call } diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-static.ll b/llvm/test/CodeGen/M68k/CodeModel/small-static.ll index 6ab9a7b61e4411de55cd67a3afd29d16276ae38f..d7fa5b0ea4e56c9576c8d3db944387eebd7a1936 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-static.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-static.ll @@ -3,7 +3,7 @@ ; RUN: -code-model=small -relocation-model=static \ ; RUN: | FileCheck %s -@ptr = external global i32* +@ptr = external global ptr @dst = external global i32 @src = external global i32 @@ -15,13 +15,13 @@ define void @test0() nounwind { ; CHECK-NEXT: move.l (src,%pc), (dst,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst, i32** @ptr - %tmp.s = load i32, i32* @src - store i32 %tmp.s, i32* @dst + store ptr @dst, ptr @ptr + %tmp.s = load i32, ptr @src + store i32 %tmp.s, ptr @dst ret void } -@ptr2 = global i32* null +@ptr2 = global ptr null @dst2 = global i32 0 @src2 = global i32 0 @@ -33,13 +33,13 @@ define void @test1() nounwind { ; CHECK-NEXT: move.l (src2,%pc), (dst2,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst2, i32** @ptr2 - %tmp.s = load i32, i32* @src2 - store i32 %tmp.s, i32* @dst2 + store ptr @dst2, ptr @ptr2 + %tmp.s = load i32, ptr @src2 + store i32 %tmp.s, ptr @dst2 ret void } -declare i8* @malloc(i32) +declare ptr @malloc(i32) define void @test2() nounwind { ; CHECK-LABEL: test2: @@ -50,12 +50,12 @@ define void @test2() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %ptr = call i8* @malloc(i32 40) + %ptr = call ptr @malloc(i32 40) ret void } -@pfoo = external global void(...)* -declare void(...)* @afoo(...) +@pfoo = external global ptr +declare ptr @afoo(...) define void @test3() nounwind { ; CHECK-LABEL: test3: @@ -67,9 +67,9 @@ define void @test3() nounwind { ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: - %tmp = call void(...)*(...) @afoo() - store void(...)* %tmp, void(...)** @pfoo - %tmp1 = load void(...)*, void(...)** @pfoo + %tmp = call ptr(...) @afoo() + store ptr %tmp, ptr @pfoo + %tmp1 = load ptr, ptr @pfoo call void(...) %tmp1() ret void } @@ -88,7 +88,7 @@ entry: ret void } -@ptr6 = internal global i32* null +@ptr6 = internal global ptr null @dst6 = internal global i32 0 @src6 = internal global i32 0 @@ -100,9 +100,9 @@ define void @test5() nounwind { ; CHECK-NEXT: move.l (src6,%pc), (dst6,%pc) ; CHECK-NEXT: rts entry: - store i32* @dst6, i32** @ptr6 - %tmp.s = load i32, i32* @src6 - store i32 %tmp.s, i32* @dst6 + store ptr @dst6, ptr @ptr6 + %tmp.s = load i32, ptr @src6 + store i32 %tmp.s, ptr @dst6 ret void } diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll index aa20461a8d6510c97c70fd0687c8b7963a36d4fc..634c08760a4e06c270fdf9edbaa985f1a6f94ff2 100644 --- a/llvm/test/CodeGen/M68k/Control/cmp.ll +++ b/llvm/test/CodeGen/M68k/Control/cmp.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=m68k -verify-machineinstrs | FileCheck %s -define i32 @test1(i32* %y) nounwind { +define i32 @test1(ptr %y) nounwind { ; CHECK-LABEL: test1: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -13,7 +13,7 @@ define i32 @test1(i32* %y) nounwind { ; CHECK-NEXT: .LBB0_2: ; %cond_true ; CHECK-NEXT: move.l #1, %d0 ; CHECK-NEXT: rts - %tmp = load i32, i32* %y ; [#uses=1] + %tmp = load i32, ptr %y ; [#uses=1] %tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; [#uses=1] br i1 %tmp.upgrd.1, label %cond_true, label %cond_false @@ -24,7 +24,7 @@ cond_true: ; preds = %0 ret i32 1 } -define i32 @test2(i32* %y) nounwind { +define i32 @test2(ptr %y) nounwind { ; CHECK-LABEL: test2: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -38,7 +38,7 @@ define i32 @test2(i32* %y) nounwind { ; CHECK-NEXT: .LBB1_2: ; %cond_true ; CHECK-NEXT: move.l #1, %d0 ; CHECK-NEXT: rts - %tmp = load i32, i32* %y ; [#uses=1] + %tmp = load i32, ptr %y ; [#uses=1] %tmp1 = shl i32 %tmp, 3 ; [#uses=1] %tmp1.upgrd.2 = icmp eq i32 %tmp1, 0 ; [#uses=1] br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false @@ -50,7 +50,7 @@ cond_true: ; preds = %0 ret i32 1 } -define i8 @test2b(i8* %y) nounwind { +define i8 @test2b(ptr %y) nounwind { ; CHECK-LABEL: test2b: ; CHECK: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %a0 @@ -64,7 +64,7 @@ define i8 @test2b(i8* %y) nounwind { ; CHECK-NEXT: .LBB2_2: ; %cond_true ; CHECK-NEXT: move.b #1, %d0 ; CHECK-NEXT: rts - %tmp = load i8, i8* %y ; [#uses=1] + %tmp = load i8, ptr %y ; [#uses=1] %tmp1 = shl i8 %tmp, 3 ; [#uses=1] %tmp1.upgrd.2 = icmp eq i8 %tmp1, 0 ; [#uses=1] br i1 %tmp1.upgrd.2, label %cond_true, label %cond_false @@ -127,8 +127,8 @@ define i32 @test6() nounwind align 2 { ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts %A = alloca {i64, i64}, align 8 - %B = getelementptr inbounds {i64, i64}, {i64, i64}* %A, i64 0, i32 1 - %C = load i64, i64* %B + %B = getelementptr inbounds {i64, i64}, ptr %A, i64 0, i32 1 + %C = load i64, ptr %B %D = icmp eq i64 %C, 0 br i1 %D, label %T, label %F T: @@ -282,7 +282,7 @@ define i8 @test18(i64 %L) { @d = global i8 0, align 1 -define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) { +define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) { ; CHECK-LABEL: test20: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: @@ -312,9 +312,9 @@ define void @test20(i32 %bf.load, i8 %x1, i8* %b_addr) { %add = add nuw nsw i32 %conv, %conv6 %tobool7 = icmp ne i32 %add, 0 %frombool = zext i1 %tobool7 to i8 - store i8 %frombool, i8* %b_addr, align 1 + store i8 %frombool, ptr %b_addr, align 1 %tobool14 = icmp ne i32 %bf.shl, 0 %frombool15 = zext i1 %tobool14 to i8 - store i8 %frombool15, i8* @d, align 1 + store i8 %frombool15, ptr @d, align 1 ret void } diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll index f4ff2582fbb17211a1ae6a6ca680a9682f091ef8..b4ecbd5c62825100d05ff9124641ee4296682e73 100644 --- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll +++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-call.ll @@ -57,8 +57,8 @@ define i8 @test_ret_i8() nounwind { ret i8 %1 } -declare void @sret_callee(%struct.A* sret(%struct.A)) -define void @test_sret(%struct.A* sret(%struct.A) %0) nounwind { +declare void @sret_callee(ptr sret(%struct.A)) +define void @test_sret(ptr sret(%struct.A) %0) nounwind { ; CHECK-LABEL: name: test_sret ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -71,7 +71,7 @@ define void @test_sret(%struct.A* sret(%struct.A) %0) nounwind { ; CHECK-NEXT: CALLb @sret_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @sret_callee(%struct.A* sret(%struct.A) %0) + call void @sret_callee(ptr sret(%struct.A) %0) ret void } @@ -105,7 +105,7 @@ define void @test_arg_i32_i16_i8() nounwind { } declare void @arg_struct_callee(%struct.A) -define void @test_arg_struct(%struct.A *%0) nounwind { +define void @test_arg_struct(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_struct ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -135,13 +135,13 @@ define void @test_arg_struct(%struct.A *%0) nounwind { ; CHECK-NEXT: CALLb @arg_struct_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 12, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - %2 = load %struct.A, %struct.A* %0 + %2 = load %struct.A, ptr %0 call void @arg_struct_callee(%struct.A %2) ret void } declare void @arg_array_callee([8 x i8]) -define void @test_arg_array([8 x i8] *%0) nounwind { +define void @test_arg_array(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_array ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -212,13 +212,13 @@ define void @test_arg_array([8 x i8] *%0) nounwind { ; CHECK-NEXT: CALLb @arg_array_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - %2 = load [8 x i8], [8 x i8]* %0 + %2 = load [8 x i8], ptr %0 call void @arg_array_callee([8 x i8] %2) ret void } -declare void @arg_pass_struct_by_ptr_callee(%struct.A*) -define void @test_arg_pass_struct_by_ptr(%struct.A *%0) nounwind { +declare void @arg_pass_struct_by_ptr_callee(ptr) +define void @test_arg_pass_struct_by_ptr(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_pass_struct_by_ptr ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -231,12 +231,12 @@ define void @test_arg_pass_struct_by_ptr(%struct.A *%0) nounwind { ; CHECK-NEXT: CALLb @arg_pass_struct_by_ptr_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 4, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_struct_by_ptr_callee(%struct.A *%0) + call void @arg_pass_struct_by_ptr_callee(ptr %0) ret void } -declare void @arg_pass_integer_byval_callee(i32* byval(i32), i16* byval(i16), i8* byval(i8)) -define void @test_arg_pass_integer_byval(i32 *%0, i16 *%1, i8 *%2) nounwind { +declare void @arg_pass_integer_byval_callee(ptr byval(i32), ptr byval(i16), ptr byval(i8)) +define void @test_arg_pass_integer_byval(ptr %0, ptr %1, ptr %2) nounwind { ; CHECK-LABEL: name: test_arg_pass_integer_byval ; CHECK: bb.1 (%ir-block.3): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.2 @@ -264,12 +264,12 @@ define void @test_arg_pass_integer_byval(i32 *%0, i16 *%1, i8 *%2) nounwind { ; CHECK-NEXT: CALLb @arg_pass_integer_byval_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 12, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_integer_byval_callee(i32* byval(i32) %0, i16* byval(i16) %1, i8* byval(i8) %2) + call void @arg_pass_integer_byval_callee(ptr byval(i32) %0, ptr byval(i16) %1, ptr byval(i8) %2) ret void } -declare void @arg_pass_struct_byval_callee(%struct.A* byval(%struct.A)) -define void @test_arg_pass_struct_byval(%struct.A *%0) nounwind { +declare void @arg_pass_struct_byval_callee(ptr byval(%struct.A)) +define void @test_arg_pass_struct_byval(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_pass_struct_byval ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -283,12 +283,12 @@ define void @test_arg_pass_struct_byval(%struct.A *%0) nounwind { ; CHECK-NEXT: CALLb @arg_pass_struct_byval_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 8, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_struct_byval_callee(%struct.A* byval(%struct.A) %0) + call void @arg_pass_struct_byval_callee(ptr byval(%struct.A) %0) ret void } -declare void @arg_pass_array_byval_callee([32 x i8]* byval([32 x i8])) -define void @test_arg_pass_array_byval([32 x i8] *%0) nounwind { +declare void @arg_pass_array_byval_callee(ptr byval([32 x i8])) +define void @test_arg_pass_array_byval(ptr %0) nounwind { ; CHECK-LABEL: name: test_arg_pass_array_byval ; CHECK: bb.1 (%ir-block.1): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 @@ -302,11 +302,11 @@ define void @test_arg_pass_array_byval([32 x i8] *%0) nounwind { ; CHECK-NEXT: CALLb @arg_pass_array_byval_callee, csr_std, implicit $sp ; CHECK-NEXT: ADJCALLSTACKUP 32, 0, implicit-def $sp, implicit-def $ccr, implicit $sp ; CHECK-NEXT: RTS - call void @arg_pass_array_byval_callee([32 x i8]* byval([32 x i8]) %0) + call void @arg_pass_array_byval_callee(ptr byval([32 x i8]) %0) ret void } -define void @test_indirect_call(void() *%fptr) nounwind { +define void @test_indirect_call(ptr %fptr) nounwind { ; CHECK-LABEL: name: test_indirect_call ; CHECK: bb.1 (%ir-block.0): ; CHECK-NEXT: [[FRAME_INDEX:%[0-9]+]]:_(p0) = G_FRAME_INDEX %fixed-stack.0 diff --git a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll index 1dd258599135452196d488f8c3a0f4b702ad08d1..0504792c3fceb796434139f2046696acdd119fba 100644 --- a/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll +++ b/llvm/test/CodeGen/M68k/GlobalISel/irtranslator-ret.ll @@ -140,7 +140,7 @@ define void @test_arg_lowering_multiple(i1 %a, i8 %b, i16 %c, i32 %d, i64 %e, i1 ret void } -define void @test_arg_lowering_ptr(i32* %x) { +define void @test_arg_lowering_ptr(ptr %x) { ; CHECK-LABEL: name: test_arg_lowering_ptr ; CHECK: bb.1 (%ir-block.0): ; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX @@ -149,7 +149,7 @@ define void @test_arg_lowering_ptr(i32* %x) { ret void } -define void @test_arg_lowering_float_ptr(float* %x) { +define void @test_arg_lowering_float_ptr(ptr %x) { ; CHECK-LABEL: name: test_arg_lowering_float_ptr ; CHECK: bb.1 (%ir-block.0): ; CHECK: [[G_F_I1:%[0-9]+]]:_(p0) = G_FRAME_INDEX diff --git a/llvm/test/CodeGen/M68k/inline-asm.ll b/llvm/test/CodeGen/M68k/inline-asm.ll index 72cdfb78e82d341612ec46c973dc1116c99f1c88..dda943920788d4b1e7fb1880c904d8e935478507 100644 --- a/llvm/test/CodeGen/M68k/inline-asm.ll +++ b/llvm/test/CodeGen/M68k/inline-asm.ll @@ -114,11 +114,11 @@ define void @register_constraints() { entry: %out = alloca i32, align 4 %0 = call i32 asm sideeffect "move.l #94, $0", "=r"() - store i32 %0, i32* %out, align 4 + store i32 %0, ptr %out, align 4 %1 = call i32 asm sideeffect "move.l #87, $0", "=d"() - store i32 %1, i32* %out, align 4 + store i32 %1, ptr %out, align 4 %2 = call i32 asm sideeffect "move.l #66, $0", "=a"() - store i32 %2, i32* %out, align 4 + store i32 %2, ptr %out, align 4 ret void } diff --git a/llvm/test/CodeGen/M68k/link-unlnk.ll b/llvm/test/CodeGen/M68k/link-unlnk.ll index 530f01b56998fd14f926bf523fb924dddfec8c7e..dfdd80e66ade7871cea5f278cacde323bf98c93f 100644 --- a/llvm/test/CodeGen/M68k/link-unlnk.ll +++ b/llvm/test/CodeGen/M68k/link-unlnk.ll @@ -59,8 +59,8 @@ entry: %arr = alloca [8 x i32], align 4 %s0 = getelementptr i32, ptr %arr, i32 0 %s1 = getelementptr i32, ptr %arr, i32 1 - store i32 %a, i32* %s0 - store i32 %b, i32* %s1 + store i32 %a, ptr %s0 + store i32 %b, ptr %s1 %ptr0 = getelementptr i32, ptr %arr, i32 0 %ptr1 = getelementptr i32, ptr %arr, i32 1 @@ -71,26 +71,26 @@ entry: %ptr6 = getelementptr i32, ptr %arr, i32 6 %ptr7 = getelementptr i32, ptr %arr, i32 7 - %res0 = load i32, i32 * %ptr0 - %res1 = load i32, i32 * %ptr1 + %res0 = load i32, ptr %ptr0 + %res1 = load i32, ptr %ptr1 %res2 = add i32 %res0, %res1 - store i32 %res2, i32 * %ptr2 + store i32 %res2, ptr %ptr2 %res3 = add i32 %res1, %res2 - store i32 %res3, i32 * %ptr3 + store i32 %res3, ptr %ptr3 %res4 = add i32 %res2, %res3 - store i32 %res4, i32 * %ptr4 + store i32 %res4, ptr %ptr4 %res5 = add i32 %res3, %res4 - store i32 %res5, i32 * %ptr5 + store i32 %res5, ptr %ptr5 %res6 = add i32 %res4, %res5 - store i32 %res6, i32 * %ptr6 + store i32 %res6, ptr %ptr6 %res7 = add i32 %res5, %res6 - store i32 %res7, i32 * %ptr7 + store i32 %res7, ptr %ptr7 ret i32 %res7 } @@ -122,8 +122,8 @@ define i32 @test_gep() { entry: %arr = alloca [8 x [8 x i32]] %ptr1 = getelementptr [8 x i32], ptr %arr, i64 0, i64 0 - store i32 12, i32 * %ptr1 + store i32 12, ptr %ptr1 %ptr2 = getelementptr [8 x i32], ptr %arr, i64 7, i64 7 - store i32 21, i32 * %ptr2 + store i32 21, ptr %ptr2 ret i32 0 } diff --git a/llvm/test/CodeGen/M68k/reserved-regs.ll b/llvm/test/CodeGen/M68k/reserved-regs.ll index 04acaf679792551624f160f5a45ad81ca20e5766..553e6c8faaed2420808e7266155b12796a5f2f57 100644 --- a/llvm/test/CodeGen/M68k/reserved-regs.ll +++ b/llvm/test/CodeGen/M68k/reserved-regs.ll @@ -26,27 +26,27 @@ ; Which is copied from `test/CodeGen/RISCV/reserved-regs.ll`. ; But currently we have problem doing codegen for the above snippet ; (https://bugs.llvm.org/show_bug.cgi?id=50377). -define void @foo(i32* nocapture readonly %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32* nocapture readonly %d, - i32* nocapture readonly %a1, i32* nocapture readonly %b1, i32* nocapture readonly %c1, i32* nocapture readonly %d1, - i32* nocapture readonly %a2, i32* nocapture readonly %b2, i32* nocapture readonly %c2, i32* nocapture readonly %d2, - i32* nocapture readonly %a3, i32* nocapture readonly %b3, i32* nocapture readonly %c3, i32* nocapture readonly %d3) { +define void @foo(ptr nocapture readonly %a, ptr nocapture readonly %b, ptr nocapture readonly %c, ptr nocapture readonly %d, + ptr nocapture readonly %a1, ptr nocapture readonly %b1, ptr nocapture readonly %c1, ptr nocapture readonly %d1, + ptr nocapture readonly %a2, ptr nocapture readonly %b2, ptr nocapture readonly %c2, ptr nocapture readonly %d2, + ptr nocapture readonly %a3, ptr nocapture readonly %b3, ptr nocapture readonly %c3, ptr nocapture readonly %d3) { entry: - %0 = load i32, i32* %a, align 4 - %1 = load i32, i32* %b, align 4 - %2 = load i32, i32* %c, align 4 - %3 = load i32, i32* %d, align 4 - %4 = load i32, i32* %a1, align 4 - %5 = load i32, i32* %b1, align 4 - %6 = load i32, i32* %c1, align 4 - %7 = load i32, i32* %d1, align 4 - %8 = load i32, i32* %a2, align 4 - %9 = load i32, i32* %b2, align 4 - %10 = load i32, i32* %c2, align 4 - %11 = load i32, i32* %d2, align 4 - %12 = load i32, i32* %a3, align 4 - %13 = load i32, i32* %b3, align 4 - %14 = load i32, i32* %c3, align 4 - %15 = load i32, i32* %d3, align 4 + %0 = load i32, ptr %a, align 4 + %1 = load i32, ptr %b, align 4 + %2 = load i32, ptr %c, align 4 + %3 = load i32, ptr %d, align 4 + %4 = load i32, ptr %a1, align 4 + %5 = load i32, ptr %b1, align 4 + %6 = load i32, ptr %c1, align 4 + %7 = load i32, ptr %d1, align 4 + %8 = load i32, ptr %a2, align 4 + %9 = load i32, ptr %b2, align 4 + %10 = load i32, ptr %c2, align 4 + %11 = load i32, ptr %d2, align 4 + %12 = load i32, ptr %a3, align 4 + %13 = load i32, ptr %b3, align 4 + %14 = load i32, ptr %c3, align 4 + %15 = load i32, ptr %d3, align 4 ; A0-NOT: %a0 ; A1-NOT: %a1 ; A2-NOT: %a2 diff --git a/llvm/test/CodeGen/M68k/varargs.ll b/llvm/test/CodeGen/M68k/varargs.ll index c04bfdd404779d78fdc5d9583d3cab117ed7fe5b..dae72edc6a34825d9d2d4c16b1f4b076cb38064e 100644 --- a/llvm/test/CodeGen/M68k/varargs.ll +++ b/llvm/test/CodeGen/M68k/varargs.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc < %s -mtriple=m68k-linux -verify-machineinstrs | FileCheck %s -%struct.va_list = type { i8* } +%struct.va_list = type { ptr } define i32 @test(i32 %X, ...) { ; Initialize variable argument processing @@ -19,23 +19,23 @@ define i32 @test(i32 %X, ...) { ; CHECK-NEXT: adda.l #8, %sp ; CHECK-NEXT: rts %ap = alloca %struct.va_list - %ap2 = bitcast %struct.va_list* %ap to i8* - call void @llvm.va_start(i8* %ap2) + %ap2 = bitcast ptr %ap to ptr + call void @llvm.va_start(ptr %ap2) ; Read a single integer argument - %tmp = va_arg i8* %ap2, i32 + %tmp = va_arg ptr %ap2, i32 ; Demonstrate usage of llvm.va_copy and llvm.va_end - %aq = alloca i8* - %aq2 = bitcast i8** %aq to i8* - call void @llvm.va_copy(i8* %aq2, i8* %ap2) - call void @llvm.va_end(i8* %aq2) + %aq = alloca ptr + %aq2 = bitcast ptr %aq to ptr + call void @llvm.va_copy(ptr %aq2, ptr %ap2) + call void @llvm.va_end(ptr %aq2) ; Stop processing of arguments. - call void @llvm.va_end(i8* %ap2) + call void @llvm.va_end(ptr %ap2) ret i32 %tmp } -declare void @llvm.va_start(i8*) -declare void @llvm.va_copy(i8*, i8*) -declare void @llvm.va_end(i8*) +declare void @llvm.va_start(ptr) +declare void @llvm.va_copy(ptr, ptr) +declare void @llvm.va_end(ptr) diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll b/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll index 9e64d7b2fa039ba559fb8c0bfce9873e672ee3dd..c276515920d52ab50d1fbe48b2dc31b67260989a 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/pr40325.ll @@ -11,7 +11,7 @@ define void @test(i32 %x, ptr %p) nounwind { ; CHECK-NEXT: andi $1, $4, 1 ; CHECK-NEXT: bgtz $1, $BB0_1 ; CHECK-NEXT: nop -; CHECK-NEXT: # %bb.1: # %foo +; CHECK-NEXT: $BB0_1: # %foo ; CHECK-NEXT: jr $ra ; CHECK-NEXT: nop %y = and i32 %x, 1 diff --git a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll index 4c10fedaa4a8849144acc5ef8521f8ee18844028..74765ff0e8f106dcdb2e6d2342f3c1832d8509f8 100644 --- a/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll +++ b/llvm/test/CodeGen/Mips/GlobalISel/llvm-ir/jump_table_and_brjt.ll @@ -25,7 +25,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32-NEXT: sltu $1, $1, $2 ; MIPS32-NEXT: bnez $1, $BB0_6 ; MIPS32-NEXT: nop -; MIPS32-NEXT: $BB0_1: # %entry +; MIPS32-NEXT: # %bb.1: # %entry ; MIPS32-NEXT: lw $2, 28($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lui $1, %hi($JTI0_0) ; MIPS32-NEXT: sll $2, $2, 2 @@ -65,7 +65,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32-NEXT: sltu $1, $1, $2 ; MIPS32-NEXT: bnez $1, $BB0_13 ; MIPS32-NEXT: nop -; MIPS32-NEXT: $BB0_8: # %sw.epilog +; MIPS32-NEXT: # %bb.8: # %sw.epilog ; MIPS32-NEXT: lw $2, 0($sp) # 4-byte Folded Reload ; MIPS32-NEXT: lui $1, %hi($JTI0_1) ; MIPS32-NEXT: sll $2, $2, 2 @@ -125,7 +125,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32_PIC-NEXT: sltu $1, $1, $2 ; MIPS32_PIC-NEXT: bnez $1, $BB0_6 ; MIPS32_PIC-NEXT: nop -; MIPS32_PIC-NEXT: $BB0_1: # %entry +; MIPS32_PIC-NEXT: # %bb.1: # %entry ; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $3, 36($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $1, %got($JTI0_0)($2) @@ -167,7 +167,7 @@ define i32 @mod4_0_to_11(i32 %a) { ; MIPS32_PIC-NEXT: sltu $1, $1, $2 ; MIPS32_PIC-NEXT: bnez $1, $BB0_13 ; MIPS32_PIC-NEXT: nop -; MIPS32_PIC-NEXT: $BB0_8: # %sw.epilog +; MIPS32_PIC-NEXT: # %bb.8: # %sw.epilog ; MIPS32_PIC-NEXT: lw $2, 8($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $3, 4($sp) # 4-byte Folded Reload ; MIPS32_PIC-NEXT: lw $1, %got($JTI0_1)($2) diff --git a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll index cbd8b2370ac9694f7ca36ea99944941f99f45dd5..de61515cff9bcbcb2aae25edce5991915e47bcb0 100644 --- a/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll +++ b/llvm/test/CodeGen/Mips/compactbranches/unsafe-in-forbidden-slot.ll @@ -18,7 +18,7 @@ sw.bb: ; preds = %entry br label %sw.epilog ; CHECK: beqzc ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB +; CHECK-NEXT: # %bb.1 ; CHECK-NEXT: j sw.bb1: ; preds = %entry, %entry @@ -26,7 +26,7 @@ sw.bb1: ; preds = %entry, %entry br label %sw.epilog ; CHECK: bnezc ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB +; CHECK-NEXT: # %bb.3 ; CHECK-NEXT: j sw.epilog: ; preds = %entry, %sw.bb1, %sw.bb diff --git a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll index 1ce46cfa07cf87fec8f5dc25a401b57e1da08ed7..634216027ef6bb130925eeb5b8857287f0a85390 100644 --- a/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll +++ b/llvm/test/CodeGen/Mips/indirect-jump-hazard/jumptables.ll @@ -42,7 +42,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS32R2-NEXT: sltiu $1, $4, 7 ; MIPS32R2-NEXT: beqz $1, $BB0_6 ; MIPS32R2-NEXT: sw $4, 4($sp) -; MIPS32R2-NEXT: $BB0_1: # %entry +; MIPS32R2-NEXT: # %bb.1: # %entry ; MIPS32R2-NEXT: sll $1, $4, 2 ; MIPS32R2-NEXT: lui $2, %hi($JTI0_0) ; MIPS32R2-NEXT: addu $1, $1, $2 @@ -100,7 +100,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS32R6-NEXT: sltiu $1, $4, 7 ; MIPS32R6-NEXT: beqz $1, $BB0_6 ; MIPS32R6-NEXT: sw $4, 4($sp) -; MIPS32R6-NEXT: $BB0_1: # %entry +; MIPS32R6-NEXT: # %bb.1: # %entry ; MIPS32R6-NEXT: sll $1, $4, 2 ; MIPS32R6-NEXT: lui $2, %hi($JTI0_0) ; MIPS32R6-NEXT: addu $1, $1, $2 @@ -159,7 +159,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS64R2-NEXT: sltiu $1, $2, 7 ; MIPS64R2-NEXT: beqz $1, .LBB0_6 ; MIPS64R2-NEXT: sw $4, 4($sp) -; MIPS64R2-NEXT: .LBB0_1: # %entry +; MIPS64R2-NEXT: # %bb.1: # %entry ; MIPS64R2-NEXT: dsll $1, $2, 3 ; MIPS64R2-NEXT: lui $2, %highest(.LJTI0_0) ; MIPS64R2-NEXT: daddiu $2, $2, %higher(.LJTI0_0) @@ -254,7 +254,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; MIPS64R6-NEXT: sltiu $1, $2, 7 ; MIPS64R6-NEXT: beqz $1, .LBB0_6 ; MIPS64R6-NEXT: sw $4, 4($sp) -; MIPS64R6-NEXT: .LBB0_1: # %entry +; MIPS64R6-NEXT: # %bb.1: # %entry ; MIPS64R6-NEXT: dsll $1, $2, 3 ; MIPS64R6-NEXT: lui $2, %highest(.LJTI0_0) ; MIPS64R6-NEXT: daddiu $2, $2, %higher(.LJTI0_0) @@ -351,7 +351,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS32R2-NEXT: sltiu $1, $4, 7 ; PIC-MIPS32R2-NEXT: beqz $1, $BB0_6 ; PIC-MIPS32R2-NEXT: sw $4, 4($sp) -; PIC-MIPS32R2-NEXT: $BB0_1: # %entry +; PIC-MIPS32R2-NEXT: # %bb.1: # %entry ; PIC-MIPS32R2-NEXT: sll $1, $4, 2 ; PIC-MIPS32R2-NEXT: lw $3, %got($JTI0_0)($2) ; PIC-MIPS32R2-NEXT: addu $1, $1, $3 @@ -413,7 +413,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS32R6-NEXT: sltiu $1, $4, 7 ; PIC-MIPS32R6-NEXT: beqz $1, $BB0_6 ; PIC-MIPS32R6-NEXT: sw $4, 4($sp) -; PIC-MIPS32R6-NEXT: $BB0_1: # %entry +; PIC-MIPS32R6-NEXT: # %bb.1: # %entry ; PIC-MIPS32R6-NEXT: sll $1, $4, 2 ; PIC-MIPS32R6-NEXT: lw $3, %got($JTI0_0)($2) ; PIC-MIPS32R6-NEXT: addu $1, $1, $3 @@ -476,7 +476,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS64R2-NEXT: sltiu $1, $3, 7 ; PIC-MIPS64R2-NEXT: beqz $1, .LBB0_6 ; PIC-MIPS64R2-NEXT: sw $4, 4($sp) -; PIC-MIPS64R2-NEXT: .LBB0_1: # %entry +; PIC-MIPS64R2-NEXT: # %bb.1: # %entry ; PIC-MIPS64R2-NEXT: dsll $1, $3, 3 ; PIC-MIPS64R2-NEXT: ld $3, %got_page(.LJTI0_0)($2) ; PIC-MIPS64R2-NEXT: daddu $1, $1, $3 @@ -539,7 +539,7 @@ define ptr @_Z3fooi(i32 signext %Letter) { ; PIC-MIPS64R6-NEXT: sltiu $1, $3, 7 ; PIC-MIPS64R6-NEXT: beqz $1, .LBB0_6 ; PIC-MIPS64R6-NEXT: sw $4, 4($sp) -; PIC-MIPS64R6-NEXT: .LBB0_1: # %entry +; PIC-MIPS64R6-NEXT: # %bb.1: # %entry ; PIC-MIPS64R6-NEXT: dsll $1, $3, 3 ; PIC-MIPS64R6-NEXT: ld $3, %got_page(.LJTI0_0)($2) ; PIC-MIPS64R6-NEXT: daddu $1, $1, $3 diff --git a/llvm/test/CodeGen/Mips/jump-table-mul.ll b/llvm/test/CodeGen/Mips/jump-table-mul.ll index 22f41f53d154bf29b72c347b94bb9ef5f0e5c326..cca6080a07544cc8a4ec16633684b38401e29968 100644 --- a/llvm/test/CodeGen/Mips/jump-table-mul.ll +++ b/llvm/test/CodeGen/Mips/jump-table-mul.ll @@ -10,7 +10,7 @@ define i64 @test(i64 %arg) { ; CHECK-NEXT: sltiu $1, $4, 11 ; CHECK-NEXT: beqz $1, .LBB0_4 ; CHECK-NEXT: nop -; CHECK-NEXT: .LBB0_1: # %entry +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: daddiu $1, $2, %lo(%neg(%gp_rel(test))) ; CHECK-NEXT: dsll $2, $4, 3 ; CHECK-NEXT: ld $3, %got_page(.LJTI0_0)($1) diff --git a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll index afb79e55f4f90b803442f82e4b0e92ce13c2effa..5d7cdbc0b69edff7b3a53ab5765c1ae1021e0ce0 100644 --- a/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll +++ b/llvm/test/CodeGen/Mips/pseudo-jump-fill.ll @@ -14,7 +14,7 @@ define i32 @test(i32 signext %x, i32 signext %c) { ; CHECK-NEXT: sltiu $1, $5, 4 ; CHECK-NEXT: beqz $1, $BB0_6 ; CHECK-NEXT: addu $3, $2, $25 -; CHECK-NEXT: $BB0_1: # %entry +; CHECK-NEXT: # %bb.1: # %entry ; CHECK-NEXT: li16 $2, 0 ; CHECK-NEXT: sll16 $5, $5, 2 ; CHECK-NEXT: lw $6, %got($JTI0_0)($3) diff --git a/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll b/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll index b8299148cd8d63c06714e7d6dc3ea87671da6035..0993a243f73bd47e28e3d6cfd7905387bb8a2a66 100644 --- a/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll +++ b/llvm/test/CodeGen/PowerPC/aix-alias-alignment-2.ll @@ -58,7 +58,7 @@ define void @foo3(%struct.B %a1) { ; ASM-NEXT: .vbyte 4, 34 ; SYM: SYMBOL TABLE: -; SYM-NEXT: 00000000 df *DEBUG* 00000000 +; SYM-NEXT: 00000000 df *DEBUG* 00000000 .file ; SYM-NEXT: 00000000 l .text 0000008a ; SYM-NEXT: 00000000 g F .text (csect: ) 00000000 .foo1 ; SYM-NEXT: 00000030 g F .text (csect: ) 00000000 .foo2 diff --git a/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll b/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll index 8bfc5139aa7479b31e585803ef7144a71b5bbb09..7e51f4173aa8aedbe35df46d3216d8b0401aafe3 100644 --- a/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll +++ b/llvm/test/CodeGen/PowerPC/aix-alias-alignment.ll @@ -61,7 +61,7 @@ define void @foo(i32 %a1, i32 %a2, i32 %a3) { ; OBJ-NEXT: c: 4e 80 00 20 blr ; SYM: SYMBOL TABLE: -; SYM-NEXT: 00000000 df *DEBUG* 00000000 +; SYM-NEXT: 00000000 df *DEBUG* 00000000 .file ; SYM-NEXT: 00000000 l .text 00000029 ; SYM-NEXT: 00000000 g F .text (csect: ) 00000000 .foo ; SYM-NEXT: 0000002c l .data 00000008 .data diff --git a/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll b/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll index f87184f7b4bf45ea3b2f0835e8ec292bb6160e68..0ad229004b8a3de2d91594d1dffc34d6d07252b3 100644 --- a/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll +++ b/llvm/test/CodeGen/PowerPC/aix-available-externally-linkage-fun.ll @@ -6,11 +6,11 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefix=OBJ %s +; RUN: llvm-readobj --symbols %t.o | FileCheck -D#NFA=2 --check-prefix=OBJ %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefix=OBJ %s +; RUN: llvm-readobj --symbols %t64.o | FileCheck -D#NFA=2 --check-prefix=OBJ %s define available_externally i32 @foo(i32 %a) { entry: @@ -27,7 +27,7 @@ entry: ; OBJ-NEXT: StorageClass: C_EXT (0x2) ; OBJ-NEXT: NumberOfAuxEntries: 1 ; OBJ-NEXT: CSECT Auxiliary Entry { -; OBJ-NEXT: Index: 2 +; OBJ-NEXT: Index: [[#NFA+2]] ; OBJ-NEXT: SectionLen: 0 ; OBJ-NEXT: ParameterHashIndex: 0x0 ; OBJ-NEXT: TypeChkSectNum: 0x0 @@ -42,7 +42,7 @@ entry: ; OBJ-NEXT: StorageClass: C_EXT (0x2) ; OBJ-NEXT: NumberOfAuxEntries: 1 ; OBJ-NEXT: CSECT Auxiliary Entry { -; OBJ-NEXT: Index: 4 +; OBJ-NEXT: Index: [[#NFA+4]] ; OBJ-NEXT: SectionLen: 0 ; OBJ-NEXT: ParameterHashIndex: 0x0 ; OBJ-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll index 11b6827c33b1ec091f91cad4f5bb486682e42fa6..ea61fdb022b5c58883acc14c3d9a592fdc5e37f1 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern-weak.ll @@ -65,16 +65,15 @@ declare extern_weak void @foo_ext_weak(ptr) ; CHECKSYM: Symbols [ ; CHECKSYM-NEXT: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: [[#Index:]] ; CHECKSYM-NEXT: Name: .foo_ext_weak ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-extern.ll b/llvm/test/CodeGen/PowerPC/aix-extern.ll index 905e458473905f147093c40de70c6f0070dad968..b4366dddedb2feac412527f932ffc4c0dfb8136d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-extern.ll +++ b/llvm/test/CodeGen/PowerPC/aix-extern.ll @@ -88,16 +88,15 @@ declare i32 @bar_extern(ptr) ; CHECKSYM: Symbols [ ; CHECKSYM-NEXT: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: [[#Index:]] ; CHECKSYM-NEXT: Name: .bar_extern ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll index 2adc51cc2aeccd939f661869e669cb254e9d62eb..c4202a0c58cee3cf041ff4873fb83f74dd767709 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-c.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-c.ll @@ -5,7 +5,8 @@ source_filename = "1.c" -; OBJ: Name: 1.c +; OBJ: Name: .file ; OBJ: Source Language ID: TB_C (0x0) ; OBJ32: CPU Version ID: TCPU_COM (0x3) ; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: Name: 1.c diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll index 22496be1dfc888ba63c4938ece547cfd5208d675..802281b6c1eaa443759a89f3622eb8cfaeedbec9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-cpp.ll @@ -5,7 +5,8 @@ source_filename = "1.cpp" -; OBJ: Name: 1.cpp +; OBJ: Name: .file ; OBJ: Source Language ID: TB_CPLUSPLUS (0x9) ; OBJ32: CPU Version ID: TCPU_COM (0x3) ; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: Name: 1.cpp diff --git a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll index 914c4facc3cf55d8472cad613aa5670afb2d69ff..99036bde702d6e584edab7a57ac5e83895177eb7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-filename-f.ll +++ b/llvm/test/CodeGen/PowerPC/aix-filename-f.ll @@ -5,7 +5,8 @@ source_filename = "1.f95" -; OBJ: Name: 1.f95 +; OBJ: Name: .file ; OBJ: Source Language ID: TB_Fortran (0x1) ; OBJ32: CPU Version ID: TCPU_COM (0x3) ; OBJ64: CPU Version ID: TCPU_PPC64 (0x2) +; OBJ: Name: 1.f95 diff --git a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll index 23fb51e9444243995b3294540825c9f84babf866..4cca1b4d6f7bad628ee37f09e1dfed0d48f67dfa 100644 --- a/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll +++ b/llvm/test/CodeGen/PowerPC/aix-func-dsc-gen.ll @@ -13,13 +13,23 @@ entry: ; CHECK-NEXT: AddressSize: 32bit ; CHECK: Symbol { ; CHECK-NEXT: Index: 0 -; CHECK-NEXT: Name: +; CHECK-NEXT: Name: .file ; CHECK-NEXT: Value (SymbolTableIndex): 0x0 ; CHECK-NEXT: Section: N_DEBUG ; CHECK-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECK-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECK-NEXT: StorageClass: C_FILE (0x67) -; CHECK-NEXT: NumberOfAuxEntries: 0 +; CHECK-NEXT: NumberOfAuxEntries: 2 +; CHECK-NEXT: File Auxiliary Entry { +; CHECK-NEXT: Index: 1 +; CHECK-NEXT: Name: +; CHECK-NEXT: Type: XFT_FN (0x0) +; CHECK-NEXT: } +; CHECK-NEXT: File Auxiliary Entry { +; CHECK-NEXT: Index: 2 +; CHECK-NEXT: Name: LLVM +; CHECK-NEXT: Type: XFT_CV (0x2) +; CHECK-NEXT: } ; CHECK-NEXT: } ; CHECK-NEXT: Symbol { ; CHECK-NEXT: Index: [[#Index:]] diff --git a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll index 09aec55a5b3dfb4fab85ee42195ee735d0f14f52..50677f36e3f7a80280e2bd45aee60b93f53900de 100644 --- a/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll +++ b/llvm/test/CodeGen/PowerPC/aix-llvm-intrinsic.ll @@ -7,12 +7,12 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --symbols %t.o | FileCheck --check-prefixes=CHECKSYM,CHECKSYM32 %s -; RUN: llvm-objdump -r -d --symbol-description %t.o | FileCheck --check-prefixes=CHECKRELOC,CHECKRELOC32 %s +; RUN: llvm-objdump -r -d --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefixes=CHECKRELOC,CHECKRELOC32 %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -o %t64.o < %s ; RUN: llvm-readobj --symbols %t64.o | FileCheck --check-prefixes=CHECKSYM,CHECKSYM64 %s -; RUN: llvm-objdump -r -d --symbol-description %t64.o | FileCheck --check-prefixes=CHECKRELOC,CHECKRELOC64 %s +; RUN: llvm-objdump -r -d --symbol-description %t64.o | FileCheck -D#NFA=2 --check-prefixes=CHECKRELOC,CHECKRELOC64 %s %struct.S = type { i32, i32 } @@ -40,17 +40,17 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { -; CHECKSYM-NEXT: Index: 1 +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: } +; CHECKSYM: Symbol { +; CHECKSYM: Index: 3 ; CHECKSYM32-NEXT: Name: .___memset ; CHECKSYM64-NEXT: Name: .___memset64 ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 @@ -59,7 +59,7 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM-NEXT: StorageClass: C_EXT (0x2) ; CHECKSYM-NEXT: NumberOfAuxEntries: 1 ; CHECKSYM-NEXT: CSECT Auxiliary Entry { -; CHECKSYM-NEXT: Index: 2 +; CHECKSYM-NEXT: Index: 4 ; CHECKSYM-NEXT: SectionLen: 0 ; CHECKSYM-NEXT: ParameterHashIndex: 0x0 ; CHECKSYM-NEXT: TypeChkSectNum: 0x0 @@ -72,19 +72,19 @@ declare void @llvm.memset.p0.i32(ptr nocapture writeonly, i8, i32, i1 immarg) ; CHECKSYM-NEXT: } ; CHECKSYM-NEXT: } -; CHECKRELOC32: 00000000 (idx: 7) .bar: -; CHECKRELOC64: 0000000000000000 (idx: 7) .bar: +; CHECKRELOC32: 00000000 (idx: [[#NFA+7]]) .bar: +; CHECKRELOC64: 0000000000000000 (idx: [[#NFA+7]]) .bar: ; CHECKRELOC-NEXT: 0: 7c 08 02 a6 mflr 0 ; CHECKRELOC32-NEXT: 4: 94 21 ff c0 stwu 1, -64(1) ; CHECKRELOC32-NEXT: 8: 80 62 00 00 lwz 3, 0(2) -; CHECKRELOC32-NEXT: 0000000a: R_TOC (idx: 13) s[TC] +; CHECKRELOC32-NEXT: 0000000a: R_TOC (idx: [[#NFA+13]]) s[TC] ; CHECKRELOC32-NEXT: c: 90 01 00 48 stw 0, 72(1) ; CHECKRELOC64-NEXT: 4: f8 21 ff 91 stdu 1, -112(1) ; CHECKRELOC64-NEXT: 8: e8 62 00 00 ld 3, 0(2) -; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: 13) s[TC] +; CHECKRELOC64-NEXT: 000000000000000a: R_TOC (idx: [[#NFA+13]]) s[TC] ; CHECKRELOC64-NEXT: c: f8 01 00 80 std 0, 128(1) ; CHECKRELOC-NEXT: 10: 80 83 00 04 lwz 4, 4(3) ; CHECKRELOC-NEXT: 14: 7c 85 23 78 mr 5, 4 ; CHECKRELOC-NEXT: 18: 4b ff ff e9 bl 0x0 -; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: 1) .___memset[PR] -; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: 1) .___memset64[PR] +; CHECKRELOC32-NEXT: 00000018: R_RBR (idx: [[#NFA+1]]) .___memset[PR] +; CHECKRELOC64-NEXT: 0000000000000018: R_RBR (idx: [[#NFA+1]]) .___memset64[PR] diff --git a/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py b/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py index a5fbb81b8d9efa47e677dcd5a5ba2a3bf417f482..84438c3552e5ccbdc2c8f76e46a58363ee778cb2 100644 --- a/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py +++ b/llvm/test/CodeGen/PowerPC/aix-overflow-toc.py @@ -9,7 +9,7 @@ # RUN: llc -mtriple powerpc-ibm-aix-xcoff -code-model=small -data-sections=false -mcpu=pwr4 -mattr=-altivec -O0 \ # RUN: -filetype=obj -o %t.o < %t.ll -# RUN: llvm-objdump --no-print-imm-hex -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS32 %s +# RUN: llvm-objdump --no-print-imm-hex -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS32 %s ## FIXME: currently only fileHeader and sectionHeaders are supported in XCOFF64. @@ -48,18 +48,18 @@ print("}") # ASM64: ld 4, L..C12289-131072(2) # @a12289 # DIS32: 0: 80 82 00 00 lwz 4, 0(2) -# DIS32: 00000002: R_TOC (idx: 24591) a0[TC] +# DIS32: 00000002: R_TOC (idx: [[#NFA+24591]]) a0[TC] # DIS32: c: 80 82 00 04 lwz 4, 4(2) -# DIS32: 0000000e: R_TOC (idx: 24593) a1[TC] +# DIS32: 0000000e: R_TOC (idx: [[#NFA+24593]]) a1[TC] # DIS32: fffc: 80 82 7f fc lwz 4, 32764(2) -# DIS32: 0000fffe: R_TOC (idx: 40973) a8191[TC] +# DIS32: 0000fffe: R_TOC (idx: [[#NFA+40973]]) a8191[TC] # DIS32: 10004: 80 82 80 00 lwz 4, -32768(2) -# DIS32: 00010006: R_TOC (idx: 40975) a8192[TC] +# DIS32: 00010006: R_TOC (idx: [[#NFA+40975]]) a8192[TC] # DIS32: 1000c: 80 82 80 04 lwz 4, -32764(2) -# DIS32: 0001000e: R_TOC (idx: 40977) a8193[TC] +# DIS32: 0001000e: R_TOC (idx: [[#NFA+40977]]) a8193[TC] # DIS32: 18004: 80 82 c0 00 lwz 4, -16384(2) -# DIS32: 00018006: R_TOC (idx: 49167) a12288[TC] +# DIS32: 00018006: R_TOC (idx: [[#NFA+49167]]) a12288[TC] # DIS32: 1800c: 80 82 c0 04 lwz 4, -16380(2) -# DIS32: 0001800e: R_TOC (idx: 49169) a12289[TC] +# DIS32: 0001800e: R_TOC (idx: [[#NFA+49169]]) a12289[TC] diff --git a/llvm/test/CodeGen/PowerPC/aix-relro-section.ll b/llvm/test/CodeGen/PowerPC/aix-relro-section.ll index 25be1f0e16f37e203e6431cee94ba58112b1d8c5..5da99191f3d072dc7131cf2ff415b5b93830fdff 100644 --- a/llvm/test/CodeGen/PowerPC/aix-relro-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-relro-section.ll @@ -4,10 +4,10 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -mxcoff-roptr < %s | FileCheck %s --check-prefix CHECK-RO ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ64 @var = external constant i32 @ptr = private constant ptr @var, section "relro-section" @@ -20,11 +20,11 @@ ; OBJ32: Relocations [ ; OBJ32-NEXT: Section (index: 2) .data { -; OBJ32-NEXT: 0x0 R_POS var(1) 0x1F +; OBJ32-NEXT: 0x0 R_POS var([[#NFA+1]]) 0x1F ; OBJ32-NEXT: } ; OBJ32-NEXT: ] ; OBJ32-NEXT: Symbols [ -; OBJ32: Index: 1 +; OBJ32: Index: [[#NFA+1]] ; OBJ32-NEXT: Name: var ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: N_UNDEF @@ -32,7 +32,7 @@ ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Index: [[#NFA+2]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -42,7 +42,7 @@ ; OBJ32-NEXT: StabInfoIndex: 0x0 ; OBJ32-NEXT: StabSectNum: 0x0 ; OBJ32-NEXT: } -; OBJ32: Index: 5 +; OBJ32: Index: [[#NFA+5]] ; OBJ32-NEXT: Name: relro-section ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: .data @@ -50,7 +50,7 @@ ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 6 +; OBJ32-NEXT: Index: [[#NFA+6]] ; OBJ32-NEXT: SectionLen: 4 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -64,11 +64,11 @@ ; OBJ64: Relocations [ ; OBJ64-NEXT: Section (index: 2) .data { -; OBJ64-NEXT: 0x0 R_POS var(1) 0x3F +; OBJ64-NEXT: 0x0 R_POS var([[#NFA+1]]) 0x3F ; OBJ64-NEXT: } ; OBJ64-NEXT: ] ; OBJ64-NEXT: Symbols [ -; OBJ64: Index: 1 +; OBJ64: Index: [[#NFA+1]] ; OBJ64-NEXT: Name: var ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: N_UNDEF @@ -76,7 +76,7 @@ ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Index: [[#NFA+2]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -85,7 +85,7 @@ ; OBJ64-NEXT: StorageMappingClass: XMC_UA (0x4) ; OBJ64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; OBJ64-NEXT: } -; OBJ64: Index: 5 +; OBJ64: Index: [[#NFA+5]] ; OBJ64-NEXT: Name: relro-section ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: .data @@ -93,7 +93,7 @@ ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 6 +; OBJ64-NEXT: Index: [[#NFA+6]] ; OBJ64-NEXT: SectionLen: 8 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll index 22b8503ef403c8ac3d94d9a76dcf8f005f778ca8..67d82c6908d75e38b48fda00ddb2868ccbefef9d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll +++ b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess.ll @@ -11,7 +11,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+aix-small-local-exec-tls \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff -xcoff-traceback-table=false \ ; RUN: --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @mySmallLocalExecTLSv1 = thread_local(localexec) global [8187 x i32] zeroinitializer, align 4 @mySmallLocalExecTLS2 = thread_local(localexec) global [4000 x i32] zeroinitializer, align 4 @@ -152,79 +152,79 @@ entry: ret i32 %add15 } -; DIS: {{.*}}aix-small-local-exec-tls-largeaccess.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: file format aix5coff64-rs6000 ; DIS: Disassembly of section .text: -; DIS: 0000000000000000 (idx: 3) .StoreArrays1: +; DIS: 0000000000000000 (idx: [[#NFA+3]]) .StoreArrays1: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, 0(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 15) mySmallLocalExecTLSv1[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+15]]) mySmallLocalExecTLSv1[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 2 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, 24(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 15) mySmallLocalExecTLSv1[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+15]]) mySmallLocalExecTLSv1[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -32468(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 17) mySmallLocalExecTLS2[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -16464(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 19) mySmallLocalExecTLS3[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+19]]) mySmallLocalExecTLS3[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 88 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, -460(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 21) mySmallLocalExecTLS4[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+21]]) mySmallLocalExecTLS4[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, 15544(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 23) mySmallLocalExecTLS5[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+23]]) mySmallLocalExecTLS5[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 102 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr -; DIS: 0000000000000040 (idx: 5) .StoreArrays2: +; DIS: 0000000000000040 (idx: [[#NFA+5]]) .StoreArrays2: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 13) mySmallLocalExecTLSv2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+13]]) mySmallLocalExecTLSv2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 13) mySmallLocalExecTLSv2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+13]]) mySmallLocalExecTLSv2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, 24(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 2 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -32468(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 17) mySmallLocalExecTLS2[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, -16464(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 19) mySmallLocalExecTLS3[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+19]]) mySmallLocalExecTLS3[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 88 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 4, -460(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 21) mySmallLocalExecTLS4[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+21]]) mySmallLocalExecTLS4[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 3, 15544(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 23) mySmallLocalExecTLS5[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+23]]) mySmallLocalExecTLS5[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 102 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000080 (idx: 7) StoreArrays1[DS]: +; DIS: 0000000000000080 (idx: [[#NFA+7]]) StoreArrays1[DS]: ; DIS-NEXT: 80: 00 00 00 00 -; DIS-NEXT: 0000000000000080: R_POS (idx: 3) .StoreArrays1 +; DIS-NEXT: 0000000000000080: R_POS (idx: [[#NFA+3]]) .StoreArrays1 ; DIS-NEXT: 84: 00 00 00 00 ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 0000000000000088: R_POS (idx: 11) TOC[TC0] +; DIS-NEXT: 0000000000000088: R_POS (idx: [[#NFA+11]]) TOC[TC0] ; DIS-NEXT: 8c: 00 00 00 b0 -; DIS: 0000000000000098 (idx: 9) StoreArrays2[DS]: +; DIS: 0000000000000098 (idx: [[#NFA+9]]) StoreArrays2[DS]: ; DIS-NEXT: 98: 00 00 00 00 -; DIS-NEXT: 0000000000000098: R_POS (idx: 5) .StoreArrays2 +; DIS-NEXT: 0000000000000098: R_POS (idx: [[#NFA+5]]) .StoreArrays2 ; DIS-NEXT: 9c: 00 00 00 40 ; DIS-NEXT: a0: 00 00 00 00 -; DIS-NEXT: 00000000000000a0: R_POS (idx: 11) TOC[TC0] +; DIS-NEXT: 00000000000000a0: R_POS (idx: [[#NFA+11]]) TOC[TC0] ; DIS-NEXT: a4: 00 00 00 b0 -; DIS: 00000000000000b0 (idx: 13) mySmallLocalExecTLSv2[TE]: +; DIS: 00000000000000b0 (idx: [[#NFA+13]]) mySmallLocalExecTLSv2[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: 25) mySmallLocalExecTLSv2[TL] +; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: [[#NFA+25]]) mySmallLocalExecTLSv2[TL] ; DIS-NEXT: b4: 00 01 79 ec ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 15) mySmallLocalExecTLSv1[TL]: -; DIS: 0000000000007fec (idx: 17) mySmallLocalExecTLS2[TL]: -; DIS: 000000000000be6c (idx: 19) mySmallLocalExecTLS3[TL]: -; DIS: 000000000000fcec (idx: 21) mySmallLocalExecTLS4[TL]: -; DIS: 0000000000013b6c (idx: 23) mySmallLocalExecTLS5[TL]: -; DIS: 00000000000179ec (idx: 25) mySmallLocalExecTLSv2[TL]: +; DIS: 0000000000000000 (idx: [[#NFA+15]]) mySmallLocalExecTLSv1[TL]: +; DIS: 0000000000007fec (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL]: +; DIS: 000000000000be6c (idx: [[#NFA+19]]) mySmallLocalExecTLS3[TL]: +; DIS: 000000000000fcec (idx: [[#NFA+21]]) mySmallLocalExecTLS4[TL]: +; DIS: 0000000000013b6c (idx: [[#NFA+23]]) mySmallLocalExecTLS5[TL]: +; DIS: 00000000000179ec (idx: [[#NFA+25]]) mySmallLocalExecTLSv2[TL]: \ No newline at end of file diff --git a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll index 725b6800549264e34c978329fef10f3aaaad582b..f7b99461be5f37cc72f9939a0ac5109e8d3d111d 100644 --- a/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll +++ b/llvm/test/CodeGen/PowerPC/aix-small-local-exec-tls-largeaccess2.ll @@ -11,7 +11,7 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=+aix-small-local-exec-tls \ ; RUN: -mtriple powerpc64-ibm-aix-xcoff -xcoff-traceback-table=false \ ; RUN: --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @mySmallLocalExecTLS6 = external thread_local(localexec) global [60 x i64], align 8 @mySmallLocalExecTLS2 = thread_local(localexec) global [3000 x i64] zeroinitializer, align 8 @@ -105,37 +105,37 @@ entry: ret i64 %add11 } -; DIS: 0000000000000000 (idx: 7) .StoreLargeAccess1: +; DIS: 0000000000000000 (idx: [[#NFA+7]]) .StoreLargeAccess1: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} mflr 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdu 1, -48(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 212 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 0, 64(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 13) MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+13]]) MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 13) MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+13]]) MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 424(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 1) mySmallLocalExecTLS6[UL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+1]]) mySmallLocalExecTLS6[UL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 203 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 1200(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 17) mySmallLocalExecTLS2[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 15) .MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+15]]) .MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 15) .MyTLSGDVar[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+15]]) .MyTLSGDVar[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 3) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+3]]) .__tls_get_addr[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 44 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 4, 440(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 6 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 100 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 32400(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 21) mySmallLocalExecTLS3[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+21]]) mySmallLocalExecTLS3[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 882 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 4, -4336(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 23) mySmallLocalExecTLS4[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+23]]) mySmallLocalExecTLS4[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} std 3, 21264(13) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: 25) mySmallLocalExecTLS5[TL] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TLS_LE (idx: [[#NFA+25]]) mySmallLocalExecTLS5[TL] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 3, 1191 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 1, 1, 48 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 0, 16(1) @@ -143,18 +143,18 @@ entry: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000068 (idx: 9) StoreLargeAccess1[DS]: +; DIS: 0000000000000068 (idx: [[#NFA+9]]) StoreLargeAccess1[DS]: ; DIS-NEXT: 68: 00 00 00 00 -; DIS-NEXT: 0000000000000068: R_POS (idx: 7) .StoreLargeAccess1 +; DIS-NEXT: 0000000000000068: R_POS (idx: [[#NFA+7]]) .StoreLargeAccess1 ; DIS-NEXT: 6c: 00 00 00 00 ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 0000000000000070: R_POS (idx: 11) TOC[TC0] +; DIS-NEXT: 0000000000000070: R_POS (idx: [[#NFA+11]]) TOC[TC0] ; DIS-NEXT: 74: 00 00 00 80 ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 17) mySmallLocalExecTLS2[TL]: -; DIS: 0000000000005dc0 (idx: 19) MyTLSGDVar[TL]: -; DIS: 00000000000076c0 (idx: 21) mySmallLocalExecTLS3[TL]: -; DIS: 000000000000d480 (idx: 23) mySmallLocalExecTLS4[TL]: -; DIS: 0000000000013240 (idx: 25) mySmallLocalExecTLS5[TL]: -; DIS: 0000000000019000 (idx: 27) mySmallLocalExecTLS[TL]: +; DIS: 0000000000000000 (idx: [[#NFA+17]]) mySmallLocalExecTLS2[TL]: +; DIS: 0000000000005dc0 (idx: [[#NFA+19]]) MyTLSGDVar[TL]: +; DIS: 00000000000076c0 (idx: [[#NFA+21]]) mySmallLocalExecTLS3[TL]: +; DIS: 000000000000d480 (idx: [[#NFA+23]]) mySmallLocalExecTLS4[TL]: +; DIS: 0000000000013240 (idx: [[#NFA+25]]) mySmallLocalExecTLS5[TL]: +; DIS: 0000000000019000 (idx: [[#NFA+27]]) mySmallLocalExecTLS[TL]: diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll index e34bb130d5ed21260fbf681d639da13adef83725..46fa52815e9693cfc656ac9ef0f55d3e5fbb24a2 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-ie-xcoff-reloc.ll @@ -1,26 +1,26 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL64 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM64 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS64 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL64 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM64 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc64-ibm-aix-xcoff -code-model=small \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL64 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM64 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS64 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL64 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM64 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL32 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM32 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS32 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL32 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM32 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS32 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mtriple=powerpc-ibm-aix-xcoff -code-model=small \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=REL32 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM32 %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS32 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=REL32 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM32 %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS32 %s @global_int_nonzero = thread_local(initialexec) global i32 1, align 4 @intern_int_zero = internal thread_local(initialexec) global i32 0, align 4 @@ -48,61 +48,60 @@ entry: declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) -; REL64: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; REL64: File: ; REL64-NEXT: Format: aix5coff64-rs6000 ; REL64-NEXT: Arch: powerpc64 ; REL64-NEXT: AddressSize: 64bit ; REL64-NEXT: Relocations [ ; REL64: Virtual Address: 0x2 -; REL64-NEXT: Symbol: intern_int_zero (17) +; REL64-NEXT: Symbol: intern_int_zero ([[#NFA+17]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 16 ; REL64-NEXT: Type: R_TOC (0x3) ; REL64-NEXT: } ; REL64: Virtual Address: 0x12 -; REL64-NEXT: Symbol: global_int_nonzero (19) +; REL64-NEXT: Symbol: global_int_nonzero ([[#NFA+19]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 16 ; REL64-NEXT: Type: R_TOC (0x3) ; REL64-NEXT: } ; REL64: Virtual Address: 0x22 -; REL64-NEXT: Symbol: intern_int_zero (17) +; REL64-NEXT: Symbol: intern_int_zero ([[#NFA+17]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 16 ; REL64-NEXT: Type: R_TOC (0x3) ; REL64-NEXT: } ; REL64: Virtual Address: 0x78 -; REL64-NEXT: Symbol: intern_int_zero (25) +; REL64-NEXT: Symbol: intern_int_zero ([[#NFA+25]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 64 ; REL64-NEXT: Type: R_TLS_IE (0x21) ; REL64-NEXT: } ; REL64: Virtual Address: 0x80 -; REL64-NEXT: Symbol: global_int_nonzero (23) +; REL64-NEXT: Symbol: global_int_nonzero ([[#NFA+23]]) ; REL64-NEXT: IsSigned: No ; REL64-NEXT: FixupBitValue: 0 ; REL64-NEXT: Length: 64 ; REL64-NEXT: Type: R_TLS_IE (0x21) ; REL64-NEXT: } -; SYM64: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; SYM64: File: ; SYM64-NEXT: Format: aix5coff64-rs6000 ; SYM64-NEXT: Arch: powerpc64 ; SYM64-NEXT: AddressSize: 64bit ; SYM64-NEXT: Symbols [ -; SYM64: Index: 17 -; SYM64-NEXT: Name: intern_int_zero +; SYM64: Name: intern_int_zero ; SYM64-NEXT: Value (RelocatableAddress): 0x78 ; SYM64-NEXT: Section: .data ; SYM64-NEXT: Type: 0x0 ; SYM64-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 18 +; SYM64-NEXT: Index: [[#INDX:]] ; SYM64-NEXT: SectionLen: 8 ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 @@ -112,7 +111,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM64-NEXT: } ; SYM64-NEXT: } -; SYM64: Index: 19 +; SYM64: Index: [[#INDX+1]] ; SYM64-NEXT: Name: global_int_nonzero ; SYM64-NEXT: Value (RelocatableAddress): 0x80 ; SYM64-NEXT: Section: .data @@ -120,7 +119,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 20 +; SYM64-NEXT: Index: [[#INDX+2]] ; SYM64-NEXT: SectionLen: 8 ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 @@ -130,7 +129,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM64-NEXT: } ; SYM64-NEXT: } -; SYM64: Index: 23 +; SYM64: Index: [[#INDX+5]] ; SYM64-NEXT: Name: global_int_nonzero ; SYM64-NEXT: Value (RelocatableAddress): 0x0 ; SYM64-NEXT: Section: .tdata @@ -138,8 +137,8 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: StorageClass: C_EXT (0x2) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 24 -; SYM64-NEXT: ContainingCsectSymbolIndex: 21 +; SYM64-NEXT: Index: [[#INDX+6]] +; SYM64-NEXT: ContainingCsectSymbolIndex: [[#INDX+3]] ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 ; SYM64-NEXT: SymbolAlignmentLog2: 0 @@ -148,7 +147,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM64-NEXT: } ; SYM64-NEXT: } -; SYM64: Index: 25 +; SYM64: Index: [[#INDX+7]] ; SYM64-NEXT: Name: intern_int_zero ; SYM64-NEXT: Value (RelocatableAddress): 0x4 ; SYM64-NEXT: Section: .tbss @@ -156,7 +155,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM64-NEXT: NumberOfAuxEntries: 1 ; SYM64-NEXT: CSECT Auxiliary Entry { -; SYM64-NEXT: Index: 26 +; SYM64-NEXT: Index: [[#INDX+8]] ; SYM64-NEXT: SectionLen: 4 ; SYM64-NEXT: ParameterHashIndex: 0x0 ; SYM64-NEXT: TypeChkSectNum: 0x0 @@ -167,121 +166,120 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM64-NEXT: } ; SYM64-NEXT: } -; DIS64: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o: file format aix5coff64-rs6000 +; DIS64: {{.*}}: file format aix5coff64-rs6000 ; DIS64: Disassembly of section .text: -; DIS64: (idx: 3) .store_intern_int_zero: +; DIS64: (idx: [[#NFA+3]]) .store_intern_int_zero: ; DIS64-NEXT: ld 4, 0(2) -; DIS64-NEXT: (idx: 17) intern_int_zero[TC] +; DIS64-NEXT: (idx: [[#NFA+17]]) intern_int_zero[TC] ; DIS64-NEXT: stwx 3, 13, 4 ; DIS64-NEXT: blr -; DIS64: (idx: 5) .load_global_int_nonzero: +; DIS64: (idx: [[#NFA+5]]) .load_global_int_nonzero: ; DIS64-NEXT: ld 3, 8(2) -; DIS64-NEXT: (idx: 19) global_int_nonzero[TC] +; DIS64-NEXT: (idx: [[#NFA+19]]) global_int_nonzero[TC] ; DIS64-NEXT: lwax 3, 13, 3 ; DIS64-NEXT: blr -; DIS64: (idx: 7) .load_intern_int_zero: +; DIS64: (idx: [[#NFA+7]]) .load_intern_int_zero: ; DIS64-NEXT: ld 3, 0(2) -; DIS64-NEXT: (idx: 17) intern_int_zero[TC] +; DIS64-NEXT: (idx: [[#NFA+17]]) intern_int_zero[TC] ; DIS64-NEXT: lwax 3, 13, 3 ; DIS64-NEXT: blr ; DIS64: Disassembly of section .data: -; DIS64: (idx: 9) store_intern_int_zero[DS]: -; DIS64: R_POS (idx: 3) .store_intern_int_zero -; DIS64: R_POS (idx: 15) TOC[TC0] -; DIS64: (idx: 11) load_global_int_nonzero[DS]: -; DIS64: R_POS (idx: 5) .load_global_int_nonzero -; DIS64: R_POS (idx: 15) TOC[TC0] -; DIS64: (idx: 13) load_intern_int_zero[DS]: -; DIS64: R_POS (idx: 7) .load_intern_int_zero -; DIS64: R_POS (idx: 15) TOC[TC0] -; DIS64: (idx: 17) intern_int_zero[TC]: -; DIS64: R_TLS_IE (idx: 25) intern_int_zero[UL] -; DIS64: (idx: 19) global_int_nonzero[TC]: -; DIS64: R_TLS_IE (idx: 23) global_int_nonzero +; DIS64: (idx: [[#NFA+9]]) store_intern_int_zero[DS]: +; DIS64: R_POS (idx: [[#NFA+3]]) .store_intern_int_zero +; DIS64: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS64: (idx: [[#NFA+11]]) load_global_int_nonzero[DS]: +; DIS64: R_POS (idx: [[#NFA+5]]) .load_global_int_nonzero +; DIS64: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS64: (idx: [[#NFA+13]]) load_intern_int_zero[DS]: +; DIS64: R_POS (idx: [[#NFA+7]]) .load_intern_int_zero +; DIS64: R_POS (idx: [[#NFA+15]]) TOC[TC0] +; DIS64: (idx: [[#NFA+17]]) intern_int_zero[TC]: +; DIS64: R_TLS_IE (idx: [[#NFA+25]]) intern_int_zero[UL] +; DIS64: (idx: [[#NFA+19]]) global_int_nonzero[TC]: +; DIS64: R_TLS_IE (idx: [[#NFA+23]]) global_int_nonzero ; DIS64: Disassembly of section .tdata: -; DIS64: (idx: 23) global_int_nonzero: +; DIS64: (idx: [[#NFA+23]]) global_int_nonzero: ; DIS64: Disassembly of section .tbss: -; DIS64: (idx: 25) intern_int_zero[UL]: +; DIS64: (idx: [[#NFA+25]]) intern_int_zero[UL]: -; REL32: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; REL32: File: ; REL32-NEXT: Format: aixcoff-rs6000 ; REL32-NEXT: Arch: powerpc ; REL32-NEXT: AddressSize: 32bit ; REL32-NEXT: Relocations [ ; REL32: Virtual Address: 0xA -; REL32-NEXT: Symbol: intern_int_zero (19) +; REL32-NEXT: Symbol: intern_int_zero ([[#NFA+19]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 16 ; REL32-NEXT: Type: R_TOC (0x3) ; REL32-NEXT: } ; REL32: Virtual Address: 0x10 -; REL32-NEXT: Symbol: .__get_tpointer (1) +; REL32-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 26 ; REL32-NEXT: Type: R_RBA (0x18) ; REL32-NEXT: } ; REL32: Virtual Address: 0x3A -; REL32-NEXT: Symbol: global_int_nonzero (21) +; REL32-NEXT: Symbol: global_int_nonzero ([[#NFA+21]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 16 ; REL32-NEXT: Type: R_TOC (0x3) ; REL32-NEXT: } ; REL32: Virtual Address: 0x40 -; REL32-NEXT: Symbol: .__get_tpointer (1) +; REL32-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 26 ; REL32-NEXT: Type: R_RBA (0x18) ; REL32-NEXT: } ; REL32: Virtual Address: 0x6A -; REL32-NEXT: Symbol: intern_int_zero (19) +; REL32-NEXT: Symbol: intern_int_zero ([[#NFA+19]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 16 ; REL32-NEXT: Type: R_TOC (0x3) ; REL32-NEXT: } ; REL32: Virtual Address: 0x70 -; REL32-NEXT: Symbol: .__get_tpointer (1) +; REL32-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 26 ; REL32-NEXT: Type: R_RBA (0x18) ; REL32-NEXT: } ; REL32: Virtual Address: 0xAC -; REL32-NEXT: Symbol: intern_int_zero (27) +; REL32-NEXT: Symbol: intern_int_zero ([[#NFA+27]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 32 ; REL32-NEXT: Type: R_TLS_IE (0x21) ; REL32-NEXT: } ; REL32: Virtual Address: 0xB0 -; REL32-NEXT: Symbol: global_int_nonzero (25) +; REL32-NEXT: Symbol: global_int_nonzero ([[#NFA+25]]) ; REL32-NEXT: IsSigned: No ; REL32-NEXT: FixupBitValue: 0 ; REL32-NEXT: Length: 32 ; REL32-NEXT: Type: R_TLS_IE (0x21) ; REL32-NEXT: } -; SYM32: File: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o +; SYM32: File: ; SYM32-NEXT: Format: aixcoff-rs6000 ; SYM32-NEXT: Arch: powerpc ; SYM32-NEXT: AddressSize: 32bit ; SYM32-NEXT: Symbols [ -; SYM32: Index: 19 -; SYM32-NEXT: Name: intern_int_zero +; SYM32: Name: intern_int_zero ; SYM32-NEXT: Value (RelocatableAddress): 0xAC ; SYM32-NEXT: Section: .data ; SYM32-NEXT: Type: 0x0 ; SYM32-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 20 +; SYM32-NEXT: Index: [[#INDX:]] ; SYM32-NEXT: SectionLen: 4 ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 @@ -292,7 +290,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StabSectNum: 0x0 ; SYM32-NEXT: } ; SYM32-NEXT: } -; SYM32: Index: 21 +; SYM32: Index: [[#INDX+1]] ; SYM32-NEXT: Name: global_int_nonzero ; SYM32-NEXT: Value (RelocatableAddress): 0xB0 ; SYM32-NEXT: Section: .data @@ -300,7 +298,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 22 +; SYM32-NEXT: Index: [[#INDX+2]] ; SYM32-NEXT: SectionLen: 4 ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 @@ -311,7 +309,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StabSectNum: 0x0 ; SYM32-NEXT: } ; SYM32-NEXT: } -; SYM32: Index: 25 +; SYM32: Index: [[#INDX+5]] ; SYM32-NEXT: Name: global_int_nonzero ; SYM32-NEXT: Value (RelocatableAddress): 0x0 ; SYM32-NEXT: Section: .tdata @@ -319,8 +317,8 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StorageClass: C_EXT (0x2) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 26 -; SYM32-NEXT: ContainingCsectSymbolIndex: 23 +; SYM32-NEXT: Index: [[#INDX+6]] +; SYM32-NEXT: ContainingCsectSymbolIndex: [[#INDX+3]] ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 ; SYM32-NEXT: SymbolAlignmentLog2: 0 @@ -330,7 +328,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StabSectNum: 0x0 ; SYM32-NEXT: } ; SYM32-NEXT: } -; SYM32: Index: 27 +; SYM32: Index: [[#INDX+7]] ; SYM32-NEXT: Name: intern_int_zero ; SYM32-NEXT: Value (RelocatableAddress): 0x4 ; SYM32-NEXT: Section: .tbss @@ -338,7 +336,7 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM32-NEXT: NumberOfAuxEntries: 1 ; SYM32-NEXT: CSECT Auxiliary Entry { -; SYM32-NEXT: Index: 28 +; SYM32-NEXT: Index: [[#INDX+8]] ; SYM32-NEXT: SectionLen: 4 ; SYM32-NEXT: ParameterHashIndex: 0x0 ; SYM32-NEXT: TypeChkSectNum: 0x0 @@ -350,38 +348,38 @@ declare nonnull ptr @llvm.threadlocal.address.p0(ptr nonnull) ; SYM32-NEXT: } ; SYM32-NEXT: } -; DIS32: {{.*}}aix-tls-ie-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 +; DIS32: file format aixcoff-rs6000 ; DIS32: Disassembly of section .text: -; DIS32: (idx: 5) .store_intern_int_zero: -; DIS32: R_TOC (idx: 19) intern_int_zero[TC] -; DIS32: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS32: (idx: [[#NFA+5]]) .store_intern_int_zero: +; DIS32: R_TOC (idx: [[#NFA+19]]) intern_int_zero[TC] +; DIS32: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS32: blr -; DIS32: (idx: 7) .load_global_int_nonzero: -; DIS32: R_TOC (idx: 21) global_int_nonzero[TC] -; DIS32: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS32: (idx: [[#NFA+7]]) .load_global_int_nonzero: +; DIS32: R_TOC (idx: [[#NFA+21]]) global_int_nonzero[TC] +; DIS32: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS32: blr -; DIS32: (idx: 9) .load_intern_int_zero: -; DIS32: R_TOC (idx: 19) intern_int_zero[TC] -; DIS32: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS32: (idx: [[#NFA+9]]) .load_intern_int_zero: +; DIS32: R_TOC (idx: [[#NFA+19]]) intern_int_zero[TC] +; DIS32: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS32: blr ; DIS32: Disassembly of section .data: -; DIS32: (idx: 11) store_intern_int_zero[DS]: -; DIS32: R_POS (idx: 5) .store_intern_int_zero -; DIS32: R_POS (idx: 17) TOC[TC0] -; DIS32: (idx: 13) load_global_int_nonzero[DS]: -; DIS32: R_POS (idx: 7) .load_global_int_nonzero -; DIS32: R_POS (idx: 17) TOC[TC0] -; DIS32: (idx: 15) load_intern_int_zero[DS]: -; DIS32: R_POS (idx: 9) .load_intern_int_zero -; DIS32: R_POS (idx: 17) TOC[TC0] -; DIS32: (idx: 19) intern_int_zero[TC]: -; DIS32: R_TLS_IE (idx: 27) intern_int_zero[UL] -; DIS32: (idx: 21) global_int_nonzero[TC]: -; DIS32: R_TLS_IE (idx: 25) global_int_nonzero +; DIS32: (idx: [[#NFA+11]]) store_intern_int_zero[DS]: +; DIS32: R_POS (idx: [[#NFA+5]]) .store_intern_int_zero +; DIS32: R_POS (idx: [[#NFA+17]]) TOC[TC0] +; DIS32: (idx: [[#NFA+13]]) load_global_int_nonzero[DS]: +; DIS32: R_POS (idx: [[#NFA+7]]) .load_global_int_nonzero +; DIS32: R_POS (idx: [[#NFA+17]]) TOC[TC0] +; DIS32: (idx: [[#NFA+15]]) load_intern_int_zero[DS]: +; DIS32: R_POS (idx: [[#NFA+9]]) .load_intern_int_zero +; DIS32: R_POS (idx: [[#NFA+17]]) TOC[TC0] +; DIS32: (idx: [[#NFA+19]]) intern_int_zero[TC]: +; DIS32: R_TLS_IE (idx: [[#NFA+27]]) intern_int_zero[UL] +; DIS32: (idx: [[#NFA+21]]) global_int_nonzero[TC]: +; DIS32: R_TLS_IE (idx: [[#NFA+25]]) global_int_nonzero ; DIS32: Disassembly of section .tdata: -; DIS32: (idx: 25) global_int_nonzero: +; DIS32: (idx: [[#NFA+25]]) global_int_nonzero: ; DIS32: Disassembly of section .tbss: -; DIS32: (idx: 27) intern_int_zero[UL]: +; DIS32: (idx: [[#NFA+27]]) intern_int_zero[UL]: diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll index 5283e24c060cca7c369d9a5b36ab47160c019f32..83296de036d0da2bb573bd71f6f5b55b2eeea1c9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8 @VarInit = global i64 87, align 8 @@ -36,81 +36,81 @@ entry: ret i64 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aix5coff64-rs6000 ; RELOC-NEXT: Arch: powerpc64 ; RELOC-NEXT: AddressSize: 64bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0x2 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (19) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x6 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (19) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (21) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: ThreadLocalVarInit (21) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x42 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (25) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x46 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (25) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (29) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xB0 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (27) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xC0 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (31) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aix5coff64-rs6000 ; SYM-NEXT: Arch: powerpc64 ; SYM-NEXT: AddressSize: 64bit ; SYM-NEXT: Symbols [ -; SYM: Index: 19 +; SYM: Index: [[#NFA+19]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -118,7 +118,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 20 +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -128,7 +128,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 21 +; SYM: Index: [[#NFA+21]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0xB0 ; SYM-NEXT: Section: .data @@ -136,7 +136,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -145,7 +145,7 @@ entry: ; SYM-NEXT: StorageMappingClass: XMC_TE (0x16) ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } -; SYM: Index: 25 +; SYM: Index: [[#NFA+25]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0xC0 ; SYM-NEXT: Section: .data @@ -153,7 +153,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -163,7 +163,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 27 +; SYM: Index: [[#NFA+27]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -171,7 +171,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -181,7 +181,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 29 +; SYM: Index: [[#NFA+29]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -189,7 +189,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -199,7 +199,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 31 +; SYM: Index: [[#NFA+31]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x10 ; SYM-NEXT: Section: .tbss @@ -207,7 +207,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -218,93 +218,93 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc-large.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: file format aix5coff64-rs6000 ; DIS: Disassembly of section .text: -; DIS: 0000000000000000 (idx: 3) .storeITLUninit: +; DIS: 0000000000000000 (idx: [[#NFA+3]]) .storeITLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdx 3, 13, 4 ; DIS-NEXT: blr -; DIS: 0000000000000010 (idx: 5) .loadTLInit: +; DIS: 0000000000000010 (idx: [[#NFA+5]]) .loadTLInit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 16(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ldx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 4, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr -; DIS: 0000000000000030 (idx: 7) .loadTLUninit: +; DIS: 0000000000000030 (idx: [[#NFA+7]]) .loadTLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stdx 4, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 24(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ldx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 3, 3, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000058 (idx: 9) VarInit[RW]: +; DIS: 0000000000000058 (idx: [[#NFA+9]]) VarInit[RW]: ; DIS-NEXT: 58: 00 00 00 00 ; DIS-NEXT: 5c: 00 00 00 57 -; DIS: 0000000000000060 (idx: 11) storeITLUninit[DS]: +; DIS: 0000000000000060 (idx: [[#NFA+11]]) storeITLUninit[DS]: ; DIS-NEXT: 60: 00 00 00 00 -; DIS-NEXT: 0000000000000060: R_POS (idx: 3) .storeITLUninit +; DIS-NEXT: 0000000000000060: R_POS (idx: [[#NFA+3]]) .storeITLUninit ; DIS-NEXT: 64: 00 00 00 00 ; DIS-NEXT: 68: 00 00 00 00 -; DIS-NEXT: 0000000000000068: R_POS (idx: 17) TOC[TC0] +; DIS-NEXT: 0000000000000068: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 6c: 00 00 00 a8 -; DIS: 0000000000000078 (idx: 13) loadTLInit[DS]: +; DIS: 0000000000000078 (idx: [[#NFA+13]]) loadTLInit[DS]: ; DIS-NEXT: 78: 00 00 00 00 -; DIS-NEXT: 0000000000000078: R_POS (idx: 5) .loadTLInit +; DIS-NEXT: 0000000000000078: R_POS (idx: [[#NFA+5]]) .loadTLInit ; DIS-NEXT: 7c: 00 00 00 10 ; DIS-NEXT: 80: 00 00 00 00 -; DIS-NEXT: 0000000000000080: R_POS (idx: 17) TOC[TC0] +; DIS-NEXT: 0000000000000080: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 84: 00 00 00 a8 -; DIS: 0000000000000090 (idx: 15) loadTLUninit[DS]: +; DIS: 0000000000000090 (idx: [[#NFA+15]]) loadTLUninit[DS]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 0000000000000090: R_POS (idx: 7) .loadTLUninit +; DIS-NEXT: 0000000000000090: R_POS (idx: [[#NFA+7]]) .loadTLUninit ; DIS-NEXT: 94: 00 00 00 30 ; DIS-NEXT: 98: 00 00 00 00 -; DIS-NEXT: 0000000000000098: R_POS (idx: 17) TOC[TC0] +; DIS-NEXT: 0000000000000098: R_POS (idx: [[#NFA+17]]) TOC[TC0] ; DIS-NEXT: 9c: 00 00 00 a8 -; DIS: 00000000000000a8 (idx: 19) IThreadLocalVarUninit[TE]: +; DIS: 00000000000000a8 (idx: [[#NFA+19]]) IThreadLocalVarUninit[TE]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: 29) IThreadLocalVarUninit[UL] +; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: [[#NFA+29]]) IThreadLocalVarUninit[UL] ; DIS-NEXT: ac: 00 00 00 08 -; DIS: 00000000000000b0 (idx: 21) ThreadLocalVarInit[TE]: +; DIS: 00000000000000b0 (idx: [[#NFA+21]]) ThreadLocalVarInit[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: 27) ThreadLocalVarInit[TL] +; DIS-NEXT: 00000000000000b0: R_TLS_LE (idx: [[#NFA+27]]) ThreadLocalVarInit[TL] ; DIS-NEXT: b4: 00 00 00 00 -; DIS: 00000000000000b8 (idx: 23) VarInit[TE]: +; DIS: 00000000000000b8 (idx: [[#NFA+23]]) VarInit[TE]: ; DIS-NEXT: b8: 00 00 00 00 -; DIS-NEXT: 00000000000000b8: R_POS (idx: 9) VarInit[RW] +; DIS-NEXT: 00000000000000b8: R_POS (idx: [[#NFA+9]]) VarInit[RW] ; DIS-NEXT: bc: 00 00 00 58 -; DIS: 00000000000000c0 (idx: 25) IThreadLocalVarUninit2[TE]: +; DIS: 00000000000000c0 (idx: [[#NFA+25]]) IThreadLocalVarUninit2[TE]: ; DIS-NEXT: c0: 00 00 00 00 -; DIS-NEXT: 00000000000000c0: R_TLS_LE (idx: 31) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 00000000000000c0: R_TLS_LE (idx: [[#NFA+31]]) IThreadLocalVarUninit2[UL] ; DIS-NEXT: c4: 00 00 00 10 ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 27) ThreadLocalVarInit[TL]: +; DIS: 0000000000000000 (idx: [[#NFA+27]]) ThreadLocalVarInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 0000000000000008 (idx: 29) IThreadLocalVarUninit[UL]: +; DIS: 0000000000000008 (idx: [[#NFA+29]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 0000000000000010 (idx: 31) IThreadLocalVarUninit2[UL]: +; DIS: 0000000000000010 (idx: [[#NFA+31]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll index 9897fc89b423018b5c207c4b371d7df5bb602beb..3b754e362f12f6f81a17ed9827241d5f7a882f57 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc-large32.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i64 1, align 8 @VarInit = global i64 87, align 8 @@ -36,69 +36,69 @@ entry: ret i64 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (21) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x16 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (21) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x18 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x4E -; RELOC-NEXT: Symbol: ThreadLocalVarInit (23) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x52 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (23) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x54 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xBE -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (27) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCU (0x30) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xC2 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (27) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOCL (0x31) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x114 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (31) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -106,26 +106,26 @@ entry: ; RELOC-NEXT: } ; RELOC: Relocation { ; RELOC-NEXT: Virtual Address: 0x118 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (29) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x120 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (33) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ -; SYM: Index: 1 +; SYM: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__get_tpointer ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -133,7 +133,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -144,7 +144,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 21 +; SYM: Index: [[#NFA+21]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x114 ; SYM-NEXT: Section: .data @@ -152,7 +152,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -163,7 +163,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 23 +; SYM: Index: [[#NFA+23]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x118 ; SYM-NEXT: Section: .data @@ -171,7 +171,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -182,7 +182,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 27 +; SYM: Index: [[#NFA+27]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x120 ; SYM-NEXT: Section: .data @@ -190,7 +190,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -201,7 +201,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 29 +; SYM: Index: [[#NFA+29]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -209,7 +209,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -220,7 +220,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 31 +; SYM: Index: [[#NFA+31]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -228,7 +228,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -239,7 +239,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 33 +; SYM: Index: [[#NFA+33]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x10 ; SYM-NEXT: Section: .tbss @@ -247,7 +247,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -259,19 +259,19 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc-large32.ll.tmp.o: file format aixcoff-rs6000 +; DIS: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storeITLUninit: +; DIS: 00000000 (idx: [[#NFA+5]]) .storeITLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: mr 5, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 6, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 3, 6 ; DIS-NEXT: stw 4, 4(3) ; DIS-NEXT: stw 5, 0(3) @@ -279,23 +279,23 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000040 (idx: 7) .loadTLInit: +; DIS: 00000040 (idx: [[#NFA+7]]) .loadTLInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) ThreadLocalVarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) ThreadLocalVarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 5, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 5, 8(5) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) VarInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) VarInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 6, 4(5) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 5, 0(5) ; DIS-NEXT: addc 4, 6, 4 @@ -304,25 +304,25 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000090 (idx: 9) .loadTLUninit: +; DIS: 00000090 (idx: [[#NFA+9]]) .loadTLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: li 5, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) IThreadLocalVarUninit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 4, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 5, 4(4) ; DIS-NEXT: li 5, 0 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stw 5, 0(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 27) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 27) IThreadLocalVarUninit2[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) @@ -334,48 +334,48 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 000000e8 (idx: 11) VarInit[RW]: +; DIS: 000000e8 (idx: [[#NFA+11]]) VarInit[RW]: ; DIS-NEXT: e8: 00 00 00 00 ; DIS-NEXT: ec: 00 00 00 57 -; DIS: 000000f0 (idx: 13) storeITLUninit[DS]: +; DIS: 000000f0 (idx: [[#NFA+13]]) storeITLUninit[DS]: ; DIS-NEXT: f0: 00 00 00 00 -; DIS-NEXT: 000000f0: R_POS (idx: 5) .storeITLUninit +; DIS-NEXT: 000000f0: R_POS (idx: [[#NFA+5]]) .storeITLUninit ; DIS-NEXT: f4: 00 00 01 14 -; DIS-NEXT: 000000f4: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 000000f4: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: f8: 00 00 00 00 -; DIS: 000000fc (idx: 15) loadTLInit[DS]: +; DIS: 000000fc (idx: [[#NFA+15]]) loadTLInit[DS]: ; DIS-NEXT: fc: 00 00 00 40 -; DIS-NEXT: 000000fc: R_POS (idx: 7) .loadTLInit +; DIS-NEXT: 000000fc: R_POS (idx: [[#NFA+7]]) .loadTLInit ; DIS-NEXT: 100: 00 00 01 14 -; DIS-NEXT: 00000100: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 00000100: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 104: 00 00 00 00 -; DIS: 00000108 (idx: 17) loadTLUninit[DS]: +; DIS: 00000108 (idx: [[#NFA+17]]) loadTLUninit[DS]: ; DIS-NEXT: 108: 00 00 00 90 -; DIS-NEXT: 00000108: R_POS (idx: 9) .loadTLUninit +; DIS-NEXT: 00000108: R_POS (idx: [[#NFA+9]]) .loadTLUninit ; DIS-NEXT: 10c: 00 00 01 14 -; DIS-NEXT: 0000010c: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000010c: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 110: 00 00 00 00 -; DIS: 00000114 (idx: 21) IThreadLocalVarUninit[TE]: +; DIS: 00000114 (idx: [[#NFA+21]]) IThreadLocalVarUninit[TE]: ; DIS-NEXT: 114: 00 00 00 08 -; DIS-NEXT: 00000114: R_TLS_LE (idx: 31) IThreadLocalVarUninit[UL] -; DIS: 00000118 (idx: 23) ThreadLocalVarInit[TE]: +; DIS-NEXT: 00000114: R_TLS_LE (idx: [[#NFA+31]]) IThreadLocalVarUninit[UL] +; DIS: 00000118 (idx: [[#NFA+23]]) ThreadLocalVarInit[TE]: ; DIS-NEXT: 118: 00 00 00 00 -; DIS-NEXT: 00000118: R_TLS_LE (idx: 29) ThreadLocalVarInit[TL] -; DIS: 0000011c (idx: 25) VarInit[TE]: +; DIS-NEXT: 00000118: R_TLS_LE (idx: [[#NFA+29]]) ThreadLocalVarInit[TL] +; DIS: 0000011c (idx: [[#NFA+25]]) VarInit[TE]: ; DIS-NEXT: 11c: 00 00 00 e8 -; DIS-NEXT: 0000011c: R_POS (idx: 11) VarInit[RW] -; DIS: 00000120 (idx: 27) IThreadLocalVarUninit2[TE]: +; DIS-NEXT: 0000011c: R_POS (idx: [[#NFA+11]]) VarInit[RW] +; DIS: 00000120 (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TE]: ; DIS-NEXT: 120: 00 00 00 10 -; DIS-NEXT: 00000120: R_TLS_LE (idx: 33) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 00000120: R_TLS_LE (idx: [[#NFA+33]]) IThreadLocalVarUninit2[UL] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 29) ThreadLocalVarInit[TL]: +; DIS: 00000000 (idx: [[#NFA+29]]) ThreadLocalVarInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000008 (idx: 31) IThreadLocalVarUninit[UL]: +; DIS: 00000008 (idx: [[#NFA+31]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 00000010 (idx: 33) IThreadLocalVarUninit2[UL]: +; DIS: 00000010 (idx: [[#NFA+33]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll index d469a869011097cc166d7358e9454cfe97203e61..c67c79e3ab7be46545b54e7b67369ba793840820 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc64-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4 @VarInit = global i32 87, align 4 @@ -36,60 +36,60 @@ entry: ret i32 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aix5coff64-rs6000 ; RELOC-NEXT: Arch: powerpc64 ; RELOC-NEXT: AddressSize: 64bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0x2 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (21) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (23) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x3E -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (27) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xA0 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (33) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (31) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xB8 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (35) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 64 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aix5coff64-rs6000 ; SYM-NEXT: Arch: powerpc64 ; SYM-NEXT: AddressSize: 64bit ; SYM-NEXT: Symbols [ -; SYM: Index: 21 +; SYM: Index: [[#NFA+21]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0xA0 ; SYM-NEXT: Section: .data @@ -97,7 +97,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -107,7 +107,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 23 +; SYM: Index: [[#NFA+23]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -115,7 +115,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -125,7 +125,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 27 +; SYM: Index: [[#NFA+27]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0xB8 ; SYM-NEXT: Section: .data @@ -133,7 +133,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -143,7 +143,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 31 +; SYM: Index: [[#NFA+31]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -151,8 +151,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 -; SYM-NEXT: ContainingCsectSymbolIndex: 29 +; SYM-NEXT: Index: [[#NFA+32]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+29]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -161,7 +161,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 33 +; SYM: Index: [[#NFA+33]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -169,7 +169,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -179,7 +179,7 @@ entry: ; SYM-NEXT: Auxiliary Type: AUX_CSECT (0xFB) ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 35 +; SYM: Index: [[#NFA+35]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -187,7 +187,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 36 +; SYM-NEXT: Index: [[#NFA+36]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -198,83 +198,83 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc.ll.tmp.o: file format aix5coff64-rs6000 +; DIS: file format aix5coff64-rs6000 ; DIS: Disassembly of section .text: -; DIS: 0000000000000000 (idx: 3) .storeITLUninit: +; DIS: 0000000000000000 (idx: [[#NFA+3]]) .storeITLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 21) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+21]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 3, 13, 4 ; DIS-NEXT: blr -; DIS: 0000000000000010 (idx: 5) .loadTLInit: +; DIS: 0000000000000010 (idx: [[#NFA+5]]) .loadTLInit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) ThreadLocalVarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) ThreadLocalVarInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 4, 16(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) VarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) VarInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(4) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} add 3, 4, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} extsw 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr -; DIS: 0000000000000030 (idx: 7) .loadTLUninit: +; DIS: 0000000000000030 (idx: [[#NFA+7]]) .loadTLUninit: ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 21) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+21]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} li 4, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 4, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} ld 3, 24(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) IThreadLocalVarUninit2[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 13, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addi 3, 3, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} extsw 3, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} blr ; DIS: Disassembly of section .data: -; DIS: 0000000000000050 (idx: 11) VarInit: +; DIS: 0000000000000050 (idx: [[#NFA+11]]) VarInit: ; DIS-NEXT: 50: 00 00 00 57 -; DIS: 0000000000000058 (idx: 13) storeITLUninit[DS]: +; DIS: 0000000000000058 (idx: [[#NFA+13]]) storeITLUninit[DS]: ; DIS-NEXT: 58: 00 00 00 00 -; DIS-NEXT: 0000000000000058: R_POS (idx: 3) .storeITLUninit +; DIS-NEXT: 0000000000000058: R_POS (idx: [[#NFA+3]]) .storeITLUninit ; DIS-NEXT: 5c: 00 00 00 00 ; DIS-NEXT: 60: 00 00 00 00 -; DIS-NEXT: 0000000000000060: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000000000000060: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 64: 00 00 00 a0 -; DIS: 0000000000000070 (idx: 15) loadTLInit[DS]: +; DIS: 0000000000000070 (idx: [[#NFA+15]]) loadTLInit[DS]: ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 0000000000000070: R_POS (idx: 5) .loadTLInit +; DIS-NEXT: 0000000000000070: R_POS (idx: [[#NFA+5]]) .loadTLInit ; DIS-NEXT: 74: 00 00 00 10 ; DIS-NEXT: 78: 00 00 00 00 -; DIS-NEXT: 0000000000000078: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000000000000078: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 7c: 00 00 00 a0 -; DIS: 0000000000000088 (idx: 17) loadTLUninit[DS]: +; DIS: 0000000000000088 (idx: [[#NFA+17]]) loadTLUninit[DS]: ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 0000000000000088: R_POS (idx: 7) .loadTLUninit +; DIS-NEXT: 0000000000000088: R_POS (idx: [[#NFA+7]]) .loadTLUninit ; DIS-NEXT: 8c: 00 00 00 30 ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 0000000000000090: R_POS (idx: 19) TOC[TC0] +; DIS-NEXT: 0000000000000090: R_POS (idx: [[#NFA+19]]) TOC[TC0] ; DIS-NEXT: 94: 00 00 00 a0 -; DIS: 00000000000000a0 (idx: 21) IThreadLocalVarUninit[TC]: +; DIS: 00000000000000a0 (idx: [[#NFA+21]]) IThreadLocalVarUninit[TC]: ; DIS-NEXT: a0: 00 00 00 00 -; DIS-NEXT: 00000000000000a0: R_TLS_LE (idx: 33) IThreadLocalVarUninit[UL] +; DIS-NEXT: 00000000000000a0: R_TLS_LE (idx: [[#NFA+33]]) IThreadLocalVarUninit[UL] ; DIS-NEXT: a4: 00 00 00 04 -; DIS: 00000000000000a8 (idx: 23) ThreadLocalVarInit[TC]: +; DIS: 00000000000000a8 (idx: [[#NFA+23]]) ThreadLocalVarInit[TC]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: 31) ThreadLocalVarInit +; DIS-NEXT: 00000000000000a8: R_TLS_LE (idx: [[#NFA+31]]) ThreadLocalVarInit ; DIS-NEXT: ac: 00 00 00 00 -; DIS: 00000000000000b0 (idx: 25) VarInit[TC]: +; DIS: 00000000000000b0 (idx: [[#NFA+25]]) VarInit[TC]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 00000000000000b0: R_POS (idx: 11) VarInit +; DIS-NEXT: 00000000000000b0: R_POS (idx: [[#NFA+11]]) VarInit ; DIS-NEXT: b4: 00 00 00 50 -; DIS: 00000000000000b8 (idx: 27) IThreadLocalVarUninit2[TC]: +; DIS: 00000000000000b8 (idx: [[#NFA+27]]) IThreadLocalVarUninit2[TC]: ; DIS-NEXT: b8: 00 00 00 00 -; DIS-NEXT: 00000000000000b8: R_TLS_LE (idx: 35) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 00000000000000b8: R_TLS_LE (idx: [[#NFA+35]]) IThreadLocalVarUninit2[UL] ; DIS-NEXT: bc: 00 00 00 08 ; DIS: Disassembly of section .tdata: -; DIS: 0000000000000000 (idx: 31) ThreadLocalVarInit: +; DIS: 0000000000000000 (idx: [[#NFA+31]]) ThreadLocalVarInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 0000000000000004 (idx: 33) IThreadLocalVarUninit[UL]: +; DIS: 0000000000000004 (idx: [[#NFA+33]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 0000000000000008 (idx: 35) IThreadLocalVarUninit2[UL]: +; DIS: 0000000000000008 (idx: [[#NFA+35]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll index a681cd815d430b7c4c78411768446814609e3591..4be292b3030fba1d0629f1589ae7bd19482780ac 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-le-xcoff-reloc32.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr7 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @ThreadLocalVarInit = thread_local(localexec) global i32 1, align 4 @VarInit = global i32 87, align 4 @@ -36,74 +36,74 @@ entry: ret i32 %add } -; RELOC: File: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit ; RELOC-NEXT: Relocations [ ; RELOC: Virtual Address: 0xA -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (23) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x10 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x3A -; RELOC-NEXT: Symbol: ThreadLocalVarInit (25) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x40 -; RELOC-NEXT: Symbol: .__get_tpointer (1) +; RELOC-NEXT: Symbol: .__get_tpointer ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 ; RELOC-NEXT: Type: R_RBA (0x18) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0x8E -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (29) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 ; RELOC-NEXT: Type: R_TOC (0x3) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xD0 -; RELOC-NEXT: Symbol: IThreadLocalVarUninit (35) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xD4 -; RELOC-NEXT: Symbol: ThreadLocalVarInit (33) +; RELOC-NEXT: Symbol: ThreadLocalVarInit ([[#NFA+33]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } ; RELOC: Virtual Address: 0xDC -; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 (37) +; RELOC-NEXT: Symbol: IThreadLocalVarUninit2 ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 ; RELOC-NEXT: Type: R_TLS_LE (0x23) ; RELOC-NEXT: } -; SYM: File: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ -; SYM: Index: 1 +; SYM: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__get_tpointer ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -111,7 +111,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -122,7 +122,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 23 +; SYM: Index: [[#NFA+23]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0xD0 ; SYM-NEXT: Section: .data @@ -130,7 +130,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -141,7 +141,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 25 +; SYM: Index: [[#NFA+25]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0xD4 ; SYM-NEXT: Section: .data @@ -149,7 +149,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -160,7 +160,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 29 +; SYM: Index: [[#NFA+29]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0xDC ; SYM-NEXT: Section: .data @@ -168,7 +168,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -179,7 +179,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 33 +; SYM: Index: [[#NFA+33]] ; SYM-NEXT: Name: ThreadLocalVarInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -187,8 +187,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 -; SYM-NEXT: ContainingCsectSymbolIndex: 31 +; SYM-NEXT: Index: [[#NFA+34]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+31]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -198,7 +198,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 35 +; SYM: Index: [[#NFA+35]] ; SYM-NEXT: Name: IThreadLocalVarUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -206,7 +206,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 36 +; SYM-NEXT: Index: [[#NFA+36]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -217,7 +217,7 @@ entry: ; SYM-NEXT: StabSectNum: 0x0 ; SYM-NEXT: } ; SYM-NEXT: } -; SYM: Index: 37 +; SYM: Index: [[#NFA+37]] ; SYM-NEXT: Name: IThreadLocalVarUninit2 ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tbss @@ -225,7 +225,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 38 +; SYM-NEXT: Index: [[#NFA+38]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -237,51 +237,51 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } -; DIS: {{.*}}aix-tls-le-xcoff-reloc32.ll.tmp.o: file format aixcoff-rs6000 +; DIS: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storeITLUninit: +; DIS: 00000000 (idx: [[#NFA+5]]) .storeITLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 5, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: mr 4, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 4, 3, 5 ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000030 (idx: 7) .loadTLInit: +; DIS: 00000030 (idx: [[#NFA+7]]) .loadTLInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) ThreadLocalVarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) ThreadLocalVarInit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) VarInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) VarInit[TC] ; DIS-NEXT: lwz 4, 0(4) ; DIS-NEXT: add 3, 4, 3 ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000070 (idx: 9) .loadTLUninit: +; DIS: 00000070 (idx: [[#NFA+9]]) .loadTLUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) IThreadLocalVarUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) IThreadLocalVarUninit[TC] ; DIS-NEXT: li 5, 1 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__get_tpointer[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__get_tpointer[PR] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} stwx 5, 3, 4 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 29) IThreadLocalVarUninit2[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+29]]) IThreadLocalVarUninit2[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwzx 3, 3, 4 ; DIS-NEXT: addi 3, 3, 1 ; DIS-NEXT: addi 1, 1, 32 @@ -290,46 +290,46 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 000000a8 (idx: 13) VarInit: +; DIS: 000000a8 (idx: [[#NFA+13]]) VarInit: ; DIS-NEXT: a8: 00 00 00 57 -; DIS: 000000ac (idx: 15) storeITLUninit[DS]: +; DIS: 000000ac (idx: [[#NFA+15]]) storeITLUninit[DS]: ; DIS-NEXT: ac: 00 00 00 00 -; DIS-NEXT: 000000ac: R_POS (idx: 5) .storeITLUninit +; DIS-NEXT: 000000ac: R_POS (idx: [[#NFA+5]]) .storeITLUninit ; DIS-NEXT: b0: 00 00 00 d0 -; DIS-NEXT: 000000b0: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 000000b0: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: b4: 00 00 00 00 -; DIS: 000000b8 (idx: 17) loadTLInit[DS]: +; DIS: 000000b8 (idx: [[#NFA+17]]) loadTLInit[DS]: ; DIS-NEXT: b8: 00 00 00 30 -; DIS-NEXT: 000000b8: R_POS (idx: 7) .loadTLInit +; DIS-NEXT: 000000b8: R_POS (idx: [[#NFA+7]]) .loadTLInit ; DIS-NEXT: bc: 00 00 00 d0 -; DIS-NEXT: 000000bc: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 000000bc: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: c0: 00 00 00 00 -; DIS: 000000c4 (idx: 19) loadTLUninit[DS]: +; DIS: 000000c4 (idx: [[#NFA+19]]) loadTLUninit[DS]: ; DIS-NEXT: c4: 00 00 00 70 -; DIS-NEXT: 000000c4: R_POS (idx: 9) .loadTLUninit +; DIS-NEXT: 000000c4: R_POS (idx: [[#NFA+9]]) .loadTLUninit ; DIS-NEXT: c8: 00 00 00 d0 -; DIS-NEXT: 000000c8: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 000000c8: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: cc: 00 00 00 00 -; DIS: 000000d0 (idx: 23) IThreadLocalVarUninit[TC]: +; DIS: 000000d0 (idx: [[#NFA+23]]) IThreadLocalVarUninit[TC]: ; DIS-NEXT: d0: 00 00 00 04 -; DIS-NEXT: 000000d0: R_TLS_LE (idx: 35) IThreadLocalVarUninit[UL] -; DIS: 000000d4 (idx: 25) ThreadLocalVarInit[TC]: +; DIS-NEXT: 000000d0: R_TLS_LE (idx: [[#NFA+35]]) IThreadLocalVarUninit[UL] +; DIS: 000000d4 (idx: [[#NFA+25]]) ThreadLocalVarInit[TC]: ; DIS-NEXT: d4: 00 00 00 00 -; DIS-NEXT: 000000d4: R_TLS_LE (idx: 33) ThreadLocalVarInit -; DIS: 000000d8 (idx: 27) VarInit[TC]: +; DIS-NEXT: 000000d4: R_TLS_LE (idx: [[#NFA+33]]) ThreadLocalVarInit +; DIS: 000000d8 (idx: [[#NFA+27]]) VarInit[TC]: ; DIS-NEXT: d8: 00 00 00 a8 -; DIS-NEXT: 000000d8: R_POS (idx: 13) VarInit -; DIS: 000000dc (idx: 29) IThreadLocalVarUninit2[TC]: +; DIS-NEXT: 000000d8: R_POS (idx: [[#NFA+13]]) VarInit +; DIS: 000000dc (idx: [[#NFA+29]]) IThreadLocalVarUninit2[TC]: ; DIS-NEXT: dc: 00 00 00 08 -; DIS-NEXT: 000000dc: R_TLS_LE (idx: 37) IThreadLocalVarUninit2[UL] +; DIS-NEXT: 000000dc: R_TLS_LE (idx: [[#NFA+37]]) IThreadLocalVarUninit2[UL] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 33) ThreadLocalVarInit: +; DIS: 00000000 (idx: [[#NFA+33]]) ThreadLocalVarInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000004 (idx: 35) IThreadLocalVarUninit[UL]: +; DIS: 00000004 (idx: [[#NFA+35]]) IThreadLocalVarUninit[UL]: ; DIS-NEXT: ... -; DIS: 00000008 (idx: 37) IThreadLocalVarUninit2[UL]: +; DIS: 00000008 (idx: [[#NFA+37]]) IThreadLocalVarUninit2[UL]: ; DIS-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll index 2dae8ee96e20d19f94695023dbe5772e582b6750..059924f392f6b78a221f3ac6696e2bcdd8ac691a 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc-large.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false --code-model=large -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @GInit = global double 1.000000e+00, align 8 @TIInit = internal thread_local global i64 1, align 8 @@ -24,7 +24,7 @@ entry: ret double %add } -; RELOC: File: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit @@ -32,7 +32,7 @@ entry: ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x16 -; RELOC-NEXT: Symbol: .TIInit (17) +; RELOC-NEXT: Symbol: .TIInit ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -40,7 +40,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: TIInit (19) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -48,7 +48,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1E -; RELOC-NEXT: Symbol: .TIInit (17) +; RELOC-NEXT: Symbol: .TIInit ([[#NFA+17]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -56,7 +56,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x22 -; RELOC-NEXT: Symbol: TIInit (19) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+19]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -64,7 +64,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x24 -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -72,7 +72,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x4E -; RELOC-NEXT: Symbol: .TWInit (21) +; RELOC-NEXT: Symbol: .TWInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -80,7 +80,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x52 -; RELOC-NEXT: Symbol: TWInit (23) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -88,7 +88,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x56 -; RELOC-NEXT: Symbol: .TWInit (21) +; RELOC-NEXT: Symbol: .TWInit ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -96,7 +96,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x5A -; RELOC-NEXT: Symbol: TWInit (23) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -104,7 +104,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x5C -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -112,7 +112,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x66 -; RELOC-NEXT: Symbol: GInit (25) +; RELOC-NEXT: Symbol: GInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -120,7 +120,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x6A -; RELOC-NEXT: Symbol: GInit (25) +; RELOC-NEXT: Symbol: GInit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -130,7 +130,7 @@ entry: ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: .storesTIInit (5) +; RELOC-NEXT: Symbol: .storesTIInit ([[#NFA+5]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -138,7 +138,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x94 -; RELOC-NEXT: Symbol: TOC (15) +; RELOC-NEXT: Symbol: TOC ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -146,7 +146,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x9C -; RELOC-NEXT: Symbol: .loadsTWInit (7) +; RELOC-NEXT: Symbol: .loadsTWInit ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -154,7 +154,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xA0 -; RELOC-NEXT: Symbol: TOC (15) +; RELOC-NEXT: Symbol: TOC ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -162,7 +162,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xA8 -; RELOC-NEXT: Symbol: TIInit (27) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -170,7 +170,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xAC -; RELOC-NEXT: Symbol: TIInit (27) +; RELOC-NEXT: Symbol: TIInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -178,7 +178,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB0 -; RELOC-NEXT: Symbol: TWInit (29) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -186,7 +186,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB4 -; RELOC-NEXT: Symbol: TWInit (29) +; RELOC-NEXT: Symbol: TWInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -194,7 +194,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xB8 -; RELOC-NEXT: Symbol: GInit (9) +; RELOC-NEXT: Symbol: GInit ([[#NFA+9]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -203,23 +203,33 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: ] -; SYM: File: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: 0 -; SYM-NEXT: Name: +; SYM-NEXT: Name: .file ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM-NEXT: StorageClass: C_FILE (0x67) -; SYM-NEXT: NumberOfAuxEntries: 0 +; SYM-NEXT: NumberOfAuxEntries: 2 +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 1 +; SYM-NEXT: Name: +; SYM-NEXT: Type: XFT_FN (0x0) +; SYM-NEXT: } +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 2 +; SYM-NEXT: Name: LLVM +; SYM-NEXT: Type: XFT_CV (0x2) +; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 1 +; SYM-NEXT: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__tls_get_addr ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -227,7 +237,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -239,7 +249,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 3 +; SYM-NEXT: Index: [[#NFA+3]] ; SYM-NEXT: Name: ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -247,7 +257,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 4 +; SYM-NEXT: Index: [[#NFA+4]] ; SYM-NEXT: SectionLen: 132 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -259,7 +269,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 5 +; SYM-NEXT: Index: [[#NFA+5]] ; SYM-NEXT: Name: .storesTIInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -267,8 +277,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 6 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+6]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -279,7 +289,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 7 +; SYM-NEXT: Index: [[#NFA+7]] ; SYM-NEXT: Name: .loadsTWInit ; SYM-NEXT: Value (RelocatableAddress): 0x40 ; SYM-NEXT: Section: .text @@ -287,8 +297,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 8 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+8]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -299,7 +309,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 9 +; SYM-NEXT: Index: [[#NFA+9]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -307,7 +317,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 10 +; SYM-NEXT: Index: [[#NFA+10]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -319,7 +329,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 11 +; SYM-NEXT: Index: [[#NFA+11]] ; SYM-NEXT: Name: storesTIInit ; SYM-NEXT: Value (RelocatableAddress): 0x90 ; SYM-NEXT: Section: .data @@ -327,7 +337,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 12 +; SYM-NEXT: Index: [[#NFA+12]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -339,7 +349,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 13 +; SYM-NEXT: Index: [[#NFA+13]] ; SYM-NEXT: Name: loadsTWInit ; SYM-NEXT: Value (RelocatableAddress): 0x9C ; SYM-NEXT: Section: .data @@ -347,7 +357,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 14 +; SYM-NEXT: Index: [[#NFA+14]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -359,7 +369,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 15 +; SYM-NEXT: Index: [[#NFA+15]] ; SYM-NEXT: Name: TOC ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -367,7 +377,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 16 +; SYM-NEXT: Index: [[#NFA+16]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -379,7 +389,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 17 +; SYM-NEXT: Index: [[#NFA+17]] ; SYM-NEXT: Name: .TIInit ; SYM-NEXT: Value (RelocatableAddress): 0xA8 ; SYM-NEXT: Section: .data @@ -387,7 +397,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 18 +; SYM-NEXT: Index: [[#NFA+18]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -399,7 +409,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 19 +; SYM-NEXT: Index: [[#NFA+19]] ; SYM-NEXT: Name: TIInit ; SYM-NEXT: Value (RelocatableAddress): 0xAC ; SYM-NEXT: Section: .data @@ -407,7 +417,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 20 +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -419,7 +429,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 21 +; SYM-NEXT: Index: [[#NFA+21]] ; SYM-NEXT: Name: .TWInit ; SYM-NEXT: Value (RelocatableAddress): 0xB0 ; SYM-NEXT: Section: .data @@ -427,7 +437,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -439,7 +449,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 23 +; SYM-NEXT: Index: [[#NFA+23]] ; SYM-NEXT: Name: TWInit ; SYM-NEXT: Value (RelocatableAddress): 0xB4 ; SYM-NEXT: Section: .data @@ -447,7 +457,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -459,7 +469,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 25 +; SYM-NEXT: Index: [[#NFA+25]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0xB8 ; SYM-NEXT: Section: .data @@ -467,7 +477,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -479,7 +489,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 27 +; SYM-NEXT: Index: [[#NFA+27]] ; SYM-NEXT: Name: TIInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -487,7 +497,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -499,7 +509,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 29 +; SYM-NEXT: Index: [[#NFA+29]] ; SYM-NEXT: Name: TWInit ; SYM-NEXT: Value (RelocatableAddress): 0x8 ; SYM-NEXT: Section: .tdata @@ -507,7 +517,7 @@ entry: ; SYM-NEXT: StorageClass: C_WEAKEXT (0x6F) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 8 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -520,49 +530,49 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: ] -; DIS: {{.*}}aix-tls-xcoff-reloc-large.ll.tmp.o: file format aixcoff-rs6000 +; DIS: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storesTIInit: +; DIS: 00000000 (idx: [[#INDX:]]) .storesTIInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: mr 6, 4 ; DIS-NEXT: mr 7, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 17) .TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+17]]) .TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 19) TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+19]]) TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 17) .TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+17]]) .TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 19) TIInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+19]]) TIInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: stw 6, 4(3) ; DIS-NEXT: stw 7, 0(3) ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000040 (idx: 7) .loadsTWInit: +; DIS: 00000040 (idx: [[#INDX+2]]) .loadsTWInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 21) .TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+21]]) .TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 4, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 23) TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+23]]) TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 21) .TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+21]]) .TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(4) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 23) TWInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+23]]) TWInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: lfd 0, 0(3) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} addis 3, 2, 0 -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: 25) GInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCU (idx: [[#NFA+25]]) GInit[TE] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 16(3) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: 25) GInit[TE] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOCL (idx: [[#NFA+25]]) GInit[TE] ; DIS-NEXT: lfd 1, 0(3) ; DIS-NEXT: fadd 1, 0, 1 ; DIS-NEXT: addi 1, 1, 32 @@ -571,42 +581,42 @@ entry: ; DIS-NEXT: blr ; DIS: Disassembly of section .data: -; DIS: 00000088 (idx: 9) GInit[RW]: +; DIS: 00000088 (idx: [[#NFA+9]]) GInit[RW]: ; DIS-NEXT: 88: 3f f0 00 00 ; DIS-NEXT: 8c: 00 00 00 00 -; DIS: 00000090 (idx: 11) storesTIInit[DS]: +; DIS: 00000090 (idx: [[#NFA+11]]) storesTIInit[DS]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 00000090: R_POS (idx: 5) .storesTIInit +; DIS-NEXT: 00000090: R_POS (idx: [[#NFA+5]]) .storesTIInit ; DIS-NEXT: 94: 00 00 00 a8 -; DIS-NEXT: 00000094: R_POS (idx: 15) TOC[TC0] +; DIS-NEXT: 00000094: R_POS (idx: [[#NFA+15]]) TOC[TC0] ; DIS-NEXT: 98: 00 00 00 00 -; DIS: 0000009c (idx: 13) loadsTWInit[DS]: +; DIS: 0000009c (idx: [[#NFA+13]]) loadsTWInit[DS]: ; DIS-NEXT: 9c: 00 00 00 40 -; DIS-NEXT: 0000009c: R_POS (idx: 7) .loadsTWInit +; DIS-NEXT: 0000009c: R_POS (idx: [[#NFA+7]]) .loadsTWInit ; DIS-NEXT: a0: 00 00 00 a8 -; DIS-NEXT: 000000a0: R_POS (idx: 15) TOC[TC0] +; DIS-NEXT: 000000a0: R_POS (idx: [[#NFA+15]]) TOC[TC0] ; DIS-NEXT: a4: 00 00 00 00 -; DIS: 000000a8 (idx: 17) .TIInit[TE]: +; DIS: 000000a8 (idx: [[#NFA+17]]) .TIInit[TE]: ; DIS-NEXT: a8: 00 00 00 00 -; DIS-NEXT: 000000a8: R_TLSM (idx: 27) TIInit[TL] -; DIS: 000000ac (idx: 19) TIInit[TE]: +; DIS-NEXT: 000000a8: R_TLSM (idx: [[#NFA+27]]) TIInit[TL] +; DIS: 000000ac (idx: [[#NFA+19]]) TIInit[TE]: ; DIS-NEXT: ac: 00 00 00 00 -; DIS-NEXT: 000000ac: R_TLS (idx: 27) TIInit[TL] -; DIS: 000000b0 (idx: 21) .TWInit[TE]: +; DIS-NEXT: 000000ac: R_TLS (idx: [[#NFA+27]]) TIInit[TL] +; DIS: 000000b0 (idx: [[#NFA+21]]) .TWInit[TE]: ; DIS-NEXT: b0: 00 00 00 00 -; DIS-NEXT: 000000b0: R_TLSM (idx: 29) TWInit[TL] -; DIS: 000000b4 (idx: 23) TWInit[TE]: +; DIS-NEXT: 000000b0: R_TLSM (idx: [[#NFA+29]]) TWInit[TL] +; DIS: 000000b4 (idx: [[#NFA+23]]) TWInit[TE]: ; DIS-NEXT: b4: 00 00 00 08 -; DIS-NEXT: 000000b4: R_TLS (idx: 29) TWInit[TL] -; DIS: 000000b8 (idx: 25) GInit[TE]: +; DIS-NEXT: 000000b4: R_TLS (idx: [[#NFA+29]]) TWInit[TL] +; DIS: 000000b8 (idx: [[#NFA+25]]) GInit[TE]: ; DIS-NEXT: b8: 00 00 00 88 -; DIS-NEXT: 000000b8: R_POS (idx: 9) GInit[RW] +; DIS-NEXT: 000000b8: R_POS (idx: [[#NFA+9]]) GInit[RW] ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 27) TIInit[TL]: +; DIS: 00000000 (idx: [[#NFA+27]]) TIInit[TL]: ; DIS-NEXT: 0: 00 00 00 00 ; DIS-NEXT: 4: 00 00 00 01 -; DIS: 00000008 (idx: 29) TWInit[TL]: +; DIS: 00000008 (idx: [[#NFA+29]]) TWInit[TL]: ; DIS-NEXT: 8: 3f f0 00 00 ; DIS-NEXT: c: 00 00 00 00 diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll index 0779686b54f3ac0b917e9db8533e2c1e5a8ced47..eb7a0e277a5652a7a9e3e4196132682c7444e411 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-reloc.ll @@ -1,8 +1,8 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefix=RELOC %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=SYM %s -; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck --check-prefix=DIS %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefix=RELOC %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=SYM %s +; RUN: llvm-objdump -D -r --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=DIS %s @const_ivar = constant i32 6, align 4 @GInit = global i32 1, align 4 @@ -25,7 +25,7 @@ entry: ret i32 %add } -; RELOC: File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o +; RELOC: File: ; RELOC-NEXT: Format: aixcoff-rs6000 ; RELOC-NEXT: Arch: powerpc ; RELOC-NEXT: AddressSize: 32bit @@ -33,7 +33,7 @@ entry: ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0xE -; RELOC-NEXT: Symbol: .TIUninit (23) +; RELOC-NEXT: Symbol: .TIUninit ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -41,7 +41,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x12 -; RELOC-NEXT: Symbol: TIUninit (25) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -49,7 +49,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x18 -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -57,7 +57,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x3A -; RELOC-NEXT: Symbol: .TGInit (27) +; RELOC-NEXT: Symbol: .TGInit ([[#NFA+27]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -65,7 +65,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x3E -; RELOC-NEXT: Symbol: TGInit (29) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+29]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -73,7 +73,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x44 -; RELOC-NEXT: Symbol: .__tls_get_addr (1) +; RELOC-NEXT: Symbol: .__tls_get_addr ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -81,7 +81,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x4A -; RELOC-NEXT: Symbol: GInit (31) +; RELOC-NEXT: Symbol: GInit ([[#NFA+31]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -91,7 +91,7 @@ entry: ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x70 -; RELOC-NEXT: Symbol: .storesTIUninit (5) +; RELOC-NEXT: Symbol: .storesTIUninit ([[#NFA+5]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -99,7 +99,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x74 -; RELOC-NEXT: Symbol: TOC (21) +; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -107,7 +107,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x7C -; RELOC-NEXT: Symbol: .loadsTGInit (7) +; RELOC-NEXT: Symbol: .loadsTGInit ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -115,7 +115,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x80 -; RELOC-NEXT: Symbol: TOC (21) +; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -123,7 +123,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x88 -; RELOC-NEXT: Symbol: TIUninit (37) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -131,7 +131,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x8C -; RELOC-NEXT: Symbol: TIUninit (37) +; RELOC-NEXT: Symbol: TIUninit ([[#NFA+37]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -139,7 +139,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: TGInit (35) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -147,7 +147,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x94 -; RELOC-NEXT: Symbol: TGInit (35) +; RELOC-NEXT: Symbol: TGInit ([[#NFA+35]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -155,7 +155,7 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x98 -; RELOC-NEXT: Symbol: GInit (15) +; RELOC-NEXT: Symbol: GInit ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 32 @@ -164,23 +164,22 @@ entry: ; RELOC-NEXT: } ; RELOC-NEXT: ] -; SYM: File: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o +; SYM: File: ; SYM-NEXT: Format: aixcoff-rs6000 ; SYM-NEXT: Arch: powerpc ; SYM-NEXT: AddressSize: 32bit ; SYM-NEXT: Symbols [ ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: 0 -; SYM-NEXT: Name: +; SYM-NEXT: Name: .file ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYM-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM-NEXT: StorageClass: C_FILE (0x67) -; SYM-NEXT: NumberOfAuxEntries: 0 -; SYM-NEXT: } -; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 1 +; SYM-NEXT: NumberOfAuxEntries: 2 +; SYM: Symbol { +; SYM-NEXT: Index: [[#NFA+1]] ; SYM-NEXT: Name: .__tls_get_addr ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: N_UNDEF @@ -188,7 +187,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 2 +; SYM-NEXT: Index: [[#NFA+2]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -200,7 +199,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 3 +; SYM-NEXT: Index: [[#NFA+3]] ; SYM-NEXT: Name: ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -208,7 +207,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 4 +; SYM-NEXT: Index: [[#NFA+4]] ; SYM-NEXT: SectionLen: 104 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -220,7 +219,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 5 +; SYM-NEXT: Index: [[#NFA+5]] ; SYM-NEXT: Name: .storesTIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .text @@ -228,8 +227,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 6 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+6]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -240,7 +239,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 7 +; SYM-NEXT: Index: [[#NFA+7]] ; SYM-NEXT: Name: .loadsTGInit ; SYM-NEXT: Value (RelocatableAddress): 0x30 ; SYM-NEXT: Section: .text @@ -248,8 +247,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 8 -; SYM-NEXT: ContainingCsectSymbolIndex: 3 +; SYM-NEXT: Index: [[#NFA+8]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -260,7 +259,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 9 +; SYM-NEXT: Index: [[#NFA+9]] ; SYM-NEXT: Name: .rodata ; SYM-NEXT: Value (RelocatableAddress): 0x68 ; SYM-NEXT: Section: .text @@ -268,7 +267,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 10 +; SYM-NEXT: Index: [[#NFA+10]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -280,7 +279,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 11 +; SYM-NEXT: Index: [[#NFA+11]] ; SYM-NEXT: Name: const_ivar ; SYM-NEXT: Value (RelocatableAddress): 0x68 ; SYM-NEXT: Section: .text @@ -288,8 +287,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 12 -; SYM-NEXT: ContainingCsectSymbolIndex: 9 +; SYM-NEXT: Index: [[#NFA+12]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+9]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -300,7 +299,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 13 +; SYM-NEXT: Index: [[#NFA+13]] ; SYM-NEXT: Name: .data ; SYM-NEXT: Value (RelocatableAddress): 0x6C ; SYM-NEXT: Section: .data @@ -308,7 +307,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 14 +; SYM-NEXT: Index: [[#NFA+14]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -320,7 +319,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 15 +; SYM-NEXT: Index: [[#NFA+15]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x6C ; SYM-NEXT: Section: .data @@ -328,8 +327,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 16 -; SYM-NEXT: ContainingCsectSymbolIndex: 13 +; SYM-NEXT: Index: [[#NFA+16]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+13]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -340,7 +339,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 17 +; SYM-NEXT: Index: [[#NFA+17]] ; SYM-NEXT: Name: storesTIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x70 ; SYM-NEXT: Section: .data @@ -348,7 +347,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 18 +; SYM-NEXT: Index: [[#NFA+18]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -360,7 +359,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 19 +; SYM-NEXT: Index: [[#NFA+19]] ; SYM-NEXT: Name: loadsTGInit ; SYM-NEXT: Value (RelocatableAddress): 0x7C ; SYM-NEXT: Section: .data @@ -368,7 +367,7 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 20 +; SYM-NEXT: Index: [[#NFA+20]] ; SYM-NEXT: SectionLen: 12 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -380,7 +379,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 21 +; SYM-NEXT: Index: [[#NFA+21]] ; SYM-NEXT: Name: TOC ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -388,7 +387,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 22 +; SYM-NEXT: Index: [[#NFA+22]] ; SYM-NEXT: SectionLen: 0 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -400,7 +399,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 23 +; SYM-NEXT: Index: [[#NFA+23]] ; SYM-NEXT: Name: .TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x88 ; SYM-NEXT: Section: .data @@ -408,7 +407,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 24 +; SYM-NEXT: Index: [[#NFA+24]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -420,7 +419,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 25 +; SYM-NEXT: Index: [[#NFA+25]] ; SYM-NEXT: Name: TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x8C ; SYM-NEXT: Section: .data @@ -428,7 +427,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 26 +; SYM-NEXT: Index: [[#NFA+26]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -440,7 +439,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 27 +; SYM-NEXT: Index: [[#NFA+27]] ; SYM-NEXT: Name: .TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x90 ; SYM-NEXT: Section: .data @@ -448,7 +447,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 28 +; SYM-NEXT: Index: [[#NFA+28]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -460,7 +459,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 29 +; SYM-NEXT: Index: [[#NFA+29]] ; SYM-NEXT: Name: TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x94 ; SYM-NEXT: Section: .data @@ -468,7 +467,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 30 +; SYM-NEXT: Index: [[#NFA+30]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -480,7 +479,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 31 +; SYM-NEXT: Index: [[#NFA+31]] ; SYM-NEXT: Name: GInit ; SYM-NEXT: Value (RelocatableAddress): 0x98 ; SYM-NEXT: Section: .data @@ -488,7 +487,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 32 +; SYM-NEXT: Index: [[#NFA+32]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -500,7 +499,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 33 +; SYM-NEXT: Index: [[#NFA+33]] ; SYM-NEXT: Name: .tdata ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -508,7 +507,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 34 +; SYM-NEXT: Index: [[#NFA+34]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -520,7 +519,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 35 +; SYM-NEXT: Index: [[#NFA+35]] ; SYM-NEXT: Name: TGInit ; SYM-NEXT: Value (RelocatableAddress): 0x0 ; SYM-NEXT: Section: .tdata @@ -528,8 +527,8 @@ entry: ; SYM-NEXT: StorageClass: C_EXT (0x2) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 36 -; SYM-NEXT: ContainingCsectSymbolIndex: 33 +; SYM-NEXT: Index: [[#NFA+36]] +; SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+33]] ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 ; SYM-NEXT: SymbolAlignmentLog2: 0 @@ -540,7 +539,7 @@ entry: ; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { -; SYM-NEXT: Index: 37 +; SYM-NEXT: Index: [[#NFA+37]] ; SYM-NEXT: Name: TIUninit ; SYM-NEXT: Value (RelocatableAddress): 0x4 ; SYM-NEXT: Section: .tbss @@ -548,7 +547,7 @@ entry: ; SYM-NEXT: StorageClass: C_HIDEXT (0x6B) ; SYM-NEXT: NumberOfAuxEntries: 1 ; SYM-NEXT: CSECT Auxiliary Entry { -; SYM-NEXT: Index: 38 +; SYM-NEXT: Index: [[#NFA+38]] ; SYM-NEXT: SectionLen: 4 ; SYM-NEXT: ParameterHashIndex: 0x0 ; SYM-NEXT: TypeChkSectNum: 0x0 @@ -563,34 +562,34 @@ entry: ; DIS: {{.*}}aix-tls-xcoff-reloc.ll.tmp.o: file format aixcoff-rs6000 ; DIS: Disassembly of section .text: -; DIS: 00000000 (idx: 5) .storesTIUninit: +; DIS: 00000000 (idx: [[#NFA+5]]) .storesTIUninit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: mr 6, 3 ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 0(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 23) .TIUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+23]]) .TIUninit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 4(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 25) TIUninit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+25]]) TIUninit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: stw 6, 0(3) ; DIS-NEXT: addi 1, 1, 32 ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000030 (idx: 7) .loadsTGInit: +; DIS: 00000030 (idx: [[#NFA+7]]) .loadsTGInit: ; DIS-NEXT: mflr 0 ; DIS-NEXT: stwu 1, -32(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 3, 8(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 27) .TGInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+27]]) .TGInit[TC] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 12(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 29) TGInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+29]]) TGInit[TC] ; DIS-NEXT: stw 0, 40(1) ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} bla 0 -; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: 1) .__tls_get_addr[PR] +; DIS-NEXT: {{0*}}[[#ADDR]]: R_RBA (idx: [[#NFA+1]]) .__tls_get_addr[PR] ; DIS-NEXT: [[#%x, ADDR:]]: {{.*}} lwz 4, 16(2) -; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: 31) GInit[TC] +; DIS-NEXT: {{0*}}[[#ADDR + 2]]: R_TOC (idx: [[#NFA+31]]) GInit[TC] ; DIS-NEXT: lwz 3, 0(3) ; DIS-NEXT: lwz 4, 0(4) ; DIS-NEXT: add 3, 4, 3 @@ -598,46 +597,46 @@ entry: ; DIS-NEXT: lwz 0, 8(1) ; DIS-NEXT: mtlr 0 ; DIS-NEXT: blr -; DIS: 00000068 (idx: 11) const_ivar: +; DIS: 00000068 (idx: [[#NFA+11]]) const_ivar: ; DIS-NEXT: 68: 00 00 00 06 ; DIS: Disassembly of section .data: -; DIS: 0000006c (idx: 15) GInit: +; DIS: 0000006c (idx: [[#NFA+15]]) GInit: ; DIS-NEXT: 6c: 00 00 00 01 -; DIS: 00000070 (idx: 17) storesTIUninit[DS]: +; DIS: 00000070 (idx: [[#NFA+17]]) storesTIUninit[DS]: ; DIS-NEXT: 70: 00 00 00 00 -; DIS-NEXT: 00000070: R_POS (idx: 5) .storesTIUninit +; DIS-NEXT: 00000070: R_POS (idx: [[#NFA+5]]) .storesTIUninit ; DIS-NEXT: 74: 00 00 00 88 -; DIS-NEXT: 00000074: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 00000074: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: 78: 00 00 00 00 -; DIS: 0000007c (idx: 19) loadsTGInit[DS]: +; DIS: 0000007c (idx: [[#NFA+19]]) loadsTGInit[DS]: ; DIS-NEXT: 7c: 00 00 00 30 -; DIS-NEXT: 0000007c: R_POS (idx: 7) .loadsTGInit +; DIS-NEXT: 0000007c: R_POS (idx: [[#NFA+7]]) .loadsTGInit ; DIS-NEXT: 80: 00 00 00 88 -; DIS-NEXT: 00000080: R_POS (idx: 21) TOC[TC0] +; DIS-NEXT: 00000080: R_POS (idx: [[#NFA+21]]) TOC[TC0] ; DIS-NEXT: 84: 00 00 00 00 -; DIS: 00000088 (idx: 23) .TIUninit[TC]: +; DIS: 00000088 (idx: [[#NFA+23]]) .TIUninit[TC]: ; DIS-NEXT: 88: 00 00 00 00 -; DIS-NEXT: 00000088: R_TLSM (idx: 37) TIUninit[UL] -; DIS: 0000008c (idx: 25) TIUninit[TC]: +; DIS-NEXT: 00000088: R_TLSM (idx: [[#NFA+37]]) TIUninit[UL] +; DIS: 0000008c (idx: [[#NFA+25]]) TIUninit[TC]: ; DIS-NEXT: 8c: 00 00 00 04 -; DIS-NEXT: 0000008c: R_TLS (idx: 37) TIUninit[UL] -; DIS: 00000090 (idx: 27) .TGInit[TC]: +; DIS-NEXT: 0000008c: R_TLS (idx: [[#NFA+37]]) TIUninit[UL] +; DIS: 00000090 (idx: [[#NFA+27]]) .TGInit[TC]: ; DIS-NEXT: 90: 00 00 00 00 -; DIS-NEXT: 00000090: R_TLSM (idx: 35) TGInit -; DIS: 00000094 (idx: 29) TGInit[TC]: +; DIS-NEXT: 00000090: R_TLSM (idx: [[#NFA+35]]) TGInit +; DIS: 00000094 (idx: [[#NFA+29]]) TGInit[TC]: ; DIS-NEXT: 94: 00 00 00 00 -; DIS-NEXT: 00000094: R_TLS (idx: 35) TGInit -; DIS: 00000098 (idx: 31) GInit[TC]: +; DIS-NEXT: 00000094: R_TLS (idx: [[#NFA+35]]) TGInit +; DIS: 00000098 (idx: [[#NFA+31]]) GInit[TC]: ; DIS-NEXT: 98: 00 00 00 6c -; DIS-NEXT: 00000098: R_POS (idx: 15) GInit +; DIS-NEXT: 00000098: R_POS (idx: [[#NFA+15]]) GInit ; DIS: Disassembly of section .tdata: -; DIS: 00000000 (idx: 35) TGInit: +; DIS: 00000000 (idx: [[#NFA+35]]) TGInit: ; DIS-NEXT: 0: 00 00 00 01 ; DIS: Disassembly of section .tbss: -; DIS: 00000004 (idx: 37) TIUninit[UL]: +; DIS: 00000004 (idx: [[#NFA+37]]) TIUninit[UL]: ; DIS-NEXT: ... attributes #0 = { nofree norecurse nounwind willreturn writeonly "frame-pointer"="none" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="pwr4" "target-features"="-altivec,-bpermd,-crypto,-direct-move,-extdiv,-float128,-htm,-mma,-paired-vector-memops,-power10-vector,-power8-vector,-power9-vector,-spe,-vsx" } diff --git a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll index 3bbdadcdb7bae5bf5ad81f57524ad25d70a18d80..f9a1a61617761d0f1976ce54238bc03074c24ba9 100644 --- a/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll +++ b/llvm/test/CodeGen/PowerPC/aix-tls-xcoff-variables.ll @@ -3,16 +3,16 @@ ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --section-headers %t.o | FileCheck --check-prefix=SECTION %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefixes=SYMS,SYMS-DATASECT %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefixes=OBJDUMP-DATASECT %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefixes=OBJDUMP-DATASECT %s ; RUN: llc -mtriple powerpc-ibm-aix-xcoff -data-sections=false -filetype=obj -o %t.o < %s ; RUN: llvm-readobj --section-headers %t.o | FileCheck --check-prefix=SECTION %s ; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefixes=SYMS,SYMS-NODATASECT %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefixes=OBJDUMP-NODATASECT %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefixes=OBJDUMP-NODATASECT %s ;; FIXME: currently only fileHeader and sectionHeaders are supported in XCOFF64. -; SECTION: File: {{.*}}aix-tls-xcoff-variables.ll.tmp.o +; SECTION: File: ; SECTION-NEXT: Format: aixcoff-rs6000 ; SECTION-NEXT: Arch: powerpc ; SECTION-NEXT: AddressSize: 32bit @@ -59,22 +59,21 @@ ; SECTION-NEXT: ] -; SYMS: File: {{.*}}aix-tls-xcoff-variables.ll.tmp.o +; SYMS: File: ; SYMS-NEXT: Format: aixcoff-rs6000 ; SYMS-NEXT: Arch: powerpc ; SYMS-NEXT: AddressSize: 32bit ; SYMS-NEXT: Symbols [ ; SYMS-NEXT: Symbol { ; SYMS-NEXT: Index: 0 -; SYMS-NEXT: Name: +; SYMS-NEXT: Name: .file ; SYMS-NEXT: Value (SymbolTableIndex): 0x0 ; SYMS-NEXT: Section: N_DEBUG ; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYMS-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYMS-NEXT: StorageClass: C_FILE (0x67) -; SYMS-NEXT: NumberOfAuxEntries: 0 -; SYMS-NEXT: } -; SYMS-NEXT: Symbol { +; SYMS-NEXT: NumberOfAuxEntries: 2 +; SYMS: Symbol { ; SYMS-NEXT: Index: [[#INDX:]] ; SYMS-NEXT: Name: tls_global_int_external_uninitialized ; SYMS-NEXT: Value (RelocatableAddress): 0x0 @@ -531,100 +530,100 @@ ; OBJDUMP-DATASECT: Disassembly of section .text: ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000000 (idx: 7) const_ivar[RO]: +; OBJDUMP-DATASECT-NEXT: 00000000 (idx: [[#NFA+7]]) const_ivar[RO]: ; OBJDUMP-DATASECT-NEXT: 0: 00 00 00 06 ; OBJDUMP-DATASECT-EMPTY: ; OBJDUMP-DATASECT-NEXT: Disassembly of section .tdata: ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000000 (idx: 11) tls_global_alias_int_external_val_initialized: +; OBJDUMP-DATASECT-NEXT: 00000000 (idx: [[#NFA+11]]) tls_global_alias_int_external_val_initialized: ; OBJDUMP-DATASECT-NEXT: 0: 00 00 00 01 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000004 (idx: 13) tls_global_int_external_zero_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000004 (idx: [[#NFA+13]]) tls_global_int_external_zero_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 4: 00 00 00 00 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000008 (idx: 15) tls_global_int_local_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000008 (idx: [[#NFA+15]]) tls_global_int_local_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 8: 00 00 00 02 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 0000000c (idx: 17) tls_global_int_weak_zero_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 0000000c (idx: [[#NFA+17]]) tls_global_int_weak_zero_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: c: 00 00 00 00 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000010 (idx: 19) tls_global_int_weak_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000010 (idx: [[#NFA+19]]) tls_global_int_weak_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 10: 00 00 00 01 ; OBJDUMP-DATASECT-NEXT: 14: 00 00 00 00 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000018 (idx: 21) tls_global_long_long_internal_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000018 (idx: [[#NFA+21]]) tls_global_long_long_internal_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 18: 00 00 00 00 ; OBJDUMP-DATASECT-NEXT: 1c: 00 00 00 01 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000020 (idx: 23) tls_global_long_long_weak_val_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000020 (idx: [[#NFA+23]]) tls_global_long_long_weak_val_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: 20: 00 00 00 00 ; OBJDUMP-DATASECT-NEXT: 24: 00 00 00 01 ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000028 (idx: 25) tls_global_long_long_weak_zero_initialized[TL]: +; OBJDUMP-DATASECT-NEXT: 00000028 (idx: [[#NFA+25]]) tls_global_long_long_weak_zero_initialized[TL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: ; OBJDUMP-DATASECT-NEXT: Disassembly of section .tbss: ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000030 (idx: 27) tls_global_int_local_zero_initialized[UL]: +; OBJDUMP-DATASECT-NEXT: 00000030 (idx: [[#NFA+27]]) tls_global_int_local_zero_initialized[UL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000034 (idx: 29) tls_global_int_common_zero_initialized[UL]: +; OBJDUMP-DATASECT-NEXT: 00000034 (idx: [[#NFA+29]]) tls_global_int_common_zero_initialized[UL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000038 (idx: 31) tls_global_double_common_zero_initialized[UL] +; OBJDUMP-DATASECT-NEXT: 00000038 (idx: [[#NFA+31]]) tls_global_double_common_zero_initialized[UL] ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-DATASECT-EMPTY: -; OBJDUMP-DATASECT-NEXT: 00000040 (idx: 33) tls_global_long_long_internal_zero_initialized[UL]: +; OBJDUMP-DATASECT-NEXT: 00000040 (idx: [[#NFA+33]]) tls_global_long_long_internal_zero_initialized[UL]: ; OBJDUMP-DATASECT-NEXT: ... ; OBJDUMP-NODATASECT: Disassembly of section .text: ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000000 (idx: 9) const_ivar: +; OBJDUMP-NODATASECT-NEXT: 00000000 (idx: [[#NFA+9]]) const_ivar: ; OBJDUMP-NODATASECT-NEXT: 0: 00 00 00 06 ; OBJDUMP-NODATASECT-EMPTY: ; OBJDUMP-NODATASECT-NEXT: Disassembly of section .tdata: ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT: 00000000 (idx: 13) tls_global_int_external_val_initialized: +; OBJDUMP-NODATASECT: 00000000 (idx: [[#NFA+13]]) tls_global_int_external_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 0: 00 00 00 01 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000004 (idx: 17) tls_global_int_external_zero_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000004 (idx: [[#NFA+17]]) tls_global_int_external_zero_initialized: ; OBJDUMP-NODATASECT-NEXT: 4: 00 00 00 00 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000008 (idx: 19) tls_global_int_local_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000008 (idx: [[#NFA+19]]) tls_global_int_local_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 8: 00 00 00 02 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 0000000c (idx: 21) tls_global_int_weak_zero_initialized: +; OBJDUMP-NODATASECT-NEXT: 0000000c (idx: [[#NFA+21]]) tls_global_int_weak_zero_initialized: ; OBJDUMP-NODATASECT-NEXT: c: 00 00 00 00 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000010 (idx: 23) tls_global_int_weak_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000010 (idx: [[#NFA+23]]) tls_global_int_weak_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 10: 00 00 00 01 ; OBJDUMP-NODATASECT-NEXT: 14: 00 00 00 00 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000018 (idx: 25) tls_global_long_long_internal_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000018 (idx: [[#NFA+25]]) tls_global_long_long_internal_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 18: 00 00 00 00 ; OBJDUMP-NODATASECT-NEXT: 1c: 00 00 00 01 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000020 (idx: 27) tls_global_long_long_weak_val_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000020 (idx: [[#NFA+27]]) tls_global_long_long_weak_val_initialized: ; OBJDUMP-NODATASECT-NEXT: 20: 00 00 00 00 ; OBJDUMP-NODATASECT-NEXT: 24: 00 00 00 01 ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000028 (idx: 29) tls_global_long_long_weak_zero_initialized: +; OBJDUMP-NODATASECT-NEXT: 00000028 (idx: [[#NFA+29]]) tls_global_long_long_weak_zero_initialized: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: ; OBJDUMP-NODATASECT-NEXT: Disassembly of section .tbss: ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000030 (idx: 31) tls_global_int_local_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000030 (idx: [[#NFA+31]]) tls_global_int_local_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000034 (idx: 33) tls_global_int_common_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000034 (idx: [[#NFA+33]]) tls_global_int_common_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000038 (idx: 35) tls_global_double_common_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000038 (idx: [[#NFA+35]]) tls_global_double_common_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... ; OBJDUMP-NODATASECT-EMPTY: -; OBJDUMP-NODATASECT-NEXT: 00000040 (idx: 37) tls_global_long_long_internal_zero_initialized[UL]: +; OBJDUMP-NODATASECT-NEXT: 00000040 (idx: [[#NFA+37]]) tls_global_long_long_internal_zero_initialized[UL]: ; OBJDUMP-NODATASECT-NEXT: ... @tls_global_int_external_val_initialized = thread_local global i32 1, align 4 diff --git a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll index 6891637b8fcbf8fb10aeeee0f0133d66784ac59f..4f1735a7435544c8feef6d401ff9fb3ee4af6dcf 100644 --- a/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll +++ b/llvm/test/CodeGen/PowerPC/aix-user-defined-memcpy.ll @@ -1,12 +1,12 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -filetype=obj -xcoff-traceback-table=false -o %t.o < %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefix=32-SYM %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefix=32-SYM %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck \ +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 \ ; RUN: --check-prefix=32-REL %s -; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=32-DIS %s +; RUN: llvm-objdump -D %t.o | FileCheck -D#NFA=2 --check-prefix=32-DIS %s ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -mcpu=pwr4 -mattr=-altivec < %s | FileCheck %s @@ -45,7 +45,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-SYM-NEXT: StorageClass: C_EXT (0x2) ; 32-SYM-NEXT: NumberOfAuxEntries: 1 ; 32-SYM-NEXT: CSECT Auxiliary Entry { -; 32-SYM-NEXT: Index: 2 +; 32-SYM-NEXT: Index: [[#NFA+2]] ; 32-SYM-NEXT: SectionLen: 0 ; 32-SYM-NEXT: ParameterHashIndex: 0x0 ; 32-SYM-NEXT: TypeChkSectNum: 0x0 @@ -64,8 +64,8 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-SYM-NEXT: StorageClass: C_EXT (0x2) ; 32-SYM-NEXT: NumberOfAuxEntries: 1 ; 32-SYM-NEXT: CSECT Auxiliary Entry { -; 32-SYM-NEXT: Index: 6 -; 32-SYM-NEXT: ContainingCsectSymbolIndex: 3 +; 32-SYM-NEXT: Index: [[#NFA+6]] +; 32-SYM-NEXT: ContainingCsectSymbolIndex: [[#NFA+3]] ; 32-SYM-NEXT: ParameterHashIndex: 0x0 ; 32-SYM-NEXT: TypeChkSectNum: 0x0 ; 32-SYM-NEXT: SymbolAlignmentLog2: 0 @@ -82,7 +82,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: Section (index: 1) .text { ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x1C -; 32-REL-NEXT: Symbol: .___memmove (1) +; 32-REL-NEXT: Symbol: .___memmove ([[#NFA+1]]) ; 32-REL-NEXT: IsSigned: Yes ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 26 @@ -92,7 +92,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: Section (index: 2) .data { ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x34 -; 32-REL-NEXT: Symbol: .memcpy (5) +; 32-REL-NEXT: Symbol: .memcpy ([[#NFA+5]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 @@ -100,7 +100,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: } ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x38 -; 32-REL-NEXT: Symbol: TOC (13) +; 32-REL-NEXT: Symbol: TOC ([[#NFA+13]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 @@ -108,7 +108,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: } ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x40 -; 32-REL-NEXT: Symbol: .call_memcpy (7) +; 32-REL-NEXT: Symbol: .call_memcpy ([[#NFA+7]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 @@ -116,7 +116,7 @@ declare void @llvm.memcpy.p0.p0.i32(ptr nocapture writeonly, ptr nocapture reado ; 32-REL-NEXT: } ; 32-REL-NEXT: Relocation { ; 32-REL-NEXT: Virtual Address: 0x44 -; 32-REL-NEXT: Symbol: TOC (13) +; 32-REL-NEXT: Symbol: TOC ([[#NFA+13]]) ; 32-REL-NEXT: IsSigned: No ; 32-REL-NEXT: FixupBitValue: 0 ; 32-REL-NEXT: Length: 32 diff --git a/llvm/test/CodeGen/PowerPC/aix-weak.ll b/llvm/test/CodeGen/PowerPC/aix-weak.ll index 84ef83a9b9661ae3551e48fb928641a95fea6d43..7bf80ad19e9e01afecd8ab93ee555b456afe01e7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-weak.ll +++ b/llvm/test/CodeGen/PowerPC/aix-weak.ll @@ -100,16 +100,15 @@ entry: ; CHECKSYM: Symbols [ ; CHECKSYM-NEXT: Symbol { ; CHECKSYM-NEXT: Index: 0 -; CHECKSYM-NEXT: Name: +; CHECKSYM-NEXT: Name: .file ; CHECKSYM-NEXT: Value (SymbolTableIndex): 0x0 ; CHECKSYM-NEXT: Section: N_DEBUG ; CHECKSYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; CHECKSYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; CHECKSYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; CHECKSYM-NEXT: StorageClass: C_FILE (0x67) -; CHECKSYM-NEXT: NumberOfAuxEntries: 0 -; CHECKSYM-NEXT: } -; CHECKSYM-NEXT: Symbol { +; CHECKSYM-NEXT: NumberOfAuxEntries: 2 +; CHECKSYM: Symbol { ; CHECKSYM-NEXT: Index: [[#Index:]] ; CHECKSYM-NEXT: Name: ; CHECKSYM-NEXT: Value (RelocatableAddress): 0x0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll index db6071653b6bccaabfca33a180aadff9382f9dd0..6464257c6f266a231b6535f226f52f4e4abccb76 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-cold.ll @@ -2,7 +2,7 @@ ; RUN: llvm-objdump --syms %t.o | FileCheck %s ; CHECK: SYMBOL TABLE: -; CHECK-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 +; CHECK-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 .file ; CHECK-NEXT: 0000000000000000 l .text 000000000000001e ; CHECK-NEXT: 0000000000000000 g F .text (csect: ) 0000000000000000 .cold_fun ; CHECK-NEXT: 0000000000000020 g O .data 0000000000000018 cold_fun diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll index 9072e98aecb2447dcf1066eca4da820e0014ccab..19c623c502132d78f4901f9d7ee6b2b20f47fd73 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data-sections.ll @@ -5,7 +5,7 @@ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -filetype=obj -data-sections -xcoff-traceback-table=false -o %t.o < %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -s %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. @@ -16,7 +16,7 @@ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -s %t.o | FileCheck --check-prefix=CHECKSYM %s ;; Test to see if the default is correct for -data-sections on AIX. @@ -28,7 +28,7 @@ ; RUN: FileCheck --check-prefixes=CHECK,CHECK64 %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mattr=-altivec -mtriple powerpc-ibm-aix-xcoff \ ; RUN: -xcoff-traceback-table=false -filetype=obj -o %t.o < %s -; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck --check-prefix=CHECKOBJ %s +; RUN: llvm-objdump -D --symbol-description %t.o | FileCheck -D#NFA=2 --check-prefix=CHECKOBJ %s ; RUN: llvm-readobj -s %t.o | FileCheck --check-prefix=CHECKSYM %s @ivar = local_unnamed_addr global i32 35, align 4 @@ -90,50 +90,50 @@ entry: ; CHECK-NEXT: L..C3: ; CHECK-NEXT: .tc f[TC],f[RW] -; CHECKOBJ: 00000038 (idx: 7) const_ivar[RO]: +; CHECKOBJ: 00000038 (idx: [[#NFA+7]]) const_ivar[RO]: ; CHECKOBJ-NEXT: 38: 00 00 00 23 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000003c (idx: 9) L...str[RO]: +; CHECKOBJ-NEXT: 0000003c (idx: [[#NFA+9]]) L...str[RO]: ; CHECKOBJ-NEXT: 3c: 61 62 63 64 ; CHECKOBJ-NEXT: 40: 65 66 67 68 ; CHECKOBJ-NEXT: 44: 00 00 00 00 ; CHECKOBJ-EMPTY: ; CHECKOBJ-NEXT: Disassembly of section .data: ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000048 (idx: 11) ivar[RW]: +; CHECKOBJ-NEXT: 00000048 (idx: [[#NFA+11]]) ivar[RW]: ; CHECKOBJ-NEXT: 48: 00 00 00 23 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000004c (idx: 13) p[RW]: +; CHECKOBJ-NEXT: 0000004c (idx: [[#NFA+13]]) p[RW]: ; CHECKOBJ-NEXT: 4c: 00 00 00 3c ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000050 (idx: 15) foo[DS]: +; CHECKOBJ-NEXT: 00000050 (idx: [[#NFA+15]]) foo[DS]: ; CHECKOBJ-NEXT: 50: 00 00 00 00 ; CHECKOBJ-NEXT: 54: 00 00 00 68 ; CHECKOBJ-NEXT: 58: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000005c (idx: 17) bar[DS]: +; CHECKOBJ-NEXT: 0000005c (idx: [[#NFA+17]]) bar[DS]: ; CHECKOBJ-NEXT: 5c: 00 00 00 10 ; CHECKOBJ-NEXT: 60: 00 00 00 68 ; CHECKOBJ-NEXT: 64: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000068 (idx: 21) p[TC]: +; CHECKOBJ-NEXT: 00000068 (idx: [[#NFA+21]]) p[TC]: ; CHECKOBJ-NEXT: 68: 00 00 00 4c ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000006c (idx: 23) ivar[TC]: +; CHECKOBJ-NEXT: 0000006c (idx: [[#NFA+23]]) ivar[TC]: ; CHECKOBJ-NEXT: 6c: 00 00 00 48 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000070 (idx: 25) a[TC]: +; CHECKOBJ-NEXT: 00000070 (idx: [[#NFA+25]]) a[TC]: ; CHECKOBJ-NEXT: 70: 00 00 00 78 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000074 (idx: 27) f[TC]: +; CHECKOBJ-NEXT: 00000074 (idx: [[#NFA+27]]) f[TC]: ; CHECKOBJ-NEXT: 74: 00 00 00 7c ; CHECKOBJ-EMPTY: ; CHECKOBJ-NEXT: Disassembly of section .bss: ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000078 (idx: 29) a[RW]: +; CHECKOBJ-NEXT: 00000078 (idx: [[#NFA+29]]) a[RW]: ; CHECKOBJ-NEXT: ... ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000007c (idx: 31) f[RW]: +; CHECKOBJ-NEXT: 0000007c (idx: [[#NFA+31]]) f[RW]: ; CHECKOBJ-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll index 58958e399cb082b17213bcb5d851f5ea8f789fd3..de937386b8b7d0c4d7b8bf8706f20a27f56544e1 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-data.ll @@ -147,7 +147,7 @@ ; CHECK-NEXT: .comm over_aligned_comm[RW],8,5 ; CHECK-NEXT: .comm array[RW],33,0 -; OBJ: File: {{.*}}aix-xcoff-data.ll.tmp.o +; OBJ: File: ; OBJ-NEXT: Format: aixcoff-rs6000 ; OBJ-NEXT: Arch: powerpc ; OBJ-NEXT: AddressSize: 32bit @@ -156,7 +156,7 @@ ; OBJ-NEXT: NumberOfSections: 3 ; OBJ-NEXT: TimeStamp: ; OBJ-NEXT: SymbolTableOffset: 0x10C -; OBJ-NEXT: SymbolTableEntries: 45 +; OBJ-NEXT: SymbolTableEntries: 47 ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } @@ -208,14 +208,26 @@ ; SYMS: Symbols [ ; SYMS-NEXT: Symbol { ; SYMS-NEXT: Index: 0 -; SYMS-NEXT: Name: +; SYMS-NEXT: Name: .file ; SYMS-NEXT: Value (SymbolTableIndex): 0x0 ; SYMS-NEXT: Section: N_DEBUG ; SYMS-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYMS32-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYMS64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; SYMS-NEXT: StorageClass: C_FILE (0x67) -; SYMS-NEXT: NumberOfAuxEntries: 0 +; SYMS-NEXT: NumberOfAuxEntries: 2 +; SYMS-NEXT: File Auxiliary Entry { +; SYMS-NEXT: Index: 1 +; SYMS-NEXT: Name: +; SYMS-NEXT: Type: XFT_FN (0x0) +; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYMS-NEXT: } +; SYMS-NEXT: File Auxiliary Entry { +; SYMS-NEXT: Index: 2 +; SYMS-NEXT: Name: LLVM +; SYMS-NEXT: Type: XFT_CV (0x2) +; SYMS64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYMS-NEXT: } ; SYMS-NEXT: } ; SYMS-NEXT: Symbol { ; SYMS-NEXT: Index: [[#INDX:]] @@ -710,7 +722,7 @@ ; OBJ64-NEXT: NumberOfSections: 3 ; OBJ64-NEXT: TimeStamp: None (0x0) ; OBJ64-NEXT: SymbolTableOffset: 0x170 -; OBJ64-NEXT: SymbolTableEntries: 45 +; OBJ64-NEXT: SymbolTableEntries: 47 ; OBJ64-NEXT: OptionalHeaderSize: 0x0 ; OBJ64-NEXT: Flags: 0x0 ; OBJ64-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll index 01d0aa9e173f91cd26af04ed4ee2e9c3c5edb7cb..bc6e9f35019828a02fc570cb10367d654f766097 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section-debug.ll @@ -47,7 +47,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS32-NEXT: } ; SYMS32-NEXT: CSECT Auxiliary Entry { ; SYMS32-NEXT: Index: [[#IND+2]] -; SYMS32-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS32-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS32-NEXT: ParameterHashIndex: 0x0 ; SYMS32-NEXT: TypeChkSectNum: 0x0 ; SYMS32-NEXT: SymbolAlignmentLog2: 0 @@ -74,7 +74,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS32-NEXT: } ; SYMS32-NEXT: CSECT Auxiliary Entry { ; SYMS32-NEXT: Index: [[#IND+5]] -; SYMS32-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS32-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS32-NEXT: ParameterHashIndex: 0x0 ; SYMS32-NEXT: TypeChkSectNum: 0x0 ; SYMS32-NEXT: SymbolAlignmentLog2: 0 @@ -107,7 +107,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+3]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 @@ -140,7 +140,7 @@ define dso_local void @test__trap_annotation_debug(i32 %a) !dbg !4 { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+7]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll index 17047460f7ca8964b4f7ced63f405d569378f148..8ee58755919b7f1308752e9083e892ee317dfc77 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-exception-section.ll @@ -24,13 +24,13 @@ define dso_local void @test__trap_annotation(i32 %a) { } ; EXCEPT: Exception section { -; EXCEPT-NEXT: Symbol: .sub_test (3) +; EXCEPT-NEXT: Symbol: .sub_test ; EXCEPT-NEXT: LangID: 0 ; EXCEPT-NEXT: Reason: 0 ; EXCEPT-NEXT: Trap Instr Addr: 0x4 ; EXCEPT-NEXT: LangID: 1 ; EXCEPT-NEXT: Reason: 2 -; EXCEPT-NEXT: Symbol: .test__trap_annotation (6) +; EXCEPT-NEXT: Symbol: .test__trap_annotation ; EXCEPT-NEXT: LangID: 0 ; EXCEPT-NEXT: Reason: 0 ; EXCEPT-NEXT: Trap Instr Addr: 0x3C @@ -75,7 +75,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS-NEXT: } ; SYMS-NEXT: CSECT Auxiliary Entry { ; SYMS-NEXT: Index: [[#IND+2]] -; SYMS-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS-NEXT: ParameterHashIndex: 0x0 ; SYMS-NEXT: TypeChkSectNum: 0x0 ; SYMS-NEXT: SymbolAlignmentLog2: 0 @@ -102,7 +102,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS-NEXT: } ; SYMS-NEXT: CSECT Auxiliary Entry { ; SYMS-NEXT: Index: [[#IND+5]] -; SYMS-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS-NEXT: ParameterHashIndex: 0x0 ; SYMS-NEXT: TypeChkSectNum: 0x0 ; SYMS-NEXT: SymbolAlignmentLog2: 0 @@ -114,13 +114,13 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS-NEXT: } ; EXCEPT64: Exception section { -; EXCEPT64-NEXT: Symbol: .sub_test (3) +; EXCEPT64-NEXT: Symbol: .sub_test ; EXCEPT64-NEXT: LangID: 0 ; EXCEPT64-NEXT: Reason: 0 ; EXCEPT64-NEXT: Trap Instr Addr: 0x4 ; EXCEPT64-NEXT: LangID: 1 ; EXCEPT64-NEXT: Reason: 2 -; EXCEPT64-NEXT: Symbol: .test__trap_annotation (6) +; EXCEPT64-NEXT: Symbol: .test__trap_annotation ; EXCEPT64-NEXT: LangID: 0 ; EXCEPT64-NEXT: Reason: 0 ; EXCEPT64-NEXT: Trap Instr Addr: 0x3C @@ -163,7 +163,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+2]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 @@ -189,7 +189,7 @@ define dso_local void @test__trap_annotation(i32 %a) { ; SYMS64-NEXT: } ; SYMS64-NEXT: CSECT Auxiliary Entry { ; SYMS64-NEXT: Index: [[#IND+5]] -; SYMS64-NEXT: ContainingCsectSymbolIndex: 1 +; SYMS64-NEXT: ContainingCsectSymbolIndex: [[#IND-2]] ; SYMS64-NEXT: ParameterHashIndex: 0x0 ; SYMS64-NEXT: TypeChkSectNum: 0x0 ; SYMS64-NEXT: SymbolAlignmentLog2: 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll index a38da2229a7e8202ca1d9af9af29b25273efc644..a28c2f2eefea28892875ee2e5d213cb03e773a13 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-explicit-section.ll @@ -48,7 +48,7 @@ entry: ; CHECK-NEXT: L..C1: ; CHECK-NEXT: .tc ext_zvar[TC],ext_zvar -; CHECKOBJ: 00000000 (idx: 5) .ext_fun: +; CHECKOBJ: 00000000 (idx: [[#INDX:]]) .ext_fun: ; CHECKOBJ-NEXT: 0: 80 62 00 00 lwz 3, 0(2) ; CHECKOBJ-NEXT: 4: 80 82 00 04 lwz 4, 4(2) ; CHECKOBJ-NEXT: 8: 80 63 00 00 lwz 3, 0(3) @@ -57,26 +57,26 @@ entry: ; CHECKOBJ-NEXT: 14: 38 63 00 01 addi 3, 3, 1 ; CHECKOBJ-NEXT: 18: 4e 80 00 20 blr ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 0000001c (idx: 9) ext_const: +; CHECKOBJ-NEXT: 0000001c (idx: [[#INDX+4]]) ext_const: ; CHECKOBJ-NEXT: 1c: 00 00 00 01 ; CHECKOBJ-EMPTY: ; CHECKOBJ-NEXT: Disassembly of section .data: ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000020 (idx: 13) ext_var: +; CHECKOBJ-NEXT: 00000020 (idx: [[#INDX+8]]) ext_var: ; CHECKOBJ-NEXT: 20: 00 00 00 01 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000024 (idx: 17) ext_zvar: +; CHECKOBJ-NEXT: 00000024 (idx: [[#INDX+12]]) ext_zvar: ; CHECKOBJ-NEXT: 24: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000028 (idx: 19) ext_fun[DS]: +; CHECKOBJ-NEXT: 00000028 (idx: [[#INDX+14]]) ext_fun[DS]: ; CHECKOBJ-NEXT: 28: 00 00 00 00 ; CHECKOBJ-NEXT: 2c: 00 00 00 34 ; CHECKOBJ-NEXT: 30: 00 00 00 00 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000034 (idx: 23) ext_var[TC]: +; CHECKOBJ-NEXT: 00000034 (idx: [[#INDX+18]]) ext_var[TC]: ; CHECKOBJ-NEXT: 34: 00 00 00 20 ; CHECKOBJ-EMPTY: -; CHECKOBJ-NEXT: 00000038 (idx: 25) ext_zvar[TC]: +; CHECKOBJ-NEXT: 00000038 (idx: [[#INDX+20]]) ext_zvar[TC]: ; CHECKOBJ-NEXT: 38: 00 00 00 24 ; CHECKSYM: Symbol {{[{][[:space:]] *}}Index: [[#INDX:]]{{[[:space:]] *}}Name: .ext_fun_sec diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll index a557b6f4f171989b9d292f7ed6713720352038bd..dbfbd0de08b9907f0cd415a12d7f5e0f69aead2c 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-funcsect.ll @@ -9,17 +9,17 @@ ; RUN: -mattr=-altivec -function-sections -xcoff-traceback-table=true \ ; RUN: -filetype=obj -o %t32.o < %s ; RUN: llvm-objdump --syms --reloc --symbol-description %t32.o | \ -; RUN: FileCheck --check-prefix=XCOFF32 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=XCOFF32 %s ; RUN: llvm-objdump -dr --symbol-description %t32.o | \ -; RUN: FileCheck --check-prefix=DIS32 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=DIS32 %s ; RUN: llc -verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -function-sections -xcoff-traceback-table=true \ ; RUN: -filetype=obj -o %t64.o < %s ; RUN: llvm-objdump --syms --reloc --symbol-description %t64.o | \ -; RUN: FileCheck --check-prefix=XCOFF64 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=XCOFF64 %s ; RUN: llvm-objdump -dr --symbol-description %t64.o | \ -; RUN: FileCheck --check-prefix=DIS64 %s +; RUN: FileCheck -D#NFA=2 --check-prefix=DIS64 %s @alias_foo = alias void (...), ptr @foo @@ -113,117 +113,117 @@ entry: ; ASM-NEXT: .globl .alias_foo ; XCOFF32: SYMBOL TABLE: -; XCOFF32-NEXT: 00000000 df *DEBUG* 00000000 (idx: 0) -; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: 1) .extern_foo[PR] -; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: 3) extern_foo[DS] -; XCOFF32-NEXT: 00000000 l .text 00000000 (idx: 5) [PR] -; XCOFF32-NEXT: 00000000 g .text 00000019 (idx: 7) .foo[PR] -; XCOFF32-NEXT: 00000000 g F .text (csect: (idx: 7) .foo[PR]) 00000000 (idx: 9) .alias_foo -; XCOFF32-NEXT: 00000020 g F .text 00000020 .hidden (idx: 11) .hidden_foo[PR] -; XCOFF32-NEXT: 00000040 g F .text 00000059 (idx: 13) .bar[PR] -; XCOFF32-NEXT: 000000c0 l F .text 0000002a (idx: 15) .static_overalign_foo[PR] -; XCOFF32-NEXT: 000000ec g O .data 0000000c (idx: 17) foo[DS] -; XCOFF32-NEXT: 000000ec g O .data (csect: (idx: 17) foo[DS]) 00000000 (idx: 19) alias_foo -; XCOFF32-NEXT: 000000f8 g O .data 0000000c .hidden (idx: 21) hidden_foo[DS] -; XCOFF32-NEXT: 00000104 g O .data 0000000c (idx: 23) bar[DS] -; XCOFF32-NEXT: 00000110 l O .data 0000000c (idx: 25) static_overalign_foo[DS] -; XCOFF32-NEXT: 0000011c l .data 00000000 (idx: 27) TOC[TC0] +; XCOFF32-NEXT: 00000000 df *DEBUG* 00000000 (idx: 0) .file +; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF32-NEXT: 00000000 *UND* 00000000 (idx: [[#NFA+3]]) extern_foo[DS] +; XCOFF32-NEXT: 00000000 l .text 00000000 (idx: [[#NFA+5]]) [PR] +; XCOFF32-NEXT: 00000000 g .text 00000019 (idx: [[#NFA+7]]) .foo[PR] +; XCOFF32-NEXT: 00000000 g F .text (csect: (idx: [[#NFA+7]]) .foo[PR]) 00000000 (idx: [[#NFA+9]]) .alias_foo +; XCOFF32-NEXT: 00000020 g F .text 00000020 .hidden (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF32-NEXT: 00000040 g F .text 00000059 (idx: [[#NFA+13]]) .bar[PR] +; XCOFF32-NEXT: 000000c0 l F .text 0000002a (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF32-NEXT: 000000ec g O .data 0000000c (idx: [[#NFA+17]]) foo[DS] +; XCOFF32-NEXT: 000000ec g O .data (csect: (idx: [[#NFA+17]]) foo[DS]) 00000000 (idx: [[#NFA+19]]) alias_foo +; XCOFF32-NEXT: 000000f8 g O .data 0000000c .hidden (idx: [[#NFA+21]]) hidden_foo[DS] +; XCOFF32-NEXT: 00000104 g O .data 0000000c (idx: [[#NFA+23]]) bar[DS] +; XCOFF32-NEXT: 00000110 l O .data 0000000c (idx: [[#NFA+25]]) static_overalign_foo[DS] +; XCOFF32-NEXT: 0000011c l .data 00000000 (idx: [[#NFA+27]]) TOC[TC0] ; XCOFF32: RELOCATION RECORDS FOR [.text]: ; XCOFF32-NEXT: OFFSET TYPE VALUE -; XCOFF32-NEXT: 0000004c R_RBR (idx: 7) .foo[PR] -; XCOFF32-NEXT: 00000054 R_RBR (idx: 15) .static_overalign_foo[PR] -; XCOFF32-NEXT: 0000005c R_RBR (idx: 9) .alias_foo -; XCOFF32-NEXT: 00000064 R_RBR (idx: 1) .extern_foo[PR] -; XCOFF32-NEXT: 0000006c R_RBR (idx: 11) .hidden_foo[PR] +; XCOFF32-NEXT: 0000004c R_RBR (idx: [[#NFA+7]]) .foo[PR] +; XCOFF32-NEXT: 00000054 R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF32-NEXT: 0000005c R_RBR (idx: [[#NFA+9]]) .alias_foo +; XCOFF32-NEXT: 00000064 R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF32-NEXT: 0000006c R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] ; XCOFF32: RELOCATION RECORDS FOR [.data]: ; XCOFF32-NEXT: OFFSET TYPE VALUE -; XCOFF32-NEXT: 00000000 R_POS (idx: 7) .foo[PR] -; XCOFF32-NEXT: 00000004 R_POS (idx: 27) TOC[TC0] -; XCOFF32-NEXT: 0000000c R_POS (idx: 11) .hidden_foo[PR] -; XCOFF32-NEXT: 00000010 R_POS (idx: 27) TOC[TC0] -; XCOFF32-NEXT: 00000018 R_POS (idx: 13) .bar[PR] -; XCOFF32-NEXT: 0000001c R_POS (idx: 27) TOC[TC0] -; XCOFF32-NEXT: 00000024 R_POS (idx: 15) .static_overalign_foo[PR] -; XCOFF32-NEXT: 00000028 R_POS (idx: 27) TOC[TC0] +; XCOFF32-NEXT: 00000000 R_POS (idx: [[#NFA+7]]) .foo[PR] +; XCOFF32-NEXT: 00000004 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF32-NEXT: 0000000c R_POS (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF32-NEXT: 00000010 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF32-NEXT: 00000018 R_POS (idx: [[#NFA+13]]) .bar[PR] +; XCOFF32-NEXT: 0000001c R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF32-NEXT: 00000024 R_POS (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF32-NEXT: 00000028 R_POS (idx: [[#NFA+27]]) TOC[TC0] ; XCOFF64: SYMBOL TABLE: -; XCOFF64-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 (idx: 0) -; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: 1) .extern_foo[PR] -; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: 3) extern_foo[DS] -; XCOFF64-NEXT: 0000000000000000 l .text 0000000000000000 (idx: 5) [PR] -; XCOFF64-NEXT: 0000000000000000 g .text 0000000000000019 (idx: 7) .foo[PR] -; XCOFF64-NEXT: 0000000000000000 g F .text (csect: (idx: 7) .foo[PR]) 0000000000000000 (idx: 9) .alias_foo -; XCOFF64-NEXT: 0000000000000020 g F .text 0000000000000020 .hidden (idx: 11) .hidden_foo[PR] -; XCOFF64-NEXT: 0000000000000040 g F .text 0000000000000059 (idx: 13) .bar[PR] -; XCOFF64-NEXT: 00000000000000c0 l F .text 000000000000002a (idx: 15) .static_overalign_foo[PR] -; XCOFF64-NEXT: 00000000000000f0 g O .data 0000000000000018 (idx: 17) foo[DS] -; XCOFF64-NEXT: 00000000000000f0 g O .data (csect: (idx: 17) foo[DS]) 0000000000000000 (idx: 19) alias_foo -; XCOFF64-NEXT: 0000000000000108 g O .data 0000000000000018 .hidden (idx: 21) hidden_foo[DS] -; XCOFF64-NEXT: 0000000000000120 g O .data 0000000000000018 (idx: 23) bar[DS] -; XCOFF64-NEXT: 0000000000000138 l O .data 0000000000000018 (idx: 25) static_overalign_foo[DS] -; XCOFF64-NEXT: 0000000000000150 l .data 0000000000000000 (idx: 27) TOC[TC0] +; XCOFF64-NEXT: 0000000000000000 df *DEBUG* 0000000000000000 (idx: 0) .file +; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF64-NEXT: 0000000000000000 *UND* 0000000000000000 (idx: [[#NFA+3]]) extern_foo[DS] +; XCOFF64-NEXT: 0000000000000000 l .text 0000000000000000 (idx: [[#NFA+5]]) [PR] +; XCOFF64-NEXT: 0000000000000000 g .text 0000000000000019 (idx: [[#NFA+7]]) .foo[PR] +; XCOFF64-NEXT: 0000000000000000 g F .text (csect: (idx: [[#NFA+7]]) .foo[PR]) 0000000000000000 (idx: [[#NFA+9]]) .alias_foo +; XCOFF64-NEXT: 0000000000000020 g F .text 0000000000000020 .hidden (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF64-NEXT: 0000000000000040 g F .text 0000000000000059 (idx: [[#NFA+13]]) .bar[PR] +; XCOFF64-NEXT: 00000000000000c0 l F .text 000000000000002a (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF64-NEXT: 00000000000000f0 g O .data 0000000000000018 (idx: [[#NFA+17]]) foo[DS] +; XCOFF64-NEXT: 00000000000000f0 g O .data (csect: (idx: [[#NFA+17]]) foo[DS]) 0000000000000000 (idx: [[#NFA+19]]) alias_foo +; XCOFF64-NEXT: 0000000000000108 g O .data 0000000000000018 .hidden (idx: [[#NFA+21]]) hidden_foo[DS] +; XCOFF64-NEXT: 0000000000000120 g O .data 0000000000000018 (idx: [[#NFA+23]]) bar[DS] +; XCOFF64-NEXT: 0000000000000138 l O .data 0000000000000018 (idx: [[#NFA+25]]) static_overalign_foo[DS] +; XCOFF64-NEXT: 0000000000000150 l .data 0000000000000000 (idx: [[#NFA+27]]) TOC[TC0] ; XCOFF64: RELOCATION RECORDS FOR [.text]: ; XCOFF64-NEXT: OFFSET TYPE VALUE -; XCOFF64-NEXT: 000000000000004c R_RBR (idx: 7) .foo[PR] -; XCOFF64-NEXT: 0000000000000054 R_RBR (idx: 15) .static_overalign_foo[PR] -; XCOFF64-NEXT: 000000000000005c R_RBR (idx: 9) .alias_foo -; XCOFF64-NEXT: 0000000000000064 R_RBR (idx: 1) .extern_foo[PR] -; XCOFF64-NEXT: 000000000000006c R_RBR (idx: 11) .hidden_foo[PR] +; XCOFF64-NEXT: 000000000000004c R_RBR (idx: [[#NFA+7]]) .foo[PR] +; XCOFF64-NEXT: 0000000000000054 R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF64-NEXT: 000000000000005c R_RBR (idx: [[#NFA+9]]) .alias_foo +; XCOFF64-NEXT: 0000000000000064 R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] +; XCOFF64-NEXT: 000000000000006c R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] ; XCOFF64: RELOCATION RECORDS FOR [.data]: ; XCOFF64-NEXT: OFFSET TYPE VALUE -; XCOFF64-NEXT: 0000000000000000 R_POS (idx: 7) .foo[PR] -; XCOFF64-NEXT: 0000000000000008 R_POS (idx: 27) TOC[TC0] -; XCOFF64-NEXT: 0000000000000018 R_POS (idx: 11) .hidden_foo[PR] -; XCOFF64-NEXT: 0000000000000020 R_POS (idx: 27) TOC[TC0] -; XCOFF64-NEXT: 0000000000000030 R_POS (idx: 13) .bar[PR] -; XCOFF64-NEXT: 0000000000000038 R_POS (idx: 27) TOC[TC0] -; XCOFF64-NEXT: 0000000000000048 R_POS (idx: 15) .static_overalign_foo[PR] -; XCOFF64-NEXT: 0000000000000050 R_POS (idx: 27) TOC[TC0] +; XCOFF64-NEXT: 0000000000000000 R_POS (idx: [[#NFA+7]]) .foo[PR] +; XCOFF64-NEXT: 0000000000000008 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF64-NEXT: 0000000000000018 R_POS (idx: [[#NFA+11]]) .hidden_foo[PR] +; XCOFF64-NEXT: 0000000000000020 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF64-NEXT: 0000000000000030 R_POS (idx: [[#NFA+13]]) .bar[PR] +; XCOFF64-NEXT: 0000000000000038 R_POS (idx: [[#NFA+27]]) TOC[TC0] +; XCOFF64-NEXT: 0000000000000048 R_POS (idx: [[#NFA+15]]) .static_overalign_foo[PR] +; XCOFF64-NEXT: 0000000000000050 R_POS (idx: [[#NFA+27]]) TOC[TC0] ; DIS32: Disassembly of section .text: -; DIS32: 00000000 (idx: 9) .alias_foo: -; DIS32: 00000020 (idx: 11) .hidden_foo[PR]: -; DIS32: 00000040 (idx: 13) .bar[PR]: +; DIS32: 00000000 (idx: [[#NFA+9]]) .alias_foo: +; DIS32: 00000020 (idx: [[#NFA+11]]) .hidden_foo[PR]: +; DIS32: 00000040 (idx: [[#NFA+13]]) .bar[PR]: ; DIS32-NEXT: 40: 7c 08 02 a6 mflr 0 ; DIS32-NEXT: 44: 94 21 ff c0 stwu 1, -64(1) ; DIS32-NEXT: 48: 90 01 00 48 stw 0, 72(1) ; DIS32-NEXT: 4c: 4b ff ff b5 bl 0x0 <.foo> -; DIS32-NEXT: 0000004c: R_RBR (idx: 7) .foo[PR] +; DIS32-NEXT: 0000004c: R_RBR (idx: [[#NFA+7]]) .foo[PR] ; DIS32-NEXT: 50: 60 00 00 00 nop ; DIS32-NEXT: 54: 48 00 00 6d bl 0xc0 <.static_overalign_foo> -; DIS32-NEXT: 00000054: R_RBR (idx: 15) .static_overalign_foo[PR] +; DIS32-NEXT: 00000054: R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] ; DIS32-NEXT: 58: 60 00 00 00 nop ; DIS32-NEXT: 5c: 4b ff ff a5 bl 0x0 <.alias_foo> -; DIS32-NEXT: 0000005c: R_RBR (idx: 9) .alias_foo +; DIS32-NEXT: 0000005c: R_RBR (idx: [[#NFA+9]]) .alias_foo ; DIS32-NEXT: 60: 60 00 00 00 nop ; DIS32-NEXT: 64: 4b ff ff 9d bl 0x0 <.extern_foo> -; DIS32-NEXT: 00000064: R_RBR (idx: 1) .extern_foo[PR] +; DIS32-NEXT: 00000064: R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] ; DIS32-NEXT: 68: 60 00 00 00 nop ; DIS32-NEXT: 6c: 4b ff ff b5 bl 0x20 <.hidden_foo> -; DIS32-NEXT: 0000006c: R_RBR (idx: 11) .hidden_foo[PR] -; DIS32: 000000c0 (idx: 15) .static_overalign_foo[PR]: +; DIS32-NEXT: 0000006c: R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] +; DIS32: 000000c0 (idx: [[#NFA+15]]) .static_overalign_foo[PR]: ; DIS64: Disassembly of section .text: -; DIS64: 0000000000000000 (idx: 9) .alias_foo: -; DIS64: 0000000000000020 (idx: 11) .hidden_foo[PR]: -; DIS64: 0000000000000040 (idx: 13) .bar[PR]: +; DIS64: 0000000000000000 (idx: [[#NFA+9]]) .alias_foo: +; DIS64: 0000000000000020 (idx: [[#NFA+11]]) .hidden_foo[PR]: +; DIS64: 0000000000000040 (idx: [[#NFA+13]]) .bar[PR]: ; DIS64-NEXT: 40: 7c 08 02 a6 mflr 0 ; DIS64-NEXT: 44: f8 21 ff 91 stdu 1, -112(1) ; DIS64-NEXT: 48: f8 01 00 80 std 0, 128(1) ; DIS64-NEXT: 4c: 4b ff ff b5 bl 0x0 <.foo> -; DIS64-NEXT: 000000000000004c: R_RBR (idx: 7) .foo[PR] +; DIS64-NEXT: 000000000000004c: R_RBR (idx: [[#NFA+7]]) .foo[PR] ; DIS64-NEXT: 50: 60 00 00 00 nop ; DIS64-NEXT: 54: 48 00 00 6d bl 0xc0 <.static_overalign_foo> -; DIS64-NEXT: 0000000000000054: R_RBR (idx: 15) .static_overalign_foo[PR] +; DIS64-NEXT: 0000000000000054: R_RBR (idx: [[#NFA+15]]) .static_overalign_foo[PR] ; DIS64-NEXT: 58: 60 00 00 00 nop ; DIS64-NEXT: 5c: 4b ff ff a5 bl 0x0 <.alias_foo> -; DIS64-NEXT: 000000000000005c: R_RBR (idx: 9) .alias_foo +; DIS64-NEXT: 000000000000005c: R_RBR (idx: [[#NFA+9]]) .alias_foo ; DIS64-NEXT: 60: 60 00 00 00 nop ; DIS64-NEXT: 64: 4b ff ff 9d bl 0x0 <.extern_foo> -; DIS64-NEXT: 0000000000000064: R_RBR (idx: 1) .extern_foo[PR] +; DIS64-NEXT: 0000000000000064: R_RBR (idx: [[#NFA+1]]) .extern_foo[PR] ; DIS64-NEXT: 68: 60 00 00 00 nop ; DIS64-NEXT: 6c: 4b ff ff b5 bl 0x20 <.hidden_foo> -; DIS64-NEXT: 000000000000006c: R_RBR (idx: 11) .hidden_foo[PR] -; DIS64: 00000000000000c0 (idx: 15) .static_overalign_foo[PR]: +; DIS64-NEXT: 000000000000006c: R_RBR (idx: [[#NFA+11]]) .hidden_foo[PR] +; DIS64: 00000000000000c0 (idx: [[#NFA+15]]) .static_overalign_foo[PR]: diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll index 31fdea9ad13ddf2e20b88e0b7c56e040f2c21d4f..8240306686abc372d55c2088b477e161c437d1c7 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-lcomm.ll @@ -29,7 +29,7 @@ ; OBJ-NEXT: TimeStamp: ; OBJ32-NEXT: SymbolTableOffset: 0x64 ; OBJ64-NEXT: SymbolTableOffset: 0xA8 -; OBJ-NEXT: SymbolTableEntries: 9 +; OBJ-NEXT: SymbolTableEntries: 11 ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll index ca13edd08513f2297a0bd36105f830f2d2faa05f..91e0f5da6e1b849053e355a6af774f70b81c39c3 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc-large.ll @@ -147,7 +147,7 @@ entry: ; DIS64: Disassembly of section .text: ; DIS64-EMPTY: -; DIS64-NEXT: 0000000000000000 (idx: 3) .foo: +; DIS64-NEXT: 0000000000000000 (idx: {{[0-9]+}}) .foo: ; DIS64-NEXT: 0: 3c 62 00 00 addis 3, 2, 0 ; DIS64-NEXT: 0000000000000002: R_TOCU (idx: [[#INDX:]]) a[TE] ; DIS64-NEXT: 4: 3c 82 00 00 addis 4, 2, 0 diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll index 5ac6a7af0db268aed59c16677eb671e02c84f6ca..6599debbd41b4e80257446900dbd98c5de152f19 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-reloc.ll @@ -1,16 +1,16 @@ ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc-ibm-aix-xcoff -mattr=-altivec \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t.o < %s -; RUN: llvm-readobj --section-headers --file-header %t.o | FileCheck --check-prefixes=OBJ,OBJ32 %s -; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck --check-prefixes=RELOC,RELOC32 %s -; RUN: llvm-readobj --syms %t.o | FileCheck --check-prefixes=SYM,SYM32 %s +; RUN: llvm-readobj --section-headers --file-header %t.o | FileCheck -D#NFA=2 --check-prefixes=OBJ,OBJ32 %s +; RUN: llvm-readobj --relocs --expand-relocs %t.o | FileCheck -D#NFA=2 --check-prefixes=RELOC,RELOC32 %s +; RUN: llvm-readobj --syms %t.o | FileCheck -D#NFA=2 --check-prefixes=SYM,SYM32 %s ; RUN: llvm-objdump -D %t.o | FileCheck --check-prefix=DIS %s ; RUN: llvm-objdump -r %t.o | FileCheck --check-prefix=DIS_REL %s ; RUN: llc -verify-machineinstrs -mcpu=pwr4 -mtriple powerpc64-ibm-aix-xcoff -mattr=-altivec \ ; RUN: -xcoff-traceback-table=false -data-sections=false -filetype=obj -o %t64.o < %s -; RUN: llvm-readobj --section-headers --file-header %t64.o | FileCheck --check-prefixes=OBJ,OBJ64 %s -; RUN: llvm-readobj --relocs --expand-relocs %t64.o | FileCheck --check-prefixes=RELOC,RELOC64 %s -; RUN: llvm-readobj --syms %t64.o | FileCheck --check-prefixes=SYM,SYM64 %s +; RUN: llvm-readobj --section-headers --file-header %t64.o | FileCheck -D#NFA=2 --check-prefixes=OBJ,OBJ64 %s +; RUN: llvm-readobj --relocs --expand-relocs %t64.o | FileCheck -D#NFA=2 --check-prefixes=RELOC,RELOC64 %s +; RUN: llvm-readobj --syms %t64.o | FileCheck -D#NFA=2 --check-prefixes=SYM,SYM64 %s ; RUN: llvm-objdump -D %t64.o | FileCheck --check-prefix=DIS64 %s ; RUN: llvm-objdump -r %t64.o | FileCheck --check-prefix=DIS_REL64 %s @@ -38,7 +38,7 @@ declare i32 @bar(i32) ; OBJ-NEXT: TimeStamp: None (0x0) ; OBJ32-NEXT: SymbolTableOffset: 0x13C ; OBJ64-NEXT: SymbolTableOffset: 0x1B8 -; OBJ-NEXT: SymbolTableEntries: 27 +; OBJ-NEXT: SymbolTableEntries: [[#NFA+27]] ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } @@ -80,7 +80,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Section (index: 1) .text { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x10 -; RELOC-NEXT: Symbol: .bar (1) +; RELOC-NEXT: Symbol: .bar ([[#NFA+1]]) ; RELOC-NEXT: IsSigned: Yes ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 26 @@ -88,7 +88,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1A -; RELOC-NEXT: Symbol: globalA (23) +; RELOC-NEXT: Symbol: globalA ([[#NFA+23]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -96,7 +96,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: } ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x1E -; RELOC-NEXT: Symbol: globalB (25) +; RELOC-NEXT: Symbol: globalB ([[#NFA+25]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC-NEXT: Length: 16 @@ -106,7 +106,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Section (index: 2) .data { ; RELOC-NEXT: Relocation { ; RELOC-NEXT: Virtual Address: 0x70 -; RELOC-NEXT: Symbol: arr (15) +; RELOC-NEXT: Symbol: arr ([[#NFA+15]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -116,7 +116,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x74 ; RELOC64-NEXT: Virtual Address: 0x78 -; RELOC-NEXT: Symbol: .foo (7) +; RELOC-NEXT: Symbol: .foo ([[#NFA+7]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -126,7 +126,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x78 ; RELOC64-NEXT: Virtual Address: 0x80 -; RELOC-NEXT: Symbol: TOC (21) +; RELOC-NEXT: Symbol: TOC ([[#NFA+21]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -136,7 +136,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x80 ; RELOC64-NEXT: Virtual Address: 0x90 -; RELOC-NEXT: Symbol: globalA (11) +; RELOC-NEXT: Symbol: globalA ([[#NFA+11]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -146,7 +146,7 @@ declare i32 @bar(i32) ; RELOC-NEXT: Relocation { ; RELOC32-NEXT: Virtual Address: 0x84 ; RELOC64-NEXT: Virtual Address: 0x98 -; RELOC-NEXT: Symbol: globalB (13) +; RELOC-NEXT: Symbol: globalB ([[#NFA+13]]) ; RELOC-NEXT: IsSigned: No ; RELOC-NEXT: FixupBitValue: 0 ; RELOC32-NEXT: Length: 32 @@ -159,14 +159,26 @@ declare i32 @bar(i32) ; SYM: Symbols [ ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: 0 -; SYM-NEXT: Name: +; SYM-NEXT: Name: .file ; SYM-NEXT: Value (SymbolTableIndex): 0x0 ; SYM-NEXT: Section: N_DEBUG ; SYM-NEXT: Source Language ID: TB_CPLUSPLUS (0x9) ; SYM32-NEXT: CPU Version ID: TCPU_COM (0x3) ; SYM64-NEXT: CPU Version ID: TCPU_PPC64 (0x2) ; SYM-NEXT: StorageClass: C_FILE (0x67) -; SYM-NEXT: NumberOfAuxEntries: 0 +; SYM-NEXT: NumberOfAuxEntries: 2 +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 1 +; SYM-NEXT: Name: +; SYM-NEXT: Type: XFT_FN (0x0) +; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYM-NEXT: } +; SYM-NEXT: File Auxiliary Entry { +; SYM-NEXT: Index: 2 +; SYM-NEXT: Name: LLVM +; SYM-NEXT: Type: XFT_CV (0x2) +; SYM64-NEXT: Auxiliary Type: AUX_FILE (0xFC) +; SYM-NEXT: } ; SYM-NEXT: } ; SYM-NEXT: Symbol { ; SYM-NEXT: Index: [[#INDX:]] diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll index cafb91aafe2329710370b498695f90b719860f08..0fa47373964a01e9feb87a65c07709f196d921aa 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-rodata.ll @@ -82,7 +82,7 @@ ; OBJ-NEXT: TimeStamp: None (0x0) ; OBJ32-NEXT: SymbolTableOffset: 0x8C ; OBJ64-NEXT: SymbolTableOffset: 0xB0 -; OBJ-NEXT: SymbolTableEntries: 21 +; OBJ-NEXT: SymbolTableEntries: 23 ; OBJ-NEXT: OptionalHeaderSize: 0x0 ; OBJ-NEXT: Flags: 0x0 ; OBJ-NEXT: } diff --git a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll index 494078010fd05340b7a6ddaf0565bc554d057958..296bef6919de51203f9c98dec3d9ef320586a07c 100644 --- a/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll +++ b/llvm/test/CodeGen/PowerPC/aix-xcoff-symbol-rename.ll @@ -10,7 +10,7 @@ ; RUN: llc -verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr4 \ ; RUN: -mattr=-altivec -data-sections=false -xcoff-traceback-table=false -filetype=obj -o %t.o < %s ; RUN: llvm-objdump -D -r --symbol-description %t.o | \ -; RUN: FileCheck --check-prefix=OBJ %s +; RUN: FileCheck --check-prefix=OBJ -D#NFA=2 %s ; This is f`o @"f\60o" = global i32 10, align 4 @@ -105,12 +105,12 @@ declare i32 @"f\40o"(...) ; OBJ: Disassembly of section .text: ; OBJ-EMPTY: -; OBJ-NEXT: 00000000 (idx: 7) .f$o: +; OBJ-NEXT: 00000000 (idx: [[#NFA+7]]) .f$o: ; OBJ-NEXT: 0: 7c 08 02 a6 mflr 0 ; OBJ-NEXT: 4: 94 21 ff c0 stwu 1, -64(1) ; OBJ-NEXT: 8: 90 01 00 48 stw 0, 72(1) ; OBJ-NEXT: c: 4b ff ff f5 bl 0x0 -; OBJ-NEXT: 0000000c: R_RBR (idx: 1) .f@o[PR] +; OBJ-NEXT: 0000000c: R_RBR (idx: [[#NFA+1]]) .f@o[PR] ; OBJ-NEXT: 10: 60 00 00 00 nop ; OBJ-NEXT: 14: 38 21 00 40 addi 1, 1, 64 ; OBJ-NEXT: 18: 80 01 00 08 lwz 0, 8(1) @@ -120,13 +120,13 @@ declare i32 @"f\40o"(...) ; OBJ-NEXT: 28: 60 00 00 00 nop ; OBJ-NEXT: 2c: 60 00 00 00 nop ; OBJ-EMPTY: -; OBJ-NEXT: 00000030 (idx: 9) .f&o: +; OBJ-NEXT: 00000030 (idx: [[#NFA+9]]) .f&o: ; OBJ-NEXT: 30: 7c 08 02 a6 mflr 0 ; OBJ-NEXT: 34: 94 21 ff c0 stwu 1, -64(1) ; OBJ-NEXT: 38: 90 01 00 48 stw 0, 72(1) ; OBJ-NEXT: 3c: 4b ff ff c5 bl 0x0 ; OBJ-NEXT: 40: 80 82 00 00 lwz 4, 0(2) -; OBJ-NEXT: 00000042: R_TOC (idx: 25) f=o[TC] +; OBJ-NEXT: 00000042: R_TOC (idx: [[#NFA+25]]) f=o[TC] ; OBJ-NEXT: 44: 80 84 00 00 lwz 4, 0(4) ; OBJ-NEXT: 48: 7c 63 22 14 add 3, 3, 4 ; OBJ-NEXT: 4c: 38 21 00 40 addi 1, 1, 64 @@ -135,49 +135,49 @@ declare i32 @"f\40o"(...) ; OBJ-NEXT: 58: 4e 80 00 20 blr ; OBJ-NEXT: 5c: 60 00 00 00 nop ; OBJ-EMPTY: -; OBJ-NEXT: 00000060 (idx: 11) .f&_o: +; OBJ-NEXT: 00000060 (idx: [[#NFA+11]]) .f&_o: ; OBJ-NEXT: 60: 80 62 00 04 lwz 3, 4(2) -; OBJ-NEXT: 00000062: R_TOC (idx: 27) f@o[TC] +; OBJ-NEXT: 00000062: R_TOC (idx: [[#NFA+27]]) f@o[TC] ; OBJ-NEXT: 64: 4e 80 00 20 blr ; OBJ-EMPTY: ; OBJ-NEXT: Disassembly of section .data: ; OBJ-EMPTY: -; OBJ-NEXT: 00000068 (idx: 15) f`o: +; OBJ-NEXT: 00000068 (idx: [[#NFA+15]]) f`o: ; OBJ-NEXT: 68: 00 00 00 0a ; OBJ-EMPTY: -; OBJ-NEXT: 0000006c (idx: 17) f$o[DS]: +; OBJ-NEXT: 0000006c (idx: [[#NFA+17]]) f$o[DS]: ; OBJ-NEXT: 6c: 00 00 00 00 -; OBJ-NEXT: 0000006c: R_POS (idx: 7) .f$o +; OBJ-NEXT: 0000006c: R_POS (idx: [[#NFA+7]]) .f$o ; OBJ-NEXT: 70: 00 00 00 90 -; OBJ-NEXT: 00000070: R_POS (idx: 23) TOC[TC0] +; OBJ-NEXT: 00000070: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; OBJ-NEXT: 74: 00 00 00 00 ; OBJ-EMPTY: -; OBJ-NEXT: 00000078 (idx: 19) f&o[DS]: +; OBJ-NEXT: 00000078 (idx: [[#NFA+19]]) f&o[DS]: ; OBJ-NEXT: 78: 00 00 00 30 -; OBJ-NEXT: 00000078: R_POS (idx: 9) .f&o +; OBJ-NEXT: 00000078: R_POS (idx: [[#NFA+9]]) .f&o ; OBJ-NEXT: 7c: 00 00 00 90 -; OBJ-NEXT: 0000007c: R_POS (idx: 23) TOC[TC0] +; OBJ-NEXT: 0000007c: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; OBJ-NEXT: 80: 00 00 00 00 ; OBJ-EMPTY: -; OBJ-NEXT: 00000084 (idx: 21) f&_o[DS]: +; OBJ-NEXT: 00000084 (idx: [[#NFA+21]]) f&_o[DS]: ; OBJ-NEXT: 84: 00 00 00 60 -; OBJ-NEXT: 00000084: R_POS (idx: 11) .f&_o +; OBJ-NEXT: 00000084: R_POS (idx: [[#NFA+11]]) .f&_o ; OBJ-NEXT: 88: 00 00 00 90 -; OBJ-NEXT: 00000088: R_POS (idx: 23) TOC[TC0] +; OBJ-NEXT: 00000088: R_POS (idx: [[#NFA+23]]) TOC[TC0] ; OBJ-NEXT: 8c: 00 00 00 00 ; OBJ-EMPTY: -; OBJ-NEXT: 00000090 (idx: 25) f=o[TC]: +; OBJ-NEXT: 00000090 (idx: [[#NFA+25]]) f=o[TC]: ; OBJ-NEXT: 90: 00 00 00 9c -; OBJ-NEXT: 00000090: R_POS (idx: 31) f=o[BS] +; OBJ-NEXT: 00000090: R_POS (idx: [[#NFA+31]]) f=o[BS] ; OBJ-EMPTY: -; OBJ-NEXT: 00000094 (idx: 27) f@o[TC]: +; OBJ-NEXT: 00000094 (idx: [[#NFA+27]]) f@o[TC]: ; OBJ-NEXT: 94: 00 00 00 00 -; OBJ-NEXT: 00000094: R_POS (idx: 3) f@o[DS] +; OBJ-NEXT: 00000094: R_POS (idx: [[#NFA+3]]) f@o[DS] ; OBJ-EMPTY: ; OBJ-NEXT: Disassembly of section .bss: ; OBJ-EMPTY: -; OBJ-NEXT: 00000098 (idx: 29) f"o"[RW]: +; OBJ-NEXT: 00000098 (idx: [[#NFA+29]]) f"o"[RW]: ; OBJ-NEXT: ... ; OBJ-EMPTY: -; OBJ-NEXT: 0000009c (idx: 31) f=o[BS]: +; OBJ-NEXT: 0000009c (idx: [[#NFA+31]]) f=o[BS]: ; OBJ-NEXT: ... diff --git a/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll b/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll index 2d2c09cc17abcc42752a7780d92d0a8cb10fe3b0..5fbd3b17d4f8aa6efdf66a75b7b5febb067cf4d5 100644 --- a/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll +++ b/llvm/test/CodeGen/PowerPC/basic-toc-data-def.ll @@ -2,9 +2,9 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms | FileCheck %s -D#INDX=5 --check-prefix=OBJ32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms | FileCheck %s -D#INDX=5 --check-prefix=OBJ64 @i = global i32 55, align 4 #0 @@ -16,8 +16,7 @@ attributes #0 = { "toc-data" } ; CHECK-NEXT: .align 2 ; CHECK-NEXT: .vbyte 4, 55 -; OBJ32: Symbol { -; OBJ32: Index: 3 +; OBJ32: Index: [[#INDX]] ; OBJ32-NEXT: Name: TOC ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: .data @@ -25,7 +24,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 4 +; OBJ32-NEXT: Index: [[#INDX+1]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -37,7 +36,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32-NEXT: Symbol { -; OBJ32-NEXT: Index: 5 +; OBJ32-NEXT: Index: [[#INDX+2]] ; OBJ32-NEXT: Name: i ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: .data @@ -45,7 +44,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 6 +; OBJ32-NEXT: Index: [[#INDX+3]] ; OBJ32-NEXT: SectionLen: 4 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -57,8 +56,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } -; OBJ64: Symbol { -; OBJ64: Index: 3 +; OBJ64: Index: [[#INDX]] ; OBJ64-NEXT: Name: TOC ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: .data @@ -66,7 +64,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 4 +; OBJ64-NEXT: Index: [[#INDX+1]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -77,7 +75,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64-NEXT: Symbol { -; OBJ64-NEXT: Index: 5 +; OBJ64-NEXT: Index: [[#INDX+2]] ; OBJ64-NEXT: Name: i ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: .data @@ -85,7 +83,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 6 +; OBJ64-NEXT: Index: [[#INDX+3]] ; OBJ64-NEXT: SectionLen: 4 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll b/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll index 04a2bfbf2dd44cf3d79e53f39e3ccd6de756a9bf..0a649f683feaa5d166ae1e22153cb433d3345674 100644 --- a/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll +++ b/llvm/test/CodeGen/PowerPC/basic-toc-data-extern.ll @@ -2,9 +2,9 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s | FileCheck %s ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ64 @i = external global i32, align 4 #0 @@ -22,16 +22,16 @@ attributes #0 = { "toc-data" } ; OBJ32: Relocations [ ; OBJ32-NEXT: Section (index: 1) .text { -; OBJ32-NEXT: 0x2 R_TOC i(1) 0xF +; OBJ32-NEXT: 0x2 R_TOC i([[#NFA+1]]) 0xF ; OBJ32-NEXT: } ; OBJ32-NEXT: Section (index: 2) .data { -; OBJ32-NEXT: 0x20 R_POS .get(5) 0x1F -; OBJ32-NEXT: 0x24 R_POS TOC(9) 0x1F +; OBJ32-NEXT: 0x20 R_POS .get([[#NFA+5]]) 0x1F +; OBJ32-NEXT: 0x24 R_POS TOC([[#NFA+9]]) 0x1F ; OBJ32-NEXT: } ; OBJ32-NEXT: ] ; OBJ32: Symbol { -; OBJ32: Index: 1 +; OBJ32: Index: [[#NFA+1]] ; OBJ32-NEXT: Name: i ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: N_UNDEF @@ -39,7 +39,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Index: [[#NFA+2]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -51,7 +51,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32: Symbol { -; OBJ32: Index: 9 +; OBJ32: Index: [[#NFA+9]] ; OBJ32-NEXT: Name: TOC ; OBJ32-NEXT: Value (RelocatableAddress): 0x2C ; OBJ32-NEXT: Section: .data @@ -59,7 +59,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 10 +; OBJ32-NEXT: Index: [[#NFA+10]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -73,16 +73,16 @@ attributes #0 = { "toc-data" } ; OBJ64: Relocations [ ; OBJ64-NEXT: Section (index: 1) .text { -; OBJ64-NEXT: 0x2 R_TOC i(1) 0xF +; OBJ64-NEXT: 0x2 R_TOC i([[#NFA+1]]) 0xF ; OBJ64-NEXT: } ; OBJ64-NEXT: Section (index: 2) .data { -; OBJ64-NEXT: 0x20 R_POS .get(5) 0x3F -; OBJ64-NEXT: 0x28 R_POS TOC(9) 0x3F +; OBJ64-NEXT: 0x20 R_POS .get([[#NFA+5]]) 0x3F +; OBJ64-NEXT: 0x28 R_POS TOC([[#NFA+9]]) 0x3F ; OBJ64-NEXT: } ; OBJ64-NEXT: ] ; OBJ64: Symbol { -; OBJ64: Index: 1 +; OBJ64: Index: [[#NFA+1]] ; OBJ64-NEXT: Name: i ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: N_UNDEF @@ -90,7 +90,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Index: [[#NFA+2]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -101,7 +101,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64: Symbol { -; OBJ64: Index: 9 +; OBJ64: Index: [[#NFA+9]] ; OBJ64-NEXT: Name: TOC ; OBJ64-NEXT: Value (RelocatableAddress): 0x38 ; OBJ64-NEXT: Section: .data @@ -109,7 +109,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 10 +; OBJ64-NEXT: Index: [[#NFA+10]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll index 17c2b438a94aa9c6ed82f8e8a00ddbc30ec4e4c1..1e48b1242f852812c5d1c39b8a15c8332d6670f6 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-td.ll @@ -9,7 +9,7 @@ ; Check that we do not crash in object mode ; OBJ64: Exception section { -; OBJ64-NEXT: Symbol: .test__tdw_annotation (6) +; OBJ64-NEXT: Symbol: .test__tdw_annotation !1 = !{!"ppc-trap-reason", !"1", !"2"} declare void @llvm.ppc.trapd(i64 %a) diff --git a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll index 24a0723bf39cf486545c6ccd081013001fdcb9b4..d18d075590d255c2ce9ca72609ff19b1e5c19b29 100644 --- a/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll +++ b/llvm/test/CodeGen/PowerPC/builtins-ppc-xlcompat-trap-annotations-tw.ll @@ -13,7 +13,7 @@ ; Check that we do not crash in object mode ; OBJ: Exception section { -; OBJ-NEXT: Symbol: .test__trap_annotation (3) +; OBJ-NEXT: Symbol: .test__trap_annotation !1 = !{!"ppc-trap-reason", !"1", !"2"} declare void @llvm.ppc.trap(i32 %a) diff --git a/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll b/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll index 480b44caaded7a591d05865fc5b822d565bf17b9..02b0a9ba4397c6834fbddb7e028fd3cf1a9a09fa 100644 --- a/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll +++ b/llvm/test/CodeGen/PowerPC/pgo-ref-directive.ll @@ -121,7 +121,7 @@ entry: ; WITHVNDS-NEXT: .ref __llvm_prf_vnds[RW] ; WITHVNDS-OBJ: SYMBOL TABLE: -; WITHVNDS-OBJ-NEXT: 00000000 df *DEBUG* 00000000 +; WITHVNDS-OBJ-NEXT: 00000000 df *DEBUG* 00000000 .file ; WITHVNDS-OBJ-NEXT: 00000000 l .text 00000008 ; WITHVNDS-OBJ-NEXT: 00000000 g F .text (csect: ) 00000000 .main ; WITHVNDS-OBJ-NEXT: 00000008 l .text 00000006 __llvm_prf_names diff --git a/llvm/test/CodeGen/PowerPC/pr59074.ll b/llvm/test/CodeGen/PowerPC/pr59074.ll new file mode 100644 index 0000000000000000000000000000000000000000..3e328c6ad9f0ba804489baf2429ab6fbb86cfab2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/pr59074.ll @@ -0,0 +1,132 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE64 +; RUN: llc -mtriple=powerpcle-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s --check-prefix=LE32 +; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE64 +; RUN: llc -mtriple=powerpc-ibm-aix -mcpu=pwr7 < %s | FileCheck %s --check-prefix=BE32 + +; To verify this doesn't crash due to array out of bound. +define void @pr59074(ptr %0) { +; LE64-LABEL: pr59074: +; LE64: # %bb.0: # %entry +; LE64-NEXT: lwz 6, 0(3) +; LE64-NEXT: li 7, 12 +; LE64-NEXT: ld 4, 16(3) +; LE64-NEXT: ld 5, 24(3) +; LE64-NEXT: addi 6, 6, -12 +; LE64-NEXT: std 4, 16(3) +; LE64-NEXT: std 5, 24(3) +; LE64-NEXT: srd 6, 7, 6 +; LE64-NEXT: li 7, 0 +; LE64-NEXT: std 7, 8(3) +; LE64-NEXT: std 6, 0(3) +; LE64-NEXT: blr +; +; LE32-LABEL: pr59074: +; LE32: # %bb.0: # %entry +; LE32-NEXT: stwu 1, -80(1) +; LE32-NEXT: .cfi_def_cfa_offset 80 +; LE32-NEXT: lwz 4, 0(3) +; LE32-NEXT: xxlxor 0, 0, 0 +; LE32-NEXT: li 5, 4 +; LE32-NEXT: addi 6, 1, 16 +; LE32-NEXT: li 7, 0 +; LE32-NEXT: li 8, 12 +; LE32-NEXT: xxswapd 0, 0 +; LE32-NEXT: addi 4, 4, -12 +; LE32-NEXT: rlwinm 9, 4, 29, 28, 31 +; LE32-NEXT: stxvd2x 0, 6, 5 +; LE32-NEXT: stw 7, 44(1) +; LE32-NEXT: stw 7, 40(1) +; LE32-NEXT: stw 7, 36(1) +; LE32-NEXT: stw 8, 16(1) +; LE32-NEXT: lwzux 5, 9, 6 +; LE32-NEXT: li 6, 7 +; LE32-NEXT: lwz 7, 8(9) +; LE32-NEXT: nand 6, 4, 6 +; LE32-NEXT: lwz 8, 4(9) +; LE32-NEXT: clrlwi 4, 4, 29 +; LE32-NEXT: lwz 9, 12(9) +; LE32-NEXT: clrlwi 6, 6, 27 +; LE32-NEXT: subfic 11, 4, 32 +; LE32-NEXT: srw 5, 5, 4 +; LE32-NEXT: slwi 10, 7, 1 +; LE32-NEXT: srw 7, 7, 4 +; LE32-NEXT: slw 6, 10, 6 +; LE32-NEXT: srw 10, 8, 4 +; LE32-NEXT: slw 8, 8, 11 +; LE32-NEXT: slw 11, 9, 11 +; LE32-NEXT: srw 4, 9, 4 +; LE32-NEXT: or 5, 8, 5 +; LE32-NEXT: or 7, 11, 7 +; LE32-NEXT: or 6, 10, 6 +; LE32-NEXT: stw 4, 12(3) +; LE32-NEXT: stw 7, 8(3) +; LE32-NEXT: stw 5, 0(3) +; LE32-NEXT: stw 6, 4(3) +; LE32-NEXT: addi 1, 1, 80 +; LE32-NEXT: blr +; +; BE64-LABEL: pr59074: +; BE64: # %bb.0: # %entry +; BE64-NEXT: lwz 6, 12(3) +; BE64-NEXT: li 7, 12 +; BE64-NEXT: ld 4, 24(3) +; BE64-NEXT: ld 5, 16(3) +; BE64-NEXT: addi 6, 6, -12 +; BE64-NEXT: std 4, 24(3) +; BE64-NEXT: std 5, 16(3) +; BE64-NEXT: srd 6, 7, 6 +; BE64-NEXT: li 7, 0 +; BE64-NEXT: std 7, 0(3) +; BE64-NEXT: std 6, 8(3) +; BE64-NEXT: blr +; +; BE32-LABEL: pr59074: +; BE32: # %bb.0: # %entry +; BE32-NEXT: lwz 4, 12(3) +; BE32-NEXT: xxlxor 0, 0, 0 +; BE32-NEXT: addi 5, 1, -64 +; BE32-NEXT: li 6, 12 +; BE32-NEXT: li 7, 0 +; BE32-NEXT: addi 8, 1, -48 +; BE32-NEXT: li 10, 7 +; BE32-NEXT: stxvw4x 0, 0, 5 +; BE32-NEXT: addi 4, 4, -12 +; BE32-NEXT: stw 6, -36(1) +; BE32-NEXT: stw 7, -40(1) +; BE32-NEXT: stw 7, -44(1) +; BE32-NEXT: rlwinm 9, 4, 29, 28, 31 +; BE32-NEXT: stw 7, -48(1) +; BE32-NEXT: sub 5, 8, 9 +; BE32-NEXT: nand 6, 4, 10 +; BE32-NEXT: clrlwi 4, 4, 29 +; BE32-NEXT: clrlwi 6, 6, 27 +; BE32-NEXT: lwz 7, 4(5) +; BE32-NEXT: lwz 8, 8(5) +; BE32-NEXT: lwz 9, 0(5) +; BE32-NEXT: lwz 5, 12(5) +; BE32-NEXT: slwi 10, 7, 1 +; BE32-NEXT: srw 11, 8, 4 +; BE32-NEXT: srw 7, 7, 4 +; BE32-NEXT: srw 5, 5, 4 +; BE32-NEXT: slw 6, 10, 6 +; BE32-NEXT: subfic 10, 4, 32 +; BE32-NEXT: srw 4, 9, 4 +; BE32-NEXT: slw 8, 8, 10 +; BE32-NEXT: slw 10, 9, 10 +; BE32-NEXT: or 6, 11, 6 +; BE32-NEXT: or 7, 10, 7 +; BE32-NEXT: or 5, 8, 5 +; BE32-NEXT: stw 4, 0(3) +; BE32-NEXT: stw 6, 8(3) +; BE32-NEXT: stw 5, 12(3) +; BE32-NEXT: stw 7, 4(3) +; BE32-NEXT: blr +entry: + %v1 = load <2 x i128>, <2 x i128>* %0 + %v2 = insertelement <2 x i128> %v1, i128 12, i32 0 + %v3 = sub <2 x i128> %v1, %v2 + %v4 = lshr <2 x i128> %v2, %v3 + store <2 x i128> %v4, <2 x i128>* %0 + ret void +} diff --git a/llvm/test/CodeGen/PowerPC/toc-data-const.ll b/llvm/test/CodeGen/PowerPC/toc-data-const.ll index 740032e26a432e956ef11980c9b7aa38b013b38a..6972079d826e02a19cf127afa849452125707c24 100644 --- a/llvm/test/CodeGen/PowerPC/toc-data-const.ll +++ b/llvm/test/CodeGen/PowerPC/toc-data-const.ll @@ -2,11 +2,11 @@ ; RUN: llc -mtriple powerpc64-ibm-aix-xcoff < %s | FileCheck %s --check-prefix CHECK ; RUN: llc -filetype=obj -mtriple powerpc-ibm-aix-xcoff -verify-machineinstrs < %s -o %t32.o -; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s --check-prefix=OBJ32 +; RUN: llvm-readobj %t32.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ32 ; RUN: llvm-objdump %t32.o -dr | FileCheck %s --check-prefix=DIS32 ; RUN: llc -filetype=obj -mtriple powerpc64-ibm-aix-xcoff -verify-machineinstrs < %s -o %t64.o -; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s --check-prefix=OBJ64 +; RUN: llvm-readobj %t64.o --syms --relocs | FileCheck %s -D#NFA=2 --check-prefix=OBJ64 ; RUN: llvm-objdump %t64.o -dr | FileCheck %s --check-prefix=DIS64 @i1 = external constant i32 #0 @@ -35,20 +35,20 @@ attributes #0 = { "toc-data" } ; OBJ32: Relocations [ ; OBJ32-NEXT: Section (index: 1) .text { -; OBJ32-NEXT: 0x2 R_TOC i1(1) 0xF -; OBJ32-NEXT: 0x26 R_TOC i2(15) 0xF +; OBJ32-NEXT: 0x2 R_TOC i1([[#NFA+1]]) 0xF +; OBJ32-NEXT: 0x26 R_TOC i2([[#NFA+15]]) 0xF ; OBJ32-NEXT: } ; OBJ32-NEXT: Section (index: 2) .data { -; OBJ32-NEXT: 0x44 R_POS .read(5) 0x1F -; OBJ32-NEXT: 0x48 R_POS TOC(13) 0x1F -; OBJ32-NEXT: 0x50 R_POS .retptr(7) 0x1F -; OBJ32-NEXT: 0x54 R_POS TOC(13) 0x1F -; OBJ32-NEXT: 0x5C R_POS i1(1) 0x1F +; OBJ32-NEXT: 0x44 R_POS .read([[#NFA+5]]) 0x1F +; OBJ32-NEXT: 0x48 R_POS TOC([[#NFA+13]]) 0x1F +; OBJ32-NEXT: 0x50 R_POS .retptr([[#NFA+7]]) 0x1F +; OBJ32-NEXT: 0x54 R_POS TOC([[#NFA+13]]) 0x1F +; OBJ32-NEXT: 0x5C R_POS i1([[#NFA+1]]) 0x1F ; OBJ32-NEXT: } ; OBJ32-NEXT: ] ; OBJ32: Symbol { -; OBJ32: Index: 1 +; OBJ32: Index: [[#NFA+1]] ; OBJ32-NEXT: Name: i1 ; OBJ32-NEXT: Value (RelocatableAddress): 0x0 ; OBJ32-NEXT: Section: N_UNDEF @@ -56,7 +56,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 2 +; OBJ32-NEXT: Index: [[#NFA+2]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -68,7 +68,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32: Symbol { -; OBJ32: Index: 13 +; OBJ32: Index: [[#NFA+13]] ; OBJ32-NEXT: Name: TOC ; OBJ32-NEXT: Value (RelocatableAddress): 0x5C ; OBJ32-NEXT: Section: .data @@ -76,7 +76,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 14 +; OBJ32-NEXT: Index: [[#NFA+14]] ; OBJ32-NEXT: SectionLen: 0 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -88,7 +88,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: } ; OBJ32-NEXT: } ; OBJ32: Symbol { -; OBJ32: Index: 15 +; OBJ32: Index: [[#NFA+15]] ; OBJ32-NEXT: Name: i2 ; OBJ32-NEXT: Value (RelocatableAddress): 0x5C ; OBJ32-NEXT: Section: .data @@ -96,7 +96,7 @@ attributes #0 = { "toc-data" } ; OBJ32-NEXT: StorageClass: C_EXT (0x2) ; OBJ32-NEXT: NumberOfAuxEntries: 1 ; OBJ32-NEXT: CSECT Auxiliary Entry { -; OBJ32-NEXT: Index: 16 +; OBJ32-NEXT: Index: [[#NFA+16]] ; OBJ32-NEXT: SectionLen: 4 ; OBJ32-NEXT: ParameterHashIndex: 0x0 ; OBJ32-NEXT: TypeChkSectNum: 0x0 @@ -110,20 +110,20 @@ attributes #0 = { "toc-data" } ; OBJ64: Relocations [ ; OBJ64-NEXT: Section (index: 1) .text { -; OBJ64-NEXT: 0x2 R_TOC i1(1) 0xF -; OBJ64-NEXT: 0x26 R_TOC i2(15) 0xF +; OBJ64-NEXT: 0x2 R_TOC i1([[#NFA+1]]) 0xF +; OBJ64-NEXT: 0x26 R_TOC i2([[#NFA+15]]) 0xF ; OBJ64-NEXT: } ; OBJ64-NEXT: Section (index: 2) .data { -; OBJ64-NEXT: 0x48 R_POS .read(5) 0x3F -; OBJ64-NEXT: 0x50 R_POS TOC(13) 0x3F -; OBJ64-NEXT: 0x60 R_POS .retptr(7) 0x3F -; OBJ64-NEXT: 0x68 R_POS TOC(13) 0x3F -; OBJ64-NEXT: 0x78 R_POS i1(1) 0x3F +; OBJ64-NEXT: 0x48 R_POS .read([[#NFA+5]]) 0x3F +; OBJ64-NEXT: 0x50 R_POS TOC([[#NFA+13]]) 0x3F +; OBJ64-NEXT: 0x60 R_POS .retptr([[#NFA+7]]) 0x3F +; OBJ64-NEXT: 0x68 R_POS TOC([[#NFA+13]]) 0x3F +; OBJ64-NEXT: 0x78 R_POS i1([[#NFA+1]]) 0x3F ; OBJ64-NEXT: } ; OBJ64-NEXT: ] ; OBJ64: Symbol { -; OBJ64: Index: 1 +; OBJ64: Index: [[#NFA+1]] ; OBJ64-NEXT: Name: i1 ; OBJ64-NEXT: Value (RelocatableAddress): 0x0 ; OBJ64-NEXT: Section: N_UNDEF @@ -131,7 +131,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 2 +; OBJ64-NEXT: Index: [[#NFA+2]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -142,7 +142,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64: Symbol { -; OBJ64: Index: 13 +; OBJ64: Index: [[#NFA+13]] ; OBJ64-NEXT: Name: TOC ; OBJ64-NEXT: Value (RelocatableAddress): 0x78 ; OBJ64-NEXT: Section: .data @@ -150,7 +150,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_HIDEXT (0x6B) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 14 +; OBJ64-NEXT: Index: [[#NFA+14]] ; OBJ64-NEXT: SectionLen: 0 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 @@ -161,7 +161,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: } ; OBJ64-NEXT: } ; OBJ64: Symbol { -; OBJ64: Index: 15 +; OBJ64: Index: [[#NFA+15]] ; OBJ64-NEXT: Name: i2 ; OBJ64-NEXT: Value (RelocatableAddress): 0x78 ; OBJ64-NEXT: Section: .data @@ -169,7 +169,7 @@ attributes #0 = { "toc-data" } ; OBJ64-NEXT: StorageClass: C_EXT (0x2) ; OBJ64-NEXT: NumberOfAuxEntries: 1 ; OBJ64-NEXT: CSECT Auxiliary Entry { -; OBJ64-NEXT: Index: 16 +; OBJ64-NEXT: Index: [[#NFA+16]] ; OBJ64-NEXT: SectionLen: 8 ; OBJ64-NEXT: ParameterHashIndex: 0x0 ; OBJ64-NEXT: TypeChkSectNum: 0x0 diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 088cc0b90a05ac50e643bd2bf7624ea0ce93d57f..13635a94d6411a7b04e1628baef04a8e396dab56 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -121,6 +121,7 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s +; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV32SSQOSID %s ; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s @@ -249,6 +250,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s +; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s ; CHECK: .attribute 4, 16 @@ -372,6 +374,7 @@ ; RV32SMMPM: .attribute 5, "rv32i2p1_smmpm0p8" ; RV32SSPM: .attribute 5, "rv32i2p1_sspm0p8" ; RV32SUPM: .attribute 5, "rv32i2p1_supm0p8" +; RV32SSQOSID: .attribute 5, "rv32i2p1_ssqosid1p0" ; RV64M: .attribute 5, "rv64i2p1_m2p0" ; RV64ZMMUL: .attribute 5, "rv64i2p1_zmmul1p0" @@ -499,6 +502,7 @@ ; RV64SMMPM: .attribute 5, "rv64i2p1_smmpm0p8" ; RV64SSPM: .attribute 5, "rv64i2p1_sspm0p8" ; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8" +; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" define i32 @addi(i32 %a) { %1 = add i32 %a, 1 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll index 23629ace4cf48cdb305364de14dd86a2e6f2ded9..acad71bb59590b953af55faf45a7d3d90ecee9a0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -719,3 +719,100 @@ define <8 x i32> @shuffle_v8i32_2(<8 x i32> %x, <8 x i32> %y) { %s = shufflevector <8 x i32> %x, <8 x i32> %y, <8 x i32> ret <8 x i32> %s } + +; FIXME: This could be expressed as a vrgather.vv +define <8 x i8> @shuffle_v64i8_v8i8(<64 x i8> %wide.vec) { +; RV32-LABEL: shuffle_v64i8_v8i8: +; RV32: # %bb.0: +; RV32-NEXT: addi sp, sp, -128 +; RV32-NEXT: .cfi_def_cfa_offset 128 +; RV32-NEXT: sw ra, 124(sp) # 4-byte Folded Spill +; RV32-NEXT: sw s0, 120(sp) # 4-byte Folded Spill +; RV32-NEXT: .cfi_offset ra, -4 +; RV32-NEXT: .cfi_offset s0, -8 +; RV32-NEXT: addi s0, sp, 128 +; RV32-NEXT: .cfi_def_cfa s0, 0 +; RV32-NEXT: andi sp, sp, -64 +; RV32-NEXT: li a0, 64 +; RV32-NEXT: mv a1, sp +; RV32-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; RV32-NEXT: vse8.v v8, (a1) +; RV32-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; RV32-NEXT: vslidedown.vi v10, v8, 8 +; RV32-NEXT: vmv.x.s a0, v10 +; RV32-NEXT: vmv.x.s a1, v8 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vmv.v.x v10, a1 +; RV32-NEXT: vslide1down.vx v10, v10, a0 +; RV32-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV32-NEXT: vslidedown.vi v12, v8, 16 +; RV32-NEXT: vmv.x.s a0, v12 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vslide1down.vx v10, v10, a0 +; RV32-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV32-NEXT: vslidedown.vi v8, v8, 24 +; RV32-NEXT: vmv.x.s a0, v8 +; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV32-NEXT: vslide1down.vx v8, v10, a0 +; RV32-NEXT: lbu a0, 32(sp) +; RV32-NEXT: lbu a1, 40(sp) +; RV32-NEXT: lbu a2, 48(sp) +; RV32-NEXT: lbu a3, 56(sp) +; RV32-NEXT: vslide1down.vx v8, v8, a0 +; RV32-NEXT: vslide1down.vx v8, v8, a1 +; RV32-NEXT: vslide1down.vx v8, v8, a2 +; RV32-NEXT: vslide1down.vx v8, v8, a3 +; RV32-NEXT: addi sp, s0, -128 +; RV32-NEXT: lw ra, 124(sp) # 4-byte Folded Reload +; RV32-NEXT: lw s0, 120(sp) # 4-byte Folded Reload +; RV32-NEXT: addi sp, sp, 128 +; RV32-NEXT: ret +; +; RV64-LABEL: shuffle_v64i8_v8i8: +; RV64: # %bb.0: +; RV64-NEXT: addi sp, sp, -128 +; RV64-NEXT: .cfi_def_cfa_offset 128 +; RV64-NEXT: sd ra, 120(sp) # 8-byte Folded Spill +; RV64-NEXT: sd s0, 112(sp) # 8-byte Folded Spill +; RV64-NEXT: .cfi_offset ra, -8 +; RV64-NEXT: .cfi_offset s0, -16 +; RV64-NEXT: addi s0, sp, 128 +; RV64-NEXT: .cfi_def_cfa s0, 0 +; RV64-NEXT: andi sp, sp, -64 +; RV64-NEXT: li a0, 64 +; RV64-NEXT: mv a1, sp +; RV64-NEXT: vsetvli zero, a0, e8, m4, ta, ma +; RV64-NEXT: vse8.v v8, (a1) +; RV64-NEXT: vsetivli zero, 1, e8, m1, ta, ma +; RV64-NEXT: vslidedown.vi v10, v8, 8 +; RV64-NEXT: vmv.x.s a0, v10 +; RV64-NEXT: vmv.x.s a1, v8 +; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64-NEXT: vmv.v.x v10, a1 +; RV64-NEXT: vslide1down.vx v10, v10, a0 +; RV64-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV64-NEXT: vslidedown.vi v12, v8, 16 +; RV64-NEXT: vmv.x.s a0, v12 +; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64-NEXT: vslide1down.vx v10, v10, a0 +; RV64-NEXT: vsetivli zero, 1, e8, m2, ta, ma +; RV64-NEXT: vslidedown.vi v8, v8, 24 +; RV64-NEXT: vmv.x.s a0, v8 +; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma +; RV64-NEXT: vslide1down.vx v8, v10, a0 +; RV64-NEXT: lbu a0, 32(sp) +; RV64-NEXT: lbu a1, 40(sp) +; RV64-NEXT: lbu a2, 48(sp) +; RV64-NEXT: lbu a3, 56(sp) +; RV64-NEXT: vslide1down.vx v8, v8, a0 +; RV64-NEXT: vslide1down.vx v8, v8, a1 +; RV64-NEXT: vslide1down.vx v8, v8, a2 +; RV64-NEXT: vslide1down.vx v8, v8, a3 +; RV64-NEXT: addi sp, s0, -128 +; RV64-NEXT: ld ra, 120(sp) # 8-byte Folded Reload +; RV64-NEXT: ld s0, 112(sp) # 8-byte Folded Reload +; RV64-NEXT: addi sp, sp, 128 +; RV64-NEXT: ret + %s = shufflevector <64 x i8> %wide.vec, <64 x i8> poison, <8 x i32> + ret <8 x i8> %s +} diff --git a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll index 6ce307146be19d64e901cd6d6fa75142937a8743..2d65c9d178b7890a46f6380576dbf247d89998c9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/stepvector.ll +++ b/llvm/test/CodeGen/RISCV/rvv/stepvector.ll @@ -733,3 +733,45 @@ entry: %3 = shl %2, %1 ret %3 } + +; maximum step is 4 * 2 = 8, so maximum step value is 7, so hi 61 bits are known +; zero +define @hi_bits_known_zero() vscale_range(2, 4) { +; CHECK-LABEL: hi_bits_known_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: ret + %step = call @llvm.experimental.stepvector.nxv2i64() + %and = and %step, shufflevector( insertelement( poison, i64 u0xfffffffffffffff8, i32 0), poison, zeroinitializer) + ret %and +} + +; the maximum step here overflows so don't set the known hi bits +define @hi_bits_known_zero_overflow() vscale_range(2, 4) { +; CHECK-LABEL: hi_bits_known_zero_overflow: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vid.v v8 +; CHECK-NEXT: li a0, -1 +; CHECK-NEXT: vmul.vx v8, v8, a0 +; CHECK-NEXT: vand.vi v8, v8, -8 +; CHECK-NEXT: ret + %step = call @llvm.experimental.stepvector.nxv2i64() + %step.mul = mul %step, shufflevector( insertelement( poison, i64 u0xffffffffffffffff, i32 0), poison, zeroinitializer) + %and = and %step.mul, shufflevector( insertelement( poison, i64 u0xfffffffffffffff8, i32 0), poison, zeroinitializer) + ret %and +} + +; step values are multiple of 8, so lo 3 bits are known zero +define @lo_bits_known_zero() { +; CHECK-LABEL: lo_bits_known_zero: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma +; CHECK-NEXT: vmv.v.i v8, 0 +; CHECK-NEXT: ret + %step = call @llvm.experimental.stepvector.nxv2i64() + %step.mul = mul %step, shufflevector( insertelement( poison, i64 8, i32 0), poison, zeroinitializer) + %and = and %step.mul, shufflevector( insertelement( poison, i64 7, i32 0), poison, zeroinitializer) + ret %and +} diff --git a/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir b/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir new file mode 100644 index 0000000000000000000000000000000000000000..93931ff950a8c0d10361d0ad7d736a7ec4ccc2b8 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir @@ -0,0 +1,186 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP32 %s +# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL32 %s +# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP64 %s +# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL64 %s +# RUN: llc -mtriple=riscv32 -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP32 %s +# RUN: llc -mtriple=riscv64 -x mir -start-before=prologepilog -stop-after=riscv-push-pop-opt -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP64 %s +--- +name: popret_rvlist5 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-ZCMP32-LABEL: name: popret_rvlist5 + ; CHECK-ZCMP32: liveins: $x1, $x8 + ; CHECK-ZCMP32-NEXT: {{ $}} + ; CHECK-ZCMP32-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -4 + ; CHECK-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: CM_POPRET 5, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL32-LABEL: name: popret_rvlist5 + ; CHECK-LIBCALL32: liveins: $x1, $x8 + ; CHECK-LIBCALL32-NEXT: {{ $}} + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2 + ; + ; CHECK-ZCMP64-LABEL: name: popret_rvlist5 + ; CHECK-ZCMP64: liveins: $x1, $x8 + ; CHECK-ZCMP64-NEXT: {{ $}} + ; CHECK-ZCMP64-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: CM_POPRET 5, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL64-LABEL: name: popret_rvlist5 + ; CHECK-LIBCALL64: liveins: $x1, $x8 + ; CHECK-LIBCALL64-NEXT: {{ $}} + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2 + ; + ; CHECK-NO-ZCMP32-LABEL: name: popret_rvlist5 + ; CHECK-NO-ZCMP32: liveins: $x1, $x8 + ; CHECK-NO-ZCMP32-NEXT: {{ $}} + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP32-NEXT: SW killed $x1, $x2, 12 :: (store (s32) into %stack.0) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x8, $x2, 8 :: (store (s32) into %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NO-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x1 = LW $x2, 12 :: (load (s32) from %stack.0) + ; CHECK-NO-ZCMP32-NEXT: $x8 = LW $x2, 8 :: (load (s32) from %stack.1) + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP32-NEXT: PseudoRET + ; + ; CHECK-NO-ZCMP64-LABEL: name: popret_rvlist5 + ; CHECK-NO-ZCMP64: liveins: $x1, $x8 + ; CHECK-NO-ZCMP64-NEXT: {{ $}} + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP64-NEXT: SD killed $x1, $x2, 8 :: (store (s64) into %stack.0) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x8, $x2, 0 :: (store (s64) into %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NO-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.0) + ; CHECK-NO-ZCMP64-NEXT: $x8 = LD $x2, 0 :: (load (s64) from %stack.1) + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP64-NEXT: PseudoRET + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + PseudoRET +... +--- +name: popretz_rvlist5 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-ZCMP32-LABEL: name: popretz_rvlist5 + ; CHECK-ZCMP32: liveins: $x1, $x8 + ; CHECK-ZCMP32-NEXT: {{ $}} + ; CHECK-ZCMP32-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -4 + ; CHECK-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: CM_POPRETZ 5, 0, implicit-def $x2, implicit-def $x10, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL32-LABEL: name: popretz_rvlist5 + ; CHECK-LIBCALL32: liveins: $x1, $x8 + ; CHECK-LIBCALL32-NEXT: {{ $}} + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit $x10 + ; + ; CHECK-ZCMP64-LABEL: name: popretz_rvlist5 + ; CHECK-ZCMP64: liveins: $x1, $x8 + ; CHECK-ZCMP64-NEXT: {{ $}} + ; CHECK-ZCMP64-NEXT: frame-setup CM_PUSH 5, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: CM_POPRETZ 5, 0, implicit-def $x2, implicit-def $x10, implicit $x2, implicit-def $x1, implicit-def $x8 + ; + ; CHECK-LIBCALL64-LABEL: name: popretz_rvlist5 + ; CHECK-LIBCALL64: liveins: $x1, $x8 + ; CHECK-LIBCALL64-NEXT: {{ $}} + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_1 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_1, implicit $x2, implicit $x10 + ; + ; CHECK-NO-ZCMP32-LABEL: name: popretz_rvlist5 + ; CHECK-NO-ZCMP32: liveins: $x1, $x8 + ; CHECK-NO-ZCMP32-NEXT: {{ $}} + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP32-NEXT: SW killed $x1, $x2, 12 :: (store (s32) into %stack.0) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x8, $x2, 8 :: (store (s32) into %stack.1) + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NO-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-NO-ZCMP32-NEXT: $x1 = LW $x2, 12 :: (load (s32) from %stack.0) + ; CHECK-NO-ZCMP32-NEXT: $x8 = LW $x2, 8 :: (load (s32) from %stack.1) + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP32-NEXT: PseudoRET implicit $x10 + ; + ; CHECK-NO-ZCMP64-LABEL: name: popretz_rvlist5 + ; CHECK-NO-ZCMP64: liveins: $x1, $x8 + ; CHECK-NO-ZCMP64-NEXT: {{ $}} + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-setup ADDI $x2, -16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 16 + ; CHECK-NO-ZCMP64-NEXT: SD killed $x1, $x2, 8 :: (store (s64) into %stack.0) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x8, $x2, 0 :: (store (s64) into %stack.1) + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NO-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x10 = ADDI $x0, 0 + ; CHECK-NO-ZCMP64-NEXT: $x1 = LD $x2, 8 :: (load (s64) from %stack.0) + ; CHECK-NO-ZCMP64-NEXT: $x8 = LD $x2, 0 :: (load (s64) from %stack.1) + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-destroy ADDI $x2, 16 + ; CHECK-NO-ZCMP64-NEXT: PseudoRET implicit $x10 + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + $x10 = COPY $x0 + PseudoRET implicit $x10 +... diff --git a/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir b/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir new file mode 100644 index 0000000000000000000000000000000000000000..db474b51432c740b793d8e4c9473183104aa6401 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/zcmp-cm-push-pop.mir @@ -0,0 +1,286 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=riscv32 -mattr=+zcmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP32 %s +# RUN: llc -mtriple=riscv32 -mattr=+save-restore -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL32 %s +# RUN: llc -mtriple=riscv64 -mattr=+zcmp -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-ZCMP64 %s +# RUN: llc -mtriple=riscv64 -mattr=+save-restore -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-LIBCALL64 %s +# RUN: llc -mtriple=riscv32 -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP32 %s +# RUN: llc -mtriple=riscv64 -x mir -run-pass=prologepilog -verify-machineinstrs -o - %s \ +# RUN: | FileCheck -check-prefixes=CHECK-NO-ZCMP64 %s +--- +name: push_rvlist15 +tracksRegLiveness: true +body: | + bb.0: + ; CHECK-ZCMP32-LABEL: name: push_rvlist15 + ; CHECK-ZCMP32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-ZCMP32-NEXT: {{ $}} + ; CHECK-ZCMP32-NEXT: frame-setup CM_PUSH 15, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8, implicit $x9, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -52 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -48 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -44 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -40 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -36 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -32 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -24 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -20 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -16 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -12 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -8 + ; CHECK-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -4 + ; CHECK-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-ZCMP32-NEXT: frame-destroy CM_POP 15, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8, implicit-def $x9, implicit-def $x18, implicit-def $x19, implicit-def $x20, implicit-def $x21, implicit-def $x22, implicit-def $x23, implicit-def $x24, implicit-def $x25, implicit-def $x26, implicit-def $x27 + ; CHECK-ZCMP32-NEXT: PseudoRET + ; + ; CHECK-LIBCALL32-LABEL: name: push_rvlist15 + ; CHECK-LIBCALL32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-LIBCALL32-NEXT: {{ $}} + ; CHECK-LIBCALL32-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_12 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -12 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -16 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -20 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -24 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -32 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -36 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -40 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -44 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -48 + ; CHECK-LIBCALL32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -52 + ; CHECK-LIBCALL32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-LIBCALL32-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_12, implicit $x2 + ; + ; CHECK-ZCMP64-LABEL: name: push_rvlist15 + ; CHECK-ZCMP64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-ZCMP64-NEXT: {{ $}} + ; CHECK-ZCMP64-NEXT: frame-setup CM_PUSH 15, 0, implicit-def $x2, implicit $x2, implicit $x1, implicit $x8, implicit $x9, implicit $x18, implicit $x19, implicit $x20, implicit $x21, implicit $x22, implicit $x23, implicit $x24, implicit $x25, implicit $x26, implicit $x27 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -104 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -96 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -88 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -80 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -72 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -64 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -48 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -40 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -32 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -24 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -16 + ; CHECK-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -8 + ; CHECK-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-ZCMP64-NEXT: frame-destroy CM_POP 15, 0, implicit-def $x2, implicit $x2, implicit-def $x1, implicit-def $x8, implicit-def $x9, implicit-def $x18, implicit-def $x19, implicit-def $x20, implicit-def $x21, implicit-def $x22, implicit-def $x23, implicit-def $x24, implicit-def $x25, implicit-def $x26, implicit-def $x27 + ; CHECK-ZCMP64-NEXT: PseudoRET + ; + ; CHECK-LIBCALL64-LABEL: name: push_rvlist15 + ; CHECK-LIBCALL64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-LIBCALL64-NEXT: {{ $}} + ; CHECK-LIBCALL64-NEXT: $x5 = frame-setup PseudoCALLReg target-flags(riscv-call) &__riscv_save_12 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -24 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -32 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -40 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -48 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -64 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -72 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -80 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -88 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -96 + ; CHECK-LIBCALL64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -104 + ; CHECK-LIBCALL64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-LIBCALL64-NEXT: frame-destroy PseudoTAIL target-flags(riscv-call) &__riscv_restore_12, implicit $x2 + ; + ; CHECK-NO-ZCMP32-LABEL: name: push_rvlist15 + ; CHECK-NO-ZCMP32: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-NO-ZCMP32-NEXT: {{ $}} + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-setup ADDI $x2, -64 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 64 + ; CHECK-NO-ZCMP32-NEXT: SW killed $x1, $x2, 60 :: (store (s32) into %stack.0) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x8, $x2, 56 :: (store (s32) into %stack.1) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x9, $x2, 52 :: (store (s32) into %stack.2) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x18, $x2, 48 :: (store (s32) into %stack.3) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x19, $x2, 44 :: (store (s32) into %stack.4) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x20, $x2, 40 :: (store (s32) into %stack.5) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x21, $x2, 36 :: (store (s32) into %stack.6) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x22, $x2, 32 :: (store (s32) into %stack.7) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x23, $x2, 28 :: (store (s32) into %stack.8) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x24, $x2, 24 :: (store (s32) into %stack.9) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x25, $x2, 20 :: (store (s32) into %stack.10) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x26, $x2, 16 :: (store (s32) into %stack.11) + ; CHECK-NO-ZCMP32-NEXT: SW killed $x27, $x2, 12 :: (store (s32) into %stack.12) + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -4 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -8 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -12 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -16 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -20 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -24 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -28 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -32 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -36 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -40 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -44 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -48 + ; CHECK-NO-ZCMP32-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -52 + ; CHECK-NO-ZCMP32-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-NO-ZCMP32-NEXT: $x1 = LW $x2, 60 :: (load (s32) from %stack.0) + ; CHECK-NO-ZCMP32-NEXT: $x8 = LW $x2, 56 :: (load (s32) from %stack.1) + ; CHECK-NO-ZCMP32-NEXT: $x9 = LW $x2, 52 :: (load (s32) from %stack.2) + ; CHECK-NO-ZCMP32-NEXT: $x18 = LW $x2, 48 :: (load (s32) from %stack.3) + ; CHECK-NO-ZCMP32-NEXT: $x19 = LW $x2, 44 :: (load (s32) from %stack.4) + ; CHECK-NO-ZCMP32-NEXT: $x20 = LW $x2, 40 :: (load (s32) from %stack.5) + ; CHECK-NO-ZCMP32-NEXT: $x21 = LW $x2, 36 :: (load (s32) from %stack.6) + ; CHECK-NO-ZCMP32-NEXT: $x22 = LW $x2, 32 :: (load (s32) from %stack.7) + ; CHECK-NO-ZCMP32-NEXT: $x23 = LW $x2, 28 :: (load (s32) from %stack.8) + ; CHECK-NO-ZCMP32-NEXT: $x24 = LW $x2, 24 :: (load (s32) from %stack.9) + ; CHECK-NO-ZCMP32-NEXT: $x25 = LW $x2, 20 :: (load (s32) from %stack.10) + ; CHECK-NO-ZCMP32-NEXT: $x26 = LW $x2, 16 :: (load (s32) from %stack.11) + ; CHECK-NO-ZCMP32-NEXT: $x27 = LW $x2, 12 :: (load (s32) from %stack.12) + ; CHECK-NO-ZCMP32-NEXT: $x2 = frame-destroy ADDI $x2, 64 + ; CHECK-NO-ZCMP32-NEXT: PseudoRET + ; + ; CHECK-NO-ZCMP64-LABEL: name: push_rvlist15 + ; CHECK-NO-ZCMP64: liveins: $x1, $x8, $x9, $x18, $x19, $x20, $x21, $x22, $x23, $x24, $x25, $x26, $x27 + ; CHECK-NO-ZCMP64-NEXT: {{ $}} + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-setup ADDI $x2, -112 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION def_cfa_offset 112 + ; CHECK-NO-ZCMP64-NEXT: SD killed $x1, $x2, 104 :: (store (s64) into %stack.0) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x8, $x2, 96 :: (store (s64) into %stack.1) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x9, $x2, 88 :: (store (s64) into %stack.2) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x18, $x2, 80 :: (store (s64) into %stack.3) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x19, $x2, 72 :: (store (s64) into %stack.4) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x20, $x2, 64 :: (store (s64) into %stack.5) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x21, $x2, 56 :: (store (s64) into %stack.6) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x22, $x2, 48 :: (store (s64) into %stack.7) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x23, $x2, 40 :: (store (s64) into %stack.8) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x24, $x2, 32 :: (store (s64) into %stack.9) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x25, $x2, 24 :: (store (s64) into %stack.10) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x26, $x2, 16 :: (store (s64) into %stack.11) + ; CHECK-NO-ZCMP64-NEXT: SD killed $x27, $x2, 8 :: (store (s64) into %stack.12) + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x1, -8 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x8, -16 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x9, -24 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x18, -32 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x19, -40 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x20, -48 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x21, -56 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x22, -64 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x23, -72 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x24, -80 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x25, -88 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x26, -96 + ; CHECK-NO-ZCMP64-NEXT: frame-setup CFI_INSTRUCTION offset $x27, -104 + ; CHECK-NO-ZCMP64-NEXT: $x1 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x8 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x9 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x18 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x19 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x20 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x21 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x22 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x23 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x24 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x25 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x26 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x27 = IMPLICIT_DEF + ; CHECK-NO-ZCMP64-NEXT: $x1 = LD $x2, 104 :: (load (s64) from %stack.0) + ; CHECK-NO-ZCMP64-NEXT: $x8 = LD $x2, 96 :: (load (s64) from %stack.1) + ; CHECK-NO-ZCMP64-NEXT: $x9 = LD $x2, 88 :: (load (s64) from %stack.2) + ; CHECK-NO-ZCMP64-NEXT: $x18 = LD $x2, 80 :: (load (s64) from %stack.3) + ; CHECK-NO-ZCMP64-NEXT: $x19 = LD $x2, 72 :: (load (s64) from %stack.4) + ; CHECK-NO-ZCMP64-NEXT: $x20 = LD $x2, 64 :: (load (s64) from %stack.5) + ; CHECK-NO-ZCMP64-NEXT: $x21 = LD $x2, 56 :: (load (s64) from %stack.6) + ; CHECK-NO-ZCMP64-NEXT: $x22 = LD $x2, 48 :: (load (s64) from %stack.7) + ; CHECK-NO-ZCMP64-NEXT: $x23 = LD $x2, 40 :: (load (s64) from %stack.8) + ; CHECK-NO-ZCMP64-NEXT: $x24 = LD $x2, 32 :: (load (s64) from %stack.9) + ; CHECK-NO-ZCMP64-NEXT: $x25 = LD $x2, 24 :: (load (s64) from %stack.10) + ; CHECK-NO-ZCMP64-NEXT: $x26 = LD $x2, 16 :: (load (s64) from %stack.11) + ; CHECK-NO-ZCMP64-NEXT: $x27 = LD $x2, 8 :: (load (s64) from %stack.12) + ; CHECK-NO-ZCMP64-NEXT: $x2 = frame-destroy ADDI $x2, 112 + ; CHECK-NO-ZCMP64-NEXT: PseudoRET + $x1 = IMPLICIT_DEF + $x8 = IMPLICIT_DEF + $x9 = IMPLICIT_DEF + $x18 = IMPLICIT_DEF + $x19 = IMPLICIT_DEF + $x20 = IMPLICIT_DEF + $x21 = IMPLICIT_DEF + $x22 = IMPLICIT_DEF + $x23 = IMPLICIT_DEF + $x24 = IMPLICIT_DEF + $x25 = IMPLICIT_DEF + $x26 = IMPLICIT_DEF + $x27 = IMPLICIT_DEF + PseudoRET +... diff --git a/llvm/test/CodeGen/SystemZ/asm-01.ll b/llvm/test/CodeGen/SystemZ/asm-01.ll index 2c4613cacb07c519115f8d1f0c2924ef4ead4fa0..28278d75b4e757cb5bd2c78c841fcd116e35ed9c 100644 --- a/llvm/test/CodeGen/SystemZ/asm-01.ll +++ b/llvm/test/CodeGen/SystemZ/asm-01.ll @@ -59,3 +59,14 @@ define void @f5(i64 %base, i64 %index) { call void asm "blah $0", "=*Q" (ptr elementtype(i64) %addr) ret void } + +; Check A, O and R format flags. +define void @f6(i64 %base) { +; CHECK-LABEL: f6: +; CHECK: blah 111,%r2 +; CHECK: br %r14 + %add = add i64 %base, 111 + %addr = inttoptr i64 %add to ptr + call void asm "blah ${0:O},${0:R}${0:A}", "=*Q" (ptr elementtype(i64) %addr) + ret void +} diff --git a/llvm/test/CodeGen/WebAssembly/immediates.ll b/llvm/test/CodeGen/WebAssembly/immediates.ll index e2342f391b13cbf92ab2f65869f44539f2f57353..9de5aa74024933ce57769fa5bc9e7c87d8b3b2f1 100644 --- a/llvm/test/CodeGen/WebAssembly/immediates.ll +++ b/llvm/test/CodeGen/WebAssembly/immediates.ll @@ -1,11 +1,5 @@ ; RUN: llc < %s -asm-verbose=false -disable-wasm-fallthrough-return-opt -wasm-keep-registers | FileCheck %s -; Usually MIPS hosts uses a legacy (non IEEE 754-2008) encoding for NaNs. -; Tests like `nan_f32` failed in attempt to compare hard-coded IEEE 754-2008 -; NaN value and a legacy NaN value provided by a system. -; FIXME: This should be based on host not target, but there's no "system-mips" feature. -; XFAIL: target={{(mips|mipsel|mips64|mips64el)-.*}} - ; Test that basic immediates assemble as expected. target triple = "wasm32-unknown-unknown" diff --git a/llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll b/llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll new file mode 100644 index 0000000000000000000000000000000000000000..fadeb397a884c2e24591714164db090e529539df --- /dev/null +++ b/llvm/test/CodeGen/WebAssembly/suboptimal-compare.ll @@ -0,0 +1,43 @@ +; RUN: llc < %s -fast-isel -O0 | FileCheck %s + +target triple = "wasm32-unknown-unknown" + +; CHECK-LABEL: gh_80053: # @gh_80053 +; CHECK-NEXT: .functype gh_80053 (i32) -> (i32) +; CHECK-NEXT: .local i32, i32, i32, i32, i32, i32 +; CHECK: i32.const 0 +; CHECK-NEXT: local.set 1 +; CHECK-NEXT: local.get 0 +; CHECK-NEXT: local.get 1 +; CHECK-NEXT: i32.eq +; CHECK-NEXT: local.set 2 +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 3 +; CHECK-NEXT: local.get 2 +; CHECK-NEXT: local.get 3 +; CHECK-NEXT: i32.and +; CHECK-NEXT: local.set 4 +; CHECK-NEXT: block +; CHECK-NEXT: local.get 4 +; CHECK-NEXT: i32.eqz +; CHECK-NEXT: br_if 0 # 0: down to label0 +; CHECK: i32.const 0 +; CHECK-NEXT: local.set 5 +; CHECK-NEXT: local.get 5 +; CHECK-NEXT: return +; CHECK-NEXT: .LBB0_2: # %BB03 +; CHECK-NEXT: end_block # label0: +; CHECK-NEXT: i32.const 1 +; CHECK-NEXT: local.set 6 +; CHECK-NEXT: local.get 6 +; CHECK-NEXT: return +; CHECK-NEXT: end_function +define i1 @gh_80053(ptr) { +BB01: + %eq = icmp eq ptr %0, null + br i1 %eq, label %BB02, label %BB03 +BB02: + ret i1 0 +BB03: + ret i1 1 +} diff --git a/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll b/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll index 9ef9c14084a7d7fd78acef4ec1aeb70790a6e5c4..3dd8463d9dd1016e58c719a7117e5e28506bb372 100644 --- a/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll +++ b/llvm/test/CodeGen/WebAssembly/xor_reassociate.ll @@ -17,7 +17,7 @@ define i32 @reassociate_xor(float %x, float %y) { ; CHECK-NEXT: local.get 0 ; CHECK-NEXT: f32.const 0x1p-23 ; CHECK-NEXT: f32.gt -; CHECK-NEXT: i32.ne +; CHECK-NEXT: i32.xor ; CHECK-NEXT: br_if 0 # 0: down to label0 ; CHECK-NEXT: # %bb.1: # %if.then.i ; CHECK-NEXT: i32.const 0 diff --git a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll index 780abc9f9dc43cfb0da009a743e14ff5ca463013..1ca870add95b5d0a3d754261cc085da6d3aaf685 100644 --- a/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512-intrinsics-fast-isel.ll @@ -21,7 +21,7 @@ define zeroext i16 @test_mm512_kunpackb(<8 x i64> %__A, <8 x i64> %__B, <8 x i64 ; X86-NEXT: kunpckbw %k0, %k1, %k1 ; X86-NEXT: vpcmpneqd 72(%ebp), %zmm3, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: movl %ebp, %esp ; X86-NEXT: popl %ebp ; X86-NEXT: .cfi_def_cfa %esp, 4 @@ -35,7 +35,7 @@ define zeroext i16 @test_mm512_kunpackb(<8 x i64> %__A, <8 x i64> %__B, <8 x i64 ; X64-NEXT: kunpckbw %k0, %k1, %k1 ; X64-NEXT: vpcmpneqd %zmm5, %zmm4, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -367,7 +367,7 @@ define zeroext i16 @test_mm512_testn_epi32_mask(<8 x i64> %__A, <8 x i64> %__B) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmd %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -385,7 +385,7 @@ define zeroext i16 @test_mm512_mask_testn_epi32_mask(i16 zeroext %__U, <8 x i64> ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmd %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -394,7 +394,7 @@ define zeroext i16 @test_mm512_mask_testn_epi32_mask(i16 zeroext %__U, <8 x i64> ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmd %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -412,7 +412,7 @@ define zeroext i8 @test_mm512_testn_epi64_mask(<8 x i64> %__A, <8 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmq %zmm0, %zmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -429,7 +429,7 @@ define zeroext i8 @test_mm512_mask_testn_epi64_mask(i8 zeroext %__U, <8 x i64> % ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmq %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -438,7 +438,7 @@ define zeroext i8 @test_mm512_mask_testn_epi64_mask(i8 zeroext %__U, <8 x i64> % ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmq %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -457,7 +457,7 @@ define zeroext i16 @test_mm512_mask_test_epi32_mask(i16 zeroext %__U, <8 x i64> ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmd %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -466,7 +466,7 @@ define zeroext i16 @test_mm512_mask_test_epi32_mask(i16 zeroext %__U, <8 x i64> ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmd %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -486,7 +486,7 @@ define zeroext i8 @test_mm512_mask_test_epi64_mask(i8 zeroext %__U, <8 x i64> %_ ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -495,7 +495,7 @@ define zeroext i8 @test_mm512_mask_test_epi64_mask(i8 zeroext %__U, <8 x i64> %_ ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmq %zmm0, %zmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll index a32b84986e895174b066394635da7776eca4a78b..00729262473daf07b82837f84f9e889a1d0480ce 100644 --- a/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512bwvl-intrinsics-fast-isel.ll @@ -9,7 +9,7 @@ define zeroext i16 @test_mm_test_epi8_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmb %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -25,7 +25,7 @@ define zeroext i16 @test_mm_mask_test_epi8_mask(i16 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestmb %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi8_mask: @@ -33,7 +33,7 @@ define zeroext i16 @test_mm_mask_test_epi8_mask(i16 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestmb %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -91,7 +91,7 @@ define zeroext i8 @test_mm_test_epi16_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmw %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -108,7 +108,7 @@ define zeroext i8 @test_mm_mask_test_epi16_mask(i8 zeroext %__U, <2 x i64> %__A, ; X86-NEXT: kmovd %eax, %k1 ; X86-NEXT: vptestmw %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi16_mask: @@ -116,7 +116,7 @@ define zeroext i8 @test_mm_mask_test_epi16_mask(i8 zeroext %__U, <2 x i64> %__A, ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestmw %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -133,7 +133,7 @@ define zeroext i16 @test_mm256_test_epi16_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmw %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -150,7 +150,7 @@ define zeroext i16 @test_mm256_mask_test_epi16_mask(i16 zeroext %__U, <4 x i64> ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestmw %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -159,7 +159,7 @@ define zeroext i16 @test_mm256_mask_test_epi16_mask(i16 zeroext %__U, <4 x i64> ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestmw %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -177,7 +177,7 @@ define zeroext i16 @test_mm_testn_epi8_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmb %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -193,7 +193,7 @@ define zeroext i16 @test_mm_mask_testn_epi8_mask(i16 zeroext %__U, <2 x i64> %__ ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestnmb %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi8_mask: @@ -201,7 +201,7 @@ define zeroext i16 @test_mm_mask_testn_epi8_mask(i16 zeroext %__U, <2 x i64> %__ ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestnmb %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -259,7 +259,7 @@ define zeroext i8 @test_mm_testn_epi16_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmw %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -276,7 +276,7 @@ define zeroext i8 @test_mm_mask_testn_epi16_mask(i8 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovd %eax, %k1 ; X86-NEXT: vptestnmw %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi16_mask: @@ -284,7 +284,7 @@ define zeroext i8 @test_mm_mask_testn_epi16_mask(i8 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestnmw %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -301,7 +301,7 @@ define zeroext i16 @test_mm256_testn_epi16_mask(<4 x i64> %__A, <4 x i64> %__B) ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmw %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovd %k0, %eax -; CHECK-NEXT: movzwl %ax, %eax +; CHECK-NEXT: # kill: def $ax killed $ax killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -318,7 +318,7 @@ define zeroext i16 @test_mm256_mask_testn_epi16_mask(i16 zeroext %__U, <4 x i64> ; X86-NEXT: kmovw {{[0-9]+}}(%esp), %k1 ; X86-NEXT: vptestnmw %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovd %k0, %eax -; X86-NEXT: movzwl %ax, %eax +; X86-NEXT: # kill: def $ax killed $ax killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -327,7 +327,7 @@ define zeroext i16 @test_mm256_mask_testn_epi16_mask(i16 zeroext %__U, <4 x i64> ; X64-NEXT: kmovd %edi, %k1 ; X64-NEXT: vptestnmw %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovd %k0, %eax -; X64-NEXT: movzwl %ax, %eax +; X64-NEXT: # kill: def $ax killed $ax killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll index 173e2bad8acebca81de38d645a28c4f5e0012067..06e7096e430bbd8a0e248ce5e48ceae2a7720e5b 100644 --- a/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/avx512vl-intrinsics-fast-isel.ll @@ -1547,7 +1547,7 @@ define zeroext i8 @test_mm_test_epi32_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmd %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1565,7 +1565,7 @@ define zeroext i8 @test_mm_mask_test_epi32_mask(i8 zeroext %__U, <2 x i64> %__A, ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi32_mask: @@ -1573,7 +1573,7 @@ define zeroext i8 @test_mm_mask_test_epi32_mask(i8 zeroext %__U, <2 x i64> %__A, ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmd %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1592,7 +1592,7 @@ define zeroext i8 @test_mm256_test_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmd %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1610,7 +1610,7 @@ define zeroext i8 @test_mm256_mask_test_epi32_mask(i8 zeroext %__U, <4 x i64> %_ ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1619,7 +1619,7 @@ define zeroext i8 @test_mm256_mask_test_epi32_mask(i8 zeroext %__U, <4 x i64> %_ ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmd %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -1637,7 +1637,7 @@ define zeroext i8 @test_mm_test_epi64_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmq %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1654,7 +1654,7 @@ define zeroext i8 @test_mm_mask_test_epi64_mask(i8 zeroext %__U, <2 x i64> %__A, ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_test_epi64_mask: @@ -1662,7 +1662,7 @@ define zeroext i8 @test_mm_mask_test_epi64_mask(i8 zeroext %__U, <2 x i64> %__A, ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmq %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1680,7 +1680,7 @@ define zeroext i8 @test_mm256_test_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestmq %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1698,7 +1698,7 @@ define zeroext i8 @test_mm256_mask_test_epi64_mask(i8 zeroext %__U, <4 x i64> %_ ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1707,7 +1707,7 @@ define zeroext i8 @test_mm256_mask_test_epi64_mask(i8 zeroext %__U, <4 x i64> %_ ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestmq %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -1726,7 +1726,7 @@ define zeroext i8 @test_mm_testn_epi32_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmd %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1744,7 +1744,7 @@ define zeroext i8 @test_mm_mask_testn_epi32_mask(i8 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi32_mask: @@ -1752,7 +1752,7 @@ define zeroext i8 @test_mm_mask_testn_epi32_mask(i8 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmd %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1771,7 +1771,7 @@ define zeroext i8 @test_mm256_testn_epi32_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmd %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1789,7 +1789,7 @@ define zeroext i8 @test_mm256_mask_testn_epi32_mask(i8 zeroext %__U, <4 x i64> % ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1798,7 +1798,7 @@ define zeroext i8 @test_mm256_mask_testn_epi32_mask(i8 zeroext %__U, <4 x i64> % ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmd %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: @@ -1816,7 +1816,7 @@ define zeroext i8 @test_mm_testn_epi64_mask(<2 x i64> %__A, <2 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmq %xmm0, %xmm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: ret{{[l|q]}} entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1833,7 +1833,7 @@ define zeroext i8 @test_mm_mask_testn_epi64_mask(i8 zeroext %__U, <2 x i64> %__A ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: retl ; ; X64-LABEL: test_mm_mask_testn_epi64_mask: @@ -1841,7 +1841,7 @@ define zeroext i8 @test_mm_mask_testn_epi64_mask(i8 zeroext %__U, <2 x i64> %__A ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmq %xmm0, %xmm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: retq entry: %and.i.i = and <2 x i64> %__B, %__A @@ -1859,7 +1859,7 @@ define zeroext i8 @test_mm256_testn_epi64_mask(<4 x i64> %__A, <4 x i64> %__B) { ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vptestnmq %ymm0, %ymm1, %k0 ; CHECK-NEXT: kmovw %k0, %eax -; CHECK-NEXT: movzbl %al, %eax +; CHECK-NEXT: # kill: def $al killed $al killed $eax ; CHECK-NEXT: vzeroupper ; CHECK-NEXT: ret{{[l|q]}} entry: @@ -1877,7 +1877,7 @@ define zeroext i8 @test_mm256_mask_testn_epi64_mask(i8 zeroext %__U, <4 x i64> % ; X86-NEXT: kmovw %eax, %k1 ; X86-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1} ; X86-NEXT: kmovw %k0, %eax -; X86-NEXT: movzbl %al, %eax +; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: vzeroupper ; X86-NEXT: retl ; @@ -1886,7 +1886,7 @@ define zeroext i8 @test_mm256_mask_testn_epi64_mask(i8 zeroext %__U, <4 x i64> % ; X64-NEXT: kmovw %edi, %k1 ; X64-NEXT: vptestnmq %ymm0, %ymm1, %k0 {%k1} ; X64-NEXT: kmovw %k0, %eax -; X64-NEXT: movzbl %al, %eax +; X64-NEXT: # kill: def $al killed $al killed $eax ; X64-NEXT: vzeroupper ; X64-NEXT: retq entry: diff --git a/llvm/test/CodeGen/X86/combine-movmsk-avx.ll b/llvm/test/CodeGen/X86/combine-movmsk-avx.ll index b3f4878745193cfd3cc485b00c6629ecd3e7aa10..6da4102bc2ecd467526684ae5bca0bdb135072c3 100644 --- a/llvm/test/CodeGen/X86/combine-movmsk-avx.ll +++ b/llvm/test/CodeGen/X86/combine-movmsk-avx.ll @@ -1,7 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=ADL +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,VTEST,VTEST-AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2,+prefer-movmsk-over-vtest | FileCheck %s --check-prefixes=CHECK,MOVMSK,MOVMSK-AVX2 declare i32 @llvm.x86.avx.movmsk.pd.256(<4 x double>) declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) @@ -9,24 +10,24 @@ declare i32 @llvm.x86.avx.movmsk.ps.256(<8 x float>) ; Use widest possible vector for movmsk comparisons (PR37087) define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) { -; CHECK-LABEL: movmskps_noneof_bitcast_v4f64: -; CHECK: # %bb.0: -; CHECK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 -; CHECK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 -; CHECK-NEXT: vtestpd %ymm0, %ymm0 -; CHECK-NEXT: sete %al -; CHECK-NEXT: vzeroupper -; CHECK-NEXT: retq +; VTEST-LABEL: movmskps_noneof_bitcast_v4f64: +; VTEST: # %bb.0: +; VTEST-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; VTEST-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 +; VTEST-NEXT: vtestpd %ymm0, %ymm0 +; VTEST-NEXT: sete %al +; VTEST-NEXT: vzeroupper +; VTEST-NEXT: retq ; -; ADL-LABEL: movmskps_noneof_bitcast_v4f64: -; ADL: # %bb.0: -; ADL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 -; ADL-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 -; ADL-NEXT: vmovmskpd %ymm0, %eax -; ADL-NEXT: testl %eax, %eax -; ADL-NEXT: sete %al -; ADL-NEXT: vzeroupper -; ADL-NEXT: retq +; MOVMSK-LABEL: movmskps_noneof_bitcast_v4f64: +; MOVMSK: # %bb.0: +; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 +; MOVMSK-NEXT: vmovmskpd %ymm0, %eax +; MOVMSK-NEXT: testl %eax, %eax +; MOVMSK-NEXT: sete %al +; MOVMSK-NEXT: vzeroupper +; MOVMSK-NEXT: retq %1 = fcmp oeq <4 x double> %a0, zeroinitializer %2 = sext <4 x i1> %1 to <4 x i64> %3 = bitcast <4 x i64> %2 to <8 x float> @@ -36,35 +37,35 @@ define i1 @movmskps_noneof_bitcast_v4f64(<4 x double> %a0) { } define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) { -; AVX1-LABEL: movmskps_allof_bitcast_v4f64: -; AVX1: # %bb.0: -; AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 -; AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 -; AVX1-NEXT: vtestpd %ymm1, %ymm0 -; AVX1-NEXT: setb %al -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: movmskps_allof_bitcast_v4f64: -; AVX2: # %bb.0: -; AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 -; AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 -; AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 -; AVX2-NEXT: vtestpd %ymm1, %ymm0 -; AVX2-NEXT: setb %al -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; ADL-LABEL: movmskps_allof_bitcast_v4f64: -; ADL: # %bb.0: -; ADL-NEXT: vxorpd %xmm1, %xmm1, %xmm1 -; ADL-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 -; ADL-NEXT: vmovmskpd %ymm0, %eax -; ADL-NEXT: cmpl $15, %eax -; ADL-NEXT: sete %al -; ADL-NEXT: vzeroupper -; ADL-NEXT: retq +; VTEST-AVX1-LABEL: movmskps_allof_bitcast_v4f64: +; VTEST-AVX1: # %bb.0: +; VTEST-AVX1-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; VTEST-AVX1-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 +; VTEST-AVX1-NEXT: vcmptrueps %ymm1, %ymm1, %ymm1 +; VTEST-AVX1-NEXT: vtestpd %ymm1, %ymm0 +; VTEST-AVX1-NEXT: setb %al +; VTEST-AVX1-NEXT: vzeroupper +; VTEST-AVX1-NEXT: retq +; +; VTEST-AVX2-LABEL: movmskps_allof_bitcast_v4f64: +; VTEST-AVX2: # %bb.0: +; VTEST-AVX2-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; VTEST-AVX2-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 +; VTEST-AVX2-NEXT: vpcmpeqd %ymm1, %ymm1, %ymm1 +; VTEST-AVX2-NEXT: vtestpd %ymm1, %ymm0 +; VTEST-AVX2-NEXT: setb %al +; VTEST-AVX2-NEXT: vzeroupper +; VTEST-AVX2-NEXT: retq +; +; MOVMSK-LABEL: movmskps_allof_bitcast_v4f64: +; MOVMSK: # %bb.0: +; MOVMSK-NEXT: vxorpd %xmm1, %xmm1, %xmm1 +; MOVMSK-NEXT: vcmpeqpd %ymm1, %ymm0, %ymm0 +; MOVMSK-NEXT: vmovmskpd %ymm0, %eax +; MOVMSK-NEXT: cmpl $15, %eax +; MOVMSK-NEXT: sete %al +; MOVMSK-NEXT: vzeroupper +; MOVMSK-NEXT: retq %1 = fcmp oeq <4 x double> %a0, zeroinitializer %2 = sext <4 x i1> %1 to <4 x i64> %3 = bitcast <4 x i64> %2 to <8 x float> @@ -78,26 +79,35 @@ define i1 @movmskps_allof_bitcast_v4f64(<4 x double> %a0) { ; define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) { -; AVX1-LABEL: movmskpd_cmpgt_v4i64: -; AVX1: # %bb.0: -; AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1 -; AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] -; AVX1-NEXT: vmovmskpd %ymm0, %eax -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: movmskpd_cmpgt_v4i64: -; AVX2: # %bb.0: -; AVX2-NEXT: vmovmskpd %ymm0, %eax -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; ADL-LABEL: movmskpd_cmpgt_v4i64: -; ADL: # %bb.0: -; ADL-NEXT: vmovmskpd %ymm0, %eax -; ADL-NEXT: vzeroupper -; ADL-NEXT: retq +; VTEST-AVX1-LABEL: movmskpd_cmpgt_v4i64: +; VTEST-AVX1: # %bb.0: +; VTEST-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; VTEST-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1 +; VTEST-AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] +; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax +; VTEST-AVX1-NEXT: vzeroupper +; VTEST-AVX1-NEXT: retq +; +; VTEST-AVX2-LABEL: movmskpd_cmpgt_v4i64: +; VTEST-AVX2: # %bb.0: +; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax +; VTEST-AVX2-NEXT: vzeroupper +; VTEST-AVX2-NEXT: retq +; +; MOVMSK-AVX1-LABEL: movmskpd_cmpgt_v4i64: +; MOVMSK-AVX1: # %bb.0: +; MOVMSK-AVX1-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; MOVMSK-AVX1-NEXT: vpcmpgtq %xmm0, %xmm1, %xmm1 +; MOVMSK-AVX1-NEXT: vblendpd {{.*#+}} ymm0 = ymm1[0,1],ymm0[2,3] +; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax +; MOVMSK-AVX1-NEXT: vzeroupper +; MOVMSK-AVX1-NEXT: retq +; +; MOVMSK-AVX2-LABEL: movmskpd_cmpgt_v4i64: +; MOVMSK-AVX2: # %bb.0: +; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax +; MOVMSK-AVX2-NEXT: vzeroupper +; MOVMSK-AVX2-NEXT: retq %1 = icmp sgt <4 x i64> zeroinitializer, %a0 %2 = sext <4 x i1> %1 to <4 x i64> %3 = bitcast <4 x i64> %2 to <4 x double> @@ -106,25 +116,33 @@ define i32 @movmskpd_cmpgt_v4i64(<4 x i64> %a0) { } define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) { -; AVX1-LABEL: movmskps_ashr_v8i32: -; AVX1: # %bb.0: -; AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 -; AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] -; AVX1-NEXT: vmovmskps %ymm0, %eax -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: movmskps_ashr_v8i32: -; AVX2: # %bb.0: -; AVX2-NEXT: vmovmskps %ymm0, %eax -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; ADL-LABEL: movmskps_ashr_v8i32: -; ADL: # %bb.0: -; ADL-NEXT: vmovmskps %ymm0, %eax -; ADL-NEXT: vzeroupper -; ADL-NEXT: retq +; VTEST-AVX1-LABEL: movmskps_ashr_v8i32: +; VTEST-AVX1: # %bb.0: +; VTEST-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 +; VTEST-AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax +; VTEST-AVX1-NEXT: vzeroupper +; VTEST-AVX1-NEXT: retq +; +; VTEST-AVX2-LABEL: movmskps_ashr_v8i32: +; VTEST-AVX2: # %bb.0: +; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax +; VTEST-AVX2-NEXT: vzeroupper +; VTEST-AVX2-NEXT: retq +; +; MOVMSK-AVX1-LABEL: movmskps_ashr_v8i32: +; MOVMSK-AVX1: # %bb.0: +; MOVMSK-AVX1-NEXT: vpsrad $31, %xmm0, %xmm1 +; MOVMSK-AVX1-NEXT: vblendps {{.*#+}} ymm0 = ymm1[0,1,2,3],ymm0[4,5,6,7] +; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax +; MOVMSK-AVX1-NEXT: vzeroupper +; MOVMSK-AVX1-NEXT: retq +; +; MOVMSK-AVX2-LABEL: movmskps_ashr_v8i32: +; MOVMSK-AVX2: # %bb.0: +; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax +; MOVMSK-AVX2-NEXT: vzeroupper +; MOVMSK-AVX2-NEXT: retq %1 = ashr <8 x i32> %a0, %2 = bitcast <8 x i32> %1 to <8 x float> %3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2) @@ -132,29 +150,39 @@ define i32 @movmskps_ashr_v8i32(<8 x i32> %a0) { } define i32 @movmskps_sext_v4i64(<4 x i32> %a0) { -; AVX1-LABEL: movmskps_sext_v4i64: -; AVX1: # %bb.0: -; AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 -; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] -; AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 -; AVX1-NEXT: vmovmskpd %ymm0, %eax -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: movmskps_sext_v4i64: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 -; AVX2-NEXT: vmovmskpd %ymm0, %eax -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; ADL-LABEL: movmskps_sext_v4i64: -; ADL: # %bb.0: -; ADL-NEXT: vpmovsxdq %xmm0, %ymm0 -; ADL-NEXT: vmovmskpd %ymm0, %eax -; ADL-NEXT: vzeroupper -; ADL-NEXT: retq +; VTEST-AVX1-LABEL: movmskps_sext_v4i64: +; VTEST-AVX1: # %bb.0: +; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 +; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; VTEST-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 +; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; VTEST-AVX1-NEXT: vmovmskpd %ymm0, %eax +; VTEST-AVX1-NEXT: vzeroupper +; VTEST-AVX1-NEXT: retq +; +; VTEST-AVX2-LABEL: movmskps_sext_v4i64: +; VTEST-AVX2: # %bb.0: +; VTEST-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 +; VTEST-AVX2-NEXT: vmovmskpd %ymm0, %eax +; VTEST-AVX2-NEXT: vzeroupper +; VTEST-AVX2-NEXT: retq +; +; MOVMSK-AVX1-LABEL: movmskps_sext_v4i64: +; MOVMSK-AVX1: # %bb.0: +; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm1 +; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; MOVMSK-AVX1-NEXT: vpmovsxdq %xmm0, %xmm0 +; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; MOVMSK-AVX1-NEXT: vmovmskpd %ymm0, %eax +; MOVMSK-AVX1-NEXT: vzeroupper +; MOVMSK-AVX1-NEXT: retq +; +; MOVMSK-AVX2-LABEL: movmskps_sext_v4i64: +; MOVMSK-AVX2: # %bb.0: +; MOVMSK-AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 +; MOVMSK-AVX2-NEXT: vmovmskpd %ymm0, %eax +; MOVMSK-AVX2-NEXT: vzeroupper +; MOVMSK-AVX2-NEXT: retq %1 = sext <4 x i32> %a0 to <4 x i64> %2 = bitcast <4 x i64> %1 to <4 x double> %3 = tail call i32 @llvm.x86.avx.movmsk.pd.256(<4 x double> %2) @@ -162,29 +190,39 @@ define i32 @movmskps_sext_v4i64(<4 x i32> %a0) { } define i32 @movmskps_sext_v8i32(<8 x i16> %a0) { -; AVX1-LABEL: movmskps_sext_v8i32: -; AVX1: # %bb.0: -; AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 -; AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] -; AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 -; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 -; AVX1-NEXT: vmovmskps %ymm0, %eax -; AVX1-NEXT: vzeroupper -; AVX1-NEXT: retq -; -; AVX2-LABEL: movmskps_sext_v8i32: -; AVX2: # %bb.0: -; AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 -; AVX2-NEXT: vmovmskps %ymm0, %eax -; AVX2-NEXT: vzeroupper -; AVX2-NEXT: retq -; -; ADL-LABEL: movmskps_sext_v8i32: -; ADL: # %bb.0: -; ADL-NEXT: vpmovsxwd %xmm0, %ymm0 -; ADL-NEXT: vmovmskps %ymm0, %eax -; ADL-NEXT: vzeroupper -; ADL-NEXT: retq +; VTEST-AVX1-LABEL: movmskps_sext_v8i32: +; VTEST-AVX1: # %bb.0: +; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 +; VTEST-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; VTEST-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 +; VTEST-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; VTEST-AVX1-NEXT: vmovmskps %ymm0, %eax +; VTEST-AVX1-NEXT: vzeroupper +; VTEST-AVX1-NEXT: retq +; +; VTEST-AVX2-LABEL: movmskps_sext_v8i32: +; VTEST-AVX2: # %bb.0: +; VTEST-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 +; VTEST-AVX2-NEXT: vmovmskps %ymm0, %eax +; VTEST-AVX2-NEXT: vzeroupper +; VTEST-AVX2-NEXT: retq +; +; MOVMSK-AVX1-LABEL: movmskps_sext_v8i32: +; MOVMSK-AVX1: # %bb.0: +; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm1 +; MOVMSK-AVX1-NEXT: vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3] +; MOVMSK-AVX1-NEXT: vpmovsxwd %xmm0, %xmm0 +; MOVMSK-AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 +; MOVMSK-AVX1-NEXT: vmovmskps %ymm0, %eax +; MOVMSK-AVX1-NEXT: vzeroupper +; MOVMSK-AVX1-NEXT: retq +; +; MOVMSK-AVX2-LABEL: movmskps_sext_v8i32: +; MOVMSK-AVX2: # %bb.0: +; MOVMSK-AVX2-NEXT: vpmovsxwd %xmm0, %ymm0 +; MOVMSK-AVX2-NEXT: vmovmskps %ymm0, %eax +; MOVMSK-AVX2-NEXT: vzeroupper +; MOVMSK-AVX2-NEXT: retq %1 = sext <8 x i16> %a0 to <8 x i32> %2 = bitcast <8 x i32> %1 to <8 x float> %3 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %2) @@ -192,23 +230,23 @@ define i32 @movmskps_sext_v8i32(<8 x i16> %a0) { } define i32 @movmskps_concat_v4f32(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: movmskps_concat_v4f32: -; CHECK: # %bb.0: -; CHECK-NEXT: vorps %xmm1, %xmm0, %xmm0 -; CHECK-NEXT: xorl %eax, %eax -; CHECK-NEXT: vtestps %xmm0, %xmm0 -; CHECK-NEXT: setne %al -; CHECK-NEXT: negl %eax -; CHECK-NEXT: retq +; VTEST-LABEL: movmskps_concat_v4f32: +; VTEST: # %bb.0: +; VTEST-NEXT: vorps %xmm1, %xmm0, %xmm0 +; VTEST-NEXT: xorl %eax, %eax +; VTEST-NEXT: vtestps %xmm0, %xmm0 +; VTEST-NEXT: setne %al +; VTEST-NEXT: negl %eax +; VTEST-NEXT: retq ; -; ADL-LABEL: movmskps_concat_v4f32: -; ADL: # %bb.0: -; ADL-NEXT: vorps %xmm1, %xmm0, %xmm0 -; ADL-NEXT: vmovmskps %xmm0, %ecx -; ADL-NEXT: xorl %eax, %eax -; ADL-NEXT: negl %ecx -; ADL-NEXT: sbbl %eax, %eax -; ADL-NEXT: retq +; MOVMSK-LABEL: movmskps_concat_v4f32: +; MOVMSK: # %bb.0: +; MOVMSK-NEXT: vorps %xmm1, %xmm0, %xmm0 +; MOVMSK-NEXT: vmovmskps %xmm0, %ecx +; MOVMSK-NEXT: xorl %eax, %eax +; MOVMSK-NEXT: negl %ecx +; MOVMSK-NEXT: sbbl %eax, %eax +; MOVMSK-NEXT: retq %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> %2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1) %3 = icmp ne i32 %2, 0 @@ -225,15 +263,6 @@ define i32 @movmskps_demanded_concat_v4f32(<4 x float> %a0, <4 x float> %a1) { ; CHECK-NEXT: negl %ecx ; CHECK-NEXT: sbbl %eax, %eax ; CHECK-NEXT: retq -; -; ADL-LABEL: movmskps_demanded_concat_v4f32: -; ADL: # %bb.0: -; ADL-NEXT: vmovmskps %xmm0, %ecx -; ADL-NEXT: andl $3, %ecx -; ADL-NEXT: xorl %eax, %eax -; ADL-NEXT: negl %ecx -; ADL-NEXT: sbbl %eax, %eax -; ADL-NEXT: retq %1 = shufflevector <4 x float> %a0, <4 x float> %a1, <8 x i32> %2 = tail call i32 @llvm.x86.avx.movmsk.ps.256(<8 x float> %1) %3 = and i32 %2, 3 diff --git a/llvm/test/CodeGen/X86/ctpop-mask.ll b/llvm/test/CodeGen/X86/ctpop-mask.ll index abbcf22f77e433ea64329f54df1105e1b0d89a66..e0a96a9f9887917f1e658d498b09fe4c9a2dcf8a 100644 --- a/llvm/test/CodeGen/X86/ctpop-mask.ll +++ b/llvm/test/CodeGen/X86/ctpop-mask.ll @@ -25,7 +25,7 @@ define i64 @ctpop_mask2(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_mask2: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $3, %edi -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_mask2: @@ -189,7 +189,7 @@ define i64 @ctpop_mask4(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_mask4: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $15, %edi -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_mask4: @@ -271,7 +271,7 @@ define i64 @ctpop_mask5(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_mask5: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $31, %edi -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_mask5: @@ -392,7 +392,7 @@ define i64 @ctpop_shifted_mask6(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_shifted_mask6: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $26112, %edi # imm = 0x6600 -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_shifted_mask6: @@ -556,7 +556,7 @@ define i64 @ctpop_shifted_mask8(i64 %x) nounwind readnone { ; X64-POPCOUNT-LABEL: ctpop_shifted_mask8: ; X64-POPCOUNT: # %bb.0: ; X64-POPCOUNT-NEXT: andl $65280, %edi # imm = 0xFF00 -; X64-POPCOUNT-NEXT: popcntq %rdi, %rax +; X64-POPCOUNT-NEXT: popcntl %edi, %eax ; X64-POPCOUNT-NEXT: retq ; ; X86-NO-POPCOUNT-LABEL: ctpop_shifted_mask8: diff --git a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll index c6ad2171aa8955800954b889010295bb1004b48a..b9ef3154cd1c3a8dd4c2fefbeb56fa812d39b314 100644 --- a/llvm/test/CodeGen/X86/fast-isel-fcmp.ll +++ b/llvm/test/CodeGen/X86/fast-isel-fcmp.ll @@ -16,21 +16,19 @@ define zeroext i1 @fcmp_oeq(float %x, float %y) { ; FAST_NOAVX-LABEL: fcmp_oeq: ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: sete %al -; FAST_NOAVX-NEXT: setnp %cl -; FAST_NOAVX-NEXT: andb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: sete %cl +; FAST_NOAVX-NEXT: setnp %al +; FAST_NOAVX-NEXT: andb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oeq: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: sete %al -; FAST_AVX-NEXT: setnp %cl -; FAST_AVX-NEXT: andb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: sete %cl +; FAST_AVX-NEXT: setnp %al +; FAST_AVX-NEXT: andb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp oeq float %x, %y ret i1 %1 @@ -48,7 +46,6 @@ define zeroext i1 @fcmp_ogt(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ogt: @@ -56,7 +53,6 @@ define zeroext i1 @fcmp_ogt(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ogt float %x, %y ret i1 %1 @@ -74,7 +70,6 @@ define zeroext i1 @fcmp_oge(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oge: @@ -82,7 +77,6 @@ define zeroext i1 @fcmp_oge(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oge float %x, %y ret i1 %1 @@ -100,7 +94,6 @@ define zeroext i1 @fcmp_olt(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_olt: @@ -108,7 +101,6 @@ define zeroext i1 @fcmp_olt(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp olt float %x, %y ret i1 %1 @@ -126,7 +118,6 @@ define zeroext i1 @fcmp_ole(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ole: @@ -134,7 +125,6 @@ define zeroext i1 @fcmp_ole(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ole float %x, %y ret i1 %1 @@ -152,7 +142,6 @@ define zeroext i1 @fcmp_one(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setne %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_one: @@ -160,7 +149,6 @@ define zeroext i1 @fcmp_one(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setne %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp one float %x, %y ret i1 %1 @@ -178,7 +166,6 @@ define zeroext i1 @fcmp_ord(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ord: @@ -186,7 +173,6 @@ define zeroext i1 @fcmp_ord(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ord float %x, %y ret i1 %1 @@ -204,7 +190,6 @@ define zeroext i1 @fcmp_uno(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uno: @@ -212,7 +197,6 @@ define zeroext i1 @fcmp_uno(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uno float %x, %y ret i1 %1 @@ -230,7 +214,6 @@ define zeroext i1 @fcmp_ueq(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: sete %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ueq: @@ -238,7 +221,6 @@ define zeroext i1 @fcmp_ueq(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: sete %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ueq float %x, %y ret i1 %1 @@ -256,7 +238,6 @@ define zeroext i1 @fcmp_ugt(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ugt: @@ -264,7 +245,6 @@ define zeroext i1 @fcmp_ugt(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ugt float %x, %y ret i1 %1 @@ -282,7 +262,6 @@ define zeroext i1 @fcmp_uge(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uge: @@ -290,7 +269,6 @@ define zeroext i1 @fcmp_uge(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uge float %x, %y ret i1 %1 @@ -308,7 +286,6 @@ define zeroext i1 @fcmp_ult(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ult: @@ -316,7 +293,6 @@ define zeroext i1 @fcmp_ult(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ult float %x, %y ret i1 %1 @@ -334,7 +310,6 @@ define zeroext i1 @fcmp_ule(float %x, float %y) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ule: @@ -342,7 +317,6 @@ define zeroext i1 @fcmp_ule(float %x, float %y) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ule float %x, %y ret i1 %1 @@ -360,21 +334,19 @@ define zeroext i1 @fcmp_une(float %x, float %y) { ; FAST_NOAVX-LABEL: fcmp_une: ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: setne %al -; FAST_NOAVX-NEXT: setp %cl -; FAST_NOAVX-NEXT: orb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: setne %cl +; FAST_NOAVX-NEXT: setp %al +; FAST_NOAVX-NEXT: orb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_une: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: setne %al -; FAST_AVX-NEXT: setp %cl -; FAST_AVX-NEXT: orb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: setne %cl +; FAST_AVX-NEXT: setp %al +; FAST_AVX-NEXT: orb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp une float %x, %y ret i1 %1 @@ -392,7 +364,6 @@ define zeroext i1 @icmp_eq(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: sete %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp eq i32 %x, %y ret i1 %1 @@ -410,7 +381,6 @@ define zeroext i1 @icmp_ne(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setne %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ne i32 %x, %y ret i1 %1 @@ -428,7 +398,6 @@ define zeroext i1 @icmp_ugt(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: seta %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ugt i32 %x, %y ret i1 %1 @@ -446,7 +415,6 @@ define zeroext i1 @icmp_uge(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setae %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp uge i32 %x, %y ret i1 %1 @@ -464,7 +432,6 @@ define zeroext i1 @icmp_ult(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setb %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ult i32 %x, %y ret i1 %1 @@ -482,7 +449,6 @@ define zeroext i1 @icmp_ule(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setbe %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp ule i32 %x, %y ret i1 %1 @@ -500,7 +466,6 @@ define zeroext i1 @icmp_sgt(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setg %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp sgt i32 %x, %y ret i1 %1 @@ -518,7 +483,6 @@ define zeroext i1 @icmp_sge(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setge %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp sge i32 %x, %y ret i1 %1 @@ -536,7 +500,6 @@ define zeroext i1 @icmp_slt(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setl %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp slt i32 %x, %y ret i1 %1 @@ -554,7 +517,6 @@ define zeroext i1 @icmp_sle(i32 %x, i32 %y) { ; FAST-NEXT: cmpl %esi, %edi ; FAST-NEXT: setle %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = icmp sle i32 %x, %y ret i1 %1 @@ -573,7 +535,6 @@ define zeroext i1 @fcmp_oeq2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oeq2: @@ -581,7 +542,6 @@ define zeroext i1 @fcmp_oeq2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oeq float %x, %x ret i1 %1 @@ -601,22 +561,20 @@ define zeroext i1 @fcmp_oeq3(float %x) { ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: xorps %xmm1, %xmm1 ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: sete %al -; FAST_NOAVX-NEXT: setnp %cl -; FAST_NOAVX-NEXT: andb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: sete %cl +; FAST_NOAVX-NEXT: setnp %al +; FAST_NOAVX-NEXT: andb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oeq3: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: sete %al -; FAST_AVX-NEXT: setnp %cl -; FAST_AVX-NEXT: andb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: sete %cl +; FAST_AVX-NEXT: setnp %al +; FAST_AVX-NEXT: andb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp oeq float %x, 0.000000e+00 ret i1 %1 @@ -632,7 +590,7 @@ define zeroext i1 @fcmp_ogt2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %1 = fcmp ogt float %x, %x ret i1 %1 @@ -652,7 +610,6 @@ define zeroext i1 @fcmp_ogt3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ogt3: @@ -661,7 +618,6 @@ define zeroext i1 @fcmp_ogt3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ogt float %x, 0.000000e+00 ret i1 %1 @@ -679,7 +635,6 @@ define zeroext i1 @fcmp_oge2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oge2: @@ -687,7 +642,6 @@ define zeroext i1 @fcmp_oge2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oge float %x, %x ret i1 %1 @@ -707,7 +661,6 @@ define zeroext i1 @fcmp_oge3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_oge3: @@ -716,7 +669,6 @@ define zeroext i1 @fcmp_oge3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp oge float %x, 0.000000e+00 ret i1 %1 @@ -732,7 +684,7 @@ define zeroext i1 @fcmp_olt2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %1 = fcmp olt float %x, %x ret i1 %1 @@ -752,7 +704,6 @@ define zeroext i1 @fcmp_olt3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: seta %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_olt3: @@ -761,7 +712,6 @@ define zeroext i1 @fcmp_olt3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: seta %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp olt float %x, 0.000000e+00 ret i1 %1 @@ -779,7 +729,6 @@ define zeroext i1 @fcmp_ole2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ole2: @@ -787,7 +736,6 @@ define zeroext i1 @fcmp_ole2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ole float %x, %x ret i1 %1 @@ -807,7 +755,6 @@ define zeroext i1 @fcmp_ole3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setae %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ole3: @@ -816,7 +763,6 @@ define zeroext i1 @fcmp_ole3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setae %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ole float %x, 0.000000e+00 ret i1 %1 @@ -832,7 +778,7 @@ define zeroext i1 @fcmp_one2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %1 = fcmp one float %x, %x ret i1 %1 @@ -852,7 +798,6 @@ define zeroext i1 @fcmp_one3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setne %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_one3: @@ -861,7 +806,6 @@ define zeroext i1 @fcmp_one3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setne %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp one float %x, 0.000000e+00 ret i1 %1 @@ -879,7 +823,6 @@ define zeroext i1 @fcmp_ord2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ord2: @@ -887,7 +830,6 @@ define zeroext i1 @fcmp_ord2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ord float %x, %x ret i1 %1 @@ -905,7 +847,6 @@ define zeroext i1 @fcmp_ord3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setnp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ord3: @@ -913,7 +854,6 @@ define zeroext i1 @fcmp_ord3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setnp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ord float %x, 0.000000e+00 ret i1 %1 @@ -931,7 +871,6 @@ define zeroext i1 @fcmp_uno2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uno2: @@ -939,7 +878,6 @@ define zeroext i1 @fcmp_uno2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uno float %x, %x ret i1 %1 @@ -957,7 +895,6 @@ define zeroext i1 @fcmp_uno3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uno3: @@ -965,7 +902,6 @@ define zeroext i1 @fcmp_uno3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uno float %x, 0.000000e+00 ret i1 %1 @@ -981,7 +917,6 @@ define zeroext i1 @fcmp_ueq2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = fcmp ueq float %x, %x ret i1 %1 @@ -1001,7 +936,6 @@ define zeroext i1 @fcmp_ueq3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: sete %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ueq3: @@ -1010,7 +944,6 @@ define zeroext i1 @fcmp_ueq3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: sete %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ueq float %x, 0.000000e+00 ret i1 %1 @@ -1028,7 +961,6 @@ define zeroext i1 @fcmp_ugt2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ugt2: @@ -1036,7 +968,6 @@ define zeroext i1 @fcmp_ugt2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ugt float %x, %x ret i1 %1 @@ -1056,7 +987,6 @@ define zeroext i1 @fcmp_ugt3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ugt3: @@ -1065,7 +995,6 @@ define zeroext i1 @fcmp_ugt3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ugt float %x, 0.000000e+00 ret i1 %1 @@ -1081,7 +1010,6 @@ define zeroext i1 @fcmp_uge2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = fcmp uge float %x, %x ret i1 %1 @@ -1101,7 +1029,6 @@ define zeroext i1 @fcmp_uge3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm1 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_uge3: @@ -1110,7 +1037,6 @@ define zeroext i1 @fcmp_uge3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm1 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp uge float %x, 0.000000e+00 ret i1 %1 @@ -1128,7 +1054,6 @@ define zeroext i1 @fcmp_ult2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ult2: @@ -1136,7 +1061,6 @@ define zeroext i1 @fcmp_ult2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ult float %x, %x ret i1 %1 @@ -1156,7 +1080,6 @@ define zeroext i1 @fcmp_ult3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setb %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ult3: @@ -1165,7 +1088,6 @@ define zeroext i1 @fcmp_ult3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setb %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ult float %x, 0.000000e+00 ret i1 %1 @@ -1181,7 +1103,6 @@ define zeroext i1 @fcmp_ule2(float %x) { ; FAST: ## %bb.0: ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %1 = fcmp ule float %x, %x ret i1 %1 @@ -1201,7 +1122,6 @@ define zeroext i1 @fcmp_ule3(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 ; FAST_NOAVX-NEXT: setbe %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_ule3: @@ -1210,7 +1130,6 @@ define zeroext i1 @fcmp_ule3(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 ; FAST_AVX-NEXT: setbe %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp ule float %x, 0.000000e+00 ret i1 %1 @@ -1228,7 +1147,6 @@ define zeroext i1 @fcmp_une2(float %x) { ; FAST_NOAVX-NEXT: ucomiss %xmm0, %xmm0 ; FAST_NOAVX-NEXT: setp %al ; FAST_NOAVX-NEXT: andb $1, %al -; FAST_NOAVX-NEXT: movzbl %al, %eax ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_une2: @@ -1236,7 +1154,6 @@ define zeroext i1 @fcmp_une2(float %x) { ; FAST_AVX-NEXT: vucomiss %xmm0, %xmm0 ; FAST_AVX-NEXT: setp %al ; FAST_AVX-NEXT: andb $1, %al -; FAST_AVX-NEXT: movzbl %al, %eax ; FAST_AVX-NEXT: retq %1 = fcmp une float %x, %x ret i1 %1 @@ -1256,22 +1173,20 @@ define zeroext i1 @fcmp_une3(float %x) { ; FAST_NOAVX: ## %bb.0: ; FAST_NOAVX-NEXT: xorps %xmm1, %xmm1 ; FAST_NOAVX-NEXT: ucomiss %xmm1, %xmm0 -; FAST_NOAVX-NEXT: setne %al -; FAST_NOAVX-NEXT: setp %cl -; FAST_NOAVX-NEXT: orb %al, %cl -; FAST_NOAVX-NEXT: andb $1, %cl -; FAST_NOAVX-NEXT: movzbl %cl, %eax +; FAST_NOAVX-NEXT: setne %cl +; FAST_NOAVX-NEXT: setp %al +; FAST_NOAVX-NEXT: orb %cl, %al +; FAST_NOAVX-NEXT: andb $1, %al ; FAST_NOAVX-NEXT: retq ; ; FAST_AVX-LABEL: fcmp_une3: ; FAST_AVX: ## %bb.0: ; FAST_AVX-NEXT: vxorps %xmm1, %xmm1, %xmm1 ; FAST_AVX-NEXT: vucomiss %xmm1, %xmm0 -; FAST_AVX-NEXT: setne %al -; FAST_AVX-NEXT: setp %cl -; FAST_AVX-NEXT: orb %al, %cl -; FAST_AVX-NEXT: andb $1, %cl -; FAST_AVX-NEXT: movzbl %cl, %eax +; FAST_AVX-NEXT: setne %cl +; FAST_AVX-NEXT: setp %al +; FAST_AVX-NEXT: orb %cl, %al +; FAST_AVX-NEXT: andb $1, %al ; FAST_AVX-NEXT: retq %1 = fcmp une float %x, 0.000000e+00 ret i1 %1 diff --git a/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll b/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll index cd3439fcddc5f67b4d229c5057ac7aa5238ac17b..0341694fe826baca98bb43f97392074ec652d265 100644 --- a/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll +++ b/llvm/test/CodeGen/X86/fast-isel-ret-ext.ll @@ -34,5 +34,5 @@ define zeroext i1 @test5(i32 %y) nounwind { ret i1 %conv ; CHECK-LABEL: test5: ; CHECK: andb $1 - ; CHECK: movzbl {{.*}}, %eax + ; CHECK-NEXT: ret } diff --git a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll index ae046be9a508326cd71c3398d7e383e676713b94..f91c4ad0e8e3434af10c18b3c56f7451a7e14c41 100644 --- a/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll +++ b/llvm/test/CodeGen/X86/keylocker-intrinsics-fast-isel.ll @@ -119,7 +119,6 @@ entry: define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesenc256kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesenc256kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -127,7 +126,6 @@ define zeroext i8 @test_mm_aesenc256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesenc256kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesenc256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xde,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -143,7 +141,6 @@ entry: define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesdec256kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdec256kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -151,7 +148,6 @@ define zeroext i8 @test_mm_aesdec256kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesdec256kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdec256kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdf,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -167,7 +163,6 @@ entry: define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesenc128kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesenc128kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -175,7 +170,6 @@ define zeroext i8 @test_mm_aesenc128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesenc128kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesenc128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdc,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -191,7 +185,6 @@ entry: define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) { ; CHECK-LABEL: test_mm_aesdec128kl_u8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdec128kl (%rsi), %xmm0 ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -199,7 +192,6 @@ define zeroext i8 @test_mm_aesdec128kl_u8(ptr %odata, <2 x i64> %idata, ptr %h) ; ; EGPR-LABEL: test_mm_aesdec128kl_u8: ; EGPR: # %bb.0: # %entry -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdec128kl (%rsi), %xmm0 # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xdd,0x06] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -223,7 +215,6 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesencwide128kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -246,7 +237,6 @@ define zeroext i8 @test__mm_aesencwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesencwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x02] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -313,7 +303,6 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdecwide128kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -336,7 +325,6 @@ define zeroext i8 @test__mm_aesdecwide128kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdecwide128kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x0a] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -403,7 +391,6 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesencwide256kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -426,7 +413,6 @@ define zeroext i8 @test__mm_aesencwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesencwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x12] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] @@ -493,7 +479,6 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; CHECK-NEXT: movaps 80(%rsi), %xmm5 ; CHECK-NEXT: movaps 96(%rsi), %xmm6 ; CHECK-NEXT: movaps 112(%rsi), %xmm7 -; CHECK-NEXT: xorl %eax, %eax ; CHECK-NEXT: aesdecwide256kl (%rdx) ; CHECK-NEXT: sete %al ; CHECK-NEXT: movaps %xmm0, (%rdi) @@ -516,7 +501,6 @@ define zeroext i8 @test__mm_aesdecwide256kl_u8(ptr %odata, ptr %idata, ptr %h) { ; EGPR-NEXT: movaps 80(%rsi), %xmm5 # encoding: [0x0f,0x28,0x6e,0x50] ; EGPR-NEXT: movaps 96(%rsi), %xmm6 # encoding: [0x0f,0x28,0x76,0x60] ; EGPR-NEXT: movaps 112(%rsi), %xmm7 # encoding: [0x0f,0x28,0x7e,0x70] -; EGPR-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; EGPR-NEXT: aesdecwide256kl (%rdx) # EVEX TO LEGACY Compression encoding: [0xf3,0x0f,0x38,0xd8,0x1a] ; EGPR-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; EGPR-NEXT: movaps %xmm0, (%rdi) # encoding: [0x0f,0x29,0x07] diff --git a/llvm/test/CodeGen/X86/lzcnt-cmp.ll b/llvm/test/CodeGen/X86/lzcnt-cmp.ll index c1cce6f5d8ca10dbfc818972d862a91ee5b9243a..6c8d5c9d55a6d55eaaaf98b908eeae8518e70189 100644 --- a/llvm/test/CodeGen/X86/lzcnt-cmp.ll +++ b/llvm/test/CodeGen/X86/lzcnt-cmp.ll @@ -50,35 +50,33 @@ define i1 @lshr_ctlz_undef_cmpeq_one_i64(i64 %in) nounwind { ; X86-BSR-NEXT: xorl $31, %eax ; X86-BSR-NEXT: addl $32, %eax ; X86-BSR-NEXT: .LBB1_2: -; X86-BSR-NEXT: testl $-64, %eax -; X86-BSR-NEXT: setne %al +; X86-BSR-NEXT: shrl $6, %eax +; X86-BSR-NEXT: # kill: def $al killed $al killed $eax ; X86-BSR-NEXT: retl ; ; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; X86-LZCNT: # %bb.0: -; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax -; X86-LZCNT-NEXT: addl $32, %eax -; X86-LZCNT-NEXT: xorl %ecx, %ecx +; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %ecx +; X86-LZCNT-NEXT: addl $32, %ecx +; X86-LZCNT-NEXT: xorl %eax, %eax ; X86-LZCNT-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-LZCNT-NEXT: cmovel %eax, %ecx -; X86-LZCNT-NEXT: testb $64, %cl -; X86-LZCNT-NEXT: setne %al +; X86-LZCNT-NEXT: cmovel %ecx, %eax +; X86-LZCNT-NEXT: shrl $6, %eax +; X86-LZCNT-NEXT: # kill: def $al killed $al killed $eax ; X86-LZCNT-NEXT: retl ; ; X64-BSR-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; X64-BSR: # %bb.0: ; X64-BSR-NEXT: bsrq %rdi, %rax ; X64-BSR-NEXT: shrl $6, %eax -; X64-BSR-NEXT: cmpl $1, %eax -; X64-BSR-NEXT: sete %al +; X64-BSR-NEXT: # kill: def $al killed $al killed $rax ; X64-BSR-NEXT: retq ; ; X64-LZCNT-LABEL: lshr_ctlz_undef_cmpeq_one_i64: ; X64-LZCNT: # %bb.0: ; X64-LZCNT-NEXT: lzcntq %rdi, %rax ; X64-LZCNT-NEXT: shrl $6, %eax -; X64-LZCNT-NEXT: cmpl $1, %eax -; X64-LZCNT-NEXT: sete %al +; X64-LZCNT-NEXT: # kill: def $al killed $al killed $rax ; X64-LZCNT-NEXT: retq %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1) %lshr = lshr i64 %ctlz, 6 @@ -131,33 +129,33 @@ define i1 @lshr_ctlz_undef_cmpne_zero_i64(i64 %in) nounwind { ; X86-BSR-NEXT: xorl $31, %eax ; X86-BSR-NEXT: addl $32, %eax ; X86-BSR-NEXT: .LBB3_2: -; X86-BSR-NEXT: testl $-64, %eax -; X86-BSR-NEXT: setne %al +; X86-BSR-NEXT: shrl $6, %eax +; X86-BSR-NEXT: # kill: def $al killed $al killed $eax ; X86-BSR-NEXT: retl ; ; X86-LZCNT-LABEL: lshr_ctlz_undef_cmpne_zero_i64: ; X86-LZCNT: # %bb.0: -; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %eax -; X86-LZCNT-NEXT: addl $32, %eax -; X86-LZCNT-NEXT: xorl %ecx, %ecx +; X86-LZCNT-NEXT: lzcntl {{[0-9]+}}(%esp), %ecx +; X86-LZCNT-NEXT: addl $32, %ecx +; X86-LZCNT-NEXT: xorl %eax, %eax ; X86-LZCNT-NEXT: cmpl $0, {{[0-9]+}}(%esp) -; X86-LZCNT-NEXT: cmovel %eax, %ecx -; X86-LZCNT-NEXT: testb $64, %cl -; X86-LZCNT-NEXT: setne %al +; X86-LZCNT-NEXT: cmovel %ecx, %eax +; X86-LZCNT-NEXT: shrl $6, %eax +; X86-LZCNT-NEXT: # kill: def $al killed $al killed $eax ; X86-LZCNT-NEXT: retl ; ; X64-BSR-LABEL: lshr_ctlz_undef_cmpne_zero_i64: ; X64-BSR: # %bb.0: ; X64-BSR-NEXT: bsrq %rdi, %rax -; X64-BSR-NEXT: testl $-64, %eax -; X64-BSR-NEXT: setne %al +; X64-BSR-NEXT: shrl $6, %eax +; X64-BSR-NEXT: # kill: def $al killed $al killed $rax ; X64-BSR-NEXT: retq ; ; X64-LZCNT-LABEL: lshr_ctlz_undef_cmpne_zero_i64: ; X64-LZCNT: # %bb.0: ; X64-LZCNT-NEXT: lzcntq %rdi, %rax -; X64-LZCNT-NEXT: testb $64, %al -; X64-LZCNT-NEXT: setne %al +; X64-LZCNT-NEXT: shrl $6, %eax +; X64-LZCNT-NEXT: # kill: def $al killed $al killed $rax ; X64-LZCNT-NEXT: retq %ctlz = call i64 @llvm.ctlz.i64(i64 %in, i1 -1) %lshr = lshr i64 %ctlz, 6 diff --git a/llvm/test/CodeGen/X86/tls-models.ll b/llvm/test/CodeGen/X86/tls-models.ll index fc8e302338d9607ef0a71ce5f84d5e1fb7f74a2e..8de9de15a5f06ee5c88d5429995a65ecfaaddcef 100644 --- a/llvm/test/CodeGen/X86/tls-models.ll +++ b/llvm/test/CodeGen/X86/tls-models.ll @@ -5,6 +5,7 @@ ; Darwin always uses the same model. ; RUN: llc < %s -mtriple=x86_64-apple-darwin | FileCheck -check-prefix=DARWIN %s +; RUN: llc < %s -mtriple=x86_64-apple-darwin -code-model=large | FileCheck -check-prefix=DARWIN %s @external_gd = external thread_local global i32 @internal_gd = internal thread_local global i32 42 diff --git a/llvm/test/CodeGen/X86/umul_fix_sat.ll b/llvm/test/CodeGen/X86/umul_fix_sat.ll index 6b6845147e04391218a0e9e397da229a5de82e8a..8c7078c7263284361a1c1f1935cd4b03947dce12 100644 --- a/llvm/test/CodeGen/X86/umul_fix_sat.ll +++ b/llvm/test/CodeGen/X86/umul_fix_sat.ll @@ -517,15 +517,13 @@ define i64 @func8(i64 %x, i64 %y) nounwind { ; X86-NEXT: adcl $0, %ecx ; X86-NEXT: addl %ebp, %edx ; X86-NEXT: adcl $0, %ecx +; X86-NEXT: shldl $1, %edx, %ecx ; X86-NEXT: shrdl $31, %edx, %eax -; X86-NEXT: movl %edx, %esi -; X86-NEXT: shrl $31, %esi -; X86-NEXT: xorl %edi, %edi -; X86-NEXT: negl %esi -; X86-NEXT: sbbl %edi, %edi -; X86-NEXT: orl %edi, %eax -; X86-NEXT: shrdl $31, %ecx, %edx -; X86-NEXT: orl %edi, %edx +; X86-NEXT: testl $-2147483648, %edx # imm = 0x80000000 +; X86-NEXT: movl $-1, %edx +; X86-NEXT: cmovnel %edx, %eax +; X86-NEXT: cmovnel %edx, %ecx +; X86-NEXT: movl %ecx, %edx ; X86-NEXT: popl %esi ; X86-NEXT: popl %edi ; X86-NEXT: popl %ebx diff --git a/llvm/test/CodeGen/X86/xaluo.ll b/llvm/test/CodeGen/X86/xaluo.ll index 5796e485f63148e8861282f3db6f84239da21d59..c2a8002c949ce6651f46412466328f15896e6309 100644 --- a/llvm/test/CodeGen/X86/xaluo.ll +++ b/llvm/test/CodeGen/X86/xaluo.ll @@ -21,7 +21,6 @@ define zeroext i1 @saddoi8(i8 signext %v1, i8 signext %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movb %dil, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 %v2) %val = extractvalue {i8, i1} %t, 0 @@ -44,7 +43,6 @@ define zeroext i1 @saddoi16(i16 %v1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 %v2) %val = extractvalue {i16, i1} %t, 0 @@ -67,7 +65,6 @@ define zeroext i1 @saddoi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -90,7 +87,6 @@ define zeroext i1 @saddoi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -114,7 +110,6 @@ define zeroext i1 @saddoinci8(i8 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movb %dil, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i8, i1} @llvm.sadd.with.overflow.i8(i8 %v1, i8 1) %val = extractvalue {i8, i1} %t, 0 @@ -137,7 +132,6 @@ define zeroext i1 @saddoinci16(i16 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i16, i1} @llvm.sadd.with.overflow.i16(i16 %v1, i16 1) %val = extractvalue {i16, i1} %t, 0 @@ -160,7 +154,6 @@ define zeroext i1 @saddoinci32(i32 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 1) %val = extractvalue {i32, i1} %t, 0 @@ -183,7 +176,6 @@ define zeroext i1 @saddoinci64(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 1) %val = extractvalue {i64, i1} %t, 0 @@ -207,7 +199,6 @@ define zeroext i1 @saddoi64imm1(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 2, i64 %v1) %val = extractvalue {i64, i1} %t, 0 @@ -231,7 +222,6 @@ define zeroext i1 @saddoi64imm2(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -2147483648) %val = extractvalue {i64, i1} %t, 0 @@ -251,12 +241,11 @@ define zeroext i1 @saddoi64imm3(i64 %v1, ptr %res) { ; ; FAST-LABEL: saddoi64imm3: ; FAST: ## %bb.0: -; FAST-NEXT: movabsq $-21474836489, %rax ## imm = 0xFFFFFFFAFFFFFFF7 -; FAST-NEXT: addq %rdi, %rax -; FAST-NEXT: seto %cl -; FAST-NEXT: movq %rax, (%rsi) -; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movabsq $-21474836489, %rcx ## imm = 0xFFFFFFFAFFFFFFF7 +; FAST-NEXT: addq %rdi, %rcx +; FAST-NEXT: seto %al +; FAST-NEXT: movq %rcx, (%rsi) +; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 -21474836489) %val = extractvalue {i64, i1} %t, 0 @@ -279,7 +268,6 @@ define zeroext i1 @saddoi64imm4(i64 %v1, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483647) %val = extractvalue {i64, i1} %t, 0 @@ -298,12 +286,11 @@ define zeroext i1 @saddoi64imm5(i64 %v1, ptr %res) { ; ; FAST-LABEL: saddoi64imm5: ; FAST: ## %bb.0: -; FAST-NEXT: movl $2147483648, %eax ## imm = 0x80000000 -; FAST-NEXT: addq %rdi, %rax -; FAST-NEXT: seto %cl -; FAST-NEXT: movq %rax, (%rsi) -; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl $2147483648, %ecx ## imm = 0x80000000 +; FAST-NEXT: addq %rdi, %rcx +; FAST-NEXT: seto %al +; FAST-NEXT: movq %rcx, (%rsi) +; FAST-NEXT: andb $1, %al ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 2147483648) %val = extractvalue {i64, i1} %t, 0 @@ -327,7 +314,6 @@ define zeroext i1 @uaddoi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -350,7 +336,6 @@ define zeroext i1 @uaddoi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -374,7 +359,6 @@ define zeroext i1 @uaddoinci8(i8 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movb %dil, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i8, i1} @llvm.uadd.with.overflow.i8(i8 %v1, i8 1) %val = extractvalue {i8, i1} %t, 0 @@ -397,7 +381,6 @@ define zeroext i1 @uaddoinci16(i16 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movw %di, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i16, i1} @llvm.uadd.with.overflow.i16(i16 %v1, i16 1) %val = extractvalue {i16, i1} %t, 0 @@ -420,7 +403,6 @@ define zeroext i1 @uaddoinci32(i32 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movl %edi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 1) %val = extractvalue {i32, i1} %t, 0 @@ -443,7 +425,6 @@ define zeroext i1 @uaddoinci64(i64 %v1, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movq %rdi, (%rsi) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 1) %val = extractvalue {i64, i1} %t, 0 @@ -467,7 +448,6 @@ define zeroext i1 @ssuboi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -490,7 +470,6 @@ define zeroext i1 @ssuboi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -514,7 +493,6 @@ define zeroext i1 @usuboi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -537,7 +515,6 @@ define zeroext i1 @usuboi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: setb %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -679,12 +656,11 @@ define zeroext i1 @saddobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB31_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.sadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -717,12 +693,11 @@ define zeroext i1 @saddobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB32_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.sadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -755,12 +730,11 @@ define zeroext i1 @uaddobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB33_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -793,12 +767,11 @@ define zeroext i1 @uaddobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB34_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.uadd.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -831,12 +804,11 @@ define zeroext i1 @ssubobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB35_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.ssub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -869,12 +841,11 @@ define zeroext i1 @ssubobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB36_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.ssub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 @@ -907,12 +878,11 @@ define zeroext i1 @usubobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB37_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i32, i1} @llvm.usub.with.overflow.i32(i32 %v1, i32 %v2) %val = extractvalue {i32, i1} %t, 0 @@ -945,12 +915,11 @@ define zeroext i1 @usubobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: ## %bb.2: ## %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: LBB38_1: ## %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: ## kill: def $al killed $al killed $eax ; FAST-NEXT: retq %t = call {i64, i1} @llvm.usub.with.overflow.i64(i64 %v1, i64 %v2) %val = extractvalue {i64, i1} %t, 0 diff --git a/llvm/test/CodeGen/X86/xmulo.ll b/llvm/test/CodeGen/X86/xmulo.ll index 6eb34b4e773e8fc022135acdfe3dbfce5a2c6016..2169b39b9dfa05428f48b3837abb48982e33d9fd 100644 --- a/llvm/test/CodeGen/X86/xmulo.ll +++ b/llvm/test/CodeGen/X86/xmulo.ll @@ -76,7 +76,7 @@ define zeroext i1 @smuloi8(i8 %v1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi8: @@ -118,7 +118,6 @@ define zeroext i1 @smuloi16(i16 %v1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi16: @@ -157,7 +156,6 @@ define zeroext i1 @smuloi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi32: @@ -196,7 +194,6 @@ define zeroext i1 @smuloi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi64: @@ -306,7 +303,7 @@ define zeroext i1 @umuloi8(i8 %v1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi8: @@ -355,7 +352,7 @@ define zeroext i1 @umuloi16(i16 %v1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movw %ax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi16: @@ -404,7 +401,7 @@ define zeroext i1 @umuloi32(i32 %v1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movl %eax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi32: @@ -453,7 +450,7 @@ define zeroext i1 @umuloi64(i64 %v1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movq %rax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi64: @@ -779,12 +776,11 @@ define zeroext i1 @smulobri8(i8 %v1, i8 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB15_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri8: @@ -843,12 +839,11 @@ define zeroext i1 @smulobri16(i16 %v1, i16 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB16_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri16: @@ -904,12 +899,11 @@ define zeroext i1 @smulobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB17_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri32: @@ -965,12 +959,11 @@ define zeroext i1 @smulobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB18_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smulobri64: @@ -1094,12 +1087,11 @@ define zeroext i1 @umulobri8(i8 %v1, i8 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB19_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri8: @@ -1162,12 +1154,11 @@ define zeroext i1 @umulobri16(i16 %v1, i16 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB20_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri16: @@ -1226,12 +1217,11 @@ define zeroext i1 @umulobri32(i32 %v1, i32 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB21_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri32: @@ -1290,12 +1280,11 @@ define zeroext i1 @umulobri64(i64 %v1, i64 %v2) { ; FAST-NEXT: # %bb.2: # %continue ; FAST-NEXT: movb $1, %al ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; FAST-NEXT: .LBB22_1: # %overflow ; FAST-NEXT: xorl %eax, %eax ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax +; FAST-NEXT: # kill: def $al killed $al killed $eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umulobri64: @@ -1422,7 +1411,7 @@ define zeroext i1 @smuloi8_load(ptr %ptr1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi8_load: @@ -1471,7 +1460,7 @@ define zeroext i1 @smuloi8_load2(i8 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi8_load2: @@ -1515,7 +1504,6 @@ define zeroext i1 @smuloi16_load(ptr %ptr1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %si, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi16_load: @@ -1556,7 +1544,6 @@ define zeroext i1 @smuloi16_load2(i16 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movw %di, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi16_load2: @@ -1597,7 +1584,6 @@ define zeroext i1 @smuloi32_load(ptr %ptr1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %esi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi32_load: @@ -1638,7 +1624,6 @@ define zeroext i1 @smuloi32_load2(i32 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movl %edi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi32_load2: @@ -1679,7 +1664,6 @@ define zeroext i1 @smuloi64_load(ptr %ptr1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rsi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi64_load: @@ -1789,7 +1773,6 @@ define zeroext i1 @smuloi64_load2(i64 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %al ; FAST-NEXT: movq %rdi, (%rdx) ; FAST-NEXT: andb $1, %al -; FAST-NEXT: movzbl %al, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: smuloi64_load2: @@ -1898,7 +1881,7 @@ define zeroext i1 @umuloi8_load(ptr %ptr1, i8 %v2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi8_load: @@ -1947,7 +1930,7 @@ define zeroext i1 @umuloi8_load2(i8 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %cl ; FAST-NEXT: movb %al, (%rdx) ; FAST-NEXT: andb $1, %cl -; FAST-NEXT: movzbl %cl, %eax +; FAST-NEXT: movl %ecx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi8_load2: @@ -1997,7 +1980,7 @@ define zeroext i1 @umuloi16_load(ptr %ptr1, i16 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movw %ax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi16_load: @@ -2050,7 +2033,7 @@ define zeroext i1 @umuloi16_load2(i16 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movw %ax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi16_load2: @@ -2101,7 +2084,7 @@ define zeroext i1 @umuloi32_load(ptr %ptr1, i32 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movl %eax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi32_load: @@ -2152,7 +2135,7 @@ define zeroext i1 @umuloi32_load2(i32 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movl %eax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi32_load2: @@ -2203,7 +2186,7 @@ define zeroext i1 @umuloi64_load(ptr %ptr1, i64 %v2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movq %rax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi64_load: @@ -2280,7 +2263,7 @@ define zeroext i1 @umuloi64_load2(i64 %v1, ptr %ptr2, ptr %res) { ; FAST-NEXT: seto %dl ; FAST-NEXT: movq %rax, (%rcx) ; FAST-NEXT: andb $1, %dl -; FAST-NEXT: movzbl %dl, %eax +; FAST-NEXT: movl %edx, %eax ; FAST-NEXT: retq ; ; WIN64-LABEL: umuloi64_load2: diff --git a/llvm/test/CodeGen/X86/xor.ll b/llvm/test/CodeGen/X86/xor.ll index 2072568b7ba75dd5aca71b6a5f8838309ab856fb..8c8b7cc516105606a107648738d32cc415ef6a7d 100644 --- a/llvm/test/CodeGen/X86/xor.ll +++ b/llvm/test/CodeGen/X86/xor.ll @@ -403,14 +403,19 @@ define i32 @PR17487(i1 %tobool) { ; ; X64-LIN-LABEL: PR17487: ; X64-LIN: # %bb.0: -; X64-LIN-NEXT: movl %edi, %eax -; X64-LIN-NEXT: andl $1, %eax +; X64-LIN-NEXT: movd %edi, %xmm0 +; X64-LIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; X64-LIN-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; X64-LIN-NEXT: pextrw $4, %xmm0, %eax ; X64-LIN-NEXT: retq ; ; X64-WIN-LABEL: PR17487: ; X64-WIN: # %bb.0: -; X64-WIN-NEXT: andb $1, %cl ; X64-WIN-NEXT: movzbl %cl, %eax +; X64-WIN-NEXT: movd %eax, %xmm0 +; X64-WIN-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,1,0,1] +; X64-WIN-NEXT: pand __xmm@00000000000000010000000000000001(%rip), %xmm0 +; X64-WIN-NEXT: pextrw $4, %xmm0, %eax ; X64-WIN-NEXT: retq %tmp = insertelement <2 x i1> undef, i1 %tobool, i32 1 %tmp1 = zext <2 x i1> %tmp to <2 x i64> diff --git a/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir b/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir index 1b7159d5f07525923f5a91baf98f00e6a92d3178..be3d1c0007998ad59e64e2cd6a23aeeeb1a74723 100644 --- a/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir +++ b/llvm/test/DebugInfo/AArch64/asan-stack-vars.mir @@ -39,85 +39,85 @@ target triple = "arm64-apple-ios" %0 = type opaque - %struct._class_t = type { %struct._class_t*, %struct._class_t*, %struct._objc_cache*, i8* (i8*, i8*)**, %struct._class_ro_t* } + %struct._class_t = type { ptr, ptr, ptr, ptr, ptr } %struct._objc_cache = type opaque - %struct._class_ro_t = type { i32, i32, i32, i8*, i8*, %struct.__method_list_t*, %struct._objc_protocol_list*, %struct._ivar_list_t*, i8*, %struct._prop_list_t* } + %struct._class_ro_t = type { i32, i32, i32, ptr, ptr, ptr, ptr, ptr, ptr, ptr } %struct.__method_list_t = type { i32, i32, [0 x %struct._objc_method] } - %struct._objc_method = type { i8*, i8*, i8* } - %struct._objc_protocol_list = type { i64, [0 x %struct._protocol_t*] } - %struct._protocol_t = type { i8*, i8*, %struct._objc_protocol_list*, %struct.__method_list_t*, %struct.__method_list_t*, %struct.__method_list_t*, %struct.__method_list_t*, %struct._prop_list_t*, i32, i32, i8**, i8*, %struct._prop_list_t* } + %struct._objc_method = type { ptr, ptr, ptr } + %struct._objc_protocol_list = type { i64, [0 x ptr] } + %struct._protocol_t = type { ptr, ptr, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, ptr, ptr, ptr } %struct._ivar_list_t = type { i32, i32, [0 x %struct._ivar_t] } - %struct._ivar_t = type { i32*, i8*, i8*, i32, i32 } + %struct._ivar_t = type { ptr, ptr, ptr, i32, i32 } %struct._prop_list_t = type { i32, i32, [0 x %struct._prop_t] } - %struct._prop_t = type { i8*, i8* } + %struct._prop_t = type { ptr, ptr } %struct.CGSize = type { double, double } @"OBJC_CLASS_$_Object" = external global %struct._class_t - @"OBJC_CLASSLIST_REFERENCES_$_" = private global %struct._class_t* @"OBJC_CLASS_$_Object", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8 + @"OBJC_CLASSLIST_REFERENCES_$_" = private global ptr @"OBJC_CLASS_$_Object", section "__DATA, __objc_classrefs, regular, no_dead_strip", align 8 @OBJC_METH_VAR_NAME_ = private unnamed_addr constant [6 x i8] c"alloc\00", section "__TEXT,__objc_methname,cstring_literals", align 1 - @OBJC_SELECTOR_REFERENCES_ = private externally_initialized global i8* getelementptr inbounds ([6 x i8], [6 x i8]* @OBJC_METH_VAR_NAME_, i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip", align 8 + @OBJC_SELECTOR_REFERENCES_ = private externally_initialized global ptr @OBJC_METH_VAR_NAME_, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip", align 8 @OBJC_METH_VAR_NAME_.1 = private unnamed_addr constant [14 x i8] c"initWithSize:\00", section "__TEXT,__objc_methname,cstring_literals", align 1 - @OBJC_SELECTOR_REFERENCES_.2 = private externally_initialized global i8* getelementptr inbounds ([14 x i8], [14 x i8]* @OBJC_METH_VAR_NAME_.1, i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip", align 8 + @OBJC_SELECTOR_REFERENCES_.2 = private externally_initialized global ptr @OBJC_METH_VAR_NAME_.1, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip", align 8 @OBJC_METH_VAR_NAME_.3 = private unnamed_addr constant [9 x i8] c"aMessage\00", section "__TEXT,__objc_methname,cstring_literals", align 1 - @OBJC_SELECTOR_REFERENCES_.4 = private externally_initialized global i8* getelementptr inbounds ([9 x i8], [9 x i8]* @OBJC_METH_VAR_NAME_.3, i32 0, i32 0), section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip", align 8 + @OBJC_SELECTOR_REFERENCES_.4 = private externally_initialized global ptr @OBJC_METH_VAR_NAME_.3, section "__DATA, __objc_selrefs, literal_pointers, no_dead_strip", align 8 @_objc_empty_cache = external global %struct._objc_cache - @"OBJC_CLASS_$_MyObject" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_MyObject", %struct._class_t* null, %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** null, %struct._class_ro_t* @"\01l_OBJC_CLASS_RO_$_MyObject" }, section "__DATA, __objc_data", align 8 - @"OBJC_METACLASS_$_MyObject" = global %struct._class_t { %struct._class_t* @"OBJC_METACLASS_$_MyObject", %struct._class_t* @"OBJC_CLASS_$_MyObject", %struct._objc_cache* @_objc_empty_cache, i8* (i8*, i8*)** null, %struct._class_ro_t* @"\01l_OBJC_METACLASS_RO_$_MyObject" }, section "__DATA, __objc_data", align 8 + @"OBJC_CLASS_$_MyObject" = global %struct._class_t { ptr @"OBJC_METACLASS_$_MyObject", ptr null, ptr @_objc_empty_cache, ptr null, ptr @"\01l_OBJC_CLASS_RO_$_MyObject" }, section "__DATA, __objc_data", align 8 + @"OBJC_METACLASS_$_MyObject" = global %struct._class_t { ptr @"OBJC_METACLASS_$_MyObject", ptr @"OBJC_CLASS_$_MyObject", ptr @_objc_empty_cache, ptr null, ptr @"\01l_OBJC_METACLASS_RO_$_MyObject" }, section "__DATA, __objc_data", align 8 @OBJC_CLASS_NAME_ = private unnamed_addr constant [9 x i8] c"MyObject\00", section "__TEXT,__objc_classname,cstring_literals", align 1 @OBJC_METH_VAR_NAME_.5 = private unnamed_addr constant [12 x i8] c"doWithSize:\00", section "__TEXT,__objc_methname,cstring_literals", align 1 @OBJC_METH_VAR_TYPE_ = private unnamed_addr constant [21 x i8] c"@32@0:8{CGSize=dd}16\00", section "__TEXT,__objc_methtype,cstring_literals", align 1 - @"\01l_OBJC_$_CLASS_METHODS_MyObject" = private global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { i8* getelementptr inbounds ([12 x i8], [12 x i8]* @OBJC_METH_VAR_NAME_.5, i32 0, i32 0), i8* getelementptr inbounds ([21 x i8], [21 x i8]* @OBJC_METH_VAR_TYPE_, i32 0, i32 0), i8* bitcast (i8* (i8*, i8*, [2 x double])* @"\01+[MyObject doWithSize:]" to i8*) }] }, section "__DATA, __objc_const", align 8 - @"\01l_OBJC_METACLASS_RO_$_MyObject" = private global %struct._class_ro_t { i32 131, i32 40, i32 40, i8* null, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), %struct.__method_list_t* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_CLASS_METHODS_MyObject" to %struct.__method_list_t*), %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8 - @"\01l_OBJC_CLASS_RO_$_MyObject" = private global %struct._class_ro_t { i32 130, i32 0, i32 0, i8* null, i8* getelementptr inbounds ([9 x i8], [9 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), %struct.__method_list_t* null, %struct._objc_protocol_list* null, %struct._ivar_list_t* null, i8* null, %struct._prop_list_t* null }, section "__DATA, __objc_const", align 8 - @"OBJC_LABEL_CLASS_$" = private global [1 x i8*] [i8* bitcast (%struct._class_t* @"OBJC_CLASS_$_MyObject" to i8*)], section "__DATA, __objc_classlist, regular, no_dead_strip", align 8 - @llvm.compiler.used = appending global [12 x i8*] [i8* bitcast (%struct._class_t** @"OBJC_CLASSLIST_REFERENCES_$_" to i8*), i8* getelementptr inbounds ([6 x i8], [6 x i8]* @OBJC_METH_VAR_NAME_, i32 0, i32 0), i8* bitcast (i8** @OBJC_SELECTOR_REFERENCES_ to i8*), i8* getelementptr inbounds ([14 x i8], [14 x i8]* @OBJC_METH_VAR_NAME_.1, i32 0, i32 0), i8* bitcast (i8** @OBJC_SELECTOR_REFERENCES_.2 to i8*), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @OBJC_METH_VAR_NAME_.3, i32 0, i32 0), i8* bitcast (i8** @OBJC_SELECTOR_REFERENCES_.4 to i8*), i8* getelementptr inbounds ([9 x i8], [9 x i8]* @OBJC_CLASS_NAME_, i32 0, i32 0), i8* getelementptr inbounds ([12 x i8], [12 x i8]* @OBJC_METH_VAR_NAME_.5, i32 0, i32 0), i8* getelementptr inbounds ([21 x i8], [21 x i8]* @OBJC_METH_VAR_TYPE_, i32 0, i32 0), i8* bitcast ({ i32, i32, [1 x %struct._objc_method] }* @"\01l_OBJC_$_CLASS_METHODS_MyObject" to i8*), i8* bitcast ([1 x i8*]* @"OBJC_LABEL_CLASS_$" to i8*)], section "llvm.metadata" - @llvm.global_ctors = appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 1, void ()* @asan.module_ctor, i8* null }] + @"\01l_OBJC_$_CLASS_METHODS_MyObject" = private global { i32, i32, [1 x %struct._objc_method] } { i32 24, i32 1, [1 x %struct._objc_method] [%struct._objc_method { ptr @OBJC_METH_VAR_NAME_.5, ptr @OBJC_METH_VAR_TYPE_, ptr @"\01+[MyObject doWithSize:]" }] }, section "__DATA, __objc_const", align 8 + @"\01l_OBJC_METACLASS_RO_$_MyObject" = private global %struct._class_ro_t { i32 131, i32 40, i32 40, ptr null, ptr @OBJC_CLASS_NAME_, ptr @"\01l_OBJC_$_CLASS_METHODS_MyObject", ptr null, ptr null, ptr null, ptr null }, section "__DATA, __objc_const", align 8 + @"\01l_OBJC_CLASS_RO_$_MyObject" = private global %struct._class_ro_t { i32 130, i32 0, i32 0, ptr null, ptr @OBJC_CLASS_NAME_, ptr null, ptr null, ptr null, ptr null, ptr null }, section "__DATA, __objc_const", align 8 + @"OBJC_LABEL_CLASS_$" = private global [1 x ptr] [ptr @"OBJC_CLASS_$_MyObject"], section "__DATA, __objc_classlist, regular, no_dead_strip", align 8 + @llvm.compiler.used = appending global [12 x ptr] [ptr @"OBJC_CLASSLIST_REFERENCES_$_", ptr @OBJC_METH_VAR_NAME_, ptr @OBJC_SELECTOR_REFERENCES_, ptr @OBJC_METH_VAR_NAME_.1, ptr @OBJC_SELECTOR_REFERENCES_.2, ptr @OBJC_METH_VAR_NAME_.3, ptr @OBJC_SELECTOR_REFERENCES_.4, ptr @OBJC_CLASS_NAME_, ptr @OBJC_METH_VAR_NAME_.5, ptr @OBJC_METH_VAR_TYPE_, ptr @"\01l_OBJC_$_CLASS_METHODS_MyObject", ptr @"OBJC_LABEL_CLASS_$"], section "llvm.metadata" + @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 1, ptr @asan.module_ctor, ptr null }] @__asan_shadow_memory_dynamic_address = external global i64 @___asan_gen_ = private unnamed_addr constant [34 x i8] c"2 32 16 9 imageSize 64 8 6 object\00", align 1 - @__stack_chk_guard = external global i8* + @__stack_chk_guard = external global ptr ; Function Attrs: noinline sanitize_address ssp uwtable - define internal i8* @"\01+[MyObject doWithSize:]"(i8* %self, i8* %_cmd, [2 x double] %imageSize.coerce) #0 !dbg !14 { + define internal ptr @"\01+[MyObject doWithSize:]"(ptr %self, ptr %_cmd, [2 x double] %imageSize.coerce) #0 !dbg !14 { entry: - %StackGuardSlot = alloca i8* - %0 = call i8* @llvm.stackguard() - call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot) - %1 = load i64, i64* @__asan_shadow_memory_dynamic_address - %self.addr = alloca i8*, align 8 - %_cmd.addr = alloca i8*, align 8 + %StackGuardSlot = alloca ptr + %0 = call ptr @llvm.stackguard() + call void @llvm.stackprotector(ptr %0, ptr %StackGuardSlot) + %1 = load i64, ptr @__asan_shadow_memory_dynamic_address + %self.addr = alloca ptr, align 8 + %_cmd.addr = alloca ptr, align 8 %MyAlloca = alloca [96 x i8], align 32, !dbg !35 - %2 = ptrtoint [96 x i8]* %MyAlloca to i64, !dbg !35 + %2 = ptrtoint ptr %MyAlloca to i64, !dbg !35 %3 = add i64 %2, 32, !dbg !35 - %4 = inttoptr i64 %3 to %struct.CGSize*, !dbg !35 + %4 = inttoptr i64 %3 to ptr, !dbg !35 %5 = add i64 %2, 64, !dbg !35 - %6 = inttoptr i64 %5 to %0**, !dbg !35 - %7 = inttoptr i64 %2 to i64*, !dbg !35 - store i64 1102416563, i64* %7, !dbg !35 + %6 = inttoptr i64 %5 to ptr, !dbg !35 + %7 = inttoptr i64 %2 to ptr, !dbg !35 + store i64 1102416563, ptr %7, !dbg !35 %8 = add i64 %2, 8, !dbg !35 - %9 = inttoptr i64 %8 to i64*, !dbg !35 - store i64 ptrtoint ([34 x i8]* @___asan_gen_ to i64), i64* %9, !dbg !35 + %9 = inttoptr i64 %8 to ptr, !dbg !35 + store i64 ptrtoint (ptr @___asan_gen_ to i64), ptr %9, !dbg !35 %10 = add i64 %2, 16, !dbg !35 - %11 = inttoptr i64 %10 to i64*, !dbg !35 - store i64 ptrtoint (i8* (i8*, i8*, [2 x double])* @"\01+[MyObject doWithSize:]" to i64), i64* %11, !dbg !35 + %11 = inttoptr i64 %10 to ptr, !dbg !35 + store i64 ptrtoint (ptr @"\01+[MyObject doWithSize:]" to i64), ptr %11, !dbg !35 %12 = lshr i64 %2, 3, !dbg !35 %13 = add i64 %12, %1, !dbg !35 %14 = add i64 %13, 0, !dbg !35 - %15 = inttoptr i64 %14 to i64*, !dbg !35 - store i64 -940689368107847183, i64* %15, align 1, !dbg !35 + %15 = inttoptr i64 %14 to ptr, !dbg !35 + store i64 -940689368107847183, ptr %15, align 1, !dbg !35 %16 = add i64 %13, 9, !dbg !35 - %17 = inttoptr i64 %16 to i16*, !dbg !35 - store i16 -3085, i16* %17, align 1, !dbg !35 + %17 = inttoptr i64 %16 to ptr, !dbg !35 + store i16 -3085, ptr %17, align 1, !dbg !35 %18 = add i64 %13, 11, !dbg !35 - %19 = inttoptr i64 %18 to i8*, !dbg !35 - store i8 -13, i8* %19, align 1, !dbg !35 - call void @llvm.dbg.declare(metadata %struct.CGSize* %4, metadata !36, metadata !DIExpression(DW_OP_deref)), !dbg !37 - call void @llvm.dbg.declare(metadata %0** %6, metadata !38, metadata !DIExpression(DW_OP_deref)), !dbg !44 - %20 = bitcast %struct.CGSize* %4 to [2 x double]* - %21 = ptrtoint [2 x double]* %20 to i64 + %19 = inttoptr i64 %18 to ptr, !dbg !35 + store i8 -13, ptr %19, align 1, !dbg !35 + call void @llvm.dbg.declare(metadata ptr %4, metadata !36, metadata !DIExpression(DW_OP_deref)), !dbg !37 + call void @llvm.dbg.declare(metadata ptr %6, metadata !38, metadata !DIExpression(DW_OP_deref)), !dbg !44 + %20 = bitcast ptr %4 to ptr + %21 = ptrtoint ptr %20 to i64 %22 = lshr i64 %21, 3 %23 = add i64 %22, %1 - %24 = inttoptr i64 %23 to i16* - %25 = load i16, i16* %24 + %24 = inttoptr i64 %23 to ptr + %25 = load i16, ptr %24 %26 = icmp ne i16 %25, 0 br i1 %26, label %27, label %28 @@ -127,50 +127,50 @@ unreachable ;