diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index 4e0096cf988aed4031523e3a8343023f88ed7322..21fa15b6a11faf485a6fd21b5d7487ccd6acfd62 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -5432,6 +5432,17 @@ uint64_t RewriteInstance::getNewFunctionOrDataAddress(uint64_t OldAddress) { if (BD && BD->isMoved()) return BD->getOutputAddress(); + if (const BinaryFunction *BF = + BC->getBinaryFunctionContainingAddress(OldAddress)) { + if (BF->isEmitted()) { + BC->errs() << "BOLT-ERROR: unable to get new address corresponding to " + "input address 0x" + << Twine::utohexstr(OldAddress) << " in function " << *BF + << ". Consider adding this function to --skip-funcs=...\n"; + exit(1); + } + } + return 0; } diff --git a/bolt/test/RISCV/unnamed-sym-no-entry.c b/bolt/test/RISCV/unnamed-sym-no-entry.c index 605bbc00aeec4638deaaef54f2505c361055e76f..b4173506b213ce574df197c0c39f1aa172a6dfa3 100644 --- a/bolt/test/RISCV/unnamed-sym-no-entry.c +++ b/bolt/test/RISCV/unnamed-sym-no-entry.c @@ -8,7 +8,7 @@ /// Verify that the binary indeed contains an unnamed symbol at _start // RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=CHECK-ELF // CHECK-ELF-DAG: [[#%x,START:]] {{.*}} FUNC GLOBAL DEFAULT [[#%d,SECTION:]] _start{{$}} -// CHECK-ELF-DAG: [[#%x,START]] {{.*}} NOTYPE LOCAL DEFAULT [[#SECTION]] {{$}} +// CHECK-ELF-DAG: [[#%x,START]] {{.*}} NOTYPE LOCAL DEFAULT [[#SECTION]] .L0 {{$}} /// Verify that BOLT did not create an extra entry point for the unnamed symbol // RUN: llvm-bolt -o %t.bolt %t --print-cfg | FileCheck %s diff --git a/bolt/test/X86/indirect-goto-pie.test b/bolt/test/X86/indirect-goto-pie.test new file mode 100644 index 0000000000000000000000000000000000000000..039ff5c41d3d6842d2e9de2d94908f7dda88fd7f --- /dev/null +++ b/bolt/test/X86/indirect-goto-pie.test @@ -0,0 +1,16 @@ +# Check that llvm-bolt fails to process PIC binaries with computed goto, as the +# support is not there yet for correctly updating dynamic relocations +# referencing code inside functions. + +REQUIRES: x86_64-linux + +RUN: %clang %S/Inputs/indirect_goto.c -o %t -fpic -pie -Wl,-q +RUN: not llvm-bolt %t -o %t.bolt --relocs=1 --print-cfg --print-only=main \ +RUN: |& FileCheck %s + +# Check that processing works if main() is skipped. +RUN: llvm-bolt %t -o %t.bolt --relocs=1 --skip-funcs=main + +CHECK: jmpq *%rax # UNKNOWN CONTROL FLOW + +CHECK: BOLT-ERROR: unable to get new address diff --git a/bolt/test/X86/shrinkwrapping-do-not-pessimize.s b/bolt/test/X86/shrinkwrapping-do-not-pessimize.s index a57131131423efc2e0bfdb1b807985631566f6a5..3fdd5f5e38fe0da9b964a36fbfb0edb35b6a15e5 100644 --- a/bolt/test/X86/shrinkwrapping-do-not-pessimize.s +++ b/bolt/test/X86/shrinkwrapping-do-not-pessimize.s @@ -53,6 +53,6 @@ end_if_1: .size _start, .-_start .data -rel: .quad end_if_1 +rel: .quad _start # CHECK: BOLT-INFO: Shrink wrapping moved 0 spills inserting load/stores and 0 spills inserting push/pops diff --git a/bolt/test/runtime/X86/Inputs/indirect_goto.c b/bolt/test/runtime/X86/Inputs/indirect_goto.c deleted file mode 100644 index b781e9e03b6d44b40567a3111d64394399ad4421..0000000000000000000000000000000000000000 --- a/bolt/test/runtime/X86/Inputs/indirect_goto.c +++ /dev/null @@ -1,18 +0,0 @@ -int main(int argc, char *argv[]) { - static const void *T1[] = { &&L1, &&L2 }; - static const void *T2[] = { &&L2, &&L3 }; - - const void **T = (argc > 1) ? T1 : T2; - - int i = 0; - -L0: - goto *T[argc]; -L1: - ++i; -L2: - i++; -L3: - i++; - return i; -} diff --git a/bolt/test/runtime/X86/indirect-goto-pie.test b/bolt/test/runtime/X86/indirect-goto-pie.test deleted file mode 100644 index 76089fda3abfb27f0daeba13db224fafc23266ab..0000000000000000000000000000000000000000 --- a/bolt/test/runtime/X86/indirect-goto-pie.test +++ /dev/null @@ -1,10 +0,0 @@ -# Check llvm-bolt processes binaries compiled from sources that use indirect goto. -REQUIRES: x86_64-linux - -RUN: %clang %S/Inputs/indirect_goto.c -o %t -fpic -pie -Wl,-q -RUN: llvm-bolt %t -o %t.bolt --relocs=1 --print-cfg --print-only=main \ -RUN: |& FileCheck %s -# The test fails as we don't update corresponding dynamic relocations. -RUN: not %t.bolt - -CHECK: jmpq *%rax # UNKNOWN CONTROL FLOW diff --git a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp index 2931325d8b57981fc097fb19a3f6cfbc0746ad54..1b92d2e60cc1731171a402e736e5c7992ab9e145 100644 --- a/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/BugproneTidyModule.cpp @@ -54,6 +54,7 @@ #include "PosixReturnCheck.h" #include "RedundantBranchConditionCheck.h" #include "ReservedIdentifierCheck.h" +#include "ReturnConstRefFromParameterCheck.h" #include "SharedPtrArrayMismatchCheck.h" #include "SignalHandlerCheck.h" #include "SignedCharMisuseCheck.h" @@ -137,6 +138,8 @@ public: "bugprone-inaccurate-erase"); CheckFactories.registerCheck( "bugprone-incorrect-enable-if"); + CheckFactories.registerCheck( + "bugprone-return-const-ref-from-parameter"); CheckFactories.registerCheck( "bugprone-switch-missing-default-case"); CheckFactories.registerCheck( diff --git a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt index 081ba67efe1538e3378e53a1f7718299a650d4e7..2d303191f88650bd1b611d95376f0f6f84916570 100644 --- a/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt +++ b/clang-tools-extra/clang-tidy/bugprone/CMakeLists.txt @@ -26,6 +26,7 @@ add_clang_library(clangTidyBugproneModule ImplicitWideningOfMultiplicationResultCheck.cpp InaccurateEraseCheck.cpp IncorrectEnableIfCheck.cpp + ReturnConstRefFromParameterCheck.cpp SuspiciousStringviewDataUsageCheck.cpp SwitchMissingDefaultCaseCheck.cpp IncDecInConditionsCheck.cpp diff --git a/clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8ae37d4f774d23041cb9b9816ae6e0d0e2c792d7 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.cpp @@ -0,0 +1,34 @@ +//===--- ReturnConstRefFromParameterCheck.cpp - clang-tidy ----------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "ReturnConstRefFromParameterCheck.h" +#include "../utils/Matchers.h" +#include "clang/ASTMatchers/ASTMatchFinder.h" +#include "clang/ASTMatchers/ASTMatchers.h" + +using namespace clang::ast_matchers; + +namespace clang::tidy::bugprone { + +void ReturnConstRefFromParameterCheck::registerMatchers(MatchFinder *Finder) { + Finder->addMatcher( + returnStmt(hasReturnValue(declRefExpr(to(parmVarDecl(hasType( + hasCanonicalType(matchers::isReferenceToConst()))))))) + .bind("ret"), + this); +} + +void ReturnConstRefFromParameterCheck::check( + const MatchFinder::MatchResult &Result) { + const auto *R = Result.Nodes.getNodeAs("ret"); + diag(R->getRetValue()->getBeginLoc(), + "returning a constant reference parameter may cause a use-after-free " + "when the parameter is constructed from a temporary"); +} + +} // namespace clang::tidy::bugprone diff --git a/clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.h b/clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.h new file mode 100644 index 0000000000000000000000000000000000000000..8768d07087383f387f922b122259e4d2af67d028 --- /dev/null +++ b/clang-tools-extra/clang-tidy/bugprone/ReturnConstRefFromParameterCheck.h @@ -0,0 +1,40 @@ +//===--- ReturnConstRefFromParameterCheck.h - clang-tidy --------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_RETURNCONSTREFFROMPARAMETERCHECK_H +#define LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_RETURNCONSTREFFROMPARAMETERCHECK_H + +#include "../ClangTidyCheck.h" + +namespace clang::tidy::bugprone { + +/// Detects return statements that return a constant reference parameter as +/// constant reference. This may cause use-after-free errors if the caller uses +/// xvalues as arguments. +/// +/// For the user-facing documentation see: +/// http://clang.llvm.org/extra/clang-tidy/checks/bugprone/return-const-ref-from-parameter.html +class ReturnConstRefFromParameterCheck : public ClangTidyCheck { +public: + ReturnConstRefFromParameterCheck(StringRef Name, ClangTidyContext *Context) + : ClangTidyCheck(Name, Context) {} + void registerMatchers(ast_matchers::MatchFinder *Finder) override; + void check(const ast_matchers::MatchFinder::MatchResult &Result) override; + std::optional getCheckTraversalKind() const override { + // Use 'AsIs' to make sure the return type is exactly the same as the + // parameter type. + return TK_AsIs; + } + bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { + return LangOpts.CPlusPlus; + } +}; + +} // namespace clang::tidy::bugprone + +#endif // LLVM_CLANG_TOOLS_EXTRA_CLANG_TIDY_BUGPRONE_RETURNCONSTREFFROMPARAMETERCHECK_H diff --git a/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp b/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp index 062f6e9911dbed35d3848a8cf7e1202ae1ec85ba..89ee45faecd7f33e8f80189ee59fad02849695aa 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp +++ b/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.cpp @@ -43,7 +43,9 @@ void UseStartsEndsWithCheck::registerMatchers(MatchFinder *Finder) { callee(cxxMethodDecl(hasName("find")).bind("find_fun")), // ... on a class with a starts_with function. on(hasType( - hasCanonicalType(hasDeclaration(ClassWithStartsWithFunction))))); + hasCanonicalType(hasDeclaration(ClassWithStartsWithFunction)))), + // Bind search expression. + hasArgument(0, expr().bind("search_expr"))); const auto RFindExpr = cxxMemberCallExpr( // A method call with a second argument of zero... @@ -52,15 +54,68 @@ void UseStartsEndsWithCheck::registerMatchers(MatchFinder *Finder) { callee(cxxMethodDecl(hasName("rfind")).bind("find_fun")), // ... on a class with a starts_with function. on(hasType( - hasCanonicalType(hasDeclaration(ClassWithStartsWithFunction))))); + hasCanonicalType(hasDeclaration(ClassWithStartsWithFunction)))), + // Bind search expression. + hasArgument(0, expr().bind("search_expr"))); + + // Match a string literal and an integer or strlen() call matching the length. + const auto HasStringLiteralAndLengthArgs = [](const auto StringArgIndex, + const auto LengthArgIndex) { + return allOf( + hasArgument(StringArgIndex, stringLiteral().bind("string_literal_arg")), + hasArgument(LengthArgIndex, + anyOf(integerLiteral().bind("integer_literal_size_arg"), + callExpr(callee(functionDecl(parameterCountIs(1), + hasName("strlen"))), + hasArgument(0, stringLiteral().bind( + "strlen_arg")))))); + }; + + // Match a string variable and a call to length() or size(). + const auto HasStringVariableAndSizeCallArgs = [](const auto StringArgIndex, + const auto LengthArgIndex) { + return allOf( + hasArgument(StringArgIndex, declRefExpr(hasDeclaration( + decl().bind("string_var_decl")))), + hasArgument(LengthArgIndex, + cxxMemberCallExpr( + callee(cxxMethodDecl(isConst(), parameterCountIs(0), + hasAnyName("size", "length"))), + on(declRefExpr( + to(decl(equalsBoundNode("string_var_decl")))))))); + }; - const auto FindOrRFindExpr = - cxxMemberCallExpr(anyOf(FindExpr, RFindExpr)).bind("find_expr"); + // Match either one of the two cases above. + const auto HasStringAndLengthArgs = + [HasStringLiteralAndLengthArgs, HasStringVariableAndSizeCallArgs]( + const auto StringArgIndex, const auto LengthArgIndex) { + return anyOf( + HasStringLiteralAndLengthArgs(StringArgIndex, LengthArgIndex), + HasStringVariableAndSizeCallArgs(StringArgIndex, LengthArgIndex)); + }; + + const auto CompareExpr = cxxMemberCallExpr( + // A method call with three arguments... + argumentCountIs(3), + // ... where the first argument is zero... + hasArgument(0, ZeroLiteral), + // ... named compare... + callee(cxxMethodDecl(hasName("compare")).bind("find_fun")), + // ... on a class with a starts_with function... + on(hasType( + hasCanonicalType(hasDeclaration(ClassWithStartsWithFunction)))), + // ... where the third argument is some string and the second a length. + HasStringAndLengthArgs(2, 1), + // Bind search expression. + hasArgument(2, expr().bind("search_expr"))); Finder->addMatcher( - // Match [=!]= with a zero on one side and a string.(r?)find on the other. - binaryOperator(hasAnyOperatorName("==", "!="), - hasOperands(FindOrRFindExpr, ZeroLiteral)) + // Match [=!]= with a zero on one side and (r?)find|compare on the other. + binaryOperator( + hasAnyOperatorName("==", "!="), + hasOperands(cxxMemberCallExpr(anyOf(FindExpr, RFindExpr, CompareExpr)) + .bind("find_expr"), + ZeroLiteral)) .bind("expr"), this); } @@ -69,9 +124,28 @@ void UseStartsEndsWithCheck::check(const MatchFinder::MatchResult &Result) { const auto *ComparisonExpr = Result.Nodes.getNodeAs("expr"); const auto *FindExpr = Result.Nodes.getNodeAs("find_expr"); const auto *FindFun = Result.Nodes.getNodeAs("find_fun"); + const auto *SearchExpr = Result.Nodes.getNodeAs("search_expr"); const auto *StartsWithFunction = Result.Nodes.getNodeAs("starts_with_fun"); + const auto *StringLiteralArg = + Result.Nodes.getNodeAs("string_literal_arg"); + const auto *IntegerLiteralSizeArg = + Result.Nodes.getNodeAs("integer_literal_size_arg"); + const auto *StrlenArg = Result.Nodes.getNodeAs("strlen_arg"); + + // Filter out compare cases where the length does not match string literal. + if (StringLiteralArg && IntegerLiteralSizeArg && + StringLiteralArg->getLength() != + IntegerLiteralSizeArg->getValue().getZExtValue()) { + return; + } + + if (StringLiteralArg && StrlenArg && + StringLiteralArg->getLength() != StrlenArg->getLength()) { + return; + } + if (ComparisonExpr->getBeginLoc().isMacroID()) { return; } @@ -79,13 +153,13 @@ void UseStartsEndsWithCheck::check(const MatchFinder::MatchResult &Result) { const bool Neg = ComparisonExpr->getOpcode() == BO_NE; auto Diagnostic = - diag(FindExpr->getBeginLoc(), "use %0 instead of %1() %select{==|!=}2 0") + diag(FindExpr->getExprLoc(), "use %0 instead of %1() %select{==|!=}2 0") << StartsWithFunction->getName() << FindFun->getName() << Neg; - // Remove possible zero second argument and ' [!=]= 0' suffix. + // Remove possible arguments after search expression and ' [!=]= 0' suffix. Diagnostic << FixItHint::CreateReplacement( CharSourceRange::getTokenRange( - Lexer::getLocForEndOfToken(FindExpr->getArg(0)->getEndLoc(), 0, + Lexer::getLocForEndOfToken(SearchExpr->getEndLoc(), 0, *Result.SourceManager, getLangOpts()), ComparisonExpr->getEndLoc()), ")"); @@ -94,11 +168,12 @@ void UseStartsEndsWithCheck::check(const MatchFinder::MatchResult &Result) { Diagnostic << FixItHint::CreateRemoval(CharSourceRange::getCharRange( ComparisonExpr->getBeginLoc(), FindExpr->getBeginLoc())); - // Replace '(r?)find' with 'starts_with'. + // Replace method name by 'starts_with'. + // Remove possible arguments before search expression. Diagnostic << FixItHint::CreateReplacement( - CharSourceRange::getTokenRange(FindExpr->getExprLoc(), - FindExpr->getExprLoc()), - StartsWithFunction->getName()); + CharSourceRange::getCharRange(FindExpr->getExprLoc(), + SearchExpr->getBeginLoc()), + (StartsWithFunction->getName() + "(").str()); // Add possible negation '!'. if (Neg) { diff --git a/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.h b/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.h index 34e97177682575c97849f542f5679a3366ba0ec6..840191f321493fe49e440b4bb7bbfc5407c64b3b 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.h +++ b/clang-tools-extra/clang-tidy/modernize/UseStartsEndsWithCheck.h @@ -13,9 +13,10 @@ namespace clang::tidy::modernize { -/// Checks whether a ``find`` or ``rfind`` result is compared with 0 and -/// suggests replacing with ``starts_with`` when the method exists in the class. -/// Notably, this will work with ``std::string`` and ``std::string_view``. +/// Checks for common roundabout ways to express ``starts_with`` and +/// ``ends_with`` and suggests replacing with ``starts_with`` when the method is +/// available. Notably, this will work with ``std::string`` and +/// ``std::string_view``. /// /// For the user-facing documentation see: /// http://clang.llvm.org/extra/clang-tidy/checks/modernize/use-starts-ends-with.html diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 28840b9beae881865b8836b855f737880f91f70a..5b1feffb89ea0602e2f38392b2ef1ff7ba365ba4 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -117,6 +117,13 @@ New checks Detects error-prone Curiously Recurring Template Pattern usage, when the CRTP can be constructed outside itself and the derived class. +- New :doc:`bugprone-return-const-ref-from-parameter + ` check. + + Detects return statements that return a constant reference parameter as constant + reference. This may cause use-after-free errors if the caller uses xvalues as + arguments. + - New :doc:`bugprone-suspicious-stringview-data-usage ` check. @@ -266,6 +273,10 @@ Changes in existing checks ` check to also remove any trailing whitespace when deleting the ``virtual`` keyword. +- Improved :doc:`modernize-use-starts-ends-with + ` check to also handle + calls to ``compare`` method. + - Improved :doc:`modernize-use-using ` check by adding support for detection of typedefs declared on function level. diff --git a/clang-tools-extra/docs/clang-tidy/checks/bugprone/return-const-ref-from-parameter.rst b/clang-tools-extra/docs/clang-tidy/checks/bugprone/return-const-ref-from-parameter.rst new file mode 100644 index 0000000000000000000000000000000000000000..f007dfe5499908d261e0939c21ff9412e3499656 --- /dev/null +++ b/clang-tools-extra/docs/clang-tidy/checks/bugprone/return-const-ref-from-parameter.rst @@ -0,0 +1,31 @@ +.. title:: clang-tidy - bugprone-return-const-ref-from-parameter + +bugprone-return-const-ref-from-parameter +======================================== + +Detects return statements that return a constant reference parameter as constant +reference. This may cause use-after-free errors if the caller uses xvalues as +arguments. + +In C++, constant reference parameters can accept xvalues which will be destructed +after the call. When the function returns such a parameter also as constant reference, +then the returned reference can be used after the object it refers to has been +destroyed. + +Example +------- + +.. code-block:: c++ + + struct S { + int v; + S(int); + ~S(); + }; + + const S &fn(const S &a) { + return a; + } + + const S& s = fn(S{1}); + s.v; // use after free diff --git a/clang-tools-extra/docs/clang-tidy/checks/list.rst b/clang-tools-extra/docs/clang-tidy/checks/list.rst index 3a06d7c30c9b79e647e2525a67577acf84121345..5d9d487f75f9cbea36f798442391fb7ad41075e1 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/list.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/list.rst @@ -120,6 +120,7 @@ Clang-Tidy Checks :doc:`bugprone-posix-return `, "Yes" :doc:`bugprone-redundant-branch-condition `, "Yes" :doc:`bugprone-reserved-identifier `, "Yes" + :doc:`bugprone-return-const-ref-from-parameter ` :doc:`bugprone-shared-ptr-array-mismatch `, "Yes" :doc:`bugprone-signal-handler `, :doc:`bugprone-signed-char-misuse `, diff --git a/clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst b/clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst index 7f8a262d2ab3aac9f4e13064062f584ea5d1460e..34237ede30a30b51f4c35703d7a2151171c356c4 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/modernize/use-starts-ends-with.rst @@ -3,15 +3,16 @@ modernize-use-starts-ends-with ============================== -Checks whether a ``find`` or ``rfind`` result is compared with 0 and suggests -replacing with ``starts_with`` when the method exists in the class. Notably, -this will work with ``std::string`` and ``std::string_view``. +Checks for common roundabout ways to express ``starts_with`` and ``ends_with`` +and suggests replacing with ``starts_with`` when the method is available. +Notably, this will work with ``std::string`` and ``std::string_view``. .. code-block:: c++ std::string s = "..."; if (s.find("prefix") == 0) { /* do something */ } if (s.rfind("prefix", 0) == 0) { /* do something */ } + if (s.compare(0, strlen("prefix"), "prefix") == 0) { /* do something */ } becomes @@ -20,3 +21,4 @@ becomes std::string s = "..."; if (s.starts_with("prefix")) { /* do something */ } if (s.starts_with("prefix")) { /* do something */ } + if (s.starts_with("prefix")) { /* do something */ } diff --git a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string index 28e2b4a231e52edbb3697d2e5c76d513c3062089..d031f27beb9dfef99d61b44bff19a6dc8e1a885f 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string +++ b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string @@ -44,6 +44,8 @@ struct basic_string { int compare(const C* s) const; int compare(size_type pos, size_type len, const _Type&) const; int compare(size_type pos, size_type len, const C* s) const; + template + int compare(size_type pos1, size_type count1, const StringViewLike& t) const; size_type find(const _Type& str, size_type pos = 0) const; size_type find(const C* s, size_type pos = 0) const; @@ -129,6 +131,8 @@ bool operator!=(const char*, const std::string&); bool operator==(const std::wstring&, const std::wstring&); bool operator==(const std::wstring&, const wchar_t*); bool operator==(const wchar_t*, const std::wstring&); + +size_t strlen(const char* str); } #endif // _STRING_ diff --git a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string.h b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string.h index 4ab7e930e4b5067f1b87529a5a9b3378a4bb59eb..af205868059a82aa0b34a4bf908538a6d71caad4 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string.h +++ b/clang-tools-extra/test/clang-tidy/checkers/Inputs/Headers/string.h @@ -12,5 +12,6 @@ #include "stddef.h" void *memcpy(void *dest, const void *src, size_t n); +size_t strlen(const char* str); #endif // _STRING_H_ diff --git a/clang-tools-extra/test/clang-tidy/checkers/abseil/redundant-strcat-calls.cpp b/clang-tools-extra/test/clang-tidy/checkers/abseil/redundant-strcat-calls.cpp index ecd17bba293c5bf5eb524f310d376648e9f297de..dbd354b132e2ff4f46012dc4c1cf006e825d041d 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/abseil/redundant-strcat-calls.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/abseil/redundant-strcat-calls.cpp @@ -1,8 +1,6 @@ // RUN: %check_clang_tidy %s abseil-redundant-strcat-calls %t -- -- -isystem %clang_tidy_headers #include -int strlen(const char *); - namespace absl { class string_view { diff --git a/clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp b/clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..a83a019ec7437da6ccda446b20af87f0639ee303 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/bugprone/return-const-ref-from-parameter.cpp @@ -0,0 +1,31 @@ +// RUN: %check_clang_tidy %s bugprone-return-const-ref-from-parameter %t + +using T = int; +using TConst = int const; +using TConstRef = int const&; + +namespace invalid { + +int const &f1(int const &a) { return a; } +// CHECK-MESSAGES: :[[@LINE-1]]:38: warning: returning a constant reference parameter + +int const &f2(T const &a) { return a; } +// CHECK-MESSAGES: :[[@LINE-1]]:36: warning: returning a constant reference parameter + +int const &f3(TConstRef a) { return a; } +// CHECK-MESSAGES: :[[@LINE-1]]:37: warning: returning a constant reference parameter + +int const &f4(TConst &a) { return a; } +// CHECK-MESSAGES: :[[@LINE-1]]:35: warning: returning a constant reference parameter + +} // namespace invalid + +namespace valid { + +int const &f1(int &a) { return a; } + +int const &f2(int &&a) { return a; } + +int f1(int const &a) { return a; } + +} // namespace valid diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp index 65ed9ed895bc4731e8c3fa8ab13ff0db11445ab8..c5b2c86befd1fec8c42c9f980367d07de51b4c69 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-starts-ends-with.cpp @@ -1,6 +1,7 @@ // RUN: %check_clang_tidy -std=c++20 %s modernize-use-starts-ends-with %t -- \ // RUN: -- -isystem %clang_tidy_headers +#include #include std::string foo(std::string); @@ -158,10 +159,64 @@ void test(std::string s, std::string_view sv, sub_string ss, sub_sub_string sss, // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use startsWith // CHECK-FIXES: puvi.startsWith("a"); + s.compare(0, 1, "a") == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with instead of compare() == 0 + // CHECK-FIXES: s.starts_with("a"); + + s.compare(0, 1, "a") != 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with instead of compare() != 0 + // CHECK-FIXES: !s.starts_with("a"); + + s.compare(0, strlen("a"), "a") == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with("a"); + + s.compare(0, std::strlen("a"), "a") == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with("a"); + + s.compare(0, std::strlen(("a")), "a") == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with("a"); + + s.compare(0, std::strlen(("a")), (("a"))) == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with("a"); + + s.compare(0, s.size(), s) == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with(s); + + s.compare(0, s.length(), s) == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with(s); + + 0 != s.compare(0, sv.length(), sv); + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with(sv); + + #define LENGTH(x) (x).length() + s.compare(0, LENGTH(s), s) == 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with(s); + + s.compare(ZERO, LENGTH(s), s) == ZERO; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: s.starts_with(s); + + s.compare(ZERO, LENGTH(sv), sv) != 0; + // CHECK-MESSAGES: :[[@LINE-1]]:{{[0-9]+}}: warning: use starts_with + // CHECK-FIXES: !s.starts_with(sv); + // Expressions that don't trigger the check are here. #define EQ(x, y) ((x) == (y)) EQ(s.find("a"), 0); #define DOTFIND(x, y) (x).find(y) DOTFIND(s, "a") == 0; + + #define STARTS_WITH_COMPARE(x, y) (x).compare(0, (x).size(), (y)) + STARTS_WITH_COMPARE(s, s) == 0; + + s.compare(0, 1, "ab") == 0; } diff --git a/clang/cmake/caches/Release.cmake b/clang/cmake/caches/Release.cmake index bd1f688d61a7ea2aaa475aaec7d6a0970c12139f..fa972636553f1f613eaa7e8f19d55f9b54f42f0d 100644 --- a/clang/cmake/caches/Release.cmake +++ b/clang/cmake/caches/Release.cmake @@ -14,6 +14,7 @@ if (LLVM_RELEASE_ENABLE_PGO) set(CLANG_BOOTSTRAP_TARGETS generate-profdata stage2 + stage2-package stage2-clang stage2-distribution stage2-install @@ -57,6 +58,7 @@ set(LLVM_TARGETS_TO_BUILD Native CACHE STRING "") set(BOOTSTRAP_CLANG_ENABLE_BOOTSTRAP ON CACHE STRING "") set(BOOTSTRAP_CLANG_BOOTSTRAP_TARGETS clang + package check-all check-llvm check-clang CACHE STRING "") diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index d1f7293a842bb684c1f881d0fb60f4926a191716..7bea43ec64f062f6617bfbf1eb26c819c17772bb 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -415,6 +415,9 @@ Bug Fixes in This Version operator. Fixes (#GH83267). +- Fix crash on ill-formed partial specialization with CRTP. + Fixes (#GH89374). + - Clang now correctly generates overloads for bit-precise integer types for builtin operators in C++. Fixes #GH82998. @@ -557,7 +560,6 @@ Bug Fixes to C++ Support - Fix a crash in requires expression with templated base class member function. Fixes (#GH84020). - Fix a crash caused by defined struct in a type alias template when the structure has fields with dependent type. Fixes (#GH75221). -- Fix placement new initializes typedef array with correct size. Fixes (#GH41441). - Fix the Itanium mangling of lambdas defined in a member of a local class (#GH88906) - Fixed a crash when trying to evaluate a user-defined ``static_assert`` message whose ``size()`` function returns a large or negative value. Fixes (#GH89407). @@ -708,6 +710,9 @@ clang-format libclang -------- +- ``clang_getSpellingLocation`` now correctly resolves macro expansions; that + is, it returns the spelling location instead of the expansion location. + Static Analyzer --------------- diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 63e951daec7477679802ad24842eb33f2652c4f4..6732a1a98452ad3c3063f8028634d19f376682f4 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -3755,14 +3755,12 @@ def err_sme_definition_using_za_in_non_sme_target : Error< def err_sme_definition_using_zt0_in_non_sme2_target : Error< "function using ZT0 state requires 'sme2'">; def warn_sme_streaming_pass_return_vl_to_non_streaming : Warning< - "passing a VL-dependent argument to/from a function that has a different" - " streaming-mode. The streaming and non-streaming vector lengths may be" - " different">, + "%select{returning|passing}0 a VL-dependent argument %select{from|to}0 a function with a different" + " streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime">, InGroup, DefaultIgnore; def warn_sme_locally_streaming_has_vl_args_returns : Warning< - "passing/returning a VL-dependent argument to/from a __arm_locally_streaming" - " function. The streaming and non-streaming vector" - " lengths may be different">, + "%select{returning|passing}0 a VL-dependent argument %select{from|to}0 a locally streaming function is undefined" + " behaviour when the streaming and non-streaming vector lengths are different at runtime">, InGroup, DefaultIgnore; def err_conflicting_attributes_arm_state : Error< "conflicting attributes for state '%0'">; diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 76ed544f3b2bb1f2e0176932098b732613ec1b7a..cca4367751b92b0812c6e16bc084d64aceea641e 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -14,14 +14,14 @@ include "riscv_vector_common.td" -defvar TypeList = ["c","s","i","l","x","f","d"]; +defvar TypeList = ["c","s","i","l","x","f","d","y"]; defvar EEWList = [["8", "(Log2EEW:3)"], ["16", "(Log2EEW:4)"], ["32", "(Log2EEW:5)"], ["64", "(Log2EEW:6)"]]; class IsFloat { - bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d")); + bit val = !or(!eq(type, "x"), !eq(type, "f"), !eq(type, "d"), !eq(type, "y")); } let SupportOverloading = false, @@ -118,7 +118,8 @@ multiclass RVVIndexedLoad { defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask", RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []) in { + !if(!eq(type, "y"), ["Zvfbfmin"], + [])) in { def: RVVOutOp1Builtin<"v", "vPCe" # eew_type # "Uv", type>; if !not(IsFloat.val) then { def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew_type # "Uv", type>; @@ -129,7 +130,8 @@ multiclass RVVIndexedLoad { defvar eew64_type = "(Log2EEW:6)"; let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask", RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], - ["RV64"]) in { + !if(!eq(type, "y"), ["Zvfbfmin", "RV64"], + ["RV64"])) in { def: RVVOutOp1Builtin<"v", "vPCe" # eew64_type # "Uv", type>; if !not(IsFloat.val) then { def: RVVOutOp1Builtin<"Uv", "UvPCUe" # eew64_type # "Uv", type>; @@ -223,7 +225,8 @@ multiclass RVVIndexedStore { defvar eew_type = eew_list[1]; let Name = op # eew # "_v", IRName = op, MaskedIRName = op # "_mask", RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []) in { + !if(!eq(type, "y"), ["Zvfbfmin"], + [])) in { def : RVVBuiltin<"v", "0Pe" # eew_type # "Uvv", type>; if !not(IsFloat.val) then { def : RVVBuiltin<"Uv", "0PUe" # eew_type # "UvUv", type>; @@ -234,7 +237,8 @@ multiclass RVVIndexedStore { defvar eew64_type = "(Log2EEW:6)"; let Name = op # eew64 # "_v", IRName = op, MaskedIRName = op # "_mask", RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin", "RV64"], - ["RV64"]) in { + !if(!eq(type, "y"), ["Zvfbfmin", "RV64"], + ["RV64"])) in { def : RVVBuiltin<"v", "0Pe" # eew64_type # "Uvv", type>; if !not(IsFloat.val) then { def : RVVBuiltin<"Uv", "0PUe" # eew64_type # "UvUv", type>; @@ -358,6 +362,10 @@ multiclass RVVNonTupleVCreateBuiltin src_lmul_list> { def vcreate # src_v # dst_v : RVVBuiltin; + let RequiredFeatures = ["Zvfbfmin"] in + def vcreate_bf16 # src_v # dst_v : RVVBuiltin; defvar src_uv = FixedVString.V; defvar src_us = FixedVString.S; @@ -683,6 +691,8 @@ defm vle8: RVVVLEBuiltin<["c"]>; defm vle16: RVVVLEBuiltin<["s"]>; let Name = "vle16_v", RequiredFeatures = ["Zvfhmin"] in defm vle16_h: RVVVLEBuiltin<["x"]>; +let Name = "vle16_v", RequiredFeatures = ["Zvfbfmin"] in + defm vle16_bf16 : RVVVLEBuiltin<["y"]>; defm vle32: RVVVLEBuiltin<["i","f"]>; defm vle64: RVVVLEBuiltin<["l","d"]>; @@ -691,6 +701,8 @@ defm vse8 : RVVVSEBuiltin<["c"]>; defm vse16: RVVVSEBuiltin<["s"]>; let Name = "vse16_v", RequiredFeatures = ["Zvfhmin"] in defm vse16_h: RVVVSEBuiltin<["x"]>; +let Name = "vse16_v", RequiredFeatures = ["Zvfbfmin"] in + defm vse16_bf16: RVVVSEBuiltin<["y"]>; defm vse32: RVVVSEBuiltin<["i","f"]>; defm vse64: RVVVSEBuiltin<["l","d"]>; @@ -699,6 +711,8 @@ defm vlse8: RVVVLSEBuiltin<["c"]>; defm vlse16: RVVVLSEBuiltin<["s"]>; let Name = "vlse16_v", RequiredFeatures = ["Zvfhmin"] in defm vlse16_h: RVVVLSEBuiltin<["x"]>; +let Name = "vlse16_v", RequiredFeatures = ["Zvfbfmin"] in + defm vlse16_bf16: RVVVLSEBuiltin<["y"]>; defm vlse32: RVVVLSEBuiltin<["i","f"]>; defm vlse64: RVVVLSEBuiltin<["l","d"]>; @@ -706,6 +720,8 @@ defm vsse8 : RVVVSSEBuiltin<["c"]>; defm vsse16: RVVVSSEBuiltin<["s"]>; let Name = "vsse16_v", RequiredFeatures = ["Zvfhmin"] in defm vsse16_h: RVVVSSEBuiltin<["x"]>; +let Name = "vsse16_v", RequiredFeatures = ["Zvfbfmin"] in + defm vsse16_bf: RVVVSSEBuiltin<["y"]>; defm vsse32: RVVVSSEBuiltin<["i","f"]>; defm vsse64: RVVVSSEBuiltin<["l","d"]>; @@ -721,6 +737,8 @@ defm vle8ff: RVVVLEFFBuiltin<["c"]>; defm vle16ff: RVVVLEFFBuiltin<["s"]>; let Name = "vle16ff_v", RequiredFeatures = ["Zvfhmin"] in defm vle16ff: RVVVLEFFBuiltin<["x"]>; +let Name = "vle16ff_v", RequiredFeatures = ["Zvfbfmin"] in + defm vle16ff: RVVVLEFFBuiltin<["y"]>; defm vle32ff: RVVVLEFFBuiltin<["i", "f"]>; defm vle64ff: RVVVLEFFBuiltin<["l", "d"]>; @@ -732,14 +750,16 @@ multiclass RVVUnitStridedSegLoadTuple { !eq(type, "l") : "64", !eq(type, "x") : "16", !eq(type, "f") : "32", - !eq(type, "d") : "64"); + !eq(type, "d") : "64", + !eq(type, "y") : "16"); foreach nf = NFList in { let Name = op # nf # "e" # eew # "_v", IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { llvm::Type *ElementVectorType = cast(ResultType)->elements()[0]; @@ -793,7 +813,8 @@ multiclass RVVUnitStridedSegStoreTuple { !eq(type, "l") : "64", !eq(type, "x") : "16", !eq(type, "f") : "32", - !eq(type, "d") : "64"); + !eq(type, "d") : "64", + !eq(type, "y") : "16"); foreach nf = NFList in { let Name = op # nf # "e" # eew # "_v", IRName = op # nf, @@ -801,7 +822,8 @@ multiclass RVVUnitStridedSegStoreTuple { NF = nf, HasMaskedOffOperand = false, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { // Masked @@ -846,14 +868,16 @@ multiclass RVVUnitStridedSegLoadFFTuple { !eq(type, "l") : "64", !eq(type, "x") : "16", !eq(type, "f") : "32", - !eq(type, "d") : "64"); + !eq(type, "d") : "64", + !eq(type, "y") : "16"); foreach nf = NFList in { let Name = op # nf # "e" # eew # "ff_v", IRName = op # nf # "ff", MaskedIRName = op # nf # "ff_mask", NF = nf, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { llvm::Type *ElementVectorType = cast(ResultType)->elements()[0]; @@ -921,14 +945,16 @@ multiclass RVVStridedSegLoadTuple { !eq(type, "l") : "64", !eq(type, "x") : "16", !eq(type, "f") : "32", - !eq(type, "d") : "64"); + !eq(type, "d") : "64", + !eq(type, "y") : "16"); foreach nf = NFList in { let Name = op # nf # "e" # eew # "_v", IRName = op # nf, MaskedIRName = op # nf # "_mask", NF = nf, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { llvm::Type *ElementVectorType = cast(ResultType)->elements()[0]; @@ -983,7 +1009,8 @@ multiclass RVVStridedSegStoreTuple { !eq(type, "l") : "64", !eq(type, "x") : "16", !eq(type, "f") : "32", - !eq(type, "d") : "64"); + !eq(type, "d") : "64", + !eq(type, "y") : "16"); foreach nf = NFList in { let Name = op # nf # "e" # eew # "_v", IRName = op # nf, @@ -992,7 +1019,8 @@ multiclass RVVStridedSegStoreTuple { HasMaskedOffOperand = false, MaskedPolicyScheme = NonePolicy, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { // Masked @@ -1041,7 +1069,8 @@ multiclass RVVIndexedSegLoadTuple { MaskedIRName = op # nf # "_mask", NF = nf, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { llvm::Type *ElementVectorType = cast(ResultType)->elements()[0]; @@ -1104,7 +1133,8 @@ multiclass RVVIndexedSegStoreTuple { HasMaskedOffOperand = false, MaskedPolicyScheme = NonePolicy, RequiredFeatures = !if(!eq(type, "x"), ["Zvfhmin"], - []), + !if(!eq(type, "y"), ["Zvfbfmin"], + [])), ManualCodegen = [{ { // Masked @@ -2308,6 +2338,12 @@ let HasMasked = false, HasVL = false, IRName = "" in { def vreinterpret_h_i : RVVBuiltin<"vFv", "Fvv", "s", "Fv">; def vreinterpret_h_u : RVVBuiltin<"UvFv", "FvUv", "s", "Fv">; } + let RequiredFeatures = ["Zvfbfmin"] in { + def vreinterpret_i_bf16 : RVVBuiltin<"vIv", "Ivv", "y", "Iv">; + def vreinterpret_u_bf16 : RVVBuiltin<"vUv", "Uvv", "y", "Uv">; + def vreinterpret_bf16_i : RVVBuiltin<"Ivv", "vIv", "y", "v">; + def vreinterpret_bf16_u : RVVBuiltin<"Uvv", "vUv", "y", "v">; + } // Reinterpret between different SEW under the same LMUL foreach dst_sew = ["(FixedSEW:8)", "(FixedSEW:16)", "(FixedSEW:32)", @@ -2372,12 +2408,16 @@ let HasMasked = false, HasVL = false, IRName = "" in { return llvm::PoisonValue::get(ResultType); }] in { def vundefined : RVVBuiltin<"v", "v", "csilxfd">; + let RequiredFeatures = ["Zvfbfmin"] in + def vundefined_bf16 : RVVBuiltin<"v", "v", "y">; def vundefined_u : RVVBuiltin<"Uv", "Uv", "csil">; foreach nf = NFList in { let NF = nf in { defvar T = "(Tuple:" # nf # ")"; def : RVVBuiltin; + let RequiredFeatures = ["Zvfbfmin"] in + def : RVVBuiltin; def : RVVBuiltin; } } @@ -2396,6 +2436,9 @@ let HasMasked = false, HasVL = false, IRName = "" in { "(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { def vlmul_trunc # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vv", "csilxfd", dst_lmul # "v">; + let RequiredFeatures = ["Zvfbfmin"] in + def vlmul_trunc_bf16 # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", + dst_lmul # "vv", "y", dst_lmul # "v">; def vlmul_trunc_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUv", "csil", dst_lmul # "Uv">; } @@ -2414,6 +2457,9 @@ let HasMasked = false, HasVL = false, IRName = "" in { "(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { def vlmul_ext # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vv", "csilxfd", dst_lmul # "v">; + let RequiredFeatures = ["Zvfbfmin"] in + def vlmul_ext_bf16 # dst_lmul : RVVBuiltin<"v" # dst_lmul # "v", + dst_lmul # "vv", "y", dst_lmul # "v">; def vlmul_ext_u # dst_lmul : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUv", "csil", dst_lmul # "Uv">; } @@ -2441,12 +2487,12 @@ let HasMasked = false, HasVL = false, IRName = "" in { } }] in { foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { - def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">; + def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfdy", dst_lmul # "v">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">; } foreach nf = NFList in { defvar T = "(Tuple:" # nf # ")"; - def : RVVBuiltin; + def : RVVBuiltin; def : RVVBuiltin; } } @@ -2474,11 +2520,15 @@ let HasMasked = false, HasVL = false, IRName = "" in { }] in { foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">; + let RequiredFeatures = ["Zvfbfmin"] in + def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "y">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">; } foreach nf = NFList in { defvar T = "(Tuple:" # nf # ")"; def : RVVBuiltin<"v" # T # "v", T # "v" # T # "vKzv", "csilxfd">; + let RequiredFeatures = ["Zvfbfmin"] in + def : RVVBuiltin<"v" # T # "v", T # "v" # T # "vKzv", "y">; def : RVVBuiltin<"Uv" # T # "Uv", T # "Uv" # T # "UvKzUv", "csil">; } } @@ -2523,7 +2573,9 @@ let HasMasked = false, HasVL = false, IRName = "" in { defvar T = "(Tuple:" # nf # ")"; defvar V = VString.S; defvar UV = VString.S; - def : RVVBuiltin; + def : RVVBuiltin; + let RequiredFeatures = ["Zvfbfmin"] in + def : RVVBuiltin; def : RVVBuiltin; } } @@ -2549,8 +2601,7 @@ multiclass RVVOutBuiltinSetZvk { if HasVS then { foreach vs2_lmul = ["(SEFixedLog2LMUL:-1)", "(SEFixedLog2LMUL:0)", - "(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)", - "(SEFixedLog2LMUL:3)"] in { + "(SEFixedLog2LMUL:1)", "(SEFixedLog2LMUL:2)"] in { defvar name = NAME # !if(!eq(NAME, "vaesz"), "", "_vs"); let OverloadedName = name, IRName = NAME # "_vs", Name = NAME # "_vs", IntrinsicTypes = [-1, 1] in diff --git a/clang/include/clang/ExtractAPI/API.h b/clang/include/clang/ExtractAPI/API.h index 92cacf65c7d64e585d00687d0121d071e3c6ca0d..d323e1668a72b1718ab62e24f139a6304b93cbdb 100644 --- a/clang/include/clang/ExtractAPI/API.h +++ b/clang/include/clang/ExtractAPI/API.h @@ -208,20 +208,20 @@ struct APIRecord { RK_ClassTemplate, RK_ClassTemplateSpecialization, RK_ClassTemplatePartialSpecialization, - RK_LastRecordContext, - RK_GlobalFunction, - RK_GlobalFunctionTemplate, - RK_GlobalFunctionTemplateSpecialization, + RK_StructField, + RK_UnionField, + RK_CXXField, + RK_StaticField, + RK_CXXFieldTemplate, RK_GlobalVariable, RK_GlobalVariableTemplate, RK_GlobalVariableTemplateSpecialization, RK_GlobalVariableTemplatePartialSpecialization, + RK_LastRecordContext, + RK_GlobalFunction, + RK_GlobalFunctionTemplate, + RK_GlobalFunctionTemplateSpecialization, RK_EnumConstant, - RK_StructField, - RK_UnionField, - RK_StaticField, - RK_CXXField, - RK_CXXFieldTemplate, RK_Concept, RK_CXXStaticMethod, RK_CXXInstanceMethod, @@ -321,6 +321,10 @@ public: RecordContext(APIRecord::RecordKind Kind) : Kind(Kind) {} + /// Append \p Other children chain into ours and empty out Other's record + /// chain. + void stealRecordChain(RecordContext &Other); + APIRecord::RecordKind getKind() const { return Kind; } struct record_iterator { @@ -370,6 +374,7 @@ private: APIRecord::RecordKind Kind; mutable APIRecord *First = nullptr; mutable APIRecord *Last = nullptr; + bool IsWellFormed() const; protected: friend class APISet; @@ -475,7 +480,7 @@ struct GlobalFunctionTemplateSpecializationRecord : GlobalFunctionRecord { }; /// This holds information associated with global functions. -struct GlobalVariableRecord : APIRecord { +struct GlobalVariableRecord : APIRecord, RecordContext { GlobalVariableRecord(StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, LinkageInfo Linkage, const DocComment &Comment, @@ -483,23 +488,28 @@ struct GlobalVariableRecord : APIRecord { DeclarationFragments SubHeading, bool IsFromSystemHeader) : APIRecord(RK_GlobalVariable, USR, Name, Parent, Loc, std::move(Availability), Linkage, Comment, Declaration, - SubHeading, IsFromSystemHeader) {} + SubHeading, IsFromSystemHeader), + RecordContext(RK_GlobalVariable) {} GlobalVariableRecord(RecordKind Kind, StringRef USR, StringRef Name, - SymbolReference Parent, - - PresumedLoc Loc, AvailabilityInfo Availability, - LinkageInfo Linkage, const DocComment &Comment, + SymbolReference Parent, PresumedLoc Loc, + AvailabilityInfo Availability, LinkageInfo Linkage, + const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, bool IsFromSystemHeader) : APIRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), Linkage, Comment, Declaration, SubHeading, - IsFromSystemHeader) {} + IsFromSystemHeader), + RecordContext(Kind) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); } - static bool classofKind(RecordKind K) { return K == RK_GlobalVariable; } + static bool classofKind(RecordKind K) { + return K == RK_GlobalVariable || K == RK_GlobalVariableTemplate || + K == RK_GlobalVariableTemplateSpecialization || + K == RK_GlobalVariableTemplatePartialSpecialization; + } private: virtual void anchor(); @@ -591,20 +601,47 @@ private: virtual void anchor(); }; +struct TagRecord : APIRecord, RecordContext { + TagRecord(RecordKind Kind, StringRef USR, StringRef Name, + SymbolReference Parent, PresumedLoc Loc, + AvailabilityInfo Availability, const DocComment &Comment, + DeclarationFragments Declaration, DeclarationFragments SubHeading, + bool IsFromSystemHeader, bool IsEmbeddedInVarDeclarator, + AccessControl Access = AccessControl()) + : APIRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), + LinkageInfo::none(), Comment, Declaration, SubHeading, + IsFromSystemHeader, std::move(Access)), + RecordContext(Kind), + IsEmbeddedInVarDeclarator(IsEmbeddedInVarDeclarator){}; + + static bool classof(const APIRecord *Record) { + return classofKind(Record->getKind()); + } + static bool classofKind(RecordKind K) { + return K == RK_Struct || K == RK_Union || K == RK_Enum; + } + + bool IsEmbeddedInVarDeclarator; + + virtual ~TagRecord() = 0; +}; + /// This holds information associated with enums. -struct EnumRecord : APIRecord, RecordContext { +struct EnumRecord : TagRecord { EnumRecord(StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(RK_Enum, USR, Name, Parent, Loc, std::move(Availability), - LinkageInfo::none(), Comment, Declaration, SubHeading, - IsFromSystemHeader), - RecordContext(RK_Enum) {} + DeclarationFragments SubHeading, bool IsFromSystemHeader, + bool IsEmbeddedInVarDeclarator, + AccessControl Access = AccessControl()) + : TagRecord(RK_Enum, USR, Name, Parent, Loc, std::move(Availability), + Comment, Declaration, SubHeading, IsFromSystemHeader, + IsEmbeddedInVarDeclarator, std::move(Access)) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); } + static bool classofKind(RecordKind K) { return K == RK_Enum; } private: @@ -612,7 +649,7 @@ private: }; /// This holds information associated with struct or union fields fields. -struct RecordFieldRecord : APIRecord { +struct RecordFieldRecord : APIRecord, RecordContext { RecordFieldRecord(RecordKind Kind, StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, @@ -620,7 +657,8 @@ struct RecordFieldRecord : APIRecord { DeclarationFragments SubHeading, bool IsFromSystemHeader) : APIRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, - IsFromSystemHeader) {} + IsFromSystemHeader), + RecordContext(Kind) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); @@ -633,16 +671,17 @@ struct RecordFieldRecord : APIRecord { }; /// This holds information associated with structs and unions. -struct RecordRecord : APIRecord, RecordContext { +struct RecordRecord : TagRecord { RecordRecord(RecordKind Kind, StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), - LinkageInfo::none(), Comment, Declaration, SubHeading, - IsFromSystemHeader), - RecordContext(Kind) {} + DeclarationFragments SubHeading, bool IsFromSystemHeader, + bool IsEmbeddedInVarDeclarator, + AccessControl Access = AccessControl()) + : TagRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), + Comment, Declaration, SubHeading, IsFromSystemHeader, + IsEmbeddedInVarDeclarator, std::move(Access)) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); @@ -651,6 +690,8 @@ struct RecordRecord : APIRecord, RecordContext { return K == RK_Struct || K == RK_Union; } + bool isAnonymousWithNoTypedef() { return Name.empty(); } + virtual ~RecordRecord() = 0; }; @@ -676,9 +717,11 @@ struct StructRecord : RecordRecord { StructRecord(StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader) + DeclarationFragments SubHeading, bool IsFromSystemHeader, + bool IsEmbeddedInVarDeclarator) : RecordRecord(RK_Struct, USR, Name, Parent, Loc, std::move(Availability), - Comment, Declaration, SubHeading, IsFromSystemHeader) {} + Comment, Declaration, SubHeading, IsFromSystemHeader, + IsEmbeddedInVarDeclarator) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); @@ -711,9 +754,11 @@ struct UnionRecord : RecordRecord { UnionRecord(StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, - DeclarationFragments SubHeading, bool IsFromSystemHeader) + DeclarationFragments SubHeading, bool IsFromSystemHeader, + bool IsEmbeddedInVarDeclarator) : RecordRecord(RK_Union, USR, Name, Parent, Loc, std::move(Availability), - Comment, Declaration, SubHeading, IsFromSystemHeader) {} + Comment, Declaration, SubHeading, IsFromSystemHeader, + IsEmbeddedInVarDeclarator) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); @@ -724,7 +769,7 @@ private: virtual void anchor(); }; -struct CXXFieldRecord : APIRecord { +struct CXXFieldRecord : APIRecord, RecordContext { CXXFieldRecord(StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, @@ -732,7 +777,8 @@ struct CXXFieldRecord : APIRecord { bool IsFromSystemHeader) : APIRecord(RK_CXXField, USR, Name, Parent, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, - IsFromSystemHeader, std::move(Access)) {} + IsFromSystemHeader, std::move(Access)), + RecordContext(RK_CXXField) {} CXXFieldRecord(RecordKind Kind, StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, @@ -742,7 +788,8 @@ struct CXXFieldRecord : APIRecord { bool IsFromSystemHeader) : APIRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), LinkageInfo::none(), Comment, Declaration, SubHeading, - IsFromSystemHeader, std::move(Access)) {} + IsFromSystemHeader, std::move(Access)), + RecordContext(Kind) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); @@ -1118,18 +1165,18 @@ struct ObjCContainerRecord : APIRecord, RecordContext { virtual ~ObjCContainerRecord() = 0; }; -struct CXXClassRecord : APIRecord, RecordContext { +struct CXXClassRecord : RecordRecord { SmallVector Bases; CXXClassRecord(StringRef USR, StringRef Name, SymbolReference Parent, PresumedLoc Loc, AvailabilityInfo Availability, const DocComment &Comment, DeclarationFragments Declaration, DeclarationFragments SubHeading, RecordKind Kind, - AccessControl Access, bool IsFromSystemHeader) - : APIRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), - LinkageInfo::none(), Comment, Declaration, SubHeading, - IsFromSystemHeader, std::move(Access)), - RecordContext(Kind) {} + AccessControl Access, bool IsFromSystemHeader, + bool IsEmbeddedInVarDeclarator = false) + : RecordRecord(Kind, USR, Name, Parent, Loc, std::move(Availability), + Comment, Declaration, SubHeading, IsFromSystemHeader, + IsEmbeddedInVarDeclarator, std::move(Access)) {} static bool classof(const APIRecord *Record) { return classofKind(Record->getKind()); diff --git a/clang/include/clang/ExtractAPI/APIRecords.inc b/clang/include/clang/ExtractAPI/APIRecords.inc index 15fee809656d9a4b5e50ba7b1f8c2ff88978128e..4cda4ef2f9be63f14b4922f09bd08ab0cafd3889 100644 --- a/clang/include/clang/ExtractAPI/APIRecords.inc +++ b/clang/include/clang/ExtractAPI/APIRecords.inc @@ -35,10 +35,11 @@ CONCRETE_RECORD(GlobalVariableTemplateSpecializationRecord, CONCRETE_RECORD(GlobalVariableTemplatePartialSpecializationRecord, GlobalVariableRecord, RK_GlobalVariableTemplatePartialSpecialization) +ABSTRACT_RECORD(TagRecord, APIRecord) CONCRETE_RECORD(EnumConstantRecord, APIRecord, RK_EnumConstant) -CONCRETE_RECORD(EnumRecord, APIRecord, RK_Enum) +CONCRETE_RECORD(EnumRecord, TagRecord, RK_Enum) ABSTRACT_RECORD(RecordFieldRecord, APIRecord) -ABSTRACT_RECORD(RecordRecord, APIRecord) +ABSTRACT_RECORD(RecordRecord, TagRecord) CONCRETE_RECORD(StructFieldRecord, RecordFieldRecord, RK_StructField) CONCRETE_RECORD(StructRecord, APIRecord, RK_Struct) CONCRETE_RECORD(UnionFieldRecord, RecordFieldRecord, RK_UnionField) @@ -99,5 +100,16 @@ RECORD_CONTEXT(ClassTemplateSpecializationRecord, RK_ClassTemplateSpecialization) RECORD_CONTEXT(ClassTemplatePartialSpecializationRecord, RK_ClassTemplatePartialSpecialization) +RECORD_CONTEXT(StructFieldRecord, RK_StructField) +RECORD_CONTEXT(UnionFieldRecord, RK_UnionField) +RECORD_CONTEXT(CXXFieldRecord, RK_CXXField) +RECORD_CONTEXT(StaticFieldRecord, RK_StaticField) +RECORD_CONTEXT(CXXFieldTemplateRecord, RK_CXXFieldTemplate) +RECORD_CONTEXT(GlobalVariableRecord, RK_GlobalVariable) +RECORD_CONTEXT(GlobalVariableTemplateRecord, RK_GlobalVariableTemplate) +RECORD_CONTEXT(GlobalVariableTemplateSpecializationRecord, + RK_GlobalVariableTemplateSpecialization) +RECORD_CONTEXT(GlobalVariableTemplatePartialSpecializationRecord, + RK_GlobalVariableTemplatePartialSpecialization) #undef RECORD_CONTEXT diff --git a/clang/include/clang/ExtractAPI/DeclarationFragments.h b/clang/include/clang/ExtractAPI/DeclarationFragments.h index 94392c185165951c39adad41cd402f83cd30119c..535da90b98284ba54f868eb4ea92d594da68c1f7 100644 --- a/clang/include/clang/ExtractAPI/DeclarationFragments.h +++ b/clang/include/clang/ExtractAPI/DeclarationFragments.h @@ -27,6 +27,8 @@ #include "clang/AST/TypeLoc.h" #include "clang/Basic/Specifiers.h" #include "clang/Lex/MacroInfo.h" +#include +#include #include namespace clang { @@ -113,28 +115,26 @@ public: ConstFragmentIterator cend() const { return Fragments.cend(); } - // Add a new Fragment at an arbitrary offset. - DeclarationFragments &insert(FragmentIterator It, StringRef Spelling, - FragmentKind Kind, - StringRef PreciseIdentifier = "", - const Decl *Declaration = nullptr) { - Fragments.insert(It, - Fragment(Spelling, Kind, PreciseIdentifier, Declaration)); - return *this; + /// Prepend another DeclarationFragments to the beginning. + /// + /// \returns a reference to the DeclarationFragments object itself after + /// appending to chain up consecutive operations. + DeclarationFragments &prepend(DeclarationFragments Other) { + return insert(begin(), std::move(Other)); } - DeclarationFragments &insert(FragmentIterator It, - DeclarationFragments &&Other) { - Fragments.insert(It, std::make_move_iterator(Other.Fragments.begin()), - std::make_move_iterator(Other.Fragments.end())); - Other.Fragments.clear(); - return *this; + /// Append another DeclarationFragments to the end. + /// + /// \returns a reference to the DeclarationFragments object itself after + /// appending to chain up consecutive operations. + DeclarationFragments &append(DeclarationFragments Other) { + return insert(end(), std::move(Other)); } /// Append a new Fragment to the end of the Fragments. /// /// \returns a reference to the DeclarationFragments object itself after - /// appending to chain up consecutive appends. + /// appending to chain up consecutive operations. DeclarationFragments &append(StringRef Spelling, FragmentKind Kind, StringRef PreciseIdentifier = "", const Decl *Declaration = nullptr) { @@ -149,18 +149,48 @@ public: return *this; } - /// Append another DeclarationFragments to the end. - /// - /// Note: \p Other is moved from and cannot be used after a call to this - /// method. + /// Inserts another DeclarationFragments at \p It. /// /// \returns a reference to the DeclarationFragments object itself after - /// appending to chain up consecutive appends. - DeclarationFragments &append(DeclarationFragments &&Other) { - Fragments.insert(Fragments.end(), - std::make_move_iterator(Other.Fragments.begin()), - std::make_move_iterator(Other.Fragments.end())); - Other.Fragments.clear(); + /// appending to chain up consecutive operations. + DeclarationFragments &insert(FragmentIterator It, + DeclarationFragments Other) { + if (Other.Fragments.empty()) + return *this; + + if (Fragments.empty()) { + Fragments = std::move(Other.Fragments); + return *this; + } + + const auto &OtherFrags = Other.Fragments; + auto ToInsertBegin = std::make_move_iterator(Other.begin()); + auto ToInsertEnd = std::make_move_iterator(Other.end()); + + // If we aren't inserting at the end let's make sure that we merge their + // last fragment with It if both are text fragments. + if (It != end() && It->Kind == FragmentKind::Text && + OtherFrags.back().Kind == FragmentKind::Text) { + auto &TheirBackSpelling = OtherFrags.back().Spelling; + It->Spelling.reserve(It->Spelling.size() + TheirBackSpelling.size()); + It->Spelling.insert(It->Spelling.begin(), TheirBackSpelling.begin(), + TheirBackSpelling.end()); + --ToInsertEnd; + } + + // If we aren't inserting at the beginning we want to merge their first + // fragment with the fragment before It if both are text fragments. + if (It != begin() && std::prev(It)->Kind == FragmentKind::Text && + OtherFrags.front().Kind == FragmentKind::Text) { + auto PrevIt = std::prev(It); + auto &TheirFrontSpelling = OtherFrags.front().Spelling; + PrevIt->Spelling.reserve(PrevIt->Spelling.size() + + TheirFrontSpelling.size()); + PrevIt->Spelling.append(TheirFrontSpelling); + ++ToInsertBegin; + } + + Fragments.insert(It, ToInsertBegin, ToInsertEnd); return *this; } @@ -177,13 +207,13 @@ public: /// Append a text Fragment of a space character. /// /// \returns a reference to the DeclarationFragments object itself after - /// appending to chain up consecutive appends. + /// appending to chain up consecutive operations. DeclarationFragments &appendSpace(); /// Append a text Fragment of a semicolon character. /// /// \returns a reference to the DeclarationFragments object itself after - /// appending to chain up consecutive appends. + /// appending to chain up consecutive operations. DeclarationFragments &appendSemicolon(); /// Removes a trailing semicolon character if present. diff --git a/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h b/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h index 4cb866892b5d00d10c7a3f70c2174b35f103563b..97cc457ea2a9263c8ce4b5910fc85b56a0c98755 100644 --- a/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h +++ b/clang/include/clang/ExtractAPI/ExtractAPIVisitor.h @@ -224,6 +224,29 @@ protected: return API.createSymbolReference(Name, USR, getOwningModuleName(D)); } + + bool isEmbeddedInVarDeclarator(const TagDecl &D) { + return D.getName().empty() && getTypedefName(&D).empty() && + D.isEmbeddedInDeclarator(); + } + + void maybeMergeWithAnonymousTag(const DeclaratorDecl &D, + RecordContext *NewRecordContext) { + if (!NewRecordContext) + return; + auto *Tag = D.getType()->getAsTagDecl(); + SmallString<128> TagUSR; + clang::index::generateUSRForDecl(Tag, TagUSR); + if (auto *Record = llvm::dyn_cast_if_present( + API.findRecordForUSR(TagUSR))) { + if (Record->IsEmbeddedInVarDeclarator) { + NewRecordContext->stealRecordChain(*Record); + auto *NewRecord = cast(NewRecordContext); + if (NewRecord->Comment.empty()) + NewRecord->Comment = Record->Comment; + } + } + } }; template @@ -273,12 +296,18 @@ bool ExtractAPIVisitorBase::VisitVarDecl(const VarDecl *Decl) { USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, Declaration, SubHeading, Access, isInSystemHeader(Decl)); - } else + } else { // Add the global variable record to the API set. - API.createRecord( + auto *NewRecord = API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Linkage, Comment, Declaration, SubHeading, isInSystemHeader(Decl)); + + // If this global variable has a non typedef'd anonymous tag type let's + // pretend the type's child records are under us in the hierarchy. + maybeMergeWithAnonymousTag(*Decl, NewRecord); + } + return true; } @@ -364,7 +393,7 @@ bool ExtractAPIVisitorBase::VisitEnumDecl(const EnumDecl *Decl) { if (Name.empty()) { llvm::raw_svector_ostream OS(QualifiedNameBuffer); Decl->printQualifiedName(OS); - Name = QualifiedNameBuffer.str(); + Name = QualifiedNameBuffer; } SmallString<128> USR; @@ -385,7 +414,7 @@ bool ExtractAPIVisitorBase::VisitEnumDecl(const EnumDecl *Decl) { auto *ER = API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, SubHeading, - isInSystemHeader(Decl)); + isInSystemHeader(Decl), isEmbeddedInVarDeclarator(*Decl)); // Now collect information about the enumerators in this enum. getDerivedExtractAPIVisitor().recordEnumConstants(ER, Decl->enumerators()); @@ -510,16 +539,10 @@ bool ExtractAPIVisitorBase::VisitRecordDecl(const RecordDecl *Decl) { if (!getDerivedExtractAPIVisitor().shouldDeclBeIncluded(Decl)) return true; - SmallString<128> QualifiedNameBuffer; // Collect symbol information. StringRef Name = Decl->getName(); if (Name.empty()) Name = getTypedefName(Decl); - if (Name.empty()) { - llvm::raw_svector_ostream OS(QualifiedNameBuffer); - Decl->printQualifiedName(OS); - Name = QualifiedNameBuffer.str(); - } SmallString<128> USR; index::generateUSRForDecl(Decl, USR); @@ -541,12 +564,12 @@ bool ExtractAPIVisitorBase::VisitRecordDecl(const RecordDecl *Decl) { API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, - SubHeading, isInSystemHeader(Decl)); + SubHeading, isInSystemHeader(Decl), isEmbeddedInVarDeclarator(*Decl)); else API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, - SubHeading, isInSystemHeader(Decl)); + SubHeading, isInSystemHeader(Decl), isEmbeddedInVarDeclarator(*Decl)); return true; } @@ -559,6 +582,9 @@ bool ExtractAPIVisitorBase::VisitCXXRecordDecl( return true; StringRef Name = Decl->getName(); + if (Name.empty()) + Name = getTypedefName(Decl); + SmallString<128> USR; index::generateUSRForDecl(Decl, USR); PresumedLoc Loc = @@ -585,8 +611,7 @@ bool ExtractAPIVisitorBase::VisitCXXRecordDecl( CXXClassRecord *Record; if (Decl->getDescribedClassTemplate()) { // Inject template fragments before class fragments. - Declaration.insert( - Declaration.begin(), + Declaration.prepend( DeclarationFragmentsBuilder::getFragmentsForRedeclarableTemplate( Decl->getDescribedClassTemplate())); Record = API.createRecord( @@ -598,7 +623,8 @@ bool ExtractAPIVisitorBase::VisitCXXRecordDecl( Record = API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, - SubHeading, Kind, Access, isInSystemHeader(Decl)); + SubHeading, Kind, Access, isInSystemHeader(Decl), + isEmbeddedInVarDeclarator(*Decl)); Record->Bases = getBases(Decl); @@ -1075,18 +1101,17 @@ bool ExtractAPIVisitorBase::VisitTypedefNameDecl( // If the underlying type was defined as part of the typedef modify it's // fragments directly and pretend the typedef doesn't exist. if (auto *TagDecl = Decl->getUnderlyingType()->getAsTagDecl()) { - if (TagDecl->getName() == Decl->getName() && - TagDecl->isEmbeddedInDeclarator() && TagDecl->isCompleteDefinition()) { + if (TagDecl->isEmbeddedInDeclarator() && TagDecl->isCompleteDefinition() && + Decl->getName() == TagDecl->getName()) { SmallString<128> TagUSR; index::generateUSRForDecl(TagDecl, TagUSR); if (auto *Record = API.findRecordForUSR(TagUSR)) { DeclarationFragments LeadingFragments; LeadingFragments.append("typedef", - DeclarationFragments::FragmentKind::Keyword, "", - nullptr); + DeclarationFragments::FragmentKind::Keyword); LeadingFragments.appendSpace(); Record->Declaration.removeTrailingSemicolon() - .insert(Record->Declaration.begin(), std::move(LeadingFragments)) + .prepend(std::move(LeadingFragments)) .append(" { ... } ", DeclarationFragments::FragmentKind::Text) .append(Name, DeclarationFragments::FragmentKind::Identifier) .appendSemicolon(); @@ -1221,26 +1246,31 @@ bool ExtractAPIVisitorBase::VisitFieldDecl(const FieldDecl *Decl) { DeclarationFragments SubHeading = DeclarationFragmentsBuilder::getSubHeading(Decl); + RecordContext *NewRecord = nullptr; if (isa(Decl->getDeclContext())) { AccessControl Access = DeclarationFragmentsBuilder::getAccessControl(Decl); - API.createRecord( + NewRecord = API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, SubHeading, Access, isInSystemHeader(Decl)); } else if (auto *RD = dyn_cast(Decl->getDeclContext())) { if (RD->isUnion()) - API.createRecord( + NewRecord = API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, SubHeading, isInSystemHeader(Decl)); else - API.createRecord( + NewRecord = API.createRecord( USR, Name, createHierarchyInformationForDecl(*Decl), Loc, AvailabilityInfo::createFromDecl(Decl), Comment, Declaration, SubHeading, isInSystemHeader(Decl)); } + // If this field has a non typedef'd anonymous tag type let's pretend the + // type's child records are under us in the hierarchy. + maybeMergeWithAnonymousTag(*Decl, NewRecord); + return true; } diff --git a/clang/include/clang/Lex/HeaderSearch.h b/clang/include/clang/Lex/HeaderSearch.h index c5f90ef4cb3682a35f0869f81ff3f5a433ca396f..5ac63dddd4d4eaeb8a3db65fef5715da99add5e3 100644 --- a/clang/include/clang/Lex/HeaderSearch.h +++ b/clang/include/clang/Lex/HeaderSearch.h @@ -56,6 +56,12 @@ class TargetInfo; /// The preprocessor keeps track of this information for each /// file that is \#included. struct HeaderFileInfo { + // TODO: Whether the file was included is not a property of the file itself. + // It's a preprocessor state, move it there. + /// True if this file has been included (or imported) **locally**. + LLVM_PREFERRED_TYPE(bool) + unsigned IsLocallyIncluded : 1; + // TODO: Whether the file was imported is not a property of the file itself. // It's a preprocessor state, move it there. /// True if this is a \#import'd file. @@ -135,10 +141,10 @@ struct HeaderFileInfo { StringRef Framework; HeaderFileInfo() - : isImport(false), isPragmaOnce(false), DirInfo(SrcMgr::C_User), - External(false), isModuleHeader(false), isTextualModuleHeader(false), - isCompilingModuleHeader(false), Resolved(false), - IndexHeaderMapHeader(false), IsValid(false) {} + : IsLocallyIncluded(false), isImport(false), isPragmaOnce(false), + DirInfo(SrcMgr::C_User), External(false), isModuleHeader(false), + isTextualModuleHeader(false), isCompilingModuleHeader(false), + Resolved(false), IndexHeaderMapHeader(false), IsValid(false) {} /// Retrieve the controlling macro for this header file, if /// any. diff --git a/clang/include/clang/Support/RISCVVIntrinsicUtils.h b/clang/include/clang/Support/RISCVVIntrinsicUtils.h index ef9d6c15724b68856f8ed99e7be0e4af4338da43..97493bae5656e90695f42a513ef27820d06e0453 100644 --- a/clang/include/clang/Support/RISCVVIntrinsicUtils.h +++ b/clang/include/clang/Support/RISCVVIntrinsicUtils.h @@ -502,7 +502,8 @@ enum RVVRequire : uint32_t { RVV_REQ_Zvksed = 1 << 14, RVV_REQ_Zvksh = 1 << 15, RVV_REQ_Zvfbfwma = 1 << 16, - RVV_REQ_Experimental = 1 << 17, + RVV_REQ_Zvfbfmin = 1 << 17, + RVV_REQ_Experimental = 1 << 18, LLVM_MARK_AS_BITMASK_ENUM(RVV_REQ_Experimental) }; diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index 78580b5b1c1063cd5f39f44ca20dbafff121818a..9fa42e75bbfd147fcf73b9ef32c63eb70dfa97ed 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -16,7 +16,7 @@ #include "clang/Basic/TargetInfo.h" #include "clang/Basic/TargetOptions.h" #include "llvm/Support/Compiler.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/Triple.h" #include diff --git a/clang/lib/Basic/Targets/WebAssembly.cpp b/clang/lib/Basic/Targets/WebAssembly.cpp index f1c925d90cb649f562e54618d92b5c2c7ec57fc3..d473fd19086460ba508499e5bddad840a789912f 100644 --- a/clang/lib/Basic/Targets/WebAssembly.cpp +++ b/clang/lib/Basic/Targets/WebAssembly.cpp @@ -148,18 +148,18 @@ bool WebAssemblyTargetInfo::initFeatureMap( llvm::StringMap &Features, DiagnosticsEngine &Diags, StringRef CPU, const std::vector &FeaturesVec) const { if (CPU == "bleeding-edge") { - Features["nontrapping-fptoint"] = true; - Features["sign-ext"] = true; - Features["bulk-memory"] = true; Features["atomics"] = true; + Features["bulk-memory"] = true; + Features["multimemory"] = true; Features["mutable-globals"] = true; - Features["tail-call"] = true; + Features["nontrapping-fptoint"] = true; Features["reference-types"] = true; - Features["multimemory"] = true; + Features["sign-ext"] = true; + Features["tail-call"] = true; setSIMDLevel(Features, SIMD128, true); } else if (CPU == "generic") { - Features["sign-ext"] = true; Features["mutable-globals"] = true; + Features["sign-ext"] = true; } return TargetInfo::initFeatureMap(Features, Diags, CPU, FeaturesVec); diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index 7e5f2edfc732cce0c7d0cc309f94b69b71a61a76..e67a600c1cdd77f6f3fb3ea5838fd10315574204 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -822,8 +822,9 @@ CodeGenFunction::evaluateOrEmitBuiltinObjectSize(const Expr *E, unsigned Type, return ConstantInt::get(ResType, ObjectSize, /*isSigned=*/true); } -const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberField( - ASTContext &Ctx, const RecordDecl *RD, StringRef Name, uint64_t &Offset) { +const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberFieldAndOffset( + ASTContext &Ctx, const RecordDecl *RD, const FieldDecl *FAMDecl, + uint64_t &Offset) { const LangOptions::StrictFlexArraysLevelKind StrictFlexArraysLevel = getLangOpts().getStrictFlexArraysLevel(); uint32_t FieldNo = 0; @@ -832,7 +833,7 @@ const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberField( return nullptr; for (const FieldDecl *FD : RD->fields()) { - if ((Name.empty() || FD->getNameAsString() == Name) && + if ((!FAMDecl || FD == FAMDecl) && Decl::isFlexibleArrayMemberLike( Ctx, FD, FD->getType(), StrictFlexArraysLevel, /*IgnoreTemplateOrMacroSubstitution=*/true)) { @@ -843,8 +844,8 @@ const FieldDecl *CodeGenFunction::FindFlexibleArrayMemberField( QualType Ty = FD->getType(); if (Ty->isRecordType()) { - if (const FieldDecl *Field = FindFlexibleArrayMemberField( - Ctx, Ty->getAsRecordDecl(), Name, Offset)) { + if (const FieldDecl *Field = FindFlexibleArrayMemberFieldAndOffset( + Ctx, Ty->getAsRecordDecl(), FAMDecl, Offset)) { const ASTRecordLayout &Layout = Ctx.getASTRecordLayout(RD); Offset += Layout.getFieldOffset(FieldNo); return Field; @@ -930,12 +931,14 @@ CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, // Get the flexible array member Decl. const RecordDecl *OuterRD = nullptr; - std::string FAMName; + const FieldDecl *FAMDecl = nullptr; if (const auto *ME = dyn_cast(Base)) { // Check if \p Base is referencing the FAM itself. const ValueDecl *VD = ME->getMemberDecl(); OuterRD = VD->getDeclContext()->getOuterLexicalRecordContext(); - FAMName = VD->getNameAsString(); + FAMDecl = dyn_cast(VD); + if (!FAMDecl) + return nullptr; } else if (const auto *DRE = dyn_cast(Base)) { // Check if we're pointing to the whole struct. QualType Ty = DRE->getDecl()->getType(); @@ -974,9 +977,11 @@ CodeGenFunction::emitFlexibleArrayMemberSize(const Expr *E, unsigned Type, if (!OuterRD) return nullptr; + // We call FindFlexibleArrayMemberAndOffset even if FAMDecl is non-null to + // get its offset. uint64_t Offset = 0; - const FieldDecl *FAMDecl = - FindFlexibleArrayMemberField(Ctx, OuterRD, FAMName, Offset); + FAMDecl = + FindFlexibleArrayMemberFieldAndOffset(Ctx, OuterRD, FAMDecl, Offset); Offset = Ctx.toCharUnitsFromBits(Offset).getQuantity(); if (!FAMDecl || !FAMDecl->getType()->isCountAttributedType()) diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index ff1873325d409fe758ddc1665d597b6ae2d0accc..a751649cdb597a520778c43ec9b98b8f4a53c310 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -3204,12 +3204,12 @@ public: llvm::Value *Index, QualType IndexType, QualType IndexedType, bool Accessed); - // Find a struct's flexible array member. It may be embedded inside multiple - // sub-structs, but must still be the last field. - const FieldDecl *FindFlexibleArrayMemberField(ASTContext &Ctx, - const RecordDecl *RD, - StringRef Name, - uint64_t &Offset); + // Find a struct's flexible array member and get its offset. It may be + // embedded inside multiple sub-structs, but must still be the last field. + const FieldDecl * + FindFlexibleArrayMemberFieldAndOffset(ASTContext &Ctx, const RecordDecl *RD, + const FieldDecl *FAMDecl, + uint64_t &Offset); /// Find the FieldDecl specified in a FAM's "counted_by" attribute. Returns /// \p nullptr if either the attribute or the field doesn't exist. diff --git a/clang/lib/CodeGen/CodeGenModule.cpp b/clang/lib/CodeGen/CodeGenModule.cpp index 0c447b20cef40d6098b2c742a632ddeaf4ba64b3..d085e735ecb443a1bc59f9dea2ba4ae319ac56ae 100644 --- a/clang/lib/CodeGen/CodeGenModule.cpp +++ b/clang/lib/CodeGen/CodeGenModule.cpp @@ -68,9 +68,9 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ConvertUTF.h" #include "llvm/Support/ErrorHandling.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/TimeProfiler.h" #include "llvm/Support/xxhash.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/Triple.h" #include "llvm/TargetParser/X86TargetParser.h" #include diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 0da92001e08c2701481b697ab3a30d7be6913bd7..76b7b9fdfb4f9b0cc8a82c1f69d534443b483fcc 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -87,12 +87,12 @@ #include "llvm/Support/PrettyStackTrace.h" #include "llvm/Support/Process.h" #include "llvm/Support/Program.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/Regex.h" #include "llvm/Support/StringSaver.h" #include "llvm/Support/VirtualFileSystem.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Host.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include // ::getenv #include #include diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index 4e6362a0f40632246ae10abc6512d703332164f0..07965b487ea79be0618244e140eda5d8a747cd68 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -617,8 +617,7 @@ void amdgpu::Linker::ConstructJob(Compilation &C, const JobAction &JA, const InputInfoList &Inputs, const ArgList &Args, const char *LinkingOutput) const { - - std::string Linker = getToolChain().GetProgramPath(getShortName()); + std::string Linker = getToolChain().GetLinkerPath(); ArgStringList CmdArgs; CmdArgs.push_back("--no-undefined"); CmdArgs.push_back("-shared"); diff --git a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp index 96b3cc3bb8ffb1620afb43ca88f17e44827931a7..2e2bce8494672fe0e29086fbf768de1d3c256b31 100644 --- a/clang/lib/Driver/ToolChains/Arch/RISCV.cpp +++ b/clang/lib/Driver/ToolChains/Arch/RISCV.cpp @@ -15,9 +15,9 @@ #include "clang/Driver/Options.h" #include "llvm/Option/ArgList.h" #include "llvm/Support/Error.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/Host.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/RISCVTargetParser.h" using namespace clang::driver; diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index e7ccf9a23e7eda2dc7b4866fc7feeddbef054202..5f5d720cf759f4a29a94b1c5bfc9fac80a5cf893 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -54,11 +54,11 @@ #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/YAMLParser.h" #include "llvm/TargetParser/ARMTargetParserCommon.h" #include "llvm/TargetParser/Host.h" #include "llvm/TargetParser/LoongArchTargetParser.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/RISCVTargetParser.h" #include diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index abe0b931676005c00de472e432051db124f6785d..6d93c1f3d7034a02dd8beed312e7b0457ba67bd6 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -15,7 +15,7 @@ #include "llvm/Frontend/Debug/Options.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/RISCVTargetParser.h" #include diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index dedbfac6cb25d26b67587d4ed273597366f1296d..f55b8bf48c13f781a69eaf464b60123618bd022b 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -30,8 +30,8 @@ #include "llvm/Option/ArgList.h" #include "llvm/Support/CodeGen.h" #include "llvm/Support/Path.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/VirtualFileSystem.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/TargetParser.h" #include diff --git a/clang/lib/ExtractAPI/API.cpp b/clang/lib/ExtractAPI/API.cpp index 5a62c5deb240836aeeb4c73d54b7c3faa371db16..96bef967d8591a248f384e330fa7948d3e3269fb 100644 --- a/clang/lib/ExtractAPI/API.cpp +++ b/clang/lib/ExtractAPI/API.cpp @@ -54,7 +54,28 @@ RecordContext *APIRecord::castToRecordContext(const APIRecord *Record) { } } +bool RecordContext::IsWellFormed() const { + // Check that First and Last are both null or both non-null. + return (First == nullptr) == (Last == nullptr); +} + +void RecordContext::stealRecordChain(RecordContext &Other) { + assert(IsWellFormed()); + // If we don't have an empty chain append Other's chain into ours. + if (First) + Last->NextInContext = Other.First; + else + First = Other.First; + + Last = Other.Last; + + // Delete Other's chain to ensure we don't accidentally traverse it. + Other.First = nullptr; + Other.Last = nullptr; +} + void RecordContext::addToRecordChain(APIRecord *Record) const { + assert(IsWellFormed()); if (!First) { First = Record; Last = Record; @@ -95,6 +116,7 @@ SymbolReference APISet::createSymbolReference(StringRef Name, StringRef USR, } APIRecord::~APIRecord() {} +TagRecord::~TagRecord() {} RecordRecord::~RecordRecord() {} RecordFieldRecord::~RecordFieldRecord() {} ObjCContainerRecord::~ObjCContainerRecord() {} diff --git a/clang/lib/ExtractAPI/DeclarationFragments.cpp b/clang/lib/ExtractAPI/DeclarationFragments.cpp index 0a243120b7c0e35c409ca7a70a269d2a7ff0ac08..9bf7950888dbb2566fad2c6765695967d1ad58c9 100644 --- a/clang/lib/ExtractAPI/DeclarationFragments.cpp +++ b/clang/lib/ExtractAPI/DeclarationFragments.cpp @@ -396,7 +396,8 @@ DeclarationFragments DeclarationFragmentsBuilder::getFragmentsForType( const TagDecl *Decl = TagTy->getDecl(); // Anonymous decl, skip this fragment. if (Decl->getName().empty()) - return Fragments; + return Fragments.append("{ ... }", + DeclarationFragments::FragmentKind::Text); SmallString<128> TagUSR; clang::index::generateUSRForDecl(Decl, TagUSR); return Fragments.append(Decl->getName(), @@ -743,11 +744,16 @@ DeclarationFragmentsBuilder::getFragmentsForEnum(const EnumDecl *EnumDecl) { QualType IntegerType = EnumDecl->getIntegerType(); if (!IntegerType.isNull()) - Fragments.append(": ", DeclarationFragments::FragmentKind::Text) + Fragments.appendSpace() + .append(": ", DeclarationFragments::FragmentKind::Text) .append( getFragmentsForType(IntegerType, EnumDecl->getASTContext(), After)) .append(std::move(After)); + if (EnumDecl->getName().empty()) + Fragments.appendSpace().append("{ ... }", + DeclarationFragments::FragmentKind::Text); + return Fragments.appendSemicolon(); } @@ -778,9 +784,12 @@ DeclarationFragments DeclarationFragmentsBuilder::getFragmentsForRecordDecl( else Fragments.append("struct", DeclarationFragments::FragmentKind::Keyword); + Fragments.appendSpace(); if (!Record->getName().empty()) - Fragments.appendSpace().append( - Record->getName(), DeclarationFragments::FragmentKind::Identifier); + Fragments.append(Record->getName(), + DeclarationFragments::FragmentKind::Identifier); + else + Fragments.append("{ ... }", DeclarationFragments::FragmentKind::Text); return Fragments.appendSemicolon(); } diff --git a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp index 8b1dcb4a4144f4044a1f7f8e7c3cb6204c2834a1..34278b5d40c4221931624b7efc2164edeb5d11a3 100644 --- a/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp +++ b/clang/lib/ExtractAPI/Serialization/SymbolGraphSerializer.cpp @@ -667,6 +667,14 @@ bool SymbolGraphSerializer::shouldSkip(const APIRecord *Record) const { if (Record->Availability.isUnconditionallyUnavailable()) return true; + // Filter out symbols without a name as we can generate correct symbol graphs + // for them. In practice these are anonymous record types that aren't attached + // to a declaration. + if (auto *Tag = dyn_cast(Record)) { + if (Tag->IsEmbeddedInVarDeclarator) + return true; + } + // Filter out symbols prefixed with an underscored as they are understood to // be symbols clients should not use. if (Record->Name.starts_with("_")) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 603268f771ac5226165ba33e30c0c97918c11c4a..6e4e6901e473f72dbe204c2b78645644d467252f 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -819,8 +819,11 @@ FormatToken *UnwrappedLineParser::parseBlock(bool MustBeDeclaration, return IfLBrace; } - if (FormatTok->is(tok::r_brace) && Tok->is(TT_NamespaceLBrace)) - FormatTok->setFinalizedType(TT_NamespaceRBrace); + if (FormatTok->is(tok::r_brace)) { + FormatTok->setBlockKind(BK_Block); + if (Tok->is(TT_NamespaceLBrace)) + FormatTok->setFinalizedType(TT_NamespaceRBrace); + } const bool IsFunctionRBrace = FormatTok->is(tok::r_brace) && Tok->is(TT_FunctionLBrace); @@ -3910,6 +3913,8 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { const FormatToken &InitialToken = *FormatTok; nextToken(); + const FormatToken *ClassName = nullptr; + bool IsDerived = false; auto IsNonMacroIdentifier = [](const FormatToken *Tok) { return Tok->is(tok::identifier) && Tok->TokenText != Tok->TokenText.upper(); }; @@ -3934,15 +3939,35 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { } if (FormatTok->is(tok::l_square) && handleCppAttributes()) continue; + const auto *Previous = FormatTok; nextToken(); - // We can have macros in between 'class' and the class name. - if (!IsNonMacroIdentifier(FormatTok->Previous) && - FormatTok->is(tok::l_paren)) { - parseParens(); + switch (FormatTok->Tok.getKind()) { + case tok::l_paren: + // We can have macros in between 'class' and the class name. + if (!IsNonMacroIdentifier(Previous)) + parseParens(); + break; + case tok::coloncolon: + break; + default: + if (!ClassName && Previous->is(tok::identifier)) + ClassName = Previous; } } + auto IsListInitialization = [&] { + if (!ClassName || IsDerived) + return false; + assert(FormatTok->is(tok::l_brace)); + const auto *Prev = FormatTok->getPreviousNonComment(); + assert(Prev); + return Prev != ClassName && Prev->is(tok::identifier) && + Prev->isNot(Keywords.kw_final) && tryToParseBracedList(); + }; + if (FormatTok->isOneOf(tok::colon, tok::less)) { + if (FormatTok->is(tok::colon)) + IsDerived = true; int AngleNestingLevel = 0; do { if (FormatTok->is(tok::less)) @@ -3955,6 +3980,8 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { break; } if (FormatTok->is(tok::l_brace)) { + if (AngleNestingLevel == 0 && IsListInitialization()) + return; calculateBraceTypes(/*ExpectClassBody=*/true); if (!tryToParseBracedList()) break; @@ -3999,6 +4026,8 @@ void UnwrappedLineParser::parseRecord(bool ParseAsExpr) { } }; if (FormatTok->is(tok::l_brace)) { + if (IsListInitialization()) + return; auto [OpenBraceType, ClosingBraceType] = GetBraceTypes(InitialToken); FormatTok->setFinalizedType(OpenBraceType); if (ParseAsExpr) { diff --git a/clang/lib/Lex/HeaderSearch.cpp b/clang/lib/Lex/HeaderSearch.cpp index 0632882b2961469c2c905b4c8a951e6bb6683937..574723b33866af4577ca052bebfa48c75d548a36 100644 --- a/clang/lib/Lex/HeaderSearch.cpp +++ b/clang/lib/Lex/HeaderSearch.cpp @@ -1574,6 +1574,7 @@ bool HeaderSearch::ShouldEnterIncludeFile(Preprocessor &PP, } } + FileInfo.IsLocallyIncluded = true; IsFirstIncludeOfFile = PP.markIncluded(File); return true; } diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index 51757f4cf727d6433144bf664637a3b9900f0da9..67132701b41cfd77574d6bac44c0dedf15f9d7c5 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -7953,7 +7953,8 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, // For variadic functions, we may have more args than parameters. // For some K&R functions, we may have less args than parameters. const auto N = std::min(Proto->getNumParams(), Args.size()); - bool AnyScalableArgsOrRet = Proto->getReturnType()->isSizelessVectorType(); + bool IsScalableRet = Proto->getReturnType()->isSizelessVectorType(); + bool IsScalableArg = false; for (unsigned ArgIdx = 0; ArgIdx < N; ++ArgIdx) { // Args[ArgIdx] can be null in malformed code. if (const Expr *Arg = Args[ArgIdx]) { @@ -7968,7 +7969,7 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, QualType ParamTy = Proto->getParamType(ArgIdx); if (ParamTy->isSizelessVectorType()) - AnyScalableArgsOrRet = true; + IsScalableArg = true; QualType ArgTy = Arg->getType(); CheckArgAlignment(Arg->getExprLoc(), FDecl, std::to_string(ArgIdx + 1), ArgTy, ParamTy); @@ -7993,7 +7994,8 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, // arguments or return values, then warn the user that the streaming and // non-streaming vector lengths may be different. const auto *CallerFD = dyn_cast(CurContext); - if (CallerFD && (!FD || !FD->getBuiltinID()) && AnyScalableArgsOrRet) { + if (CallerFD && (!FD || !FD->getBuiltinID()) && + (IsScalableArg || IsScalableRet)) { bool IsCalleeStreaming = ExtInfo.AArch64SMEAttributes & FunctionType::SME_PStateSMEnabledMask; bool IsCalleeStreamingCompatible = @@ -8002,8 +8004,14 @@ void Sema::checkCall(NamedDecl *FDecl, const FunctionProtoType *Proto, ArmStreamingType CallerFnType = getArmStreamingFnType(CallerFD); if (!IsCalleeStreamingCompatible && (CallerFnType == ArmStreamingCompatible || - ((CallerFnType == ArmStreaming) ^ IsCalleeStreaming))) - Diag(Loc, diag::warn_sme_streaming_pass_return_vl_to_non_streaming); + ((CallerFnType == ArmStreaming) ^ IsCalleeStreaming))) { + if (IsScalableArg) + Diag(Loc, diag::warn_sme_streaming_pass_return_vl_to_non_streaming) + << /*IsArg=*/true; + if (IsScalableRet) + Diag(Loc, diag::warn_sme_streaming_pass_return_vl_to_non_streaming) + << /*IsArg=*/false; + } } FunctionType::ArmStateValue CalleeArmZAState = diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index 452e00fa32b10208a3ce638f4f501eecd818af85..378615497b13cfd25404bf7e80066bcbb5e97b0b 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -12417,12 +12417,16 @@ bool Sema::CheckFunctionDeclaration(Scope *S, FunctionDecl *NewFD, bool UsesZT0 = Attr && Attr->isNewZT0(); if (NewFD->hasAttr()) { - if (NewFD->getReturnType()->isSizelessVectorType() || - llvm::any_of(NewFD->parameters(), [](ParmVarDecl *P) { + if (NewFD->getReturnType()->isSizelessVectorType()) + Diag(NewFD->getLocation(), + diag::warn_sme_locally_streaming_has_vl_args_returns) + << /*IsArg=*/false; + if (llvm::any_of(NewFD->parameters(), [](ParmVarDecl *P) { return P->getOriginalType()->isSizelessVectorType(); })) Diag(NewFD->getLocation(), - diag::warn_sme_locally_streaming_has_vl_args_returns); + diag::warn_sme_locally_streaming_has_vl_args_returns) + << /*IsArg=*/true; } if (const auto *FPT = NewFD->getType()->getAs()) { FunctionProtoType::ExtProtoInfo EPI = FPT->getExtProtoInfo(); diff --git a/clang/lib/Sema/SemaRISCVVectorLookup.cpp b/clang/lib/Sema/SemaRISCVVectorLookup.cpp index bf89a4ac51afd22e5660fac5e5a0f364733aa154..26e13e87b1d6b65a0abb1fd964dfe097a2a6d422 100644 --- a/clang/lib/Sema/SemaRISCVVectorLookup.cpp +++ b/clang/lib/Sema/SemaRISCVVectorLookup.cpp @@ -216,6 +216,7 @@ void RISCVIntrinsicManagerImpl::ConstructRVVIntrinsics( {"zvksed", RVV_REQ_Zvksed}, {"zvksh", RVV_REQ_Zvksh}, {"zvfbfwma", RVV_REQ_Zvfbfwma}, + {"zvfbfmin", RVV_REQ_Zvfbfmin}, {"experimental", RVV_REQ_Experimental}}; // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 4bda31ba67c02d03e1d9323fdef4d3e763ca871c..bbcb7c33a985793bd8331e5e3ed5a49cd3b789e6 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -9460,6 +9460,7 @@ DeclResult Sema::ActOnClassTemplateSpecialization( Diag(TemplateNameLoc, diag::err_partial_spec_fully_specialized) << ClassTemplate->getDeclName(); isPartialSpecialization = false; + Invalid = true; } } @@ -9675,6 +9676,7 @@ DeclResult Sema::ActOnClassTemplateSpecialization( if (SkipBody && SkipBody->ShouldSkip) return SkipBody->Previous; + Specialization->setInvalidDecl(Invalid); return Specialization; } diff --git a/clang/lib/Sema/SemaTemplateDeduction.cpp b/clang/lib/Sema/SemaTemplateDeduction.cpp index 0b6375001f532623a3a86b0fcf57f163e7afc07b..c3815bca038554bfa1cf76775b1550c55fcbd6c0 100644 --- a/clang/lib/Sema/SemaTemplateDeduction.cpp +++ b/clang/lib/Sema/SemaTemplateDeduction.cpp @@ -1914,6 +1914,9 @@ static TemplateDeductionResult DeduceTemplateArgumentsByTypeMatch( if (!S.isCompleteType(Info.getLocation(), A)) return Result; + if (getCanonicalRD(A)->isInvalidDecl()) + return Result; + // Reset the incorrectly deduced argument from above. Deduced = DeducedOrig; diff --git a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp index 787a485e0b2f8c36f9526e3d3f2b5728e68329a6..d544cfac55ba36c057e6fa84667470061df929f9 100644 --- a/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiateDecl.cpp @@ -5184,6 +5184,7 @@ void Sema::InstantiateFunctionDefinition(SourceLocation PointOfInstantiation, ParmVarDecl *Parm = Function->getParamDecl(0); TypeSourceInfo *NewParmSI = IR.TransformType(Parm->getTypeSourceInfo()); + assert(NewParmSI && "Type transformation failed."); Parm->setType(NewParmSI->getType()); Parm->setTypeSourceInfo(NewParmSI); }; diff --git a/clang/lib/Sema/TreeTransform.h b/clang/lib/Sema/TreeTransform.h index 539a18eb92a7ce324d5788acf6b91d60b20594c1..9404be5a46f3f73d503fe298e94ca7a0aaae384b 100644 --- a/clang/lib/Sema/TreeTransform.h +++ b/clang/lib/Sema/TreeTransform.h @@ -12943,19 +12943,6 @@ TreeTransform::TransformCXXNewExpr(CXXNewExpr *E) { ArraySize = NewArraySize.get(); } - // Per C++0x [expr.new]p5, the type being constructed may be a - // typedef of an array type. - QualType AllocType = AllocTypeInfo->getType(); - if (ArraySize && E->isTypeDependent()) { - if (const ConstantArrayType *Array = - SemaRef.Context.getAsConstantArrayType(AllocType)) { - ArraySize = IntegerLiteral::Create(SemaRef.Context, Array->getSize(), - SemaRef.Context.getSizeType(), - E->getBeginLoc()); - AllocType = Array->getElementType(); - } - } - // Transform the placement arguments (if any). bool ArgumentChanged = false; SmallVector PlacementArgs; @@ -13017,6 +13004,7 @@ TreeTransform::TransformCXXNewExpr(CXXNewExpr *E) { return E; } + QualType AllocType = AllocTypeInfo->getType(); if (!ArraySize) { // If no array size was specified, but the new expression was // instantiated with an array type (e.g., "new T" where T is diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index 21cf72ab0f912146fc89b1be2b91a2c7f5f4418b..30195868ca9965b7f4f9d5f20f9ca19caf1b416c 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -171,34 +171,9 @@ GetAffectingModuleMaps(const Preprocessor &PP, Module *RootModule) { .ModulesPruneNonAffectingModuleMaps) return std::nullopt; - SmallVector ModulesToProcess{RootModule}; - const HeaderSearch &HS = PP.getHeaderSearchInfo(); - - SmallVector FilesByUID; - HS.getFileMgr().GetUniqueIDMapping(FilesByUID); - - if (FilesByUID.size() > HS.header_file_size()) - FilesByUID.resize(HS.header_file_size()); - - for (unsigned UID = 0, LastUID = FilesByUID.size(); UID != LastUID; ++UID) { - OptionalFileEntryRef File = FilesByUID[UID]; - if (!File) - continue; - - const HeaderFileInfo *HFI = HS.getExistingLocalFileInfo(*File); - if (!HFI || (HFI->isModuleHeader && !HFI->isCompilingModuleHeader)) - continue; - - for (const auto &KH : HS.findResolvedModulesForHeader(*File)) { - if (!KH.getModule()) - continue; - ModulesToProcess.push_back(KH.getModule()); - } - } - const ModuleMap &MM = HS.getModuleMap(); - SourceManager &SourceMgr = PP.getSourceManager(); + const SourceManager &SourceMgr = PP.getSourceManager(); std::set ModuleMaps; auto CollectIncludingModuleMaps = [&](FileID FID, FileEntryRef F) { @@ -233,12 +208,48 @@ GetAffectingModuleMaps(const Preprocessor &PP, Module *RootModule) { } }; - for (const Module *CurrentModule : ModulesToProcess) { + // Handle all the affecting modules referenced from the root module. + + std::queue Q; + Q.push(RootModule); + while (!Q.empty()) { + const Module *CurrentModule = Q.front(); + Q.pop(); + CollectIncludingMapsFromAncestors(CurrentModule); for (const Module *ImportedModule : CurrentModule->Imports) CollectIncludingMapsFromAncestors(ImportedModule); for (const Module *UndeclaredModule : CurrentModule->UndeclaredUses) CollectIncludingMapsFromAncestors(UndeclaredModule); + + for (auto *M : CurrentModule->submodules()) + Q.push(M); + } + + // Handle textually-included headers that belong to other modules. + + SmallVector FilesByUID; + HS.getFileMgr().GetUniqueIDMapping(FilesByUID); + + if (FilesByUID.size() > HS.header_file_size()) + FilesByUID.resize(HS.header_file_size()); + + for (unsigned UID = 0, LastUID = FilesByUID.size(); UID != LastUID; ++UID) { + OptionalFileEntryRef File = FilesByUID[UID]; + if (!File) + continue; + + const HeaderFileInfo *HFI = HS.getExistingLocalFileInfo(*File); + if (!HFI) + continue; // We have no information on this being a header file. + if (!HFI->isCompilingModuleHeader && HFI->isModuleHeader) + continue; // Modular header, handled in the above module-based loop. + if (!HFI->isCompilingModuleHeader && !HFI->IsLocallyIncluded) + continue; // Non-modular header not included locally is not affecting. + + for (const auto &KH : HS.findResolvedModulesForHeader(*File)) + if (const Module *M = KH.getModule()) + CollectIncludingMapsFromAncestors(M); } return ModuleMaps; @@ -2053,14 +2064,13 @@ void ASTWriter::WriteHeaderSearch(const HeaderSearch &HS) { if (!File) continue; - // Get the file info. Skip emitting this file if we have no information on - // it as a header file (in which case HFI will be null) or if it hasn't - // changed since it was loaded. Also skip it if it's for a modular header - // from a different module; in that case, we rely on the module(s) - // containing the header to provide this information. const HeaderFileInfo *HFI = HS.getExistingLocalFileInfo(*File); - if (!HFI || (HFI->isModuleHeader && !HFI->isCompilingModuleHeader)) - continue; + if (!HFI) + continue; // We have no information on this being a header file. + if (!HFI->isCompilingModuleHeader && HFI->isModuleHeader) + continue; // Header file info is tracked by the owning module file. + if (!HFI->isCompilingModuleHeader && !PP->alreadyIncluded(*File)) + continue; // Non-modular header not included is not needed. // Massage the file path into an appropriate form. StringRef Filename = File->getName(); @@ -3618,7 +3628,6 @@ class ASTIdentifierTableTrait { /// doesn't check whether the name has macros defined; use PublicMacroIterator /// to check that. bool isInterestingIdentifier(const IdentifierInfo *II, uint64_t MacroOffset) { - II->getObjCOrBuiltinID(); bool IsInteresting = II->getNotableIdentifierID() != tok::NotableIdentifierKind::not_notable || @@ -5097,7 +5106,7 @@ void ASTWriter::WriteSpecialDeclRecords(Sema &SemaRef) { DeclsToCheckForDeferredDiags.push_back(getDeclID(D)); if (!DeclsToCheckForDeferredDiags.empty()) Stream.EmitRecord(DECLS_TO_CHECK_FOR_DEFERRED_DIAGS, - DeclsToCheckForDeferredDiags); + DeclsToCheckForDeferredDiags); // Write the record containing CUDA-specific declaration references. RecordData CUDASpecialDeclRefs; diff --git a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp index bd495cd0f9710de291d9aa20f76d3fea24757efb..a0aa2316a7b45dac40dc41e01ccdecd5a3b4311d 100644 --- a/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/StreamChecker.cpp @@ -600,7 +600,7 @@ struct StreamOperationEvaluator { SValBuilder &SVB; const ASTContext &ACtx; - SymbolRef StreamSym; + SymbolRef StreamSym = nullptr; const StreamState *SS = nullptr; const CallExpr *CE = nullptr; StreamErrorState NewES; diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c new file mode 100644 index 0000000000000000000000000000000000000000..8c8e1cdfb658847c0656b83ab61b91f98fe9b39b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vcreate.c @@ -0,0 +1,477 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vcreate_v_bf16m1_bf16m2( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, [[V0]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv4bf16( [[TMP0]], [[V1]], i64 4) +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vcreate_v_bf16m1_bf16m2(vbfloat16m1_t v0, vbfloat16m1_t v1) { + return __riscv_vcreate_v_bf16m1_bf16m2(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local @test_vcreate_v_bf16m1_bf16m4( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, [[V0]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( [[TMP0]], [[V1]], i64 4) +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( [[TMP1]], [[V2]], i64 8) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( [[TMP2]], [[V3]], i64 12) +// CHECK-RV64-NEXT: ret [[TMP3]] +// +vbfloat16m4_t test_vcreate_v_bf16m1_bf16m4(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3) { + return __riscv_vcreate_v_bf16m1_bf16m4(v0, v1, v2, v3); +} + +// CHECK-RV64-LABEL: define dso_local @test_vcreate_v_bf16m1_bf16m8( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]], [[V7:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, [[V0]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP0]], [[V1]], i64 4) +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP1]], [[V2]], i64 8) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP2]], [[V3]], i64 12) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP3]], [[V4]], i64 16) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP4]], [[V5]], i64 20) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP5]], [[V6]], i64 24) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[TMP6]], [[V7]], i64 28) +// CHECK-RV64-NEXT: ret [[TMP7]] +// +vbfloat16m8_t test_vcreate_v_bf16m1_bf16m8(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3, + vbfloat16m1_t v4, vbfloat16m1_t v5, + vbfloat16m1_t v6, vbfloat16m1_t v7) { + return __riscv_vcreate_v_bf16m1_bf16m8(v0, v1, v2, v3, v4, v5, v6, v7); +} + +// CHECK-RV64-LABEL: define dso_local @test_vcreate_v_bf16m2_bf16m4( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[V0]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[TMP0]], [[V1]], i64 8) +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vcreate_v_bf16m2_bf16m4(vbfloat16m2_t v0, vbfloat16m2_t v1) { + return __riscv_vcreate_v_bf16m2_bf16m4(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local @test_vcreate_v_bf16m2_bf16m8( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[V0]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP0]], [[V1]], i64 8) +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP1]], [[V2]], i64 16) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[TMP2]], [[V3]], i64 24) +// CHECK-RV64-NEXT: ret [[TMP3]] +// +vbfloat16m8_t test_vcreate_v_bf16m2_bf16m8(vbfloat16m2_t v0, vbfloat16m2_t v1, + vbfloat16m2_t v2, vbfloat16m2_t v3) { + return __riscv_vcreate_v_bf16m2_bf16m8(v0, v1, v2, v3); +} + +// CHECK-RV64-LABEL: define dso_local @test_vcreate_v_bf16m4_bf16m8( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, [[V0]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv16bf16( [[TMP0]], [[V1]], i64 16) +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vcreate_v_bf16m4_bf16m8(vbfloat16m4_t v0, vbfloat16m4_t v1) { + return __riscv_vcreate_v_bf16m4_bf16m8(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vcreate_v_bf16mf4x2( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: ret { , } [[TMP1]] +// +vbfloat16mf4x2_t test_vcreate_v_bf16mf4x2(vbfloat16mf4_t v0, + vbfloat16mf4_t v1) { + return __riscv_vcreate_v_bf16mf4x2(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vcreate_v_bf16mf4x3( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: ret { , , } [[TMP2]] +// +vbfloat16mf4x3_t test_vcreate_v_bf16mf4x3(vbfloat16mf4_t v0, vbfloat16mf4_t v1, + vbfloat16mf4_t v2) { + return __riscv_vcreate_v_bf16mf4x3(v0, v1, v2); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vcreate_v_bf16mf4x4( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: ret { , , , } [[TMP3]] +// +vbfloat16mf4x4_t test_vcreate_v_bf16mf4x4(vbfloat16mf4_t v0, vbfloat16mf4_t v1, + vbfloat16mf4_t v2, + vbfloat16mf4_t v3) { + return __riscv_vcreate_v_bf16mf4x4(v0, v1, v2, v3); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vcreate_v_bf16mf4x5( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP4]] +// +vbfloat16mf4x5_t test_vcreate_v_bf16mf4x5(vbfloat16mf4_t v0, vbfloat16mf4_t v1, + vbfloat16mf4_t v2, vbfloat16mf4_t v3, + vbfloat16mf4_t v4) { + return __riscv_vcreate_v_bf16mf4x5(v0, v1, v2, v3, v4); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vcreate_v_bf16mf4x6( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP5]] +// +vbfloat16mf4x6_t test_vcreate_v_bf16mf4x6(vbfloat16mf4_t v0, vbfloat16mf4_t v1, + vbfloat16mf4_t v2, vbfloat16mf4_t v3, + vbfloat16mf4_t v4, + vbfloat16mf4_t v5) { + return __riscv_vcreate_v_bf16mf4x6(v0, v1, v2, v3, v4, v5); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vcreate_v_bf16mf4x7( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V6]], 6 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP6]] +// +vbfloat16mf4x7_t test_vcreate_v_bf16mf4x7(vbfloat16mf4_t v0, vbfloat16mf4_t v1, + vbfloat16mf4_t v2, vbfloat16mf4_t v3, + vbfloat16mf4_t v4, vbfloat16mf4_t v5, + vbfloat16mf4_t v6) { + return __riscv_vcreate_v_bf16mf4x7(v0, v1, v2, v3, v4, v5, v6); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vcreate_v_bf16mf4x8( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]], [[V7:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V7]], 7 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP7]] +// +vbfloat16mf4x8_t test_vcreate_v_bf16mf4x8(vbfloat16mf4_t v0, vbfloat16mf4_t v1, + vbfloat16mf4_t v2, vbfloat16mf4_t v3, + vbfloat16mf4_t v4, vbfloat16mf4_t v5, + vbfloat16mf4_t v6, + vbfloat16mf4_t v7) { + return __riscv_vcreate_v_bf16mf4x8(v0, v1, v2, v3, v4, v5, v6, v7); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vcreate_v_bf16mf2x2( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: ret { , } [[TMP1]] +// +vbfloat16mf2x2_t test_vcreate_v_bf16mf2x2(vbfloat16mf2_t v0, + vbfloat16mf2_t v1) { + return __riscv_vcreate_v_bf16mf2x2(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vcreate_v_bf16mf2x3( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: ret { , , } [[TMP2]] +// +vbfloat16mf2x3_t test_vcreate_v_bf16mf2x3(vbfloat16mf2_t v0, vbfloat16mf2_t v1, + vbfloat16mf2_t v2) { + return __riscv_vcreate_v_bf16mf2x3(v0, v1, v2); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vcreate_v_bf16mf2x4( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: ret { , , , } [[TMP3]] +// +vbfloat16mf2x4_t test_vcreate_v_bf16mf2x4(vbfloat16mf2_t v0, vbfloat16mf2_t v1, + vbfloat16mf2_t v2, + vbfloat16mf2_t v3) { + return __riscv_vcreate_v_bf16mf2x4(v0, v1, v2, v3); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vcreate_v_bf16mf2x5( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP4]] +// +vbfloat16mf2x5_t test_vcreate_v_bf16mf2x5(vbfloat16mf2_t v0, vbfloat16mf2_t v1, + vbfloat16mf2_t v2, vbfloat16mf2_t v3, + vbfloat16mf2_t v4) { + return __riscv_vcreate_v_bf16mf2x5(v0, v1, v2, v3, v4); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vcreate_v_bf16mf2x6( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP5]] +// +vbfloat16mf2x6_t test_vcreate_v_bf16mf2x6(vbfloat16mf2_t v0, vbfloat16mf2_t v1, + vbfloat16mf2_t v2, vbfloat16mf2_t v3, + vbfloat16mf2_t v4, + vbfloat16mf2_t v5) { + return __riscv_vcreate_v_bf16mf2x6(v0, v1, v2, v3, v4, v5); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vcreate_v_bf16mf2x7( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V6]], 6 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP6]] +// +vbfloat16mf2x7_t test_vcreate_v_bf16mf2x7(vbfloat16mf2_t v0, vbfloat16mf2_t v1, + vbfloat16mf2_t v2, vbfloat16mf2_t v3, + vbfloat16mf2_t v4, vbfloat16mf2_t v5, + vbfloat16mf2_t v6) { + return __riscv_vcreate_v_bf16mf2x7(v0, v1, v2, v3, v4, v5, v6); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vcreate_v_bf16mf2x8( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]], [[V7:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V7]], 7 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP7]] +// +vbfloat16mf2x8_t test_vcreate_v_bf16mf2x8(vbfloat16mf2_t v0, vbfloat16mf2_t v1, + vbfloat16mf2_t v2, vbfloat16mf2_t v3, + vbfloat16mf2_t v4, vbfloat16mf2_t v5, + vbfloat16mf2_t v6, + vbfloat16mf2_t v7) { + return __riscv_vcreate_v_bf16mf2x8(v0, v1, v2, v3, v4, v5, v6, v7); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vcreate_v_bf16m1x2( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: ret { , } [[TMP1]] +// +vbfloat16m1x2_t test_vcreate_v_bf16m1x2(vbfloat16m1_t v0, vbfloat16m1_t v1) { + return __riscv_vcreate_v_bf16m1x2(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vcreate_v_bf16m1x3( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: ret { , , } [[TMP2]] +// +vbfloat16m1x3_t test_vcreate_v_bf16m1x3(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2) { + return __riscv_vcreate_v_bf16m1x3(v0, v1, v2); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vcreate_v_bf16m1x4( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: ret { , , , } [[TMP3]] +// +vbfloat16m1x4_t test_vcreate_v_bf16m1x4(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3) { + return __riscv_vcreate_v_bf16m1x4(v0, v1, v2, v3); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vcreate_v_bf16m1x5( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP4]] +// +vbfloat16m1x5_t test_vcreate_v_bf16m1x5(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3, + vbfloat16m1_t v4) { + return __riscv_vcreate_v_bf16m1x5(v0, v1, v2, v3, v4); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vcreate_v_bf16m1x6( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP5]] +// +vbfloat16m1x6_t test_vcreate_v_bf16m1x6(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3, + vbfloat16m1_t v4, vbfloat16m1_t v5) { + return __riscv_vcreate_v_bf16m1x6(v0, v1, v2, v3, v4, v5); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vcreate_v_bf16m1x7( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP5]], [[V6]], 6 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP6]] +// +vbfloat16m1x7_t test_vcreate_v_bf16m1x7(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3, + vbfloat16m1_t v4, vbfloat16m1_t v5, + vbfloat16m1_t v6) { + return __riscv_vcreate_v_bf16m1x7(v0, v1, v2, v3, v4, v5, v6); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vcreate_v_bf16m1x8( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]], [[V4:%.*]], [[V5:%.*]], [[V6:%.*]], [[V7:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , , , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP3]], [[V4]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[V5]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP5]], [[V6]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[V7]], 7 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP7]] +// +vbfloat16m1x8_t test_vcreate_v_bf16m1x8(vbfloat16m1_t v0, vbfloat16m1_t v1, + vbfloat16m1_t v2, vbfloat16m1_t v3, + vbfloat16m1_t v4, vbfloat16m1_t v5, + vbfloat16m1_t v6, vbfloat16m1_t v7) { + return __riscv_vcreate_v_bf16m1x8(v0, v1, v2, v3, v4, v5, v6, v7); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vcreate_v_bf16m2x2( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: ret { , } [[TMP1]] +// +vbfloat16m2x2_t test_vcreate_v_bf16m2x2(vbfloat16m2_t v0, vbfloat16m2_t v1) { + return __riscv_vcreate_v_bf16m2x2(v0, v1); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vcreate_v_bf16m2x3( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: ret { , , } [[TMP2]] +// +vbfloat16m2x3_t test_vcreate_v_bf16m2x3(vbfloat16m2_t v0, vbfloat16m2_t v1, + vbfloat16m2_t v2) { + return __riscv_vcreate_v_bf16m2x3(v0, v1, v2); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vcreate_v_bf16m2x4( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]], [[V2:%.*]], [[V3:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , , , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } [[TMP1]], [[V2]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = insertvalue { , , , } [[TMP2]], [[V3]], 3 +// CHECK-RV64-NEXT: ret { , , , } [[TMP3]] +// +vbfloat16m2x4_t test_vcreate_v_bf16m2x4(vbfloat16m2_t v0, vbfloat16m2_t v1, + vbfloat16m2_t v2, vbfloat16m2_t v3) { + return __riscv_vcreate_v_bf16m2x4(v0, v1, v2, v3); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vcreate_v_bf16m4x2( +// CHECK-RV64-SAME: [[V0:%.*]], [[V1:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } poison, [[V0]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = insertvalue { , } [[TMP0]], [[V1]], 1 +// CHECK-RV64-NEXT: ret { , } [[TMP1]] +// +vbfloat16m4x2_t test_vcreate_v_bf16m4x2(vbfloat16m4_t v0, vbfloat16m4_t v1) { + return __riscv_vcreate_v_bf16m4x2(v0, v1); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c new file mode 100644 index 0000000000000000000000000000000000000000..11a385dbe5c9a2a5ebc82e94ee6329704b7204f5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vget.c @@ -0,0 +1,333 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv8bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m2_bf16m1(vbfloat16m2_t src, size_t index) { + return __riscv_vget_v_bf16m2_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m4_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv16bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m4_bf16m1(vbfloat16m4_t src, size_t index) { + return __riscv_vget_v_bf16m4_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m8_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv32bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m8_bf16m1(vbfloat16m8_t src, size_t index) { + return __riscv_vget_v_bf16m8_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m4_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m4_bf16m2(vbfloat16m4_t src, size_t index) { + return __riscv_vget_v_bf16m4_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m8_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m8_bf16m2(vbfloat16m8_t src, size_t index) { + return __riscv_vget_v_bf16m8_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m8_bf16m4( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv16bf16.nxv32bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vget_v_bf16m8_bf16m4(vbfloat16m8_t src, size_t index) { + return __riscv_vget_v_bf16m8_bf16m4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x2_bf16mf4( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x2_bf16mf4(vbfloat16mf4x2_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x2_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x3_bf16mf4( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x3_bf16mf4(vbfloat16mf4x3_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x3_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x4_bf16mf4( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x4_bf16mf4(vbfloat16mf4x4_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x4_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x5_bf16mf4( +// CHECK-RV64-SAME: { , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x5_bf16mf4(vbfloat16mf4x5_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x5_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x6_bf16mf4( +// CHECK-RV64-SAME: { , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x6_bf16mf4(vbfloat16mf4x6_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x6_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x7_bf16mf4( +// CHECK-RV64-SAME: { , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x7_bf16mf4(vbfloat16mf4x7_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x7_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x8_bf16mf4( +// CHECK-RV64-SAME: { , , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x8_bf16mf4(vbfloat16mf4x8_t src, + size_t index) { + return __riscv_vget_v_bf16mf4x8_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x2_bf16mf2( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x2_bf16mf2(vbfloat16mf2x2_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x2_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x3_bf16mf2( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x3_bf16mf2(vbfloat16mf2x3_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x3_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x4_bf16mf2( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x4_bf16mf2(vbfloat16mf2x4_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x4_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x5_bf16mf2( +// CHECK-RV64-SAME: { , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x5_bf16mf2(vbfloat16mf2x5_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x5_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x6_bf16mf2( +// CHECK-RV64-SAME: { , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x6_bf16mf2(vbfloat16mf2x6_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x6_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x7_bf16mf2( +// CHECK-RV64-SAME: { , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x7_bf16mf2(vbfloat16mf2x7_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x7_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x8_bf16mf2( +// CHECK-RV64-SAME: { , , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x8_bf16mf2(vbfloat16mf2x8_t src, + size_t index) { + return __riscv_vget_v_bf16mf2x8_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x2_bf16m1( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x2_bf16m1(vbfloat16m1x2_t src, size_t index) { + return __riscv_vget_v_bf16m1x2_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x3_bf16m1( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x3_bf16m1(vbfloat16m1x3_t src, size_t index) { + return __riscv_vget_v_bf16m1x3_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x4_bf16m1( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x4_bf16m1(vbfloat16m1x4_t src, size_t index) { + return __riscv_vget_v_bf16m1x4_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x5_bf16m1( +// CHECK-RV64-SAME: { , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x5_bf16m1(vbfloat16m1x5_t src, size_t index) { + return __riscv_vget_v_bf16m1x5_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x6_bf16m1( +// CHECK-RV64-SAME: { , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x6_bf16m1(vbfloat16m1x6_t src, size_t index) { + return __riscv_vget_v_bf16m1x6_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x7_bf16m1( +// CHECK-RV64-SAME: { , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x7_bf16m1(vbfloat16m1x7_t src, size_t index) { + return __riscv_vget_v_bf16m1x7_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x8_bf16m1( +// CHECK-RV64-SAME: { , , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x8_bf16m1(vbfloat16m1x8_t src, size_t index) { + return __riscv_vget_v_bf16m1x8_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2x2_bf16m2( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m2x2_bf16m2(vbfloat16m2x2_t src, size_t index) { + return __riscv_vget_v_bf16m2x2_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2x3_bf16m2( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m2x3_bf16m2(vbfloat16m2x3_t src, size_t index) { + return __riscv_vget_v_bf16m2x3_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2x4_bf16m2( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m2x4_bf16m2(vbfloat16m2x4_t src, size_t index) { + return __riscv_vget_v_bf16m2x4_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m4x2_bf16m4( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vget_v_bf16m4x2_bf16m4(vbfloat16m4x2_t src, size_t index) { + return __riscv_vget_v_bf16m4x2_bf16m4(src, 0); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c new file mode 100644 index 0000000000000000000000000000000000000000..6f54ddf3f87c07ec3f647cbce3cd31c4ba975791 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16.c @@ -0,0 +1,132 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv1bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4(const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf4(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv2bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2(const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv4bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1(const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m1(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv8bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2(const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv16bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4(const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m4(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv32bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8(const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m8(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_v_bf16mf4_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_v_bf16mf2_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_v_bf16m1_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m2_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m4_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m8_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..f73cfe73bae05c6a2345a23ff5838fda33827564 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vle16ff.c @@ -0,0 +1,177 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_v_bf16mf4(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_v_bf16mf2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_v_bf16m1(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_v_bf16m2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_v_bf16m4(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64( poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_v_bf16m8(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf4_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf2_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m1_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m2_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m4_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m8_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c new file mode 100644 index 0000000000000000000000000000000000000000..3ab73c512316116d471fa21242e3e8e35669fc6f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_ext_v.c @@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_ext_v_bf16mf4_bf16mf2(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_v_bf16mf4_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_ext_v_bf16mf4_bf16m1(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_v_bf16mf4_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_ext_v_bf16mf4_bf16m2(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_v_bf16mf4_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16mf4_bf16m4(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_v_bf16mf4_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16mf4_bf16m8(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_v_bf16mf4_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_ext_v_bf16mf2_bf16m1(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_v_bf16mf2_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_ext_v_bf16mf2_bf16m2(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_v_bf16mf2_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16mf2_bf16m4(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_v_bf16mf2_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16mf2_bf16m8(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_v_bf16mf2_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_ext_v_bf16m1_bf16m2(vbfloat16m1_t value) { + return __riscv_vlmul_ext_v_bf16m1_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16m1_bf16m4(vbfloat16m1_t value) { + return __riscv_vlmul_ext_v_bf16m1_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16m1_bf16m8(vbfloat16m1_t value) { + return __riscv_vlmul_ext_v_bf16m1_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16m2_bf16m4(vbfloat16m2_t value) { + return __riscv_vlmul_ext_v_bf16m2_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16m2_bf16m8(vbfloat16m2_t value) { + return __riscv_vlmul_ext_v_bf16m2_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m4_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16m4_bf16m8(vbfloat16m4_t value) { + return __riscv_vlmul_ext_v_bf16m4_bf16m8(value); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c new file mode 100644 index 0000000000000000000000000000000000000000..478b1e556113e678409cbb07185dca44d9a805ba --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlmul_trunc_v.c @@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv2bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16mf2_bf16mf4(vbfloat16mf2_t value) { + return __riscv_vlmul_trunc_v_bf16mf2_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv4bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m1_bf16mf4(vbfloat16m1_t value) { + return __riscv_vlmul_trunc_v_bf16m1_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv4bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m1_bf16mf2(vbfloat16m1_t value) { + return __riscv_vlmul_trunc_v_bf16m1_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv8bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m2_bf16mf4(vbfloat16m2_t value) { + return __riscv_vlmul_trunc_v_bf16m2_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv8bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m2_bf16mf2(vbfloat16m2_t value) { + return __riscv_vlmul_trunc_v_bf16m2_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv8bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_trunc_v_bf16m2_bf16m1(vbfloat16m2_t value) { + return __riscv_vlmul_trunc_v_bf16m2_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m4_bf16mf4(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_v_bf16m4_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m4_bf16mf2(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_v_bf16m4_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_trunc_v_bf16m4_bf16m1(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_v_bf16m4_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_trunc_v_bf16m4_bf16m2(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_v_bf16m4_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m8_bf16mf4(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_v_bf16m8_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m8_bf16mf2(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_v_bf16m8_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_trunc_v_bf16m8_bf16m1(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_v_bf16m8_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_trunc_v_bf16m8_bf16m2(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_v_bf16m8_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv16bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_trunc_v_bf16m8_bf16m4(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_v_bf16m8_bf16m4(value); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..147c820da9a600da86cd6eb4a569975f80d8db0f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4(const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxei16_v_bf16mf4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2(const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxei16_v_bf16mf2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxei16_v_bf16m1(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxei16_v_bf16m2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxei16_v_bf16m4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8(const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vloxei16_v_bf16m8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m1_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m8_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..c35a6eb68171a3b11a650aea175225fff1d22973 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg2ei16.c @@ -0,0 +1,121 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf4x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf2x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m1x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m2x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m4x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf4x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf2x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m1x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m2x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m4x2_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..00c14b562bc5108fdfd17d1d57bcc74842c6df03 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg3ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf4x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf2x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m1x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m2x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf4x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf2x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m1x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m2x3_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..9289638807d6188054e17c5f2cb2d2358f583914 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg4ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf4x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf2x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m1x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m2x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf4x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf2x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m1x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m2x4_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..04c210d7a7966ede2616dc1ce21ec76e5843a59d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg5ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf4x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf2x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg5ei16_v_bf16m1x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf4x5_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf2x5_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16m1x5_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..7ef2249630d9425d78cef64ef1ad351b966b3880 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg6ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf4x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf2x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg6ei16_v_bf16m1x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf4x6_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf2x6_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16m1x6_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..b1d5ee604018d4b0e6b230a5e9cb66ce3c01f78f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg7ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf4x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf2x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg7ei16_v_bf16m1x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf4x7_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf2x7_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16m1x7_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..1e1c762e0d0b8a1ef690ba2d4965882cefb60161 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vloxseg8ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf4x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf2x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg8ei16_v_bf16m1x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf4x8_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf2x8_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16m1x8_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c new file mode 100644 index 0000000000000000000000000000000000000000..c5c98f3abc52d1f82c8a883f87faaf3f845a3154 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlse16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv1bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_v_bf16mf4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv2bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_v_bf16mf2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv4bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_v_bf16m1(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv8bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_v_bf16m2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv16bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_v_bf16m4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv32bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_v_bf16m8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m1_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m8_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..6ea8a1b4a4292e747e7517e078d3a0bf96a7ee84 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16.c @@ -0,0 +1,114 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf4x2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf2x2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m1x2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m2x2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m4x2(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16_v_bf16mf4x2_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16_v_bf16mf2x2_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16_v_bf16m1x2_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16_v_bf16m2x2_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16_v_bf16m4x2_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..cecf6f1153946ad3257f30d7dbb4e32f2461b657 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg2e16ff.c @@ -0,0 +1,179 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf4x2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf2x2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m1x2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m2x2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16bf16.i64( poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m4x2(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf4x2_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf2x2_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m1x2_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m2x2_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m4x2_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..2c8d679d8d63ecc6b201d361308ea4b6c1ea3078 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16.c @@ -0,0 +1,93 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf4x3(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf2x3(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m1x3(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m2x3(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16_v_bf16mf4x3_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16_v_bf16mf2x3_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16_v_bf16m1x3_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16_v_bf16m2x3_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..e7660a74c93d304037cf036065742a7ac18fdb7c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg3e16ff.c @@ -0,0 +1,161 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf4x3(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf2x3(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m1x3(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m2x3(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf4x3_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf2x3_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m1x3_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m2x3_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c7480e10028a95336698ae1f09bea024bae8f278 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16.c @@ -0,0 +1,93 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf4x4(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf2x4(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m1x4(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m2x4(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16_v_bf16mf4x4_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16_v_bf16mf2x4_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16_v_bf16m1x4_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16_v_bf16m2x4_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..de1e40c98729cee1c7e3c710edd995a46c85de1e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg4e16ff.c @@ -0,0 +1,177 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf4x4(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf2x4(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m1x4(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m2x4(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf4x4_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf2x4_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m1x4_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m2x4_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..08d4af94ee542bc53952490d06d427038ae71196 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16.c @@ -0,0 +1,72 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf4x5(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf2x5(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16m1x5(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg5e16_v_bf16mf4x5_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg5e16_v_bf16mf2x5_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg5e16_v_bf16m1x5_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..b19b51a28edacb6c3bf435804fb96d95c03f5e46 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg5e16ff.c @@ -0,0 +1,147 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf4x5(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf2x5(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg5e16ff_v_bf16m1x5(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf4x5_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf2x5_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16m1x5_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..018c18098122cc4cf2192ac867618793617aff89 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16.c @@ -0,0 +1,72 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf4x6(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf2x6(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16m1x6(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg6e16_v_bf16mf4x6_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg6e16_v_bf16mf2x6_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg6e16_v_bf16m1x6_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..2104f8e083f2d133781a9dcc1be048c7b2a19a0c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg6e16ff.c @@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf4x6(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf2x6(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg6e16ff_v_bf16m1x6(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf4x6_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf2x6_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16m1x6_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..b15ef25d0c1fcae79de7d0984d442b02ad620c9e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16.c @@ -0,0 +1,72 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf4x7(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf2x7(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16m1x7(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg7e16_v_bf16mf4x7_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg7e16_v_bf16mf2x7_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg7e16_v_bf16m1x7_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..42361b6375cbf1d1a5ae93487f66bf5506bbec90 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg7e16ff.c @@ -0,0 +1,171 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf4x7(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf2x7(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg7e16ff_v_bf16m1x7(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf4x7_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf2x7_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16m1x7_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..7f113a21e9bf92e3f46dd28a692197edbcc47969 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16.c @@ -0,0 +1,72 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf4x8(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf2x8(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8(const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16m1x8(rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg8e16_v_bf16mf4x8_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg8e16_v_bf16mf2x8_m(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg8e16_v_bf16m1x8_m(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..c9cf4ba0243cec3a3c7b1cb4156b5f3dfdd0d98f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlseg8e16ff.c @@ -0,0 +1,183 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf4x8(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf2x8(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8(const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vlseg8e16ff_v_bf16m1x8(rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf4x8_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf2x8_m(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16m1x8_m(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..92b5c2948fa31646b81e0c02817b3653eb546e03 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg2e16.c @@ -0,0 +1,119 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf4x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf2x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_v_bf16m1x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_v_bf16m2x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_v_bf16m4x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf4x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf2x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m1x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m2x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m4x2_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d834ead8365ca4dd1d5189c4655921448a4fa8c3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg3e16.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf4x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf2x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_v_bf16m1x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_v_bf16m2x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf4x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf2x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m1x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m2x3_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d59822b0fb35f6cdb8a44012147398708c74a5c7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg4e16.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf4x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf2x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_v_bf16m1x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_v_bf16m2x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf4x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf2x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m1x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m2x4_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..a8c653585b3be3e5b0c691e3f1ad54b92222a7f6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg5e16.c @@ -0,0 +1,75 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf4x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf2x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg5e16_v_bf16m1x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf4x5_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf2x5_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16m1x5_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..1271f7b4eb7678a8f0cdf2200e37dbcf2e430e63 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg6e16.c @@ -0,0 +1,75 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf4x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf2x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg6e16_v_bf16m1x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf4x6_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf2x6_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16m1x6_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..f86541cc27f9f95ba9de6014c9d02b7639b6ae65 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg7e16.c @@ -0,0 +1,75 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf4x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf2x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg7e16_v_bf16m1x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf4x7_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf2x7_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16m1x7_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..071ff57a56f97b978ec875e157af8188385e362b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vlsseg8e16.c @@ -0,0 +1,75 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf4x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf2x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8(const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg8e16_v_bf16m1x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf4x8_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf2x8_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16m1x8_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..cb51dc0abbb851cbe246c9e94d2aec1978e45f5d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4(const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxei16_v_bf16mf4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2(const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxei16_v_bf16mf2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxei16_v_bf16m1(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxei16_v_bf16m2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxei16_v_bf16m4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8(const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vluxei16_v_bf16m8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m1_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m8_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..983c9936448523dd536ab450f48812e4c6f05fd3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg2ei16.c @@ -0,0 +1,121 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf4x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf2x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m1x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m2x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m4x2(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf4x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf2x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m1x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m2x2_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m4x2_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..8d89952bea2b0b6e5e0531718471204242f17cc7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg3ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf4x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf2x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m1x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m2x3(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf4x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf2x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m1x3_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m2x3_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..2751b1245f1670308f5d197b841eb98d71ade12b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg4ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf4x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf2x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m1x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m2x4(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf4x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf2x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m1x4_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m2x4_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..9cd84e561dfaa53d99c3db4dce4e9f7d837e467d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg5ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf4x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf2x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg5ei16_v_bf16m1x5(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf4x5_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf2x5_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16m1x5_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..95ce415c871cf124c889ae60f139f8f94aeee021 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg6ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf4x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf2x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg6ei16_v_bf16m1x6(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf4x6_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf2x6_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16m1x6_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..c1b84c434e4e75ab279d482310595d6a49440ec1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg7ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf4x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf2x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg7ei16_v_bf16m1x7(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf4x7_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf2x7_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16m1x7_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..32e5ab40e40a2e20953dca3f2715dc9aa8105a52 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vluxseg8ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf4x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf2x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg8ei16_v_bf16m1x8(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf4x8_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf2x8_m(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16m1x8_m(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vreinterpret.c new file mode 100644 index 0000000000000000000000000000000000000000..30120be47154bce70da2cbc953451225badd4f8b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vreinterpret.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vreinterpret_v_i16mf4_bf16mf4(vint16mf4_t src) { + return __riscv_vreinterpret_v_i16mf4_bf16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vreinterpret_v_i16mf2_bf16mf2(vint16mf2_t src) { + return __riscv_vreinterpret_v_i16mf2_bf16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m1_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vreinterpret_v_i16m1_bf16m1(vint16m1_t src) { + return __riscv_vreinterpret_v_i16m1_bf16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m2_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vreinterpret_v_i16m2_bf16m2(vint16m2_t src) { + return __riscv_vreinterpret_v_i16m2_bf16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m4_bf16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vreinterpret_v_i16m4_bf16m4(vint16m4_t src) { + return __riscv_vreinterpret_v_i16m4_bf16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m8_bf16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vreinterpret_v_i16m8_bf16m8(vint16m8_t src) { + return __riscv_vreinterpret_v_i16m8_bf16m8(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vreinterpret_v_u16mf4_bf16mf4(vuint16mf4_t src) { + return __riscv_vreinterpret_v_u16mf4_bf16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vreinterpret_v_u16mf2_bf16mf2(vuint16mf2_t src) { + return __riscv_vreinterpret_v_u16mf2_bf16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m1_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vreinterpret_v_u16m1_bf16m1(vuint16m1_t src) { + return __riscv_vreinterpret_v_u16m1_bf16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m2_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vreinterpret_v_u16m2_bf16m2(vuint16m2_t src) { + return __riscv_vreinterpret_v_u16m2_bf16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m4_bf16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vreinterpret_v_u16m4_bf16m4(vuint16m4_t src) { + return __riscv_vreinterpret_v_u16m4_bf16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m8_bf16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vreinterpret_v_u16m8_bf16m8(vuint16m8_t src) { + return __riscv_vreinterpret_v_u16m8_bf16m8(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vreinterpret_v_bf16mf4_i16mf4(vbfloat16mf4_t src) { + return __riscv_vreinterpret_v_bf16mf4_i16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vreinterpret_v_bf16mf2_i16mf2(vbfloat16mf2_t src) { + return __riscv_vreinterpret_v_bf16mf2_i16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m1_i16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vreinterpret_v_bf16m1_i16m1(vbfloat16m1_t src) { + return __riscv_vreinterpret_v_bf16m1_i16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m2_i16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vreinterpret_v_bf16m2_i16m2(vbfloat16m2_t src) { + return __riscv_vreinterpret_v_bf16m2_i16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m4_i16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vreinterpret_v_bf16m4_i16m4(vbfloat16m4_t src) { + return __riscv_vreinterpret_v_bf16m4_i16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m8_i16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vreinterpret_v_bf16m8_i16m8(vbfloat16m8_t src) { + return __riscv_vreinterpret_v_bf16m8_i16m8(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vreinterpret_v_bf16mf4_u16mf4(vbfloat16mf4_t src) { + return __riscv_vreinterpret_v_bf16mf4_u16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vreinterpret_v_bf16mf2_u16mf2(vbfloat16mf2_t src) { + return __riscv_vreinterpret_v_bf16mf2_u16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m1_u16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vreinterpret_v_bf16m1_u16m1(vbfloat16m1_t src) { + return __riscv_vreinterpret_v_bf16m1_u16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m2_u16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vreinterpret_v_bf16m2_u16m2(vbfloat16m2_t src) { + return __riscv_vreinterpret_v_bf16m2_u16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m4_u16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vreinterpret_v_bf16m4_u16m4(vbfloat16m4_t src) { + return __riscv_vreinterpret_v_bf16m4_u16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m8_u16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vreinterpret_v_bf16m8_u16m8(vbfloat16m8_t src) { + return __riscv_vreinterpret_v_bf16m8_u16m8(src); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vse16.c new file mode 100644 index 0000000000000000000000000000000000000000..4bfc5b7350cbc6a13b2adffdbfef002da8b310d7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vse16.c @@ -0,0 +1,135 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf4(__bf16 *rs1, vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vse16_v_bf16mf4(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf2(__bf16 *rs1, vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vse16_v_bf16mf2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m1(__bf16 *rs1, vbfloat16m1_t vs3, size_t vl) { + return __riscv_vse16_v_bf16m1(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m2(__bf16 *rs1, vbfloat16m2_t vs3, size_t vl) { + return __riscv_vse16_v_bf16m2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m4(__bf16 *rs1, vbfloat16m4_t vs3, size_t vl) { + return __riscv_vse16_v_bf16m4(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m8(__bf16 *rs1, vbfloat16m8_t vs3, size_t vl) { + return __riscv_vse16_v_bf16m8(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vse16_v_bf16mf4_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vse16_v_bf16mf2_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vse16_v_bf16m1_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vse16_v_bf16m2_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vse16_v_bf16m4_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vse16_v_bf16m8_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c new file mode 100644 index 0000000000000000000000000000000000000000..779c24bd6469b007a1e2cef14ed364bafb6989e5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vset.c @@ -0,0 +1,364 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m1_bf16m2( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv4bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vset_v_bf16m1_bf16m2(vbfloat16m2_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m2(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m1_bf16m4( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vset_v_bf16m1_bf16m4(vbfloat16m4_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m4(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m2_bf16m4( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vset_v_bf16m2_bf16m4(vbfloat16m4_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset_v_bf16m2_bf16m4(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m1_bf16m8( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vset_v_bf16m1_bf16m8(vbfloat16m8_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m8(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m2_bf16m8( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vset_v_bf16m2_bf16m8(vbfloat16m8_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset_v_bf16m2_bf16m8(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m4_bf16m8( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv16bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vset_v_bf16m4_bf16m8(vbfloat16m8_t dest, size_t index, + vbfloat16m4_t value) { + return __riscv_vset_v_bf16m4_bf16m8(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16mf4_bf16mf4x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vset_v_bf16mf4_bf16mf4x2(vbfloat16mf4x2_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x2(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16mf4_bf16mf4x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vset_v_bf16mf4_bf16mf4x3(vbfloat16mf4x3_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x3(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16mf4_bf16mf4x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vset_v_bf16mf4_bf16mf4x4(vbfloat16mf4x4_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x4(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vset_v_bf16mf4_bf16mf4x5( +// CHECK-RV64-SAME: { , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vset_v_bf16mf4_bf16mf4x5(vbfloat16mf4x5_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x5(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vset_v_bf16mf4_bf16mf4x6( +// CHECK-RV64-SAME: { , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vset_v_bf16mf4_bf16mf4x6(vbfloat16mf4x6_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x6(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vset_v_bf16mf4_bf16mf4x7( +// CHECK-RV64-SAME: { , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vset_v_bf16mf4_bf16mf4x7(vbfloat16mf4x7_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x7(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vset_v_bf16mf4_bf16mf4x8( +// CHECK-RV64-SAME: { , , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vset_v_bf16mf4_bf16mf4x8(vbfloat16mf4x8_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset_v_bf16mf4_bf16mf4x8(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16mf2_bf16mf2x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vset_v_bf16mf2_bf16mf2x2(vbfloat16mf2x2_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x2(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16mf2_bf16mf2x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vset_v_bf16mf2_bf16mf2x3(vbfloat16mf2x3_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x3(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16mf2_bf16mf2x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vset_v_bf16mf2_bf16mf2x4(vbfloat16mf2x4_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x4(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vset_v_bf16mf2_bf16mf2x5( +// CHECK-RV64-SAME: { , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vset_v_bf16mf2_bf16mf2x5(vbfloat16mf2x5_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x5(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vset_v_bf16mf2_bf16mf2x6( +// CHECK-RV64-SAME: { , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vset_v_bf16mf2_bf16mf2x6(vbfloat16mf2x6_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x6(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vset_v_bf16mf2_bf16mf2x7( +// CHECK-RV64-SAME: { , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vset_v_bf16mf2_bf16mf2x7(vbfloat16mf2x7_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x7(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vset_v_bf16mf2_bf16mf2x8( +// CHECK-RV64-SAME: { , , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vset_v_bf16mf2_bf16mf2x8(vbfloat16mf2x8_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset_v_bf16mf2_bf16mf2x8(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16m1_bf16m1x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vset_v_bf16m1_bf16m1x2(vbfloat16m1x2_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x2(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16m1_bf16m1x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vset_v_bf16m1_bf16m1x3(vbfloat16m1x3_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x3(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16m1_bf16m1x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vset_v_bf16m1_bf16m1x4(vbfloat16m1x4_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x4(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vset_v_bf16m1_bf16m1x5( +// CHECK-RV64-SAME: { , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vset_v_bf16m1_bf16m1x5(vbfloat16m1x5_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x5(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vset_v_bf16m1_bf16m1x6( +// CHECK-RV64-SAME: { , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vset_v_bf16m1_bf16m1x6(vbfloat16m1x6_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x6(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vset_v_bf16m1_bf16m1x7( +// CHECK-RV64-SAME: { , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vset_v_bf16m1_bf16m1x7(vbfloat16m1x7_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x7(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vset_v_bf16m1_bf16m1x8( +// CHECK-RV64-SAME: { , , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vset_v_bf16m1_bf16m1x8(vbfloat16m1x8_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset_v_bf16m1_bf16m1x8(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16m2_bf16m2x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vset_v_bf16m2_bf16m2x2(vbfloat16m2x2_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset_v_bf16m2_bf16m2x2(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16m2_bf16m2x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vset_v_bf16m2_bf16m2x3(vbfloat16m2x3_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset_v_bf16m2_bf16m2x3(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16m2_bf16m2x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vset_v_bf16m2_bf16m2x4(vbfloat16m2x4_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset_v_bf16m2_bf16m2x4(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16m4_bf16m4x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vset_v_bf16m4_bf16m4x2(vbfloat16m4x2_t dest, size_t index, + vbfloat16m4_t value) { + return __riscv_vset_v_bf16m4_bf16m4x2(dest, 0, value); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..dc3c25f4cbe8f28bbde5c4dc87b80a20157182da --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf4(__bf16 *rs1, vuint16mf4_t rs2, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vsoxei16_v_bf16mf4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf2(__bf16 *rs1, vuint16mf2_t rs2, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vsoxei16_v_bf16mf2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m1(__bf16 *rs1, vuint16m1_t rs2, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vsoxei16_v_bf16m1(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m2(__bf16 *rs1, vuint16m2_t rs2, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vsoxei16_v_bf16m2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m4(__bf16 *rs1, vuint16m4_t rs2, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vsoxei16_v_bf16m4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m8(__bf16 *rs1, vuint16m8_t rs2, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vsoxei16_v_bf16m8(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vuint16mf4_t rs2, + vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vsoxei16_v_bf16mf4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vuint16mf2_t rs2, + vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vsoxei16_v_bf16mf2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t rs2, + vbfloat16m1_t vs3, size_t vl) { + return __riscv_vsoxei16_v_bf16m1_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t rs2, + vbfloat16m2_t vs3, size_t vl) { + return __riscv_vsoxei16_v_bf16m2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t rs2, + vbfloat16m4_t vs3, size_t vl) { + return __riscv_vsoxei16_v_bf16m4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vuint16m8_t rs2, + vbfloat16m8_t vs3, size_t vl) { + return __riscv_vsoxei16_v_bf16m8_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..a98ca6ae63a6bd15bf1b59a65c32168f90b23784 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg2ei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf4x2(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16mf4x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf2x2(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16mf2x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m1x2(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16m1x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m2x2(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16m2x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m4x2(__bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16m4x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x2_t vs3, + size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16mf4x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x2_t vs3, + size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16mf2x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16m1x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16m2x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16_v_bf16m4x2_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..0f08957b30a7e5291934b540cef59831a951a8a8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg3ei16.c @@ -0,0 +1,123 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf4x3(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16mf4x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf2x3(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16mf2x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m1x3(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16m1x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m2x3(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16m2x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x3_t vs3, + size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16mf4x3_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x3_t vs3, + size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16mf2x3_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16m1x3_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16_v_bf16m2x3_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..0b29625998b0879a9b2603deded2b8f51d068b79 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg4ei16.c @@ -0,0 +1,131 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf4x4(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16mf4x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf2x4(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16mf2x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m1x4(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16m1x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m2x4(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16m2x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x4_t vs3, + size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16mf4x4_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x4_t vs3, + size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16mf2x4_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16m1x4_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16_v_bf16m2x4_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..0fc4d57918a4998951a221ffc1044d0d28d7f7b5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg5ei16.c @@ -0,0 +1,107 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf4x5(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16_v_bf16mf4x5(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf2x5(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16_v_bf16mf2x5(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16m1x5(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16_v_bf16m1x5(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x5_t vs3, + size_t vl) { + return __riscv_vsoxseg5ei16_v_bf16mf4x5_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x5_t vs3, + size_t vl) { + return __riscv_vsoxseg5ei16_v_bf16mf2x5_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16_v_bf16m1x5_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..e0c628c7eeec7614b8776670916a2631a464a704 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg6ei16.c @@ -0,0 +1,113 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf4x6(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16_v_bf16mf4x6(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf2x6(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16_v_bf16mf2x6(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16m1x6(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16_v_bf16m1x6(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x6_t vs3, + size_t vl) { + return __riscv_vsoxseg6ei16_v_bf16mf4x6_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x6_t vs3, + size_t vl) { + return __riscv_vsoxseg6ei16_v_bf16mf2x6_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16_v_bf16m1x6_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..4ae28ba5cedd94c86306b94f5c94526eb2252632 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg7ei16.c @@ -0,0 +1,119 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf4x7(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16_v_bf16mf4x7(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf2x7(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16_v_bf16mf2x7(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16m1x7(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16_v_bf16m1x7(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x7_t vs3, + size_t vl) { + return __riscv_vsoxseg7ei16_v_bf16mf4x7_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x7_t vs3, + size_t vl) { + return __riscv_vsoxseg7ei16_v_bf16mf2x7_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16_v_bf16m1x7_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..942a3239934adb9b4902da485295e65f1faf0e0e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsoxseg8ei16.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf4x8(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16_v_bf16mf4x8(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf2x8(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16_v_bf16mf2x8(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16m1x8(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16_v_bf16m1x8(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x8_t vs3, + size_t vl) { + return __riscv_vsoxseg8ei16_v_bf16mf4x8_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x8_t vs3, + size_t vl) { + return __riscv_vsoxseg8ei16_v_bf16mf2x8_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16_v_bf16m1x8_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsse16.c new file mode 100644 index 0000000000000000000000000000000000000000..13eb05bb3b0c80c51ae7f3763be1a6c30e04346f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsse16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vsse16_v_bf16mf4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vsse16_v_bf16mf2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m1(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vsse16_v_bf16m1(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vsse16_v_bf16m2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vsse16_v_bf16m4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m8(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vsse16_v_bf16m8(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vsse16_v_bf16mf4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vsse16_v_bf16mf2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1_t vs3, size_t vl) { + return __riscv_vsse16_v_bf16m1_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2_t vs3, size_t vl) { + return __riscv_vsse16_v_bf16m2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m4_t vs3, size_t vl) { + return __riscv_vsse16_v_bf16m4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m8_t vs3, size_t vl) { + return __riscv_vsse16_v_bf16m8_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..a6384b15423902ef6d014c89d8b405f8f1ce88c0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg2e16.c @@ -0,0 +1,134 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf4x2(__bf16 *rs1, vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16mf4x2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf2x2(__bf16 *rs1, vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16mf2x2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m1x2(__bf16 *rs1, vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16m1x2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m2x2(__bf16 *rs1, vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16m2x2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m4x2(__bf16 *rs1, vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16m4x2(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16mf4x2_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsseg2e16_v_bf16mf2x2_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x2_t vs3, + size_t vl) { + return __riscv_vsseg2e16_v_bf16m1x2_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x2_t vs3, + size_t vl) { + return __riscv_vsseg2e16_v_bf16m2x2_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vbfloat16m4x2_t vs3, + size_t vl) { + return __riscv_vsseg2e16_v_bf16m4x2_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..b04177c8db4dc113082353821c748aaaeb95de05 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg3e16.c @@ -0,0 +1,117 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf4x3(__bf16 *rs1, vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsseg3e16_v_bf16mf4x3(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf2x3(__bf16 *rs1, vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsseg3e16_v_bf16mf2x3(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m1x3(__bf16 *rs1, vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsseg3e16_v_bf16m1x3(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m2x3(__bf16 *rs1, vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsseg3e16_v_bf16m2x3(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsseg3e16_v_bf16mf4x3_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsseg3e16_v_bf16mf2x3_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x3_t vs3, + size_t vl) { + return __riscv_vsseg3e16_v_bf16m1x3_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x3_t vs3, + size_t vl) { + return __riscv_vsseg3e16_v_bf16m2x3_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..3745c3af566efd9c97bd43b0eea0eab1d0f3f5fe --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg4e16.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf4x4(__bf16 *rs1, vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsseg4e16_v_bf16mf4x4(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf2x4(__bf16 *rs1, vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsseg4e16_v_bf16mf2x4(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m1x4(__bf16 *rs1, vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsseg4e16_v_bf16m1x4(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m2x4(__bf16 *rs1, vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsseg4e16_v_bf16m2x4(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsseg4e16_v_bf16mf4x4_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsseg4e16_v_bf16mf2x4_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x4_t vs3, + size_t vl) { + return __riscv_vsseg4e16_v_bf16m1x4_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x4_t vs3, + size_t vl) { + return __riscv_vsseg4e16_v_bf16m2x4_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..8aa59fbb521ca088ed7be10730c36a8bec9f05d8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg5e16.c @@ -0,0 +1,102 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf4x5(__bf16 *rs1, vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsseg5e16_v_bf16mf4x5(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf2x5(__bf16 *rs1, vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsseg5e16_v_bf16mf2x5(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16m1x5(__bf16 *rs1, vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsseg5e16_v_bf16m1x5(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsseg5e16_v_bf16mf4x5_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsseg5e16_v_bf16mf2x5_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x5_t vs3, + size_t vl) { + return __riscv_vsseg5e16_v_bf16m1x5_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..a2b3fd5e1102897be2ba5069e56a81a6e4be990e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg6e16.c @@ -0,0 +1,108 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf4x6(__bf16 *rs1, vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsseg6e16_v_bf16mf4x6(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf2x6(__bf16 *rs1, vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsseg6e16_v_bf16mf2x6(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16m1x6(__bf16 *rs1, vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsseg6e16_v_bf16m1x6(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsseg6e16_v_bf16mf4x6_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsseg6e16_v_bf16mf2x6_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x6_t vs3, + size_t vl) { + return __riscv_vsseg6e16_v_bf16m1x6_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..3664769177658f1e8d1af043b8117b0fefb3f922 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg7e16.c @@ -0,0 +1,114 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf4x7(__bf16 *rs1, vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsseg7e16_v_bf16mf4x7(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf2x7(__bf16 *rs1, vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsseg7e16_v_bf16mf2x7(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16m1x7(__bf16 *rs1, vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsseg7e16_v_bf16m1x7(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsseg7e16_v_bf16mf4x7_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsseg7e16_v_bf16mf2x7_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x7_t vs3, + size_t vl) { + return __riscv_vsseg7e16_v_bf16m1x7_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..2c6717726e7230b6cefb0165715b8189caaef4e9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsseg8e16.c @@ -0,0 +1,120 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf4x8(__bf16 *rs1, vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsseg8e16_v_bf16mf4x8(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf2x8(__bf16 *rs1, vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsseg8e16_v_bf16mf2x8(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16m1x8(__bf16 *rs1, vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsseg8e16_v_bf16m1x8(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsseg8e16_v_bf16mf4x8_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsseg8e16_v_bf16mf2x8_m(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x8_t vs3, + size_t vl) { + return __riscv_vsseg8e16_v_bf16m1x8_m(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..a6aacb536854c51d5c649dd396d428fdef14e458 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg2e16.c @@ -0,0 +1,139 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf4x2(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16mf4x2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf2x2(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16mf2x2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m1x2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x2_t vs3, + size_t vl) { + return __riscv_vssseg2e16_v_bf16m1x2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m2x2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2x2_t vs3, + size_t vl) { + return __riscv_vssseg2e16_v_bf16m2x2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m4x2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m4x2_t vs3, + size_t vl) { + return __riscv_vssseg2e16_v_bf16m4x2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16mf4x2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16mf2x2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16m1x2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16m2x2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vssseg2e16_v_bf16m4x2_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..4ce7ef9bbf044a3913dd657409e23b7ca1fcbadf --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg3e16.c @@ -0,0 +1,121 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf4x3(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vssseg3e16_v_bf16mf4x3(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf2x3(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vssseg3e16_v_bf16mf2x3(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m1x3(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x3_t vs3, + size_t vl) { + return __riscv_vssseg3e16_v_bf16m1x3(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m2x3(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2x3_t vs3, + size_t vl) { + return __riscv_vssseg3e16_v_bf16m2x3(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vssseg3e16_v_bf16mf4x3_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vssseg3e16_v_bf16mf2x3_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vssseg3e16_v_bf16m1x3_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vssseg3e16_v_bf16m2x3_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..f8d980f8946fc5a42580f96e0d7094a3fdc41396 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg4e16.c @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf4x4(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vssseg4e16_v_bf16mf4x4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf2x4(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vssseg4e16_v_bf16mf2x4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m1x4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x4_t vs3, + size_t vl) { + return __riscv_vssseg4e16_v_bf16m1x4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m2x4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2x4_t vs3, + size_t vl) { + return __riscv_vssseg4e16_v_bf16m2x4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vssseg4e16_v_bf16mf4x4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vssseg4e16_v_bf16mf2x4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vssseg4e16_v_bf16m1x4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vssseg4e16_v_bf16m2x4_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..115cdf480d9714e5f07a7e783b27e3060f285914 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg5e16.c @@ -0,0 +1,105 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf4x5(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vssseg5e16_v_bf16mf4x5(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf2x5(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vssseg5e16_v_bf16mf2x5(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16m1x5(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x5_t vs3, + size_t vl) { + return __riscv_vssseg5e16_v_bf16m1x5(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vssseg5e16_v_bf16mf4x5_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vssseg5e16_v_bf16mf2x5_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vssseg5e16_v_bf16m1x5_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c74f19905a4d29f45aac6a962632cfb3987c041f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg6e16.c @@ -0,0 +1,111 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf4x6(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vssseg6e16_v_bf16mf4x6(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf2x6(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vssseg6e16_v_bf16mf2x6(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16m1x6(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x6_t vs3, + size_t vl) { + return __riscv_vssseg6e16_v_bf16m1x6(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vssseg6e16_v_bf16mf4x6_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vssseg6e16_v_bf16mf2x6_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vssseg6e16_v_bf16m1x6_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d1ff80f684a4a9d3838af8d6466d34191549bd90 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg7e16.c @@ -0,0 +1,117 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf4x7(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vssseg7e16_v_bf16mf4x7(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf2x7(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vssseg7e16_v_bf16mf2x7(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16m1x7(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x7_t vs3, + size_t vl) { + return __riscv_vssseg7e16_v_bf16m1x7(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vssseg7e16_v_bf16mf4x7_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vssseg7e16_v_bf16mf2x7_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vssseg7e16_v_bf16m1x7_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..e80ff10dab50e5fa1e2d29a4b238d7d66aebd312 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vssseg8e16.c @@ -0,0 +1,123 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf4x8(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vssseg8e16_v_bf16mf4x8(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf2x8(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vssseg8e16_v_bf16mf2x8(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16m1x8(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x8_t vs3, + size_t vl) { + return __riscv_vssseg8e16_v_bf16m1x8(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vssseg8e16_v_bf16mf4x8_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vssseg8e16_v_bf16mf2x8_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vssseg8e16_v_bf16m1x8_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..5bbff43146203562d869a90978b7e597b1bf0b71 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf4(__bf16 *rs1, vuint16mf4_t rs2, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vsuxei16_v_bf16mf4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf2(__bf16 *rs1, vuint16mf2_t rs2, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vsuxei16_v_bf16mf2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m1(__bf16 *rs1, vuint16m1_t rs2, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vsuxei16_v_bf16m1(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m2(__bf16 *rs1, vuint16m2_t rs2, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vsuxei16_v_bf16m2(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m4(__bf16 *rs1, vuint16m4_t rs2, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vsuxei16_v_bf16m4(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m8(__bf16 *rs1, vuint16m8_t rs2, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vsuxei16_v_bf16m8(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vuint16mf4_t rs2, + vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vsuxei16_v_bf16mf4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vuint16mf2_t rs2, + vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vsuxei16_v_bf16mf2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t rs2, + vbfloat16m1_t vs3, size_t vl) { + return __riscv_vsuxei16_v_bf16m1_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t rs2, + vbfloat16m2_t vs3, size_t vl) { + return __riscv_vsuxei16_v_bf16m2_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t rs2, + vbfloat16m4_t vs3, size_t vl) { + return __riscv_vsuxei16_v_bf16m4_m(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vuint16m8_t rs2, + vbfloat16m8_t vs3, size_t vl) { + return __riscv_vsuxei16_v_bf16m8_m(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..27db36fa9531e9f447ad0ed3b009e2e6a52b2b8d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg2ei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf4x2(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16mf4x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf2x2(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16mf2x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m1x2(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16m1x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m2x2(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16m2x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m4x2(__bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16m4x2(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x2_t vs3, + size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16mf4x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x2_t vs3, + size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16mf2x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16m1x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16m2x2_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16_v_bf16m4x2_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..9c482373689563a731cb725e845532cf8b2e0c15 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg3ei16.c @@ -0,0 +1,123 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf4x3(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16mf4x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf2x3(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16mf2x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m1x3(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16m1x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m2x3(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16m2x3(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x3_t vs3, + size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16mf4x3_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x3_t vs3, + size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16mf2x3_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16m1x3_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16_v_bf16m2x3_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..63b13ec6a32ffce9af1c744a9b0fab2f51c09931 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg4ei16.c @@ -0,0 +1,131 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf4x4(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16mf4x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf2x4(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16mf2x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m1x4(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16m1x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m2x4(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16m2x4(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x4_t vs3, + size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16mf4x4_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x4_t vs3, + size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16mf2x4_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16m1x4_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16_v_bf16m2x4_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..4d93f05b0a101827b4cb9ff508b47e529e4ffdfa --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg5ei16.c @@ -0,0 +1,107 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf4x5(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16_v_bf16mf4x5(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf2x5(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16_v_bf16mf2x5(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16m1x5(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16_v_bf16m1x5(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x5_t vs3, + size_t vl) { + return __riscv_vsuxseg5ei16_v_bf16mf4x5_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x5_t vs3, + size_t vl) { + return __riscv_vsuxseg5ei16_v_bf16mf2x5_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16_v_bf16m1x5_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..0b6ef26c3751f08c779c26157b6e8fff74da32c3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg6ei16.c @@ -0,0 +1,113 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf4x6(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16_v_bf16mf4x6(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf2x6(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16_v_bf16mf2x6(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16m1x6(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16_v_bf16m1x6(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x6_t vs3, + size_t vl) { + return __riscv_vsuxseg6ei16_v_bf16mf4x6_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x6_t vs3, + size_t vl) { + return __riscv_vsuxseg6ei16_v_bf16mf2x6_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16_v_bf16m1x6_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..10debde6ef60837de98c830b354bb6f4642e94c5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg7ei16.c @@ -0,0 +1,119 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf4x7(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16_v_bf16mf4x7(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf2x7(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16_v_bf16mf2x7(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16m1x7(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16_v_bf16m1x7(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x7_t vs3, + size_t vl) { + return __riscv_vsuxseg7ei16_v_bf16mf4x7_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x7_t vs3, + size_t vl) { + return __riscv_vsuxseg7ei16_v_bf16mf2x7_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16_v_bf16m1x7_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..175c7c478173b6fb0e278a3a5a1d8ce4f81cbe0e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vsuxseg8ei16.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf4x8(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16_v_bf16mf4x8(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf2x8(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16_v_bf16mf2x8(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16m1x8(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16_v_bf16m1x8(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x8_t vs3, + size_t vl) { + return __riscv_vsuxseg8ei16_v_bf16mf4x8_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x8_t vs3, + size_t vl) { + return __riscv_vsuxseg8ei16_v_bf16mf2x8_m(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16_v_bf16m1x8_m(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c new file mode 100644 index 0000000000000000000000000000000000000000..5a2c8731b9551cd5c557e24a37e29a883fab2f30 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/bfloat16/vundefined.c @@ -0,0 +1,280 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vundefined_bf16mf4( +// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret poison +// +vbfloat16mf4_t test_vundefined_bf16mf4() { + return __riscv_vundefined_bf16mf4(); +} + +// CHECK-RV64-LABEL: define dso_local @test_vundefined_bf16mf2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret poison +// +vbfloat16mf2_t test_vundefined_bf16mf2() { + return __riscv_vundefined_bf16mf2(); +} + +// CHECK-RV64-LABEL: define dso_local @test_vundefined_bf16m1( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret poison +// +vbfloat16m1_t test_vundefined_bf16m1() { return __riscv_vundefined_bf16m1(); } + +// CHECK-RV64-LABEL: define dso_local @test_vundefined_bf16m2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret poison +// +vbfloat16m2_t test_vundefined_bf16m2() { return __riscv_vundefined_bf16m2(); } + +// CHECK-RV64-LABEL: define dso_local @test_vundefined_bf16m4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret poison +// +vbfloat16m4_t test_vundefined_bf16m4() { return __riscv_vundefined_bf16m4(); } + +// CHECK-RV64-LABEL: define dso_local @test_vundefined_bf16m8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret poison +// +vbfloat16m8_t test_vundefined_bf16m8() { return __riscv_vundefined_bf16m8(); } + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_bf16mf4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vbfloat16mf4x2_t test_vundefined_bf16mf4x2() { + return __riscv_vundefined_bf16mf4x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_bf16mf4x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vbfloat16mf4x3_t test_vundefined_bf16mf4x3() { + return __riscv_vundefined_bf16mf4x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_bf16mf4x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vbfloat16mf4x4_t test_vundefined_bf16mf4x4() { + return __riscv_vundefined_bf16mf4x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_bf16mf4x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vbfloat16mf4x5_t test_vundefined_bf16mf4x5() { + return __riscv_vundefined_bf16mf4x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_bf16mf4x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vbfloat16mf4x6_t test_vundefined_bf16mf4x6() { + return __riscv_vundefined_bf16mf4x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_bf16mf4x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vbfloat16mf4x7_t test_vundefined_bf16mf4x7() { + return __riscv_vundefined_bf16mf4x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_bf16mf4x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vbfloat16mf4x8_t test_vundefined_bf16mf4x8() { + return __riscv_vundefined_bf16mf4x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_bf16mf2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vbfloat16mf2x2_t test_vundefined_bf16mf2x2() { + return __riscv_vundefined_bf16mf2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_bf16mf2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vbfloat16mf2x3_t test_vundefined_bf16mf2x3() { + return __riscv_vundefined_bf16mf2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_bf16mf2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vbfloat16mf2x4_t test_vundefined_bf16mf2x4() { + return __riscv_vundefined_bf16mf2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_bf16mf2x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vbfloat16mf2x5_t test_vundefined_bf16mf2x5() { + return __riscv_vundefined_bf16mf2x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_bf16mf2x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vbfloat16mf2x6_t test_vundefined_bf16mf2x6() { + return __riscv_vundefined_bf16mf2x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_bf16mf2x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vbfloat16mf2x7_t test_vundefined_bf16mf2x7() { + return __riscv_vundefined_bf16mf2x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_bf16mf2x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vbfloat16mf2x8_t test_vundefined_bf16mf2x8() { + return __riscv_vundefined_bf16mf2x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_bf16m1x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vbfloat16m1x2_t test_vundefined_bf16m1x2() { + return __riscv_vundefined_bf16m1x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_bf16m1x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vbfloat16m1x3_t test_vundefined_bf16m1x3() { + return __riscv_vundefined_bf16m1x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_bf16m1x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vbfloat16m1x4_t test_vundefined_bf16m1x4() { + return __riscv_vundefined_bf16m1x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vundefined_bf16m1x5( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , } poison +// +vbfloat16m1x5_t test_vundefined_bf16m1x5() { + return __riscv_vundefined_bf16m1x5(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vundefined_bf16m1x6( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , } poison +// +vbfloat16m1x6_t test_vundefined_bf16m1x6() { + return __riscv_vundefined_bf16m1x6(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vundefined_bf16m1x7( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , } poison +// +vbfloat16m1x7_t test_vundefined_bf16m1x7() { + return __riscv_vundefined_bf16m1x7(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vundefined_bf16m1x8( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , , , , , } poison +// +vbfloat16m1x8_t test_vundefined_bf16m1x8() { + return __riscv_vundefined_bf16m1x8(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_bf16m2x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vbfloat16m2x2_t test_vundefined_bf16m2x2() { + return __riscv_vundefined_bf16m2x2(); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vundefined_bf16m2x3( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , } poison +// +vbfloat16m2x3_t test_vundefined_bf16m2x3() { + return __riscv_vundefined_bf16m2x3(); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vundefined_bf16m2x4( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , , , } poison +// +vbfloat16m2x4_t test_vundefined_bf16m2x4() { + return __riscv_vundefined_bf16m2x4(); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vundefined_bf16m4x2( +// CHECK-RV64-SAME: ) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: ret { , } poison +// +vbfloat16m4x2_t test_vundefined_bf16m4x2() { + return __riscv_vundefined_bf16m4x2(); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c index 76a9ddc0d5294651536ec95e1d18cee597f8cec6..3e37ac4b7749976b9bd3d82156a1779e2f31693e 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdf_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c index 468c3f18378d3c3dbd4eecb1e49a39ee31aba953..c29c1e983fce6748c0942a2bf03bc5d5cc8f95d3 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdm_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c index bc6a17e4b6f0fba07b5bd53e0100540a59a963b8..7ed9f5c36e98d1acd96c8a890e395388db91c372 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesef_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c index e0e1662b76f9cb29cde526be865904ab5dc4a7e5..34eec0037491fdbef8af75cf41d59e67685f3d61 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesem_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c index 0700b60fa639953e9fbeae9553e93341b76d38a4..bfe0b0602717fa9efc12c27aaf7d255154ecad76 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8(vuint32m8_t vd, vuint32m4_t vs2, size_t vl return __riscv_vaesz_vs_u32m4_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c index f9d855a72d2885c75066ede8c9e8a8761d7d1f68..fe9090225596d45b309cb79fb49ba15602ba4541 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv_u32m8(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs_u32m8_u32m8(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c new file mode 100644 index 0000000000000000000000000000000000000000..7f8ddf75156b76e8179907ab383d6fd419efb762 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vget.c @@ -0,0 +1,333 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv8bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m2_bf16m1(vbfloat16m2_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m4_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv16bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m4_bf16m1(vbfloat16m4_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m8_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv32bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m8_bf16m1(vbfloat16m8_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m4_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m4_bf16m2(vbfloat16m4_t src, size_t index) { + return __riscv_vget_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m8_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m8_bf16m2(vbfloat16m8_t src, size_t index) { + return __riscv_vget_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m8_bf16m4( +// CHECK-RV64-SAME: [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv16bf16.nxv32bf16( [[SRC]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vget_v_bf16m8_bf16m4(vbfloat16m8_t src, size_t index) { + return __riscv_vget_bf16m4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x2_bf16mf4( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x2_bf16mf4(vbfloat16mf4x2_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x3_bf16mf4( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x3_bf16mf4(vbfloat16mf4x3_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x4_bf16mf4( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x4_bf16mf4(vbfloat16mf4x4_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x5_bf16mf4( +// CHECK-RV64-SAME: { , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x5_bf16mf4(vbfloat16mf4x5_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x6_bf16mf4( +// CHECK-RV64-SAME: { , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x6_bf16mf4(vbfloat16mf4x6_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x7_bf16mf4( +// CHECK-RV64-SAME: { , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x7_bf16mf4(vbfloat16mf4x7_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf4x8_bf16mf4( +// CHECK-RV64-SAME: { , , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vget_v_bf16mf4x8_bf16mf4(vbfloat16mf4x8_t src, + size_t index) { + return __riscv_vget_bf16mf4(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x2_bf16mf2( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x2_bf16mf2(vbfloat16mf2x2_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x3_bf16mf2( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x3_bf16mf2(vbfloat16mf2x3_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x4_bf16mf2( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x4_bf16mf2(vbfloat16mf2x4_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x5_bf16mf2( +// CHECK-RV64-SAME: { , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x5_bf16mf2(vbfloat16mf2x5_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x6_bf16mf2( +// CHECK-RV64-SAME: { , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x6_bf16mf2(vbfloat16mf2x6_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x7_bf16mf2( +// CHECK-RV64-SAME: { , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x7_bf16mf2(vbfloat16mf2x7_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16mf2x8_bf16mf2( +// CHECK-RV64-SAME: { , , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vget_v_bf16mf2x8_bf16mf2(vbfloat16mf2x8_t src, + size_t index) { + return __riscv_vget_bf16mf2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x2_bf16m1( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x2_bf16m1(vbfloat16m1x2_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x3_bf16m1( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x3_bf16m1(vbfloat16m1x3_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x4_bf16m1( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x4_bf16m1(vbfloat16m1x4_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x5_bf16m1( +// CHECK-RV64-SAME: { , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x5_bf16m1(vbfloat16m1x5_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x6_bf16m1( +// CHECK-RV64-SAME: { , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x6_bf16m1(vbfloat16m1x6_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x7_bf16m1( +// CHECK-RV64-SAME: { , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x7_bf16m1(vbfloat16m1x7_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m1x8_bf16m1( +// CHECK-RV64-SAME: { , , , , , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vget_v_bf16m1x8_bf16m1(vbfloat16m1x8_t src, size_t index) { + return __riscv_vget_bf16m1(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2x2_bf16m2( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m2x2_bf16m2(vbfloat16m2x2_t src, size_t index) { + return __riscv_vget_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2x3_bf16m2( +// CHECK-RV64-SAME: { , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m2x3_bf16m2(vbfloat16m2x3_t src, size_t index) { + return __riscv_vget_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m2x4_bf16m2( +// CHECK-RV64-SAME: { , , , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vget_v_bf16m2x4_bf16m2(vbfloat16m2x4_t src, size_t index) { + return __riscv_vget_bf16m2(src, 0); +} + +// CHECK-RV64-LABEL: define dso_local @test_vget_v_bf16m4x2_bf16m4( +// CHECK-RV64-SAME: { , } [[SRC:%.*]], i64 noundef [[INDEX:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[SRC]], 0 +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vget_v_bf16m4x2_bf16m4(vbfloat16m4x2_t src, size_t index) { + return __riscv_vget_bf16m4(src, 0); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16.c new file mode 100644 index 0000000000000000000000000000000000000000..765e9d8346388f1f1fcc1a6a919594bff17b1053 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16.c @@ -0,0 +1,72 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, size_t vl) { + return __riscv_vle16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, size_t vl) { + return __riscv_vle16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, size_t vl) { + return __riscv_vle16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..9ef6a091b9d5e3d35e05591c5798b34858a4fa08 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vle16ff.c @@ -0,0 +1,93 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_ext_v.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_ext_v.c new file mode 100644 index 0000000000000000000000000000000000000000..6a4ef411cfa5a7262b13d95757d78a4d981d090e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_ext_v.c @@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv2bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_ext_v_bf16mf4_bf16mf2(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv4bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_ext_v_bf16mf4_bf16m1(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_ext_v_bf16mf4_bf16m2(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16mf4_bf16m4(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf4_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv1bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16mf4_bf16m8(vbfloat16mf4_t value) { + return __riscv_vlmul_ext_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv4bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_ext_v_bf16mf2_bf16m1(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_ext_v_bf16mf2_bf16m2(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16mf2_bf16m4(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16mf2_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv2bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16mf2_bf16m8(vbfloat16mf2_t value) { + return __riscv_vlmul_ext_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m1_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv4bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_ext_v_bf16m1_bf16m2(vbfloat16m1_t value) { + return __riscv_vlmul_ext_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m1_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16m1_bf16m4(vbfloat16m1_t value) { + return __riscv_vlmul_ext_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m1_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16m1_bf16m8(vbfloat16m1_t value) { + return __riscv_vlmul_ext_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m2_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv8bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_ext_v_bf16m2_bf16m4(vbfloat16m2_t value) { + return __riscv_vlmul_ext_bf16m4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m2_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16m2_bf16m8(vbfloat16m2_t value) { + return __riscv_vlmul_ext_bf16m8(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_ext_v_bf16m4_bf16m8( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv16bf16( poison, [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlmul_ext_v_bf16m4_bf16m8(vbfloat16m4_t value) { + return __riscv_vlmul_ext_bf16m8(value); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_trunc_v.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_trunc_v.c new file mode 100644 index 0000000000000000000000000000000000000000..04ca0ac94259aaae885d952430df53dbbeb2c1be --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlmul_trunc_v.c @@ -0,0 +1,159 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16mf2_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv2bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16mf2_bf16mf4(vbfloat16mf2_t value) { + return __riscv_vlmul_trunc_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv4bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m1_bf16mf4(vbfloat16m1_t value) { + return __riscv_vlmul_trunc_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m1_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv4bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m1_bf16mf2(vbfloat16m1_t value) { + return __riscv_vlmul_trunc_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv8bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m2_bf16mf4(vbfloat16m2_t value) { + return __riscv_vlmul_trunc_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m2_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv8bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m2_bf16mf2(vbfloat16m2_t value) { + return __riscv_vlmul_trunc_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m2_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv8bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_trunc_v_bf16m2_bf16m1(vbfloat16m2_t value) { + return __riscv_vlmul_trunc_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m4_bf16mf4(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m4_bf16mf2(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_trunc_v_bf16m4_bf16m1(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m4_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_trunc_v_bf16m4_bf16m2(vbfloat16m4_t value) { + return __riscv_vlmul_trunc_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv1bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlmul_trunc_v_bf16m8_bf16mf4(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_bf16mf4(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16mf2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv2bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlmul_trunc_v_bf16m8_bf16mf2(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_bf16mf2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16m1( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv4bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlmul_trunc_v_bf16m8_bf16m1(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_bf16m1(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16m2( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlmul_trunc_v_bf16m8_bf16m2(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_bf16m2(value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlmul_trunc_v_bf16m8_bf16m4( +// CHECK-RV64-SAME: [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.extract.nxv16bf16.nxv32bf16( [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlmul_trunc_v_bf16m8_bf16m4(vbfloat16m8_t value) { + return __riscv_vlmul_trunc_bf16m4(value); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..f57636a7c74c905ab673e9122fed7a31ff3d4d04 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4(const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2(const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8(const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vloxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..e43a37959da5a4ab70425871ea4a06bd970f9e27 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg2ei16.c @@ -0,0 +1,121 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..52950e897a2fddca3117d838b5fc63cf5a908226 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg3ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..3351c42c25c171a82433c293619144e4c8b7a028 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg4ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..4651c0ecad853cfd5e8f583e7f91036a1557992d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg5ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg5ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..c70b924c5cab75fc96cf879a6483c60baf38efbc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg6ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg6ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..985b0053362f445690911b5b259d5e5e0c96d68f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg7ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg7ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..413773b1657a29e6ef3103ff7619863861e7cf1b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vloxseg8ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxseg8ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlse16.c new file mode 100644 index 0000000000000000000000000000000000000000..300100a94371e2141dda000821281998a4ba9451 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlse16.c @@ -0,0 +1,75 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..2304cc3a7cddab4af991e692fcca0efaa8ee7b71 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16.c @@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg2e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..f645d5872c269601d6095fa43a61f3cbbc5983df --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg2e16ff.c @@ -0,0 +1,94 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP5]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP4]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..0ce174b2402aa6547ab8ac6bbc13ef80424b07da --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16.c @@ -0,0 +1,53 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg3e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..3545a54199a7ff29abf24aed7739a85a96fddbbb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg3e16ff.c @@ -0,0 +1,85 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP6]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c17b1eab338b588be9b8e755b672d27de9506392 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16.c @@ -0,0 +1,53 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg4e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..3aadacfd62eb23f377606e17030e848c6ad2dd46 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg4e16ff.c @@ -0,0 +1,93 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP9]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP8]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..029916fde042ac22bd76adc2ddcaabdb04718c39 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg5e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg5e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg5e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..d1c991ed2cee37ac24f15a50546ae691fc0edcc2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg5e16ff.c @@ -0,0 +1,78 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP11]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP10]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..33ecd52a6e66dce9ee924001f23db58ec7d38ac7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg6e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg6e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg6e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..5bc58996f14b7b5e6d22257e7a06b6a58849bebe --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg6e16ff.c @@ -0,0 +1,84 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP12]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..9804f5edac6132da1099ccb158ba46ed4e95b6f6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg7e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg7e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg7e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..646c177806cfe89fa5889ca025b84d76c8ab412b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg7e16ff.c @@ -0,0 +1,90 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP15]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP14]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..a969317f246d3fc2556273b6bdc96eb7ff4ead37 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_m(vbool64_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg8e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_m(vbool32_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg8e16(vm, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + size_t vl) { + return __riscv_vlseg8e16(vm, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..bec9006b8afc8943a14a347385c3e11f6bde4a47 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlseg8e16ff.c @@ -0,0 +1,96 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_m(vbool64_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_m(vbool32_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff(vm, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = insertvalue { , , , , , , , } poison, [[TMP1]], 0 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , , , , , , , } [[TMP2]], [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 2 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , , , , , } [[TMP4]], [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 3 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , , , } [[TMP6]], [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 4 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } [[TMP8]], [[TMP9]], 4 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 5 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 5 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 6 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 6 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 7 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 7 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP0]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP17]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP16]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff(vm, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..ba5cf455287e055e48cd1e72c89b770157d2360f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg2e16.c @@ -0,0 +1,64 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..0cdad1c52725dc8ba6391059491efc185a7fe6e3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg3e16.c @@ -0,0 +1,53 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d45e46fd9326f2bee57dfbb584cd41785a68b0a4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg4e16.c @@ -0,0 +1,53 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d7484e5e6e6dd111db5cef238f7544e5fe2e00b1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg5e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..9bbdc186f0f59a212b6ae071ab7a08761cc08ae7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg6e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..364d664525fdfdda38a52f521dd9a0f009e8daab --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg7e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..0d6a391b2ea70c39bb8f5788bbd63978647c6019 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vlsseg8e16.c @@ -0,0 +1,42 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_m(vbool64_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_m(vbool32_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..2654821297402e9dc64503a8fb9cbbdf2f07f506 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4(const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2(const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8(const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vluxei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_m(vbool64_t vm, const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_m(vbool32_t vm, const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_m(vbool2_t vm, const __bf16 *rs1, + vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..b862aae053dac34a869850b584c367e8c36e9364 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg2ei16.c @@ -0,0 +1,121 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2(const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_m(vbool4_t vm, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..372523aebc995c02a902c481234d921b2d925320 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg3ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..dda3615cd2042292440e7d4f86b33012c4179954 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg4ei16.c @@ -0,0 +1,99 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4(const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_m(vbool8_t vm, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..52dbe05328d84b02c49733bc979c3198dc9d68ad --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg5ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg5ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..40cb79b3684e2713fc9ba9ee9138c1b471164adc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg6ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg6ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..00bea1db887928340c88b8baf29620b52f122ee3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg7ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg7ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..29fa54d073995867a8076606db5d920cf4569012 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vluxseg8ei16.c @@ -0,0 +1,77 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8(const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8(const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8(const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxseg8ei16(rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16(vm, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( poison, poison, poison, poison, poison, poison, poison, poison, ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 3) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_m(vbool16_t vm, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16(vm, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vreinterpret.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vreinterpret.c new file mode 100644 index 0000000000000000000000000000000000000000..2e14f42fa34603b7d1d9a66422866815ffb08468 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vreinterpret.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16mf4_bf16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vreinterpret_v_i16mf4_bf16mf4(vint16mf4_t src) { + return __riscv_vreinterpret_bf16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16mf2_bf16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vreinterpret_v_i16mf2_bf16mf2(vint16mf2_t src) { + return __riscv_vreinterpret_bf16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m1_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vreinterpret_v_i16m1_bf16m1(vint16m1_t src) { + return __riscv_vreinterpret_bf16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m2_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vreinterpret_v_i16m2_bf16m2(vint16m2_t src) { + return __riscv_vreinterpret_bf16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m4_bf16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vreinterpret_v_i16m4_bf16m4(vint16m4_t src) { + return __riscv_vreinterpret_bf16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_i16m8_bf16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vreinterpret_v_i16m8_bf16m8(vint16m8_t src) { + return __riscv_vreinterpret_bf16m8(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16mf4_bf16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vreinterpret_v_u16mf4_bf16mf4(vuint16mf4_t src) { + return __riscv_vreinterpret_bf16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16mf2_bf16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vreinterpret_v_u16mf2_bf16mf2(vuint16mf2_t src) { + return __riscv_vreinterpret_bf16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m1_bf16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vreinterpret_v_u16m1_bf16m1(vuint16m1_t src) { + return __riscv_vreinterpret_bf16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m2_bf16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vreinterpret_v_u16m2_bf16m2(vuint16m2_t src) { + return __riscv_vreinterpret_bf16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m4_bf16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vreinterpret_v_u16m4_bf16m4(vuint16m4_t src) { + return __riscv_vreinterpret_bf16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_u16m8_bf16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vreinterpret_v_u16m8_bf16m8(vuint16m8_t src) { + return __riscv_vreinterpret_bf16m8(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf4_i16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf4_t test_vreinterpret_v_bf16mf4_i16mf4(vbfloat16mf4_t src) { + return __riscv_vreinterpret_i16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf2_i16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16mf2_t test_vreinterpret_v_bf16mf2_i16mf2(vbfloat16mf2_t src) { + return __riscv_vreinterpret_i16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m1_i16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m1_t test_vreinterpret_v_bf16m1_i16m1(vbfloat16m1_t src) { + return __riscv_vreinterpret_i16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m2_i16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m2_t test_vreinterpret_v_bf16m2_i16m2(vbfloat16m2_t src) { + return __riscv_vreinterpret_i16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m4_i16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m4_t test_vreinterpret_v_bf16m4_i16m4(vbfloat16m4_t src) { + return __riscv_vreinterpret_i16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m8_i16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vint16m8_t test_vreinterpret_v_bf16m8_i16m8(vbfloat16m8_t src) { + return __riscv_vreinterpret_i16m8(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf4_u16mf4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf4_t test_vreinterpret_v_bf16mf4_u16mf4(vbfloat16mf4_t src) { + return __riscv_vreinterpret_u16mf4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16mf2_u16mf2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16mf2_t test_vreinterpret_v_bf16mf2_u16mf2(vbfloat16mf2_t src) { + return __riscv_vreinterpret_u16mf2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m1_u16m1( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m1_t test_vreinterpret_v_bf16m1_u16m1(vbfloat16m1_t src) { + return __riscv_vreinterpret_u16m1(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m2_u16m2( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m2_t test_vreinterpret_v_bf16m2_u16m2(vbfloat16m2_t src) { + return __riscv_vreinterpret_u16m2(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m4_u16m4( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m4_t test_vreinterpret_v_bf16m4_u16m4(vbfloat16m4_t src) { + return __riscv_vreinterpret_u16m4(src); +} + +// CHECK-RV64-LABEL: define dso_local @test_vreinterpret_v_bf16m8_u16m8( +// CHECK-RV64-SAME: [[SRC:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = bitcast [[SRC]] to +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vuint16m8_t test_vreinterpret_v_bf16m8_u16m8(vbfloat16m8_t src) { + return __riscv_vreinterpret_u16m8(src); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vse16.c new file mode 100644 index 0000000000000000000000000000000000000000..0fe9076b1f10e3817c8010597504f673b77a76ce --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vse16.c @@ -0,0 +1,135 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv1bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf4(__bf16 *rs1, vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vse16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv2bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf2(__bf16 *rs1, vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vse16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv4bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m1(__bf16 *rs1, vbfloat16m1_t vs3, size_t vl) { + return __riscv_vse16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv8bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m2(__bf16 *rs1, vbfloat16m2_t vs3, size_t vl) { + return __riscv_vse16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv16bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m4(__bf16 *rs1, vbfloat16m4_t vs3, size_t vl) { + return __riscv_vse16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.nxv32bf16.i64( [[VS3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m8(__bf16 *rs1, vbfloat16m8_t vs3, size_t vl) { + return __riscv_vse16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv1bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vse16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv2bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vse16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv4bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vse16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv8bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vse16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv16bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vse16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vse16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vse.mask.nxv32bf16.i64( [[VS3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vse16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vse16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c new file mode 100644 index 0000000000000000000000000000000000000000..67fb436bf22a704efddad9a40984fe84ff77c678 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vset.c @@ -0,0 +1,364 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m1_bf16m2( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv8bf16.nxv4bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vset_v_bf16m1_bf16m2(vbfloat16m2_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m1_bf16m4( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv4bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vset_v_bf16m1_bf16m4(vbfloat16m4_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m2_bf16m4( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv16bf16.nxv8bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vset_v_bf16m2_bf16m4(vbfloat16m4_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m1_bf16m8( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv4bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vset_v_bf16m1_bf16m8(vbfloat16m8_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m2_bf16m8( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv8bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vset_v_bf16m2_bf16m8(vbfloat16m8_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local @test_vset_v_bf16m4_bf16m8( +// CHECK-RV64-SAME: [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.vector.insert.nxv32bf16.nxv16bf16( [[DEST]], [[VALUE]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vset_v_bf16m4_bf16m8(vbfloat16m8_t dest, size_t index, + vbfloat16m4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16mf4_bf16mf4x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf4x2_t test_vset_v_bf16mf4_bf16mf4x2(vbfloat16mf4x2_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16mf4_bf16mf4x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf4x3_t test_vset_v_bf16mf4_bf16mf4x3(vbfloat16mf4x3_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16mf4_bf16mf4x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf4x4_t test_vset_v_bf16mf4_bf16mf4x4(vbfloat16mf4x4_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vset_v_bf16mf4_bf16mf4x5( +// CHECK-RV64-SAME: { , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf4x5_t test_vset_v_bf16mf4_bf16mf4x5(vbfloat16mf4x5_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vset_v_bf16mf4_bf16mf4x6( +// CHECK-RV64-SAME: { , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf4x6_t test_vset_v_bf16mf4_bf16mf4x6(vbfloat16mf4x6_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vset_v_bf16mf4_bf16mf4x7( +// CHECK-RV64-SAME: { , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf4x7_t test_vset_v_bf16mf4_bf16mf4x7(vbfloat16mf4x7_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vset_v_bf16mf4_bf16mf4x8( +// CHECK-RV64-SAME: { , , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf4x8_t test_vset_v_bf16mf4_bf16mf4x8(vbfloat16mf4x8_t dest, + size_t index, + vbfloat16mf4_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16mf2_bf16mf2x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16mf2x2_t test_vset_v_bf16mf2_bf16mf2x2(vbfloat16mf2x2_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16mf2_bf16mf2x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16mf2x3_t test_vset_v_bf16mf2_bf16mf2x3(vbfloat16mf2x3_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16mf2_bf16mf2x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16mf2x4_t test_vset_v_bf16mf2_bf16mf2x4(vbfloat16mf2x4_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vset_v_bf16mf2_bf16mf2x5( +// CHECK-RV64-SAME: { , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16mf2x5_t test_vset_v_bf16mf2_bf16mf2x5(vbfloat16mf2x5_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vset_v_bf16mf2_bf16mf2x6( +// CHECK-RV64-SAME: { , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16mf2x6_t test_vset_v_bf16mf2_bf16mf2x6(vbfloat16mf2x6_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vset_v_bf16mf2_bf16mf2x7( +// CHECK-RV64-SAME: { , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16mf2x7_t test_vset_v_bf16mf2_bf16mf2x7(vbfloat16mf2x7_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vset_v_bf16mf2_bf16mf2x8( +// CHECK-RV64-SAME: { , , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16mf2x8_t test_vset_v_bf16mf2_bf16mf2x8(vbfloat16mf2x8_t dest, + size_t index, + vbfloat16mf2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16m1_bf16m1x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m1x2_t test_vset_v_bf16m1_bf16m1x2(vbfloat16m1x2_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16m1_bf16m1x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m1x3_t test_vset_v_bf16m1_bf16m1x3(vbfloat16m1x3_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16m1_bf16m1x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m1x4_t test_vset_v_bf16m1_bf16m1x4(vbfloat16m1x4_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vset_v_bf16m1_bf16m1x5( +// CHECK-RV64-SAME: { , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP0]] +// +vbfloat16m1x5_t test_vset_v_bf16m1_bf16m1x5(vbfloat16m1x5_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vset_v_bf16m1_bf16m1x6( +// CHECK-RV64-SAME: { , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP0]] +// +vbfloat16m1x6_t test_vset_v_bf16m1_bf16m1x6(vbfloat16m1x6_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vset_v_bf16m1_bf16m1x7( +// CHECK-RV64-SAME: { , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP0]] +// +vbfloat16m1x7_t test_vset_v_bf16m1_bf16m1x7(vbfloat16m1x7_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vset_v_bf16m1_bf16m1x8( +// CHECK-RV64-SAME: { , , , , , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , , , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP0]] +// +vbfloat16m1x8_t test_vset_v_bf16m1_bf16m1x8(vbfloat16m1x8_t dest, size_t index, + vbfloat16m1_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16m2_bf16m2x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m2x2_t test_vset_v_bf16m2_bf16m2x2(vbfloat16m2x2_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vset_v_bf16m2_bf16m2x3( +// CHECK-RV64-SAME: { , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , } [[TMP0]] +// +vbfloat16m2x3_t test_vset_v_bf16m2_bf16m2x3(vbfloat16m2x3_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vset_v_bf16m2_bf16m2x4( +// CHECK-RV64-SAME: { , , , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , , , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , , , } [[TMP0]] +// +vbfloat16m2x4_t test_vset_v_bf16m2_bf16m2x4(vbfloat16m2x4_t dest, size_t index, + vbfloat16m2_t value) { + return __riscv_vset(dest, 0, value); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vset_v_bf16m4_bf16m4x2( +// CHECK-RV64-SAME: { , } [[DEST:%.*]], i64 noundef [[INDEX:%.*]], [[VALUE:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = insertvalue { , } [[DEST]], [[VALUE]], 0 +// CHECK-RV64-NEXT: ret { , } [[TMP0]] +// +vbfloat16m4x2_t test_vset_v_bf16m4_bf16m4x2(vbfloat16m4x2_t dest, size_t index, + vbfloat16m4_t value) { + return __riscv_vset(dest, 0, value); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..a374e019665c7afb63be5f94452187ec25611728 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf4(__bf16 *rs1, vuint16mf4_t rs2, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vsoxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf2(__bf16 *rs1, vuint16mf2_t rs2, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vsoxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m1(__bf16 *rs1, vuint16m1_t rs2, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vsoxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m2(__bf16 *rs1, vuint16m2_t rs2, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vsoxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m4(__bf16 *rs1, vuint16m4_t rs2, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vsoxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m8(__bf16 *rs1, vuint16m8_t rs2, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vsoxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vuint16mf4_t rs2, + vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vsoxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vuint16mf2_t rs2, + vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vsoxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t rs2, + vbfloat16m1_t vs3, size_t vl) { + return __riscv_vsoxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t rs2, + vbfloat16m2_t vs3, size_t vl) { + return __riscv_vsoxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t rs2, + vbfloat16m4_t vs3, size_t vl) { + return __riscv_vsoxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxei.mask.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxei16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vuint16m8_t rs2, + vbfloat16m8_t vs3, size_t vl) { + return __riscv_vsoxei16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..088ef855cd1c52ee251b34e5963a9cb54c323636 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg2ei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf4x2(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf2x2(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m1x2(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m2x2(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m4x2(__bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x2_t vs3, + size_t vl) { + return __riscv_vsoxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x2_t vs3, + size_t vl) { + return __riscv_vsoxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg2ei16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsoxseg2ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..aee2c3ce96af04d5ffb1d23fdb949170f7cfa873 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg3ei16.c @@ -0,0 +1,123 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf4x3(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf2x3(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m1x3(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m2x3(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x3_t vs3, + size_t vl) { + return __riscv_vsoxseg3ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x3_t vs3, + size_t vl) { + return __riscv_vsoxseg3ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg3ei16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsoxseg3ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..4d2232129c4e43cf4ad70ca0fd9b1593fb71001d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg4ei16.c @@ -0,0 +1,131 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf4x4(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf2x4(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m1x4(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m2x4(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x4_t vs3, + size_t vl) { + return __riscv_vsoxseg4ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x4_t vs3, + size_t vl) { + return __riscv_vsoxseg4ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg4ei16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsoxseg4ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..5975ed0cc17938dade702966469ebca9f78c2f64 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg5ei16.c @@ -0,0 +1,107 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf4x5(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf2x5(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16m1x5(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x5_t vs3, + size_t vl) { + return __riscv_vsoxseg5ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x5_t vs3, + size_t vl) { + return __riscv_vsoxseg5ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg5ei16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsoxseg5ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..cca77d6dc66876709cc207b44f1ad62b25da328a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg6ei16.c @@ -0,0 +1,113 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf4x6(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf2x6(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16m1x6(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x6_t vs3, + size_t vl) { + return __riscv_vsoxseg6ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x6_t vs3, + size_t vl) { + return __riscv_vsoxseg6ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg6ei16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsoxseg6ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..f258f74f4b259fd4b11f7eff55960b39d25872b1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg7ei16.c @@ -0,0 +1,119 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf4x7(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf2x7(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16m1x7(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x7_t vs3, + size_t vl) { + return __riscv_vsoxseg7ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x7_t vs3, + size_t vl) { + return __riscv_vsoxseg7ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg7ei16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsoxseg7ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..8f718ac3b730087395f6c7d189a086aa1b2bab2e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsoxseg8ei16.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf4x8(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf2x8(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16m1x8(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x8_t vs3, + size_t vl) { + return __riscv_vsoxseg8ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x8_t vs3, + size_t vl) { + return __riscv_vsoxseg8ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsoxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsoxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsoxseg8ei16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsoxseg8ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsse16.c new file mode 100644 index 0000000000000000000000000000000000000000..103d2bff32288e622c472f4896a6e99936f21cbd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsse16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv1bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vsse16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv2bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vsse16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv4bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m1(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vsse16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv8bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vsse16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv16bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vsse16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.nxv32bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m8(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vsse16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv1bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vsse16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv2bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vsse16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv4bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1_t vs3, size_t vl) { + return __riscv_vsse16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv8bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2_t vs3, size_t vl) { + return __riscv_vsse16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv16bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m4_t vs3, size_t vl) { + return __riscv_vsse16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsse16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsse.mask.nxv32bf16.i64( [[VS3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsse16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m8_t vs3, size_t vl) { + return __riscv_vsse16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c302d828fd0523b0e456f9c3d67c3f02e995c96c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg2e16.c @@ -0,0 +1,134 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf4x2(__bf16 *rs1, vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf2x2(__bf16 *rs1, vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m1x2(__bf16 *rs1, vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m2x2(__bf16 *rs1, vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m4x2(__bf16 *rs1, vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsseg2e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x2_t vs3, + size_t vl) { + return __riscv_vsseg2e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x2_t vs3, + size_t vl) { + return __riscv_vsseg2e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg2e16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vbfloat16m4x2_t vs3, + size_t vl) { + return __riscv_vsseg2e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..644d2145dc11862f1fdfc539dc4a13b6a582afde --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg3e16.c @@ -0,0 +1,117 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf4x3(__bf16 *rs1, vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsseg3e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf2x3(__bf16 *rs1, vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsseg3e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m1x3(__bf16 *rs1, vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsseg3e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m2x3(__bf16 *rs1, vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsseg3e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsseg3e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsseg3e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x3_t vs3, + size_t vl) { + return __riscv_vsseg3e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg3e16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x3_t vs3, + size_t vl) { + return __riscv_vsseg3e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..7dbd0577278522f6550fdc559a33d89be6e32ba3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg4e16.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf4x4(__bf16 *rs1, vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsseg4e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf2x4(__bf16 *rs1, vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsseg4e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m1x4(__bf16 *rs1, vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsseg4e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m2x4(__bf16 *rs1, vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsseg4e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsseg4e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsseg4e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x4_t vs3, + size_t vl) { + return __riscv_vsseg4e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg4e16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, vbfloat16m2x4_t vs3, + size_t vl) { + return __riscv_vsseg4e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..be8a12c0507877360c335660af174c042ca30634 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg5e16.c @@ -0,0 +1,102 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf4x5(__bf16 *rs1, vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsseg5e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf2x5(__bf16 *rs1, vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsseg5e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16m1x5(__bf16 *rs1, vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsseg5e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsseg5e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsseg5e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg5e16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x5_t vs3, + size_t vl) { + return __riscv_vsseg5e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..4de257158927032b33e3c5cde44a33b063509755 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg6e16.c @@ -0,0 +1,108 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf4x6(__bf16 *rs1, vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsseg6e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf2x6(__bf16 *rs1, vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsseg6e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16m1x6(__bf16 *rs1, vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsseg6e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsseg6e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsseg6e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg6e16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x6_t vs3, + size_t vl) { + return __riscv_vsseg6e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..24252fe479402411fce2527120076de59440d8d1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg7e16.c @@ -0,0 +1,114 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf4x7(__bf16 *rs1, vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsseg7e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf2x7(__bf16 *rs1, vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsseg7e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16m1x7(__bf16 *rs1, vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsseg7e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsseg7e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsseg7e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg7e16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x7_t vs3, + size_t vl) { + return __riscv_vsseg7e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c6f5e5db5d9c794c22b3f230337d8cfcf78980a5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsseg8e16.c @@ -0,0 +1,120 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf4x8(__bf16 *rs1, vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsseg8e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf2x8(__bf16 *rs1, vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsseg8e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16m1x8(__bf16 *rs1, vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsseg8e16(rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsseg8e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsseg8e16(vm, rs1, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsseg8e16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, vbfloat16m1x8_t vs3, + size_t vl) { + return __riscv_vsseg8e16(vm, rs1, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..ee6d701667dd46dfcac386dff147c498604f681c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg2e16.c @@ -0,0 +1,139 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf4x2(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf2x2(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m1x2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x2_t vs3, + size_t vl) { + return __riscv_vssseg2e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m2x2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2x2_t vs3, + size_t vl) { + return __riscv_vssseg2e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m4x2(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m4x2_t vs3, + size_t vl) { + return __riscv_vssseg2e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg2e16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg2e16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vssseg2e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c8562ff453642e7902fc850ddaaee2e3ed9be39f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg3e16.c @@ -0,0 +1,121 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf4x3(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vssseg3e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf2x3(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vssseg3e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m1x3(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x3_t vs3, + size_t vl) { + return __riscv_vssseg3e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m2x3(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2x3_t vs3, + size_t vl) { + return __riscv_vssseg3e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vssseg3e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vssseg3e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vssseg3e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg3e16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg3e16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vssseg3e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..64069bdc03baa4aee73f25c3216030a99eadffb8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg4e16.c @@ -0,0 +1,129 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf4x4(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vssseg4e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf2x4(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vssseg4e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m1x4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x4_t vs3, + size_t vl) { + return __riscv_vssseg4e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m2x4(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m2x4_t vs3, + size_t vl) { + return __riscv_vssseg4e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vssseg4e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vssseg4e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vssseg4e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg4e16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg4e16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vssseg4e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..00cc1066474b019593ebd5188afa83420c23d12c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg5e16.c @@ -0,0 +1,105 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf4x5(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vssseg5e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf2x5(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vssseg5e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16m1x5(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x5_t vs3, + size_t vl) { + return __riscv_vssseg5e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vssseg5e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vssseg5e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg5e16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg5e16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vssseg5e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..8be7e9fe56aadb8422af7d57b15d5fc05777452c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg6e16.c @@ -0,0 +1,111 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf4x6(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vssseg6e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf2x6(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vssseg6e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16m1x6(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x6_t vs3, + size_t vl) { + return __riscv_vssseg6e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vssseg6e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vssseg6e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg6e16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg6e16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vssseg6e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..28c17de2ea1d9aa6cca2a1280a47b6c27640b117 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg7e16.c @@ -0,0 +1,117 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf4x7(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vssseg7e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf2x7(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vssseg7e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16m1x7(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x7_t vs3, + size_t vl) { + return __riscv_vssseg7e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vssseg7e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vssseg7e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg7e16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg7e16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vssseg7e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..90f0e46cf9766674d35ca8ef6b116d2cbc4996e5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vssseg8e16.c @@ -0,0 +1,123 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf4x8(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vssseg8e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf2x8(__bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vssseg8e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16m1x8(__bf16 *rs1, ptrdiff_t rs2, vbfloat16m1x8_t vs3, + size_t vl) { + return __riscv_vssseg8e16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vssseg8e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vssseg8e16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vssseg8e16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vssseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vssseg8e16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, ptrdiff_t rs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vssseg8e16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..ef8083df5cfb78988582d8d4fa017d16a89ac760 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf4(__bf16 *rs1, vuint16mf4_t rs2, vbfloat16mf4_t vs3, + size_t vl) { + return __riscv_vsuxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf2(__bf16 *rs1, vuint16mf2_t rs2, vbfloat16mf2_t vs3, + size_t vl) { + return __riscv_vsuxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m1( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m1(__bf16 *rs1, vuint16m1_t rs2, vbfloat16m1_t vs3, + size_t vl) { + return __riscv_vsuxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m2(__bf16 *rs1, vuint16m2_t rs2, vbfloat16m2_t vs3, + size_t vl) { + return __riscv_vsuxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m4(__bf16 *rs1, vuint16m4_t rs2, vbfloat16m4_t vs3, + size_t vl) { + return __riscv_vsuxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m8(__bf16 *rs1, vuint16m8_t rs2, vbfloat16m8_t vs3, + size_t vl) { + return __riscv_vsuxei16(rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv1bf16.nxv1i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf4_m(vbool64_t vm, __bf16 *rs1, vuint16mf4_t rs2, + vbfloat16mf4_t vs3, size_t vl) { + return __riscv_vsuxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16mf2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv2bf16.nxv2i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16mf2_m(vbool32_t vm, __bf16 *rs1, vuint16mf2_t rs2, + vbfloat16mf2_t vs3, size_t vl) { + return __riscv_vsuxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m1_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv4bf16.nxv4i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m1_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t rs2, + vbfloat16m1_t vs3, size_t vl) { + return __riscv_vsuxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv8bf16.nxv8i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t rs2, + vbfloat16m2_t vs3, size_t vl) { + return __riscv_vsuxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv16bf16.nxv16i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m4_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t rs2, + vbfloat16m4_t vs3, size_t vl) { + return __riscv_vsuxei16(vm, rs1, rs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxei16_v_bf16m8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxei.mask.nxv32bf16.nxv32i16.i64( [[VS3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxei16_v_bf16m8_m(vbool2_t vm, __bf16 *rs1, vuint16m8_t rs2, + vbfloat16m8_t vs3, size_t vl) { + return __riscv_vsuxei16(vm, rs1, rs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..0ca9429723694c8be6607ba484675178f22d358d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg2ei16.c @@ -0,0 +1,141 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf4x2(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf2x2(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m1x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m1x2(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m2x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m2x2(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m4x2( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m4x2(__bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf4x2_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x2_t vs3, + size_t vl) { + return __riscv_vsuxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16mf2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16mf2x2_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x2_t vs3, + size_t vl) { + return __riscv_vsuxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m1x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m1x2_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m2x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m2x2_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg2ei16_v_bf16m4x2_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VS3]], 1 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg2ei16_v_bf16m4x2_m(vbool4_t vm, __bf16 *rs1, vuint16m4_t vs2, + vbfloat16m4x2_t vs3, size_t vl) { + return __riscv_vsuxseg2ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..873af1b1a1d802293da4b113d225a16b014365e6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg3ei16.c @@ -0,0 +1,123 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf4x3(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf2x3(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m1x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m1x3(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m2x3( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m2x3(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf4x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf4x3_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x3_t vs3, + size_t vl) { + return __riscv_vsuxseg3ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16mf2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16mf2x3_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x3_t vs3, + size_t vl) { + return __riscv_vsuxseg3ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m1x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m1x3_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg3ei16_v_bf16m2x3_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VS3]], 2 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg3ei16_v_bf16m2x3_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x3_t vs3, size_t vl) { + return __riscv_vsuxseg3ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..f0c497e107979e5d68925ba27b1ab9d12dfc6eef --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg4ei16.c @@ -0,0 +1,131 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf4x4(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf2x4(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m1x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m1x4(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m2x4( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m2x4(__bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf4x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf4x4_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x4_t vs3, + size_t vl) { + return __riscv_vsuxseg4ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16mf2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16mf2x4_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x4_t vs3, + size_t vl) { + return __riscv_vsuxseg4ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m1x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m1x4_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg4ei16_v_bf16m2x4_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg4ei16_v_bf16m2x4_m(vbool8_t vm, __bf16 *rs1, vuint16m2_t vs2, + vbfloat16m2x4_t vs3, size_t vl) { + return __riscv_vsuxseg4ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..6a2ce44b869d0e1cb26b726a30ebf23c7f8b2353 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg5ei16.c @@ -0,0 +1,107 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf4x5(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf2x5(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16m1x5( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16m1x5(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf4x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf4x5_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x5_t vs3, + size_t vl) { + return __riscv_vsuxseg5ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16mf2x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16mf2x5_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x5_t vs3, + size_t vl) { + return __riscv_vsuxseg5ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg5ei16_v_bf16m1x5_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg5ei16_v_bf16m1x5_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x5_t vs3, size_t vl) { + return __riscv_vsuxseg5ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..84827b645e34d6ed526cf830ec8d557ab0a854d3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg6ei16.c @@ -0,0 +1,113 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf4x6(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf2x6(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16m1x6( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16m1x6(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf4x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf4x6_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x6_t vs3, + size_t vl) { + return __riscv_vsuxseg6ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16mf2x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16mf2x6_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x6_t vs3, + size_t vl) { + return __riscv_vsuxseg6ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg6ei16_v_bf16m1x6_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg6ei16_v_bf16m1x6_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x6_t vs3, size_t vl) { + return __riscv_vsuxseg6ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..e8c00aaebe86db2e49765095c4c8db25c5fd6ed6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg7ei16.c @@ -0,0 +1,119 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf4x7(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf2x7(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16m1x7( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16m1x7(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf4x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf4x7_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x7_t vs3, + size_t vl) { + return __riscv_vsuxseg7ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16mf2x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16mf2x7_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x7_t vs3, + size_t vl) { + return __riscv_vsuxseg7ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg7ei16_v_bf16m1x7_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg7ei16_v_bf16m1x7_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x7_t vs3, size_t vl) { + return __riscv_vsuxseg7ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..ff96cef336ea12fc228a0cd59cba7bba770c5150 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/bfloat16/vsuxseg8ei16.c @@ -0,0 +1,125 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf4x8(__bf16 *rs1, vuint16mf4_t vs2, + vbfloat16mf4x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf2x8(__bf16 *rs1, vuint16mf2_t vs2, + vbfloat16mf2x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16m1x8( +// CHECK-RV64-SAME: ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16m1x8(__bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16(rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf4x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf4x8_m(vbool64_t vm, __bf16 *rs1, + vuint16mf4_t vs2, vbfloat16mf4x8_t vs3, + size_t vl) { + return __riscv_vsuxseg8ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16mf2x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16mf2x8_m(vbool32_t vm, __bf16 *rs1, + vuint16mf2_t vs2, vbfloat16mf2x8_t vs3, + size_t vl) { + return __riscv_vsuxseg8ei16(vm, rs1, vs2, vs3, vl); +} + +// CHECK-RV64-LABEL: define dso_local void @test_vsuxseg8ei16_v_bf16m1x8_m( +// CHECK-RV64-SAME: [[VM:%.*]], ptr noundef [[RS1:%.*]], [[VS2:%.*]], { , , , , , , , } [[VS3:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VS3]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VS3]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VS3]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VS3]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VS3]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VS3]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VS3]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VS3]], 7 +// CHECK-RV64-NEXT: call void @llvm.riscv.vsuxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VS2]], [[VM]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret void +// +void test_vsuxseg8ei16_v_bf16m1x8_m(vbool16_t vm, __bf16 *rs1, vuint16m1_t vs2, + vbfloat16m1x8_t vs3, size_t vl) { + return __riscv_vsuxseg8ei16(vm, rs1, vs2, vs3, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c index 9c91d2a1192d569001b459eb37bfe0d8ddc2a0ed..ec3cd1a5a6968ddb4df6bcfd0889492a7c7b74e7 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdf_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c index dac9eb38713b4d1cda1e01303af096593bc07dd7..85d452543db2bc3d5503d82276ddaae23fc530e0 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesdm_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c index 01875afa525efc08e40241fb75cd06a2c94aaa6e..6727ff24b83d3f50366e00c4a0c894ed178c3a43 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesef_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c index e9a0add21c92d5126ff6a186801884ba3d5b385c..6ebfd5ff4962e4c85c419d3ddd018d6a1037a31d 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vaesem_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c index c80e4ebce5e5b782e858f3fb66e8f6b82b9b3853..fe657a603d7b7561458ffdd71df14c59caedaf9a 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8(vuint32m8_t vd, vuint32m4_t vs2, size_t vl return __riscv_vaesz(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c index cfc8532835eaa3a5252416c6df8d91a9e5eef1f1..82f275af3e5002c029f69a08f837df63db840ecd 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8 -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 3) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16.c new file mode 100644 index 0000000000000000000000000000000000000000..53d8b4d625e7bffa0132c840dbb7747678ae0cd0 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf4_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m1_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m4_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m8_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf4_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m1_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m4_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m8_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf4_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m1_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m4_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m8_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf4_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16mf2_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m1_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m2_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m4_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vle16_v_bf16m8_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..b7e689e00ada59e746d056e5931efbd53c98da2d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vle16ff.c @@ -0,0 +1,321 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf4_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m1_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m4_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m8_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf4_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m1_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m4_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m8_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf4_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m1_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m4_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m8_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf4_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16mf2_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m1_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m2_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m4_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vle16ff_v_bf16m8_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..c0cacbf48d01d09728c44d7b0f6173375ca92882 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxei16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m1_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m1_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m1_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16mf2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m1_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16_v_bf16m8_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..085a3784f87e2724f767ec91d49521c7b769a56d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg2ei16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf4x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf2x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m1x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m2x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m4x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_tum(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf4x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_tum(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf2x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m1x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m2x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m4x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_tumu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf4x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_tumu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf2x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_tumu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m1x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m2x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m4x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_mu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf4x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_mu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16mf2x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m1x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m2x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_v_bf16m4x2_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..43d21bd63478bc7667786c20c7d2a75a251640bc --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg3ei16.c @@ -0,0 +1,217 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf4x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf2x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m1x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m2x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_tum(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf4x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_tum(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf2x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m1x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m2x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_tumu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf4x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_tumu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf2x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_tumu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m1x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m2x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_mu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf4x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_mu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16mf2x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m1x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_v_bf16m2x3_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..43c25cf7d5700cd0a9deb451345f057c037f2d72 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg4ei16.c @@ -0,0 +1,233 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf4x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf2x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m1x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m2x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_tum(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf4x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_tum(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf2x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m1x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m2x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_tumu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf4x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_tumu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf2x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m1x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m2x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_mu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf4x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_mu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16mf2x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m1x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_v_bf16m2x4_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..9177193a223479950afd0ff9c5347aec690426dd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg5ei16.c @@ -0,0 +1,189 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf4x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf2x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16m1x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_tum(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf4x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_tum(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf2x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16m1x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_tumu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf4x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_tumu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf2x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_tumu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16m1x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_mu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf4x5_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_mu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16mf2x5_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_v_bf16m1x5_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..6e6ef3a5a254b8c11b9bc7fd35f9e13487cc15ed --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg6ei16.c @@ -0,0 +1,201 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf4x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf2x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16m1x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_tum(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf4x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_tum(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf2x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16m1x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_tumu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf4x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_tumu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf2x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16m1x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_mu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf4x6_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_mu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16mf2x6_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_v_bf16m1x6_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..08b013399d3775504cca915b4ad091903b2f0c77 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg7ei16.c @@ -0,0 +1,213 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf4x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf2x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16m1x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_tum(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf4x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_tum(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf2x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16m1x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_tumu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf4x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_tumu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf2x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_tumu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16m1x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_mu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf4x7_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_mu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16mf2x7_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_v_bf16m1x7_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..aa738359fec3f22ef06d4be3f2ec1535b3312190 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vloxseg8ei16.c @@ -0,0 +1,225 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf4x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf2x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16m1x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_tum(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf4x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_tum(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf2x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16m1x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_tumu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf4x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_tumu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf2x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_tumu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16m1x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_mu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf4x8_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_mu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16mf2x8_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_v_bf16m1x8_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlse16.c new file mode 100644 index 0000000000000000000000000000000000000000..150d9031b24c703e29591047d70df33c4ec44b9c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlse16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m1_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m1_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m1_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16mf2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m1_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_v_bf16m8_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..61328eca7ce0cd5e47bd5d36e1c7ebb00ac798eb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf4x2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf2x2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m1x2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m2x2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m4x2_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_tum(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf4x2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_tum(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf2x2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m1x2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m2x2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m4x2_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_tumu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf4x2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_tumu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf2x2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_tumu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m1x2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m2x2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m4x2_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_mu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf4x2_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_mu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16mf2x2_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m1x2_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m2x2_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_v_bf16m4x2_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..8a0bfb50c90907a3a255757a606fedca7ce3dfab --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg2e16ff.c @@ -0,0 +1,369 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf4x2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf2x2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_tu(vbfloat16m1x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m1x2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_tu(vbfloat16m2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m2x2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_tu(vbfloat16m4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m4x2_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_tum(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf4x2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_tum(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf2x2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m1x2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m2x2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m4x2_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_tumu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf4x2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_tumu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf2x2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_tumu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m1x2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m2x2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m4x2_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_mu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf4x2_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_mu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16mf2x2_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m1x2_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m2x2_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_v_bf16m4x2_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..10ec33ec6fecd3502976e34cb9037268aa8ff61e --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16.c @@ -0,0 +1,217 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf4x3_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf2x3_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m1x3_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m2x3_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_tum(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf4x3_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_tum(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf2x3_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m1x3_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m2x3_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_tumu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf4x3_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_tumu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf2x3_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_tumu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m1x3_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m2x3_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_mu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf4x3_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_mu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16mf2x3_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m1x3_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_v_bf16m2x3_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..03cef3d745a7b39db13be8f24d72e699ef3ffc19 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg3e16ff.c @@ -0,0 +1,345 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf4x3_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf2x3_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_tu(vbfloat16m1x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m1x3_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_tu(vbfloat16m2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m2x3_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_tum(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf4x3_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_tum(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf2x3_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m1x3_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m2x3_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_tumu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf4x3_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_tumu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf2x3_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_tumu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m1x3_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m2x3_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_mu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf4x3_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_mu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16mf2x3_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m1x3_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_v_bf16m2x3_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..770458e69ecfe99070cc1de88f23be635583b96b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16.c @@ -0,0 +1,233 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf4x4_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf2x4_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m1x4_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m2x4_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tum(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf4x4_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tum(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf2x4_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m1x4_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m2x4_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tumu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf4x4_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tumu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf2x4_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m1x4_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m2x4_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_mu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf4x4_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_mu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16mf2x4_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m1x4_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_v_bf16m2x4_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..6be407d665675e8036d332acb10bd2fe6d234d77 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg4e16ff.c @@ -0,0 +1,393 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf4x4_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf2x4_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_tu(vbfloat16m1x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m1x4_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_tu(vbfloat16m2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m2x4_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_tum(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf4x4_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_tum(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf2x4_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m1x4_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m2x4_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_tumu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf4x4_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_tumu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf2x4_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m1x4_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m2x4_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_mu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf4x4_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_mu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16mf2x4_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m1x4_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_v_bf16m2x4_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..7ce59eb05effa474689ed5c2fb79a6d53b682e37 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16.c @@ -0,0 +1,189 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf4x5_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf2x5_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16m1x5_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_tum(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf4x5_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_tum(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf2x5_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16m1x5_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_tumu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf4x5_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_tumu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf2x5_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_tumu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16m1x5_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_mu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf4x5_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_mu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16mf2x5_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_v_bf16m1x5_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..08b00d68fb96f81aa1747fdd249b98050dd85388 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg5e16ff.c @@ -0,0 +1,333 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf4x5_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf2x5_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_tu(vbfloat16m1x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16m1x5_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_tum(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf4x5_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_tum(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf2x5_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16m1x5_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_tumu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf4x5_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_tumu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf2x5_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_tumu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16m1x5_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_mu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf4x5_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_mu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16mf2x5_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_v_bf16m1x5_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..1bcf360b86fe322458c53f3dd940a45a4b5f54f8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16.c @@ -0,0 +1,201 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf4x6_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf2x6_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16m1x6_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_tum(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf4x6_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_tum(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf2x6_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16m1x6_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_tumu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf4x6_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_tumu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf2x6_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16m1x6_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_mu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf4x6_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_mu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16mf2x6_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_v_bf16m1x6_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..ab2a169cf2a0aa56076b6860f7725a94e6b54ce6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg6e16ff.c @@ -0,0 +1,369 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf4x6_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf2x6_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tu(vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16m1x6_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tum(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf4x6_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tum(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf2x6_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16m1x6_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tumu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf4x6_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tumu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf2x6_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16m1x6_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_mu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf4x6_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_mu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16mf2x6_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_v_bf16m1x6_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..0147a14abcd3661d2c1f2dd53b2cc223fd9ee5ca --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16.c @@ -0,0 +1,213 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf4x7_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf2x7_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16m1x7_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_tum(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf4x7_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_tum(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf2x7_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16m1x7_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_tumu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf4x7_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_tumu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf2x7_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_tumu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16m1x7_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_mu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf4x7_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_mu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16mf2x7_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_v_bf16m1x7_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..1eee11324dba3ddc8b83aa480756d3abc1af96bb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg7e16ff.c @@ -0,0 +1,405 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf4x7_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf2x7_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_tu(vbfloat16m1x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16m1x7_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_tum(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf4x7_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_tum(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf2x7_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16m1x7_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_tumu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf4x7_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_tumu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf2x7_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_tumu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16m1x7_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_mu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf4x7_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_mu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16mf2x7_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_v_bf16m1x7_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..b11f79f4e6a4e9b424d1317c5ac6477079ee7a52 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16.c @@ -0,0 +1,225 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf4x8_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf2x8_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16m1x8_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_tum(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf4x8_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_tum(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf2x8_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16m1x8_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_tumu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf4x8_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_tumu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf2x8_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_tumu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16m1x8_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_mu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf4x8_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_mu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16mf2x8_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_v_bf16m1x8_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..4f5e3868f78cd675e48512f1f120770fb704fe80 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlseg8e16ff.c @@ -0,0 +1,441 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf4x8_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf2x8_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_tu(vbfloat16m1x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16m1x8_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_tum(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf4x8_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_tum(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf2x8_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16m1x8_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_tumu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf4x8_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_tumu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf2x8_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_tumu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16m1x8_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_mu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf4x8_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_mu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16mf2x8_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_v_bf16m1x8_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..9ab83506e3a4b5b25e937c3a3696ae57cd5c93ba --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg2e16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf4x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf2x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m1x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m2x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m4x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_tum(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf4x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_tum(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf2x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m1x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m2x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m4x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_tumu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf4x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_tumu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf2x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_tumu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m1x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m2x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m4x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_mu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf4x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_mu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16mf2x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m1x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m2x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_v_bf16m4x2_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..8e02291afd1cee8054e21737f1de010f011eda60 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg3e16.c @@ -0,0 +1,217 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf4x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf2x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m1x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m2x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_tum(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf4x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_tum(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf2x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m1x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m2x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_tumu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf4x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_tumu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf2x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_tumu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m1x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m2x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_mu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf4x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_mu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16mf2x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m1x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_v_bf16m2x3_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..c9c57d5156e2ec43fe6fc3588aa866b10dbc85c3 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg4e16.c @@ -0,0 +1,233 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf4x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf2x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m1x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m2x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_tum(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf4x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_tum(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf2x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m1x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m2x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_tumu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf4x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_tumu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf2x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m1x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m2x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_mu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf4x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_mu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16mf2x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m1x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_v_bf16m2x4_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..2f4f7e6f0f79af78db962df00a60e29223c738b2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg5e16.c @@ -0,0 +1,189 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf4x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf2x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16m1x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_tum(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf4x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_tum(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf2x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16m1x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_tumu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf4x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_tumu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf2x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_tumu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16m1x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_mu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf4x5_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_mu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16mf2x5_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_v_bf16m1x5_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..5dd8adc57c690fa2b6afbb10388902954a922ff1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg6e16.c @@ -0,0 +1,201 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf4x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf2x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16m1x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_tum(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf4x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_tum(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf2x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16m1x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_tumu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf4x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_tumu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf2x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16m1x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_mu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf4x6_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_mu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16mf2x6_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_v_bf16m1x6_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..dd6acd4906cbe5cd51bc9a8e55f6f893804acdb1 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg7e16.c @@ -0,0 +1,213 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf4x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf2x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16m1x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_tum(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf4x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_tum(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf2x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16m1x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_tumu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf4x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_tumu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf2x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_tumu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16m1x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_mu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf4x7_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_mu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16mf2x7_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_v_bf16m1x7_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..9973765dc6544940e8bb830256d1a76a8ae11271 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vlsseg8e16.c @@ -0,0 +1,225 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf4x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf2x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16m1x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_tum(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf4x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_tum(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf2x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16m1x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_tumu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf4x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_tumu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf2x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_tumu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16m1x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_mu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf4x8_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_mu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16mf2x8_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_v_bf16m1x8_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..490f594671e5e6a0e510a9b720e4cef824a61660 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxei16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m1_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m1_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m1_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16mf2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m1_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, const __bf16 *rs1, vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16_v_bf16m8_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..c363102b8c2b2f3a9cd3ca7997417ca1fa4c13cf --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg2ei16.c @@ -0,0 +1,249 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf4x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf2x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m1x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m2x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m4x2_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_tum(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf4x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_tum(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf2x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m1x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m2x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m4x2_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_tumu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf4x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_tumu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf2x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_tumu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m1x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m2x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m4x2_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_mu(vbool64_t vm, vbfloat16mf4x2_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf4x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_mu(vbool32_t vm, vbfloat16mf2x2_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16mf2x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m1x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m2x2_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, const __bf16 *rs1, vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_v_bf16m4x2_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..b93fd2b5afd487e79fc7b77c420dab2d91b47fda --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg3ei16.c @@ -0,0 +1,217 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf4x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf2x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m1x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m2x3_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_tum(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf4x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_tum(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf2x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m1x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m2x3_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_tumu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf4x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_tumu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf2x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_tumu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m1x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m2x3_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_mu(vbool64_t vm, vbfloat16mf4x3_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf4x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_mu(vbool32_t vm, vbfloat16mf2x3_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16mf2x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m1x3_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_v_bf16m2x3_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..ba48a9e1d5f5820ffd9b074ba40dacba306b4479 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg4ei16.c @@ -0,0 +1,233 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf4x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf2x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m1x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m2x4_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_tum(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf4x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_tum(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf2x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m1x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m2x4_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_tumu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf4x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_tumu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf2x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m1x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m2x4_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_mu(vbool64_t vm, vbfloat16mf4x4_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf4x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_mu(vbool32_t vm, vbfloat16mf2x4_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16mf2x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m1x4_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, const __bf16 *rs1, vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_v_bf16m2x4_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..9e8443b135a63542fd9855ccca13d9293df42609 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg5ei16.c @@ -0,0 +1,189 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf4x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf2x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16m1x5_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_tum(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf4x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_tum(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf2x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16m1x5_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_tumu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf4x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_tumu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf2x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_tumu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16m1x5_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_mu(vbool64_t vm, vbfloat16mf4x5_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf4x5_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_mu(vbool32_t vm, vbfloat16mf2x5_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16mf2x5_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_v_bf16m1x5_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..635baa5378ba7f26d068a56f75649ba4b7d6dcdf --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg6ei16.c @@ -0,0 +1,201 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf4x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf2x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16m1x6_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_tum(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf4x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_tum(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf2x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16m1x6_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_tumu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf4x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_tumu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf2x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16m1x6_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_mu(vbool64_t vm, vbfloat16mf4x6_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf4x6_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_mu(vbool32_t vm, vbfloat16mf2x6_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16mf2x6_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_v_bf16m1x6_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..69045bc79853d65ac5dde187f181a24b18776e60 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg7ei16.c @@ -0,0 +1,213 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf4x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf2x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16m1x7_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_tum(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf4x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_tum(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf2x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16m1x7_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_tumu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf4x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_tumu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf2x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_tumu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16m1x7_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_mu(vbool64_t vm, vbfloat16mf4x7_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf4x7_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_mu(vbool32_t vm, vbfloat16mf2x7_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16mf2x7_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_v_bf16m1x7_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..17cb9dd26a75558d7e9a1bc73e02bac8bf24043f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/bfloat16/vluxseg8ei16.c @@ -0,0 +1,225 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf4x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf2x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16m1x8_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_tum(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf4x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_tum(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf2x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16m1x8_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_tumu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf4x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_tumu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf2x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_tumu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16m1x8_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_mu(vbool64_t vm, vbfloat16mf4x8_t vd, const __bf16 *rs1, vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf4x8_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_mu(vbool32_t vm, vbfloat16mf2x8_t vd, const __bf16 *rs1, vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16mf2x8_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, const __bf16 *rs1, vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_v_bf16m1x8_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c index 8c18e323f7ceca225f58a82e504c64bd327c3675..27457c8f3af9b9643c54e616b67d14bf8112dc11 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdf_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c index 7566be80e9d93df4098541d3187a954ce8eb5e89..e23194eac3dcbb3b430b6c858e550c88bb008811 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdm_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c index ddeed6e78be1327e746e1229fd51d782cb097a5e..4e99777b57fbcf93acec1ee568bc11184f4a8e7f 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesef_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c index 2bd6350798f64348d0a1c96d409643602287a54d..7488792effd4297fbc6a8c8675b91ac604aa99a6 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesem_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c index 101efd751f86e3f6310854536f38026fa903892a..08291a2cbca6be16f2265c970560c09967b03ef2 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8_tu(vuint32m8_t vd, vuint32m4_t vs2, size_t return __riscv_vaesz_vs_u32m4_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c index c58f8d22d4601de639e882ca476b13d52cbf29a8..11faf7f36d23ef971d622b5e0efcd52a5908397c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv_u32m8_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs_u32m8_u32m8_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16.c new file mode 100644 index 0000000000000000000000000000000000000000..bc7996306cc3be3803778dc46b4e0f21991b1134 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16.c @@ -0,0 +1,273 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, + size_t vl) { + return __riscv_vle16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vle16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vle16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vle16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vle16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vle16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vle.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vle16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vle16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..75ad618e426284d72a7f16dca17399f9e540ae95 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vle16ff.c @@ -0,0 +1,363 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 2 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vle16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf4_t test_vle16ff_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16mf2_t test_vle16ff_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m1_t test_vle16ff_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m2_t test_vle16ff_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m4_t test_vle16ff_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vle16ff_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call { , i64 } @llvm.riscv.vleff.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , i64 } [[TMP0]], 0 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , i64 } [[TMP0]], 1 +// CHECK-RV64-NEXT: store i64 [[TMP2]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret [[TMP1]] +// +vbfloat16m8_t test_vle16ff_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, size_t *new_vl, + size_t vl) { + return __riscv_vle16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..389031e75c7401fc1c028c0d0d81cec050a66830 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxei16.c @@ -0,0 +1,291 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, + vuint16m8_t rs2, size_t vl) { + return __riscv_vloxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vloxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vloxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vloxei16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vloxei16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vloxei16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vloxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vloxei16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vloxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vloxei16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vloxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vloxei16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vloxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vloxei16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vloxei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..eab9cb4d632eca15a500d7903bce7d3b0a849971 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg2ei16.c @@ -0,0 +1,306 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_tum(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_tum(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_tum(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_tum(vbool8_t vm, + vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_tum(vbool4_t vm, + vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_tumu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_tumu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_tumu(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_tumu(vbool8_t vm, + vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_tumu(vbool4_t vm, + vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vloxseg2ei16_v_bf16mf4x2_mu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vloxseg2ei16_v_bf16mf2x2_mu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vloxseg2ei16_v_bf16m1x2_mu(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vloxseg2ei16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vloxseg2ei16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vloxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vloxseg2ei16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vloxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..ba5294df12542d6b0d2bf94aa3709389fef001e8 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg3ei16.c @@ -0,0 +1,264 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_tum(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_tum(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_tum(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_tum(vbool8_t vm, + vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_tumu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_tumu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_tumu(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_tumu(vbool8_t vm, + vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vloxseg3ei16_v_bf16mf4x3_mu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vloxseg3ei16_v_bf16mf2x3_mu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vloxseg3ei16_v_bf16m1x3_mu(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vloxseg3ei16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vloxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vloxseg3ei16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..94e96b9875a1b7ae2cec7e3312f667dcf21d8848 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg4ei16.c @@ -0,0 +1,280 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_tum(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_tum(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_tum(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_tum(vbool8_t vm, + vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_tumu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_tumu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_tumu(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_tumu(vbool8_t vm, + vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vloxseg4ei16_v_bf16mf4x4_mu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vloxseg4ei16_v_bf16mf2x4_mu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vloxseg4ei16_v_bf16m1x4_mu(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vloxseg4ei16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vloxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vloxseg4ei16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vloxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..54f1a6626d4895d3c18aa992e570e6ce1507b8c5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg5ei16.c @@ -0,0 +1,226 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_tum(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg5ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_tum(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg5ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_tum(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_tumu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg5ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_tumu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg5ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_tumu(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vloxseg5ei16_v_bf16mf4x5_mu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vloxseg5ei16_v_bf16mf2x5_mu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vloxseg5ei16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vloxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vloxseg5ei16_v_bf16m1x5_mu(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg5ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..a1ee2af0de3d8a00cd6115126748a5912fd967d2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg6ei16.c @@ -0,0 +1,238 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_tum(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg6ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_tum(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg6ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_tum(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_tumu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg6ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_tumu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg6ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_tumu(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vloxseg6ei16_v_bf16mf4x6_mu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vloxseg6ei16_v_bf16mf2x6_mu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vloxseg6ei16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vloxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vloxseg6ei16_v_bf16m1x6_mu(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg6ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..6b9cd5cf05267d78d420636940e0d0fa964cb786 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg7ei16.c @@ -0,0 +1,250 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_tum(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg7ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_tum(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg7ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_tum(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_tumu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg7ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_tumu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg7ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_tumu(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vloxseg7ei16_v_bf16mf4x7_mu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vloxseg7ei16_v_bf16mf2x7_mu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vloxseg7ei16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vloxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vloxseg7ei16_v_bf16m1x7_mu(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg7ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..f743b83d83c0fb02438b145e4515493f4cff14ca --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vloxseg8ei16.c @@ -0,0 +1,262 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_tum(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg8ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_tum(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg8ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_tum(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_tumu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vloxseg8ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_tumu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vloxseg8ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_tumu(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vloxseg8ei16_v_bf16mf4x8_mu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vloxseg8ei16_v_bf16mf2x8_mu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vloxseg8ei16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vloxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vloxseg8ei16_v_bf16m1x8_mu(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vloxseg8ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlse16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlse16.c new file mode 100644 index 0000000000000000000000000000000000000000..95652db60be027b7e497e9d7756ec90706a0a950 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlse16.c @@ -0,0 +1,291 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlse16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv1bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vlse16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv2bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vlse16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv4bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vlse16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv8bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vlse16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv16bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vlse16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vlse16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vlse.mask.nxv32bf16.i64( [[VD]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vlse16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlse16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..2d15ad7713e01ac03f00a6930abcc7c71b48816a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16.c @@ -0,0 +1,275 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_tum(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_tum(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_tumu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_tumu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_tumu(vbool16_t vm, vbfloat16m1x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlseg2e16_v_bf16mf4x2_mu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlseg2e16_v_bf16mf2x2_mu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlseg2e16_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlseg2e16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlseg2e16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg2e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..d08cb9254e1ee19211bb58a7227e210cea596754 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg2e16ff.c @@ -0,0 +1,419 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_tu(vbfloat16m1x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_tu(vbfloat16m2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_tu(vbfloat16m4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_tum(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_tum(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_tum(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_tumu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_tumu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_tumu(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_tumu(vbool8_t vm, + vbfloat16m2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_tumu(vbool4_t vm, + vbfloat16m4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf4x2_t test_vlseg2e16ff_v_bf16mf4x2_mu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16mf2x2_t test_vlseg2e16ff_v_bf16mf2x2_mu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m1x2_t test_vlseg2e16ff_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m2x2_t test_vlseg2e16ff_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlseg2e16ff_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , , i64 } @llvm.riscv.vlseg2ff.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , i64 } [[TMP2]], 0 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = insertvalue { , } poison, [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , i64 } [[TMP2]], 1 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , } [[TMP4]], [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , i64 } [[TMP2]], 2 +// CHECK-RV64-NEXT: store i64 [[TMP7]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , } [[TMP6]] +// +vbfloat16m4x2_t test_vlseg2e16ff_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg2e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..336e8d0b898389dfe0d4dba433fcd529b3bb1c52 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16.c @@ -0,0 +1,239 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_tum(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_tum(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_tumu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_tumu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_tumu(vbool16_t vm, vbfloat16m1x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlseg3e16_v_bf16mf4x3_mu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlseg3e16_v_bf16mf2x3_mu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlseg3e16_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlseg3e16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg3e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..7dc19f9199c6972297f8a42cfb2d68dfeb9b9753 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg3e16ff.c @@ -0,0 +1,386 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_tu(vbfloat16m1x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_tu(vbfloat16m2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_tum(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_tum(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_tum(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_tumu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_tumu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_tumu(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_tumu(vbool8_t vm, + vbfloat16m2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf4x3_t test_vlseg3e16ff_v_bf16mf4x3_mu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16mf2x3_t test_vlseg3e16ff_v_bf16mf2x3_mu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m1x3_t test_vlseg3e16ff_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlseg3e16ff_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , , i64 } @llvm.riscv.vlseg3ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , i64 } [[TMP3]], 0 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = insertvalue { , , } poison, [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , i64 } [[TMP3]], 1 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , } [[TMP5]], [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , i64 } [[TMP3]], 2 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , } [[TMP7]], [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , i64 } [[TMP3]], 3 +// CHECK-RV64-NEXT: store i64 [[TMP10]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , } [[TMP9]] +// +vbfloat16m2x3_t test_vlseg3e16ff_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg3e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..ddb335cc242e6d82d215d5d66f954cb4928c11ee --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16.c @@ -0,0 +1,255 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tum(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tum(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_tumu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_tumu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_tumu(vbool16_t vm, vbfloat16m1x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlseg4e16_v_bf16mf4x4_mu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlseg4e16_v_bf16mf2x4_mu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlseg4e16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlseg4e16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg4e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..b16766c184d16c42549ce3eb0de774deb2c518e6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg4e16ff.c @@ -0,0 +1,434 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_tu(vbfloat16m1x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_tu(vbfloat16m2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_tum(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_tum(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_tum(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_tumu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_tumu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_tumu(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_tumu(vbool8_t vm, + vbfloat16m2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf4x4_t test_vlseg4e16ff_v_bf16mf4x4_mu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16mf2x4_t test_vlseg4e16ff_v_bf16mf2x4_mu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m1x4_t test_vlseg4e16ff_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlseg4e16ff_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , , i64 } @llvm.riscv.vlseg4ff.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 0 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = insertvalue { , , , } poison, [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 1 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , } [[TMP6]], [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 2 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , } [[TMP8]], [[TMP9]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 3 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , } [[TMP10]], [[TMP11]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , i64 } [[TMP4]], 4 +// CHECK-RV64-NEXT: store i64 [[TMP13]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , } [[TMP12]] +// +vbfloat16m2x4_t test_vlseg4e16ff_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg4e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..8b8fb4457de2b282f9bc54a4d7b802fcdf580e7b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16.c @@ -0,0 +1,207 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_tum(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_tum(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_tumu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_tumu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_tumu(vbool16_t vm, vbfloat16m1x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlseg5e16_v_bf16mf4x5_mu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlseg5e16_v_bf16mf2x5_mu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlseg5e16_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg5e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..7aab7e9e205da96594bf0decf59ec3f3ef71b0ae --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg5e16ff.c @@ -0,0 +1,365 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_tu(vbfloat16m1x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_tum(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_tum(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_tum(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_tumu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_tumu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_tumu(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf4x5_t test_vlseg5e16ff_v_bf16mf4x5_mu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16mf2x5_t test_vlseg5e16ff_v_bf16mf2x5_mu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlseg5e16ff_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , , i64 } @llvm.riscv.vlseg5ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 0 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = insertvalue { , , , , } poison, [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 1 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , } [[TMP7]], [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 2 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , } [[TMP9]], [[TMP10]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 3 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , } [[TMP11]], [[TMP12]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 4 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , } [[TMP13]], [[TMP14]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , i64 } [[TMP5]], 5 +// CHECK-RV64-NEXT: store i64 [[TMP16]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , } [[TMP15]] +// +vbfloat16m1x5_t test_vlseg5e16ff_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg5e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..916997df7eb2dd1f1624e8e03b2ab25cd336cbe7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16.c @@ -0,0 +1,219 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_tum(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_tum(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_tumu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_tumu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_tumu(vbool16_t vm, vbfloat16m1x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlseg6e16_v_bf16mf4x6_mu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlseg6e16_v_bf16mf2x6_mu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlseg6e16_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg6e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..7d269acd4a1adf956cfb93732e6d7e85f74ad133 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg6e16ff.c @@ -0,0 +1,401 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tu(vbfloat16m1x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tum(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tum(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tum(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_tumu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_tumu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_tumu(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf4x6_t test_vlseg6e16ff_v_bf16mf4x6_mu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16mf2x6_t test_vlseg6e16ff_v_bf16mf2x6_mu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlseg6e16ff_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , , i64 } @llvm.riscv.vlseg6ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 0 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = insertvalue { , , , , , } poison, [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 1 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , } [[TMP8]], [[TMP9]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 2 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , } [[TMP10]], [[TMP11]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 3 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , } [[TMP12]], [[TMP13]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 4 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , } [[TMP14]], [[TMP15]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 5 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , } [[TMP16]], [[TMP17]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , i64 } [[TMP6]], 6 +// CHECK-RV64-NEXT: store i64 [[TMP19]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP18]] +// +vbfloat16m1x6_t test_vlseg6e16ff_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg6e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d664f6c24e4b156d2297dad73b3d244985c419fb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16.c @@ -0,0 +1,231 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_tum(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_tum(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_tumu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_tumu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_tumu(vbool16_t vm, vbfloat16m1x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlseg7e16_v_bf16mf4x7_mu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlseg7e16_v_bf16mf2x7_mu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlseg7e16_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg7e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..bf7920a7f613a031d9d981f83c48fafb4050e4a9 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg7e16ff.c @@ -0,0 +1,437 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_tu(vbfloat16m1x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_tum(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_tum(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_tum(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_tumu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_tumu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_tumu(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf4x7_t test_vlseg7e16ff_v_bf16mf4x7_mu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16mf2x7_t test_vlseg7e16ff_v_bf16mf2x7_mu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlseg7e16ff_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , , i64 } @llvm.riscv.vlseg7ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP8:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 0 +// CHECK-RV64-NEXT: [[TMP9:%.*]] = insertvalue { , , , , , , } poison, [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 1 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = insertvalue { , , , , , , } [[TMP9]], [[TMP10]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 2 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = insertvalue { , , , , , , } [[TMP11]], [[TMP12]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 3 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = insertvalue { , , , , , , } [[TMP13]], [[TMP14]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 4 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = insertvalue { , , , , , , } [[TMP15]], [[TMP16]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 5 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = insertvalue { , , , , , , } [[TMP17]], [[TMP18]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 6 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = insertvalue { , , , , , , } [[TMP19]], [[TMP20]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = extractvalue { , , , , , , , i64 } [[TMP7]], 7 +// CHECK-RV64-NEXT: store i64 [[TMP22]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP21]] +// +vbfloat16m1x7_t test_vlseg7e16ff_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg7e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..66d7b64611f9a17c61d1a10bae26f56414dde176 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16.c @@ -0,0 +1,243 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tu(vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_tum(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_tum(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tum(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_tumu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_tumu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_tumu(vbool16_t vm, vbfloat16m1x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_tumu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlseg8e16_v_bf16mf4x8_mu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlseg8e16_v_bf16mf2x8_mu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_mu(vm, vd, rs1, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlseg8e16_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, + const __bf16 *rs1, size_t vl) { + return __riscv_vlseg8e16_mu(vm, vd, rs1, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c new file mode 100644 index 0000000000000000000000000000000000000000..049984355afee70f4bc9f12461690d22af64d6a7 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlseg8e16ff.c @@ -0,0 +1,473 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[VL]]) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_tu(vbfloat16m1x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tu(vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_tum(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_tum(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_tum(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tum(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_tumu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_tumu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_tumu(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_tumu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf4x8_t test_vlseg8e16ff_v_bf16mf4x8_mu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16mf2x8_t test_vlseg8e16ff_v_bf16mf2x8_mu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(vm, vd, rs1, new_vl, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlseg8e16ff_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], ptr noundef [[NEW_VL:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , , i64 } @llvm.riscv.vlseg8ff.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: [[TMP9:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 0 +// CHECK-RV64-NEXT: [[TMP10:%.*]] = insertvalue { , , , , , , , } poison, [[TMP9]], 0 +// CHECK-RV64-NEXT: [[TMP11:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 1 +// CHECK-RV64-NEXT: [[TMP12:%.*]] = insertvalue { , , , , , , , } [[TMP10]], [[TMP11]], 1 +// CHECK-RV64-NEXT: [[TMP13:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 2 +// CHECK-RV64-NEXT: [[TMP14:%.*]] = insertvalue { , , , , , , , } [[TMP12]], [[TMP13]], 2 +// CHECK-RV64-NEXT: [[TMP15:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 3 +// CHECK-RV64-NEXT: [[TMP16:%.*]] = insertvalue { , , , , , , , } [[TMP14]], [[TMP15]], 3 +// CHECK-RV64-NEXT: [[TMP17:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 4 +// CHECK-RV64-NEXT: [[TMP18:%.*]] = insertvalue { , , , , , , , } [[TMP16]], [[TMP17]], 4 +// CHECK-RV64-NEXT: [[TMP19:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 5 +// CHECK-RV64-NEXT: [[TMP20:%.*]] = insertvalue { , , , , , , , } [[TMP18]], [[TMP19]], 5 +// CHECK-RV64-NEXT: [[TMP21:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 6 +// CHECK-RV64-NEXT: [[TMP22:%.*]] = insertvalue { , , , , , , , } [[TMP20]], [[TMP21]], 6 +// CHECK-RV64-NEXT: [[TMP23:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 7 +// CHECK-RV64-NEXT: [[TMP24:%.*]] = insertvalue { , , , , , , , } [[TMP22]], [[TMP23]], 7 +// CHECK-RV64-NEXT: [[TMP25:%.*]] = extractvalue { , , , , , , , , i64 } [[TMP8]], 8 +// CHECK-RV64-NEXT: store i64 [[TMP25]], ptr [[NEW_VL]], align 8 +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP24]] +// +vbfloat16m1x8_t test_vlseg8e16ff_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, + const __bf16 *rs1, + size_t *new_vl, size_t vl) { + return __riscv_vlseg8e16ff_mu(vm, vd, rs1, new_vl, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c new file mode 100644 index 0000000000000000000000000000000000000000..ad0cc42d2304c44f3a534c8212d02adf2ab0ed37 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg2e16.c @@ -0,0 +1,296 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_tum(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_tum(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_tum(vbool16_t vm, vbfloat16m1x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_tum(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_tum(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_tumu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_tumu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_tumu(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_tumu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_tumu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vlsseg2e16_v_bf16mf4x2_mu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vlsseg2e16_v_bf16mf2x2_mu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg2e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vlsseg2e16_v_bf16m1x2_mu(vbool16_t vm, vbfloat16m1x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vlsseg2e16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vlsseg2e16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vlsseg2.mask.nxv16bf16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vlsseg2e16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg2e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c new file mode 100644 index 0000000000000000000000000000000000000000..d9866c24dcdd047cd0e4b972e6534d8fb1e10a87 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg3e16.c @@ -0,0 +1,256 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_tum(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_tum(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_tum(vbool16_t vm, vbfloat16m1x3_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_tum(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_tumu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_tumu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_tumu(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_tumu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vlsseg3e16_v_bf16mf4x3_mu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vlsseg3e16_v_bf16mf2x3_mu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg3e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vlsseg3e16_v_bf16m1x3_mu(vbool16_t vm, vbfloat16m1x3_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vlsseg3e16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vlsseg3.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vlsseg3e16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg3e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c new file mode 100644 index 0000000000000000000000000000000000000000..ceb8e7412d06fae552b487538f50e23520d9fa8a --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg4e16.c @@ -0,0 +1,272 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_tum(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_tum(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_tum(vbool16_t vm, vbfloat16m1x4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_tum(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_tumu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_tumu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_tumu(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_tumu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vlsseg4e16_v_bf16mf4x4_mu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vlsseg4e16_v_bf16mf2x4_mu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg4e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vlsseg4e16_v_bf16m1x4_mu(vbool16_t vm, vbfloat16m1x4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vlsseg4e16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vlsseg4.mask.nxv8bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vlsseg4e16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg4e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c new file mode 100644 index 0000000000000000000000000000000000000000..ff43061fc70d2e8e5b028825d392fbb6995fa9db --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg5e16.c @@ -0,0 +1,220 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg5e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_tum(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_tum(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_tum(vbool16_t vm, vbfloat16m1x5_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg5e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_tumu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_tumu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_tumu(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vlsseg5e16_v_bf16mf4x5_mu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vlsseg5e16_v_bf16mf2x5_mu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg5e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vlsseg5e16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vlsseg5.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vlsseg5e16_v_bf16m1x5_mu(vbool16_t vm, vbfloat16m1x5_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg5e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c new file mode 100644 index 0000000000000000000000000000000000000000..4220e8e07839191224e43852cc8c1e5204f96191 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg6e16.c @@ -0,0 +1,232 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg6e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_tum(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_tum(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_tum(vbool16_t vm, vbfloat16m1x6_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg6e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_tumu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_tumu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_tumu(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vlsseg6e16_v_bf16mf4x6_mu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vlsseg6e16_v_bf16mf2x6_mu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg6e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vlsseg6e16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vlsseg6.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vlsseg6e16_v_bf16m1x6_mu(vbool16_t vm, vbfloat16m1x6_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg6e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c new file mode 100644 index 0000000000000000000000000000000000000000..45705a6dae78ea52fd7e590af0a4fb1385a9843f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg7e16.c @@ -0,0 +1,244 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg7e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_tum(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_tum(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_tum(vbool16_t vm, vbfloat16m1x7_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg7e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_tumu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_tumu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_tumu(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vlsseg7e16_v_bf16mf4x7_mu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vlsseg7e16_v_bf16mf2x7_mu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg7e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vlsseg7e16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vlsseg7.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vlsseg7e16_v_bf16m1x7_mu(vbool16_t vm, vbfloat16m1x7_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg7e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg8e16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg8e16.c new file mode 100644 index 0000000000000000000000000000000000000000..dd3a5fd367345abef770b84e8de8b01296a7cea5 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vlsseg8e16.c @@ -0,0 +1,256 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg8e16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_tum(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_tum(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_tum(vbool16_t vm, vbfloat16m1x8_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg8e16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_tumu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_tumu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_tumu(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv1bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vlsseg8e16_v_bf16mf4x8_mu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv2bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vlsseg8e16_v_bf16mf2x8_mu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + ptrdiff_t rs2, size_t vl) { + return __riscv_vlsseg8e16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vlsseg8e16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], i64 noundef [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vlsseg8.mask.nxv4bf16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], i64 [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vlsseg8e16_v_bf16m1x8_mu(vbool16_t vm, vbfloat16m1x8_t vd, + const __bf16 *rs1, ptrdiff_t rs2, + size_t vl) { + return __riscv_vlsseg8e16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxei16.c new file mode 100644 index 0000000000000000000000000000000000000000..10e7fb56146198944537a46673d546052fa8c6e2 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxei16.c @@ -0,0 +1,291 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_tu(vbfloat16mf4_t vd, const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_tu(vbfloat16mf2_t vd, const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_tu(vbfloat16m1_t vd, const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_tu(vbfloat16m2_t vd, const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_tu(vbfloat16m4_t vd, const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_tu( +// CHECK-RV64-SAME: [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_tu(vbfloat16m8_t vd, const __bf16 *rs1, + vuint16m8_t rs2, size_t vl) { + return __riscv_vluxei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_tum(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_tum(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_tum(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_tum(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_tum(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_tum(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vluxei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_tumu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_tumu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_tumu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_tumu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_tumu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_tumu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vluxei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv1bf16.nxv1i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf4_t test_vluxei16_v_bf16mf4_mu(vbool64_t vm, vbfloat16mf4_t vd, + const __bf16 *rs1, vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16mf2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv2bf16.nxv2i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16mf2_t test_vluxei16_v_bf16mf2_mu(vbool32_t vm, vbfloat16mf2_t vd, + const __bf16 *rs1, vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m1_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv4bf16.nxv4i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m1_t test_vluxei16_v_bf16m1_mu(vbool16_t vm, vbfloat16m1_t vd, + const __bf16 *rs1, vuint16m1_t rs2, + size_t vl) { + return __riscv_vluxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv8bf16.nxv8i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m2_t test_vluxei16_v_bf16m2_mu(vbool8_t vm, vbfloat16m2_t vd, + const __bf16 *rs1, vuint16m2_t rs2, + size_t vl) { + return __riscv_vluxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv16bf16.nxv16i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m4_t test_vluxei16_v_bf16m4_mu(vbool4_t vm, vbfloat16m4_t vd, + const __bf16 *rs1, vuint16m4_t rs2, + size_t vl) { + return __riscv_vluxei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local @test_vluxei16_v_bf16m8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vluxei.mask.nxv32bf16.nxv32i16.i64( [[VD]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret [[TMP0]] +// +vbfloat16m8_t test_vluxei16_v_bf16m8_mu(vbool2_t vm, vbfloat16m8_t vd, + const __bf16 *rs1, vuint16m8_t rs2, + size_t vl) { + return __riscv_vluxei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..40b94c5d40767b00249a970c409c708b9c1b7beb --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg2ei16.c @@ -0,0 +1,306 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_tu(vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_tu(vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_tu(vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_tu(vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_tu( +// CHECK-RV64-SAME: { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_tu(vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_tum(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_tum(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_tum(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_tum(vbool8_t vm, + vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_tum(vbool4_t vm, + vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_tumu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_tumu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_tumu(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_tumu(vbool8_t vm, + vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_tumu(vbool4_t vm, + vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf4x2_t test_vluxseg2ei16_v_bf16mf4x2_mu(vbool64_t vm, + vbfloat16mf4x2_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16mf2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16mf2x2_t test_vluxseg2ei16_v_bf16mf2x2_mu(vbool32_t vm, + vbfloat16mf2x2_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m1x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m1x2_t test_vluxseg2ei16_v_bf16m1x2_mu(vbool16_t vm, + vbfloat16m1x2_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m2x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m2x2_t test_vluxseg2ei16_v_bf16m2x2_mu(vbool8_t vm, vbfloat16m2x2_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , } @test_vluxseg2ei16_v_bf16m4x2_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = call { , } @llvm.riscv.vluxseg2.mask.nxv16bf16.nxv16i16.i64( [[TMP0]], [[TMP1]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , } [[TMP2]] +// +vbfloat16m4x2_t test_vluxseg2ei16_v_bf16m4x2_mu(vbool4_t vm, vbfloat16m4x2_t vd, + const __bf16 *rs1, + vuint16m4_t rs2, size_t vl) { + return __riscv_vluxseg2ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..305e811f197b51eb571ed3a747ee881e8eda91a6 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg3ei16.c @@ -0,0 +1,264 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_tu(vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_tu(vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_tu(vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_tu( +// CHECK-RV64-SAME: { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_tu(vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_tum(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_tum(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_tum(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_tum(vbool8_t vm, + vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_tumu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_tumu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_tumu(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_tumu(vbool8_t vm, + vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf4x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf4x3_t test_vluxseg3ei16_v_bf16mf4x3_mu(vbool64_t vm, + vbfloat16mf4x3_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16mf2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16mf2x3_t test_vluxseg3ei16_v_bf16mf2x3_mu(vbool32_t vm, + vbfloat16mf2x3_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m1x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m1x3_t test_vluxseg3ei16_v_bf16m1x3_mu(vbool16_t vm, + vbfloat16m1x3_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , } @test_vluxseg3ei16_v_bf16m2x3_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = call { , , } @llvm.riscv.vluxseg3.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , } [[TMP3]] +// +vbfloat16m2x3_t test_vluxseg3ei16_v_bf16m2x3_mu(vbool8_t vm, vbfloat16m2x3_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg3ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg4ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg4ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..eeb7834b44eff0af262d698be2e6ae2c0cf929f4 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg4ei16.c @@ -0,0 +1,280 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_tu(vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_tu(vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_tu(vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_tu( +// CHECK-RV64-SAME: { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_tu(vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_tum(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_tum(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_tum(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_tum(vbool8_t vm, + vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_tumu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_tumu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_tumu(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_tumu(vbool8_t vm, + vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf4x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf4x4_t test_vluxseg4ei16_v_bf16mf4x4_mu(vbool64_t vm, + vbfloat16mf4x4_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16mf2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16mf2x4_t test_vluxseg4ei16_v_bf16mf2x4_mu(vbool32_t vm, + vbfloat16mf2x4_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m1x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m1x4_t test_vluxseg4ei16_v_bf16m1x4_mu(vbool16_t vm, + vbfloat16m1x4_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , } @test_vluxseg4ei16_v_bf16m2x4_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = call { , , , } @llvm.riscv.vluxseg4.mask.nxv8bf16.nxv8i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , } [[TMP4]] +// +vbfloat16m2x4_t test_vluxseg4ei16_v_bf16m2x4_mu(vbool8_t vm, vbfloat16m2x4_t vd, + const __bf16 *rs1, + vuint16m2_t rs2, size_t vl) { + return __riscv_vluxseg4ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..0efa49935450a96f9e9a905b683d4214cd92d320 --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg5ei16.c @@ -0,0 +1,226 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_tu(vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_tu(vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_tu( +// CHECK-RV64-SAME: { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_tu(vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_tum(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg5ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_tum(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg5ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_tum(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_tumu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg5ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_tumu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg5ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_tumu(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf4x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf4x5_t test_vluxseg5ei16_v_bf16mf4x5_mu(vbool64_t vm, + vbfloat16mf4x5_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16mf2x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16mf2x5_t test_vluxseg5ei16_v_bf16mf2x5_mu(vbool32_t vm, + vbfloat16mf2x5_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , } @test_vluxseg5ei16_v_bf16m1x5_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = call { , , , , } @llvm.riscv.vluxseg5.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , } [[TMP5]] +// +vbfloat16m1x5_t test_vluxseg5ei16_v_bf16m1x5_mu(vbool16_t vm, + vbfloat16m1x5_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg5ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..42f09322f7b72dcd649119e3025547025551766d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg6ei16.c @@ -0,0 +1,238 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_tu(vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_tu(vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_tu( +// CHECK-RV64-SAME: { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_tu(vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_tum(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg6ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_tum(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg6ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_tum(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_tumu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg6ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_tumu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg6ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_tumu(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf4x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf4x6_t test_vluxseg6ei16_v_bf16mf4x6_mu(vbool64_t vm, + vbfloat16mf4x6_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16mf2x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16mf2x6_t test_vluxseg6ei16_v_bf16mf2x6_mu(vbool32_t vm, + vbfloat16mf2x6_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , } @test_vluxseg6ei16_v_bf16m1x6_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = call { , , , , , } @llvm.riscv.vluxseg6.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , } [[TMP6]] +// +vbfloat16m1x6_t test_vluxseg6ei16_v_bf16m1x6_mu(vbool16_t vm, + vbfloat16m1x6_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg6ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..7a6f6eef4e0b5d22e1b037e0c2f39002a5b1974c --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg7ei16.c @@ -0,0 +1,250 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_tu(vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_tu(vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_tu( +// CHECK-RV64-SAME: { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_tu(vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_tum(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg7ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_tum(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg7ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_tum(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_tumu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg7ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_tumu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg7ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_tumu(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf4x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf4x7_t test_vluxseg7ei16_v_bf16mf4x7_mu(vbool64_t vm, + vbfloat16mf4x7_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16mf2x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16mf2x7_t test_vluxseg7ei16_v_bf16mf2x7_mu(vbool32_t vm, + vbfloat16mf2x7_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , } @test_vluxseg7ei16_v_bf16m1x7_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = call { , , , , , , } @llvm.riscv.vluxseg7.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , } [[TMP7]] +// +vbfloat16m1x7_t test_vluxseg7ei16_v_bf16m1x7_mu(vbool16_t vm, + vbfloat16m1x7_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg7ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c new file mode 100644 index 0000000000000000000000000000000000000000..57207ccad17ed5b482031d09c2c6127f2d2d6abd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/bfloat16/vluxseg8ei16.c @@ -0,0 +1,262 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv64 -target-feature +v \ +// RUN: -target-feature +experimental-zvfbfmin \ +// RUN: -target-feature +experimental-zvfbfwma -disable-O0-optnone \ +// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ +// RUN: FileCheck --check-prefix=CHECK-RV64 %s + +#include + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_tu(vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_tu(vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_tu( +// CHECK-RV64-SAME: { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], i64 [[VL]]) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_tu(vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_tu(vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_tum(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg8ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_tum(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg8ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_tum( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 2) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_tum(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_tum(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_tumu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, + size_t vl) { + return __riscv_vluxseg8ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_tumu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, + size_t vl) { + return __riscv_vluxseg8ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_tumu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 0) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_tumu(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_tumu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf4x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv1bf16.nxv1i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf4x8_t test_vluxseg8ei16_v_bf16mf4x8_mu(vbool64_t vm, + vbfloat16mf4x8_t vd, + const __bf16 *rs1, + vuint16mf4_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16mf2x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv2bf16.nxv2i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16mf2x8_t test_vluxseg8ei16_v_bf16mf2x8_mu(vbool32_t vm, + vbfloat16mf2x8_t vd, + const __bf16 *rs1, + vuint16mf2_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_mu(vm, vd, rs1, rs2, vl); +} + +// CHECK-RV64-LABEL: define dso_local { , , , , , , , } @test_vluxseg8ei16_v_bf16m1x8_mu( +// CHECK-RV64-SAME: [[VM:%.*]], { , , , , , , , } [[VD:%.*]], ptr noundef [[RS1:%.*]], [[RS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = extractvalue { , , , , , , , } [[VD]], 0 +// CHECK-RV64-NEXT: [[TMP1:%.*]] = extractvalue { , , , , , , , } [[VD]], 1 +// CHECK-RV64-NEXT: [[TMP2:%.*]] = extractvalue { , , , , , , , } [[VD]], 2 +// CHECK-RV64-NEXT: [[TMP3:%.*]] = extractvalue { , , , , , , , } [[VD]], 3 +// CHECK-RV64-NEXT: [[TMP4:%.*]] = extractvalue { , , , , , , , } [[VD]], 4 +// CHECK-RV64-NEXT: [[TMP5:%.*]] = extractvalue { , , , , , , , } [[VD]], 5 +// CHECK-RV64-NEXT: [[TMP6:%.*]] = extractvalue { , , , , , , , } [[VD]], 6 +// CHECK-RV64-NEXT: [[TMP7:%.*]] = extractvalue { , , , , , , , } [[VD]], 7 +// CHECK-RV64-NEXT: [[TMP8:%.*]] = call { , , , , , , , } @llvm.riscv.vluxseg8.mask.nxv4bf16.nxv4i16.i64( [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]], ptr [[RS1]], [[RS2]], [[VM]], i64 [[VL]], i64 1) +// CHECK-RV64-NEXT: ret { , , , , , , , } [[TMP8]] +// +vbfloat16m1x8_t test_vluxseg8ei16_v_bf16m1x8_mu(vbool16_t vm, + vbfloat16m1x8_t vd, + const __bf16 *rs1, + vuint16m1_t rs2, size_t vl) { + return __riscv_vluxseg8ei16_mu(vm, vd, rs1, rs2, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c index 34fd46465c34a84ad0a55536b85be1258766f27e..646854e671d794cb61e31179dfb5e6e17691519c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdf.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdf_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdf_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdf_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdf.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdf_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdf_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c index 2d0f8e7cafc7e88b6e2de982220df8469b7fcaec..90668f3f191bdcec897ce7dd24d86cddf9ac60d4 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesdm.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesdm_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesdm_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesdm_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesdm.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesdm_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesdm_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c index 26518b9a709fec5e7766c782de543b3d65379e57..8bb3e69233ad3ddd506ef1bdbeaa36b4f9921915 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesef.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesef_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesef_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesef_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesef.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesef_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesef_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c index 67e13665eea8439cc2a4f0abf32cd14e12a67b3b..5a83675aa0e6dc5e05a5ee28bc5d1a2a3d051341 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesem.c @@ -206,13 +206,3 @@ vuint32m8_t test_vaesem_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) return __riscv_vaesem_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesem_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesem.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesem_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesem_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c index 71698175d7b6b7a747a7a8191a73bf6060817e57..afc7827a18a15ae1a2f0e142cff415f3fb465c52 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vaesz.c @@ -156,13 +156,3 @@ vuint32m8_t test_vaesz_vs_u32m4_u32m8_tu(vuint32m8_t vd, vuint32m4_t vs2, size_t return __riscv_vaesz_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vaesz_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vaesz.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vaesz_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vaesz_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c index 0df390bd0724a0eb3fcda654c098427940f21e73..7b70c4e2a790ffb64822a1393bd206205a368b39 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vsm4r.c @@ -206,13 +206,3 @@ vuint32m8_t test_vsm4r_vv_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { return __riscv_vsm4r_vv_tu(vd, vs2, vl); } -// CHECK-RV64-LABEL: define dso_local @test_vsm4r_vs_u32m8_u32m8_tu -// CHECK-RV64-SAME: ( [[VD:%.*]], [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call @llvm.riscv.vsm4r.vs.nxv16i32.nxv16i32.i64( [[VD]], [[VS2]], i64 [[VL]], i64 2) -// CHECK-RV64-NEXT: ret [[TMP0]] -// -vuint32m8_t test_vsm4r_vs_u32m8_u32m8_tu(vuint32m8_t vd, vuint32m8_t vs2, size_t vl) { - return __riscv_vsm4r_vs_tu(vd, vs2, vl); -} - diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c index 48d775b88878648d9f93ade6779a0eaf58b2da64..33f3dce73baea43bbf453257373b8551e3e7b6ee 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector.c @@ -2489,78 +2489,78 @@ void test_integer(void) { // CHECK-ASM: vno vuc = vec_cntlz(vsc); - // CHECK: call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %{{.*}}, i1 false) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %{{.*}}, i1 false) // CHECK-ASM: vclzb vuc = vec_cntlz(vuc); - // CHECK: call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %{{.*}}, i1 false) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %{{.*}}, i1 false) // CHECK-ASM: vclzb vus = vec_cntlz(vss); - // CHECK: call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %{{.*}}, i1 false) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %{{.*}}, i1 false) // CHECK-ASM: vclzh vus = vec_cntlz(vus); - // CHECK: call <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %{{.*}}, i1 false) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.ctlz.v8i16(<8 x i16> %{{.*}}, i1 false) // CHECK-ASM: vclzh vui = vec_cntlz(vsi); - // CHECK: call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %{{.*}}, i1 false) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %{{.*}}, i1 false) // CHECK-ASM: vclzf vui = vec_cntlz(vui); - // CHECK: call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %{{.*}}, i1 false) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.ctlz.v4i32(<4 x i32> %{{.*}}, i1 false) // CHECK-ASM: vclzf vul = vec_cntlz(vsl); - // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false) // CHECK-ASM: vclzg vul = vec_cntlz(vul); - // CHECK: call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.ctlz.v2i64(<2 x i64> %{{.*}}, i1 false) // CHECK-ASM: vclzg vuc = vec_cnttz(vsc); - // CHECK: call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %{{.*}}, i1 false) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.cttz.v16i8(<16 x i8> %{{.*}}, i1 false) // CHECK-ASM: vctzb vuc = vec_cnttz(vuc); - // CHECK: call <16 x i8> @llvm.cttz.v16i8(<16 x i8> %{{.*}}, i1 false) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.cttz.v16i8(<16 x i8> %{{.*}}, i1 false) // CHECK-ASM: vctzb vus = vec_cnttz(vss); - // CHECK: call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %{{.*}}, i1 false) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.cttz.v8i16(<8 x i16> %{{.*}}, i1 false) // CHECK-ASM: vctzh vus = vec_cnttz(vus); - // CHECK: call <8 x i16> @llvm.cttz.v8i16(<8 x i16> %{{.*}}, i1 false) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.cttz.v8i16(<8 x i16> %{{.*}}, i1 false) // CHECK-ASM: vctzh vui = vec_cnttz(vsi); - // CHECK: call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %{{.*}}, i1 false) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.cttz.v4i32(<4 x i32> %{{.*}}, i1 false) // CHECK-ASM: vctzf vui = vec_cnttz(vui); - // CHECK: call <4 x i32> @llvm.cttz.v4i32(<4 x i32> %{{.*}}, i1 false) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.cttz.v4i32(<4 x i32> %{{.*}}, i1 false) // CHECK-ASM: vctzf vul = vec_cnttz(vsl); - // CHECK: call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %{{.*}}, i1 false) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> %{{.*}}, i1 false) // CHECK-ASM: vctzg vul = vec_cnttz(vul); - // CHECK: call <2 x i64> @llvm.cttz.v2i64(<2 x i64> %{{.*}}, i1 false) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> %{{.*}}, i1 false) // CHECK-ASM: vctzg vuc = vec_popcnt(vsc); - // CHECK: call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) // CHECK-ASM: vpopct vuc = vec_popcnt(vuc); - // CHECK: call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) // CHECK-ASM: vpopct vus = vec_popcnt(vss); - // CHECK: call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) // (emulated) vus = vec_popcnt(vus); - // CHECK: call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) // (emulated) vui = vec_popcnt(vsi); - // CHECK: call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) // (emulated) vui = vec_popcnt(vui); - // CHECK: call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) // (emulated) vul = vec_popcnt(vsl); - // CHECK: call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) // (emulated) vul = vec_popcnt(vul); - // CHECK: call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) // (emulated) vsc = vec_rl(vsc, vuc); diff --git a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c index 6c26b51c542e5db8a011d0fff5c2ca73008ac99b..15e72ecf51dac1e1cb61b391b29ffc4a7281cb73 100644 --- a/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c +++ b/clang/test/CodeGen/SystemZ/builtins-systemz-zvector2.c @@ -577,28 +577,28 @@ void test_integer(void) { // CHECK-ASM: vnx vuc = vec_popcnt(vsc); - // CHECK: call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) // CHECK-ASM: vpopctb vuc = vec_popcnt(vuc); - // CHECK: call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) + // CHECK: call range(i8 0, 9) <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %{{.*}}) // CHECK-ASM: vpopctb vus = vec_popcnt(vss); - // CHECK: call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) // CHECK-ASM: vpopcth vus = vec_popcnt(vus); - // CHECK: call <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) + // CHECK: call range(i16 0, 17) <8 x i16> @llvm.ctpop.v8i16(<8 x i16> %{{.*}}) // CHECK-ASM: vpopcth vui = vec_popcnt(vsi); - // CHECK: call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) // CHECK-ASM: vpopctf vui = vec_popcnt(vui); - // CHECK: call <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) + // CHECK: call range(i32 0, 33) <4 x i32> @llvm.ctpop.v4i32(<4 x i32> %{{.*}}) // CHECK-ASM: vpopctf vul = vec_popcnt(vsl); - // CHECK: call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) // CHECK-ASM: vpopctg vul = vec_popcnt(vul); - // CHECK: call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) + // CHECK: call range(i64 0, 65) <2 x i64> @llvm.ctpop.v2i64(<2 x i64> %{{.*}}) // CHECK-ASM: vpopctg vf = vec_slb(vf, vsi); diff --git a/clang/test/CodeGen/builtins-wasm.c b/clang/test/CodeGen/builtins-wasm.c index d486d12085f9fcece37da182858849cb3fb366a8..9a323da9a8e8465704f06afd6ddc29f50d2a691c 100644 --- a/clang/test/CodeGen/builtins-wasm.c +++ b/clang/test/CodeGen/builtins-wasm.c @@ -406,7 +406,7 @@ i32x4 bitselect(i32x4 x, i32x4 y, i32x4 c) { i8x16 popcnt(i8x16 x) { return __builtin_wasm_popcnt_i8x16(x); - // WEBASSEMBLY: call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x) + // WEBASSEMBLY: call range(i8 0, 9) <16 x i8> @llvm.ctpop.v16i8(<16 x i8> %x) // WEBASSEMBLY-NEXT: ret } diff --git a/clang/test/CodeGen/ms-intrinsics-other.c b/clang/test/CodeGen/ms-intrinsics-other.c index 0e9dfe34b84cc7d89b1853f54a5d84c61f9dc3e6..fa8422e5bf19fb1f2ec653b564e3ca3cf9338c53 100644 --- a/clang/test/CodeGen/ms-intrinsics-other.c +++ b/clang/test/CodeGen/ms-intrinsics-other.c @@ -56,7 +56,7 @@ unsigned char test_BitScanForward(unsigned LONG *Index, unsigned LONG Mask) { // CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: -// CHECK: [[INDEX:%[0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %Mask, i1 true) +// CHECK: [[INDEX:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %Mask, i1 true) // CHECK: store i32 [[INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] @@ -70,7 +70,7 @@ unsigned char test_BitScanReverse(unsigned LONG *Index, unsigned LONG Mask) { // CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: -// CHECK: [[REVINDEX:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %Mask, i1 true) +// CHECK: [[REVINDEX:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %Mask, i1 true) // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[REVINDEX]], 31 // CHECK: store i32 [[INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] @@ -86,7 +86,7 @@ unsigned char test_BitScanForward64(unsigned LONG *Index, unsigned __int64 Mask) // CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: -// CHECK: [[INDEX:%[0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %Mask, i1 true) +// CHECK: [[INDEX:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 %Mask, i1 true) // CHECK: [[TRUNC_INDEX:%[0-9]+]] = trunc nuw nsw i64 [[INDEX]] to i32 // CHECK: store i32 [[TRUNC_INDEX]], ptr %Index, align 4 // CHECK: br label %[[END_LABEL]] @@ -101,7 +101,7 @@ unsigned char test_BitScanReverse64(unsigned LONG *Index, unsigned __int64 Mask) // CHECK: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: -// CHECK: [[REVINDEX:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %Mask, i1 true) +// CHECK: [[REVINDEX:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %Mask, i1 true) // CHECK: [[TRUNC_REVINDEX:%[0-9]+]] = trunc nuw nsw i64 [[REVINDEX]] to i32 // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63 // CHECK: store i32 [[INDEX]], ptr %Index, align 4 @@ -187,7 +187,7 @@ unsigned short test__lzcnt16(unsigned short x) { return __lzcnt16(x); } // CHECK: i16 @test__lzcnt16 -// CHECK: [[RESULT:%[0-9]+]] = tail call i16 @llvm.ctlz.i16(i16 %x, i1 false) +// CHECK: [[RESULT:%[0-9]+]] = tail call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 %x, i1 false) // CHECK: ret i16 [[RESULT]] // CHECK: } @@ -195,7 +195,7 @@ unsigned int test__lzcnt(unsigned int x) { return __lzcnt(x); } // CHECK: i32 @test__lzcnt -// CHECK: [[RESULT:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %x, i1 false) +// CHECK: [[RESULT:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %x, i1 false) // CHECK: ret i32 [[RESULT]] // CHECK: } @@ -203,7 +203,7 @@ unsigned __int64 test__lzcnt64(unsigned __int64 x) { return __lzcnt64(x); } // CHECK: i64 @test__lzcnt64 -// CHECK: [[RESULT:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %x, i1 false) +// CHECK: [[RESULT:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %x, i1 false) // CHECK: ret i64 [[RESULT]] // CHECK: } @@ -211,7 +211,7 @@ unsigned short test__popcnt16(unsigned short x) { return __popcnt16(x); } // CHECK: i16 @test__popcnt16 -// CHECK: [[RESULT:%[0-9]+]] = tail call i16 @llvm.ctpop.i16(i16 %x) +// CHECK: [[RESULT:%[0-9]+]] = tail call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 %x) // CHECK: ret i16 [[RESULT]] // CHECK: } @@ -219,7 +219,7 @@ unsigned int test__popcnt(unsigned int x) { return __popcnt(x); } // CHECK: i32 @test__popcnt -// CHECK: [[RESULT:%[0-9]+]] = tail call i32 @llvm.ctpop.i32(i32 %x) +// CHECK: [[RESULT:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 %x) // CHECK: ret i32 [[RESULT]] // CHECK: } @@ -227,7 +227,7 @@ unsigned __int64 test__popcnt64(unsigned __int64 x) { return __popcnt64(x); } // CHECK: i64 @test__popcnt64 -// CHECK: [[RESULT:%[0-9]+]] = tail call i64 @llvm.ctpop.i64(i64 %x) +// CHECK: [[RESULT:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 %x) // CHECK: ret i64 [[RESULT]] // CHECK: } diff --git a/clang/test/CodeGen/ms-intrinsics.c b/clang/test/CodeGen/ms-intrinsics.c index 6eabd725e2f7c6b06d6959c86a1d0bafb05e48f7..c3d64fda0b901fd4afc7e334152fdb456421c1a5 100644 --- a/clang/test/CodeGen/ms-intrinsics.c +++ b/clang/test/CodeGen/ms-intrinsics.c @@ -157,7 +157,7 @@ unsigned char test_BitScanForward(unsigned long *Index, unsigned long Mask) { // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[IDXGEP:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr %Index, {{i64|i32}} 4 -// CHECK: [[INDEX:%[0-9]+]] = tail call i32 @llvm.cttz.i32(i32 %Mask, i1 true) +// CHECK: [[INDEX:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %Mask, i1 true) // CHECK: store i32 [[INDEX]], ptr [[IDXGEP]], align 4 // CHECK: br label %[[END_LABEL]] @@ -172,7 +172,7 @@ unsigned char test_BitScanReverse(unsigned long *Index, unsigned long Mask) { // CHECK: ret i8 [[RESULT]] // CHECK: [[ISNOTZERO_LABEL]]: // CHECK: [[IDXGEP:%[a-z0-9._]+]] = getelementptr inbounds i8, ptr %Index, {{i64|i32}} 4 -// CHECK: [[REVINDEX:%[0-9]+]] = tail call i32 @llvm.ctlz.i32(i32 %Mask, i1 true) +// CHECK: [[REVINDEX:%[0-9]+]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %Mask, i1 true) // CHECK: [[INDEX:%[0-9]+]] = xor i32 [[REVINDEX]], 31 // CHECK: store i32 [[INDEX]], ptr [[IDXGEP]], align 4 // CHECK: br label %[[END_LABEL]] @@ -188,7 +188,7 @@ unsigned char test_BitScanForward64(unsigned long *Index, unsigned __int64 Mask) // CHECK-ARM-X64: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK-ARM-X64: ret i8 [[RESULT]] // CHECK-ARM-X64: [[ISNOTZERO_LABEL]]: -// CHECK-ARM-X64: [[INDEX:%[0-9]+]] = tail call i64 @llvm.cttz.i64(i64 %Mask, i1 true) +// CHECK-ARM-X64: [[INDEX:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 %Mask, i1 true) // CHECK-ARM-X64: [[TRUNC_INDEX:%[0-9]+]] = trunc nuw nsw i64 [[INDEX]] to i32 // CHECK-ARM-X64: store i32 [[TRUNC_INDEX]], ptr %Index, align 4 // CHECK-ARM-X64: br label %[[END_LABEL]] @@ -203,7 +203,7 @@ unsigned char test_BitScanReverse64(unsigned long *Index, unsigned __int64 Mask) // CHECK-ARM-X64: [[RESULT:%[a-z0-9._]+]] = phi i8 [ 0, %[[ISZERO_LABEL:[a-z0-9._]+]] ], [ 1, %[[ISNOTZERO_LABEL]] ] // CHECK-ARM-X64: ret i8 [[RESULT]] // CHECK-ARM-X64: [[ISNOTZERO_LABEL]]: -// CHECK-ARM-X64: [[REVINDEX:%[0-9]+]] = tail call i64 @llvm.ctlz.i64(i64 %Mask, i1 true) +// CHECK-ARM-X64: [[REVINDEX:%[0-9]+]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %Mask, i1 true) // CHECK-ARM-X64: [[TRUNC_REVINDEX:%[0-9]+]] = trunc nuw nsw i64 [[REVINDEX]] to i32 // CHECK-ARM-X64: [[INDEX:%[0-9]+]] = xor i32 [[TRUNC_REVINDEX]], 63 // CHECK-ARM-X64: store i32 [[INDEX]], ptr %Index, align 4 diff --git a/clang/test/CodeGenOpenCL/builtins-generic-amdgcn.cl b/clang/test/CodeGenOpenCL/builtins-generic-amdgcn.cl index b093fcbf7d9894d3b38478b8254589e10ee4b572..37bea1ff93303941991b0bc4edd0af70e2f28bf2 100644 --- a/clang/test/CodeGenOpenCL/builtins-generic-amdgcn.cl +++ b/clang/test/CodeGenOpenCL/builtins-generic-amdgcn.cl @@ -4,14 +4,14 @@ #pragma OPENCL EXTENSION cl_khr_fp16 : enable // CHECK-LABEL: @test_builtin_clz( -// CHECK: tail call i32 @llvm.ctlz.i32(i32 %a, i1 true) +// CHECK: tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 %a, i1 true) void test_builtin_clz(global int* out, int a) { *out = __builtin_clz(a); } // CHECK-LABEL: @test_builtin_clzl( -// CHECK: tail call i64 @llvm.ctlz.i64(i64 %a, i1 true) +// CHECK: tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 %a, i1 true) void test_builtin_clzl(global long* out, long a) { *out = __builtin_clzl(a); diff --git a/clang/test/Driver/amdgpu-toolchain.c b/clang/test/Driver/amdgpu-toolchain.c index 4300e7e9f66705b84b5c69fef21ccc34899b81db..faaff05004f6deb6249103f809e4207eddfc2e32 100644 --- a/clang/test/Driver/amdgpu-toolchain.c +++ b/clang/test/Driver/amdgpu-toolchain.c @@ -24,3 +24,7 @@ // RUN: -L. -fconvergent-functions %s 2>&1 | FileCheck -check-prefix=MCPU %s // LTO: clang{{.*}} "-flto=full"{{.*}}"-fconvergent-functions" // MCPU: ld.lld{{.*}}"-L."{{.*}}"-plugin-opt=mcpu=gfx906" + +// RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx906 -nogpulib \ +// RUN: -fuse-ld=ld %s 2>&1 | FileCheck -check-prefixes=LD %s +// LD: ld.lld" diff --git a/clang/test/Driver/fast-math.c b/clang/test/Driver/fast-math.c index 882e81fd14d34a7f352f35aae5abeed153611994..b07d5732932cdb61b1daa350426351d9aad32f68 100644 --- a/clang/test/Driver/fast-math.c +++ b/clang/test/Driver/fast-math.c @@ -7,324 +7,309 @@ // Both of them use gcc driver for as. // // RUN: %clang -### -fno-honor-infinities -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-INFS %s +// RUN: | FileCheck --check-prefixes=CHECK,NINF,NO-NNAN,NO-FINITE-ONLY %s // infinites [sic] is a supported alternative spelling of infinities. // RUN: %clang -### -fno-honor-infinites -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-INFS %s -// CHECK-NO-INFS: "-cc1" -// CHECK-NO-INFS: "-menable-no-infs" +// RUN: | FileCheck --check-prefixes=CHECK,NINF,NO-NNAN,NO-FINITE-ONLY %s // // RUN: %clang -### -fno-fast-math -fno-honor-infinities -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH-NO-INFS %s -// CHECK-NO-FAST-MATH-NO-INFS: "-cc1" -// CHECK-NO-FAST-MATH-NO-INFS: "-menable-no-infs" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NINF,NO-NNAN,NO-FINITE-ONLY %s // // RUN: %clang -### -fno-honor-infinities -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-INFS-NO-FAST-MATH %s -// CHECK-NO-INFS-NO-FAST-MATH: "-cc1" -// CHECK-NO-INFS-NO-FAST-MATH-NOT: "-menable-no-infs" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NINF,NO-NNAN,NO-FINITE-ONLY %s // // RUN: %clang -### -fno-signed-zeros -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-SIGNED-ZEROS %s -// CHECK-NO-SIGNED-ZEROS: "-cc1" -// CHECK-NO-SIGNED-ZEROS: "-fno-signed-zeros" +// RUN: | FileCheck --check-prefixes=CHECK,NSZ,NOROUNDING %s // // RUN: %clang -### -fno-fast-math -fno-signed-zeros -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH-NO-SIGNED-ZEROS %s -// CHECK-NO-FAST-MATH-NO-SIGNED-ZEROS: "-cc1" -// CHECK-NO-FAST-MATH-NO-SIGNED-ZEROS: "-fno-signed-zeros" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NSZ %s // // RUN: %clang -### -fno-signed-zeros -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-SIGNED-ZEROS-NO-FAST-MATH %s -// CHECK-NO-SIGNED-ZEROS-NO-FAST-MATH: "-cc1" -// CHECK-NO-SIGNED-ZEROS-NO-FAST-MATH-NOT: "-fno-signed-zeros" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NSZ,NOROUNDING %s // // RUN: %clang -### -freciprocal-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-RECIPROCAL-MATH %s -// CHECK-RECIPROCAL-MATH: "-cc1" -// CHECK-RECIPROCAL-MATH: "-freciprocal-math" +// RUN: | FileCheck --check-prefixes=CHECK,ARCP,NOROUNDING %s // // RUN: %clang -### -fno-fast-math -freciprocal-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH-RECIPROCAL-MATH %s -// CHECK-NO-FAST-MATH-RECIPROCAL-MATH: "-cc1" -// CHECK-NO-FAST-MATH-RECIPROCAL-MATH: "-freciprocal-math" +// RUN: | FileCheck --check-prefixes=CHECK,ARCP,NOROUNDING %s // // RUN: %clang -### -freciprocal-math -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-RECIPROCAL-MATH-NO-FAST-MATH %s -// CHECK-RECIPROCAL-MATH-NO-FAST-MATH: "-cc1" -// CHECK-RECIPROCAL-MATH-NO-FAST-MATH-NOT: "-freciprocal-math" +// RUN: | FileCheck --check-prefixes=CHECK,NO-ARCP,NOROUNDING %s // // RUN: %clang -### -fno-honor-nans -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NANS %s -// CHECK-NO-NANS: "-cc1" -// CHECK-NO-NANS: "-menable-no-nans" +// RUN: | FileCheck --check-prefixes=CHECK,NNAN,NO-NINF,NO-FINITE-ONLY,NOROUNDING %s // // RUN: %clang -### -fno-fast-math -fno-honor-nans -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH-NO-NANS %s -// CHECK-NO-FAST-MATH-NO-NANS: "-cc1" -// CHECK-NO-FAST-MATH-NO-NANS: "-menable-no-nans" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NNAN,NO-NINF,NO-FINITE-ONLY,NOROUNDING %s // // RUN: %clang -### -fno-honor-nans -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NANS-NO-FAST-MATH %s -// CHECK-NO-NANS-NO-FAST-MATH: "-cc1" -// CHECK-NO-NANS-NO-FAST-MATH-NOT: "-menable-no-nans" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NNAN,NO-NINF,NO-FINITE-ONLY,NOROUNDING %s // // RUN: %clang -### -ffast-math -fno-approx-func -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-FAST-MATH-NO-APPROX-FUNC %s -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-cc1" -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-menable-no-infs" -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-menable-no-nans" -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-fno-signed-zeros" -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-mreassociate" -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-freciprocal-math" -// CHECK-FAST-MATH-NO-APPROX-FUNC: "-ffp-contract=fast" -// CHECK-FAST-MATH-NO-APPROX-FUNC-NOT: "-ffast-math" -// CHECK-FAST-MATH-NO-APPROX-FUNC-NOT: "-fapprox-func" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NINF,NNAN,FINITE-ONLY,NSZ,ARCP,NO-AFN,NO-ERRNO,NOROUNDING %s // // RUN: %clang -### -fno-approx-func -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-APPROX-FUNC-FAST-MATH %s -// CHECK-NO-APPROX-FUNC-FAST-MATH: "-cc1" -// CHECK-NO-APPROX-FUNC-FAST-MATH: "-ffast-math" +// RUN: | FileCheck --check-prefixes=CHECK,FAST,NINF,NNAN,FINITE-ONLY,NSZ,ARCP,AFN,NO-ERRNO,NOROUNDING %s // // RUN: %clang -### -fapprox-func -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-APPROX-FUNC %s -// CHECK-APPROX-FUNC: "-cc1" -// CHECK-APPROX-FUNC: "-fapprox-func" +// RUN: | FileCheck --check-prefixes=CHECK,AFN %s // // RUN: %clang -### -fno-fast-math -fapprox-func -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH-APPROX-FUNC %s -// CHECK-NO-FAST-MATH-APPROX-FUNC: "-cc1" -// CHECK-NO-FAST-MATH-APPROX-FUNC: "-fapprox-func" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,AFN,NOROUNDING %s // // RUN: %clang -### -fapprox-func -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-APPROX-FUNC-NO-FAST-MATH %s -// CHECK-APPROX-FUNC-NO-FAST-MATH: "-cc1" -// CHECK-APPROX-FUNC-NO-FAST-MATH-NOT: "-fapprox-func" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-AFN %s // // RUN: %clang -### -fmath-errno -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-MATH-ERRNO %s -// CHECK-MATH-ERRNO: "-cc1" -// CHECK-MATH-ERRNO: "-fmath-errno" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,ERRNO %s // // RUN: %clang -### -fmath-errno -fno-math-errno -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s -// CHECK-NO-MATH-ERRNO: "-cc1" -// CHECK-NO-MATH-ERRNO-NOT: "-fmath-errno" +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // // Target defaults for -fmath-errno (reusing the above checks). // RUN: %clang -### -target i686-unknown-linux -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,ERRNO %s // RUN: %clang -### -target i686-apple-darwin -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-unknown-freebsd -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-unknown-netbsd -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-unknown-openbsd -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### --target=x86_64-unknown-haiku -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-unknown-dragonfly -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-fuchsia -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-linux-android -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target x86_64-linux-musl -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### --target=amdgcn-amd-amdhsa -nogpuinc -nogpulib -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target amdgcn-amd-amdpal -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target amdgcn-mesa-mesa3d -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // // Check that -ffast-math disables -fmath-errno, and -fno-fast-math merely // preserves the target default. Also check various flag set operations between // the two flags. (Resuses above checks.) // RUN: %clang -### -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -fmath-errno -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -ffast-math -fmath-errno -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,ERRNO %s // RUN: %clang -### -target i686-unknown-linux -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,ERRNO %s // RUN: %clang -### -target i686-unknown-linux -fno-math-errno -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,ERRNO %s // RUN: %clang -### -target i686-apple-darwin -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -target i686-apple-darwin -fno-math-errno -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // RUN: %clang -### -fno-fast-math -fno-math-errno -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-MATH-ERRNO %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO %s // // RUN: %clang -### -fno-math-errno -fassociative-math -freciprocal-math \ // RUN: -fno-signed-zeros -fno-trapping-math -fapprox-func -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-UNSAFE-MATH %s -// CHECK-UNSAFE-MATH: "-cc1" -// CHECK-UNSAFE-MATH: "-funsafe-math-optimizations" -// CHECK-UNSAFE-MATH: "-mreassociate" +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO,UNSAFE,ARCP,NSZ,NO-TRAPPING,REASSOC %s // // RUN: %clang -### -fno-fast-math -fno-math-errno -fassociative-math -freciprocal-math \ // RUN: -fno-signed-zeros -fno-trapping-math -fapprox-func -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH-UNSAFE-MATH %s -// CHECK-NO-FAST-MATH-UNSAFE-MATH: "-cc1" -// CHECK-NO-FAST-MATH-UNSAFE-MATH: "-funsafe-math-optimizations" -// CHECK-NO-FAST-MATH-UNSAFE-MATH: "-mreassociate" +// RUN: | FileCheck --check-prefixes=CHECK,NO-ERRNO,UNSAFE,ARCP,NSZ,NO-TRAPPING,REASSOC %s // The 2nd -fno-fast-math overrides -fassociative-math. // RUN: %clang -### -fno-fast-math -fno-math-errno -fassociative-math -freciprocal-math \ // RUN: -fno-fast-math -fno-signed-zeros -fno-trapping-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-UNSAFE-MATH-NO-FAST-MATH %s -// CHECK-UNSAFE-MATH-NO-FAST-MATH: "-cc1" -// CHECK-UNSAFE-MATH-NO-FAST-MATH-NOT: "-funsafe-math-optimizations" -// CHECK-UNSAFE-MATH-NO-FAST-MATH-NOT: "-mreassociate" +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,NO-REASSOC,NO-ARCP,NSZ,NO-TRAPPING %s // // Check that various umbrella flags also enable these frontend options. // RUN: %clang -### -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-INFS %s -// RUN: %clang -### -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NANS %s -// RUN: %clang -### -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,FAST,NINF,NNAN,FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // RUN: %clang -### -ffinite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-INFS %s -// RUN: %clang -### -ffinite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NANS %s +// RUN: | FileCheck --check-prefixes=CHECK,NINF,NNAN,FINITE-ONLY %s // RUN: %clang -### -funsafe-math-optimizations -fno-math-errno -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NNAN,NO-NINF,NO-FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // // One umbrella flag is *really* weird and also changes the semantics of the // program by adding a special preprocessor macro. Check that the frontend flag // modeling this semantic change is provided. Also check that the flag is not // present if any of the optimizations are disabled. -// RUN: %clang -### -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-FAST-MATH %s // RUN: %clang -### -fno-fast-math -ffast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-FAST-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,FAST,NINF,NNAN,FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // RUN: %clang -### -funsafe-math-optimizations -ffinite-math-only \ // RUN: -fno-math-errno -ffp-contract=fast -fno-rounding-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-FAST-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,FAST,NINF,NNAN,FINITE-ONLY,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // RUN: %clang -### -fno-honor-infinities -fno-honor-nans -fno-math-errno \ // RUN: -fassociative-math -freciprocal-math -fno-signed-zeros -fapprox-func \ // RUN: -fno-trapping-math -ffp-contract=fast -fno-rounding-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-FAST-MATH %s -// CHECK-FAST-MATH: "-cc1" -// CHECK-FAST-MATH: "-ffast-math" -// CHECK-FAST-MATH: "-ffinite-math-only" +// RUN: | FileCheck --check-prefixes=CHECK,FAST,NINF,NNAN,FINITE-ONLY,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // // RUN: %clang -### -ffast-math -fno-fast-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NINF,NO-NNAN,NO-FINITE-ONLY,NO-REASSOC,NO-NSZ,NO-ARCP,NO-AFN,NOROUNDING %s // RUN: %clang -### -ffast-math -fno-finite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NINF,NO-NNAN,NO-FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NOROUNDING %s + +// FIXME: This case leaves nnan and ninf. That seems wrong! // RUN: %clang -### -ffast-math -fno-unsafe-math-optimizations -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NINF,NNAN,FINITE-ONLY,NO-REASSOC,NO-NSZ,NO-ARCP,NO-AFN,NOROUNDING %s // RUN: %clang -### -ffast-math -fmath-errno -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NINF,NNAN,FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,ERRNO,NOROUNDING %s // RUN: %clang -### -ffast-math -fno-associative-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-FAST-MATH --check-prefix=CHECK-ASSOC-MATH %s -// CHECK-NO-FAST-MATH: "-cc1" -// CHECK-NO-FAST-MATH-NOT: "-ffast-math" -// CHECK-ASSOC-MATH-NOT: "-mreassociate" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NINF,NNAN,FINITE-ONLY,NO-REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // // Check various means of disabling these flags, including disabling them after // they've been enabled via an umbrella flag. // RUN: %clang -### -fno-honor-infinities -fhonor-infinities -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-INFS %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-NINF,NO-NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffinite-math-only -fhonor-infinities -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-INFS %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-NINF,NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffinite-math-only -fno-finite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-INFS %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-NINF,NO-NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffast-math -fhonor-infinities -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-INFS %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NINF,NNAN,NO-FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // RUN: %clang -### -ffast-math -fno-finite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-INFS %s -// CHECK-NO-NO-INFS: "-cc1" -// CHECK-NO-NO-INFS-NOT: "-menable-no-infs" -// CHECK-NO-NO-INFS-NOT: "-ffinite-math-only" -// CHECK-NO-NO-INFS: "-o" +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-NINF,NO-NNAN,NO-FINITE-ONLY,REASSOC,NSZ,ARCP,AFN,CONTRACT-FAST,NO-ERRNO,NOROUNDING %s // // RUN: %clang -### -fno-honor-nans -fhonor-nans -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-NANS %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-NINF,NO-NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffinite-math-only -fhonor-nans -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-NANS %s +// RUN: | FileCheck --check-prefixes=CHECK,NINF,NO-NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffinite-math-only -fno-finite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-NANS %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-NINF,NO-NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffast-math -fhonor-nans -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-NANS %s +// RUN: | FileCheck --check-prefixes=CHECK,NINF,NO-NNAN,NO-FINITE-ONLY %s // RUN: %clang -### -ffast-math -fno-finite-math-only -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-NO-NANS %s -// CHECK-NO-NO-NANS: "-cc1" -// CHECK-NO-NO-NANS-NOT: "-menable-no-nans" -// CHECK-NO-NO-NANS-NOT: "-ffinite-math-only" -// CHECK-NO-NO-NANS: "-o" +// RUN: | FileCheck --check-prefixes=CHECK,NO-NINF,NO-NNAN,NO-FINITE-ONLY %s // A later inverted option overrides an earlier option. // RUN: %clang -### -fassociative-math -freciprocal-math -fno-signed-zeros \ // RUN: -fno-trapping-math -fno-associative-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-REASSOC,ARCP,NSZ,NO-TRAPPING %s + +// RUN: %clang -### -funsafe-math-optimizations -fno-associative-math -c %s 2>&1 \ +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,NO-REASSOC,ARCP,NSZ,AFN %s -// RUN: %clang -### -funsafe-math-optimizations -fno-associative-math -c %s \ -// RUN: 2>&1 | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: %clang -### -funsafe-math-optimizations -fno-reciprocal-math -c %s 2>&1 \ +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,REASSOC,NO-ARCP,NSZ,AFN %s -// RUN: %clang -### -funsafe-math-optimizations -fno-reciprocal-math -c %s \ -// RUN: 2>&1 | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// reassoc requires nsz // RUN: %clang -### -funsafe-math-optimizations -fsigned-zeros -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,NO-REASSOC,ARCP,NO-NSZ,AFN %s + +// FIXME: Shouldn't trapping math disable all unsafe math? // RUN: %clang -### -funsafe-math-optimizations -ftrapping-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,ARCP,NSZ,AFN,TRAPPING %s + // RUN: %clang -### -funsafe-math-optimizations -fno-unsafe-math-optimizations \ // RUN: -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,NO-REASSOC,NO-ARCP,NO-NSZ,NO-AFN %s // RUN: %clang -### -ffast-math -fno-associative-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-UNSAFE,NO-REASSOC,ARCP,NSZ,AFN %s // RUN: %clang -### -ffast-math -fno-reciprocal-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-UNSAFE,NNAN,NINF,FINITE-ONLY,REASSOC,NO-ARCP,CONTRACT-FAST,NSZ,AFN %s + +// reassoc requires nsz // RUN: %clang -### -ffast-math -fsigned-zeros -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s -// RUN: %clang -### -ffast-math -ftrapping-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s -// RUN: %clang -### -ffast-math -fno-unsafe-math-optimizations -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-UNSAFE,NNAN,NINF,FINITE-ONLY,NO-REASSOC,ARCP,CONTRACT-FAST,NO-NSZ,AFN %s -// CHECK-NO-UNSAFE-MATH: "-cc1" -// CHECK-NO-UNSAFE-MATH-NOT: "-funsafe-math-optimizations" -// CHECK-NO_UNSAFE-MATH-NOT: "-mreassociate" -// CHECK-NO-UNSAFE-MATH: "-o" +// FIXME: Shouldn't trapping math disable unsafe math? +// RUN: %clang -### -ffast-math -ftrapping-math -c %s 2>&1 \ +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-UNSAFE,ARCP,NSZ,AFN,TRAPPING %s +// FIXME: -fno-unsafe-math-optimizations shouldn't imply trapping math +// RUN: %clang -### -ffast-math -fno-unsafe-math-optimizations -c %s 2>&1 \ +// RUN: | FileCheck --check-prefixes=CHECK,NO-FAST,NO-UNSAFE,NO-ARCP,NO-NSZ,NO-AFN,TRAPPING %s // Reassociate is allowed because it does not require reciprocal-math. // RUN: %clang -### -fassociative-math -freciprocal-math -fno-signed-zeros \ // RUN: -fno-trapping-math -fno-reciprocal-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-REASSOC-NO-UNSAFE-MATH %s - -// CHECK-REASSOC-NO-UNSAFE-MATH: "-cc1" -// CHECK-REASSOC-NO_UNSAFE-MATH-NOT: "-funsafe-math-optimizations" -// CHECK-REASSOC-NO_UNSAFE-MATH: "-mreassociate" -// CHECK-REASSOC-NO-UNSAFE-MATH-NOT: "-funsafe-math-optimizations" -// CHECK-REASSOC-NO-UNSAFE-MATH: "-o" +// RUN: | FileCheck --check-prefixes=CHECK,REASSOC,NO-ARCP,NSZ,NO-TRAPPING %s // In these runs, reassociate is not allowed because both no-signed-zeros and no-trapping-math are required. // RUN: %clang -### -fassociative-math -freciprocal-math -fno-signed-zeros \ // RUN: -fno-trapping-math -fsigned-zeros -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-REASSOC-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-REASSOC,ARCP,NO-NSZ,NO-TRAPPING %s // RUN: %clang -### -fassociative-math -freciprocal-math -fno-signed-zeros \ // RUN: -fno-trapping-math -ftrapping-math -c %s 2>&1 \ -// RUN: | FileCheck --check-prefix=CHECK-NO-REASSOC-NO-UNSAFE-MATH %s +// RUN: | FileCheck --check-prefixes=CHECK,NO-REASSOC,ARCP,NSZ,TRAPPING %s + +// The checks below allow stringing together prefixes to select the expected +// set of cc1 options for any combination of floating-point options. +// This is based on the assumption that the order of the flags when rendered +// is stable, so the negative checks only need to appear where the option would +// appear if used. + +// start marker +// CHECK: "-cc1" + +// NO-NINF-NOT: "-menable-no-infs" +// NINF-SAME: "-menable-no-infs" + +// NO-NNAN-NOT: "-menable-no-nans" +// NNAN-SAME: "-menable-no-nans" + +// NO-AFN-NOT: "-fapprox-func" +// AFN-SAME: "-fapprox-func" + +// NO-ERRNO-NOT: "-fmath-errno" +// ERRNO-SAME: "-fmath-errno" + +// NO-UNSAFE-NOT: "-funsafe-math-optimizations" +// UNSAFE-SAME: "-funsafe-math-optimizations" + +// NO-NSZ-NOT: "-fno-signed-zeros" +// NSZ-SAME: "-fno-signed-zeros" + +// NO-REASSOC-NOT: "-mreassociate" +// REASSOC-SAME: "-mreassociate" + +// NO-ARCP-NOT: "-freciprocal-math" +// ARCP-SAME: "-freciprocal-math" + +// NO-DENORM-NOT: "-fdenormal-fp-math" +// DENORM-IEEE-SAME: "-fdenormal-fp-math=ieee,ieee" +// DENORM-PS-SAME: "-fdenormal-fp-math=preserve-sign,preserve-sign" +// DENORM-PZ-SAME: "-fdenormal-fp-math=positive-zero,positive-zero" + +// NO-CONTRACT-NOT: "-ffp-contract" +// CONTRACT-OFF-SAME: "-ffp-contract=off" +// CONTRACT-ON-SAME: "-ffp-contract=on" +// CONTRACT-FAST-SAME: "-ffp-contract=fast" + +// This one is odd because -frounding-math is the default +// NO-NOROUNDING-NOT: "-fno-rounding-math" +// NOROUNDING-SAME: "-fno-rounding-math" + +// NO-TRAPPING-NOT: "-ffp-exception-behavior=strict" +// NO-TRAPPING-NOT: "-ffp-exception-behavior=maytrap" +// TRAPPING-SAME: "-ffp-exception-behavior=strict" + +// NO-FAST-NOT: "-ffast-math" +// FAST-SAME: "-ffast-math" + +// NO-FINITE-ONLY-NOT: "-ffinite-math-only" +// FINITE-ONLY-SAME: "-ffinite-math-only" + +// NO-CX-RANGE-NOT: "-complex-range" +// CX-RANGE-FULL-SAME: "-complex-range=full" +// CX-RANGE-PROMO-SAME: "-complex-range=promoted" +// CX-RANGE-IMPRO-SAME: "-complex-range=improved" +// CX-RANGE-BASIC-SAME: "-complex-range=basic" -// CHECK-NO-REASSOC-NO-UNSAFE-MATH: "-cc1" -// CHECK-NO-REASSOC-NO_UNSAFE-MATH-NOT: "-funsafe-math-optimizations" -// CHECK-NO-REASSOC-NO_UNSAFE-MATH-NOT: "-mreassociate" -// CHECK-NO-REASSOC-NO_UNSAFE-MATH-NOT: "-funsafe-math-optimizations" -// CHECK-NO-REASSOC-NO-UNSAFE-MATH: "-o" +// end marker +// CHECK-SAME: "-o" // This isn't fast-math, but the option is handled in the same place as other FP params. diff --git a/clang/test/ExtractAPI/anonymous_record_no_typedef.c b/clang/test/ExtractAPI/anonymous_record_no_typedef.c index 049e8b1f85bb96afab5ab352110068667faa8367..71e460afb1283327ff18a42e893059dc2c08ea91 100644 --- a/clang/test/ExtractAPI/anonymous_record_no_typedef.c +++ b/clang/test/ExtractAPI/anonymous_record_no_typedef.c @@ -1,417 +1,182 @@ -// XFAIL: * // RUN: rm -rf %t -// RUN: split-file %s %t -// RUN: sed -e "s@INPUT_DIR@%{/t:regex_replacement}@g" \ -// RUN: %t/reference.output.json.in >> %t/reference.output.json -// RUN: %clang_cc1 -extract-api --pretty-sgf -triple arm64-apple-macosx \ -// RUN: -x c-header %t/input.h -o %t/output.json -verify +// RUN: %clang_cc1 -extract-api --pretty-sgf --emit-sgf-symbol-labels-for-testing \ +// RUN: -triple arm64-apple-macosx -isystem %S -fretain-comments-from-system-headers \ +// RUN: -x c-header %s -o %t/output.symbols.json -verify -// Generator version is not consistent across test runs, normalize it. -// RUN: sed -e "s@\"generator\": \".*\"@\"generator\": \"?\"@g" \ -// RUN: %t/output.json >> %t/output-normalized.json -// RUN: diff %t/reference.output.json %t/output-normalized.json +// RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix GLOBAL +// RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix PREFIX +// RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix CONTENT +/// A global variable with an anonymous struct type. +struct { char *prefix; char *content; } global; +// GLOBAL-LABEL: "!testLabel": "c:@global" +// GLOBAL: "declarationFragments": [ +// GLOBAL-NEXT: { +// GLOBAL-NEXT: "kind": "keyword", +// GLOBAL-NEXT: "spelling": "struct" +// GLOBAL-NEXT: }, +// GLOBAL-NEXT: { +// GLOBAL-NEXT: "kind": "text", +// GLOBAL-NEXT: "spelling": " { ... } " +// GLOBAL-NEXT: }, +// GLOBAL-NEXT: { +// GLOBAL-NEXT: "kind": "identifier", +// GLOBAL-NEXT: "spelling": "global" +// GLOBAL-NEXT: }, +// GLOBAL-NEXT: { +// GLOBAL-NEXT: "kind": "text", +// GLOBAL-NEXT: "spelling": ";" +// GLOBAL-NEXT: } +// GLOBAL-NEXT: ], +// GLOBAL: "text": "A global variable with an anonymous struct type." +// GLOBAL: "kind": { +// GLOBAL-NEXT: "displayName": "Global Variable", +// GLOBAL-NEXT: "identifier": "c.var" +// GLOBAL: "title": "global" +// GLOBAL: "pathComponents": [ +// GLOBAL-NEXT: "global" +// GLOBAL-NEXT:] + +// PREFIX: "!testRelLabel": "memberOf $ c:@S@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@prefix $ c:@global" +// PREFIX-LABEL: "!testLabel": "c:@S@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@prefix" +// PREFIX: "title": "prefix" +// PREFIX: "pathComponents": [ +// PREFIX-NEXT: "global", +// PREFIX-NEXT: "prefix" +// PREFIX-NEXT: ] + +// CONTENT: "!testRelLabel": "memberOf $ c:@S@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@content $ c:@global" +// CONTENT-LABEL: "!testLabel": "c:@S@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@content" +// CONTENT: "title": "content" +// CONTENT: "pathComponents": [ +// CONTENT-NEXT: "global", +// CONTENT-NEXT: "content" +// CONTENT-NEXT: ] -//--- input.h /// A Vehicle struct Vehicle { + // RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix TYPE + // RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix BICYCLE + // RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix CAR /// The type of vehicle. enum { Bicycle, Car } type; + // TYPE-LABEL: "!testLabel": "c:@S@Vehicle@FI@type" + // TYPE: "declarationFragments": [ + // TYPE-NEXT: { + // TYPE-NEXT: "kind": "keyword", + // TYPE-NEXT: "spelling": "enum" + // TYPE-NEXT: }, + // TYPE-NEXT: { + // TYPE-NEXT: "kind": "text", + // TYPE-NEXT: "spelling": " { ... } " + // TYPE-NEXT: }, + // TYPE-NEXT: { + // TYPE-NEXT: "kind": "identifier", + // TYPE-NEXT: "spelling": "type" + // TYPE-NEXT: }, + // TYPE-NEXT: { + // TYPE-NEXT: "kind": "text", + // TYPE-NEXT: "spelling": ";" + // TYPE-NEXT: } + // TYPE-NEXT: ], + // TYPE: "text": "The type of vehicle." + // TYPE: "title": "type" + + // BICYCLE: "!testRelLabel": "memberOf $ c:@S@Vehicle@E@anonymous_record_no_typedef.c@{{[0-9]+}}@Bicycle $ c:@S@Vehicle@FI@type" + // BICYCLE-LABEL: "!testLabel": "c:@S@Vehicle@E@anonymous_record_no_typedef.c@{{[0-9]+}}@Bicycle" + // BICYCLE: "title": "Bicycle" + // BICYCLE: "pathComponents": [ + // BICYCLE-NEXT: "Vehicle", + // BICYCLE-NEXT: "type", + // BICYCLE-NEXT: "Bicycle" + // BICYCLE-NEXT: ] + // CAR: "!testRelLabel": "memberOf $ c:@S@Vehicle@E@anonymous_record_no_typedef.c@{{[0-9]+}}@Car $ c:@S@Vehicle@FI@type" + // CAR-LABEL: "!testLabel": "c:@S@Vehicle@E@anonymous_record_no_typedef.c@{{[0-9]+}}@Car" + // CAR: "title": "Car" + // CAR: "pathComponents": [ + // CAR-NEXT: "Vehicle", + // CAR-NEXT: "type", + // CAR-NEXT: "Car" + // CAR-NEXT: ] + + // RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix INFORMATION + // RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix WHEELS + // RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix NAME /// The information about the vehicle. - struct { + union { int wheels; char *name; } information; + // INFORMATION-LABEL: "!testLabel": "c:@S@Vehicle@FI@information" + // INFORMATION: "declarationFragments": [ + // INFORMATION-NEXT: { + // INFORMATION-NEXT: "kind": "keyword", + // INFORMATION-NEXT: "spelling": "union" + // INFORMATION-NEXT: }, + // INFORMATION-NEXT: { + // INFORMATION-NEXT: "kind": "text", + // INFORMATION-NEXT: "spelling": " { ... } " + // INFORMATION-NEXT: }, + // INFORMATION-NEXT: { + // INFORMATION-NEXT: "kind": "identifier", + // INFORMATION-NEXT: "spelling": "information" + // INFORMATION-NEXT: }, + // INFORMATION-NEXT: { + // INFORMATION-NEXT: "kind": "text", + // INFORMATION-NEXT: "spelling": ";" + // INFORMATION-NEXT: } + // INFORMATION-NEXT: ], + // INFORMATION: "text": "The information about the vehicle." + // INFORMATION: "title": "information" + + // WHEELS: "!testRelLabel": "memberOf $ c:@S@Vehicle@U@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@wheels $ c:@S@Vehicle@FI@information" + // WHEELS-LABEL: "!testLabel": "c:@S@Vehicle@U@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@wheels" + // WHEELS: "title": "wheels" + // WHEELS: "pathComponents": [ + // WHEELS-NEXT: "Vehicle", + // WHEELS-NEXT: "information", + // WHEELS-NEXT: "wheels" + // WHEELS-NEXT: ] + + // NAME: "!testRelLabel": "memberOf $ c:@S@Vehicle@U@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@name $ c:@S@Vehicle@FI@information" + // NAME-LABEL: "!testLabel": "c:@S@Vehicle@U@anonymous_record_no_typedef.c@{{[0-9]+}}@FI@name" + // NAME: "title": "name" + // NAME: "pathComponents": [ + // NAME-NEXT: "Vehicle", + // NAME-NEXT: "information", + // NAME-NEXT: "name" + // NAME-NEXT: ] }; -// expected-no-diagnostics -//--- reference.output.json.in -{ - "metadata": { - "formatVersion": { - "major": 0, - "minor": 5, - "patch": 3 - }, - "generator": "?" - }, - "module": { - "name": "", - "platform": { - "architecture": "arm64", - "operatingSystem": { - "minimumVersion": { - "major": 11, - "minor": 0, - "patch": 0 - }, - "name": "macosx" - }, - "vendor": "apple" - } - }, - "relationships": [ - { - "kind": "memberOf", - "source": "c:@S@Vehicle@E@input.h@64@Bicycle", - "target": "c:@S@Vehicle@E@input.h@64", - "targetFallback": "Vehicle::enum (unnamed)" - }, - { - "kind": "memberOf", - "source": "c:@S@Vehicle@E@input.h@64@Car", - "target": "c:@S@Vehicle@E@input.h@64", - "targetFallback": "Vehicle::enum (unnamed)" - }, - { - "kind": "memberOf", - "source": "c:@S@Vehicle@FI@type", - "target": "c:@S@Vehicle", - "targetFallback": "Vehicle" - }, - { - "kind": "memberOf", - "source": "c:@S@Vehicle@FI@information", - "target": "c:@S@Vehicle", - "targetFallback": "Vehicle" - } - ], - "symbols": [ - { - "accessLevel": "public", - "declarationFragments": [ - { - "kind": "keyword", - "spelling": "enum" - }, - { - "kind": "text", - "spelling": ": " - }, - { - "kind": "typeIdentifier", - "preciseIdentifier": "c:i", - "spelling": "unsigned int" - }, - { - "kind": "text", - "spelling": ";" - } - ], - "docComment": { - "lines": [ - { - "range": { - "end": { - "character": 28, - "line": 2 - }, - "start": { - "character": 8, - "line": 2 - } - }, - "text": "The type of vehicle." - } - ] - }, - "identifier": { - "interfaceLanguage": "c", - "precise": "c:@S@Vehicle@E@input.h@64" - }, - "kind": { - "displayName": "Enumeration", - "identifier": "c.enum" - }, - "location": { - "position": { - "character": 4, - "line": 3 - }, - "uri": "file://INPUT_DIR/input.h" - }, - "names": { - "navigator": [ - { - "kind": "identifier", - "spelling": "Vehicle::enum (unnamed)" - } - ], - "title": "Vehicle::enum (unnamed)" - }, - "pathComponents": [ - "Vehicle::enum (unnamed)" - ] - }, - { - "accessLevel": "public", - "declarationFragments": [ - { - "kind": "identifier", - "spelling": "Bicycle" - } - ], - "identifier": { - "interfaceLanguage": "c", - "precise": "c:@S@Vehicle@E@input.h@64@Bicycle" - }, - "kind": { - "displayName": "Enumeration Case", - "identifier": "c.enum.case" - }, - "location": { - "position": { - "character": 8, - "line": 4 - }, - "uri": "file://INPUT_DIR/input.h" - }, - "names": { - "navigator": [ - { - "kind": "identifier", - "spelling": "Bicycle" - } - ], - "subHeading": [ - { - "kind": "identifier", - "spelling": "Bicycle" - } - ], - "title": "Bicycle" - }, - "pathComponents": [ - "Vehicle::enum (unnamed)", - "Bicycle" - ] - }, - { - "accessLevel": "public", - "declarationFragments": [ - { - "kind": "identifier", - "spelling": "Car" - } - ], - "identifier": { - "interfaceLanguage": "c", - "precise": "c:@S@Vehicle@E@input.h@64@Car" - }, - "kind": { - "displayName": "Enumeration Case", - "identifier": "c.enum.case" - }, - "location": { - "position": { - "character": 8, - "line": 5 - }, - "uri": "file://INPUT_DIR/input.h" - }, - "names": { - "navigator": [ - { - "kind": "identifier", - "spelling": "Car" - } - ], - "subHeading": [ - { - "kind": "identifier", - "spelling": "Car" - } - ], - "title": "Car" - }, - "pathComponents": [ - "Vehicle::enum (unnamed)", - "Car" - ] - }, - { - "accessLevel": "public", - "declarationFragments": [ - { - "kind": "keyword", - "spelling": "struct" - }, - { - "kind": "text", - "spelling": " " - }, - { - "kind": "identifier", - "spelling": "Vehicle" - }, - { - "kind": "text", - "spelling": ";" - } - ], - "docComment": { - "lines": [ - { - "range": { - "end": { - "character": 13, - "line": 0 - }, - "start": { - "character": 4, - "line": 0 - } - }, - "text": "A Vehicle" - } - ] - }, - "identifier": { - "interfaceLanguage": "c", - "precise": "c:@S@Vehicle" - }, - "kind": { - "displayName": "Structure", - "identifier": "c.struct" - }, - "location": { - "position": { - "character": 7, - "line": 1 - }, - "uri": "file://INPUT_DIR/input.h" - }, - "names": { - "navigator": [ - { - "kind": "identifier", - "spelling": "Vehicle" - } - ], - "subHeading": [ - { - "kind": "identifier", - "spelling": "Vehicle" - } - ], - "title": "Vehicle" - }, - "pathComponents": [ - "Vehicle" - ] - }, - { - "accessLevel": "public", - "declarationFragments": [ - { - "kind": "keyword", - "spelling": "enum" - }, - { - "kind": "text", - "spelling": " " - }, - { - "kind": "identifier", - "spelling": "type" - }, - { - "kind": "text", - "spelling": ";" - } - ], - "identifier": { - "interfaceLanguage": "c", - "precise": "c:@S@Vehicle@FI@type" - }, - "kind": { - "displayName": "Instance Property", - "identifier": "c.property" - }, - "location": { - "position": { - "character": 6, - "line": 6 - }, - "uri": "file://INPUT_DIR/input.h" - }, - "names": { - "navigator": [ - { - "kind": "identifier", - "spelling": "type" - } - ], - "subHeading": [ - { - "kind": "identifier", - "spelling": "type" - } - ], - "title": "type" - }, - "pathComponents": [ - "Vehicle", - "type" - ] - }, - { - "accessLevel": "public", - "declarationFragments": [ - { - "kind": "keyword", - "spelling": "struct" - }, - { - "kind": "text", - "spelling": " " - }, - { - "kind": "identifier", - "spelling": "information" - }, - { - "kind": "text", - "spelling": ";" - } - ], - "identifier": { - "interfaceLanguage": "c", - "precise": "c:@S@Vehicle@FI@information" - }, - "kind": { - "displayName": "Instance Property", - "identifier": "c.property" - }, - "location": { - "position": { - "character": 6, - "line": 12 - }, - "uri": "file://INPUT_DIR/input.h" - }, - "names": { - "navigator": [ - { - "kind": "identifier", - "spelling": "information" - } - ], - "subHeading": [ - { - "kind": "identifier", - "spelling": "information" - } - ], - "title": "information" - }, - "pathComponents": [ - "Vehicle", - "information" - ] - } - ] -} +// RUN: FileCheck %s --input-file %t/output.symbols.json --check-prefix GLOBALENUM +enum { + GlobalCase, + GlobalOtherCase +}; +// GLOBALENUM-DAG: "!testRelLabel": "memberOf $ c:@Ea@GlobalCase@GlobalCase $ c:@Ea@GlobalCase" +// GLOBALENUM-DAG: "!testRelLabel": "memberOf $ c:@Ea@GlobalCase@GlobalOtherCase $ c:@Ea@GlobalCase" +// GLOBALENUM-LABEL: "!testLabel": "c:@Ea@GlobalCase" +// GLOBALENUM: "declarationFragments": [ +// GLOBALENUM-NEXT: { +// GLOBALENUM-NEXT: "kind": "keyword", +// GLOBALENUM-NEXT: "spelling": "enum" +// GLOBALENUM-NEXT: }, +// GLOBALENUM-NEXT: { +// GLOBALENUM-NEXT: "kind": "text", +// GLOBALENUM-NEXT: "spelling": " : " +// GLOBALENUM-NEXT: }, +// GLOBALENUM-NEXT: { +// GLOBALENUM-NEXT: "kind": "typeIdentifier", +// GLOBALENUM-NEXT: "preciseIdentifier": "c:i", +// GLOBALENUM-NEXT: "spelling": "unsigned int" +// GLOBALENUM-NEXT: }, +// GLOBALENUM-NEXT: { +// GLOBALENUM-NEXT: "kind": "text", +// GLOBALENUM-NEXT: "spelling": " { ... };" +// GLOBALENUM-NEXT: } +// GLOBALENUM-NEXT: ] + +// expected-no-diagnostics diff --git a/clang/test/ExtractAPI/enum.c b/clang/test/ExtractAPI/enum.c index 1cdf45ca3cdf4ba0d097a736e7477167ff5a3987..67e003834a7d58243236c59554e372e3bb8d4f1c 100644 --- a/clang/test/ExtractAPI/enum.c +++ b/clang/test/ExtractAPI/enum.c @@ -147,7 +147,7 @@ enum { }, { "kind": "text", - "spelling": ": " + "spelling": " : " }, { "kind": "typeIdentifier", @@ -459,7 +459,7 @@ enum { }, { "kind": "text", - "spelling": ": " + "spelling": " : " }, { "kind": "typeIdentifier", @@ -686,7 +686,7 @@ enum { }, { "kind": "text", - "spelling": ": " + "spelling": " : " }, { "kind": "typeIdentifier", @@ -695,7 +695,7 @@ enum { }, { "kind": "text", - "spelling": ";" + "spelling": " { ... };" } ], "identifier": { @@ -778,7 +778,7 @@ enum { }, { "kind": "text", - "spelling": ": " + "spelling": " : " }, { "kind": "typeIdentifier", @@ -787,7 +787,7 @@ enum { }, { "kind": "text", - "spelling": ";" + "spelling": " { ... };" } ], "identifier": { diff --git a/clang/test/ExtractAPI/function_noexcepts.cpp b/clang/test/ExtractAPI/function_noexcepts.cpp index d95eaaa7e769a5a226ef30ca18680be655475f33..fc18ecb04fefd012b3c8e85c9229660040c2cdad 100644 --- a/clang/test/ExtractAPI/function_noexcepts.cpp +++ b/clang/test/ExtractAPI/function_noexcepts.cpp @@ -63,11 +63,7 @@ void getFooBar() noexcept(false); }, { "kind": "text", - "spelling": "()" - }, - { - "kind": "text", - "spelling": " " + "spelling": "() " }, { "kind": "keyword", @@ -139,11 +135,7 @@ void getFooBar() noexcept(false); }, { "kind": "text", - "spelling": "()" - }, - { - "kind": "text", - "spelling": " " + "spelling": "() " }, { "kind": "keyword", @@ -223,11 +215,7 @@ void getFooBar() noexcept(false); }, { "kind": "text", - "spelling": "()" - }, - { - "kind": "text", - "spelling": " " + "spelling": "() " }, { "kind": "keyword", diff --git a/clang/test/ExtractAPI/methods.cpp b/clang/test/ExtractAPI/methods.cpp index 412c0bb3f903c3d51db897a4f566941dd0fa1a2c..67f04b4d33db833aa883d070c8bf018baa0f5131 100644 --- a/clang/test/ExtractAPI/methods.cpp +++ b/clang/test/ExtractAPI/methods.cpp @@ -81,11 +81,7 @@ class Foo { // SETL-NEXT: }, // SETL-NEXT: { // SETL-NEXT: "kind": "text", - // SETL-NEXT: "spelling": ")" - // SETL-NEXT: }, - // SETL-NEXT: { - // SETL-NEXT: "kind": "text", - // SETL-NEXT: "spelling": " " + // SETL-NEXT: "spelling": ") " // SETL-NEXT: }, // SETL-NEXT: { // SETL-NEXT: "kind": "keyword", diff --git a/clang/test/ExtractAPI/objc_block.m b/clang/test/ExtractAPI/objc_block.m index 4a4335ec09832d65f80fb891bce9529590e8371d..4761a864f5349f5d03ba947be8ac66814fca5d51 100644 --- a/clang/test/ExtractAPI/objc_block.m +++ b/clang/test/ExtractAPI/objc_block.m @@ -35,11 +35,7 @@ // NOPARAM-NEXT: }, // NOPARAM-NEXT: { // NOPARAM-NEXT: "kind": "text", -// NOPARAM-NEXT: "spelling": " (^" -// NOPARAM-NEXT: }, -// NOPARAM-NEXT: { -// NOPARAM-NEXT: "kind": "text", -// NOPARAM-NEXT: "spelling": ")()) " +// NOPARAM-NEXT: "spelling": " (^)()) " // NOPARAM-NEXT: }, // NOPARAM-NEXT: { // NOPARAM-NEXT: "kind": "internalParam", @@ -65,11 +61,7 @@ // NOPARAM-NEXT: }, // NOPARAM-NEXT: { // NOPARAM-NEXT: "kind": "text", -// NOPARAM-NEXT: "spelling": " (^" -// NOPARAM-NEXT: }, -// NOPARAM-NEXT: { -// NOPARAM-NEXT: "kind": "text", -// NOPARAM-NEXT: "spelling": ")()) " +// NOPARAM-NEXT: "spelling": " (^)()) " // NOPARAM-NEXT: }, // NOPARAM-NEXT: { // NOPARAM-NEXT: "kind": "internalParam", @@ -120,11 +112,7 @@ // PARAM-NEXT: }, // PARAM-NEXT: { // PARAM-NEXT: "kind": "text", -// PARAM-NEXT: "spelling": " (^" -// PARAM-NEXT: }, -// PARAM-NEXT: { -// PARAM-NEXT: "kind": "text", -// PARAM-NEXT: "spelling": ")(" +// PARAM-NEXT: "spelling": " (^)(" // PARAM-NEXT: }, // PARAM-NEXT: { // PARAM-NEXT: "kind": "typeIdentifier", @@ -167,11 +155,7 @@ // PARAM-NEXT: }, // PARAM-NEXT: { // PARAM-NEXT: "kind": "text", -// PARAM-NEXT: "spelling": " (^" -// PARAM-NEXT: }, -// PARAM-NEXT: { -// PARAM-NEXT: "kind": "text", -// PARAM-NEXT: "spelling": ")(" +// PARAM-NEXT: "spelling": " (^)(" // PARAM-NEXT: }, // PARAM-NEXT: { // PARAM-NEXT: "kind": "typeIdentifier", @@ -239,11 +223,7 @@ // MULTIPARAM-NEXT: }, // MULTIPARAM-NEXT: { // MULTIPARAM-NEXT: "kind": "text", -// MULTIPARAM-NEXT: "spelling": " (^" -// MULTIPARAM-NEXT: }, -// MULTIPARAM-NEXT: { -// MULTIPARAM-NEXT: "kind": "text", -// MULTIPARAM-NEXT: "spelling": ")(" +// MULTIPARAM-NEXT: "spelling": " (^)(" // MULTIPARAM-NEXT: }, // MULTIPARAM-NEXT: { // MULTIPARAM-NEXT: "kind": "typeIdentifier", @@ -303,11 +283,7 @@ // MULTIPARAM-NEXT: }, // MULTIPARAM-NEXT: { // MULTIPARAM-NEXT: "kind": "text", -// MULTIPARAM-NEXT: "spelling": " (^" -// MULTIPARAM-NEXT: }, -// MULTIPARAM-NEXT: { -// MULTIPARAM-NEXT: "kind": "text", -// MULTIPARAM-NEXT: "spelling": ")(" +// MULTIPARAM-NEXT: "spelling": " (^)(" // MULTIPARAM-NEXT: }, // MULTIPARAM-NEXT: { // MULTIPARAM-NEXT: "kind": "typeIdentifier", @@ -392,11 +368,7 @@ // VARIADIC-NEXT: }, // VARIADIC-NEXT: { // VARIADIC-NEXT: "kind": "text", -// VARIADIC-NEXT: "spelling": " (^" -// VARIADIC-NEXT: }, -// VARIADIC-NEXT: { -// VARIADIC-NEXT: "kind": "text", -// VARIADIC-NEXT: "spelling": ")(" +// VARIADIC-NEXT: "spelling": " (^)(" // VARIADIC-NEXT: }, // VARIADIC-NEXT: { // VARIADIC-NEXT: "kind": "typeIdentifier", @@ -439,11 +411,7 @@ // VARIADIC-NEXT: }, // VARIADIC-NEXT: { // VARIADIC-NEXT: "kind": "text", -// VARIADIC-NEXT: "spelling": " (^" -// VARIADIC-NEXT: }, -// VARIADIC-NEXT: { -// VARIADIC-NEXT: "kind": "text", -// VARIADIC-NEXT: "spelling": ")(" +// VARIADIC-NEXT: "spelling": " (^)(" // VARIADIC-NEXT: }, // VARIADIC-NEXT: { // VARIADIC-NEXT: "kind": "typeIdentifier", diff --git a/clang/test/ExtractAPI/typedef_anonymous_record.c b/clang/test/ExtractAPI/typedef_anonymous_record.c index 9e00ff752546546eacfc700090382dd0c260810a..9c03e9e190ed6bb15f986203d60fb48a9d1e6761 100644 --- a/clang/test/ExtractAPI/typedef_anonymous_record.c +++ b/clang/test/ExtractAPI/typedef_anonymous_record.c @@ -21,7 +21,7 @@ typedef struct { } MyStruct; // MYSTRUCT-NEXT: }, // MYSTRUCT-NEXT: { // MYSTRUCT-NEXT: "kind": "text", -// MYSTRUCT-NEXT: "spelling": " " +// MYSTRUCT-NEXT: "spelling": " { ... } " // MYSTRUCT-NEXT: }, // MYSTRUCT-NEXT: { // MYSTRUCT-NEXT: "kind": "identifier", @@ -97,7 +97,7 @@ typedef enum { Case } MyEnum; // MYENUM-NEXT: }, // MYENUM-NEXT: { // MYENUM-NEXT: "kind": "text", -// MYENUM-NEXT: "spelling": " " +// MYENUM-NEXT: "spelling": " { ... } " // MYENUM-NEXT: }, // MYENUM-NEXT: { // MYENUM-NEXT: "kind": "identifier", diff --git a/clang/test/ExtractAPI/typedef_struct_enum.c b/clang/test/ExtractAPI/typedef_struct_enum.c index fb6fbe987624f8681a20dd6abf00ae8022ce9fb5..64b7186756660fba7e1e42f9759d7dc675d2af13 100644 --- a/clang/test/ExtractAPI/typedef_struct_enum.c +++ b/clang/test/ExtractAPI/typedef_struct_enum.c @@ -72,7 +72,7 @@ typedef enum Test2 { // TEST2-NEXT: }, // TEST2-NEXT: { // TEST2-NEXT: "kind": "text", -// TEST2-NEXT: "spelling": ": " +// TEST2-NEXT: "spelling": " : " // TEST2-NEXT: }, // TEST2-NEXT: { // TEST2-NEXT: "kind": "typeIdentifier", diff --git a/clang/test/Headers/wasm.c b/clang/test/Headers/wasm.c index 57f8b6d0db176a29ac71454b1f0c3e1c41aaf3b1..b22d87a5f8b7005d6732a079a83af93d833889b7 100644 --- a/clang/test/Headers/wasm.c +++ b/clang/test/Headers/wasm.c @@ -1572,7 +1572,7 @@ uint32_t test_i8x16_bitmask(v128_t a) { // CHECK-LABEL: @test_i8x16_popcnt( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = bitcast <4 x i32> [[A:%.*]] to <16 x i8> -// CHECK-NEXT: [[TMP1:%.*]] = tail call <16 x i8> @llvm.ctpop.v16i8(<16 x i8> [[TMP0]]), !range [[RNG5:![0-9]+]] +// CHECK-NEXT: [[TMP1:%.*]] = tail call range(i8 0, 9) <16 x i8> @llvm.ctpop.v16i8(<16 x i8> [[TMP0]]) // CHECK-NEXT: [[TMP2:%.*]] = bitcast <16 x i8> [[TMP1]] to <4 x i32> // CHECK-NEXT: ret <4 x i32> [[TMP2]] // diff --git a/clang/test/Modules/prune-non-affecting-module-map-files-textual.c b/clang/test/Modules/prune-non-affecting-module-map-files-textual.c new file mode 100644 index 0000000000000000000000000000000000000000..fce325d4774c270647fbd2a2eaf2fff7a15daada --- /dev/null +++ b/clang/test/Modules/prune-non-affecting-module-map-files-textual.c @@ -0,0 +1,46 @@ +// This test checks that a module map with a textual header can be marked as +// non-affecting. + +// RUN: rm -rf %t && mkdir %t +// RUN: split-file %s %t + +//--- X.modulemap +module X { textual header "X.h" } +//--- X.h +typedef int X_int; + +//--- Y.modulemap +module Y { textual header "Y.h" } +//--- Y.h +typedef int Y_int; + +//--- A.modulemap +module A { header "A.h" export * } +//--- A.h +#include "X.h" + +// RUN: %clang_cc1 -fmodules -emit-module %t/A.modulemap -fmodule-name=A -o %t/A0.pcm \ +// RUN: -fmodule-map-file=%t/X.modulemap +// RUN: %clang_cc1 -fsyntax-only -module-file-info %t/A0.pcm | FileCheck %s --check-prefix=A0 --implicit-check-not=Y.modulemap +// A0: Input file: {{.*}}X.modulemap + +// RUN: %clang_cc1 -fmodules -emit-module %t/A.modulemap -fmodule-name=A -o %t/A1.pcm \ +// RUN: -fmodule-map-file=%t/X.modulemap -fmodule-map-file=%t/Y.modulemap +// RUN: %clang_cc1 -fsyntax-only -module-file-info %t/A0.pcm | FileCheck %s --check-prefix=A1 \ +// RUN: --implicit-check-not=Y.modulemap +// A1: Input file: {{.*}}X.modulemap + +// RUN: diff %t/A0.pcm %t/A1.pcm + +//--- B.modulemap +module B { header "B.h" export * } +//--- B.h +#include "A.h" +typedef X_int B_int; + +// RUN: %clang_cc1 -fmodules -emit-module %t/B.modulemap -fmodule-name=B -o %t/B.pcm \ +// RUN: -fmodule-file=A=%t/A0.pcm \ +// RUN: -fmodule-map-file=%t/A.modulemap -fmodule-map-file=%t/X.modulemap -fmodule-map-file=%t/Y.modulemap +// RUN: %clang_cc1 -fsyntax-only -module-file-info %t/B.pcm | FileCheck %s --check-prefix=B \ +// RUN: --implicit-check-not=X.modulemap --implicit-check-not=Y.modulemap +// B: Input file: {{.*}}B.modulemap diff --git a/clang/test/Preprocessor/riscv-target-features.c b/clang/test/Preprocessor/riscv-target-features.c index 646043681fe330cf1f1281214ca22ecf6e0858cb..ee4f81cd654bca2c4690acd936671faf00405189 100644 --- a/clang/test/Preprocessor/riscv-target-features.c +++ b/clang/test/Preprocessor/riscv-target-features.c @@ -174,6 +174,7 @@ // CHECK-NOT: __riscv_ssqosid{{.*$}} // CHECK-NOT: __riscv_supm{{.*$}} // CHECK-NOT: __riscv_zaamo {{.*$}} +// CHECK-NOT: __riscv_zabha {{.*$}} // CHECK-NOT: __riscv_zalasr {{.*$}} // CHECK-NOT: __riscv_zalrsc {{.*$}} // CHECK-NOT: __riscv_zfbfmin {{.*$}} @@ -698,10 +699,10 @@ // CHECK-ZA64RS-EXT: __riscv_za64rs 1000000{{$}} // RUN: %clang --target=riscv32 \ -// RUN: -march=rv32i_zacas1p0 -E -dM %s \ +// RUN: -march=rv32ia_zacas1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s // RUN: %clang --target=riscv64 \ -// RUN: -march=rv64i_zacas1p0 -E -dM %s \ +// RUN: -march=rv64ia_zacas1p0 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZACAS-EXT %s // CHECK-ZACAS-EXT: __riscv_zacas 1000000{{$}} @@ -1552,6 +1553,14 @@ // RUN: -o - | FileCheck --check-prefix=CHECK-ZAAMO-EXT %s // CHECK-ZAAMO-EXT: __riscv_zaamo 2000{{$}} +// RUN: %clang --target=riscv32 -menable-experimental-extensions \ +// RUN: -march=rv32ia_zabha1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZABHA-EXT %s +// RUN: %clang --target=riscv64 -menable-experimental-extensions \ +// RUN: -march=rv64ia_zabha1p0 -E -dM %s \ +// RUN: -o - | FileCheck --check-prefix=CHECK-ZABHA-EXT %s +// CHECK-ZABHA-EXT: __riscv_zabha 1000000{{$}} + // RUN: %clang --target=riscv32 -menable-experimental-extensions \ // RUN: -march=rv32i_zalasr0p1 -E -dM %s \ // RUN: -o - | FileCheck --check-prefix=CHECK-ZALASR-EXT %s diff --git a/clang/test/Preprocessor/wasm-target-features.c b/clang/test/Preprocessor/wasm-target-features.c index eccd432aa8eee66d12bf146a291bf0f6cd10696c..32e24ad1b71656eca04d6db46b3bc730576a531d 100644 --- a/clang/test/Preprocessor/wasm-target-features.c +++ b/clang/test/Preprocessor/wasm-target-features.c @@ -1,38 +1,29 @@ // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -msimd128 \ -// RUN: | FileCheck %s -check-prefix=SIMD128 -// RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -msimd128 \ -// RUN: | FileCheck %s -check-prefix=SIMD128 -// -// SIMD128:#define __wasm_simd128__ 1{{$}} - -// RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mrelaxed-simd \ -// RUN: | FileCheck %s -check-prefix=RELAXED-SIMD +// RUN: -target wasm32-unknown-unknown -matomics \ +// RUN: | FileCheck %s -check-prefix=ATOMICS // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mrelaxed-simd \ -// RUN: | FileCheck %s -check-prefix=RELAXED-SIMD +// RUN: -target wasm64-unknown-unknown -matomics \ +// RUN: | FileCheck %s -check-prefix=ATOMICS // -// RELAXED-SIMD:#define __wasm_relaxed_simd__ 1{{$}} +// ATOMICS: #define __wasm_atomics__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mnontrapping-fptoint \ -// RUN: | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT +// RUN: -target wasm32-unknown-unknown -pthread \ +// RUN: | FileCheck %s -check-prefix=PTHREAD // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mnontrapping-fptoint \ -// RUN: | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT +// RUN: -target wasm64-unknown-unknown -pthread \ +// RUN: | FileCheck %s -check-prefix=PTHREAD // -// NONTRAPPING-FPTOINT:#define __wasm_nontrapping_fptoint__ 1{{$}} +// PTHREAD: #define __wasm_atomics__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -msign-ext \ -// RUN: | FileCheck %s -check-prefix=SIGN-EXT +// RUN: -target wasm32-unknown-unknown -mbulk-memory \ +// RUN: | FileCheck %s -check-prefix=BULK-MEMORY // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -msign-ext \ -// RUN: | FileCheck %s -check-prefix=SIGN-EXT +// RUN: -target wasm64-unknown-unknown -mbulk-memory \ +// RUN: | FileCheck %s -check-prefix=BULK-MEMORY // -// SIGN-EXT:#define __wasm_sign_ext__ 1{{$}} +// BULK-MEMORY: #define __wasm_bulk_memory__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mexception-handling \ @@ -41,34 +32,34 @@ // RUN: -target wasm64-unknown-unknown -mexception-handling \ // RUN: | FileCheck %s -check-prefix=EXCEPTION-HANDLING // -// EXCEPTION-HANDLING:#define __wasm_exception_handling__ 1{{$}} +// EXCEPTION-HANDLING: #define __wasm_exception_handling__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mbulk-memory \ -// RUN: | FileCheck %s -check-prefix=BULK-MEMORY +// RUN: -target wasm32-unknown-unknown -mextended-const \ +// RUN: | FileCheck %s -check-prefix=EXTENDED-CONST // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mbulk-memory \ -// RUN: | FileCheck %s -check-prefix=BULK-MEMORY +// RUN: -target wasm64-unknown-unknown -mextended-const \ +// RUN: | FileCheck %s -check-prefix=EXTENDED-CONST // -// BULK-MEMORY:#define __wasm_bulk_memory__ 1{{$}} +// EXTENDED-CONST: #define __wasm_extended_const__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -matomics \ -// RUN: | FileCheck %s -check-prefix=ATOMICS +// RUN: -target wasm32-unknown-unknown -mmultimemory \ +// RUN: | FileCheck %s -check-prefix=MULTIMEMORY // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -matomics \ -// RUN: | FileCheck %s -check-prefix=ATOMICS +// RUN: -target wasm64-unknown-unknown -mmultimemory \ +// RUN: | FileCheck %s -check-prefix=MULTIMEMORY // -// ATOMICS:#define __wasm_atomics__ 1{{$}} +// MULTIMEMORY: #define __wasm_multimemory__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -pthread \ -// RUN: | FileCheck %s -check-prefix=PTHREAD +// RUN: -target wasm32-unknown-unknown -mmultivalue \ +// RUN: | FileCheck %s -check-prefix=MULTIVALUE // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -pthread \ -// RUN: | FileCheck %s -check-prefix=PTHREAD +// RUN: -target wasm64-unknown-unknown -mmultivalue \ +// RUN: | FileCheck %s -check-prefix=MULTIVALUE // -// PTHREAD:#define __wasm_atomics__ 1{{$}} +// MULTIVALUE: #define __wasm_multivalue__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mmutable-globals \ @@ -77,26 +68,17 @@ // RUN: -target wasm64-unknown-unknown -mmutable-globals \ // RUN: | FileCheck %s -check-prefix=MUTABLE-GLOBALS // -// MUTABLE-GLOBALS:#define __wasm_mutable_globals__ 1{{$}} +// MUTABLE-GLOBALS: #define __wasm_mutable_globals__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mmultivalue \ -// RUN: | FileCheck %s -check-prefix=MULTIVALUE +// RUN: -target wasm32-unknown-unknown -mnontrapping-fptoint \ +// RUN: | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mmultivalue \ -// RUN: | FileCheck %s -check-prefix=MULTIVALUE +// RUN: -target wasm64-unknown-unknown -mnontrapping-fptoint \ +// RUN: | FileCheck %s -check-prefix=NONTRAPPING-FPTOINT // -// MULTIVALUE:#define __wasm_multivalue__ 1{{$}} +// NONTRAPPING-FPTOINT: #define __wasm_nontrapping_fptoint__ 1{{$}} -// RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mtail-call \ -// RUN: | FileCheck %s -check-prefix=TAIL-CALL -// RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mtail-call \ -// RUN: | FileCheck %s -check-prefix=TAIL-CALL -// -// TAIL-CALL:#define __wasm_tail_call__ 1{{$}} -// // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mreference-types \ // RUN: | FileCheck %s -check-prefix=REFERENCE-TYPES @@ -104,26 +86,43 @@ // RUN: -target wasm64-unknown-unknown -mreference-types \ // RUN: | FileCheck %s -check-prefix=REFERENCE-TYPES // -// REFERENCE-TYPES:#define __wasm_reference_types__ 1{{$}} -// +// REFERENCE-TYPES: #define __wasm_reference_types__ 1{{$}} + // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mextended-const \ -// RUN: | FileCheck %s -check-prefix=EXTENDED-CONST +// RUN: -target wasm32-unknown-unknown -mrelaxed-simd \ +// RUN: | FileCheck %s -check-prefix=RELAXED-SIMD // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mextended-const \ -// RUN: | FileCheck %s -check-prefix=EXTENDED-CONST +// RUN: -target wasm64-unknown-unknown -mrelaxed-simd \ +// RUN: | FileCheck %s -check-prefix=RELAXED-SIMD // -// EXTENDED-CONST:#define __wasm_extended_const__ 1{{$}} +// RELAXED-SIMD: #define __wasm_relaxed_simd__ 1{{$}} + +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm32-unknown-unknown -msign-ext \ +// RUN: | FileCheck %s -check-prefix=SIGN-EXT +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm64-unknown-unknown -msign-ext \ +// RUN: | FileCheck %s -check-prefix=SIGN-EXT // +// SIGN-EXT: #define __wasm_sign_ext__ 1{{$}} + // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm32-unknown-unknown -mmultimemory \ -// RUN: | FileCheck %s -check-prefix=MULTIMEMORY +// RUN: -target wasm32-unknown-unknown -msimd128 \ +// RUN: | FileCheck %s -check-prefix=SIMD128 // RUN: %clang -E -dM %s -o - 2>&1 \ -// RUN: -target wasm64-unknown-unknown -mmultimemory \ -// RUN: | FileCheck %s -check-prefix=MULTIMEMORY +// RUN: -target wasm64-unknown-unknown -msimd128 \ +// RUN: | FileCheck %s -check-prefix=SIMD128 // -// MULTIMEMORY:#define __wasm_multimemory__ 1{{$}} +// SIMD128: #define __wasm_simd128__ 1{{$}} + +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm32-unknown-unknown -mtail-call \ +// RUN: | FileCheck %s -check-prefix=TAIL-CALL +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm64-unknown-unknown -mtail-call \ +// RUN: | FileCheck %s -check-prefix=TAIL-CALL // +// TAIL-CALL: #define __wasm_tail_call__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=mvp \ @@ -132,20 +131,30 @@ // RUN: -target wasm64-unknown-unknown -mcpu=mvp \ // RUN: | FileCheck %s -check-prefix=MVP // -// MVP-NOT:#define __wasm_simd128__ -// MVP-NOT:#define __wasm_nontrapping_fptoint__ -// MVP-NOT:#define __wasm_sign_ext__ -// MVP-NOT:#define __wasm_exception_handling__ -// MVP-NOT:#define __wasm_bulk_memory__ -// MVP-NOT:#define __wasm_atomics__ -// MVP-NOT:#define __wasm_mutable_globals__ -// MVP-NOT:#define __wasm_multivalue__ -// MVP-NOT:#define __wasm_tail_call__ -// MVP-NOT:#define __wasm_reference_types__ -// MVP-NOT:#define __wasm_extended_const__ -// MVP-NOT:#define __wasm_multimemory__ -// MVP-NOT:#define __wasm_relaxed_simd__ +// MVP-NOT: #define __wasm_atomics__ 1{{$}} +// MVP-NOT: #define __wasm_bulk_memory__ 1{{$}} +// MVP-NOT: #define __wasm_exception_handling__ 1{{$}} +// MVP-NOT: #define __wasm_extended_const__ 1{{$}} +// MVP-NOT: #define __wasm_multimemory__ 1{{$}} +// MVP-NOT: #define __wasm_multivalue__ 1{{$}} +// MVP-NOT: #define __wasm_mutable_globals__ 1{{$}} +// MVP-NOT: #define __wasm_nontrapping_fptoint__ 1{{$}} +// MVP-NOT: #define __wasm_reference_types__ 1{{$}} +// MVP-NOT: #define __wasm_relaxed_simd__ 1{{$}} +// MVP-NOT: #define __wasm_sign_ext__ 1{{$}} +// MVP-NOT: #define __wasm_simd128__ 1{{$}} +// MVP-NOT: #define __wasm_tail_call__ 1{{$}} +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm32-unknown-unknown -mcpu=generic \ +// RUN: | FileCheck %s -check-prefix=GENERIC-INCLUDE +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm64-unknown-unknown -mcpu=generic \ +// RUN: | FileCheck %s -check-prefix=GENERIC-INCLUDE +// +// GENERIC-INCLUDE-DAG: #define __wasm_mutable_globals__ 1{{$}} +// GENERIC-INCLUDE-DAG: #define __wasm_sign_ext__ 1{{$}} +// // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=generic \ // RUN: | FileCheck %s -check-prefix=GENERIC @@ -153,19 +162,35 @@ // RUN: -target wasm64-unknown-unknown -mcpu=generic \ // RUN: | FileCheck %s -check-prefix=GENERIC // -// GENERIC-DAG:#define __wasm_sign_ext__ 1{{$}} -// GENERIC-DAG:#define __wasm_mutable_globals__ 1{{$}} -// GENERIC-NOT:#define __wasm_nontrapping_fptoint__ 1{{$}} -// GENERIC-NOT:#define __wasm_bulk_memory__ 1{{$}} -// GENERIC-NOT:#define __wasm_simd128__ 1{{$}} -// GENERIC-NOT:#define __wasm_atomics__ 1{{$}} -// GENERIC-NOT:#define __wasm_tail_call__ 1{{$}} -// GENERIC-NOT:#define __wasm_multimemory__ 1{{$}} -// GENERIC-NOT:#define __wasm_exception_handling__ 1{{$}} -// GENERIC-NOT:#define __wasm_multivalue__ 1{{$}} -// GENERIC-NOT:#define __wasm_reference_types__ 1{{$}} -// GENERIC-NOT:#define __wasm_extended_const__ 1{{$}} +// GENERIC-NOT: #define __wasm_atomics__ 1{{$}} +// GENERIC-NOT: #define __wasm_bulk_memory__ 1{{$}} +// GENERIC-NOT: #define __wasm_exception_handling__ 1{{$}} +// GENERIC-NOT: #define __wasm_extended_const__ 1{{$}} +// GENERIC-NOT: #define __wasm_multimemory__ 1{{$}} +// GENERIC-NOT: #define __wasm_multivalue__ 1{{$}} +// GENERIC-NOT: #define __wasm_nontrapping_fptoint__ 1{{$}} +// GENERIC-NOT: #define __wasm_reference_types__ 1{{$}} +// GENERIC-NOT: #define __wasm_relaxed_simd__ 1{{$}} +// GENERIC-NOT: #define __wasm_simd128__ 1{{$}} +// GENERIC-NOT: #define __wasm_tail_call__ 1{{$}} +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge \ +// RUN: | FileCheck %s -check-prefix=BLEEDING-EDGE-INCLUDE +// RUN: %clang -E -dM %s -o - 2>&1 \ +// RUN: -target wasm64-unknown-unknown -mcpu=bleeding-edge \ +// RUN: | FileCheck %s -check-prefix=BLEEDING-EDGE-INCLUDE +// +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_atomics__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_bulk_memory__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_multimemory__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_mutable_globals__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_nontrapping_fptoint__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_reference_types__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_sign_ext__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_simd128__ 1{{$}} +// BLEEDING-EDGE-INCLUDE-DAG: #define __wasm_tail_call__ 1{{$}} +// // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge \ // RUN: | FileCheck %s -check-prefix=BLEEDING-EDGE @@ -173,19 +198,10 @@ // RUN: -target wasm64-unknown-unknown -mcpu=bleeding-edge \ // RUN: | FileCheck %s -check-prefix=BLEEDING-EDGE // -// BLEEDING-EDGE-DAG:#define __wasm_nontrapping_fptoint__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_sign_ext__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_bulk_memory__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_simd128__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_atomics__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_mutable_globals__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_tail_call__ 1{{$}} -// BLEEDING-EDGE-DAG:#define __wasm_multimemory__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_exception_handling__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_multivalue__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_reference_types__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_extended_const__ 1{{$}} -// BLEEDING-EDGE-NOT:#define __wasm_relaxed_simd__ 1{{$}} +// BLEEDING-EDGE-NOT: #define __wasm_exception_handling__ 1{{$}} +// BLEEDING-EDGE-NOT: #define __wasm_extended_const__ 1{{$}} +// BLEEDING-EDGE-NOT: #define __wasm_multivalue__ 1{{$}} +// BLEEDING-EDGE-NOT: #define __wasm_relaxed_simd__ 1{{$}} // RUN: %clang -E -dM %s -o - 2>&1 \ // RUN: -target wasm32-unknown-unknown -mcpu=bleeding-edge -mno-simd128 \ @@ -194,4 +210,4 @@ // RUN: -target wasm64-unknown-unknown -mcpu=bleeding-edge -mno-simd128 \ // RUN: | FileCheck %s -check-prefix=BLEEDING-EDGE-NO-SIMD128 // -// BLEEDING-EDGE-NO-SIMD128-NOT:#define __wasm_simd128__ +// BLEEDING-EDGE-NO-SIMD128-NOT: #define __wasm_simd128__ 1{{$}} diff --git a/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c b/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c index 6a1feeb9bf53976325eda4e393c738a392c103b9..e55e84a61034fa927a55622f8b13c87606d747b9 100644 --- a/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c +++ b/clang/test/Sema/aarch64-incompat-sm-builtin-calls.c @@ -33,7 +33,8 @@ svuint32_t incompat_sve_sm(svbool_t pg, svuint32_t a, int16_t b) __arm_streaming return __builtin_sve_svld1_gather_u32base_index_u32(pg, a, b); } -// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-warning@+2 {{returning a VL-dependent argument from a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} +// expected-warning@+1 {{passing a VL-dependent argument to a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __arm_locally_streaming svuint32_t incompat_sve_ls(svbool_t pg, svuint32_t a, int64_t b) { // expected-warning@+1 {{builtin call has undefined behaviour when called from a streaming function}} return __builtin_sve_svld1_gather_u32base_index_u32(pg, a, b); @@ -49,7 +50,8 @@ svuint32_t incompat_sve2_sm(svbool_t pg, svuint32_t a, int64_t b) __arm_streamin return __builtin_sve_svldnt1_gather_u32base_index_u32(pg, a, b); } -// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-warning@+2 {{returning a VL-dependent argument from a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} +// expected-warning@+1 {{passing a VL-dependent argument to a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __arm_locally_streaming svuint32_t incompat_sve2_ls(svbool_t pg, svuint32_t a, int64_t b) { // expected-warning@+1 {{builtin call has undefined behaviour when called from a streaming function}} return __builtin_sve_svldnt1_gather_u32base_index_u32(pg, a, b); @@ -70,7 +72,8 @@ svfloat64_t streaming_caller_sve(svbool_t pg, svfloat64_t a, float64_t b) __arm_ return svadd_n_f64_m(pg, a, b); } -// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-warning@+2 {{returning a VL-dependent argument from a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} +// expected-warning@+1 {{passing a VL-dependent argument to a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __arm_locally_streaming svfloat64_t locally_streaming_caller_sve(svbool_t pg, svfloat64_t a, float64_t b) { // expected-no-warning return svadd_n_f64_m(pg, a, b); @@ -86,7 +89,8 @@ svint16_t streaming_caller_sve2(svint16_t op1, svint16_t op2) __arm_streaming { return svmul_lane_s16(op1, op2, 0); } -// expected-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-warning@+2 {{returning a VL-dependent argument from a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} +// expected-warning@+1 {{passing a VL-dependent argument to a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __arm_locally_streaming svint16_t locally_streaming_caller_sve2(svint16_t op1, svint16_t op2) { // expected-no-warning return svmul_lane_s16(op1, op2, 0); diff --git a/clang/test/Sema/aarch64-sme-func-attrs.c b/clang/test/Sema/aarch64-sme-func-attrs.c index 12de16509ccb8d276282c14263614d83e29dc6b3..3d90723d32f1e7da9e94b4dbaea5afa2d5811134 100644 --- a/clang/test/Sema/aarch64-sme-func-attrs.c +++ b/clang/test/Sema/aarch64-sme-func-attrs.c @@ -509,73 +509,73 @@ void sme_no_streaming_with_vl_arg(__SVInt8_t a) { } __SVInt8_t sme_no_streaming_returns_vl(void) { __SVInt8_t r; return r; } -// expected-warning@+2 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} -// expected-cpp-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-warning@+2 {{passing a VL-dependent argument to a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} +// expected-cpp-warning@+1 {{passing a VL-dependent argument to a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __arm_locally_streaming void sme_locally_streaming_with_vl_arg(__SVInt8_t a) { } -// expected-warning@+2 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} -// expected-cpp-warning@+1 {{passing/returning a VL-dependent argument to/from a __arm_locally_streaming function. The streaming and non-streaming vector lengths may be different}} +// expected-warning@+2 {{returning a VL-dependent argument from a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} +// expected-cpp-warning@+1 {{returning a VL-dependent argument from a locally streaming function is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __arm_locally_streaming __SVInt8_t sme_locally_streaming_returns_vl(void) { __SVInt8_t r; return r; } void sme_no_streaming_calling_streaming_with_vl_args() { __SVInt8_t a; - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} sme_streaming_with_vl_arg(a); } void sme_no_streaming_calling_streaming_with_return_vl() { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __SVInt8_t r = sme_streaming_returns_vl(); } void sme_streaming_calling_non_streaming_with_vl_args(void) __arm_streaming { __SVInt8_t a; - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} sme_no_streaming_with_vl_arg(a); } void sme_streaming_calling_non_streaming_with_return_vl(void) __arm_streaming { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __SVInt8_t r = sme_no_streaming_returns_vl(); } void sme_no_streaming_calling_streaming_with_vl_args_param(__SVInt8_t arg, void (*sc)( __SVInt8_t arg) __arm_streaming) { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} sc(arg); } __SVInt8_t sme_no_streaming_calling_streaming_return_vl_param(__SVInt8_t (*s)(void) __arm_streaming) { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} return s(); } void sme_streaming_compatible_calling_streaming_with_vl_args(__SVInt8_t arg) __arm_streaming_compatible { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} sme_streaming_with_vl_arg(arg); } void sme_streaming_compatible_calling_sme_streaming_return_vl(void) __arm_streaming_compatible { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __SVInt8_t r = sme_streaming_returns_vl(); } void sme_streaming_compatible_calling_no_streaming_with_vl_args(__SVInt8_t arg) __arm_streaming_compatible { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{passing a VL-dependent argument to a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} sme_no_streaming_with_vl_arg(arg); } void sme_streaming_compatible_calling_no_sme_streaming_return_vl(void) __arm_streaming_compatible { - // expected-warning@+2 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} - // expected-cpp-warning@+1 {{passing a VL-dependent argument to/from a function that has a different streaming-mode. The streaming and non-streaming vector lengths may be different}} + // expected-warning@+2 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} + // expected-cpp-warning@+1 {{returning a VL-dependent argument from a function with a different streaming-mode is undefined behaviour when the streaming and non-streaming vector lengths are different at runtime}} __SVInt8_t r = sme_no_streaming_returns_vl(); } diff --git a/clang/test/SemaCXX/PR41441.cpp b/clang/test/SemaCXX/PR41441.cpp deleted file mode 100644 index 3f60b6e209207a8fe787b1912c6aaa2f7ed19013..0000000000000000000000000000000000000000 --- a/clang/test/SemaCXX/PR41441.cpp +++ /dev/null @@ -1,32 +0,0 @@ -// RUN: %clang --target=x86_64-pc-linux -S -fno-discard-value-names -emit-llvm -o - %s | FileCheck %s - -namespace std { - using size_t = decltype(sizeof(int)); -}; -void* operator new[](std::size_t, void*) noexcept; - -// CHECK: call void @llvm.memset.p0.i64(ptr align 1 %x, i8 0, i64 8, i1 false) -// CHECK: call void @llvm.memset.p0.i64(ptr align 16 %x, i8 0, i64 32, i1 false) -template -void f() -{ - typedef TYPE TArray[8]; - - TArray x; - new(&x) TArray(); -} - -template -void f1() { - int (*x)[1] = new int[1][1]; -} -template void f1(); -void f2() { - int (*x)[1] = new int[1][1]; -} - -int main() -{ - f(); - f(); -} diff --git a/clang/test/SemaCXX/template-specialization.cpp b/clang/test/SemaCXX/template-specialization.cpp index 7b26ff9f5c5ba4982dfce2e9b52cbb6ff710d8d2..eabb84f2e13d3ec5a86da42e3b563f4e28b535af 100644 --- a/clang/test/SemaCXX/template-specialization.cpp +++ b/clang/test/SemaCXX/template-specialization.cpp @@ -52,3 +52,31 @@ void instantiate() { } } + +namespace GH89374 { + +struct A {}; + +template +struct MatrixBase { // #GH89374-MatrixBase + template + Derived &operator=(const MatrixBase &); // #GH89374-copy-assignment +}; + +template +struct solve_retval; + +template +struct solve_retval : MatrixBase > {}; +// expected-error@-1 {{partial specialization of 'solve_retval' does not use any of its template parameters}} + +void ApproximateChebyshev() { + MatrixBase c; + c = solve_retval(); + // expected-error@-1 {{no viable overloaded '='}} + // expected-note@#GH89374-copy-assignment {{candidate template ignored: could not match 'MatrixBase' against 'solve_retval'}} + // expected-note@#GH89374-MatrixBase {{candidate function (the implicit copy assignment operator) not viable: no known conversion from 'solve_retval' to 'const MatrixBase' for 1st argument}} + // expected-note@#GH89374-MatrixBase {{candidate function (the implicit move assignment operator) not viable: no known conversion from 'solve_retval' to 'MatrixBase' for 1st argument}} +} + +} // namespace GH89374 diff --git a/clang/tools/c-index-test/c-index-test.c b/clang/tools/c-index-test/c-index-test.c index 21619888cfa5f3f3d835ce767eb566658ea62852..e078e9bdce027a6a2f3b8b0b25ece3a69d8c85d6 100644 --- a/clang/tools/c-index-test/c-index-test.c +++ b/clang/tools/c-index-test/c-index-test.c @@ -464,10 +464,10 @@ static void PrintRange(CXSourceRange R, const char *str) { CXFile begin_file, end_file; unsigned begin_line, begin_column, end_line, end_column; - clang_getSpellingLocation(clang_getRangeStart(R), - &begin_file, &begin_line, &begin_column, 0); - clang_getSpellingLocation(clang_getRangeEnd(R), - &end_file, &end_line, &end_column, 0); + clang_getFileLocation(clang_getRangeStart(R), &begin_file, &begin_line, + &begin_column, 0); + clang_getFileLocation(clang_getRangeEnd(R), &end_file, &end_line, &end_column, + 0); if (!begin_file || !end_file) return; @@ -849,13 +849,13 @@ static void PrintCursor(CXCursor Cursor, const char *CommentSchemaFile) { printf(", "); Loc = clang_getCursorLocation(Ovl); - clang_getSpellingLocation(Loc, 0, &line, &column, 0); + clang_getFileLocation(Loc, 0, &line, &column, 0); printf("%d:%d", line, column); } printf("]"); } else { CXSourceLocation Loc = clang_getCursorLocation(Referenced); - clang_getSpellingLocation(Loc, 0, &line, &column, 0); + clang_getFileLocation(Loc, 0, &line, &column, 0); printf(":%d:%d", line, column); } @@ -1047,7 +1047,7 @@ static void PrintCursor(CXCursor Cursor, const char *CommentSchemaFile) { if (!clang_equalCursors(SpecializationOf, clang_getNullCursor())) { CXSourceLocation Loc = clang_getCursorLocation(SpecializationOf); CXString Name = clang_getCursorSpelling(SpecializationOf); - clang_getSpellingLocation(Loc, 0, &line, &column, 0); + clang_getFileLocation(Loc, 0, &line, &column, 0); printf(" [Specialization of %s:%d:%d]", clang_getCString(Name), line, column); clang_disposeString(Name); @@ -1094,7 +1094,7 @@ static void PrintCursor(CXCursor Cursor, const char *CommentSchemaFile) { printf(" [Overrides "); for (I = 0; I != num_overridden; ++I) { CXSourceLocation Loc = clang_getCursorLocation(overridden[I]); - clang_getSpellingLocation(Loc, 0, &line, &column, 0); + clang_getFileLocation(Loc, 0, &line, &column, 0); lineCols[I].line = line; lineCols[I].col = column; } @@ -1257,8 +1257,8 @@ void PrintDiagnostic(CXDiagnostic Diagnostic) { fprintf(stderr, "%s\n", clang_getCString(Msg)); clang_disposeString(Msg); - clang_getSpellingLocation(clang_getDiagnosticLocation(Diagnostic), - &file, 0, 0, 0); + clang_getFileLocation(clang_getDiagnosticLocation(Diagnostic), &file, 0, 0, + 0); if (!file) return; @@ -1271,9 +1271,8 @@ void PrintDiagnostic(CXDiagnostic Diagnostic) { CXSourceLocation end = clang_getRangeEnd(range); unsigned start_line, start_column, end_line, end_column; CXFile start_file, end_file; - clang_getSpellingLocation(start, &start_file, &start_line, - &start_column, 0); - clang_getSpellingLocation(end, &end_file, &end_line, &end_column, 0); + clang_getFileLocation(start, &start_file, &start_line, &start_column, 0); + clang_getFileLocation(end, &end_file, &end_line, &end_column, 0); if (clang_equalLocations(start, end)) { /* Insertion. */ if (start_file == file) @@ -1356,7 +1355,7 @@ enum CXChildVisitResult FilteredPrintingVisitor(CXCursor Cursor, if (!Data->Filter || (Cursor.kind == *(enum CXCursorKind *)Data->Filter)) { CXSourceLocation Loc = clang_getCursorLocation(Cursor); unsigned line, column; - clang_getSpellingLocation(Loc, 0, &line, &column, 0); + clang_getFileLocation(Loc, 0, &line, &column, 0); printf("// %s: %s:%d:%d: ", FileCheckPrefix, GetCursorSource(Cursor), line, column); PrintCursor(Cursor, Data->CommentSchemaFile); @@ -1417,7 +1416,7 @@ static enum CXChildVisitResult FunctionScanVisitor(CXCursor Cursor, curColumn++; Loc = clang_getCursorLocation(Cursor); - clang_getSpellingLocation(Loc, &file, 0, 0, 0); + clang_getFileLocation(Loc, &file, 0, 0, 0); source = clang_getFileName(file); if (clang_getCString(source)) { @@ -1483,8 +1482,7 @@ void InclusionVisitor(CXFile includedFile, CXSourceLocation *includeStack, for (i = 0; i < includeStackLen; ++i) { CXFile includingFile; unsigned line, column; - clang_getSpellingLocation(includeStack[i], &includingFile, &line, - &column, 0); + clang_getFileLocation(includeStack[i], &includingFile, &line, &column, 0); fname = clang_getFileName(includingFile); printf(" %s:%d:%d\n", clang_getCString(fname), line, column); clang_disposeString(fname); @@ -2984,7 +2982,7 @@ static void inspect_print_cursor(CXCursor Cursor) { CXString Spelling; const char *cspell; unsigned line, column; - clang_getSpellingLocation(CursorLoc, 0, &line, &column, 0); + clang_getFileLocation(CursorLoc, 0, &line, &column, 0); printf("%d:%d ", line, column); PrintCursor(Cursor, NULL); PrintCursorExtent(Cursor); @@ -3100,7 +3098,7 @@ static void inspect_evaluate_cursor(CXCursor Cursor) { unsigned line, column; CXEvalResult ER; - clang_getSpellingLocation(CursorLoc, 0, &line, &column, 0); + clang_getFileLocation(CursorLoc, 0, &line, &column, 0); printf("%d:%d ", line, column); PrintCursor(Cursor, NULL); PrintCursorExtent(Cursor); @@ -3135,7 +3133,7 @@ static void inspect_macroinfo_cursor(CXCursor Cursor) { CXString Spelling; const char *cspell; unsigned line, column; - clang_getSpellingLocation(CursorLoc, 0, &line, &column, 0); + clang_getFileLocation(CursorLoc, 0, &line, &column, 0); printf("%d:%d ", line, column); PrintCursor(Cursor, NULL); PrintCursorExtent(Cursor); @@ -4328,10 +4326,10 @@ int perform_token_annotation(int argc, const char **argv) { skipped_ranges = clang_getSkippedRanges(TU, file); for (i = 0; i != skipped_ranges->count; ++i) { unsigned start_line, start_column, end_line, end_column; - clang_getSpellingLocation(clang_getRangeStart(skipped_ranges->ranges[i]), - 0, &start_line, &start_column, 0); - clang_getSpellingLocation(clang_getRangeEnd(skipped_ranges->ranges[i]), - 0, &end_line, &end_column, 0); + clang_getFileLocation(clang_getRangeStart(skipped_ranges->ranges[i]), 0, + &start_line, &start_column, 0); + clang_getFileLocation(clang_getRangeEnd(skipped_ranges->ranges[i]), 0, + &end_line, &end_column, 0); printf("Skipping: "); PrintExtent(stdout, start_line, start_column, end_line, end_column); printf("\n"); @@ -4351,10 +4349,10 @@ int perform_token_annotation(int argc, const char **argv) { case CXToken_Literal: kind = "Literal"; break; case CXToken_Comment: kind = "Comment"; break; } - clang_getSpellingLocation(clang_getRangeStart(extent), - 0, &start_line, &start_column, 0); - clang_getSpellingLocation(clang_getRangeEnd(extent), - 0, &end_line, &end_column, 0); + clang_getFileLocation(clang_getRangeStart(extent), 0, &start_line, + &start_column, 0); + clang_getFileLocation(clang_getRangeEnd(extent), 0, &end_line, &end_column, + 0); printf("%s: \"%s\" ", kind, clang_getCString(spelling)); clang_disposeString(spelling); PrintExtent(stdout, start_line, start_column, end_line, end_column); diff --git a/clang/tools/driver/cc1_main.cpp b/clang/tools/driver/cc1_main.cpp index b5c6be3c557bb374c1f5f835d692db80634cae3f..2aebc6d3c017826447cd181789cf1d553864e960 100644 --- a/clang/tools/driver/cc1_main.cpp +++ b/clang/tools/driver/cc1_main.cpp @@ -39,7 +39,6 @@ #include "llvm/Support/ManagedStatic.h" #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/Signals.h" #include "llvm/Support/TargetSelect.h" #include "llvm/Support/TimeProfiler.h" @@ -48,6 +47,7 @@ #include "llvm/Target/TargetMachine.h" #include "llvm/TargetParser/AArch64TargetParser.h" #include "llvm/TargetParser/ARMTargetParser.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include #ifdef CLANG_HAVE_RLIMITS diff --git a/clang/tools/libclang/CXSourceLocation.cpp b/clang/tools/libclang/CXSourceLocation.cpp index ba70cbfee8995f25b9cef3e5f0cf59606331eb27..53cb71f7276f29913894e73b584865a12860cad7 100644 --- a/clang/tools/libclang/CXSourceLocation.cpp +++ b/clang/tools/libclang/CXSourceLocation.cpp @@ -319,8 +319,7 @@ void clang_getSpellingLocation(CXSourceLocation location, const SourceManager &SM = *static_cast(location.ptr_data[0]); - // FIXME: This should call SourceManager::getSpellingLoc(). - SourceLocation SpellLoc = SM.getFileLoc(Loc); + SourceLocation SpellLoc = SM.getSpellingLoc(Loc); std::pair LocInfo = SM.getDecomposedLoc(SpellLoc); FileID FID = LocInfo.first; unsigned FileOffset = LocInfo.second; diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp b/clang/unittests/Format/TokenAnnotatorTest.cpp index 34999b7376397b62c74f239f18da88544fa0308d..6b8ab441cb46f86f9708bc542b4cc5960d9c12a0 100644 --- a/clang/unittests/Format/TokenAnnotatorTest.cpp +++ b/clang/unittests/Format/TokenAnnotatorTest.cpp @@ -2855,6 +2855,66 @@ TEST_F(TokenAnnotatorTest, BraceKind) { ASSERT_EQ(Tokens.size(), 18u) << Tokens; EXPECT_BRACE_KIND(Tokens[8], BK_BracedInit); EXPECT_BRACE_KIND(Tokens[16], BK_BracedInit); + + Tokens = annotate("struct {};"); + ASSERT_EQ(Tokens.size(), 5u) << Tokens; + EXPECT_BRACE_KIND(Tokens[1], BK_Block); + EXPECT_BRACE_KIND(Tokens[2], BK_Block); + + Tokens = annotate("struct : Base {};"); + ASSERT_EQ(Tokens.size(), 7u) << Tokens; + EXPECT_BRACE_KIND(Tokens[3], BK_Block); + EXPECT_BRACE_KIND(Tokens[4], BK_Block); + + Tokens = annotate("struct Foo {};"); + ASSERT_EQ(Tokens.size(), 6u) << Tokens; + EXPECT_BRACE_KIND(Tokens[2], BK_Block); + EXPECT_BRACE_KIND(Tokens[3], BK_Block); + + Tokens = annotate("struct ::Foo {};"); + ASSERT_EQ(Tokens.size(), 7u) << Tokens; + EXPECT_BRACE_KIND(Tokens[3], BK_Block); + EXPECT_BRACE_KIND(Tokens[4], BK_Block); + + Tokens = annotate("struct NS::Foo {};"); + ASSERT_EQ(Tokens.size(), 8u) << Tokens; + EXPECT_BRACE_KIND(Tokens[4], BK_Block); + EXPECT_BRACE_KIND(Tokens[5], BK_Block); + + Tokens = annotate("struct Foo {};"); + ASSERT_EQ(Tokens.size(), 9u) << Tokens; + EXPECT_BRACE_KIND(Tokens[5], BK_Block); + EXPECT_BRACE_KIND(Tokens[6], BK_Block); + + Tokens = annotate("struct Foo final {};"); + ASSERT_EQ(Tokens.size(), 7u) << Tokens; + EXPECT_BRACE_KIND(Tokens[3], BK_Block); + EXPECT_BRACE_KIND(Tokens[4], BK_Block); + + Tokens = annotate("struct [[foo]] [[bar]] Foo final : Base1, Base2 {};"); + ASSERT_EQ(Tokens.size(), 21u) << Tokens; + EXPECT_BRACE_KIND(Tokens[17], BK_Block); + EXPECT_BRACE_KIND(Tokens[18], BK_Block); + + Tokens = annotate("struct Foo x{};"); + ASSERT_EQ(Tokens.size(), 7u) << Tokens; + EXPECT_BRACE_KIND(Tokens[3], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[4], BK_BracedInit); + + Tokens = annotate("struct ::Foo x{};"); + ASSERT_EQ(Tokens.size(), 8u) << Tokens; + EXPECT_BRACE_KIND(Tokens[4], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[5], BK_BracedInit); + + Tokens = annotate("struct NS::Foo x{};"); + ASSERT_EQ(Tokens.size(), 9u) << Tokens; + EXPECT_BRACE_KIND(Tokens[5], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[6], BK_BracedInit); + + Tokens = annotate("struct Foo x{};"); + ASSERT_EQ(Tokens.size(), 10u) << Tokens; + EXPECT_BRACE_KIND(Tokens[6], BK_BracedInit); + EXPECT_BRACE_KIND(Tokens[7], BK_BracedInit); } TEST_F(TokenAnnotatorTest, UnderstandsElaboratedTypeSpecifier) { diff --git a/clang/unittests/libclang/LibclangTest.cpp b/clang/unittests/libclang/LibclangTest.cpp index 87075a46d75187b0d8a1e2c3fa4be877a93f00ae..6de4d02bf74f4ffc5c983ae69f1a340bf4d40540 100644 --- a/clang/unittests/libclang/LibclangTest.cpp +++ b/clang/unittests/libclang/LibclangTest.cpp @@ -1292,6 +1292,37 @@ void func() {} EXPECT_EQ(attrCount, 1); } +TEST_F(LibclangParseTest, clang_getSpellingLocation) { + std::string fileName = "main.c"; + WriteFile(fileName, "#define X(value) int x = value;\nX(42)\n"); + + ClangTU = clang_parseTranslationUnit(Index, fileName.c_str(), nullptr, 0, + nullptr, 0, TUFlags); + + int declarationCount = 0; + Traverse([&declarationCount](CXCursor cursor, + CXCursor parent) -> CXChildVisitResult { + if (cursor.kind == CXCursor_VarDecl) { + declarationCount++; + + CXSourceLocation cxl = clang_getCursorLocation(cursor); + unsigned line; + + // We expect clang_getFileLocation to return the expansion location, + // whereas clang_getSpellingLocation should resolve the macro expansion + // and return the location of the macro definition. + clang_getFileLocation(cxl, nullptr, &line, nullptr, nullptr); + EXPECT_EQ(line, 2U); + clang_getSpellingLocation(cxl, nullptr, &line, nullptr, nullptr); + EXPECT_EQ(line, 1U); + } + + return CXChildVisit_Recurse; + }); + + EXPECT_EQ(declarationCount, 1); +} + class LibclangRewriteTest : public LibclangParseTest { public: CXRewriter Rew = nullptr; diff --git a/clang/utils/TableGen/RISCVVEmitter.cpp b/clang/utils/TableGen/RISCVVEmitter.cpp index 5e41ef9f9d2684037988014b79d87755847959d7..48cd83cabfc7d032bb207243fabe8ee2bfeef513 100644 --- a/clang/utils/TableGen/RISCVVEmitter.cpp +++ b/clang/utils/TableGen/RISCVVEmitter.cpp @@ -670,6 +670,7 @@ void RVVEmitter::createRVVIntrinsics( .Case("Zvksed", RVV_REQ_Zvksed) .Case("Zvksh", RVV_REQ_Zvksh) .Case("Zvfbfwma", RVV_REQ_Zvfbfwma) + .Case("Zvfbfmin", RVV_REQ_Zvfbfmin) .Case("Experimental", RVV_REQ_Experimental) .Default(RVV_REQ_None); assert(RequireExt != RVV_REQ_None && "Unrecognized required feature?"); diff --git a/compiler-rt/lib/fuzzer/build.sh b/compiler-rt/lib/fuzzer/build.sh index f7f329c0d19c765ca898338abe4dbd0c3153c013..f58fd9557ce3d5c0a670d88c54911f08f51efa03 100755 --- a/compiler-rt/lib/fuzzer/build.sh +++ b/compiler-rt/lib/fuzzer/build.sh @@ -2,7 +2,7 @@ LIBFUZZER_SRC_DIR=$(dirname $0) CXX="${CXX:-clang}" for f in $LIBFUZZER_SRC_DIR/*.cpp; do - $CXX -g -O2 -fno-omit-frame-pointer -std=c++14 $f -c & + $CXX -g -O2 -fno-omit-frame-pointer -std=c++17 $f -c & done wait rm -f libFuzzer.a diff --git a/compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp b/compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp index 28e5a11a37f257318fc4fad94d0add526f3c1338..5f3c8b81c07b31266ecc84533322b5608220db10 100644 --- a/compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp +++ b/compiler-rt/lib/scudo/standalone/mem_map_fuchsia.cpp @@ -84,6 +84,13 @@ static zx_handle_t getPlaceholderVmo() { return Vmo; } +// Checks if MAP_ALLOWNOMEM allows the given error code. +static bool IsNoMemError(zx_status_t Status) { + // Note: _zx_vmar_map returns ZX_ERR_NO_RESOURCES if the VMAR does not contain + // a suitable free spot. + return Status == ZX_ERR_NO_MEMORY || Status == ZX_ERR_NO_RESOURCES; +} + MemMapFuchsia::MemMapFuchsia(uptr Base, uptr Capacity) : MapAddr(Base), WindowBase(Base), WindowSize(Capacity) { // Create the VMO. @@ -101,7 +108,7 @@ bool MemMapFuchsia::mapImpl(UNUSED uptr Addr, uptr Size, const char *Name, // Create the VMO. zx_status_t Status = _zx_vmo_create(Size, 0, &Vmo); if (UNLIKELY(Status != ZX_OK)) { - if (Status != ZX_ERR_NO_MEMORY || !AllowNoMem) + if (!IsNoMemError(Status) || !AllowNoMem) dieOnError(Status, "zx_vmo_create", Size); return false; } @@ -116,7 +123,7 @@ bool MemMapFuchsia::mapImpl(UNUSED uptr Addr, uptr Size, const char *Name, Status = _zx_vmar_map(_zx_vmar_root_self(), MapFlags, 0, Vmo, 0, Size, &MapAddr); if (UNLIKELY(Status != ZX_OK)) { - if (Status != ZX_ERR_NO_MEMORY || !AllowNoMem) + if (!IsNoMemError(Status) || !AllowNoMem) dieOnError(Status, "zx_vmar_map", Size); Status = _zx_handle_close(Vmo); @@ -187,7 +194,7 @@ bool MemMapFuchsia::remapImpl(uptr Addr, uptr Size, const char *Name, _zx_vmar_map(_zx_vmar_root_self(), MapFlags, Addr - getRootVmarBase(), Vmo, Addr - MapAddr, Size, &MappedAddr); if (UNLIKELY(Status != ZX_OK)) { - if (Status != ZX_ERR_NO_MEMORY || !AllowNoMem) + if (!IsNoMemError(Status) || !AllowNoMem) dieOnError(Status, "zx_vmar_map", Size); return false; } @@ -227,7 +234,7 @@ bool ReservedMemoryFuchsia::createImpl(UNUSED uptr Addr, uptr Size, zx_status_t Status = _zx_vmar_map(_zx_vmar_root_self(), ZX_VM_ALLOW_FAULTS, 0, getPlaceholderVmo(), 0, Size, &Base); if (UNLIKELY(Status != ZX_OK)) { - if (Status != ZX_ERR_NO_MEMORY || !AllowNoMem) + if (!IsNoMemError(Status) || !AllowNoMem) dieOnError(Status, "zx_vmar_map", Size); return false; } diff --git a/compiler-rt/test/CMakeLists.txt b/compiler-rt/test/CMakeLists.txt index edc007aaf477a74ac58e9585d9ee680e43b0d5f4..8805cc8f798f18bd4113cd11722be0e278ddc927 100644 --- a/compiler-rt/test/CMakeLists.txt +++ b/compiler-rt/test/CMakeLists.txt @@ -92,6 +92,9 @@ if(COMPILER_RT_CAN_EXECUTE_TESTS) if(COMPILER_RT_BUILD_PROFILE AND COMPILER_RT_HAS_PROFILE) compiler_rt_test_runtime(profile) endif() + if(COMPILER_RT_BUILD_CTX_PROFILE) + compiler_rt_test_runtime(ctx_profile) + endif() if(COMPILER_RT_BUILD_MEMPROF) compiler_rt_test_runtime(memprof) endif() diff --git a/compiler-rt/test/ctx_profile/CMakeLists.txt b/compiler-rt/test/ctx_profile/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..23c6fb16ed1f40e4f559322613a0d2260b7afd22 --- /dev/null +++ b/compiler-rt/test/ctx_profile/CMakeLists.txt @@ -0,0 +1,21 @@ +set(CTX_PROFILE_LIT_SOURCE_DIR ${CMAKE_CURRENT_SOURCE_DIR}) + +set(CTX_PROFILE_TESTSUITES) + +# Add unit tests. +if(COMPILER_RT_INCLUDE_TESTS) + foreach(arch ${CTX_PROFILE_SUPPORTED_ARCH}) + string(TOUPPER ${arch} ARCH_UPPER_CASE) + set(CONFIG_NAME ${ARCH_UPPER_CASE}${OS_NAME}Config) + configure_lit_site_cfg( + ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.py.in + ${CMAKE_CURRENT_BINARY_DIR}/Unit/${CONFIG_NAME}/lit.site.cfg.py) + list(APPEND CTX_PROFILE_TEST_DEPS CtxProfileUnitTests) + list(APPEND CTX_PROFILE_TESTSUITES ${CMAKE_CURRENT_BINARY_DIR}/Unit/${CONFIG_NAME}) + endforeach() +endif() + +add_lit_testsuite(check-ctx_profile "Running the Contextual Profiler tests" + ${CTX_PROFILE_TESTSUITES} + DEPENDS ${CTX_PROFILE_TEST_DEPS}) +set_target_properties(check-ctx_profile PROPERTIES FOLDER "Compiler-RT Misc") diff --git a/compiler-rt/test/ctx_profile/Unit/lit.site.cfg.py.in b/compiler-rt/test/ctx_profile/Unit/lit.site.cfg.py.in new file mode 100644 index 0000000000000000000000000000000000000000..32a8c48e9c1c797bbf74f1daed4ca6a522e39e30 --- /dev/null +++ b/compiler-rt/test/ctx_profile/Unit/lit.site.cfg.py.in @@ -0,0 +1,27 @@ +@LIT_SITE_CFG_IN_HEADER@ + +import os +import platform +import re +import shlex + +# Load common config for all compiler-rt unit tests. +lit_config.load_config(config, "@COMPILER_RT_BINARY_DIR@/unittests/lit.common.unit.configured") + +# Setup config name. +config.name = 'CtxProfile-Unit' +config.target_arch = "@arch@" +assert config.target_arch == 'x86_64' + +config.test_exec_root = os.path.join("@COMPILER_RT_BINARY_DIR@", + "lib", "ctx_profile", "tests") + +config.test_source_root = config.test_exec_root + +# When LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=on, the initial value of +# config.compiler_rt_libdir (COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR) has the +# host triple as the trailing path component. The value is incorrect for i386 +# tests on x86_64 hosts and vice versa. But, since only x86_64 is enabled as +# target, and we don't support different environments for building and, +# respectivelly, running tests, we shouldn't see this case. +assert not config.enable_per_target_runtime_dir or config.target_arch == config.host_arch diff --git a/compiler-rt/test/memprof/CMakeLists.txt b/compiler-rt/test/memprof/CMakeLists.txt index 3f0ba3812485d2042a942937e5e4737c8732abe0..fa6a4cd5f0b76ab6121d8303716163183f5ef9eb 100644 --- a/compiler-rt/test/memprof/CMakeLists.txt +++ b/compiler-rt/test/memprof/CMakeLists.txt @@ -43,6 +43,19 @@ foreach(arch ${MEMPROF_TEST_ARCH}) ${CMAKE_CURRENT_BINARY_DIR}/${CONFIG_NAME}) endforeach() +# Add unit tests. +if(COMPILER_RT_INCLUDE_TESTS) + foreach(arch ${MEMPROF_TEST_ARCH}) + string(TOUPPER ${arch} ARCH_UPPER_CASE) + set(CONFIG_NAME ${ARCH_UPPER_CASE}${OS_NAME}Config) + configure_lit_site_cfg( + ${CMAKE_CURRENT_SOURCE_DIR}/Unit/lit.site.cfg.py.in + ${CMAKE_CURRENT_BINARY_DIR}/Unit/${CONFIG_NAME}/lit.site.cfg.py) + list(APPEND MEMPROF_TEST_DEPS MemProfUnitTests) + list(APPEND MEMPROF_TESTSUITES ${CMAKE_CURRENT_BINARY_DIR}/Unit/${CONFIG_NAME}) + endforeach() +endif() + add_lit_testsuite(check-memprof "Running the MemProfiler tests" ${MEMPROF_TESTSUITES} DEPENDS ${MEMPROF_TEST_DEPS}) diff --git a/compiler-rt/test/memprof/Unit/lit.site.cfg.py.in b/compiler-rt/test/memprof/Unit/lit.site.cfg.py.in new file mode 100644 index 0000000000000000000000000000000000000000..c968e403a44d09e77bb56b585a902c0bf7c7e64b --- /dev/null +++ b/compiler-rt/test/memprof/Unit/lit.site.cfg.py.in @@ -0,0 +1,30 @@ +@LIT_SITE_CFG_IN_HEADER@ + +import os +import platform +import re +import shlex + +# Load common config for all compiler-rt unit tests. +lit_config.load_config(config, "@COMPILER_RT_BINARY_DIR@/unittests/lit.common.unit.configured") + +# Setup config name. +config.name = 'MemProfiler-Unit' +config.target_arch = "@arch@" +assert config.target_arch == 'x86_64' + +config.test_exec_root = os.path.join("@COMPILER_RT_BINARY_DIR@", + "lib", "memprof", "tests") + +config.test_source_root = config.test_exec_root + +# When LLVM_ENABLE_PER_TARGET_RUNTIME_DIR=on, the initial value of +# config.compiler_rt_libdir (COMPILER_RT_RESOLVED_LIBRARY_OUTPUT_DIR) has the +# host triple as the trailing path component. The value is incorrect for i386 +# tests on x86_64 hosts and vice versa. But, since only x86_64 is enabled as +# target, and we don't support different environments for building and, +# respectivelly, running tests, we shouldn't see this case. +assert not config.enable_per_target_runtime_dir or config.target_arch == config.host_arch + +if not config.parallelism_group: + config.parallelism_group = 'shadow-memory' \ No newline at end of file diff --git a/flang/docs/Preprocessing.md b/flang/docs/Preprocessing.md index 3c523472f39bd018e5516b43f7acc0dcabedc2bc..0b70d857833cef03d2ba8aed0d00311d6e778f9a 100644 --- a/flang/docs/Preprocessing.md +++ b/flang/docs/Preprocessing.md @@ -93,6 +93,9 @@ local: * If a `#define` or `#undef` directive appears among continuation lines, it may or may not affect text in the continued statement that appeared before the directive. +* A backslash at the end of a free form source line is a continuation + marker, with no space skipping or special handling of a leading `&` + on the next line. ## Behavior that few compilers properly support (or none), but should: diff --git a/flang/include/flang/Lower/Allocatable.h b/flang/include/flang/Lower/Allocatable.h index d3c16de377c1d7a8c1a6581bfe683f270c7e23d0..e8738f0407e77ffe3f4f1ed6632074e38614015d 100644 --- a/flang/include/flang/Lower/Allocatable.h +++ b/flang/include/flang/Lower/Allocatable.h @@ -55,12 +55,14 @@ void genDeallocateStmt(AbstractConverter &converter, void genDeallocateBox(AbstractConverter &converter, const fir::MutableBoxValue &box, mlir::Location loc, + const Fortran::semantics::Symbol *sym = nullptr, mlir::Value declaredTypeDesc = {}); /// Deallocate an allocatable if it is allocated at the end of its lifetime. void genDeallocateIfAllocated(AbstractConverter &converter, const fir::MutableBoxValue &box, - mlir::Location loc); + mlir::Location loc, + const Fortran::semantics::Symbol *sym = nullptr); /// Create a MutableBoxValue for an allocatable or pointer entity. /// If the variables is a local variable that is not a dummy, it will be diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index 6927488517e63b8775354ad117dd9982e0856219..604f2bd969eed51a7331fccb7887bd3443a04d25 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -335,6 +335,8 @@ struct IntrinsicLibrary { mlir::Value genSelectedRealKind(mlir::Type, llvm::ArrayRef); mlir::Value genSetExponent(mlir::Type resultType, llvm::ArrayRef args); + fir::ExtendedValue genShape(mlir::Type resultType, + llvm::ArrayRef); template mlir::Value genShift(mlir::Type resultType, llvm::ArrayRef); mlir::Value genShiftA(mlir::Type resultType, llvm::ArrayRef); diff --git a/flang/include/flang/Optimizer/Transforms/Passes.h b/flang/include/flang/Optimizer/Transforms/Passes.h index 402a7a3f875299f0b7d1af447b97ace14a70730d..402f212387e41d77009b3b3aa178ef31beb375a6 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.h +++ b/flang/include/flang/Optimizer/Transforms/Passes.h @@ -37,8 +37,7 @@ namespace fir { #define GEN_PASS_DECL_ANNOTATECONSTANTOPERANDS #define GEN_PASS_DECL_ARRAYVALUECOPY #define GEN_PASS_DECL_CHARACTERCONVERSION -#define GEN_PASS_DECL_CFGCONVERSIONONFUNC -#define GEN_PASS_DECL_CFGCONVERSIONONREDUCTION +#define GEN_PASS_DECL_CFGCONVERSION #define GEN_PASS_DECL_EXTERNALNAMECONVERSION #define GEN_PASS_DECL_MEMREFDATAFLOWOPT #define GEN_PASS_DECL_SIMPLIFYINTRINSICS @@ -53,8 +52,6 @@ namespace fir { std::unique_ptr createAffineDemotionPass(); std::unique_ptr createArrayValueCopyPass(fir::ArrayValueCopyOptions options = {}); -std::unique_ptr createFirToCfgOnFuncPass(); -std::unique_ptr createFirToCfgOnReductionPass(); std::unique_ptr createCharacterConversionPass(); std::unique_ptr createExternalNameConversionPass(); std::unique_ptr diff --git a/flang/include/flang/Optimizer/Transforms/Passes.td b/flang/include/flang/Optimizer/Transforms/Passes.td index c0b32459a935069c15aa271eaed26c232ccf3cc1..88e4321e5b2bcb1d583a51f23e8254173b079487 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.td +++ b/flang/include/flang/Optimizer/Transforms/Passes.td @@ -137,8 +137,7 @@ def CharacterConversion : Pass<"character-conversion"> { ]; } -class CFGConversionBase - : Pass<"cfg-conversion-on-" # optExt # "-opt", operation> { +def CFGConversion : Pass<"cfg-conversion"> { let summary = "Convert FIR structured control flow ops to CFG ops."; let description = [{ Transform the `fir.do_loop`, `fir.if`, `fir.iterate_while` and @@ -157,14 +156,6 @@ class CFGConversionBase ]; } -def CFGConversionOnFunc : CFGConversionBase<"func", "mlir::func::FuncOp"> { - let constructor = "::fir::createFirToCfgOnFuncPass()"; -} - -def CFGConversionOnReduction : CFGConversionBase<"reduce", "mlir::omp::DeclareReductionOp"> { - let constructor = "::fir::createFirToCfgOnReductionPass()"; -} - def ExternalNameConversion : Pass<"external-name-interop", "mlir::ModuleOp"> { let summary = "Convert name for external interoperability"; let description = [{ diff --git a/flang/include/flang/Parser/parse-tree.h b/flang/include/flang/Parser/parse-tree.h index d7c23755c57b2bdc76b4a01cac4f08f8a5d0e8ce..4641f9d20d5b9566dd97e6c43f7bc6e328fb156a 100644 --- a/flang/include/flang/Parser/parse-tree.h +++ b/flang/include/flang/Parser/parse-tree.h @@ -455,7 +455,8 @@ struct SpecificationPart { struct InternalSubprogram { UNION_CLASS_BOILERPLATE(InternalSubprogram); std::variant, - common::Indirection> + common::Indirection, + common::Indirection> u; }; diff --git a/flang/include/flang/Parser/preprocessor.h b/flang/include/flang/Parser/preprocessor.h index 630d5273d427c6e84dfaef7993ed407f968e00f5..c3076435be5f0bddfad89e76bad6e230087c3c5e 100644 --- a/flang/include/flang/Parser/preprocessor.h +++ b/flang/include/flang/Parser/preprocessor.h @@ -81,6 +81,7 @@ public: void Undefine(std::string macro); bool IsNameDefined(const CharBlock &); bool IsFunctionLikeDefinition(const CharBlock &); + bool AnyDefinitions() const { return !definitions_.empty(); } // When called with partialFunctionLikeMacro not null, MacroReplacement() // and ReplaceMacros() handle an unclosed function-like macro reference diff --git a/flang/include/flang/Runtime/numeric.h b/flang/include/flang/Runtime/numeric.h index 3d9cb8b5b0acdc0a7bff5b99c8ed15c40c96e0e6..7d3f91360c8cfb1dde466dfdc140b10f787ce017 100644 --- a/flang/include/flang/Runtime/numeric.h +++ b/flang/include/flang/Runtime/numeric.h @@ -356,10 +356,18 @@ CppTypeFor RTDECL(Scale16)( CppTypeFor, std::int64_t); #endif +// SELECTED_CHAR_KIND +CppTypeFor RTDECL(SelectedCharKind)( + const char *, int, const char *, std::size_t); + // SELECTED_INT_KIND CppTypeFor RTDECL(SelectedIntKind)( const char *, int, void *, int); +// SELECTED_LOGICAL_KIND +CppTypeFor RTDECL(SelectedLogicalKind)( + const char *, int, void *, int); + // SELECTED_REAL_KIND CppTypeFor RTDECL(SelectedRealKind)( const char *, int, void *, int, void *, int, void *, int); diff --git a/flang/include/flang/Tools/CLOptions.inc b/flang/include/flang/Tools/CLOptions.inc index f02c969ca1c314997757b8e059871a08f8e5ab83..a9d8ebc84e2e1089398bdf91610303c7111f4256 100644 --- a/flang/include/flang/Tools/CLOptions.inc +++ b/flang/include/flang/Tools/CLOptions.inc @@ -87,8 +87,6 @@ DisableOption(BoxedProcedureRewrite, "boxed-procedure-rewrite", DisableOption(ExternalNameConversion, "external-name-interop", "convert names with external convention"); -// TODO: remove once these are used for non-codegen passes -#if !defined(FLANG_EXCLUDE_CODEGEN) using PassConstructor = std::unique_ptr(); template @@ -108,7 +106,12 @@ void addNestedPassToAllTopLevelOperations( addNestedPassToOps(pm, ctor); } -#endif + +void addNestedPassToAllTopLevelOperationsConditionally(mlir::PassManager &pm, + llvm::cl::opt &disabled, PassConstructor ctor) { + if (!disabled) + addNestedPassToAllTopLevelOperations(pm, ctor); +} /// Generic for adding a pass to the pass manager if it is not disabled. template @@ -146,10 +149,8 @@ static void addCanonicalizerPassWithoutRegionSimplification( } inline void addCfgConversionPass(mlir::PassManager &pm) { - addNestedPassConditionally( - pm, disableCfgConversion, fir::createFirToCfgOnFuncPass); - addNestedPassConditionally( - pm, disableCfgConversion, fir::createFirToCfgOnReductionPass); + addNestedPassToAllTopLevelOperationsConditionally( + pm, disableCfgConversion, fir::createCFGConversion); } inline void addAVC( diff --git a/flang/lib/Evaluate/intrinsics.cpp b/flang/lib/Evaluate/intrinsics.cpp index f07f94b1a022c9f02db49c4b6be527690714694d..1b73cadb682d988278b5da7f8ef8b2e309632d66 100644 --- a/flang/lib/Evaluate/intrinsics.cpp +++ b/flang/lib/Evaluate/intrinsics.cpp @@ -777,7 +777,9 @@ static const IntrinsicInterface genericIntrinsicFunction[]{ {"identity", SameType, Rank::scalar, Optionality::optional}, {"ordered", AnyLogical, Rank::scalar, Optionality::optional}}, SameType, Rank::scalar, IntrinsicClass::transformationalFunction}, - {"repeat", {{"string", SameCharNoLen, Rank::scalar}, {"ncopies", AnyInt}}, + {"repeat", + {{"string", SameCharNoLen, Rank::scalar}, + {"ncopies", AnyInt, Rank::scalar}}, SameCharNoLen, Rank::scalar, IntrinsicClass::transformationalFunction}, {"reshape", {{"source", SameType, Rank::array}, {"shape", AnyInt, Rank::shape}, diff --git a/flang/lib/Evaluate/type.cpp b/flang/lib/Evaluate/type.cpp index a369e07f94a1fbebbbb62d2cf032cbb528c6c61d..ee1e5b398d9b02451ba3ceb409117c8678c8aff6 100644 --- a/flang/lib/Evaluate/type.cpp +++ b/flang/lib/Evaluate/type.cpp @@ -731,7 +731,7 @@ bool SomeKind::operator==( return PointeeComparison(derivedTypeSpec_, that.derivedTypeSpec_); } -int SelectedCharKind(const std::string &s, int defaultKind) { // 16.9.168 +int SelectedCharKind(const std::string &s, int defaultKind) { // F'2023 16.9.180 auto lower{parser::ToLowerCaseLetters(s)}; auto n{lower.size()}; while (n > 0 && lower[0] == ' ') { diff --git a/flang/lib/Frontend/FrontendActions.cpp b/flang/lib/Frontend/FrontendActions.cpp index d91846dde95a839bdc0501ad3498f358905bd52a..87a714d17015cbdbda2159f7fd69d6a2a79f44c8 100644 --- a/flang/lib/Frontend/FrontendActions.cpp +++ b/flang/lib/Frontend/FrontendActions.cpp @@ -63,10 +63,10 @@ #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/FileSystem.h" #include "llvm/Support/Path.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/SourceMgr.h" #include "llvm/Support/ToolOutputFile.h" #include "llvm/Target/TargetMachine.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/Transforms/Utils/ModuleUtils.h" #include diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index 38f61528d7e28add5a500e16dcdd25a954e5fd61..8e84ea2fc5d5223df3cb98b335b007bdeb9a37c0 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -859,18 +859,20 @@ genDeallocate(fir::FirOpBuilder &builder, void Fortran::lower::genDeallocateBox( Fortran::lower::AbstractConverter &converter, const fir::MutableBoxValue &box, mlir::Location loc, - mlir::Value declaredTypeDesc) { + const Fortran::semantics::Symbol *sym, mlir::Value declaredTypeDesc) { const Fortran::lower::SomeExpr *statExpr = nullptr; const Fortran::lower::SomeExpr *errMsgExpr = nullptr; ErrorManager errorManager; errorManager.init(converter, loc, statExpr, errMsgExpr); fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - genDeallocate(builder, converter, loc, box, errorManager, declaredTypeDesc); + genDeallocate(builder, converter, loc, box, errorManager, declaredTypeDesc, + sym); } void Fortran::lower::genDeallocateIfAllocated( Fortran::lower::AbstractConverter &converter, - const fir::MutableBoxValue &box, mlir::Location loc) { + const fir::MutableBoxValue &box, mlir::Location loc, + const Fortran::semantics::Symbol *sym) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Value isAllocated = fir::factory::genIsAllocatedOrAssociatedTest(builder, loc, box); @@ -880,9 +882,9 @@ void Fortran::lower::genDeallocateIfAllocated( eleType.isa() && box.isPolymorphic()) { mlir::Value declaredTypeDesc = builder.create( loc, mlir::TypeAttr::get(eleType)); - genDeallocateBox(converter, box, loc, declaredTypeDesc); + genDeallocateBox(converter, box, loc, sym, declaredTypeDesc); } else { - genDeallocateBox(converter, box, loc); + genDeallocateBox(converter, box, loc, sym); } }) .end(); diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index 2d2d9eba905bdd519f24e305e3b5edc34b1d3a35..21db0cac11bf6ac3cbacde79b3406d36ce414fb3 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -916,13 +916,14 @@ static void instantiateLocal(Fortran::lower::AbstractConverter &converter, break; case VariableCleanUp::Deallocate: auto *converterPtr = &converter; - converter.getFctCtx().attachCleanup([converterPtr, loc, exv]() { + auto *sym = &var.getSymbol(); + converter.getFctCtx().attachCleanup([converterPtr, loc, exv, sym]() { const fir::MutableBoxValue *mutableBox = exv.getBoxOf(); assert(mutableBox && "trying to deallocate entity not lowered as allocatable"); Fortran::lower::genDeallocateIfAllocated(*converterPtr, *mutableBox, - loc); + loc, sym); }); } } @@ -1715,7 +1716,8 @@ void Fortran::lower::genDeclareSymbol( const fir::ExtendedValue &exv, fir::FortranVariableFlagsEnum extraFlags, bool force) { if (converter.getLoweringOptions().getLowerToHighLevelFIR() && - !Fortran::semantics::IsProcedure(sym) && + (!Fortran::semantics::IsProcedure(sym) || + Fortran::semantics::IsPointer(sym)) && !sym.detailsIf()) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); const mlir::Location loc = genLocation(converter, sym); diff --git a/flang/lib/Lower/HostAssociations.cpp b/flang/lib/Lower/HostAssociations.cpp index 8eb548eb2bd5fe488900fcc4ea907eadd98b2da2..2e2656356719f80c4e15a86d92fd71c9a4bcd433 100644 --- a/flang/lib/Lower/HostAssociations.cpp +++ b/flang/lib/Lower/HostAssociations.cpp @@ -182,10 +182,10 @@ class CapturedProcedure : public CapturedSymbols { public: static mlir::Type getType(Fortran::lower::AbstractConverter &converter, const Fortran::semantics::Symbol &sym) { + mlir::Type funTy = Fortran::lower::getDummyProcedureType(sym, converter); if (Fortran::semantics::IsPointer(sym)) - TODO(converter.getCurrentLocation(), - "capture procedure pointer in internal procedure"); - return Fortran::lower::getDummyProcedureType(sym, converter); + return fir::ReferenceType::get(funTy); + return funTy; } static void instantiateHostTuple(const InstantiateHostTuple &args, diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index d933c07aba0e0c05c2392db9d8bbcd79e9e0d0dd..b56bdedc07bf53531d96b6f469b839240e4c7898 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -4187,21 +4187,27 @@ void Fortran::lower::attachDeclarePostDeallocAction( std::stringstream fctName; fctName << converter.mangleName(sym) << declarePostDeallocSuffix.str(); - mlir::Operation &op = builder.getInsertionBlock()->back(); - if (op.hasAttr(mlir::acc::getDeclareActionAttrName())) { - auto attr = op.getAttrOfType( + mlir::Operation *op = &builder.getInsertionBlock()->back(); + if (auto resOp = mlir::dyn_cast(*op)) { + assert(resOp.getOperands().size() == 0 && + "expect only fir.result op with no operand"); + op = op->getPrevNode(); + } + assert(op && "expect operation to attach the post deallocation action"); + if (op->hasAttr(mlir::acc::getDeclareActionAttrName())) { + auto attr = op->getAttrOfType( mlir::acc::getDeclareActionAttrName()); - op.setAttr(mlir::acc::getDeclareActionAttrName(), - mlir::acc::DeclareActionAttr::get( - builder.getContext(), attr.getPreAlloc(), - attr.getPostAlloc(), attr.getPreDealloc(), - /*postDealloc=*/builder.getSymbolRefAttr(fctName.str()))); + op->setAttr(mlir::acc::getDeclareActionAttrName(), + mlir::acc::DeclareActionAttr::get( + builder.getContext(), attr.getPreAlloc(), + attr.getPostAlloc(), attr.getPreDealloc(), + /*postDealloc=*/builder.getSymbolRefAttr(fctName.str()))); } else { - op.setAttr(mlir::acc::getDeclareActionAttrName(), - mlir::acc::DeclareActionAttr::get( - builder.getContext(), - /*preAlloc=*/{}, /*postAlloc=*/{}, /*preDealloc=*/{}, - /*postDealloc=*/builder.getSymbolRefAttr(fctName.str()))); + op->setAttr(mlir::acc::getDeclareActionAttrName(), + mlir::acc::DeclareActionAttr::get( + builder.getContext(), + /*preAlloc=*/{}, /*postAlloc=*/{}, /*preDealloc=*/{}, + /*postDealloc=*/builder.getSymbolRefAttr(fctName.str()))); } } diff --git a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp index 8bb2f83282b5565fd651f439f42f55b84443cd34..b419686e8ce467293f81609c16ebdb71e35dd24d 100644 --- a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp +++ b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp @@ -135,6 +135,12 @@ void DataSharingProcessor::insertBarrier() { } void DataSharingProcessor::insertLastPrivateCompare(mlir::Operation *op) { + mlir::omp::LoopNestOp loopOp; + if (auto wrapper = mlir::dyn_cast(op)) + loopOp = wrapper.isWrapper() + ? mlir::cast(wrapper.getWrappedLoop()) + : nullptr; + bool cmpCreated = false; mlir::OpBuilder::InsertionGuard guard(firOpBuilder); for (const omp::Clause &clause : clauses) { @@ -214,18 +220,20 @@ void DataSharingProcessor::insertLastPrivateCompare(mlir::Operation *op) { // Update the original variable just before exiting the worksharing // loop. Conversion as follows: // - // omp.wsloop { - // omp.wsloop { ... - // ... store - // store ===> %v = arith.addi %iv, %step - // omp.yield %cmp = %step < 0 ? %v < %ub : %v > %ub - // } fir.if %cmp { - // fir.store %v to %loopIV - // ^%lpv_update_blk: - // } - // omp.yield - // } - // + // omp.wsloop { omp.wsloop { + // omp.loop_nest { omp.loop_nest { + // ... ... + // store ===> store + // omp.yield %v = arith.addi %iv, %step + // } %cmp = %step < 0 ? %v < %ub : %v > %ub + // omp.terminator fir.if %cmp { + // } fir.store %v to %loopIV + // ^%lpv_update_blk: + // } + // omp.yield + // } + // omp.terminator + // } // Only generate the compare once in presence of multiple LastPrivate // clauses. @@ -233,14 +241,13 @@ void DataSharingProcessor::insertLastPrivateCompare(mlir::Operation *op) { continue; cmpCreated = true; - mlir::Location loc = op->getLoc(); - mlir::Operation *lastOper = op->getRegion(0).back().getTerminator(); + mlir::Location loc = loopOp.getLoc(); + mlir::Operation *lastOper = loopOp.getRegion().back().getTerminator(); firOpBuilder.setInsertionPoint(lastOper); - mlir::Value iv = op->getRegion(0).front().getArguments()[0]; - mlir::Value ub = - mlir::dyn_cast(op).getUpperBound()[0]; - mlir::Value step = mlir::dyn_cast(op).getStep()[0]; + mlir::Value iv = loopOp.getIVs()[0]; + mlir::Value ub = loopOp.getUpperBound()[0]; + mlir::Value step = loopOp.getStep()[0]; // v = iv + step // cmp = step < 0 ? v < ub : v > ub @@ -259,7 +266,7 @@ void DataSharingProcessor::insertLastPrivateCompare(mlir::Operation *op) { auto ifOp = firOpBuilder.create(loc, cmpOp, /*else*/ false); firOpBuilder.setInsertionPointToStart(&ifOp.getThenRegion().front()); assert(loopIV && "loopIV was not set"); - firOpBuilder.create(op->getLoc(), v, loopIV); + firOpBuilder.create(loopOp.getLoc(), v, loopIV); lastPrivIP = firOpBuilder.saveInsertionPoint(); } else { TODO(converter.getCurrentLocation(), diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index e932f7c284bca89fc60cc6ab0115ef687a8e5807..f454f5a45a5150ded64e8f351aa53027b350a55f 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -366,10 +366,29 @@ getDeclareTargetFunctionDevice( return std::nullopt; } -static llvm::SmallVector +/// Set up the entry block of the given `omp.loop_nest` operation, adding a +/// block argument for each loop induction variable and allocating and +/// initializing a private value to hold each of them. +/// +/// This function can also bind the symbols of any variables that should match +/// block arguments on parent loop wrapper operations attached to the same +/// loop. This allows the introduction of any necessary `hlfir.declare` +/// operations inside of the entry block of the `omp.loop_nest` operation and +/// not directly under any of the wrappers, which would invalidate them. +/// +/// \param [in] op - the loop nest operation. +/// \param [in] converter - PFT to MLIR conversion interface. +/// \param [in] loc - location. +/// \param [in] args - symbols of induction variables. +/// \param [in] wrapperSyms - symbols of variables to be mapped to loop wrapper +/// entry block arguments. +/// \param [in] wrapperArgs - entry block arguments of parent loop wrappers. +static void genLoopVars(mlir::Operation *op, Fortran::lower::AbstractConverter &converter, mlir::Location &loc, - llvm::ArrayRef args) { + llvm::ArrayRef args, + llvm::ArrayRef wrapperSyms = {}, + llvm::ArrayRef wrapperArgs = {}) { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); auto ®ion = op->getRegion(0); @@ -380,6 +399,12 @@ genLoopVars(mlir::Operation *op, Fortran::lower::AbstractConverter &converter, llvm::SmallVector tiv(args.size(), loopVarType); llvm::SmallVector locs(args.size(), loc); firOpBuilder.createBlock(®ion, {}, tiv, locs); + + // Bind the entry block arguments of parent wrappers to the corresponding + // symbols. + for (auto [arg, prv] : llvm::zip_equal(wrapperSyms, wrapperArgs)) + converter.bindSymbol(*arg, prv); + // The argument is not currently in memory, so make a temporary for the // argument, and store it there, then bind that location to the argument. mlir::Operation *storeOp = nullptr; @@ -389,7 +414,6 @@ genLoopVars(mlir::Operation *op, Fortran::lower::AbstractConverter &converter, createAndSetPrivatizedLoopVar(converter, loc, indexVal, argSymbol); } firOpBuilder.setInsertionPointAfter(storeOp); - return llvm::SmallVector(args); } static void genReductionVars( @@ -410,58 +434,6 @@ static void genReductionVars( } } -static llvm::SmallVector -genLoopAndReductionVars( - mlir::Operation *op, Fortran::lower::AbstractConverter &converter, - mlir::Location &loc, - llvm::ArrayRef loopArgs, - llvm::ArrayRef reductionArgs, - llvm::ArrayRef reductionTypes) { - fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); - - llvm::SmallVector blockArgTypes; - llvm::SmallVector blockArgLocs; - blockArgTypes.reserve(loopArgs.size() + reductionArgs.size()); - blockArgLocs.reserve(blockArgTypes.size()); - mlir::Block *entryBlock; - - if (loopArgs.size()) { - std::size_t loopVarTypeSize = 0; - for (const Fortran::semantics::Symbol *arg : loopArgs) - loopVarTypeSize = std::max(loopVarTypeSize, arg->GetUltimate().size()); - mlir::Type loopVarType = getLoopVarType(converter, loopVarTypeSize); - std::fill_n(std::back_inserter(blockArgTypes), loopArgs.size(), - loopVarType); - std::fill_n(std::back_inserter(blockArgLocs), loopArgs.size(), loc); - } - if (reductionArgs.size()) { - llvm::copy(reductionTypes, std::back_inserter(blockArgTypes)); - std::fill_n(std::back_inserter(blockArgLocs), reductionArgs.size(), loc); - } - entryBlock = firOpBuilder.createBlock(&op->getRegion(0), {}, blockArgTypes, - blockArgLocs); - // The argument is not currently in memory, so make a temporary for the - // argument, and store it there, then bind that location to the argument. - if (loopArgs.size()) { - mlir::Operation *storeOp = nullptr; - for (auto [argIndex, argSymbol] : llvm::enumerate(loopArgs)) { - mlir::Value indexVal = - fir::getBase(op->getRegion(0).front().getArgument(argIndex)); - storeOp = - createAndSetPrivatizedLoopVar(converter, loc, indexVal, argSymbol); - } - firOpBuilder.setInsertionPointAfter(storeOp); - } - // Bind the reduction arguments to their block arguments - for (auto [arg, prv] : llvm::zip_equal( - reductionArgs, - llvm::drop_begin(entryBlock->getArguments(), loopArgs.size()))) { - converter.bindSymbol(*arg, prv); - } - - return llvm::SmallVector(loopArgs); -} - static void markDeclareTarget(mlir::Operation *op, Fortran::lower::AbstractConverter &converter, @@ -1270,20 +1242,16 @@ static void genTeamsClauses(Fortran::lower::AbstractConverter &converter, static void genWsloopClauses( Fortran::lower::AbstractConverter &converter, Fortran::semantics::SemanticsContext &semaCtx, - Fortran::lower::StatementContext &stmtCtx, - Fortran::lower::pft::Evaluation &eval, const List &clauses, + Fortran::lower::StatementContext &stmtCtx, const List &clauses, mlir::Location loc, mlir::omp::WsloopClauseOps &clauseOps, - llvm::SmallVectorImpl &iv, llvm::SmallVectorImpl &reductionTypes, llvm::SmallVectorImpl &reductionSyms) { fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); ClauseProcessor cp(converter, semaCtx, clauses); - cp.processCollapse(loc, eval, clauseOps, iv); cp.processNowait(clauseOps); cp.processOrdered(clauseOps); cp.processReduction(loc, clauseOps, &reductionTypes, &reductionSyms); cp.processSchedule(stmtCtx, clauseOps); - clauseOps.loopInclusiveAttr = firOpBuilder.getUnitAttr(); // TODO Support delayed privatization. if (ReductionProcessor::doReductionByRef(clauseOps.reductionVars)) @@ -1526,7 +1494,8 @@ genSimdOp(Fortran::lower::AbstractConverter &converter, auto *nestedEval = getCollapsedLoopEval(eval, getCollapseValue(clauses)); auto ivCallback = [&](mlir::Operation *op) { - return genLoopVars(op, converter, loc, iv); + genLoopVars(op, converter, loc, iv); + return iv; }; createBodyOfOp(*loopOp, @@ -1801,32 +1770,48 @@ genWsloopOp(Fortran::lower::AbstractConverter &converter, Fortran::semantics::SemanticsContext &semaCtx, Fortran::lower::pft::Evaluation &eval, mlir::Location loc, const List &clauses) { + fir::FirOpBuilder &firOpBuilder = converter.getFirOpBuilder(); DataSharingProcessor dsp(converter, semaCtx, clauses, eval); dsp.processStep1(); Fortran::lower::StatementContext stmtCtx; - mlir::omp::WsloopClauseOps clauseOps; + mlir::omp::LoopNestClauseOps loopClauseOps; + mlir::omp::WsloopClauseOps wsClauseOps; llvm::SmallVector iv; llvm::SmallVector reductionTypes; llvm::SmallVector reductionSyms; - genWsloopClauses(converter, semaCtx, stmtCtx, eval, clauses, loc, clauseOps, - iv, reductionTypes, reductionSyms); + genLoopNestClauses(converter, semaCtx, eval, clauses, loc, loopClauseOps, iv); + genWsloopClauses(converter, semaCtx, stmtCtx, clauses, loc, wsClauseOps, + reductionTypes, reductionSyms); + + // Create omp.wsloop wrapper and populate entry block arguments with reduction + // variables. + auto wsloopOp = firOpBuilder.create(loc, wsClauseOps); + llvm::SmallVector reductionLocs(reductionSyms.size(), loc); + mlir::Block *wsloopEntryBlock = firOpBuilder.createBlock( + &wsloopOp.getRegion(), {}, reductionTypes, reductionLocs); + firOpBuilder.setInsertionPoint( + Fortran::lower::genOpenMPTerminator(firOpBuilder, wsloopOp, loc)); + + // Create nested omp.loop_nest and fill body with loop contents. + auto loopOp = firOpBuilder.create(loc, loopClauseOps); auto *nestedEval = getCollapsedLoopEval(eval, getCollapseValue(clauses)); auto ivCallback = [&](mlir::Operation *op) { - return genLoopAndReductionVars(op, converter, loc, iv, reductionSyms, - reductionTypes); + genLoopVars(op, converter, loc, iv, reductionSyms, + wsloopEntryBlock->getArguments()); + return iv; }; - return genOpWithBody( - OpWithBodyGenInfo(converter, semaCtx, loc, *nestedEval, - llvm::omp::Directive::OMPD_do) - .setClauses(&clauses) - .setDataSharingProcessor(&dsp) - .setReductions(&reductionSyms, &reductionTypes) - .setGenRegionEntryCb(ivCallback), - clauseOps); + createBodyOfOp(*loopOp, + OpWithBodyGenInfo(converter, semaCtx, loc, *nestedEval, + llvm::omp::Directive::OMPD_do) + .setClauses(&clauses) + .setDataSharingProcessor(&dsp) + .setReductions(&reductionSyms, &reductionTypes) + .setGenRegionEntryCb(ivCallback)); + return wsloopOp; } //===----------------------------------------------------------------------===// @@ -2482,8 +2467,8 @@ static void genOMP(Fortran::lower::AbstractConverter &converter, mlir::Operation *Fortran::lower::genOpenMPTerminator(fir::FirOpBuilder &builder, mlir::Operation *op, mlir::Location loc) { - if (mlir::isa(op)) + if (mlir::isa(op)) return builder.create(loc); return builder.create(loc); } diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp index 23fabaf34abac1d43cbe6ab13ad65bb2f66503de..895340549f7c67d33a1a093b235c3ec079f06d88 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp @@ -295,6 +295,33 @@ mlir::Value ReductionProcessor::createScalarCombiner( return reductionOp; } +/// Generate a fir::ShapeShift op describing the provided boxed array. +static fir::ShapeShiftOp getShapeShift(fir::FirOpBuilder &builder, + mlir::Location loc, mlir::Value box) { + fir::SequenceType sequenceType = mlir::cast( + hlfir::getFortranElementOrSequenceType(box.getType())); + const unsigned rank = sequenceType.getDimension(); + llvm::SmallVector lbAndExtents; + lbAndExtents.reserve(rank * 2); + + mlir::Type idxTy = builder.getIndexType(); + for (unsigned i = 0; i < rank; ++i) { + // TODO: ideally we want to hoist box reads out of the critical section. + // We could do this by having box dimensions in block arguments like + // OpenACC does + mlir::Value dim = builder.createIntegerConstant(loc, idxTy, i); + auto dimInfo = + builder.create(loc, idxTy, idxTy, idxTy, box, dim); + lbAndExtents.push_back(dimInfo.getLowerBound()); + lbAndExtents.push_back(dimInfo.getExtent()); + } + + auto shapeShiftTy = fir::ShapeShiftType::get(builder.getContext(), rank); + auto shapeShift = + builder.create(loc, shapeShiftTy, lbAndExtents); + return shapeShift; +} + /// Create reduction combiner region for reduction variables which are boxed /// arrays static void genBoxCombiner(fir::FirOpBuilder &builder, mlir::Location loc, @@ -330,29 +357,7 @@ static void genBoxCombiner(fir::FirOpBuilder &builder, mlir::Location loc, return; } - const unsigned rank = seqTy.getDimension(); - llvm::SmallVector extents; - extents.reserve(rank); - llvm::SmallVector lbAndExtents; - lbAndExtents.reserve(rank * 2); - - // Get box lowerbounds and extents: - mlir::Type idxTy = builder.getIndexType(); - for (unsigned i = 0; i < rank; ++i) { - // TODO: ideally we want to hoist box reads out of the critical section. - // We could do this by having box dimensions in block arguments like - // OpenACC does - mlir::Value dim = builder.createIntegerConstant(loc, idxTy, i); - auto dimInfo = - builder.create(loc, idxTy, idxTy, idxTy, lhs, dim); - extents.push_back(dimInfo.getExtent()); - lbAndExtents.push_back(dimInfo.getLowerBound()); - lbAndExtents.push_back(dimInfo.getExtent()); - } - - auto shapeShiftTy = fir::ShapeShiftType::get(builder.getContext(), rank); - auto shapeShift = - builder.create(loc, shapeShiftTy, lbAndExtents); + fir::ShapeShiftOp shapeShift = getShapeShift(builder, loc, lhs); // Iterate over array elements, applying the equivalent scalar reduction: @@ -364,8 +369,8 @@ static void genBoxCombiner(fir::FirOpBuilder &builder, mlir::Location loc, // loop nest directly. // This function already controls all of the code in this region so we // know this won't miss any opportuinties for clever elemental inlining - hlfir::LoopNest nest = - hlfir::genLoopNest(loc, builder, extents, /*isUnordered=*/true); + hlfir::LoopNest nest = hlfir::genLoopNest( + loc, builder, shapeShift.getExtents(), /*isUnordered=*/true); builder.setInsertionPointToStart(nest.innerLoop.getBody()); mlir::Type refTy = fir::ReferenceType::get(seqTy.getEleTy()); auto lhsEleAddr = builder.create( @@ -561,7 +566,8 @@ createReductionInitRegion(fir::FirOpBuilder &builder, mlir::Location loc, } // Create the private copy from the initial fir.box: - hlfir::Entity source = hlfir::Entity{blockArg}; + mlir::Value loadedBox = builder.loadIfRef(loc, blockArg); + hlfir::Entity source = hlfir::Entity{loadedBox}; // Allocating on the heap in case the whole reduction is nested inside of a // loop @@ -585,11 +591,23 @@ createReductionInitRegion(fir::FirOpBuilder &builder, mlir::Location loc, } // Put the temporary inside of a box: - hlfir::Entity box = hlfir::genVariableBox(loc, builder, temp); - // hlfir::genVariableBox removes fir.heap<> around the element type - mlir::Value convertedBox = builder.createConvert(loc, ty, box.getBase()); - builder.create(loc, initValue, convertedBox); - builder.create(loc, convertedBox, boxAlloca); + // hlfir::genVariableBox doesn't handle non-default lower bounds + mlir::Value box; + fir::ShapeShiftOp shapeShift = getShapeShift(builder, loc, loadedBox); + mlir::Type boxType = loadedBox.getType(); + if (mlir::isa(temp.getType())) + // the box created by the declare form createTempFromMold is missing lower + // bounds info + box = builder.create(loc, boxType, temp, shapeShift, + /*shift=*/mlir::Value{}); + else + box = builder.create( + loc, boxType, temp, shapeShift, + /*slice=*/mlir::Value{}, + /*typeParams=*/llvm::ArrayRef{}); + + builder.create(loc, initValue, box); + builder.create(loc, box, boxAlloca); if (ifUnallocated) builder.setInsertionPointAfter(ifUnallocated); return boxAlloca; diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index 4ee7258004fa74d7a6be6d59437d0f85b9959cc0..e28d14cd318d368a90dcc933efa49c4eed5b4033 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -554,6 +554,10 @@ static constexpr IntrinsicHandler handlers[]{ {"radix", asAddr, handleDynamicOptional}}}, /*isElemental=*/false}, {"set_exponent", &I::genSetExponent}, + {"shape", + &I::genShape, + {{{"source", asBox}, {"kind", asValue}}}, + /*isElemental=*/false}, {"shifta", &I::genShiftA}, {"shiftl", &I::genShift}, {"shiftr", &I::genShift}, @@ -5821,6 +5825,35 @@ mlir::Value IntrinsicLibrary::genSetExponent(mlir::Type resultType, fir::getBase(args[1]))); } +// SHAPE +fir::ExtendedValue +IntrinsicLibrary::genShape(mlir::Type resultType, + llvm::ArrayRef args) { + assert(args.size() >= 1); + const fir::ExtendedValue &array = args[0]; + int rank = array.rank(); + if (rank == 0) + TODO(loc, "shape intrinsic lowering with assumed-rank source"); + mlir::Type indexType = builder.getIndexType(); + mlir::Type extentType = fir::unwrapSequenceType(resultType); + mlir::Type seqType = fir::SequenceType::get( + {static_cast(rank)}, extentType); + mlir::Value shapeArray = builder.createTemporary(loc, seqType); + mlir::Type shapeAddrType = builder.getRefType(extentType); + for (int dim = 0; dim < rank; ++dim) { + mlir::Value extent = fir::factory::readExtent(builder, loc, array, dim); + extent = builder.createConvert(loc, extentType, extent); + auto index = builder.createIntegerConstant(loc, indexType, dim); + auto shapeAddr = builder.create(loc, shapeAddrType, + shapeArray, index); + builder.create(loc, extent, shapeAddr); + } + mlir::Value shapeArrayExtent = + builder.createIntegerConstant(loc, indexType, rank); + llvm::SmallVector extents{shapeArrayExtent}; + return fir::ArrayBoxValue{shapeArray, extents}; +} + // SHIFTL, SHIFTR template mlir::Value IntrinsicLibrary::genShift(mlir::Type resultType, diff --git a/flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp b/flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp index 45609a99995d0a03ed65550cbc9a708388cb9dc8..a62f6cde0e09b8a30271e9ebc607bcd8258c5067 100644 --- a/flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp +++ b/flang/lib/Optimizer/Transforms/ControlFlowConverter.cpp @@ -24,8 +24,7 @@ #include "llvm/Support/CommandLine.h" namespace fir { -#define GEN_PASS_DEF_CFGCONVERSIONONFUNC -#define GEN_PASS_DEF_CFGCONVERSIONONREDUCTION +#define GEN_PASS_DEF_CFGCONVERSION #include "flang/Optimizer/Transforms/Passes.h.inc" } // namespace fir @@ -309,9 +308,10 @@ public: }; /// Convert FIR structured control flow ops to CFG ops. -template class PassBase> -class CfgConversionTemplate : public PassBase { +class CfgConversion : public fir::impl::CFGConversionBase { public: + using CFGConversionBase::CFGConversionBase; + void runOnOperation() override { auto *context = &this->getContext(); mlir::RewritePatternSet patterns(context); @@ -333,14 +333,6 @@ public: } }; -class CfgConversionOnFunc - : public CfgConversionTemplate {}; - -class CfgConversionOnReduction - : public CfgConversionTemplate { -}; } // namespace /// Expose conversion rewriters to other passes @@ -349,13 +341,3 @@ void fir::populateCfgConversionRewrites(mlir::RewritePatternSet &patterns, patterns.insert( patterns.getContext(), forceLoopToExecuteOnce); } - -/// Convert FIR's structured control flow ops to CFG ops. This -/// conversion enables the `createLowerToCFGPass` to transform these to CFG -/// form. -std::unique_ptr fir::createFirToCfgOnFuncPass() { - return std::make_unique(); -} -std::unique_ptr fir::createFirToCfgOnReductionPass() { - return std::make_unique(); -} diff --git a/flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp b/flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp index 959099d039a5e60f4fbc76b160862355bc7449f0..005e84cb8e9f9a2a307094f4b54f58e62e04b422 100644 --- a/flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp +++ b/flang/lib/Optimizer/Transforms/OMPFunctionFiltering.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "flang/Optimizer/Dialect/FIRDialect.h" +#include "flang/Optimizer/Dialect/FIROpsSupport.h" #include "flang/Optimizer/Transforms/Passes.h" #include "mlir/Dialect/Func/IR/FuncOps.h" @@ -66,6 +67,16 @@ public: SymbolTable::UseRange funcUses = *funcOp.getSymbolUses(op); for (SymbolTable::SymbolUse use : funcUses) { Operation *callOp = use.getUser(); + if (auto internalFunc = mlir::dyn_cast(callOp)) { + // Do not delete internal procedures holding the symbol of their + // Fortran host procedure as attribute. + internalFunc->removeAttr(fir::getHostSymbolAttrName()); + // Set public visibility so that the function is not deleted by MLIR + // because unused. Changing it is OK here because the function will + // be deleted anyway in the second filtering phase. + internalFunc.setVisibility(mlir::SymbolTable::Visibility::Public); + continue; + } // If the callOp has users then replace them with Undef values. if (!callOp->use_empty()) { SmallVector undefResults; diff --git a/flang/lib/Parser/Fortran-parsers.cpp b/flang/lib/Parser/Fortran-parsers.cpp index 2bdb8e38db95da00dca0c50c0b7fd70d299f2c5d..ff01974b549a1ee9e3f9695f9de09eb1a3700799 100644 --- a/flang/lib/Parser/Fortran-parsers.cpp +++ b/flang/lib/Parser/Fortran-parsers.cpp @@ -123,7 +123,8 @@ TYPE_PARSER(first( TYPE_CONTEXT_PARSER("internal subprogram"_en_US, (construct(indirect(functionSubprogram)) || construct(indirect(subroutineSubprogram))) / - forceEndOfStmt) + forceEndOfStmt || + construct(indirect(compilerDirective))) // R511 internal-subprogram-part -> contains-stmt [internal-subprogram]... TYPE_CONTEXT_PARSER("internal subprogram part"_en_US, diff --git a/flang/lib/Parser/prescan.cpp b/flang/lib/Parser/prescan.cpp index 96db3955299f33d12c30ba4df4b6f297fb9f1d1d..2d46eae531b1861e1b4af62a5ca319b2edd28a29 100644 --- a/flang/lib/Parser/prescan.cpp +++ b/flang/lib/Parser/prescan.cpp @@ -29,15 +29,18 @@ Prescanner::Prescanner(Messages &messages, CookedSource &cooked, Preprocessor &preprocessor, common::LanguageFeatureControl lfc) : messages_{messages}, cooked_{cooked}, preprocessor_{preprocessor}, allSources_{preprocessor_.allSources()}, features_{lfc}, + backslashFreeFormContinuation_{preprocessor.AnyDefinitions()}, encoding_{allSources_.encoding()} {} Prescanner::Prescanner(const Prescanner &that) : messages_{that.messages_}, cooked_{that.cooked_}, preprocessor_{that.preprocessor_}, allSources_{that.allSources_}, - features_{that.features_}, inFixedForm_{that.inFixedForm_}, + features_{that.features_}, + backslashFreeFormContinuation_{that.backslashFreeFormContinuation_}, + inFixedForm_{that.inFixedForm_}, fixedFormColumnLimit_{that.fixedFormColumnLimit_}, - encoding_{that.encoding_}, prescannerNesting_{that.prescannerNesting_ + - 1}, + encoding_{that.encoding_}, + prescannerNesting_{that.prescannerNesting_ + 1}, skipLeadingAmpersand_{that.skipLeadingAmpersand_}, compilerDirectiveBloomFilter_{that.compilerDirectiveBloomFilter_}, compilerDirectiveSentinels_{that.compilerDirectiveSentinels_} {} @@ -1226,9 +1229,14 @@ bool Prescanner::Continuation(bool mightNeedFixedFormSpace) { } else { return FreeFormContinuation(); } - } else { - return false; + } else if (*at_ == '\\' && at_ + 2 == nextLine_ && + backslashFreeFormContinuation_ && !inFixedForm_ && nextLine_ < limit_) { + // cpp-like handling of \ at end of a free form source line + BeginSourceLine(nextLine_); + NextLine(); + return true; } + return false; } std::optional diff --git a/flang/lib/Parser/prescan.h b/flang/lib/Parser/prescan.h index 581980001bcc23dca1eb2a9fa387043797d2e026..3ee4c5a2c69eaaf29b59ea9dc5aa9f36f266e085 100644 --- a/flang/lib/Parser/prescan.h +++ b/flang/lib/Parser/prescan.h @@ -197,6 +197,7 @@ private: Preprocessor &preprocessor_; AllSources &allSources_; common::LanguageFeatureControl features_; + bool backslashFreeFormContinuation_{false}; bool inFixedForm_{false}; int fixedFormColumnLimit_{72}; Encoding encoding_{Encoding::UTF_8}; diff --git a/flang/lib/Semantics/check-call.cpp b/flang/lib/Semantics/check-call.cpp index ce82cccf26d54684f16e28df5aff561015806d70..db0949e905a658349111ced89b837a6afa737e82 100644 --- a/flang/lib/Semantics/check-call.cpp +++ b/flang/lib/Semantics/check-call.cpp @@ -1929,6 +1929,7 @@ bool CheckArguments(const characteristics::Procedure &proc, bool explicitInterface{proc.HasExplicitInterface()}; evaluate::FoldingContext foldingContext{context.foldingContext()}; parser::ContextualMessages &messages{foldingContext.messages()}; + bool allowArgumentConversions{true}; if (!explicitInterface || treatingExternalAsImplicit) { parser::Messages buffer; { @@ -1945,11 +1946,12 @@ bool CheckArguments(const characteristics::Procedure &proc, } return false; // don't pile on } + allowArgumentConversions = false; } if (explicitInterface) { auto buffer{CheckExplicitInterface(proc, actuals, context, &scope, - intrinsic, /*allowArgumentConversions=*/true, /*extentErrors=*/true, - ignoreImplicitVsExplicit)}; + intrinsic, allowArgumentConversions, + /*extentErrors=*/true, ignoreImplicitVsExplicit)}; if (!buffer.empty()) { if (treatingExternalAsImplicit) { if (auto *msg{messages.Say( diff --git a/flang/lib/Semantics/expression.cpp b/flang/lib/Semantics/expression.cpp index a270e4b385e8dbe8b1f7e02350929d801930051f..b8396209fc68549f7b807b78709cd0589992400a 100644 --- a/flang/lib/Semantics/expression.cpp +++ b/flang/lib/Semantics/expression.cpp @@ -2989,8 +2989,8 @@ void ExpressionAnalyzer::Analyze(const parser::CallStmt &callStmt) { for (const auto &arg : actualArgList) { analyzer.Analyze(arg, true /* is subroutine call */); } - auto chevrons{AnalyzeChevrons(callStmt)}; - if (!analyzer.fatalErrors() && chevrons) { + if (auto chevrons{AnalyzeChevrons(callStmt)}; + chevrons && !analyzer.fatalErrors()) { if (std::optional callee{ GetCalleeAndArguments(std::get(call.t), analyzer.GetActuals(), true /* subroutine */)}) { diff --git a/flang/lib/Semantics/program-tree.cpp b/flang/lib/Semantics/program-tree.cpp index bf773f3810c847b129b49e6a68b18d8639c90c7d..13c85c17459e121a0baf5c58dff98114a8e51784 100644 --- a/flang/lib/Semantics/program-tree.cpp +++ b/flang/lib/Semantics/program-tree.cpp @@ -10,6 +10,7 @@ #include "flang/Common/idioms.h" #include "flang/Parser/char-block.h" #include "flang/Semantics/scope.h" +#include "flang/Semantics/semantics.h" namespace Fortran::semantics { @@ -76,7 +77,8 @@ static void GetGenerics( } template -static ProgramTree BuildSubprogramTree(const parser::Name &name, const T &x) { +static ProgramTree BuildSubprogramTree( + const parser::Name &name, SemanticsContext &context, const T &x) { const auto &spec{std::get(x.t)}; const auto &exec{std::get(x.t)}; const auto &subps{ @@ -89,7 +91,11 @@ static ProgramTree BuildSubprogramTree(const parser::Name &name, const T &x) { for (const auto &subp : std::get>(subps->t)) { common::visit( - [&](const auto &y) { node.AddChild(ProgramTree::Build(y.value())); }, + [&](const auto &y) { + if (auto child{ProgramTree::Build(y.value(), context)}) { + node.AddChild(std::move(*child)); + } + }, subp.u); } } @@ -97,13 +103,14 @@ static ProgramTree BuildSubprogramTree(const parser::Name &name, const T &x) { } static ProgramTree BuildSubprogramTree( - const parser::Name &name, const parser::BlockData &x) { + const parser::Name &name, SemanticsContext &, const parser::BlockData &x) { const auto &spec{std::get(x.t)}; return ProgramTree{name, spec}; } template -static ProgramTree BuildModuleTree(const parser::Name &name, const T &x) { +static ProgramTree BuildModuleTree( + const parser::Name &name, SemanticsContext &context, const T &x) { const auto &spec{std::get(x.t)}; const auto &subps{std::get>(x.t)}; ProgramTree node{name, spec}; @@ -112,28 +119,42 @@ static ProgramTree BuildModuleTree(const parser::Name &name, const T &x) { for (const auto &subp : std::get>(subps->t)) { common::visit( - [&](const auto &y) { node.AddChild(ProgramTree::Build(y.value())); }, + [&](const auto &y) { + if (auto child{ProgramTree::Build(y.value(), context)}) { + node.AddChild(std::move(*child)); + } + }, subp.u); } } return node; } -ProgramTree ProgramTree::Build(const parser::ProgramUnit &x) { - return common::visit([](const auto &y) { return Build(y.value()); }, x.u); +ProgramTree ProgramTree::Build( + const parser::ProgramUnit &x, SemanticsContext &context) { + return common::visit( + [&](const auto &y) { + auto node{Build(y.value(), context)}; + CHECK(node.has_value()); + return std::move(*node); + }, + x.u); } -ProgramTree ProgramTree::Build(const parser::MainProgram &x) { +std::optional ProgramTree::Build( + const parser::MainProgram &x, SemanticsContext &context) { const auto &stmt{ std::get>>(x.t)}; const auto &end{std::get>(x.t)}; static parser::Name emptyName; - auto result{stmt ? BuildSubprogramTree(stmt->statement.v, x).set_stmt(*stmt) - : BuildSubprogramTree(emptyName, x)}; - return result.set_endStmt(end); + auto result{stmt + ? BuildSubprogramTree(stmt->statement.v, context, x).set_stmt(*stmt) + : BuildSubprogramTree(emptyName, context, x)}; + return std::move(result.set_endStmt(end)); } -ProgramTree ProgramTree::Build(const parser::FunctionSubprogram &x) { +std::optional ProgramTree::Build( + const parser::FunctionSubprogram &x, SemanticsContext &context) { const auto &stmt{std::get>(x.t)}; const auto &end{std::get>(x.t)}; const auto &name{std::get(stmt.statement.t)}; @@ -144,13 +165,14 @@ ProgramTree ProgramTree::Build(const parser::FunctionSubprogram &x) { bindingSpec = &*suffix->binding; } } - return BuildSubprogramTree(name, x) + return BuildSubprogramTree(name, context, x) .set_stmt(stmt) .set_endStmt(end) .set_bindingSpec(bindingSpec); } -ProgramTree ProgramTree::Build(const parser::SubroutineSubprogram &x) { +std::optional ProgramTree::Build( + const parser::SubroutineSubprogram &x, SemanticsContext &context) { const auto &stmt{std::get>(x.t)}; const auto &end{std::get>(x.t)}; const auto &name{std::get(stmt.statement.t)}; @@ -159,48 +181,56 @@ ProgramTree ProgramTree::Build(const parser::SubroutineSubprogram &x) { stmt.statement.t)}) { bindingSpec = &*binding; } - return BuildSubprogramTree(name, x) + return BuildSubprogramTree(name, context, x) .set_stmt(stmt) .set_endStmt(end) .set_bindingSpec(bindingSpec); } -ProgramTree ProgramTree::Build(const parser::SeparateModuleSubprogram &x) { +std::optional ProgramTree::Build( + const parser::SeparateModuleSubprogram &x, SemanticsContext &context) { const auto &stmt{std::get>(x.t)}; const auto &end{ std::get>(x.t)}; const auto &name{stmt.statement.v}; - return BuildSubprogramTree(name, x).set_stmt(stmt).set_endStmt(end); + return BuildSubprogramTree(name, context, x).set_stmt(stmt).set_endStmt(end); } -ProgramTree ProgramTree::Build(const parser::Module &x) { +std::optional ProgramTree::Build( + const parser::Module &x, SemanticsContext &context) { const auto &stmt{std::get>(x.t)}; const auto &end{std::get>(x.t)}; const auto &name{stmt.statement.v}; - return BuildModuleTree(name, x).set_stmt(stmt).set_endStmt(end); + return BuildModuleTree(name, context, x).set_stmt(stmt).set_endStmt(end); } -ProgramTree ProgramTree::Build(const parser::Submodule &x) { +std::optional ProgramTree::Build( + const parser::Submodule &x, SemanticsContext &context) { const auto &stmt{std::get>(x.t)}; const auto &end{std::get>(x.t)}; const auto &name{std::get(stmt.statement.t)}; - return BuildModuleTree(name, x).set_stmt(stmt).set_endStmt(end); + return BuildModuleTree(name, context, x).set_stmt(stmt).set_endStmt(end); } -ProgramTree ProgramTree::Build(const parser::BlockData &x) { +std::optional ProgramTree::Build( + const parser::BlockData &x, SemanticsContext &context) { const auto &stmt{std::get>(x.t)}; const auto &end{std::get>(x.t)}; static parser::Name emptyName; - auto result{stmt.statement.v ? BuildSubprogramTree(*stmt.statement.v, x) - : BuildSubprogramTree(emptyName, x)}; - return result.set_stmt(stmt).set_endStmt(end); + auto result{stmt.statement.v + ? BuildSubprogramTree(*stmt.statement.v, context, x) + : BuildSubprogramTree(emptyName, context, x)}; + return std::move(result.set_stmt(stmt).set_endStmt(end)); } -ProgramTree ProgramTree::Build(const parser::CompilerDirective &) { - DIE("ProgramTree::Build() called for CompilerDirective"); +std::optional ProgramTree::Build( + const parser::CompilerDirective &x, SemanticsContext &context) { + context.Say(x.source, "Compiler directive ignored here"_warn_en_US); + return std::nullopt; } -ProgramTree ProgramTree::Build(const parser::OpenACCRoutineConstruct &) { +std::optional ProgramTree::Build( + const parser::OpenACCRoutineConstruct &, SemanticsContext &) { DIE("ProgramTree::Build() called for OpenACCRoutineConstruct"); } diff --git a/flang/lib/Semantics/program-tree.h b/flang/lib/Semantics/program-tree.h index d49b0405d8b122de9d88ba5e2c28f14451d595a1..ab00261a964a13c3e604b132528bc27be5be81fb 100644 --- a/flang/lib/Semantics/program-tree.h +++ b/flang/lib/Semantics/program-tree.h @@ -26,6 +26,7 @@ namespace Fortran::semantics { class Scope; +class SemanticsContext; class ProgramTree { public: @@ -34,16 +35,25 @@ public: std::list>; // Build the ProgramTree rooted at one of these program units. - static ProgramTree Build(const parser::ProgramUnit &); - static ProgramTree Build(const parser::MainProgram &); - static ProgramTree Build(const parser::FunctionSubprogram &); - static ProgramTree Build(const parser::SubroutineSubprogram &); - static ProgramTree Build(const parser::SeparateModuleSubprogram &); - static ProgramTree Build(const parser::Module &); - static ProgramTree Build(const parser::Submodule &); - static ProgramTree Build(const parser::BlockData &); - static ProgramTree Build(const parser::CompilerDirective &); - static ProgramTree Build(const parser::OpenACCRoutineConstruct &); + static ProgramTree Build(const parser::ProgramUnit &, SemanticsContext &); + static std::optional Build( + const parser::MainProgram &, SemanticsContext &); + static std::optional Build( + const parser::FunctionSubprogram &, SemanticsContext &); + static std::optional Build( + const parser::SubroutineSubprogram &, SemanticsContext &); + static std::optional Build( + const parser::SeparateModuleSubprogram &, SemanticsContext &); + static std::optional Build( + const parser::Module &, SemanticsContext &); + static std::optional Build( + const parser::Submodule &, SemanticsContext &); + static std::optional Build( + const parser::BlockData &, SemanticsContext &); + static std::optional Build( + const parser::CompilerDirective &, SemanticsContext &); + static std::optional Build( + const parser::OpenACCRoutineConstruct &, SemanticsContext &); ENUM_CLASS(Kind, // kind of node Program, Function, Subroutine, MpSubprogram, Module, Submodule, BlockData) diff --git a/flang/lib/Semantics/resolve-names.cpp b/flang/lib/Semantics/resolve-names.cpp index b941f257a95ea3d8f4903d5bfef37107231d175f..7bd1f4e4e9618566e4f889fe39142edd6f3a7fb7 100644 --- a/flang/lib/Semantics/resolve-names.cpp +++ b/flang/lib/Semantics/resolve-names.cpp @@ -1779,7 +1779,6 @@ void AttrsVisitor::SetBindNameOn(Symbol &symbol) { !symbol.attrs().test(Attr::BIND_C)) { return; } - std::optional label{ evaluate::GetScalarConstantValue(bindName_)}; // 18.9.2(2): discard leading and trailing blanks @@ -1798,16 +1797,18 @@ void AttrsVisitor::SetBindNameOn(Symbol &symbol) { } else { label = symbol.name().ToString(); } - // Check if a symbol has two Bind names. + // Checks whether a symbol has two Bind names. std::string oldBindName; - if (symbol.GetBindName()) { - oldBindName = *symbol.GetBindName(); + if (const auto *bindName{symbol.GetBindName()}) { + oldBindName = *bindName; } symbol.SetBindName(std::move(*label)); if (!oldBindName.empty()) { if (const std::string * newBindName{symbol.GetBindName()}) { if (oldBindName != *newBindName) { - Say(symbol.name(), "The entity '%s' has multiple BIND names"_err_en_US); + Say(symbol.name(), + "The entity '%s' has multiple BIND names ('%s' and '%s')"_err_en_US, + symbol.name(), oldBindName, *newBindName); } } } @@ -4986,7 +4987,9 @@ Symbol &DeclarationVisitor::DeclareUnknownEntity( if (symbol.attrs().test(Attr::EXTERNAL)) { ConvertToProcEntity(symbol); } - SetBindNameOn(symbol); + if (attrs.test(Attr::BIND_C)) { + SetBindNameOn(symbol); + } return symbol; } } @@ -8886,7 +8889,7 @@ void ResolveNamesVisitor::Post(const parser::CompilerDirective &x) { } } } else { - Say(x.source, "Compiler directive was ignored"_warn_en_US); + Say(x.source, "Unrecognized compiler directive was ignored"_warn_en_US); } } @@ -8901,7 +8904,7 @@ bool ResolveNamesVisitor::Pre(const parser::ProgramUnit &x) { ResolveAccParts(context(), x, &topScope_); return false; } - auto root{ProgramTree::Build(x)}; + auto root{ProgramTree::Build(x, context())}; SetScope(topScope_); ResolveSpecificationParts(root); FinishSpecificationParts(root); diff --git a/flang/runtime/edit-output.cpp b/flang/runtime/edit-output.cpp index a06ed258f0f1d2751f31f3d319f81944b15cda31..13ab91fc56eade41609ad11e6825cf031f3a9ccf 100644 --- a/flang/runtime/edit-output.cpp +++ b/flang/runtime/edit-output.cpp @@ -446,6 +446,7 @@ RT_API_ATTRS bool RealOutputEditing::EditFOutput(const DataEdit &edit) { fracDigits = sizeof buffer_ - 2; // sign & NUL } } + bool emitTrailingZeroes{!(flags & decimal::Minimize)}; // Multiple conversions may be needed to get the right number of // effective rounded fractional digits. bool canIncrease{true}; @@ -526,11 +527,18 @@ RT_API_ATTRS bool RealOutputEditing::EditFOutput(const DataEdit &edit) { } int digitsBeforePoint{std::max(0, std::min(expo, convertedDigits))}; int zeroesBeforePoint{std::max(0, expo - digitsBeforePoint)}; + if (zeroesBeforePoint > 0 && (flags & decimal::Minimize)) { + // If a minimized result looks like an integer, emit all of + // its digits rather than clipping some to zeroes. + // This can happen with HUGE(0._2) == 65504._2. + flags &= ~decimal::Minimize; + continue; + } int zeroesAfterPoint{std::min(fracDigits, std::max(0, -expo))}; int digitsAfterPoint{convertedDigits - digitsBeforePoint}; - int trailingZeroes{flags & decimal::Minimize - ? 0 - : std::max(0, fracDigits - (zeroesAfterPoint + digitsAfterPoint))}; + int trailingZeroes{emitTrailingZeroes + ? std::max(0, fracDigits - (zeroesAfterPoint + digitsAfterPoint)) + : 0}; if (digitsBeforePoint + zeroesBeforePoint + zeroesAfterPoint + digitsAfterPoint + trailingZeroes == 0) { @@ -822,6 +830,11 @@ RT_API_ATTRS bool EditLogicalOutput( case 'Z': return EditBOZOutput<4>(io, edit, reinterpret_cast(&truth), sizeof truth); + case 'A': { // legacy extension + int truthBits{truth}; + return EditCharacterOutput( + io, edit, reinterpret_cast(&truthBits), sizeof truthBits); + } default: io.GetIoErrorHandler().SignalError(IostatErrorInFormat, "Data edit descriptor '%c' may not be used with a LOGICAL data item", diff --git a/flang/runtime/numeric.cpp b/flang/runtime/numeric.cpp index abd3e500029fe49ab915b17e93f99d73f769ac0a..52b5a56894d8846587e40f3222298bda717f777f 100644 --- a/flang/runtime/numeric.cpp +++ b/flang/runtime/numeric.cpp @@ -9,6 +9,7 @@ #include "flang/Runtime/numeric.h" #include "numeric-templates.h" #include "terminator.h" +#include "tools.h" #include "flang/Common/float128.h" #include #include @@ -18,30 +19,30 @@ namespace Fortran::runtime { template -inline RT_API_ATTRS RES getIntArgValue(const char *source, int line, void *arg, - int kind, std::int64_t defaultValue, int resKind) { +inline RT_API_ATTRS RES GetIntArgValue(const char *source, int line, + const void *arg, int kind, std::int64_t defaultValue, int resKind) { RES res; if (!arg) { res = static_cast(defaultValue); } else if (kind == 1) { res = static_cast( - *static_cast *>(arg)); + *static_cast *>(arg)); } else if (kind == 2) { res = static_cast( - *static_cast *>(arg)); + *static_cast *>(arg)); } else if (kind == 4) { res = static_cast( - *static_cast *>(arg)); + *static_cast *>(arg)); } else if (kind == 8) { res = static_cast( - *static_cast *>(arg)); + *static_cast *>(arg)); #ifdef __SIZEOF_INT128__ } else if (kind == 16) { if (resKind != 16) { Terminator{source, line}.Crash("Unexpected integer kind in runtime"); } res = static_cast( - *static_cast *>(arg)); + *static_cast *>(arg)); #endif } else { Terminator{source, line}.Crash("Unexpected integer kind in runtime"); @@ -112,6 +113,22 @@ inline RT_API_ATTRS CppTypeFor SelectedIntKind(T x) { return -1; } +// SELECTED_LOGICAL_KIND (F'2023 16.9.182) +template +inline RT_API_ATTRS CppTypeFor SelectedLogicalKind( + T x) { + if (x <= 2) { + return 1; + } else if (x <= 4) { + return 2; + } else if (x <= 9) { + return 4; + } else if (x <= 18) { + return 8; + } + return -1; +} + // SELECTED_REAL_KIND (16.9.170) template inline RT_API_ATTRS CppTypeFor SelectedRealKind( @@ -717,40 +734,72 @@ CppTypeFor RTDEF(Scale10)( } #endif +// SELECTED_CHAR_KIND +CppTypeFor RTDEF(SelectedCharKind)( + const char *source, int line, const char *x, std::size_t length) { + static const char *keywords[]{ + "ASCII", "DEFAULT", "UCS-2", "ISO_10646", "UCS-4", nullptr}; + switch (IdentifyValue(x, length, keywords)) { + case 0: // ASCII + case 1: // DEFAULT + return 1; + case 2: // UCS-2 + return 2; + case 3: // ISO_10646 + case 4: // UCS-4 + return 4; + default: + return -1; + } +} // SELECTED_INT_KIND CppTypeFor RTDEF(SelectedIntKind)( const char *source, int line, void *x, int xKind) { #ifdef __SIZEOF_INT128__ CppTypeFor r = - getIntArgValue>( + GetIntArgValue>( source, line, x, xKind, /*defaultValue*/ 0, /*resKind*/ 16); #else - std::int64_t r = getIntArgValue( + std::int64_t r = GetIntArgValue( source, line, x, xKind, /*defaultValue*/ 0, /*resKind*/ 8); #endif return SelectedIntKind(r); } +// SELECTED_LOGICAL_KIND +CppTypeFor RTDEF(SelectedLogicalKind)( + const char *source, int line, void *x, int xKind) { +#ifdef __SIZEOF_INT128__ + CppTypeFor r = + GetIntArgValue>( + source, line, x, xKind, /*defaultValue*/ 0, /*resKind*/ 16); +#else + std::int64_t r = GetIntArgValue( + source, line, x, xKind, /*defaultValue*/ 0, /*resKind*/ 8); +#endif + return SelectedLogicalKind(r); +} + // SELECTED_REAL_KIND CppTypeFor RTDEF(SelectedRealKind)(const char *source, int line, void *precision, int pKind, void *range, int rKind, void *radix, int dKind) { #ifdef __SIZEOF_INT128__ CppTypeFor p = - getIntArgValue>( + GetIntArgValue>( source, line, precision, pKind, /*defaultValue*/ 0, /*resKind*/ 16); CppTypeFor r = - getIntArgValue>( + GetIntArgValue>( source, line, range, rKind, /*defaultValue*/ 0, /*resKind*/ 16); CppTypeFor d = - getIntArgValue>( + GetIntArgValue>( source, line, radix, dKind, /*defaultValue*/ 2, /*resKind*/ 16); #else - std::int64_t p = getIntArgValue( + std::int64_t p = GetIntArgValue( source, line, precision, pKind, /*defaultValue*/ 0, /*resKind*/ 8); - std::int64_t r = getIntArgValue( + std::int64_t r = GetIntArgValue( source, line, range, rKind, /*defaultValue*/ 0, /*resKind*/ 8); - std::int64_t d = getIntArgValue( + std::int64_t d = GetIntArgValue( source, line, radix, dKind, /*defaultValue*/ 2, /*resKind*/ 8); #endif return SelectedRealKind(p, r, d); diff --git a/flang/test/Driver/bbc-mlir-pass-pipeline.f90 b/flang/test/Driver/bbc-mlir-pass-pipeline.f90 index bd7facad1ce12fe6d00ca4f3db94894750981459..2ee832e3c57a6bf6f75900a3c8789543dca3b0f9 100644 --- a/flang/test/Driver/bbc-mlir-pass-pipeline.f90 +++ b/flang/test/Driver/bbc-mlir-pass-pipeline.f90 @@ -38,12 +38,14 @@ end program ! CHECK-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! CHECK-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! CHECK-NEXT: Pipeline Collection : ['func.func', 'omp.declare_reduction'] +! CHECK-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! CHECK-NEXT: 'fir.global' Pipeline +! CHECK-NEXT: CFGConversion ! CHECK-NEXT: 'func.func' Pipeline ! CHECK-NEXT: PolymorphicOpConversion -! CHECK-NEXT: CFGConversionOnFunc +! CHECK-NEXT: CFGConversion ! CHECK-NEXT: 'omp.declare_reduction' Pipeline -! CHECK-NEXT: CFGConversionOnReduction +! CHECK-NEXT: CFGConversion ! CHECK-NEXT: SCFToControlFlow ! CHECK-NEXT: Canonicalizer diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 deleted file mode 100644 index b5bb0f1c1b25604180097d7d44ddf4299c64257b..0000000000000000000000000000000000000000 --- a/flang/test/Driver/driver-help-hidden.f90 +++ /dev/null @@ -1,173 +0,0 @@ - -!-------------------------- -! FLANG DRIVER (flang-new) -!-------------------------- -! RUN: %flang --help-hidden 2>&1 | FileCheck %s -! RUN: not %flang -help-hidden 2>&1 | FileCheck %s --check-prefix=ERROR-FLANG - -!---------------------------------------- -! FLANG FRONTEND DRIVER (flang-new -fc1) -!---------------------------------------- -! RUN: not %flang_fc1 --help-hidden 2>&1 | FileCheck %s --check-prefix=ERROR-FLANG-FC1 -! RUN: not %flang_fc1 -help-hidden 2>&1 | FileCheck %s --check-prefix=ERROR-FLANG-FC1 - -! CHECK:USAGE: flang-new -! CHECK-EMPTY: -! CHECK-NEXT: DRIVER OPTIONS: -! CHECK-NEXT: --driver-mode= Set the driver mode to either 'gcc', 'g++', 'cpp', 'cl' or 'flang' -! CHECK-EMPTY: -! CHECK-NEXT:OPTIONS: -! CHECK-NEXT: -### Print (but do not run) the commands to run for this compilation -! CHECK-NEXT: -ccc-print-phases Dump list of actions to perform -! CHECK-NEXT: -cpp Enable predefined and command line preprocessor macros -! CHECK-NEXT: -c Only run preprocess, compile, and assemble steps -! CHECK-NEXT: -dM Print macro definitions in -E mode instead of normal output -! CHECK-NEXT: -dumpmachine Display the compiler's target processor -! CHECK-NEXT: -dumpversion Display the version of the compiler -! CHECK-NEXT: -D = Define to (or 1 if omitted) -! CHECK-NEXT: -emit-llvm Use the LLVM representation for assembler and object files -! CHECK-NEXT: -E Only run the preprocessor -! CHECK-NEXT: -falternative-parameter-statement -! CHECK-NEXT: Enable the old style PARAMETER statement -! CHECK-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation -! CHECK-NEXT: -fbackslash Specify that backslash in string introduces an escape character -! CHECK-NEXT: -fcolor-diagnostics Enable colors in diagnostics -! CHECK-NEXT: -fconvert= Set endian conversion of data for unformatted files -! CHECK-NEXT: -fdefault-double-8 Set the default double precision kind to an 8 byte wide type -! CHECK-NEXT: -fdefault-integer-8 Set the default integer and logical kind to an 8 byte wide type -! CHECK-NEXT: -fdefault-real-8 Set the default real kind to an 8 byte wide type -! CHECK-NEXT: -ffast-math Allow aggressive, lossy floating-point optimizations -! CHECK-NEXT: -ffixed-form Process source files in fixed form -! CHECK-NEXT: -ffixed-line-length= -! CHECK-NEXT: Use as character line width in fixed mode -! CHECK-NEXT: -ffp-contract= Form fused FP ops (e.g. FMAs) -! CHECK-NEXT: -ffree-form Process source files in free form -! CHECK-NEXT: -fhonor-infinities Specify that floating-point optimizations are not allowed that assume arguments and results are not +-inf. -! CHECK-NEXT: -fhonor-nans Specify that floating-point optimizations are not allowed that assume arguments and results are not NANs. -! CHECK-NEXT: -fimplicit-none No implicit typing allowed unless overridden by IMPLICIT statements -! CHECK-NEXT: -finput-charset= Specify the default character set for source files -! CHECK-NEXT: -fintegrated-as Enable the integrated assembler -! CHECK-NEXT: -fintrinsic-modules-path -! CHECK-NEXT: Specify where to find the compiled intrinsic modules -! CHECK-NEXT: -flang-deprecated-no-hlfir -! CHECK-NEXT: Do not use HLFIR lowering (deprecated) -! CHECK-NEXT: -flang-experimental-hlfir -! CHECK-NEXT: Use HLFIR lowering (experimental) -! CHECK-NEXT: -flarge-sizes Use INTEGER(KIND=8) for the result type in size-related intrinsics -! CHECK-NEXT: -flogical-abbreviations Enable logical abbreviations -! CHECK-NEXT: -flto=auto Enable LTO in 'full' mode -! CHECK-NEXT: -flto=jobserver Enable LTO in 'full' mode -! CHECK-NEXT: -flto= Set LTO mode -! CHECK-NEXT: -flto Enable LTO in 'full' mode -! CHECK-NEXT: -fms-runtime-lib= -! CHECK-NEXT: Select Windows run-time library -! CHECK-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE -! CHECK-NEXT: -fno-color-diagnostics Disable colors in diagnostics -! CHECK-NEXT: -fno-fortran-main Do not include Fortran_main.a (provided by Flang) when linking -! CHECK-NEXT: -fno-integrated-as Disable the integrated assembler -! CHECK-NEXT: -fno-lto Disable LTO mode (default) -! CHECK-NEXT: -fno-ppc-native-vector-element-order -! CHECK-NEXT: Specifies PowerPC non-native vector element order -! CHECK-NEXT: -fno-rtlib-add-rpath Do not add -rpath with architecture-specific resource directory to the linker flags. When --hip-link is specified, do not add -rpath with HIP runtime library directory to the linker flags -! CHECK-NEXT: -fno-signed-zeros Allow optimizations that ignore the sign of floating point zeros -! CHECK-NEXT: -fno-stack-arrays Allocate array temporaries on the heap (default) -! CHECK-NEXT: -fno-version-loops-for-stride -! CHECK-NEXT: Do not create unit-strided loops (default) -! CHECK-NEXT: -fomit-frame-pointer Omit the frame pointer from functions that don't need it. Some stack unwinding cases, such as profilers and sanitizers, may prefer specifying -fno-omit-frame-pointer. On many targets, -O1 and higher omit the frame pointer by default. -m[no-]omit-leaf-frame-pointer takes precedence for leaf functions -! CHECK-NEXT: -fopenacc Enable OpenACC -! CHECK-NEXT: -fopenmp-assume-no-nested-parallelism -! CHECK-NEXT: Assert no nested parallel regions in the GPU -! CHECK-NEXT: -fopenmp-assume-no-thread-state -! CHECK-NEXT: Assert no thread in a parallel region modifies an ICV -! CHECK-NEXT: -fopenmp-target-debug Enable debugging in the OpenMP offloading device RTL -! CHECK-NEXT: -fopenmp-targets= -! CHECK-NEXT: Specify comma-separated list of triples OpenMP offloading targets to be supported -! CHECK-NEXT: -fopenmp-version= -! CHECK-NEXT: Set OpenMP version (e.g. 45 for OpenMP 4.5, 51 for OpenMP 5.1). Default value is 11 for Flang -! CHECK-NEXT: -fopenmp Parse OpenMP pragmas and generate parallel code. -! CHECK-NEXT: -foptimization-record-file= -! CHECK-NEXT: Specify the output name of the file containing the optimization remarks. Implies -fsave-optimization-record. On Darwin platforms, this cannot be used with multiple -arch options. -! CHECK-NEXT: -foptimization-record-passes= -! CHECK-NEXT: Only include passes which match a specified regular expression in the generated optimization record (by default, include all passes) -! CHECK-NEXT: -fpass-plugin= Load pass plugin from a dynamic shared object file (only with new pass manager). -! CHECK-NEXT: -fppc-native-vector-element-order -! CHECK-NEXT: Specifies PowerPC native vector element order (default) -! CHECK-NEXT: -freciprocal-math Allow division operations to be reassociated -! CHECK-NEXT: -fropi Generate read-only position independent code (ARM only) -! CHECK-NEXT: -frtlib-add-rpath Add -rpath with architecture-specific resource directory to the linker flags. When --hip-link is specified, also add -rpath with HIP runtime library directory to the linker flags -! CHECK-NEXT: -frwpi Generate read-write position independent code (ARM only) -! CHECK-NEXT: -fsave-optimization-record= -! CHECK-NEXT: Generate an optimization record file in a specific format -! CHECK-NEXT: -fsave-optimization-record -! CHECK-NEXT: Generate a YAML optimization record file -! CHECK-NEXT: -fstack-arrays Attempt to allocate array temporaries on the stack, no matter their size -! CHECK-NEXT: -fsyntax-only Run the preprocessor, parser and semantic analysis stages -! CHECK-NEXT: -funderscoring Appends one trailing underscore to external names -! CHECK-NEXT: -fveclib= Use the given vector functions library -! CHECK-NEXT: -fversion-loops-for-stride -! CHECK-NEXT: Create unit-strided versions of loops -! CHECK-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. -! CHECK-NEXT: --gcc-install-dir= -! CHECK-NEXT: Use GCC installation in the specified directory. The directory ends with path components like 'lib{,32,64}/gcc{,-cross}/$triple/$version'. Note: executables (e.g. ld) used by the compiler are not overridden by the selected GCC installation -! CHECK-NEXT: --gcc-toolchain= Specify a directory where Flang can find 'lib{,32,64}/gcc{,-cross}/$triple/$version'. Flang will use the GCC installation with the largest version -! CHECK-NEXT: -gline-directives-only Emit debug line info directives only -! CHECK-NEXT: -gline-tables-only Emit debug line number tables only -! CHECK-NEXT: -gpulibc Link the LLVM C Library for GPUs -! CHECK-NEXT: -g Generate source-level debug information -! CHECK-NEXT: --help-hidden Display help for hidden options -! CHECK-NEXT: -help Display available options -! CHECK-NEXT: -isysroot Set the system root directory (usually /) -! CHECK-NEXT: -I Add directory to the end of the list of include search paths -! CHECK-NEXT: -L Add directory to library search path -! CHECK-NEXT: -march= For a list of available architectures for the target use '-mcpu=help' -! CHECK-NEXT: -mcode-object-version= -! CHECK-NEXT: Specify code object ABI version. Defaults to 5. (AMDGPU only) -! CHECK-NEXT: -mcpu= For a list of available CPUs for the target use '-mcpu=help' -! CHECK-NEXT: -mllvm= Alias for -mllvm -! CHECK-NEXT: -mllvm Additional arguments to forward to LLVM's option processing -! CHECK-NEXT: -mmlir Additional arguments to forward to MLIR's option processing -! CHECK-NEXT: -mno-outline-atomics Don't generate local calls to out-of-line atomic operations -! CHECK-NEXT: -module-dir Put MODULE files in -! CHECK-NEXT: -moutline-atomics Generate local calls to out-of-line atomic operations -! CHECK-NEXT: -mrvv-vector-bits= -! CHECK-NEXT: Specify the size in bits of an RVV vector register -! CHECK-NEXT: -msve-vector-bits= -! CHECK-NEXT: Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only) -! CHECK-NEXT: --no-offload-arch= -! CHECK-NEXT: Remove CUDA/HIP offloading device architecture (e.g. sm_35, gfx906) from the list of devices to compile for. 'all' resets the list to its default value. -! CHECK-NEXT: -nocpp Disable predefined and command line preprocessor macros -! CHECK-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation -! CHECK-NEXT: --offload-arch= Specify an offloading device architecture for CUDA, HIP, or OpenMP. (e.g. sm_35). If 'native' is used the compiler will detect locally installed architectures. For HIP offloading, the device architecture can be followed by target ID features delimited by a colon (e.g. gfx908:xnack+:sramecc-). May be specified more than once. -! CHECK-NEXT: --offload-device-only Only compile for the offloading device. -! CHECK-NEXT: --offload-host-device Compile for both the offloading host and device (default). -! CHECK-NEXT: --offload-host-only Only compile for the offloading host. -! CHECK-NEXT: -o Write output to -! CHECK-NEXT: -pedantic Warn on language extensions -! CHECK-NEXT: -print-effective-triple Print the effective target triple -! CHECK-NEXT: -print-target-triple Print the normalized target triple -! CHECK-NEXT: -pthread Support POSIX threads in generated code -! CHECK-NEXT: -P Disable linemarker output in -E mode -! CHECK-NEXT: -resource-dir The directory which holds the compiler resource files -! CHECK-NEXT: --rocm-path= ROCm installation path, used for finding and automatically linking required bitcode libraries. -! CHECK-NEXT: -Rpass-analysis= Report transformation analysis from optimization passes whose name matches the given POSIX regular expression -! CHECK-NEXT: -Rpass-missed= Report missed transformations by optimization passes whose name matches the given POSIX regular expression -! CHECK-NEXT: -Rpass= Report transformations performed by optimization passes whose name matches the given POSIX regular expression -! CHECK-NEXT: -R Enable the specified remark -! CHECK-NEXT: -save-temps= Save intermediate compilation results. -! CHECK-NEXT: -save-temps Alias for --save-temps=cwd -! CHECK-NEXT: -std= Language standard to compile for -! CHECK-NEXT: -S Only run preprocess and compilation steps -! CHECK-NEXT: --target= Generate code for the given target -! CHECK-NEXT: -U Undefine macro -! CHECK-NEXT: --version Print version information -! CHECK-NEXT: -v Show commands to run and use verbose output -! CHECK-NEXT: -Wl, Pass the comma separated arguments in to the linker -! CHECK-NEXT: -W Enable the specified warning -! CHECK-NEXT: -Xflang Pass to the flang compiler -! CHECK-NEXT: -x Treat subsequent input files as having type - - -! ERROR-FLANG: error: unknown argument '-help-hidden'; did you mean '--help-hidden'? - -! Frontend driver -help-hidden is not supported -! ERROR-FLANG-FC1: error: unknown argument: '{{.*}}' diff --git a/flang/test/Driver/driver-help.f90 b/flang/test/Driver/driver-help.f90 index 0b0a493baf07f7e63f291f97ee979c63fd365dbc..4c3609db80b9acc15720d1a4bcd1c3f751f1e387 100644 --- a/flang/test/Driver/driver-help.f90 +++ b/flang/test/Driver/driver-help.f90 @@ -1,298 +1,15 @@ - -!-------------------------- -! FLANG DRIVER (flang) -!-------------------------- ! RUN: %flang -help 2>&1 | FileCheck %s --check-prefix=HELP ! RUN: not %flang -helps 2>&1 | FileCheck %s --check-prefix=ERROR -!---------------------------------------- -! FLANG FRONTEND DRIVER (flang -fc1) -!---------------------------------------- ! RUN: %flang_fc1 -help 2>&1 | FileCheck %s --check-prefix=HELP-FC1 ! RUN: not %flang_fc1 -helps 2>&1 | FileCheck %s --check-prefix=ERROR ! HELP:USAGE: flang ! HELP-EMPTY: ! HELP-NEXT:OPTIONS: -! HELP-NEXT: -### Print (but do not run) the commands to run for this compilation -! HELP-NEXT: -cpp Enable predefined and command line preprocessor macros -! HELP-NEXT: -c Only run preprocess, compile, and assemble steps -! HELP-NEXT: -dM Print macro definitions in -E mode instead of normal output -! HELP-NEXT: -dumpmachine Display the compiler's target processor -! HELP-NEXT: -dumpversion Display the version of the compiler -! HELP-NEXT: -D = Define to (or 1 if omitted) -! HELP-NEXT: -emit-llvm Use the LLVM representation for assembler and object files -! HELP-NEXT: -E Only run the preprocessor -! HELP-NEXT: -falternative-parameter-statement -! HELP-NEXT: Enable the old style PARAMETER statement -! HELP-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation -! HELP-NEXT: -fbackslash Specify that backslash in string introduces an escape character -! HELP-NEXT: -fcolor-diagnostics Enable colors in diagnostics -! HELP-NEXT: -fconvert= Set endian conversion of data for unformatted files -! HELP-NEXT: -fdefault-double-8 Set the default double precision kind to an 8 byte wide type -! HELP-NEXT: -fdefault-integer-8 Set the default integer and logical kind to an 8 byte wide type -! HELP-NEXT: -fdefault-real-8 Set the default real kind to an 8 byte wide type -! HELP-NEXT: -ffast-math Allow aggressive, lossy floating-point optimizations -! HELP-NEXT: -ffixed-form Process source files in fixed form -! HELP-NEXT: -ffixed-line-length= -! HELP-NEXT: Use as character line width in fixed mode -! HELP-NEXT: -ffp-contract= Form fused FP ops (e.g. FMAs) -! HELP-NEXT: -ffree-form Process source files in free form -! HELP-NEXT: -fhonor-infinities Specify that floating-point optimizations are not allowed that assume arguments and results are not +-inf. -! HELP-NEXT: -fhonor-nans Specify that floating-point optimizations are not allowed that assume arguments and results are not NANs. -! HELP-NEXT: -fimplicit-none No implicit typing allowed unless overridden by IMPLICIT statements -! HELP-NEXT: -finput-charset= Specify the default character set for source files -! HELP-NEXT: -fintegrated-as Enable the integrated assembler -! HELP-NEXT: -fintrinsic-modules-path -! HELP-NEXT: Specify where to find the compiled intrinsic modules -! HELP-NEXT: -flarge-sizes Use INTEGER(KIND=8) for the result type in size-related intrinsics -! HELP-NEXT: -flogical-abbreviations Enable logical abbreviations -! HELP-NEXT: -flto=auto Enable LTO in 'full' mode -! HELP-NEXT: -flto=jobserver Enable LTO in 'full' mode -! HELP-NEXT: -flto= Set LTO mode -! HELP-NEXT: -flto Enable LTO in 'full' mode -! HELP-NEXT: -fms-runtime-lib= -! HELP-NEXT: Select Windows run-time library -! HELP-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE -! HELP-NEXT: -fno-color-diagnostics Disable colors in diagnostics -! HELP-NEXT: -fno-fortran-main Do not include Fortran_main.a (provided by Flang) when linking -! HELP-NEXT: -fno-integrated-as Disable the integrated assembler -! HELP-NEXT: -fno-lto Disable LTO mode (default) -! HELP-NEXT: -fno-ppc-native-vector-element-order -! HELP-NEXT: Specifies PowerPC non-native vector element order -! HELP-NEXT: -fno-rtlib-add-rpath Do not add -rpath with architecture-specific resource directory to the linker flags. When --hip-link is specified, do not add -rpath with HIP runtime library directory to the linker flags -! HELP-NEXT: -fno-signed-zeros Allow optimizations that ignore the sign of floating point zeros -! HELP-NEXT: -fno-stack-arrays Allocate array temporaries on the heap (default) -! HELP-NEXT: -fno-version-loops-for-stride -! HELP-NEXT: Do not create unit-strided loops (default) -! HELP-NEXT: -fomit-frame-pointer Omit the frame pointer from functions that don't need it. Some stack unwinding cases, such as profilers and sanitizers, may prefer specifying -fno-omit-frame-pointer. On many targets, -O1 and higher omit the frame pointer by default. -m[no-]omit-leaf-frame-pointer takes precedence for leaf functions -! HELP-NEXT: -fopenacc Enable OpenACC -! HELP-NEXT: -fopenmp-target-debug Enable debugging in the OpenMP offloading device RTL -! HELP-NEXT: -fopenmp-targets= -! HELP-NEXT: Specify comma-separated list of triples OpenMP offloading targets to be supported -! HELP-NEXT: -fopenmp-version= -! HELP-NEXT: Set OpenMP version (e.g. 45 for OpenMP 4.5, 51 for OpenMP 5.1). Default value is 11 for Flang -! HELP-NEXT: -fopenmp Parse OpenMP pragmas and generate parallel code. -! HELP-NEXT: -foptimization-record-file= -! HELP-NEXT: Specify the output name of the file containing the optimization remarks. Implies -fsave-optimization-record. On Darwin platforms, this cannot be used with multiple -arch options. -! HELP-NEXT: -foptimization-record-passes= -! HELP-NEXT: Only include passes which match a specified regular expression in the generated optimization record (by default, include all passes) -! HELP-NEXT: -fpass-plugin= Load pass plugin from a dynamic shared object file (only with new pass manager). -! HELP-NEXT: -fppc-native-vector-element-order -! HELP-NEXT: Specifies PowerPC native vector element order (default) -! HELP-NEXT: -freciprocal-math Allow division operations to be reassociated -! HELP-NEXT: -fropi Generate read-only position independent code (ARM only) -! HELP-NEXT: -frtlib-add-rpath Add -rpath with architecture-specific resource directory to the linker flags. When --hip-link is specified, also add -rpath with HIP runtime library directory to the linker flags -! HELP-NEXT: -frwpi Generate read-write position independent code (ARM only) -! HELP-NEXT: -fsave-optimization-record= -! HELP-NEXT: Generate an optimization record file in a specific format -! HELP-NEXT: -fsave-optimization-record -! HELP-NEXT: Generate a YAML optimization record file -! HELP-NEXT: -fstack-arrays Attempt to allocate array temporaries on the stack, no matter their size -! HELP-NEXT: -fsyntax-only Run the preprocessor, parser and semantic analysis stages -! HELP-NEXT: -funderscoring Appends one trailing underscore to external names -! HELP-NEXT: -fveclib= Use the given vector functions library -! HELP-NEXT: -fversion-loops-for-stride -! HELP-NEXT: Create unit-strided versions of loops -! HELP-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. -! HELP-NEXT: --gcc-install-dir= -! HELP-NEXT: Use GCC installation in the specified directory. The directory ends with path components like 'lib{,32,64}/gcc{,-cross}/$triple/$version'. Note: executables (e.g. ld) used by the compiler are not overridden by the selected GCC installation -! HELP-NEXT: --gcc-toolchain= Specify a directory where Flang can find 'lib{,32,64}/gcc{,-cross}/$triple/$version'. Flang will use the GCC installation with the largest version -! HELP-NEXT: -gline-directives-only Emit debug line info directives only -! HELP-NEXT: -gline-tables-only Emit debug line number tables only -! HELP-NEXT: -gpulibc Link the LLVM C Library for GPUs -! HELP-NEXT: -g Generate source-level debug information -! HELP-NEXT: --help-hidden Display help for hidden options -! HELP-NEXT: -help Display available options -! HELP-NEXT: -isysroot Set the system root directory (usually /) -! HELP-NEXT: -I Add directory to the end of the list of include search paths -! HELP-NEXT: -L Add directory to library search path -! HELP-NEXT: -march= For a list of available architectures for the target use '-mcpu=help' -! HELP-NEXT: -mcode-object-version= -! HELP-NEXT: Specify code object ABI version. Defaults to 5. (AMDGPU only) -! HELP-NEXT: -mcpu= For a list of available CPUs for the target use '-mcpu=help' -! HELP-NEXT: -mllvm= Alias for -mllvm -! HELP-NEXT: -mllvm Additional arguments to forward to LLVM's option processing -! HELP-NEXT: -mmlir Additional arguments to forward to MLIR's option processing -! HELP-NEXT: -mno-outline-atomics Don't generate local calls to out-of-line atomic operations -! HELP-NEXT: -module-dir Put MODULE files in -! HELP-NEXT: -moutline-atomics Generate local calls to out-of-line atomic operations -! HELP-NEXT: -mrvv-vector-bits= -! HELP-NEXT: Specify the size in bits of an RVV vector register -! HELP-NEXT: -msve-vector-bits= -! HELP-NEXT: Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only) -! HELP-NEXT: --no-offload-arch= -! HELP-NEXT: Remove CUDA/HIP offloading device architecture (e.g. sm_35, gfx906) from the list of devices to compile for. 'all' resets the list to its default value. -! HELP-NEXT: -nocpp Disable predefined and command line preprocessor macros -! HELP-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation -! HELP-NEXT: --offload-arch= Specify an offloading device architecture for CUDA, HIP, or OpenMP. (e.g. sm_35). If 'native' is used the compiler will detect locally installed architectures. For HIP offloading, the device architecture can be followed by target ID features delimited by a colon (e.g. gfx908:xnack+:sramecc-). May be specified more than once. -! HELP-NEXT: --offload-device-only Only compile for the offloading device. -! HELP-NEXT: --offload-host-device Compile for both the offloading host and device (default). -! HELP-NEXT: --offload-host-only Only compile for the offloading host. -! HELP-NEXT: -o Write output to -! HELP-NEXT: -pedantic Warn on language extensions -! HELP-NEXT: -print-effective-triple Print the effective target triple -! HELP-NEXT: -print-target-triple Print the normalized target triple -! HELP-NEXT: -pthread Support POSIX threads in generated code -! HELP-NEXT: -P Disable linemarker output in -E mode -! HELP-NEXT: --rocm-path= ROCm installation path, used for finding and automatically linking required bitcode libraries. -! HELP-NEXT: -Rpass-analysis= Report transformation analysis from optimization passes whose name matches the given POSIX regular expression -! HELP-NEXT: -Rpass-missed= Report missed transformations by optimization passes whose name matches the given POSIX regular expression -! HELP-NEXT: -Rpass= Report transformations performed by optimization passes whose name matches the given POSIX regular expression -! HELP-NEXT: -R Enable the specified remark -! HELP-NEXT: -save-temps= Save intermediate compilation results. -! HELP-NEXT: -save-temps Alias for --save-temps=cwd -! HELP-NEXT: -std= Language standard to compile for -! HELP-NEXT: -S Only run preprocess and compilation steps -! HELP-NEXT: --target= Generate code for the given target -! HELP-NEXT: -U Undefine macro -! HELP-NEXT: --version Print version information -! HELP-NEXT: -v Show commands to run and use verbose output -! HELP-NEXT: -Wl, Pass the comma separated arguments in to the linker -! HELP-NEXT: -W Enable the specified warning -! HELP-NEXT: -Xflang Pass to the flang compiler -! HELP-NEXT: -x Treat subsequent input files as having type - ! HELP-FC1:USAGE: flang ! HELP-FC1-EMPTY: ! HELP-FC1-NEXT:OPTIONS: -! HELP-FC1-NEXT: -cpp Enable predefined and command line preprocessor macros -! HELP-FC1-NEXT: --dependent-lib= Add dependent library -! HELP-FC1-NEXT: -dM Print macro definitions in -E mode instead of normal output -! HELP-FC1-NEXT: -D = Define to (or 1 if omitted) -! HELP-FC1-NEXT: -emit-fir Build the parse tree, then lower it to FIR -! HELP-FC1-NEXT: -emit-hlfir Build the parse tree, then lower it to HLFIR -! HELP-FC1-NEXT: -emit-llvm-bc Build ASTs then convert to LLVM, emit .bc file -! HELP-FC1-NEXT: -emit-llvm Use the LLVM representation for assembler and object files -! HELP-FC1-NEXT: -emit-obj Emit native object files -! HELP-FC1-NEXT: -E Only run the preprocessor -! HELP-FC1-NEXT: -falternative-parameter-statement -! HELP-FC1-NEXT: Enable the old style PARAMETER statement -! HELP-FC1-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation -! HELP-FC1-NEXT: -fbackslash Specify that backslash in string introduces an escape character -! HELP-FC1-NEXT: -fcolor-diagnostics Enable colors in diagnostics -! HELP-FC1-NEXT: -fconvert= Set endian conversion of data for unformatted files -! HELP-FC1-NEXT: -fdebug-dump-all Dump symbols and the parse tree after the semantic checks -! HELP-FC1-NEXT: -fdebug-dump-parse-tree-no-sema -! HELP-FC1-NEXT: Dump the parse tree (skips the semantic checks) -! HELP-FC1-NEXT: -fdebug-dump-parse-tree Dump the parse tree -! HELP-FC1-NEXT: -fdebug-dump-parsing-log -! HELP-FC1-NEXT: Run instrumented parse and dump the parsing log -! HELP-FC1-NEXT: -fdebug-dump-pft Dump the pre-fir parse tree -! HELP-FC1-NEXT: -fdebug-dump-provenance Dump provenance -! HELP-FC1-NEXT: -fdebug-dump-symbols Dump symbols after the semantic analysis -! HELP-FC1-NEXT: -fdebug-measure-parse-tree -! HELP-FC1-NEXT: Measure the parse tree -! HELP-FC1-NEXT: -fdebug-module-writer Enable debug messages while writing module files -! HELP-FC1-NEXT: -fdebug-pass-manager Prints debug information for the new pass manager -! HELP-FC1-NEXT: -fdebug-pre-fir-tree Dump the pre-FIR tree -! HELP-FC1-NEXT: -fdebug-unparse-no-sema Unparse and stop (skips the semantic checks) -! HELP-FC1-NEXT: -fdebug-unparse-with-symbols -! HELP-FC1-NEXT: Unparse and stop. -! HELP-FC1-NEXT: -fdebug-unparse Unparse and stop. -! HELP-FC1-NEXT: -fdefault-double-8 Set the default double precision kind to an 8 byte wide type -! HELP-FC1-NEXT: -fdefault-integer-8 Set the default integer and logical kind to an 8 byte wide type -! HELP-FC1-NEXT: -fdefault-real-8 Set the default real kind to an 8 byte wide type -! HELP-FC1-NEXT: -fembed-offload-object= -! HELP-FC1-NEXT: Embed Offloading device-side binary into host object file as a section. -! HELP-FC1-NEXT: -ffast-math Allow aggressive, lossy floating-point optimizations -! HELP-FC1-NEXT: -ffixed-form Process source files in fixed form -! HELP-FC1-NEXT: -ffixed-line-length= -! HELP-FC1-NEXT: Use as character line width in fixed mode -! HELP-FC1-NEXT: -ffp-contract= Form fused FP ops (e.g. FMAs) -! HELP-FC1-NEXT: -ffree-form Process source files in free form -! HELP-FC1-NEXT: -fget-definition -! HELP-FC1-NEXT: Get the symbol definition from -! HELP-FC1-NEXT: -fget-symbols-sources Dump symbols and their source code locations -! HELP-FC1-NEXT: -fimplicit-none No implicit typing allowed unless overridden by IMPLICIT statements -! HELP-FC1-NEXT: -finput-charset= Specify the default character set for source files -! HELP-FC1-NEXT: -fintrinsic-modules-path -! HELP-FC1-NEXT: Specify where to find the compiled intrinsic modules -! HELP-FC1-NEXT: -flarge-sizes Use INTEGER(KIND=8) for the result type in size-related intrinsics -! HELP-FC1-NEXT: -flogical-abbreviations Enable logical abbreviations -! HELP-FC1-NEXT: -flto= Set LTO mode -! HELP-FC1-NEXT: -flto Enable LTO in 'full' mode -! HELP-FC1-NEXT: -fno-analyzed-objects-for-unparse -! HELP-FC1-NEXT: Do not use the analyzed objects when unparsing -! HELP-FC1-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE -! HELP-FC1-NEXT: -fno-debug-pass-manager Disables debug printing for the new pass manager -! HELP-FC1-NEXT: -fno-ppc-native-vector-element-order -! HELP-FC1-NEXT: Specifies PowerPC non-native vector element order -! HELP-FC1-NEXT: -fno-reformat Dump the cooked character stream in -E mode -! HELP-FC1-NEXT: -fno-signed-zeros Allow optimizations that ignore the sign of floating point zeros -! HELP-FC1-NEXT: -fno-stack-arrays Allocate array temporaries on the heap (default) -! HELP-FC1-NEXT: -fno-version-loops-for-stride -! HELP-FC1-NEXT: Do not create unit-strided loops (default) -! HELP-FC1-NEXT: -fopenacc Enable OpenACC -! HELP-FC1-NEXT: -fopenmp-host-ir-file-path -! HELP-FC1-NEXT: Path to the IR file produced by the frontend for the host. -! HELP-FC1-NEXT: -fopenmp-is-target-device -! HELP-FC1-NEXT: Generate code only for an OpenMP target device. -! HELP-FC1-NEXT: -fopenmp-target-debug Enable debugging in the OpenMP offloading device RTL -! HELP-FC1-NEXT: -fopenmp-version= -! HELP-FC1-NEXT: Set OpenMP version (e.g. 45 for OpenMP 4.5, 51 for OpenMP 5.1). Default value is 11 for Flang -! HELP-FC1-NEXT: -fopenmp Parse OpenMP pragmas and generate parallel code. -! HELP-FC1-NEXT: -fpass-plugin= Load pass plugin from a dynamic shared object file (only with new pass manager). -! HELP-FC1-NEXT: -fppc-native-vector-element-order -! HELP-FC1-NEXT: Specifies PowerPC native vector element order (default) -! HELP-FC1-NEXT: -freciprocal-math Allow division operations to be reassociated -! HELP-FC1-NEXT: -fstack-arrays Attempt to allocate array temporaries on the stack, no matter their size -! HELP-FC1-NEXT: -fsyntax-only Run the preprocessor, parser and semantic analysis stages -! HELP-FC1-NEXT: -funderscoring Appends one trailing underscore to external names -! HELP-FC1-NEXT: -fveclib= Use the given vector functions library -! HELP-FC1-NEXT: -fversion-loops-for-stride -! HELP-FC1-NEXT: Create unit-strided versions of loops -! HELP-FC1-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. -! HELP-FC1-NEXT: -gpulibc Link the LLVM C Library for GPUs -! HELP-FC1-NEXT: -help Display available options -! HELP-FC1-NEXT: -init-only Only execute frontend initialization -! HELP-FC1-NEXT: -I Add directory to the end of the list of include search paths -! HELP-FC1-NEXT: -load Load the named plugin (dynamic shared object) -! HELP-FC1-NEXT: -mcode-object-version= -! HELP-FC1-NEXT: Specify code object ABI version. Defaults to 5. (AMDGPU only) -! HELP-FC1-NEXT: -menable-no-infs Allow optimization to assume there are no infinities. -! HELP-FC1-NEXT: -menable-no-nans Allow optimization to assume there are no NaNs. -! HELP-FC1-NEXT: -mframe-pointer= Specify which frame pointers to retain. -! HELP-FC1-NEXT: -mllvm Additional arguments to forward to LLVM's option processing -! HELP-FC1-NEXT: -mmlir Additional arguments to forward to MLIR's option processing -! HELP-FC1-NEXT: -module-dir Put MODULE files in -! HELP-FC1-NEXT: -module-suffix Use as the suffix for module files (the default value is `.mod`) -! HELP-FC1-NEXT: -mreassociate Allow reassociation transformations for floating-point instructions -! HELP-FC1-NEXT: -mrelocation-model -! HELP-FC1-NEXT: The relocation model to use -! HELP-FC1-NEXT: -mvscale-max= Specify the vscale maximum. Defaults to the vector length agnostic value of "0". (AArch64/RISC-V only) -! HELP-FC1-NEXT: -mvscale-min= Specify the vscale minimum. Defaults to "1". (AArch64/RISC-V only) -! HELP-FC1-NEXT: -nocpp Disable predefined and command line preprocessor macros -! HELP-FC1-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation -! HELP-FC1-NEXT: -opt-record-file -! HELP-FC1-NEXT: File name to use for YAML optimization record output -! HELP-FC1-NEXT: -opt-record-format -! HELP-FC1-NEXT: The format used for serializing remarks (default: YAML) -! HELP-FC1-NEXT: -opt-record-passes -! HELP-FC1-NEXT: Only record remark information for passes whose names match the given regular expression -! HELP-FC1-NEXT: -o Write output to -! HELP-FC1-NEXT: -pedantic Warn on language extensions -! HELP-FC1-NEXT: -pic-is-pie File is for a position independent executable -! HELP-FC1-NEXT: -pic-level Value for __PIC__ -! HELP-FC1-NEXT: -plugin Use the named plugin action instead of the default action (use "help" to list available options) -! HELP-FC1-NEXT: -pthread Support POSIX threads in generated code -! HELP-FC1-NEXT: -P Disable linemarker output in -E mode -! HELP-FC1-NEXT: -Rpass-analysis= Report transformation analysis from optimization passes whose name matches the given POSIX regular expression -! HELP-FC1-NEXT: -Rpass-missed= Report missed transformations by optimization passes whose name matches the given POSIX regular expression -! HELP-FC1-NEXT: -Rpass= Report transformations performed by optimization passes whose name matches the given POSIX regular expression -! HELP-FC1-NEXT: -R Enable the specified remark -! HELP-FC1-NEXT: -save-temps= Save intermediate compilation results. -! HELP-FC1-NEXT: -save-temps Alias for --save-temps=cwd -! HELP-FC1-NEXT: -std= Language standard to compile for -! HELP-FC1-NEXT: -S Only run preprocess and compilation steps -! HELP-FC1-NEXT: -target-cpu Target a specific cpu type -! HELP-FC1-NEXT: -target-feature Target specific attributes -! HELP-FC1-NEXT: -test-io Run the InputOuputTest action. Use for development and testing only. -! HELP-FC1-NEXT: -triple Specify target triple (e.g. i686-apple-darwin9) -! HELP-FC1-NEXT: -U Undefine macro -! HELP-FC1-NEXT: -version Print the compiler version -! HELP-FC1-NEXT: -W Enable the specified warning -! HELP-FC1-NEXT: -x Treat subsequent input files as having type ! ERROR: error: unknown argument '-helps'; did you mean '-help' diff --git a/flang/test/Driver/mlir-debug-pass-pipeline.f90 b/flang/test/Driver/mlir-debug-pass-pipeline.f90 index ef84cb80ecf1db05d3daae41414ad4bc0f00c640..06957604d7aadcfa81724cfd3410fb6e34ad1e65 100644 --- a/flang/test/Driver/mlir-debug-pass-pipeline.f90 +++ b/flang/test/Driver/mlir-debug-pass-pipeline.f90 @@ -58,12 +58,14 @@ end program ! ALL-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! ALL-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! ALL-NEXT: Pipeline Collection : ['func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: 'fir.global' Pipeline +! ALL-NEXT: CFGConversion ! ALL-NEXT: 'func.func' Pipeline ! ALL-NEXT: PolymorphicOpConversion -! ALL-NEXT: CFGConversionOnFunc +! ALL-NEXT: CFGConversion ! ALL-NEXT: 'omp.declare_reduction' Pipeline -! ALL-NEXT: CFGConversionOnReduction +! ALL-NEXT: CFGConversion ! ALL-NEXT: SCFToControlFlow ! ALL-NEXT: Canonicalizer ! ALL-NEXT: SimplifyRegionLite diff --git a/flang/test/Driver/mlir-pass-pipeline.f90 b/flang/test/Driver/mlir-pass-pipeline.f90 index d1ff2869b0a6a94d79ab88276197dc7306ae23ff..0272739aba4d0ad2476c851ed7fe448a3d33dba0 100644 --- a/flang/test/Driver/mlir-pass-pipeline.f90 +++ b/flang/test/Driver/mlir-pass-pipeline.f90 @@ -52,12 +52,14 @@ end program ! O2-NEXT: 'func.func' Pipeline ! O2-NEXT: PolymorphicOpConversion ! O2-NEXT: AddAliasTags -! ALL-NEXT: Pipeline Collection : ['func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: 'fir.global' Pipeline +! ALL-NEXT: CFGConversion ! ALL-NEXT: 'func.func' Pipeline ! NOTO2-NEXT: PolymorphicOpConversion -! ALL-NEXT: CFGConversionOnFunc +! ALL-NEXT: CFGConversion ! ALL-NEXT: 'omp.declare_reduction' Pipeline -! ALL-NEXT: CFGConversionOnReduction +! ALL-NEXT: CFGConversion ! ALL-NEXT: SCFToControlFlow ! ALL-NEXT: Canonicalizer diff --git a/flang/test/Fir/array-value-copy-2.fir b/flang/test/Fir/array-value-copy-2.fir index cb8d6ca2b05540ca49bd20c027f6b44a5570152e..21b340af10c6b818ae82bb3b41a5ef7281aaf9f4 100644 --- a/flang/test/Fir/array-value-copy-2.fir +++ b/flang/test/Fir/array-value-copy-2.fir @@ -1,5 +1,5 @@ -// RUN: fir-opt --array-value-copy --cfg-conversion-on-func-opt %s | FileCheck %s -// RUN: fir-opt --array-value-copy="optimize-conflicts=true" --cfg-conversion-on-func-opt %s | FileCheck %s +// RUN: fir-opt --array-value-copy --cfg-conversion %s | FileCheck %s +// RUN: fir-opt --array-value-copy="optimize-conflicts=true" --cfg-conversion %s | FileCheck %s // CHECK-LABEL: func @_QPslice1( // CHECK-NOT: fir.allocmem diff --git a/flang/test/Fir/basic-program.fir b/flang/test/Fir/basic-program.fir index 28c597fc918cd7a2c5ea05e04f9dc9917d1dea6e..d4826dd2e4762cabdbf7d9dddd95e96988c5e4a6 100644 --- a/flang/test/Fir/basic-program.fir +++ b/flang/test/Fir/basic-program.fir @@ -60,11 +60,13 @@ func.func @_QQmain() { // PASSES-NEXT: AddAliasTags -// PASSES-NEXT: Pipeline Collection : ['func.func', 'omp.declare_reduction'] +// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +// PASSES-NEXT: 'fir.global' Pipeline +// PASSES-NEXT: CFGConversion // PASSES-NEXT: 'func.func' Pipeline -// PASSES-NEXT: CFGConversionOnFunc +// PASSES-NEXT: CFGConversion // PASSES-NEXT: 'omp.declare_reduction' Pipeline -// PASSES-NEXT: CFGConversionOnReduction +// PASSES-NEXT: CFGConversion // PASSES-NEXT: SCFToControlFlow // PASSES-NEXT: Canonicalizer diff --git a/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir b/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir index fa7979e8875afcd2da56d95618b0262016a65084..8cf4f566964f9169702ee431fdca2725e41c4c63 100644 --- a/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir +++ b/flang/test/Fir/convert-to-llvm-openmp-and-fir.fir @@ -1,4 +1,4 @@ -// RUN: fir-opt --split-input-file --cfg-conversion-on-func-opt --fir-to-llvm-ir="target=aarch64-unknown-linux-gnu" %s | FileCheck %s +// RUN: fir-opt --split-input-file --cfg-conversion --fir-to-llvm-ir="target=aarch64-unknown-linux-gnu" %s | FileCheck %s func.func @_QPsb1(%arg0: !fir.ref {fir.bindc_name = "n"}, %arg1: !fir.ref> {fir.bindc_name = "arr"}) { %c1_i64 = arith.constant 1 : i64 @@ -7,15 +7,17 @@ func.func @_QPsb1(%arg0: !fir.ref {fir.bindc_name = "n"}, %arg1: !fir.ref - omp.wsloop nowait - for (%arg2) : i32 = (%c1_i32) to (%2) inclusive step (%c1_i32) { - fir.store %arg2 to %1 : !fir.ref - %3 = fir.load %1 : !fir.ref - %4 = fir.convert %3 : (i32) -> i64 - %5 = arith.subi %4, %c1_i64 : i64 - %6 = fir.coordinate_of %arg1, %5 : (!fir.ref>, i64) -> !fir.ref - fir.store %3 to %6 : !fir.ref - omp.yield + omp.wsloop nowait { + omp.loop_nest (%arg2) : i32 = (%c1_i32) to (%2) inclusive step (%c1_i32) { + fir.store %arg2 to %1 : !fir.ref + %3 = fir.load %1 : !fir.ref + %4 = fir.convert %3 : (i32) -> i64 + %5 = arith.subi %4, %c1_i64 : i64 + %6 = fir.coordinate_of %arg1, %5 : (!fir.ref>, i64) -> !fir.ref + fir.store %3 to %6 : !fir.ref + omp.yield + } + omp.terminator } omp.terminator } @@ -31,7 +33,7 @@ func.func @_QPsb1(%arg0: !fir.ref {fir.bindc_name = "n"}, %arg1: !fir.ref !llvm.ptr // CHECK: %[[N:.*]] = llvm.load %[[N_REF]] : !llvm.ptr -> i32 // CHECK: omp.wsloop nowait -// CHECK-SAME: for (%[[I:.*]]) : i32 = (%[[ONE_2]]) to (%[[N]]) inclusive step (%[[ONE_2]]) { +// CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[ONE_2]]) to (%[[N]]) inclusive step (%[[ONE_2]]) { // CHECK: llvm.store %[[I]], %[[I_VAR]] : i32, !llvm.ptr // CHECK: %[[I1:.*]] = llvm.load %[[I_VAR]] : !llvm.ptr -> i32 // CHECK: %[[I1_EXT:.*]] = llvm.sext %[[I1]] : i32 to i64 @@ -42,6 +44,8 @@ func.func @_QPsb1(%arg0: !fir.ref {fir.bindc_name = "n"}, %arg1: !fir.ref> {fir.bindc_name = "arr"}) { omp.parallel { %c1 = arith.constant 1 : i32 %c50 = arith.constant 50 : i32 - omp.wsloop for (%indx) : i32 = (%c1) to (%c50) inclusive step (%c1) { - %1 = fir.convert %indx : (i32) -> i64 - %c1_i64 = arith.constant 1 : i64 - %2 = arith.subi %1, %c1_i64 : i64 - %3 = fir.coordinate_of %arr, %2 : (!fir.box>, i64) -> !fir.ref - fir.store %indx to %3 : !fir.ref - omp.yield + omp.wsloop { + omp.loop_nest (%indx) : i32 = (%c1) to (%c50) inclusive step (%c1) { + %1 = fir.convert %indx : (i32) -> i64 + %c1_i64 = arith.constant 1 : i64 + %2 = arith.subi %1, %c1_i64 : i64 + %3 = fir.coordinate_of %arr, %2 : (!fir.box>, i64) -> !fir.ref + fir.store %indx to %3 : !fir.ref + omp.yield + } + omp.terminator } omp.terminator } @@ -98,9 +105,11 @@ func.func @_QPsb(%arr: !fir.box> {fir.bindc_name = "arr"}) { // CHECK: omp.parallel { // CHECK: %[[C1:.*]] = llvm.mlir.constant(1 : i32) : i32 // CHECK: %[[C50:.*]] = llvm.mlir.constant(50 : i32) : i32 -// CHECK: omp.wsloop for (%[[INDX:.*]]) : i32 = (%[[C1]]) to (%[[C50]]) inclusive step (%[[C1]]) { -// CHECK: llvm.store %[[INDX]], %{{.*}} : i32, !llvm.ptr -// CHECK: omp.yield +// CHECK: omp.wsloop { +// CHECK-NEXT: omp.loop_nest (%[[INDX:.*]]) : i32 = (%[[C1]]) to (%[[C50]]) inclusive step (%[[C1]]) { +// CHECK: llvm.store %[[INDX]], %{{.*}} : i32, !llvm.ptr +// CHECK: omp.yield +// CHECK: omp.terminator // CHECK: omp.terminator // CHECK: llvm.return @@ -708,18 +717,20 @@ func.func @_QPsb() { // CHECK-SAME: %[[ARRAY_REF:.*]]: !llvm.ptr // CHECK: %[[RED_ACCUMULATOR:.*]] = llvm.alloca %2 x i32 {bindc_name = "x"} : (i64) -> !llvm.ptr // CHECK: omp.parallel { -// CHECK: omp.wsloop reduction(@[[EQV_REDUCTION]] %[[RED_ACCUMULATOR]] -> %[[PRV:.+]] : !llvm.ptr) for -// CHECK: %[[ARRAY_ELEM_REF:.*]] = llvm.getelementptr %[[ARRAY_REF]][0, %{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr -// CHECK: %[[ARRAY_ELEM:.*]] = llvm.load %[[ARRAY_ELEM_REF]] : !llvm.ptr -> i32 -// CHECK: %[[LPRV:.+]] = llvm.load %[[PRV]] : !llvm.ptr -> i32 -// CHECK: %[[ZERO_1:.*]] = llvm.mlir.constant(0 : i64) : i32 -// CHECK: %[[ARGVAL_1:.*]] = llvm.icmp "ne" %[[LPRV]], %[[ZERO_1]] : i32 -// CHECK: %[[ZERO_2:.*]] = llvm.mlir.constant(0 : i64) : i32 -// CHECK: %[[ARGVAL_2:.*]] = llvm.icmp "ne" %[[ARRAY_ELEM]], %[[ZERO_2]] : i32 -// CHECK: %[[RES:.*]] = llvm.icmp "eq" %[[ARGVAL_2]], %[[ARGVAL_1]] : i1 -// CHECK: %[[RES_EXT:.*]] = llvm.zext %[[RES]] : i1 to i32 -// CHECK: llvm.store %[[RES_EXT]], %[[PRV]] : i32, !llvm.ptr -// CHECK: omp.yield +// CHECK: omp.wsloop reduction(@[[EQV_REDUCTION]] %[[RED_ACCUMULATOR]] -> %[[PRV:.+]] : !llvm.ptr) { +// CHECK-NEXT: omp.loop_nest +// CHECK: %[[ARRAY_ELEM_REF:.*]] = llvm.getelementptr %[[ARRAY_REF]][0, %{{.*}}] : (!llvm.ptr, i64) -> !llvm.ptr +// CHECK: %[[ARRAY_ELEM:.*]] = llvm.load %[[ARRAY_ELEM_REF]] : !llvm.ptr -> i32 +// CHECK: %[[LPRV:.+]] = llvm.load %[[PRV]] : !llvm.ptr -> i32 +// CHECK: %[[ZERO_1:.*]] = llvm.mlir.constant(0 : i64) : i32 +// CHECK: %[[ARGVAL_1:.*]] = llvm.icmp "ne" %[[LPRV]], %[[ZERO_1]] : i32 +// CHECK: %[[ZERO_2:.*]] = llvm.mlir.constant(0 : i64) : i32 +// CHECK: %[[ARGVAL_2:.*]] = llvm.icmp "ne" %[[ARRAY_ELEM]], %[[ZERO_2]] : i32 +// CHECK: %[[RES:.*]] = llvm.icmp "eq" %[[ARGVAL_2]], %[[ARGVAL_1]] : i1 +// CHECK: %[[RES_EXT:.*]] = llvm.zext %[[RES]] : i1 to i32 +// CHECK: llvm.store %[[RES_EXT]], %[[PRV]] : i32, !llvm.ptr +// CHECK: omp.yield +// CHECK: omp.terminator // CHECK: omp.terminator // CHECK: llvm.return @@ -747,21 +758,24 @@ func.func @_QPsimple_reduction(%arg0: !fir.ref>> %c1_i32 = arith.constant 1 : i32 %c100_i32 = arith.constant 100 : i32 %c1_i32_0 = arith.constant 1 : i32 - omp.wsloop reduction(@eqv_reduction %1 -> %prv : !fir.ref>) for (%arg1) : i32 = (%c1_i32) to (%c100_i32) inclusive step (%c1_i32_0) { - fir.store %arg1 to %3 : !fir.ref - %4 = fir.load %3 : !fir.ref - %5 = fir.convert %4 : (i32) -> i64 - %c1_i64 = arith.constant 1 : i64 - %6 = arith.subi %5, %c1_i64 : i64 - %7 = fir.coordinate_of %arg0, %6 : (!fir.ref>>, i64) -> !fir.ref> - %8 = fir.load %7 : !fir.ref> - %lprv = fir.load %prv : !fir.ref> - %lprv1 = fir.convert %lprv : (!fir.logical<4>) -> i1 - %9 = fir.convert %8 : (!fir.logical<4>) -> i1 - %10 = arith.cmpi eq, %9, %lprv1 : i1 - %11 = fir.convert %10 : (i1) -> !fir.logical<4> - fir.store %11 to %prv : !fir.ref> - omp.yield + omp.wsloop reduction(@eqv_reduction %1 -> %prv : !fir.ref>) { + omp.loop_nest (%arg1) : i32 = (%c1_i32) to (%c100_i32) inclusive step (%c1_i32_0) { + fir.store %arg1 to %3 : !fir.ref + %4 = fir.load %3 : !fir.ref + %5 = fir.convert %4 : (i32) -> i64 + %c1_i64 = arith.constant 1 : i64 + %6 = arith.subi %5, %c1_i64 : i64 + %7 = fir.coordinate_of %arg0, %6 : (!fir.ref>>, i64) -> !fir.ref> + %8 = fir.load %7 : !fir.ref> + %lprv = fir.load %prv : !fir.ref> + %lprv1 = fir.convert %lprv : (!fir.logical<4>) -> i1 + %9 = fir.convert %8 : (!fir.logical<4>) -> i1 + %10 = arith.cmpi eq, %9, %lprv1 : i1 + %11 = fir.convert %10 : (i1) -> !fir.logical<4> + fir.store %11 to %prv : !fir.ref> + omp.yield + } + omp.terminator } omp.terminator } diff --git a/flang/test/Fir/loop01.fir b/flang/test/Fir/loop01.fir index c849797b969eba5bda1e38cce73b888c0c85efa4..72ca1c3989e453d41f3605c14cb48bc657f8e654 100644 --- a/flang/test/Fir/loop01.fir +++ b/flang/test/Fir/loop01.fir @@ -1,4 +1,4 @@ -// RUN: fir-opt --split-input-file --cfg-conversion-on-func-opt %s | FileCheck %s +// RUN: fir-opt --split-input-file --cfg-conversion %s | FileCheck %s func.func @x(%lb : index, %ub : index, %step : index, %b : i1, %addr : !fir.ref) { fir.do_loop %iv = %lb to %ub step %step unordered { diff --git a/flang/test/Fir/loop02.fir b/flang/test/Fir/loop02.fir index 8918666f0b3460d8b1982e83dd13de3b9f9cf557..50948e0e7aa6b53dcc40fafb74f112b401b29f89 100644 --- a/flang/test/Fir/loop02.fir +++ b/flang/test/Fir/loop02.fir @@ -1,5 +1,5 @@ -// RUN: fir-opt --cfg-conversion-on-func-opt="always-execute-loop-body=true" %s | FileCheck %s -// RUN: fir-opt --cfg-conversion-on-func-opt %s | FileCheck %s --check-prefix=NOOPT +// RUN: fir-opt --cfg-conversion="always-execute-loop-body=true" %s | FileCheck %s +// RUN: fir-opt --cfg-conversion %s | FileCheck %s --check-prefix=NOOPT func.func @x(%addr : !fir.ref) { %bound = arith.constant 452 : index diff --git a/flang/test/Lower/CUDA/cuda-allocatable.cuf b/flang/test/Lower/CUDA/cuda-allocatable.cuf index 251ff16a56c797cf02c38e29bdccc2ad62dfa79e..eff5f13669e904ce9eb80e8dbeb2f0795a27af6d 100644 --- a/flang/test/Lower/CUDA/cuda-allocatable.cuf +++ b/flang/test/Lower/CUDA/cuda-allocatable.cuf @@ -17,6 +17,15 @@ end subroutine ! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: %[[BOX_LOAD:.*]] = fir.load %[[BOX_DECL]]#1 : !fir.ref>>> +! CHECK: %[[ADDR:.*]] = fir.box_addr %[[BOX_LOAD]] : (!fir.box>>) -> !fir.heap> +! CHECK: %[[ADDR_I64:.*]] = fir.convert %[[ADDR]] : (!fir.heap>) -> i64 +! CHECK: %[[C0:.*]] = arith.constant 0 : i64 +! CHECK: %[[NE_C0:.*]] = arith.cmpi ne, %[[ADDR_I64]], %[[C0]] : i64 +! CHECK: fir.if %[[NE_C0]] { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } + subroutine sub2() real, allocatable, managed :: a(:) integer :: istat @@ -37,6 +46,10 @@ end subroutine ! CHECK: %[[STAT:.*]] = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda, hasStat} -> i32 ! CHECK: fir.store %[[STAT]] to %[[ISTAT_DECL]]#1 : !fir.ref +! CHECK: fir.if %{{.*}} { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } + subroutine sub3() integer, allocatable, pinned :: a(:,:) logical :: plog @@ -50,6 +63,9 @@ end subroutine ! CHECK: %[[PLOG_DECL:.*]]:2 = hlfir.declare %5 {uniq_name = "_QFsub3Eplog"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) ! CHECK-2: fir.call @_FortranAAllocatableSetBounds ! CHECK: %{{.*}} = fir.cuda_allocate %[[BOX_DECL]]#1 : !fir.ref>>> pinned(%[[PLOG_DECL]]#1 : !fir.ref>) {cuda_attr = #fir.cuda} -> i32 +! CHECK: fir.if %{{.*}} { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } subroutine sub4() real, allocatable, device :: a(:) @@ -65,6 +81,9 @@ end subroutine ! CHECK: fir.call @_FortranAAllocatableSetBounds ! CHECK: %[[STREAM:.*]] = fir.load %[[ISTREAM_DECL]]#0 : !fir.ref ! CHECK: %{{.*}} = fir.cuda_allocate %[[BOX_DECL]]#1 : !fir.ref>>> stream(%[[STREAM]] : i32) {cuda_attr = #fir.cuda} -> i32 +! CHECK: fir.if %{{.*}} { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } subroutine sub5() real, allocatable, device :: a(:) @@ -80,6 +99,11 @@ end subroutine ! CHECK: %[[LOAD_B:.*]] = fir.load %[[BOX_B_DECL]]#1 : !fir.ref>>> ! CHECK: fir.call @_FortranAAllocatableSetBounds ! CHECK: %{{.*}} = fir.cuda_allocate %[[BOX_A_DECL]]#1 : !fir.ref>>> source(%[[LOAD_B]] : !fir.box>>) {cuda_attr = #fir.cuda} -> i32 +! CHECK: fir.if +! CHECK: fir.freemem +! CHECK: fir.if %{{.*}} { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_A_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } subroutine sub6() real, allocatable, device :: a(:) @@ -95,6 +119,9 @@ end subroutine ! CHECK: %[[LOAD_B:.*]] = fir.load %[[BOX_B_DECL]]#1 : !fir.ref>>> ! CHECK: fir.call @_FortranAAllocatableApplyMold ! CHECK: %{{.*}} = fir.cuda_allocate %[[BOX_A_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: fir.if %{{.*}} { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_A_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } subroutine sub7() real, allocatable, device :: a(:) @@ -120,3 +147,6 @@ end subroutine ! CHECK: %[[ERR_BOX:.*]] = fir.embox %[[ERR_DECL]]#1 : (!fir.ref>) -> !fir.box> ! CHECK: %[[STAT:.*]] = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> errmsg(%15 : !fir.box>) {cuda_attr = #fir.cuda, hasStat} -> i32 ! CHECK: fir.store %[[STAT]] to %[[ISTAT_DECL]]#1 : !fir.ref +! CHECK: fir.if %{{.*}} { +! CHECK: %{{.*}} = fir.cuda_deallocate %[[BOX_DECL]]#1 : !fir.ref>>> {cuda_attr = #fir.cuda} -> i32 +! CHECK: } diff --git a/flang/test/Lower/HLFIR/internal-procedures.f90 b/flang/test/Lower/HLFIR/internal-procedures.f90 index fff7125897ddfed701cfea93adbd0110bc009f5c..3c443991180905b0c1131e95a2abeefaaf0ac2cc 100644 --- a/flang/test/Lower/HLFIR/internal-procedures.f90 +++ b/flang/test/Lower/HLFIR/internal-procedures.f90 @@ -52,3 +52,30 @@ end subroutine ! CHECK: %[[VAL_4:.*]]:2 = fir.unboxchar %[[VAL_3]] : (!fir.boxchar<1>) -> (!fir.ref>, index) ! CHECK: %[[VAL_5:.*]]:2 = hlfir.declare %[[VAL_4]]#0 typeparams %[[VAL_4]]#1 {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_scalar_charEc"} : (!fir.ref>, index) -> (!fir.boxchar<1>, !fir.ref>) ! CHECK: fir.call @_QPbar(%[[VAL_5]]#0) {{.*}}: (!fir.boxchar<1>) -> () + +subroutine test_proc_pointer(p) + real, pointer, external :: p + call internal() +contains + subroutine internal() + real :: x + x = p() + end subroutine +end subroutine +! CHECK-LABEL: func.func @_QPtest_proc_pointer( +! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>) { +! CHECK: %[[VAL_1:.*]]:2 = hlfir.declare %[[VAL_0]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointerEp"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) +! CHECK: %[[VAL_2:.*]] = fir.alloca tuple ()>>> +! CHECK: %[[VAL_3:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_4:.*]] = fir.coordinate_of %[[VAL_2]], %[[VAL_3]] : (!fir.ref ()>>>>, i32) -> !fir.llvm_ptr ()>>> +! CHECK: fir.store %[[VAL_1]]#1 to %[[VAL_4]] : !fir.llvm_ptr ()>>> +! CHECK: fir.call @_QFtest_proc_pointerPinternal(%[[VAL_2]]) {{.*}}: (!fir.ref ()>>>>) -> () +! CHECK: return +! CHECK: } + +! CHECK-LABEL: func.func private @_QFtest_proc_pointerPinternal( +! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref ()>>>> {fir.host_assoc}) attributes {fir.host_symbol = @_QPtest_proc_pointer, llvm.linkage = #llvm.linkage} { +! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_2:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_1]] : (!fir.ref ()>>>>, i32) -> !fir.llvm_ptr ()>>> +! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_2]] : !fir.llvm_ptr ()>>> +! CHECK: %[[VAL_4:.*]]:2 = hlfir.declare %[[VAL_3]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFtest_proc_pointerEp"} : (!fir.ref ()>>) -> (!fir.ref ()>>, !fir.ref ()>>) diff --git a/flang/test/Lower/Intrinsics/shape.f90 b/flang/test/Lower/Intrinsics/shape.f90 new file mode 100644 index 0000000000000000000000000000000000000000..60f28a326e99516b5557804278397ecb2c568da7 --- /dev/null +++ b/flang/test/Lower/Intrinsics/shape.f90 @@ -0,0 +1,74 @@ +! Test SHAPE with function results +! RUN: bbc -emit-hlfir -o - %s | FileCheck %s + +subroutine test() + interface + function return_array() + real, pointer :: return_array(:, :, :) + end function + end interface + print *, shape(return_array()) +end subroutine +! CHECK-LABEL: func.func @_QPtest() { +! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.array<3xi32> +! CHECK: %[[VAL_7:.*]] = fir.call @_QPreturn_array() {{.*}}: () -> !fir.box>> +! CHECK: fir.save_result %[[VAL_7]] to %[[VAL_1:.*]] : !fir.box>>, !fir.ref>>> +! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = ".tmp.func_result"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_8]]#1 : !fir.ref>>> +! CHECK: %[[VAL_10:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_11:.*]]:3 = fir.box_dims %[[VAL_9]], %[[VAL_10]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]]#1 : (index) -> i32 +! CHECK: %[[VAL_13:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_14:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_13]] : (!fir.ref>, index) -> !fir.ref +! CHECK: fir.store %[[VAL_12]] to %[[VAL_14]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_16:.*]]:3 = fir.box_dims %[[VAL_9]], %[[VAL_15]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]]#1 : (index) -> i32 +! CHECK: %[[VAL_18:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_19:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_18]] : (!fir.ref>, index) -> !fir.ref +! CHECK: fir.store %[[VAL_17]] to %[[VAL_19]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_21:.*]]:3 = fir.box_dims %[[VAL_9]], %[[VAL_20]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[VAL_22:.*]] = fir.convert %[[VAL_21]]#1 : (index) -> i32 +! CHECK: %[[VAL_23:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>, index) -> !fir.ref +! CHECK: fir.store %[[VAL_22]] to %[[VAL_24]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.constant 3 : index +! CHECK: %[[VAL_26:.*]] = fir.shape %[[VAL_25]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_26]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) + +subroutine test_kind() + interface + function return_array() + real, pointer :: return_array(:, :, :) + end function + end interface + print *, shape(return_array(), kind=8) +end subroutine +! CHECK-LABEL: func.func @_QPtest_kind() { +! CHECK: %[[VAL_0:.*]] = fir.alloca !fir.array<3xi64> +! CHECK: %[[VAL_7:.*]] = fir.call @_QPreturn_array() {{.*}}: () -> !fir.box>> +! CHECK: fir.save_result %[[VAL_7]] to %[[VAL_1:.*]] : !fir.box>>, !fir.ref>>> +! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_1]] {uniq_name = ".tmp.func_result"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_8]]#1 : !fir.ref>>> +! CHECK: %[[VAL_10:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_11:.*]]:3 = fir.box_dims %[[VAL_9]], %[[VAL_10]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]]#1 : (index) -> i64 +! CHECK: %[[VAL_13:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_14:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_13]] : (!fir.ref>, index) -> !fir.ref +! CHECK: fir.store %[[VAL_12]] to %[[VAL_14]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_16:.*]]:3 = fir.box_dims %[[VAL_9]], %[[VAL_15]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]]#1 : (index) -> i64 +! CHECK: %[[VAL_18:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_19:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_18]] : (!fir.ref>, index) -> !fir.ref +! CHECK: fir.store %[[VAL_17]] to %[[VAL_19]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_21:.*]]:3 = fir.box_dims %[[VAL_9]], %[[VAL_20]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[VAL_22:.*]] = fir.convert %[[VAL_21]]#1 : (index) -> i64 +! CHECK: %[[VAL_23:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>, index) -> !fir.ref +! CHECK: fir.store %[[VAL_22]] to %[[VAL_24]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.constant 3 : index +! CHECK: %[[VAL_26:.*]] = fir.shape %[[VAL_25]] : (index) -> !fir.shape<1> +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_26]]) {uniq_name = ".tmp.intrinsic_result"} : (!fir.ref>, !fir.shape<1>) -> (!fir.ref>, !fir.ref>) diff --git a/flang/test/Lower/OpenACC/acc-declare.f90 b/flang/test/Lower/OpenACC/acc-declare.f90 index 401b654adeb61b6d9b4f03416e2ed654ea8fbb0a..5d3f9e3fe97e4a1b076c594366502535dbed5021 100644 --- a/flang/test/Lower/OpenACC/acc-declare.f90 +++ b/flang/test/Lower/OpenACC/acc-declare.f90 @@ -245,6 +245,11 @@ module acc_declare ! CHECK: fir.freemem %{{.*}} : !fir.heap> ! CHECK: fir.store %{{.*}} to %{{.*}} {acc.declare_action = #acc.declare_action} : !fir.ref>>> +! CHECK: fir.if +! CHECK: fir.freemem %{{.*}} : !fir.heap> +! CHECK: fir.store %{{.*}} to %{{.*}}#1 {acc.declare_action = #acc.declare_action} : !fir.ref>>> +! CHECK: } + end subroutine ! CHECK-LABEL: func.func private @_QMacc_declareFacc_declare_allocateEa_acc_declare_update_desc_post_alloc( diff --git a/flang/test/Lower/OpenMP/FIR/copyin.f90 b/flang/test/Lower/OpenMP/FIR/copyin.f90 index 20023a81977aef18299a797ae640e06bdbf044a3..e256404d3d55ce6030c625b817250cbded8d885a 100644 --- a/flang/test/Lower/OpenMP/FIR/copyin.f90 +++ b/flang/test/Lower/OpenMP/FIR/copyin.f90 @@ -145,10 +145,13 @@ end ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]] : !fir.ref ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_9:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_9]] to %[[VAL_3]] : !fir.ref -! CHECK: fir.call @_QPsub4(%[[VAL_4]]) {{.*}}: (!fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_9:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_9]] to %[[VAL_3]] : !fir.ref +! CHECK: fir.call @_QPsub4(%[[VAL_4]]) {{.*}}: (!fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -286,7 +289,8 @@ end subroutine !CHECK: %[[val_c1_i32:.*]] = arith.constant 1 : i32 !CHECK: %[[val_19:.*]] = fir.load %[[val_13]] : !fir.ref !CHECK: %[[val_c1_i32_2:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop for (%[[arg:.*]]) : i32 = (%[[val_c1_i32]]) to (%[[val_19]]) inclusive step (%[[val_c1_i32_2]]) { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[arg:.*]]) : i32 = (%[[val_c1_i32]]) to (%[[val_19]]) inclusive step (%[[val_c1_i32_2]]) { !CHECK: fir.store %[[arg]] to %[[val_9]] : !fir.ref !CHECK: %[[val_20:.*]] = fir.load %[[val_16]] : !fir.ref !CHECK: %[[val_21:.*]] = fir.load %[[val_9]] : !fir.ref @@ -296,6 +300,8 @@ end subroutine !CHECK: } !CHECK: omp.terminator !CHECK: } +!CHECK: omp.terminator +!CHECK: } !CHECK: return !CHECK: } subroutine common_2() diff --git a/flang/test/Lower/OpenMP/FIR/flush.f90 b/flang/test/Lower/OpenMP/FIR/flush.f90 index 2868367fbdba64176257b1623cbb539c69b2090a..2c281632b85cb0460bf43436858cbe7f174d4021 100644 --- a/flang/test/Lower/OpenMP/FIR/flush.f90 +++ b/flang/test/Lower/OpenMP/FIR/flush.f90 @@ -1,7 +1,7 @@ ! This test checks lowering of OpenMP Flush Directive. !RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion-on-func-opt | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="LLVMIRDialect,OMPDialect" +!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="LLVMIRDialect,OMPDialect" subroutine flush_standalone(a, b, c) integer, intent(inout) :: a, b, c diff --git a/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 b/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 index 389bcba35f77f5e17296a75c9b8a68ad5684831b..86c4d917fa51eefd3b1b667f83395fe4e1a39368 100644 --- a/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 +++ b/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 @@ -17,7 +17,8 @@ !CHECK: %[[val_c1_i32:.*]] = arith.constant 1 : i32 !CHECK: %[[val_c100_i32:.*]] = arith.constant 100 : i32 !CHECK: %[[val_c1_i32_0:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop for (%[[arg:.*]]) : i32 = (%[[val_c1_i32]]) to (%[[val_c100_i32]]) inclusive step (%[[val_c1_i32_0]]) { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[arg:.*]]) : i32 = (%[[val_c1_i32]]) to (%[[val_c100_i32]]) inclusive step (%[[val_c1_i32_0]]) { !CHECK: fir.store %[[arg]] to %[[val_0]] : !fir.ref !CHECK: %[[val_11:.*]] = arith.addi %[[arg]], %[[val_c1_i32_0]] : i32 !CHECK: %[[val_c0_i32:.*]] = arith.constant 0 : i32 @@ -34,6 +35,8 @@ !CHECK: } !CHECK: omp.yield !CHECK: } +!CHECK: omp.terminator +!CHECK: } !CHECK: return !CHECK: } subroutine lastprivate_common diff --git a/flang/test/Lower/OpenMP/FIR/location.f90 b/flang/test/Lower/OpenMP/FIR/location.f90 index 648377837670329e860e3d58cb967e0a6ff6aa50..6a7fb3c035846eeb68ab4684df2d13d86ef52afd 100644 --- a/flang/test/Lower/OpenMP/FIR/location.f90 +++ b/flang/test/Lower/OpenMP/FIR/location.f90 @@ -28,11 +28,14 @@ end !CHECK-LABEL: sub_loop subroutine sub_loop() -!CHECK: omp.wsloop {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest {{.*}} { !$omp do do i=1,10 print *, i !CHECK: omp.yield loc(#[[LOOP_LOC:.*]]) +!CHECK: } loc(#[[LOOP_LOC]]) +!CHECK: omp.terminator loc(#[[LOOP_LOC]]) !CHECK: } loc(#[[LOOP_LOC]]) end do !$omp end do @@ -60,9 +63,9 @@ end subroutine !CHECK: #[[PAR_LOC]] = loc("{{.*}}location.f90":9:9) !CHECK: #[[TAR_LOC]] = loc("{{.*}}location.f90":21:9) -!CHECK: #[[LOOP_LOC]] = loc("{{.*}}location.f90":32:9) -!CHECK: #[[BAR_LOC]] = loc("{{.*}}location.f90":44:9) -!CHECK: #[[TW_LOC]] = loc("{{.*}}location.f90":46:9) -!CHECK: #[[TY_LOC]] = loc("{{.*}}location.f90":48:9) -!CHECK: #[[IF_LOC]] = loc("{{.*}}location.f90":55:14) -!CHECK: #[[TASK_LOC]] = loc("{{.*}}location.f90":55:9) +!CHECK: #[[LOOP_LOC]] = loc("{{.*}}location.f90":33:9) +!CHECK: #[[BAR_LOC]] = loc("{{.*}}location.f90":47:9) +!CHECK: #[[TW_LOC]] = loc("{{.*}}location.f90":49:9) +!CHECK: #[[TY_LOC]] = loc("{{.*}}location.f90":51:9) +!CHECK: #[[IF_LOC]] = loc("{{.*}}location.f90":58:14) +!CHECK: #[[TASK_LOC]] = loc("{{.*}}location.f90":58:9) diff --git a/flang/test/Lower/OpenMP/FIR/master.f90 b/flang/test/Lower/OpenMP/FIR/master.f90 index 3bac582c7725a889ae053102e0f8ca29d39fc623..dd9910da2f419034749611f205e256e9b67db16e 100644 --- a/flang/test/Lower/OpenMP/FIR/master.f90 +++ b/flang/test/Lower/OpenMP/FIR/master.f90 @@ -1,5 +1,5 @@ !RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion-on-func-opt | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect" +!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect" !=============================================================================== ! parallel construct with function call which has master construct internally diff --git a/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 b/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 index 2060e2062c1a34db57223bfeb1bed46b748f8931..16832355f5d1bcc29510b44acd6f4f8a16acfaf7 100644 --- a/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 +++ b/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 @@ -12,8 +12,9 @@ !CHECK-DAG: %[[ARG1_PVT:.*]] = fir.alloca !fir.char<1,5> {bindc_name = "arg1", ! Check that we are accessing the clone inside the loop -!CHECK-DAG: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { -!CHECK-DAG: %[[UNIT:.*]] = arith.constant 6 : i32 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: %[[UNIT:.*]] = arith.constant 6 : i32 !CHECK-NEXT: %[[ADDR:.*]] = fir.address_of(@_QQclX !CHECK-NEXT: %[[CVT0:.*]] = fir.convert %[[ADDR]] !CHECK-NEXT: %[[CNST:.*]] = arith.constant @@ -36,9 +37,12 @@ ! Testing lastprivate val update !CHECK-DAG: %[[CVT:.*]] = fir.convert %[[ARG1_REF]] : (!fir.ref>) -> !fir.ref !CHECK-DAG: %[[CVT1:.*]] = fir.convert %[[ARG1_PVT]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: fir.call @llvm.memmove.p0.p0.i64(%[[CVT]], %[[CVT1]]{{.*}}) -!CHECK-DAG: } -!CHECK-DAG: omp.yield +!CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[CVT]], %[[CVT1]]{{.*}}) +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine lastprivate_character(arg1) character(5) :: arg1 @@ -55,7 +59,8 @@ end subroutine !CHECK: func @_QPlastprivate_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}) { !CHECK-DAG: omp.parallel { !CHECK-DAG: %[[CLONE:.*]] = fir.alloca i32 {bindc_name = "arg1" -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -70,8 +75,11 @@ end subroutine ! Testing lastprivate val update !CHECK-NEXT: %[[CLONE_LD:.*]] = fir.load %[[CLONE]] : !fir.ref !CHECK-NEXT: fir.store %[[CLONE_LD]] to %[[ARG1]] : !fir.ref -!CHECK-DAG: } -!CHECK-DAG: omp.yield +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine lastprivate_int(arg1) integer :: arg1 @@ -90,7 +98,8 @@ end subroutine !CHECK: omp.parallel { !CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" !CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -108,6 +117,9 @@ end subroutine !CHECK-DAG: fir.store %[[CLONE_LD2]] to %[[ARG2]] : !fir.ref !CHECK: } !CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine mult_lastprivate_int(arg1, arg2) integer :: arg1, arg2 @@ -127,7 +139,8 @@ end subroutine !CHECK: omp.parallel { !CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" !CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { !Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -145,6 +158,9 @@ end subroutine !CHECK-DAG: fir.store %[[CLONE_LD1]] to %[[ARG1]] : !fir.ref !CHECK: } !CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine mult_lastprivate_int2(arg1, arg2) integer :: arg1, arg2 @@ -169,7 +185,8 @@ end subroutine ! Lastprivate Allocation !CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" !CHECK-NOT: omp.barrier -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -185,6 +202,9 @@ end subroutine !CHECK-NEXT: fir.store %[[CLONE_LD]] to %[[ARG2]] : !fir.ref !CHECK-NEXT: } !CHECK-NEXT: omp.yield +!CHECK-NEXT: } +!CHECK-NEXT: omp.terminator +!CHECK-NEXT: } subroutine firstpriv_lastpriv_int(arg1, arg2) integer :: arg1, arg2 @@ -207,7 +227,8 @@ end subroutine !CHECK-NEXT: %[[FPV_LD:.*]] = fir.load %[[ARG1]] : !fir.ref !CHECK-NEXT: fir.store %[[FPV_LD]] to %[[CLONE1]] : !fir.ref !CHECK-NEXT: omp.barrier -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 !CHECK: %[[C0:.*]] = arith.constant 0 : i32 @@ -222,6 +243,9 @@ end subroutine !CHECK-NEXT: fir.store %[[CLONE_LD]] to %[[ARG1]] : !fir.ref !CHECK-NEXT: } !CHECK-NEXT: omp.yield +!CHECK-NEXT: } +!CHECK-NEXT: omp.terminator +!CHECK-NEXT: } subroutine firstpriv_lastpriv_int2(arg1) integer :: arg1 diff --git a/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 b/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 index c99bf761333b8150201cdeda28c2dd3f743957d4..fb0fb9594c350e21957b462382cc021899fc2f2e 100644 --- a/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 +++ b/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 @@ -13,30 +13,33 @@ ! CHECK: %[[ONE:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_4:.*]] : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_6:.*]]) : i32 = (%[[ONE]]) to (%[[VAL_3]]) inclusive step (%[[VAL_5]]) { -! CHECK: fir.store %[[VAL_6]] to %[[PRIV_I]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i32) -> index -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> index -! CHECK: %[[VAL_11:.*]] = arith.constant 1 : index -! CHECK: %[[LB:.*]] = fir.convert %[[VAL_8]] : (index) -> i32 -! CHECK: %[[VAL_12:.*]]:2 = fir.do_loop %[[VAL_13:[^ ]*]] = -! CHECK-SAME: %[[VAL_8]] to %[[VAL_10]] step %[[VAL_11]] -! CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i32) { -! CHECK: fir.store %[[IV]] to %[[PRIV_J]] : !fir.ref -! CHECK: %[[LOAD:.*]] = fir.load %[[PRIV_I]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[PRIV_J]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.addi %[[LOAD]], %[[VAL_15]] : i32 -! CHECK: fir.store %[[VAL_16]] to %[[PRIV_X]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_13]], %[[VAL_11]] : index -! CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_11]] : (index) -> i32 -! CHECK: %[[IVLOAD:.*]] = fir.load %[[PRIV_J]] : !fir.ref -! CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] -! CHECK: fir.result %[[VAL_17]], %[[IVINC]] : index, i32 +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_6:.*]]) : i32 = (%[[ONE]]) to (%[[VAL_3]]) inclusive step (%[[VAL_5]]) { +! CHECK: fir.store %[[VAL_6]] to %[[PRIV_I]] : !fir.ref +! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 +! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i32) -> index +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_4]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> index +! CHECK: %[[VAL_11:.*]] = arith.constant 1 : index +! CHECK: %[[LB:.*]] = fir.convert %[[VAL_8]] : (index) -> i32 +! CHECK: %[[VAL_12:.*]]:2 = fir.do_loop %[[VAL_13:[^ ]*]] = +! CHECK-SAME: %[[VAL_8]] to %[[VAL_10]] step %[[VAL_11]] +! CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i32) { +! CHECK: fir.store %[[IV]] to %[[PRIV_J]] : !fir.ref +! CHECK: %[[LOAD:.*]] = fir.load %[[PRIV_I]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[PRIV_J]] : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.addi %[[LOAD]], %[[VAL_15]] : i32 +! CHECK: fir.store %[[VAL_16]] to %[[PRIV_X]] : !fir.ref +! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_13]], %[[VAL_11]] : index +! CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_11]] : (index) -> i32 +! CHECK: %[[IVLOAD:.*]] = fir.load %[[PRIV_J]] : !fir.ref +! CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] +! CHECK: fir.result %[[VAL_17]], %[[IVINC]] : index, i32 +! CHECK: } +! CHECK: fir.store %[[VAL_12]]#1 to %[[PRIV_J]] : !fir.ref +! CHECK: omp.yield ! CHECK: } -! CHECK: fir.store %[[VAL_12]]#1 to %[[PRIV_J]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 b/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 index 8b75ecbaae8c73c9741dad7b9e465df452dfb371..2e68d25a15edc118a3ad5b6c96f7240735188019 100644 --- a/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 +++ b/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 @@ -249,31 +249,33 @@ subroutine simple_loop_1 real, allocatable :: r; ! FIRDialect: omp.parallel !$OMP PARALLEL PRIVATE(r) - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! FIRDialect: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! FIRDialect: omp.wsloop { + ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref + ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref + ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! FIRDialect: omp.yield - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: omp.yield + ! FIRDialect: omp.terminator + ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> + ! FIRDialect: fir.if {{%.*}} { + ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> + ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap + ! FIRDialect: fir.freemem [[AD]] : !fir.heap + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> !$OMP END DO ! FIRDialect: omp.terminator !$OMP END PARALLEL @@ -285,31 +287,33 @@ subroutine simple_loop_2 real, allocatable :: r; ! FIRDialect: omp.parallel !$OMP PARALLEL - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! FIRDialect: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! FIRDialect: omp.wsloop { + ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO PRIVATE(r) do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref + ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref + ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! FIRDialect: omp.yield - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: omp.yield + ! FIRDialect: omp.terminator + ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> + ! FIRDialect: fir.if {{%.*}} { + ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> + ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap + ! FIRDialect: fir.freemem [[AD]] : !fir.heap + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> !$OMP END DO ! FIRDialect: omp.terminator !$OMP END PARALLEL @@ -320,31 +324,33 @@ subroutine simple_loop_3 integer :: i real, allocatable :: r; ! FIRDialect: omp.parallel - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! FIRDialect: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! FIRDialect: omp.wsloop { + ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO PRIVATE(r) do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref + ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref + ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! FIRDialect: omp.yield - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: omp.yield + ! FIRDialect: omp.terminator + ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> + ! FIRDialect: fir.if {{%.*}} { + ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> + ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap + ! FIRDialect: fir.freemem [[AD]] : !fir.heap + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> !$OMP END PARALLEL DO ! FIRDialect: omp.terminator end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 b/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 index 0c0834cfafe9c3d8123f195f2064e7e57b7ea422..7730ab87a719af248a8bf2da56b2dba8cd45dbb3 100644 --- a/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 +++ b/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 @@ -1,7 +1,7 @@ ! REQUIRES: openmp_runtime !RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion-on-func-opt | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect,LLVMDialect" +!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect,LLVMDialect" !=============================================================================== ! Parallel sections construct diff --git a/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 b/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 index 6eb39a2f63725f343ae5a31b89c8c7d847564977..490f6d0cf7bcabc5ca649790fc7ce0cca65b29ef 100644 --- a/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 +++ b/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 @@ -17,10 +17,14 @@ subroutine omp_do_firstprivate(a) ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 ! CHECK-NEXT: %[[UB:.*]] = fir.load %[[CLONE]] : !fir.ref ! CHECK-NEXT: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: omp.wsloop for (%[[ARG1:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) + ! CHECK-NEXT: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { ! CHECK-NEXT: fir.store %[[ARG1]] to %[[REF]] : !fir.ref ! CHECK-NEXT: fir.call @_QPfoo(%[[REF]], %[[CLONE]]) {{.*}}: (!fir.ref, !fir.ref) -> () ! CHECK-NEXT: omp.yield + ! CHECK-NEXT: } + ! CHECK-NEXT: omp.terminator + ! CHECK-NEXT: } do i=1, a call foo(i, a) end do @@ -48,10 +52,14 @@ subroutine omp_do_firstprivate2(a, n) ! CHECK: %[[LB:.*]] = fir.load %[[CLONE]] : !fir.ref ! CHECK-NEXT: %[[UB:.*]] = fir.load %[[CLONE1]] : !fir.ref ! CHECK-NEXT: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: omp.wsloop for (%[[ARG2:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) + ! CHECK-NEXT: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[ARG2:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { ! CHECK-NEXT: fir.store %[[ARG2]] to %[[REF]] : !fir.ref ! CHECK-NEXT: fir.call @_QPfoo(%[[REF]], %[[CLONE]]) {{.*}}: (!fir.ref, !fir.ref) -> () ! CHECK-NEXT: omp.yield + ! CHECK-NEXT: } + ! CHECK-NEXT: omp.terminator + ! CHECK-NEXT: } do i= a, n call foo(i, a) end do diff --git a/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 b/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 index 8649cf284ffd9d070540b7852ec41476e0f72ddc..630d647bc64b60ff070da462e61c10079a81fc79 100644 --- a/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 +++ b/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 @@ -6,19 +6,21 @@ subroutine simple_parallel_do integer :: i ! CHECK: omp.parallel - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.yield + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -32,19 +34,21 @@ subroutine parallel_do_with_parallel_clauses(cond, nt) ! CHECK: %[[COND_CVT:.*]] = fir.convert %[[COND]] : (!fir.logical<4>) -> i1 ! CHECK: %[[NT:.*]] = fir.load %[[NT_REF]] : !fir.ref ! CHECK: omp.parallel if(%[[COND_CVT]] : i1) num_threads(%[[NT]] : i32) proc_bind(close) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO IF(cond) NUM_THREADS(nt) PROC_BIND(close) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.yield + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -55,19 +59,21 @@ subroutine parallel_do_with_clauses(nt) integer :: i ! CHECK: %[[NT:.*]] = fir.load %[[NT_REF]] : !fir.ref ! CHECK: omp.parallel num_threads(%[[NT]] : i32) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop schedule(dynamic) for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop schedule(dynamic) { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) !$OMP PARALLEL DO NUM_THREADS(nt) SCHEDULE(dynamic) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.yield + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -83,18 +89,19 @@ subroutine parallel_do_with_privatisation_clauses(cond,nt) integer :: nt integer :: i ! CHECK: omp.parallel - ! CHECK: %[[PRIVATE_COND_REF:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} - ! CHECK: %[[PRIVATE_NT_REF:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} - ! CHECK: %[[NT_VAL:.*]] = fir.load %[[NT_REF]] : !fir.ref - ! CHECK: fir.store %[[NT_VAL]] to %[[PRIVATE_NT_REF]] : !fir.ref - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[PRIVATE_COND_REF:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} + ! CHECK: %[[PRIVATE_NT_REF:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} + ! CHECK: %[[NT_VAL:.*]] = fir.load %[[NT_REF]] : !fir.ref + ! CHECK: fir.store %[[NT_VAL]] to %[[PRIVATE_NT_REF]] : !fir.ref + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO PRIVATE(cond) FIRSTPRIVATE(nt) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 ! CHECK: %[[PRIVATE_COND_VAL:.*]] = fir.load %[[PRIVATE_COND_REF]] : !fir.ref> ! CHECK: %[[PRIVATE_COND_VAL_CVT:.*]] = fir.convert %[[PRIVATE_COND_VAL]] : (!fir.logical<4>) -> i1 @@ -104,7 +111,8 @@ subroutine parallel_do_with_privatisation_clauses(cond,nt) print*, i, cond, nt end do ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -140,10 +148,13 @@ end subroutine parallel_private_do ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV]] : !fir.ref -! CHECK: fir.call @_QPfoo(%[[I_PRIV]], %[[COND_ADDR]], %[[NT_ADDR]]) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV]] : !fir.ref +! CHECK: fir.call @_QPfoo(%[[I_PRIV]], %[[COND_ADDR]], %[[NT_ADDR]]) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -182,10 +193,13 @@ end subroutine omp_parallel_multiple_firstprivate_do ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref -! CHECK: fir.call @_QPbar(%[[I_PRIV_ADDR]], %[[A_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref +! CHECK: fir.call @_QPbar(%[[I_PRIV_ADDR]], %[[A_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -224,10 +238,13 @@ end subroutine parallel_do_private ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref -! CHECK: fir.call @_QPfoo(%[[I_PRIV_ADDR]], %[[COND_ADDR]], %[[NT_ADDR]]) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref +! CHECK: fir.call @_QPfoo(%[[I_PRIV_ADDR]], %[[COND_ADDR]], %[[NT_ADDR]]) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -266,10 +283,13 @@ end subroutine omp_parallel_do_multiple_firstprivate ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref -! CHECK: fir.call @_QPbar(%[[I_PRIV_ADDR]], %[[A_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref +! CHECK: fir.call @_QPbar(%[[I_PRIV_ADDR]], %[[A_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 b/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 index d6c10bdee88d54977d684bc88ef4657ff833b18c..32cc6d17c420be00db13ae059abaf6dd42cd8a37 100644 --- a/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 +++ b/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 @@ -77,24 +77,27 @@ end ! CHECK: %[[VAL_3:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_4:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_6:.*]]) : i32 = (%[[VAL_3]]) to (%[[VAL_4]]) inclusive step (%[[VAL_5]]) { -! CHECK: fir.store %[[VAL_6]] to %[[VAL_0]] : !fir.ref -! CHECK: cf.br ^bb1 -! CHECK: ^bb1: -! CHECK: %[[VAL_7:.*]] = arith.constant 3 : i32 -! CHECK: fir.store %[[VAL_7]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_10:.*]] = arith.cmpi sgt, %[[VAL_8]], %[[VAL_9]] : i32 -! CHECK: cf.cond_br %[[VAL_10]], ^bb2, ^bb3 -! CHECK: ^bb2: -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.constant false -! CHECK: %[[VAL_13:.*]] = arith.constant false -! CHECK: %[[VAL_14:.*]] = fir.call @_FortranAStopStatement(%[[VAL_11]], %[[VAL_12]], %[[VAL_13]]) {{.*}} : (i32, i1, i1) -> none -! CHECK: omp.yield -! CHECK: ^bb3: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_6:.*]]) : i32 = (%[[VAL_3]]) to (%[[VAL_4]]) inclusive step (%[[VAL_5]]) { +! CHECK: fir.store %[[VAL_6]] to %[[VAL_0]] : !fir.ref +! CHECK: cf.br ^bb1 +! CHECK: ^bb1: +! CHECK: %[[VAL_7:.*]] = arith.constant 3 : i32 +! CHECK: fir.store %[[VAL_7]] to %[[VAL_2]] : !fir.ref +! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 +! CHECK: %[[VAL_10:.*]] = arith.cmpi sgt, %[[VAL_8]], %[[VAL_9]] : i32 +! CHECK: cf.cond_br %[[VAL_10]], ^bb2, ^bb3 +! CHECK: ^bb2: +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_2]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = arith.constant false +! CHECK: %[[VAL_13:.*]] = arith.constant false +! CHECK: %[[VAL_14:.*]] = fir.call @_FortranAStopStatement(%[[VAL_11]], %[[VAL_12]], %[[VAL_13]]) {{.*}} : (i32, i1, i1) -> none +! CHECK: omp.yield +! CHECK: ^bb3: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: cf.br ^bb1 ! CHECK: ^bb1: diff --git a/flang/test/Lower/OpenMP/FIR/target.f90 b/flang/test/Lower/OpenMP/FIR/target.f90 index ca3162340d7846261bbac7479a88c79aeafc066a..a7344e02cf7cca09f051f4b542fcea8604e0fe1a 100644 --- a/flang/test/Lower/OpenMP/FIR/target.f90 +++ b/flang/test/Lower/OpenMP/FIR/target.f90 @@ -487,7 +487,8 @@ subroutine omp_target_parallel_do !CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 !CHECK: %[[VAL_6:.*]] = arith.constant 1024 : i32 !CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 - !CHECK: omp.wsloop for (%[[VAL_8:.*]]) : i32 = (%[[VAL_5]]) to (%[[VAL_6]]) inclusive step (%[[VAL_7]]) { + !CHECK: omp.wsloop { + !CHECK: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_5]]) to (%[[VAL_6]]) inclusive step (%[[VAL_7]]) { !CHECK: fir.store %[[VAL_8]] to %[[VAL_4]] : !fir.ref !CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 !CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_4]] : !fir.ref @@ -501,6 +502,8 @@ subroutine omp_target_parallel_do end do !CHECK: omp.yield !CHECK: } + !CHECK: omp.terminator + !CHECK: } !CHECK: omp.terminator !CHECK: } !CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/FIR/unstructured.f90 b/flang/test/Lower/OpenMP/FIR/unstructured.f90 index bfaf38b7ef1afc5f4620dd2d2add5e9988551d9a..6d1c9aab146401e6b8107ab4b890f138d4f06f26 100644 --- a/flang/test/Lower/OpenMP/FIR/unstructured.f90 +++ b/flang/test/Lower/OpenMP/FIR/unstructured.f90 @@ -67,27 +67,33 @@ end ! CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 ! CHECK: cond_br %{{[0-9]*}}, ^bb2, ^bb4 ! CHECK: ^bb2: // pred: ^bb1 -! CHECK: omp.wsloop for (%[[ARG1:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG1]] to %[[ALLOCA_2]] : !fir.ref -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD_1:.*]] = fir.load %[[ALLOCA_2]] : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_1]]) -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest (%[[ARG1:.*]]) : {{.*}} { +! CHECK: fir.store %[[ARG1]] to %[[ALLOCA_2]] : !fir.ref +! CHECK: @_FortranAioBeginExternalListOutput +! CHECK: %[[LOAD_1:.*]] = fir.load %[[ALLOCA_2]] : !fir.ref +! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_1]]) +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } -! CHECK: omp.wsloop for (%[[ARG2:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG2]] to %[[ALLOCA_1]] : !fir.ref -! CHECK: br ^bb1 -! CHECK: ^bb2: // 2 preds: ^bb1, ^bb5 -! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb6 -! CHECK: ^bb3: // pred: ^bb2 -! CHECK: cond_br %{{[0-9]*}}, ^bb4, ^bb5 -! CHECK: ^bb4: // pred: ^bb3 -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD_2:.*]] = fir.load %[[ALLOCA_K]] : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_2]]) -! CHECK: br ^bb2 -! CHECK: ^bb6: // 2 preds: ^bb2, ^bb4 -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest (%[[ARG2:.*]]) : {{.*}} { +! CHECK: fir.store %[[ARG2]] to %[[ALLOCA_1]] : !fir.ref +! CHECK: br ^bb1 +! CHECK: ^bb2: // 2 preds: ^bb1, ^bb5 +! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb6 +! CHECK: ^bb3: // pred: ^bb2 +! CHECK: cond_br %{{[0-9]*}}, ^bb4, ^bb5 +! CHECK: ^bb4: // pred: ^bb3 +! CHECK: @_FortranAioBeginExternalListOutput +! CHECK: %[[LOAD_2:.*]] = fir.load %[[ALLOCA_K]] : !fir.ref +! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_2]]) +! CHECK: br ^bb2 +! CHECK: ^bb6: // 2 preds: ^bb2, ^bb4 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: br ^bb1 ! CHECK: ^bb4: // pred: ^bb1 @@ -117,20 +123,23 @@ end ! CHECK-LABEL: func @_QPss4{{.*}} { ! CHECK: omp.parallel { ! CHECK: %[[ALLOCA:.*]] = fir.alloca i32 {{{.*}}, pinned} -! CHECK: omp.wsloop for (%[[ARG:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG]] to %[[ALLOCA]] : !fir.ref -! CHECK: %[[COND:.*]] = arith.cmpi eq, %{{.*}}, %{{.*}} -! CHECK: %[[COND_XOR:.*]] = arith.xori %[[COND]], %{{.*}} -! CHECK: fir.if %[[COND_XOR]] { -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA]] : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD]]) -! CHECK: } else { -! CHECK: } -! CHECK-NEXT: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest (%[[ARG:.*]]) : {{.*}} { +! CHECK: fir.store %[[ARG]] to %[[ALLOCA]] : !fir.ref +! CHECK: %[[COND:.*]] = arith.cmpi eq, %{{.*}}, %{{.*}} +! CHECK: %[[COND_XOR:.*]] = arith.xori %[[COND]], %{{.*}} +! CHECK: fir.if %[[COND_XOR]] { +! CHECK: @_FortranAioBeginExternalListOutput +! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA]] : !fir.ref +! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD]]) +! CHECK: } else { +! CHECK: } +! CHECK-NEXT: omp.yield +! CHECK-NEXT: } +! CHECK-NEXT: omp.terminator +! CHECK-NEXT: } +! CHECK: omp.terminator ! CHECK-NEXT: } -! CHECK: omp.terminator -! CHECK-NEXT:} subroutine ss4(n) ! CYCLE in OpenMP wsloop constructs !$omp parallel do i = 1, 3 @@ -146,20 +155,23 @@ end ! CHECK-LABEL: func @_QPss5() { ! CHECK: omp.parallel { -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB3:.*]] -! CHECK: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK: ^[[BB3]]: -! CHECK: br ^[[BB2]] -! CHECK: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB3:.*]] +! CHECK: ^[[BB4]]: +! CHECK: br ^[[BB6]] +! CHECK: ^[[BB3]]: +! CHECK: br ^[[BB2]] +! CHECK: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -186,20 +198,23 @@ end ! CHECK: ^[[BB1_OUTER]]: ! CHECK: cond_br %{{.*}}, ^[[BB2_OUTER:.*]], ^[[BB3_OUTER:.*]] ! CHECK: ^[[BB2_OUTER]]: -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK: ^[[BB5]] -! CHECK: br ^[[BB2]] -! CHECK: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] +! CHECK: ^[[BB4]]: +! CHECK: br ^[[BB6]] +! CHECK: ^[[BB5]] +! CHECK: br ^[[BB2]] +! CHECK: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: br ^[[BB1_OUTER]] ! CHECK: ^[[BB3_OUTER]]: @@ -230,20 +245,23 @@ end ! CHECK: cond_br %{{.*}}, ^[[BB2_OUTER:.*]], ^[[BB3_OUTER:.*]] ! CHECK-NEXT: ^[[BB2_OUTER:.*]]: ! CHECK: omp.parallel { -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK-NEXT: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK-NEXT: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK-NEXT: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK-NEXT: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK-NEXT: ^[[BB5]]: -! CHECK: br ^[[BB2]] -! CHECK-NEXT: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK-NEXT: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK-NEXT: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK-NEXT: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] +! CHECK-NEXT: ^[[BB4]]: +! CHECK: br ^[[BB6]] +! CHECK-NEXT: ^[[BB5]]: +! CHECK: br ^[[BB2]] +! CHECK-NEXT: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -268,20 +286,23 @@ end ! CHECK-LABEL: func @_QPss8() { ! CHECK: omp.parallel { -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK-NEXT: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK: ^[[BB4]]: -! CHECK-NEXT: br ^[[BB6]] -! CHECK: ^[[BB5]]: -! CHECK: br ^[[BB2]] -! CHECK-NEXT: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK-NEXT: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] +! CHECK: ^[[BB4]]: +! CHECK-NEXT: br ^[[BB6]] +! CHECK: ^[[BB5]]: +! CHECK: br ^[[BB2]] +! CHECK-NEXT: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 index 4030f46299d0b0b55bd3bfbb3c2fab140f8f7953..e4b85fb447767f4778a7be6b39de69eaf448d80c 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 @@ -19,11 +19,14 @@ do i=1, 9 ! CHECK: %[[VAL_3:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 4 : i32 -! CHECK: omp.wsloop schedule(static = %[[VAL_5]] : i32) nowait for (%[[ARG0:.*]]) : i32 = (%[[VAL_2]]) to (%[[VAL_3]]) inclusive step (%[[VAL_4]]) { -! CHECK: fir.store %[[ARG0]] to %[[STORE_IV:.*]] : !fir.ref -! CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]] : !fir.ref -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield +! CHECK: omp.wsloop schedule(static = %[[VAL_5]] : i32) nowait { +! CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[VAL_2]]) to (%[[VAL_3]]) inclusive step (%[[VAL_4]]) { +! CHECK: fir.store %[[ARG0]] to %[[STORE_IV:.*]] : !fir.ref +! CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]] : !fir.ref +! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } end do @@ -37,13 +40,16 @@ do i=1, 9 ! CHECK: %[[VAL_15:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_17:.*]] = arith.constant 4 : i32 -! CHECK: omp.wsloop schedule(static = %[[VAL_17]] : i32) nowait for (%[[ARG1:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { -! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref -! CHECK: %[[VAL_24:.*]] = arith.constant 2 : i32 -! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_24]], %[[LOAD_IV1]] : i32 -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_25]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield +! CHECK: omp.wsloop schedule(static = %[[VAL_17]] : i32) nowait { +! CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { +! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref +! CHECK: %[[VAL_24:.*]] = arith.constant 2 : i32 +! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_24]], %[[LOAD_IV1]] : i32 +! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_25]]) {{.*}}: (!fir.ref, i32) -> i1 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } end do @@ -61,13 +67,16 @@ end do ! CHECK: %[[VAL_30:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_31:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: omp.wsloop schedule(static = %[[VAL_32]] : i32) nowait for (%[[ARG2:.*]]) : i32 = (%[[VAL_29]]) to (%[[VAL_30]]) inclusive step (%[[VAL_31]]) { -! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]] : !fir.ref -! CHECK: %[[VAL_39:.*]] = arith.constant 3 : i32 -! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]] : !fir.ref -! CHECK: %[[VAL_40:.*]] = arith.muli %[[VAL_39]], %[[LOAD_IV2]] : i32 -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_40]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield +! CHECK: omp.wsloop schedule(static = %[[VAL_32]] : i32) nowait { +! CHECK-NEXT: omp.loop_nest (%[[ARG2:.*]]) : i32 = (%[[VAL_29]]) to (%[[VAL_30]]) inclusive step (%[[VAL_31]]) { +! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]] : !fir.ref +! CHECK: %[[VAL_39:.*]] = arith.constant 3 : i32 +! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]] : !fir.ref +! CHECK: %[[VAL_40:.*]] = arith.muli %[[VAL_39]], %[[LOAD_IV2]] : i32 +! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_40]]) {{.*}}: (!fir.ref, i32) -> i1 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: return ! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 index 933fc0910e3382c323d0e77f540255099e565ca1..a2ba3ebfe1967d86c4d6ce95e1287d9dce24ee01 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 @@ -39,19 +39,22 @@ program wsloop_collapse do i = 1, a do j= 1, b do k = 1, c -! CHECK: omp.wsloop for (%[[ARG0:.*]], %[[ARG1:.*]], %[[ARG2:.*]]) : i32 = (%[[VAL_20]], %[[VAL_23]], %[[VAL_26]]) to (%[[VAL_21]], %[[VAL_24]], %[[VAL_27]]) inclusive step (%[[VAL_22]], %[[VAL_25]], %[[VAL_28]]) { -! CHECK: fir.store %[[ARG0]] to %[[STORE_IV0:.*]] : !fir.ref -! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref -! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_6]] : !fir.ref -! CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = arith.addi %[[VAL_12]], %[[LOAD_IV0]] : i32 -! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref -! CHECK: %[[VAL_14:.*]] = arith.addi %[[VAL_13]], %[[LOAD_IV1]] : i32 -! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_14]], %[[LOAD_IV2]] : i32 -! CHECK: fir.store %[[VAL_15]] to %[[VAL_6]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]], %[[ARG1:.*]], %[[ARG2:.*]]) : i32 = (%[[VAL_20]], %[[VAL_23]], %[[VAL_26]]) to (%[[VAL_21]], %[[VAL_24]], %[[VAL_27]]) inclusive step (%[[VAL_22]], %[[VAL_25]], %[[VAL_28]]) { +! CHECK: fir.store %[[ARG0]] to %[[STORE_IV0:.*]] : !fir.ref +! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref +! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_6]] : !fir.ref +! CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]] : !fir.ref +! CHECK: %[[VAL_13:.*]] = arith.addi %[[VAL_12]], %[[LOAD_IV0]] : i32 +! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref +! CHECK: %[[VAL_14:.*]] = arith.addi %[[VAL_13]], %[[LOAD_IV1]] : i32 +! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_14]], %[[LOAD_IV2]] : i32 +! CHECK: fir.store %[[VAL_15]] to %[[VAL_6]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } x = x + i + j + k end do diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 index 1c381475f6cbb12a0a8bf6173393993811fa262f..941885bdb1e384f7864fd628e43db21703b6c5eb 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 @@ -11,23 +11,27 @@ program wsloop_dynamic !CHECK: omp.parallel { !$OMP DO SCHEDULE(monotonic:dynamic) -!CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(dynamic, monotonic) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref +!CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} +!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 +!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 +!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 +!CHECK: omp.wsloop schedule(dynamic, monotonic) nowait { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { +!CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref do i=1, 9 print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 +!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput +!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref +!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 +!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 end do -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$OMP END DO NOWAIT !$OMP END PARALLEL diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 index 3f425200b8fa48d83f2cab708d1832940b2999ff..96a3e71f34b1eaba442d6d562c880df0da168e5d 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 @@ -12,24 +12,27 @@ program wsloop_dynamic !CHECK: omp.parallel { !$OMP DO SCHEDULE(nonmonotonic:dynamic) -!CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(dynamic, nonmonotonic) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref +!CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} +!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 +!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 +!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 +!CHECK: omp.wsloop schedule(dynamic, nonmonotonic) nowait { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) +!CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref do i=1, 9 print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 +!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput +!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref +!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 +!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 end do -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$OMP END DO NOWAIT !$OMP END PARALLEL diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 index 7548d7a597228a29ab2a2cdd719ab6a8debde72e..fec027608d991365d1eb921e84fa00cc06ee08f7 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 @@ -6,9 +6,12 @@ subroutine wsloop_ordered_no_para() integer :: a(10), i -! CHECK: omp.wsloop ordered(0) for (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop ordered(0) { +! CHECK-NEXT: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator +! CHECK: } !$omp do ordered do i = 2, 10 @@ -25,9 +28,12 @@ subroutine wsloop_ordered_with_para() integer :: a(10), i ! CHECK: func @_QPwsloop_ordered_with_para() { -! CHECK: omp.wsloop ordered(1) for (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop ordered(1) { +! CHECK-NEXT: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator +! CHECK: } !$omp do ordered(1) do i = 2, 10 diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 index 08f5a0fcdbae67068cdab5adba9c5ee178b91ad7..b6dfec09007e54a82cbd8d6a9bad9eebd2a2db10 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 @@ -80,13 +80,16 @@ ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 +! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -116,14 +119,17 @@ end subroutine ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> f32 -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_9]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> f32 +! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_9]], %[[VAL_11]] fastmath : f32 +! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -152,13 +158,16 @@ end subroutine ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 +! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -187,14 +196,17 @@ end subroutine ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> f32 -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_10]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> f32 +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_10]], %[[VAL_11]] fastmath : f32 +! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -229,21 +241,24 @@ end subroutine ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) for (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_16]] : i32 -! CHECK: fir.store %[[VAL_17]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = arith.addi %[[VAL_21]], %[[VAL_22]] : i32 -! CHECK: fir.store %[[VAL_23]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_16]] : i32 +! CHECK: fir.store %[[VAL_17]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: fir.store %[[VAL_20]] to %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_23:.*]] = arith.addi %[[VAL_21]], %[[VAL_22]] : i32 +! CHECK: fir.store %[[VAL_23]] to %[[VAL_13]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -282,24 +297,27 @@ end subroutine ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) for (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]] : (i32) -> f32 -! CHECK: %[[VAL_18:.*]] = arith.addf %[[VAL_15]], %[[VAL_17]] fastmath : f32 -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> f32 -! CHECK: %[[VAL_22:.*]] = arith.addf %[[VAL_19]], %[[VAL_21]] fastmath : f32 -! CHECK: fir.store %[[VAL_22]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: fir.store %[[VAL_26]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]] : (i32) -> f32 +! CHECK: %[[VAL_18:.*]] = arith.addf %[[VAL_15]], %[[VAL_17]] fastmath : f32 +! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> f32 +! CHECK: %[[VAL_22:.*]] = arith.addf %[[VAL_19]], %[[VAL_21]] fastmath : f32 +! CHECK: fir.store %[[VAL_22]] to %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 +! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 +! CHECK: fir.store %[[VAL_26]] to %[[VAL_13]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -341,28 +359,31 @@ end subroutine ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_2]] -> %[[VAL_13:.*]] : !fir.ref, @add_reduction_byref_i64 %[[VAL_3]] -> %[[VAL_14:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_4]] -> %[[VAL_15:.*]] : !fir.ref, @add_reduction_byref_f64 %[[VAL_1]] -> %[[VAL_16:.*]] : !fir.ref) for (%[[VAL_17:.*]]) : i32 = (%[[VAL_10]]) to (%[[VAL_11]]) inclusive step (%[[VAL_12]]) { -! CHECK: fir.store %[[VAL_17]] to %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_22]] : (i32) -> i64 -! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_21]], %[[VAL_23]] : i64 -! CHECK: fir.store %[[VAL_24]] to %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_26]] : (i32) -> f32 -! CHECK: %[[VAL_28:.*]] = arith.addf %[[VAL_25]], %[[VAL_27]] fastmath : f32 -! CHECK: fir.store %[[VAL_28]] to %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_16]] : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_30]] : (i32) -> f64 -! CHECK: %[[VAL_32:.*]] = arith.addf %[[VAL_29]], %[[VAL_31]] fastmath : f64 -! CHECK: fir.store %[[VAL_32]] to %[[VAL_16]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_2]] -> %[[VAL_13:.*]] : !fir.ref, @add_reduction_byref_i64 %[[VAL_3]] -> %[[VAL_14:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_4]] -> %[[VAL_15:.*]] : !fir.ref, @add_reduction_byref_f64 %[[VAL_1]] -> %[[VAL_16:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_17:.*]]) : i32 = (%[[VAL_10]]) to (%[[VAL_11]]) inclusive step (%[[VAL_12]]) { +! CHECK: fir.store %[[VAL_17]] to %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: fir.store %[[VAL_20]] to %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_14]] : !fir.ref +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_22]] : (i32) -> i64 +! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_21]], %[[VAL_23]] : i64 +! CHECK: fir.store %[[VAL_24]] to %[[VAL_14]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]] : !fir.ref +! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_26]] : (i32) -> f32 +! CHECK: %[[VAL_28:.*]] = arith.addf %[[VAL_25]], %[[VAL_27]] fastmath : f32 +! CHECK: fir.store %[[VAL_28]] to %[[VAL_15]] : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_16]] : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_30]] : (i32) -> f64 +! CHECK: %[[VAL_32:.*]] = arith.addf %[[VAL_29]], %[[VAL_31]] fastmath : f64 +! CHECK: fir.store %[[VAL_32]] to %[[VAL_16]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 index dc96b875f745f2d953e3f0fca22f326b9af42b2a..e0b9330b1a6d5cf8240a40674dcd13a693ebe822 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 @@ -55,13 +55,16 @@ ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 +! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -91,14 +94,17 @@ end subroutine ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> f32 -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_9]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> f32 +! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_9]], %[[VAL_11]] fastmath : f32 +! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -127,13 +133,16 @@ end subroutine ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 +! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -162,14 +171,17 @@ end subroutine ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) for (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> f32 -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_10]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { +! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> f32 +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_10]], %[[VAL_11]] fastmath : f32 +! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -204,21 +216,24 @@ end subroutine ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) for (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_16]] : i32 -! CHECK: fir.store %[[VAL_17]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = arith.addi %[[VAL_21]], %[[VAL_22]] : i32 -! CHECK: fir.store %[[VAL_23]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_16]] : i32 +! CHECK: fir.store %[[VAL_17]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: fir.store %[[VAL_20]] to %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_23:.*]] = arith.addi %[[VAL_21]], %[[VAL_22]] : i32 +! CHECK: fir.store %[[VAL_23]] to %[[VAL_13]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -257,24 +272,27 @@ end subroutine ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) for (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]] : (i32) -> f32 -! CHECK: %[[VAL_18:.*]] = arith.addf %[[VAL_15]], %[[VAL_17]] fastmath : f32 -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> f32 -! CHECK: %[[VAL_22:.*]] = arith.addf %[[VAL_19]], %[[VAL_21]] fastmath : f32 -! CHECK: fir.store %[[VAL_22]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: fir.store %[[VAL_26]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]] : (i32) -> f32 +! CHECK: %[[VAL_18:.*]] = arith.addf %[[VAL_15]], %[[VAL_17]] fastmath : f32 +! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> f32 +! CHECK: %[[VAL_22:.*]] = arith.addf %[[VAL_19]], %[[VAL_21]] fastmath : f32 +! CHECK: fir.store %[[VAL_22]] to %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_7]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 +! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 +! CHECK: fir.store %[[VAL_26]] to %[[VAL_13]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -316,28 +334,31 @@ end subroutine ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_2]] -> %[[VAL_13:.*]] : !fir.ref, @add_reduction_i64 %[[VAL_3]] -> %[[VAL_14:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_4]] -> %[[VAL_15:.*]] : !fir.ref, @add_reduction_f64 %[[VAL_1]] -> %[[VAL_16:.*]] : !fir.ref) for (%[[VAL_17:.*]]) : i32 = (%[[VAL_10]]) to (%[[VAL_11]]) inclusive step (%[[VAL_12]]) { -! CHECK: fir.store %[[VAL_17]] to %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_22]] : (i32) -> i64 -! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_21]], %[[VAL_23]] : i64 -! CHECK: fir.store %[[VAL_24]] to %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_26]] : (i32) -> f32 -! CHECK: %[[VAL_28:.*]] = arith.addf %[[VAL_25]], %[[VAL_27]] fastmath : f32 -! CHECK: fir.store %[[VAL_28]] to %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_16]] : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_30]] : (i32) -> f64 -! CHECK: %[[VAL_32:.*]] = arith.addf %[[VAL_29]], %[[VAL_31]] fastmath : f64 -! CHECK: fir.store %[[VAL_32]] to %[[VAL_16]] : !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_2]] -> %[[VAL_13:.*]] : !fir.ref, @add_reduction_i64 %[[VAL_3]] -> %[[VAL_14:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_4]] -> %[[VAL_15:.*]] : !fir.ref, @add_reduction_f64 %[[VAL_1]] -> %[[VAL_16:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_17:.*]]) : i32 = (%[[VAL_10]]) to (%[[VAL_11]]) inclusive step (%[[VAL_12]]) { +! CHECK: fir.store %[[VAL_17]] to %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: fir.store %[[VAL_20]] to %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_14]] : !fir.ref +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_22]] : (i32) -> i64 +! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_21]], %[[VAL_23]] : i64 +! CHECK: fir.store %[[VAL_24]] to %[[VAL_14]] : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]] : !fir.ref +! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_26]] : (i32) -> f32 +! CHECK: %[[VAL_28:.*]] = arith.addf %[[VAL_25]], %[[VAL_27]] fastmath : f32 +! CHECK: fir.store %[[VAL_28]] to %[[VAL_15]] : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_16]] : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_9]] : !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_30]] : (i32) -> f64 +! CHECK: %[[VAL_32:.*]] = arith.addf %[[VAL_29]], %[[VAL_31]] fastmath : f64 +! CHECK: fir.store %[[VAL_32]] to %[[VAL_16]] : !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 index 6717597ff3b04d8f85c3b41b48d9145f848bb1fb..b25ab84f60fe916aefbf68fc93f168b858ad39bb 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 @@ -23,7 +23,8 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iandEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@iand_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for +!CHECK: omp.wsloop byref reduction(@iand_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref !CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] !CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref @@ -31,6 +32,7 @@ !CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_iand(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 index 9bc45f9f3a0d870af97e7d72ddcdc6792f02cd89..dfc140d7d5f61925b8f1b1d0f493b56c3fd8119e 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 @@ -13,7 +13,8 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iandEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[IAND_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for +!CHECK: omp.wsloop reduction(@[[IAND_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref !CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] !CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref @@ -21,6 +22,7 @@ !CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_iand(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 index 1baa59a510fa11cf3984a3617da30ba25f7ad075..56eb087bae5a0801b832b5f68bcfa5398e01af23 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 @@ -22,7 +22,8 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_ieorEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@ieor_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for +!CHECK: omp.wsloop byref reduction(@ieor_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref !CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] !CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref @@ -30,6 +31,7 @@ !CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_ieor(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 index 9c07d5ee20873b2a15f649f0d7854bc7cfeadfb1..1ddf82b828cb016d49aafb84dec5d03e8b88d937 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 @@ -13,7 +13,8 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_ieorEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[IEOR_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for +!CHECK: omp.wsloop reduction(@[[IEOR_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref !CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] !CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref @@ -21,6 +22,7 @@ !CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_ieor(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 index 5482ef33fc8aa926c37e9c21bf11a58a00559b01..e761d24cd303b6ade2f5cbb7806918f130ebabc6 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 @@ -22,7 +22,8 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iorEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@ior_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for +!CHECK: omp.wsloop byref reduction(@ior_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref !CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] !CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref @@ -30,6 +31,7 @@ !CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_ior(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 index 79cc8b2d892275dac4c813eae8996c3fd270e732..148dbc909babe921d4791f2eb91eda6dffc22f78 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 @@ -13,7 +13,8 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iorEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[IOR_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for +!CHECK: omp.wsloop reduction(@[[IOR_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref !CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] !CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref @@ -21,6 +22,7 @@ !CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_ior(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 index 696ff68b2059cd1b00d7e69657ecf9bf5368b848..17cd02a0ca7ff7bbae85fc96d83b8212b17353c0 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 @@ -36,21 +36,23 @@ ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 +! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 +! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -78,21 +80,23 @@ end subroutine ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 +! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 +! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -128,45 +132,47 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @eqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @eqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) for (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi eq, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi eq, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi eq, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @eqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @eqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 +! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 +! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_28:.*]] = arith.cmpi eq, %[[VAL_26]], %[[VAL_27]] : i1 +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 +! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_39:.*]] = arith.cmpi eq, %[[VAL_37]], %[[VAL_38]] : i1 +! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 +! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 +! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_50:.*]] = arith.cmpi eq, %[[VAL_48]], %[[VAL_49]] : i1 +! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 index 6dcb3952655eabd2c3a5be7815abfe63715a31a5..e714e45540c393fb392608e9a97552264f37dcce 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 @@ -30,21 +30,23 @@ ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 +! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 +! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -72,21 +74,23 @@ end subroutine ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 +! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 +! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -122,45 +126,47 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @eqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @eqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) for (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi eq, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi eq, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi eq, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @eqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @eqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 +! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 +! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_28:.*]] = arith.cmpi eq, %[[VAL_26]], %[[VAL_27]] : i1 +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 +! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_39:.*]] = arith.cmpi eq, %[[VAL_37]], %[[VAL_38]] : i1 +! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 +! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 +! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_50:.*]] = arith.cmpi eq, %[[VAL_48]], %[[VAL_49]] : i1 +! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 index a31abd0def56e16da67efac729c9b6e985281ac2..89d16c3191b26e72501924f2c013421aea63104c 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 @@ -37,21 +37,23 @@ ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 +! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 +! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -79,21 +81,23 @@ end subroutine ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 +! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 +! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -129,45 +133,47 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @neqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @neqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) for (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi ne, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi ne, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi ne, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @neqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @neqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 +! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 +! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_28:.*]] = arith.cmpi ne, %[[VAL_26]], %[[VAL_27]] : i1 +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 +! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_39:.*]] = arith.cmpi ne, %[[VAL_37]], %[[VAL_38]] : i1 +! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 +! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 +! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_50:.*]] = arith.cmpi ne, %[[VAL_48]], %[[VAL_49]] : i1 +! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 index 702c185e25ee401c99f332448f7b0c80b00e9f86..106e867f367b7da8e8bb4560577926c704168199 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 @@ -31,21 +31,23 @@ ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 +! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 +! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -73,21 +75,23 @@ end subroutine ! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref +! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 +! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 +! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> +! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -123,45 +127,47 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @neqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @neqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) for (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi ne, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi ne, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi ne, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @neqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @neqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 +! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 +! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_28:.*]] = arith.cmpi ne, %[[VAL_26]], %[[VAL_27]] : i1 +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 +! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_39:.*]] = arith.cmpi ne, %[[VAL_37]], %[[VAL_38]] : i1 +! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref +! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 +! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 +! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 +! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_50:.*]] = arith.cmpi ne, %[[VAL_48]], %[[VAL_49]] : i1 +! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> +! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 index 80b720e3aac1d10ffefedc61394561d4b14c9eb4..a4244d11a55867b3d1f1749c8e1d3dbaeb901473 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 @@ -32,25 +32,30 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi sgt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref +!CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpi sgt, %[[LPRV]], %[[Y_I]] : i32 +!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] +!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator !CHECK-LABEL: @_QPreduction_max_real !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_max_realEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield +!CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator subroutine reduction_max_int(y) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 index c3b821ea5912468c2c10767bca5e5dddf63e3bd2..e000bc36ca3fbb052ca79fc94d07dfa51100ea68 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 @@ -21,25 +21,30 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MAX_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi sgt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref +!CHECK: omp.wsloop reduction(@[[MAX_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpi sgt, %[[LPRV]], %[[Y_I]] : i32 +!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] +!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator !CHECK-LABEL: @_QPreduction_max_real !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_max_realEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MAX_DECLARE_F]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield +!CHECK: omp.wsloop reduction(@[[MAX_DECLARE_F]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator subroutine reduction_max_int(y) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 index b284f8e5d96721345b20349f869f7caa12947e29..17435e1a194ca4f94ea7269e72a7f2bad986f8ae 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 @@ -32,26 +32,30 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_min_intEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi slt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield +!CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpi slt, %[[LPRV]], %[[Y_I]] : i32 +!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] +!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator !CHECK-LABEL: @_QPreduction_min_real !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_min_realEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield +!CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator subroutine reduction_min_int(y) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 index ab33e180ed883dee446720b2175f3a9d40cb1f4e..1d18ece7297d4e0f15db599ae867e140819f169e 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 @@ -21,26 +21,30 @@ !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_min_intEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MIN_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi slt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield +!CHECK: omp.wsloop reduction(@[[MIN_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpi slt, %[[LPRV]], %[[Y_I]] : i32 +!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] +!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator !CHECK-LABEL: @_QPreduction_min_real !CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> !CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_min_realEx"} !CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MIN_DECLARE_F]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) for -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield +!CHECK: omp.wsloop reduction(@[[MIN_DECLARE_F]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest +!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref +!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] +!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref +!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 +!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: omp.terminator subroutine reduction_min_int(y) diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 index 2e3f8ca3c207dd0b53529bbd922226158707cd84..751e4c8c57094cc87a512a3300f11f1408da4a15 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 @@ -11,23 +11,26 @@ program wsloop_dynamic !CHECK: omp.parallel { !$OMP DO SCHEDULE(simd: runtime) -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(runtime, simd) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[STORE:.*]] : !fir.ref +!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 +!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 +!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 +!CHECK: omp.wsloop schedule(runtime, simd) nowait { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { +!CHECK: fir.store %[[I]] to %[[STORE:.*]] : !fir.ref do i=1, 9 print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[STORE]] : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 +!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput +!CHECK: %[[LOAD:.*]] = fir.load %[[STORE]] : !fir.ref +!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 +!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 end do -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$OMP END DO NOWAIT !$OMP END PARALLEL diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 index 4f34f30f3e7c98189cb2a648821ea6cbe0d89a0a..4bd876012278924da02bad5e694d49ce4289df33 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 @@ -14,26 +14,29 @@ program wsloop_variable integer(kind=16) :: i16, i16_lb real :: x -!CHECK: %[[TMP0:.*]] = arith.constant 1 : i32 -!CHECK: %[[TMP1:.*]] = arith.constant 100 : i32 -!CHECK: %[[TMP2:.*]] = fir.convert %[[TMP0]] : (i32) -> i64 -!CHECK: %[[TMP3:.*]] = fir.convert %{{.*}} : (i8) -> i64 -!CHECK: %[[TMP4:.*]] = fir.convert %{{.*}} : (i16) -> i64 -!CHECK: %[[TMP5:.*]] = fir.convert %{{.*}} : (i128) -> i64 -!CHECK: %[[TMP6:.*]] = fir.convert %[[TMP1]] : (i32) -> i64 -!CHECK: %[[TMP7:.*]] = fir.convert %{{.*}} : (i32) -> i64 -!CHECK: omp.wsloop for (%[[ARG0:.*]], %[[ARG1:.*]]) : i64 = (%[[TMP2]], %[[TMP5]]) to (%[[TMP3]], %[[TMP6]]) inclusive step (%[[TMP4]], %[[TMP7]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i64) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV0:.*]] : !fir.ref -!CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref -!CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]] : !fir.ref -!CHECK: %[[LOAD_IV0_I64:.*]] = fir.convert %[[LOAD_IV0]] : (i16) -> i64 -!CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref -!CHECK: %[[TMP10:.*]] = arith.addi %[[LOAD_IV0_I64]], %[[LOAD_IV1]] : i64 -!CHECK: %[[TMP11:.*]] = fir.convert %[[TMP10]] : (i64) -> f32 -!CHECK: fir.store %[[TMP11]] to %{{.*}} : !fir.ref -!CHECK: omp.yield -!CHECK: } +!CHECK: %[[TMP0:.*]] = arith.constant 1 : i32 +!CHECK: %[[TMP1:.*]] = arith.constant 100 : i32 +!CHECK: %[[TMP2:.*]] = fir.convert %[[TMP0]] : (i32) -> i64 +!CHECK: %[[TMP3:.*]] = fir.convert %{{.*}} : (i8) -> i64 +!CHECK: %[[TMP4:.*]] = fir.convert %{{.*}} : (i16) -> i64 +!CHECK: %[[TMP5:.*]] = fir.convert %{{.*}} : (i128) -> i64 +!CHECK: %[[TMP6:.*]] = fir.convert %[[TMP1]] : (i32) -> i64 +!CHECK: %[[TMP7:.*]] = fir.convert %{{.*}} : (i32) -> i64 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]], %[[ARG1:.*]]) : i64 = (%[[TMP2]], %[[TMP5]]) to (%[[TMP3]], %[[TMP6]]) inclusive step (%[[TMP4]], %[[TMP7]]) { +!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i64) -> i16 +!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV0:.*]] : !fir.ref +!CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref +!CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]] : !fir.ref +!CHECK: %[[LOAD_IV0_I64:.*]] = fir.convert %[[LOAD_IV0]] : (i16) -> i64 +!CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref +!CHECK: %[[TMP10:.*]] = arith.addi %[[LOAD_IV0_I64]], %[[LOAD_IV1]] : i64 +!CHECK: %[[TMP11:.*]] = fir.convert %[[TMP10]] : (i64) -> f32 +!CHECK: fir.store %[[TMP11]] to %{{.*}} : !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$omp do collapse(2) do i2 = 1, i1_ub, i2_s @@ -43,18 +46,20 @@ program wsloop_variable end do !$omp end do -!CHECK: %[[TMP12:.*]] = arith.constant 1 : i32 -!CHECK: %[[TMP13:.*]] = fir.convert %{{.*}} : (i8) -> i32 -!CHECK: %[[TMP14:.*]] = fir.convert %{{.*}} : (i64) -> i32 -!CHECK: omp.wsloop for (%[[ARG0:.*]]) : i32 = (%[[TMP12]]) to (%[[TMP13]]) inclusive step (%[[TMP14]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE3:.*]] : !fir.ref -!CHECK: %[[LOAD3:.*]] = fir.load %[[STORE3]] : !fir.ref -!CHECK: %[[TMP16:.*]] = fir.convert %[[LOAD3]] : (i16) -> f32 - -!CHECK: fir.store %[[TMP16]] to %{{.*}} : !fir.ref -!CHECK: omp.yield -!CHECK: } +!CHECK: %[[TMP12:.*]] = arith.constant 1 : i32 +!CHECK: %[[TMP13:.*]] = fir.convert %{{.*}} : (i8) -> i32 +!CHECK: %[[TMP14:.*]] = fir.convert %{{.*}} : (i64) -> i32 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[TMP12]]) to (%[[TMP13]]) inclusive step (%[[TMP14]]) { +!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 +!CHECK: fir.store %[[ARG0_I16]] to %[[STORE3:.*]] : !fir.ref +!CHECK: %[[LOAD3:.*]] = fir.load %[[STORE3]] : !fir.ref +!CHECK: %[[TMP16:.*]] = fir.convert %[[LOAD3]] : (i16) -> f32 +!CHECK: fir.store %[[TMP16]] to %{{.*}} : !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$omp do do i2 = 1, i1_ub, i8_s @@ -62,17 +67,20 @@ program wsloop_variable end do !$omp end do -!CHECK: %[[TMP17:.*]] = fir.convert %{{.*}} : (i8) -> i64 -!CHECK: %[[TMP18:.*]] = fir.convert %{{.*}} : (i16) -> i64 -!CHECK: %[[TMP19:.*]] = fir.convert %{{.*}} : (i32) -> i64 -!CHECK: omp.wsloop for (%[[ARG1:.*]]) : i64 = (%[[TMP17]]) to (%[[TMP18]]) inclusive step (%[[TMP19]]) { -!CHECK: %[[ARG1_I128:.*]] = fir.convert %[[ARG1]] : (i64) -> i128 -!CHECK: fir.store %[[ARG1_I128]] to %[[STORE4:.*]] : !fir.ref -!CHECK: %[[LOAD4:.*]] = fir.load %[[STORE4]] : !fir.ref -!CHECK: %[[TMP21:.*]] = fir.convert %[[LOAD4]] : (i128) -> f32 -!CHECK: fir.store %[[TMP21]] to %{{.*}} : !fir.ref -!CHECK: omp.yield -!CHECK: } +!CHECK: %[[TMP17:.*]] = fir.convert %{{.*}} : (i8) -> i64 +!CHECK: %[[TMP18:.*]] = fir.convert %{{.*}} : (i16) -> i64 +!CHECK: %[[TMP19:.*]] = fir.convert %{{.*}} : (i32) -> i64 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i64 = (%[[TMP17]]) to (%[[TMP18]]) inclusive step (%[[TMP19]]) { +!CHECK: %[[ARG1_I128:.*]] = fir.convert %[[ARG1]] : (i64) -> i128 +!CHECK: fir.store %[[ARG1_I128]] to %[[STORE4:.*]] : !fir.ref +!CHECK: %[[LOAD4:.*]] = fir.load %[[STORE4]] : !fir.ref +!CHECK: %[[TMP21:.*]] = fir.convert %[[LOAD4]] : (i128) -> f32 +!CHECK: fir.store %[[TMP21]] to %{{.*}} : !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$omp do do i16 = i1_lb, i2_ub, i4_s @@ -97,34 +105,37 @@ end program wsloop_variable !CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref !CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_8]] : (i8) -> i32 !CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_9]] : (i16) -> i32 -!CHECK: omp.wsloop for (%[[ARG0:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV:.*]] : !fir.ref -!CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_0]] : !fir.ref -!CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i128) -> index -!CHECK: %[[VAL_15:.*]] = arith.constant 100 : i32 -!CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> index -!CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_4]] : !fir.ref -!CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_17]] : (i32) -> index -!CHECK: %[[LB:.*]] = fir.convert %[[VAL_14]] : (index) -> i64 -!CHECK: %[[VAL_19:.*]]:2 = fir.do_loop %[[VAL_20:[^ ]*]] = -!CHECK-SAME: %[[VAL_14]] to %[[VAL_16]] step %[[VAL_18]] -!CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i64) { -!CHECK: fir.store %[[IV]] to %[[VAL_5]] : !fir.ref -!CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]] : !fir.ref -!CHECK: %[[VAL_22:.*]] = fir.convert %[[LOAD_IV]] : (i16) -> i64 -!CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_5]] : !fir.ref -!CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_22]], %[[VAL_23]] : i64 -!CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i64) -> f32 -!CHECK: fir.store %[[VAL_25]] to %[[VAL_6]] : !fir.ref -!CHECK: %[[VAL_26:.*]] = arith.addi %[[VAL_20]], %[[VAL_18]] : index -!CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_18]] : (index) -> i64 -!CHECK: %[[IVLOAD:.*]] = fir.load %[[VAL_5]] : !fir.ref -!CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] -!CHECK: fir.result %[[VAL_26]], %[[IVINC]] : index, i64 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 +!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV:.*]] : !fir.ref +!CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_0]] : !fir.ref +!CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i128) -> index +!CHECK: %[[VAL_15:.*]] = arith.constant 100 : i32 +!CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> index +!CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_4]] : !fir.ref +!CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_17]] : (i32) -> index +!CHECK: %[[LB:.*]] = fir.convert %[[VAL_14]] : (index) -> i64 +!CHECK: %[[VAL_19:.*]]:2 = fir.do_loop %[[VAL_20:[^ ]*]] = +!CHECK-SAME: %[[VAL_14]] to %[[VAL_16]] step %[[VAL_18]] +!CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i64) { +!CHECK: fir.store %[[IV]] to %[[VAL_5]] : !fir.ref +!CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]] : !fir.ref +!CHECK: %[[VAL_22:.*]] = fir.convert %[[LOAD_IV]] : (i16) -> i64 +!CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_5]] : !fir.ref +!CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_22]], %[[VAL_23]] : i64 +!CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i64) -> f32 +!CHECK: fir.store %[[VAL_25]] to %[[VAL_6]] : !fir.ref +!CHECK: %[[VAL_26:.*]] = arith.addi %[[VAL_20]], %[[VAL_18]] : index +!CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_18]] : (index) -> i64 +!CHECK: %[[IVLOAD:.*]] = fir.load %[[VAL_5]] : !fir.ref +!CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] +!CHECK: fir.result %[[VAL_26]], %[[IVINC]] : index, i64 +!CHECK: } +!CHECK: fir.store %[[VAL_19]]#1 to %[[VAL_5]] : !fir.ref +!CHECK: omp.yield !CHECK: } -!CHECK: fir.store %[[VAL_19]]#1 to %[[VAL_5]] : !fir.ref -!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: } subroutine wsloop_variable_sub @@ -146,16 +157,19 @@ subroutine wsloop_variable_sub !CHECK: %[[C1:.*]] = arith.constant 1 : i32 !CHECK: %[[C10:.*]] = arith.constant 10 : i32 !CHECK: %[[C1_2:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop for (%[[ARG0:.*]]) : i32 = (%[[C1]]) to (%[[C10]]) inclusive step (%[[C1_2]]) { -!CHECK: %[[ARG0_I8:.*]] = fir.convert %[[ARG0]] : (i32) -> i8 -!CHECK: fir.store %[[ARG0_I8]] to %[[IV2]] : !fir.ref -!CHECK: %[[IV2LOAD:.*]] = fir.load %[[IV2]] : !fir.ref -!CHECK: %[[J1LOAD:.*]] = fir.load %[[J1]] : !fir.ref -!CHECK: %[[VAL_27:.*]] = arith.cmpi eq, %[[IV2LOAD]], %[[J1LOAD]] : i8 -!CHECK: fir.if %[[VAL_27]] { -!CHECK: } else { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[C1]]) to (%[[C10]]) inclusive step (%[[C1_2]]) { +!CHECK: %[[ARG0_I8:.*]] = fir.convert %[[ARG0]] : (i32) -> i8 +!CHECK: fir.store %[[ARG0_I8]] to %[[IV2]] : !fir.ref +!CHECK: %[[IV2LOAD:.*]] = fir.load %[[IV2]] : !fir.ref +!CHECK: %[[J1LOAD:.*]] = fir.load %[[J1]] : !fir.ref +!CHECK: %[[VAL_27:.*]] = arith.cmpi eq, %[[IV2LOAD]], %[[J1LOAD]] : i8 +!CHECK: fir.if %[[VAL_27]] { +!CHECK: } else { +!CHECK: } +!CHECK: omp.yield !CHECK: } -!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: } j1 = 5 diff --git a/flang/test/Lower/OpenMP/FIR/wsloop.f90 b/flang/test/Lower/OpenMP/FIR/wsloop.f90 index abc0489b08ff5560ed6b3b30490ba37b0ff0148d..c9e428abdb440e6bf566506f9a6d4832abfc3268 100644 --- a/flang/test/Lower/OpenMP/FIR/wsloop.f90 +++ b/flang/test/Lower/OpenMP/FIR/wsloop.f90 @@ -7,21 +7,23 @@ subroutine simple_loop integer :: i ! CHECK: omp.parallel !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine @@ -30,21 +32,23 @@ subroutine simple_loop_with_step integer :: i ! CHECK: omp.parallel !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 2 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) - ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref + ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 2 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { + ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref !$OMP DO do i=1, 9, 2 - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine @@ -53,20 +57,22 @@ subroutine loop_with_schedule_nowait integer :: i ! CHECK: omp.parallel !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop schedule(runtime) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop schedule(runtime) nowait { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO SCHEDULE(runtime) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO NOWAIT - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine diff --git a/flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90 b/flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90 index 5c624d31b5f36da27113d4ed98ab798a254c8099..c245137f16c7af0fcb5b8dca104c5ac2fbbf7e88 100644 --- a/flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90 +++ b/flang/test/Lower/OpenMP/Todo/omp-default-clause-inner-loop.f90 @@ -12,7 +12,8 @@ ! CHECK: %[[const_1:.*]] = arith.constant 1 : i32 ! CHECK: %[[const_2:.*]] = arith.constant 10 : i32 ! CHECK: %[[const_3:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[ARG:.*]]) : i32 = (%[[const_1]]) to (%[[const_2]]) inclusive step (%[[const_3]]) { +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[ARG:.*]]) : i32 = (%[[const_1]]) to (%[[const_2]]) inclusive step (%[[const_3]]) { ! CHECK: fir.store %[[ARG]] to %[[TEMP]] : !fir.ref ! EXPECTED: %[[temp_1:.*]] = fir.load %[[PRIVATE_Z]] : !fir.ref ! CHECK: %[[temp_1:.*]] = fir.load %{{.*}} : !fir.ref @@ -24,6 +25,8 @@ ! CHECK: } ! CHECK: omp.terminator ! CHECK: } +! CHECK: omp.terminator +! CHECK: } subroutine nested_default_clause() integer x, y, z !$omp parallel do default(private) diff --git a/flang/test/Lower/OpenMP/copyin.f90 b/flang/test/Lower/OpenMP/copyin.f90 index 895e1abd274f30eeaae4156e884c948bd75fa21a..dda563303148bbb059c51dc9bfed8c288fa6c066 100644 --- a/flang/test/Lower/OpenMP/copyin.f90 +++ b/flang/test/Lower/OpenMP/copyin.f90 @@ -156,10 +156,13 @@ end ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_9]]#0 : !fir.ref ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_14:.*]]) : i32 = (%[[VAL_11]]) to (%[[VAL_12]]) inclusive step (%[[VAL_13]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]]#1 : !fir.ref -! CHECK: fir.call @_QPsub4(%[[VAL_9]]#1) fastmath : (!fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_11]]) to (%[[VAL_12]]) inclusive step (%[[VAL_13]]) { +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]]#1 : !fir.ref +! CHECK: fir.call @_QPsub4(%[[VAL_9]]#1) fastmath : (!fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -320,13 +323,16 @@ end subroutine ! CHECK: %[[VAL_34:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref ! CHECK: %[[VAL_36:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_37:.*]]) : i32 = (%[[VAL_34]]) to (%[[VAL_35]]) inclusive step (%[[VAL_36]]) { -! CHECK: fir.store %[[VAL_37]] to %[[VAL_20]]#1 : !fir.ref -! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_40:.*]] = arith.addi %[[VAL_38]], %[[VAL_39]] : i32 -! CHECK: hlfir.assign %[[VAL_40]] to %[[VAL_31]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_37:.*]]) : i32 = (%[[VAL_34]]) to (%[[VAL_35]]) inclusive step (%[[VAL_36]]) { +! CHECK: fir.store %[[VAL_37]] to %[[VAL_20]]#1 : !fir.ref +! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_40:.*]] = arith.addi %[[VAL_38]], %[[VAL_39]] : i32 +! CHECK: hlfir.assign %[[VAL_40]] to %[[VAL_31]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/default-clause-byref.f90 b/flang/test/Lower/OpenMP/default-clause-byref.f90 index 1167ba7e6ae0d47c14a6b6bf68a4c5d3fcda70eb..6a91927ab02dba5ea3a4d2d422450b1b42826de7 100644 --- a/flang/test/Lower/OpenMP/default-clause-byref.f90 +++ b/flang/test/Lower/OpenMP/default-clause-byref.f90 @@ -352,10 +352,13 @@ subroutine skipped_default_clause_checks() type(it)::iii !CHECK: omp.parallel { -!CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[VAL_Z_DECLARE]]#0 -> %[[PRV:.+]] : !fir.ref) for (%[[ARG:.*]]) {{.*}} { +!CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[VAL_Z_DECLARE]]#0 -> %[[PRV:.+]] : !fir.ref) { +!CHECK-NEXT: omp.loop_nest (%[[ARG:.*]]) {{.*}} { !CHECK: omp.yield !CHECK: } !CHECK: omp.terminator +!CHECK: } +!CHECK: omp.terminator !CHECK: } !$omp parallel do default(private) REDUCTION(MIN:z) do i = 1, 10 diff --git a/flang/test/Lower/OpenMP/default-clause.f90 b/flang/test/Lower/OpenMP/default-clause.f90 index 9a47e561338f1e49189845b0ff86ec72ff345e87..d3c6550821f0d47d4a94b51ed326690c15e12b85 100644 --- a/flang/test/Lower/OpenMP/default-clause.f90 +++ b/flang/test/Lower/OpenMP/default-clause.f90 @@ -352,10 +352,13 @@ subroutine skipped_default_clause_checks() type(it)::iii !CHECK: omp.parallel { -!CHECK: omp.wsloop reduction(@min_i32 %[[VAL_Z_DECLARE]]#0 -> %[[PRV:.+]] : !fir.ref) for (%[[ARG:.*]]) {{.*}} { +!CHECK: omp.wsloop reduction(@min_i32 %[[VAL_Z_DECLARE]]#0 -> %[[PRV:.+]] : !fir.ref) { +!CHECK-NEXT: omp.loop_nest (%[[ARG:.*]]) {{.*}} { !CHECK: omp.yield !CHECK: } !CHECK: omp.terminator +!CHECK: } +!CHECK: omp.terminator !CHECK: } !$omp parallel do default(private) REDUCTION(MIN:z) do i = 1, 10 diff --git a/flang/test/Lower/OpenMP/function-filtering-3.f90 b/flang/test/Lower/OpenMP/function-filtering-3.f90 new file mode 100644 index 0000000000000000000000000000000000000000..a277c06d620669b8a5eb66f14c715f1b567f5f9f --- /dev/null +++ b/flang/test/Lower/OpenMP/function-filtering-3.f90 @@ -0,0 +1,34 @@ +! RUN: %flang_fc1 -fopenmp -flang-experimental-hlfir -emit-llvm %s -o - | FileCheck --check-prefixes=LLVM-HOST,LLVM-ALL %s +! RUN: %flang_fc1 -fopenmp -emit-hlfir %s -o - | FileCheck --check-prefixes=MLIR-HOST,MLIR-ALL %s +! RUN: %flang_fc1 -fopenmp -fopenmp-is-target-device -flang-experimental-hlfir -emit-llvm %s -o - | FileCheck --check-prefixes=LLVM-DEVICE,LLVM-ALL %s +! RUN: %flang_fc1 -fopenmp -fopenmp-is-target-device -emit-hlfir %s -o - | FileCheck --check-prefixes=MLIR-DEVICE,MLIR-ALL %s +! RUN: bbc -fopenmp -emit-hlfir %s -o - | FileCheck --check-prefixes=MLIR-HOST,MLIR-ALL %s +! RUN: bbc -fopenmp -fopenmp-is-target-device -emit-hlfir %s -o - | FileCheck --check-prefixes=MLIR-DEVICE,MLIR-ALL %s + +! Check that the correct LLVM IR functions are kept for the host and device +! after running the whole set of translation and transformation passes from +! Fortran. + +! MLIR-HOST: func.func @{{.*}}host_parent_procedure( +! MLIR-HOST: return +! MLIR-DEVICE-NOT: func.func {{.*}}host_parent_procedure( + +! LLVM-HOST: define {{.*}} @host_parent_procedure{{.*}}( +! LLVM-DEVICE-NOT: {{.*}} @{{.*}}_host_parent_procedure{{.*}}( +subroutine host_parent_procedure(x) + integer, intent(out) :: x + call target_internal_proc(x) +contains +! MLIR-ALL: func.func {{.*}}@_QFhost_parent_procedurePtarget_internal_proc( + +! LLVM-HOST: define {{.*}} @_QFhost_parent_procedurePtarget_internal_proc( +! LLVM-DEVICE-NOT: define {{.*}} @_QFhost_parent_procedurePtarget_internal_proc( +! LLVM-ALL: define {{.*}} @__omp_offloading_{{.*}}QFhost_parent_procedurePtarget_internal_proc{{.*}}( + +subroutine target_internal_proc(x) + integer, intent(out) :: x + !$omp target map(from:x) + x = 10 + !$omp end target +end subroutine +end subroutine diff --git a/flang/test/Lower/OpenMP/hlfir-wsloop.f90 b/flang/test/Lower/OpenMP/hlfir-wsloop.f90 index b6be77fe3016d13f5253b6a4a394d4e82aa42159..fea05ae3d6bce34cac15d146f3cd91cbf597345f 100644 --- a/flang/test/Lower/OpenMP/hlfir-wsloop.f90 +++ b/flang/test/Lower/OpenMP/hlfir-wsloop.f90 @@ -11,17 +11,19 @@ subroutine simple_loop ! CHECK: omp.parallel !$OMP PARALLEL ! CHECK-DAG: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[IV:.*]] = fir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loopEi"} : (!fir.ref) -> !fir.ref - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_ST]]) to (%[[WS_END]]) inclusive step (%[[WS_ST]]) + ! CHECK: %[[IV:.*]] = fir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loopEi"} : (!fir.ref) -> !fir.ref + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_ST]]) to (%[[WS_END]]) inclusive step (%[[WS_ST]]) { !$OMP DO do i=1, 9 ! CHECK: fir.store %[[I]] to %[[IV:.*]] : !fir.ref ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine diff --git a/flang/test/Lower/OpenMP/lastprivate-commonblock.f90 b/flang/test/Lower/OpenMP/lastprivate-commonblock.f90 index a11bdee156637b0db5b2c8cd298036f5beb99a95..78adf09c6fe34553149c00f65867bd1adc140b90 100644 --- a/flang/test/Lower/OpenMP/lastprivate-commonblock.f90 +++ b/flang/test/Lower/OpenMP/lastprivate-commonblock.f90 @@ -2,35 +2,38 @@ !CHECK: fir.global common @[[CB_C:.*]](dense<0> : vector<8xi8>) : !fir.array<8xi8> !CHECK-LABEL: func.func @_QPlastprivate_common -!CHECK: %[[CB_C_REF:.*]] = fir.address_of(@[[CB_C]]) : !fir.ref> -!CHECK: %[[CB_C_REF_CVT:.*]] = fir.convert %[[CB_C_REF]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[CB_C_X_COOR:.*]] = fir.coordinate_of %[[CB_C_REF_CVT]], %{{.*}} : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[CB_C_X_ADDR:.*]] = fir.convert %[[CB_C_X_COOR]] : (!fir.ref) -> !fir.ref -!CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[CB_C_X_ADDR]] {uniq_name = "_QFlastprivate_commonEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[CB_C_REF_CVT:.*]] = fir.convert %[[CB_C_REF]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[CB_C_Y_COOR:.*]] = fir.coordinate_of %[[CB_C_REF_CVT]], %{{.*}} : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[CB_C_Y_ADDR:.*]] = fir.convert %[[CB_C_Y_COOR]] : (!fir.ref) -> !fir.ref -!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[CB_C_Y_ADDR]] {uniq_name = "_QFlastprivate_commonEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[PRIVATE_X_REF:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivate_commonEx"} -!CHECK: %[[PRIVATE_X_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_X_REF]] {uniq_name = "_QFlastprivate_commonEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[PRIVATE_Y_REF:.*]] = fir.alloca f32 {bindc_name = "y", pinned, uniq_name = "_QFlastprivate_commonEy"} -!CHECK: %[[PRIVATE_Y_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_Y_REF]] {uniq_name = "_QFlastprivate_commonEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -!CHECK: %[[V:.*]] = arith.addi %[[I]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[NEG_STEP:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[V_LT:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[V_GT:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[LAST_ITER:.*]] = arith.select %[[NEG_STEP]], %[[V_LT]], %[[V_GT]] : i1 -!CHECK: fir.if %[[LAST_ITER]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref -!CHECK: %[[PRIVATE_X_VAL:.*]] = fir.load %[[PRIVATE_X_DECL]]#0 : !fir.ref -!CHECK: hlfir.assign %[[PRIVATE_X_VAL]] to %[[X_DECL]]#0 temporary_lhs : f32, !fir.ref -!CHECK: %[[PRIVATE_Y_VAL:.*]] = fir.load %[[PRIVATE_Y_DECL]]#0 : !fir.ref -!CHECK: hlfir.assign %[[PRIVATE_Y_VAL]] to %[[Y_DECL]]#0 temporary_lhs : f32, !fir.ref +!CHECK: %[[CB_C_REF:.*]] = fir.address_of(@[[CB_C]]) : !fir.ref> +!CHECK: %[[CB_C_REF_CVT:.*]] = fir.convert %[[CB_C_REF]] : (!fir.ref>) -> !fir.ref> +!CHECK: %[[CB_C_X_COOR:.*]] = fir.coordinate_of %[[CB_C_REF_CVT]], %{{.*}} : (!fir.ref>, index) -> !fir.ref +!CHECK: %[[CB_C_X_ADDR:.*]] = fir.convert %[[CB_C_X_COOR]] : (!fir.ref) -> !fir.ref +!CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[CB_C_X_ADDR]] {uniq_name = "_QFlastprivate_commonEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[CB_C_REF_CVT:.*]] = fir.convert %[[CB_C_REF]] : (!fir.ref>) -> !fir.ref> +!CHECK: %[[CB_C_Y_COOR:.*]] = fir.coordinate_of %[[CB_C_REF_CVT]], %{{.*}} : (!fir.ref>, index) -> !fir.ref +!CHECK: %[[CB_C_Y_ADDR:.*]] = fir.convert %[[CB_C_Y_COOR]] : (!fir.ref) -> !fir.ref +!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[CB_C_Y_ADDR]] {uniq_name = "_QFlastprivate_commonEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[PRIVATE_X_REF:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivate_commonEx"} +!CHECK: %[[PRIVATE_X_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_X_REF]] {uniq_name = "_QFlastprivate_commonEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[PRIVATE_Y_REF:.*]] = fir.alloca f32 {bindc_name = "y", pinned, uniq_name = "_QFlastprivate_commonEy"} +!CHECK: %[[PRIVATE_Y_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_Y_REF]] {uniq_name = "_QFlastprivate_commonEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { +!CHECK: %[[V:.*]] = arith.addi %[[I]], %{{.*}} : i32 +!CHECK: %[[C0:.*]] = arith.constant 0 : i32 +!CHECK: %[[NEG_STEP:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 +!CHECK: %[[V_LT:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 +!CHECK: %[[V_GT:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 +!CHECK: %[[LAST_ITER:.*]] = arith.select %[[NEG_STEP]], %[[V_LT]], %[[V_GT]] : i1 +!CHECK: fir.if %[[LAST_ITER]] { +!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref +!CHECK: %[[PRIVATE_X_VAL:.*]] = fir.load %[[PRIVATE_X_DECL]]#0 : !fir.ref +!CHECK: hlfir.assign %[[PRIVATE_X_VAL]] to %[[X_DECL]]#0 temporary_lhs : f32, !fir.ref +!CHECK: %[[PRIVATE_Y_VAL:.*]] = fir.load %[[PRIVATE_Y_DECL]]#0 : !fir.ref +!CHECK: hlfir.assign %[[PRIVATE_Y_VAL]] to %[[Y_DECL]]#0 temporary_lhs : f32, !fir.ref +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator !CHECK: } -!CHECK: omp.yield -!CHECK: } subroutine lastprivate_common common /c/ x, y real x, y diff --git a/flang/test/Lower/OpenMP/lastprivate-iv.f90 b/flang/test/Lower/OpenMP/lastprivate-iv.f90 index 70fe500129d128fafd3b847283323f676331a579..24c20281b9c3897c58761586165d8f87ef5f9825 100644 --- a/flang/test/Lower/OpenMP/lastprivate-iv.f90 +++ b/flang/test/Lower/OpenMP/lastprivate-iv.f90 @@ -2,28 +2,31 @@ ! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s !CHECK-LABEL: func @_QPlastprivate_iv_inc -!CHECK: %[[I_MEM:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -!CHECK: %[[I:.*]]:2 = hlfir.declare %[[I_MEM]] {uniq_name = "_QFlastprivate_iv_incEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[I2_MEM:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFlastprivate_iv_incEi"} -!CHECK: %[[I2:.*]]:2 = hlfir.declare %[[I2_MEM]] {uniq_name = "_QFlastprivate_iv_incEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[LB:.*]] = arith.constant 4 : i32 -!CHECK: %[[UB:.*]] = arith.constant 10 : i32 -!CHECK: %[[STEP:.*]] = arith.constant 3 : i32 -!CHECK: omp.wsloop for (%[[IV:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { -!CHECK: fir.store %[[IV]] to %[[I]]#1 : !fir.ref -!CHECK: %[[V:.*]] = arith.addi %[[IV]], %[[STEP]] : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[STEP_NEG:.*]] = arith.cmpi slt, %[[STEP]], %[[C0]] : i32 -!CHECK: %[[V_LT:.*]] = arith.cmpi slt, %[[V]], %[[UB]] : i32 -!CHECK: %[[V_GT:.*]] = arith.cmpi sgt, %[[V]], %[[UB]] : i32 -!CHECK: %[[CMP:.*]] = arith.select %[[STEP_NEG]], %[[V_LT]], %[[V_GT]] : i1 -!CHECK: fir.if %[[CMP]] { -!CHECK: fir.store %[[V]] to %[[I]]#1 : !fir.ref -!CHECK: %[[I_VAL:.*]] = fir.load %[[I]]#0 : !fir.ref -!CHECK: hlfir.assign %[[I_VAL]] to %[[I2]]#0 temporary_lhs : i32, !fir.ref +!CHECK: %[[I_MEM:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} +!CHECK: %[[I:.*]]:2 = hlfir.declare %[[I_MEM]] {uniq_name = "_QFlastprivate_iv_incEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[I2_MEM:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFlastprivate_iv_incEi"} +!CHECK: %[[I2:.*]]:2 = hlfir.declare %[[I2_MEM]] {uniq_name = "_QFlastprivate_iv_incEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[LB:.*]] = arith.constant 4 : i32 +!CHECK: %[[UB:.*]] = arith.constant 10 : i32 +!CHECK: %[[STEP:.*]] = arith.constant 3 : i32 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[IV:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { +!CHECK: fir.store %[[IV]] to %[[I]]#1 : !fir.ref +!CHECK: %[[V:.*]] = arith.addi %[[IV]], %[[STEP]] : i32 +!CHECK: %[[C0:.*]] = arith.constant 0 : i32 +!CHECK: %[[STEP_NEG:.*]] = arith.cmpi slt, %[[STEP]], %[[C0]] : i32 +!CHECK: %[[V_LT:.*]] = arith.cmpi slt, %[[V]], %[[UB]] : i32 +!CHECK: %[[V_GT:.*]] = arith.cmpi sgt, %[[V]], %[[UB]] : i32 +!CHECK: %[[CMP:.*]] = arith.select %[[STEP_NEG]], %[[V_LT]], %[[V_GT]] : i1 +!CHECK: fir.if %[[CMP]] { +!CHECK: fir.store %[[V]] to %[[I]]#1 : !fir.ref +!CHECK: %[[I_VAL:.*]] = fir.load %[[I]]#0 : !fir.ref +!CHECK: hlfir.assign %[[I_VAL]] to %[[I2]]#0 temporary_lhs : i32, !fir.ref +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator !CHECK: } -!CHECK: omp.yield -!CHECK: } subroutine lastprivate_iv_inc() integer :: i @@ -34,28 +37,31 @@ subroutine lastprivate_iv_inc() end subroutine !CHECK-LABEL: func @_QPlastprivate_iv_dec -!CHECK: %[[I_MEM:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -!CHECK: %[[I:.*]]:2 = hlfir.declare %[[I_MEM]] {uniq_name = "_QFlastprivate_iv_decEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[I2_MEM:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFlastprivate_iv_decEi"} -!CHECK: %[[I2:.*]]:2 = hlfir.declare %[[I2_MEM]] {uniq_name = "_QFlastprivate_iv_decEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[LB:.*]] = arith.constant 10 : i32 -!CHECK: %[[UB:.*]] = arith.constant 1 : i32 -!CHECK: %[[STEP:.*]] = arith.constant -3 : i32 -!CHECK: omp.wsloop for (%[[IV:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { -!CHECK: fir.store %[[IV]] to %[[I]]#1 : !fir.ref -!CHECK: %[[V:.*]] = arith.addi %[[IV]], %[[STEP]] : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[STEP_NEG:.*]] = arith.cmpi slt, %[[STEP]], %[[C0]] : i32 -!CHECK: %[[V_LT:.*]] = arith.cmpi slt, %[[V]], %[[UB]] : i32 -!CHECK: %[[V_GT:.*]] = arith.cmpi sgt, %[[V]], %[[UB]] : i32 -!CHECK: %[[CMP:.*]] = arith.select %[[STEP_NEG]], %[[V_LT]], %[[V_GT]] : i1 -!CHECK: fir.if %[[CMP]] { -!CHECK: fir.store %[[V]] to %[[I]]#1 : !fir.ref -!CHECK: %[[I_VAL:.*]] = fir.load %[[I]]#0 : !fir.ref -!CHECK: hlfir.assign %[[I_VAL]] to %[[I2]]#0 temporary_lhs : i32, !fir.ref +!CHECK: %[[I_MEM:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} +!CHECK: %[[I:.*]]:2 = hlfir.declare %[[I_MEM]] {uniq_name = "_QFlastprivate_iv_decEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[I2_MEM:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFlastprivate_iv_decEi"} +!CHECK: %[[I2:.*]]:2 = hlfir.declare %[[I2_MEM]] {uniq_name = "_QFlastprivate_iv_decEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[LB:.*]] = arith.constant 10 : i32 +!CHECK: %[[UB:.*]] = arith.constant 1 : i32 +!CHECK: %[[STEP:.*]] = arith.constant -3 : i32 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[IV:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { +!CHECK: fir.store %[[IV]] to %[[I]]#1 : !fir.ref +!CHECK: %[[V:.*]] = arith.addi %[[IV]], %[[STEP]] : i32 +!CHECK: %[[C0:.*]] = arith.constant 0 : i32 +!CHECK: %[[STEP_NEG:.*]] = arith.cmpi slt, %[[STEP]], %[[C0]] : i32 +!CHECK: %[[V_LT:.*]] = arith.cmpi slt, %[[V]], %[[UB]] : i32 +!CHECK: %[[V_GT:.*]] = arith.cmpi sgt, %[[V]], %[[UB]] : i32 +!CHECK: %[[CMP:.*]] = arith.select %[[STEP_NEG]], %[[V_LT]], %[[V_GT]] : i1 +!CHECK: fir.if %[[CMP]] { +!CHECK: fir.store %[[V]] to %[[I]]#1 : !fir.ref +!CHECK: %[[I_VAL:.*]] = fir.load %[[I]]#0 : !fir.ref +!CHECK: hlfir.assign %[[I_VAL]] to %[[I2]]#0 temporary_lhs : i32, !fir.ref +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator !CHECK: } -!CHECK: omp.yield -!CHECK: } subroutine lastprivate_iv_dec() integer :: i diff --git a/flang/test/Lower/OpenMP/location.f90 b/flang/test/Lower/OpenMP/location.f90 index 1e01a4828dd9e1b23c44f1bf3dbc344ee994539a..5d340937a81ce01fa710617dd684b6416489ae24 100644 --- a/flang/test/Lower/OpenMP/location.f90 +++ b/flang/test/Lower/OpenMP/location.f90 @@ -28,11 +28,14 @@ end !CHECK-LABEL: sub_loop subroutine sub_loop() -!CHECK: omp.wsloop {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest {{.*}} { !$omp do do i=1,10 print *, i !CHECK: omp.yield loc(#[[LOOP_LOC:.*]]) +!CHECK: } loc(#[[LOOP_LOC]]) +!CHECK: omp.terminator loc(#[[LOOP_LOC]]) !CHECK: } loc(#[[LOOP_LOC]]) end do !$omp end do @@ -60,9 +63,9 @@ end subroutine !CHECK: #[[PAR_LOC]] = loc("{{.*}}location.f90":9:9) !CHECK: #[[TAR_LOC]] = loc("{{.*}}location.f90":21:9) -!CHECK: #[[LOOP_LOC]] = loc("{{.*}}location.f90":32:9) -!CHECK: #[[BAR_LOC]] = loc("{{.*}}location.f90":44:9) -!CHECK: #[[TW_LOC]] = loc("{{.*}}location.f90":46:9) -!CHECK: #[[TY_LOC]] = loc("{{.*}}location.f90":48:9) -!CHECK: #[[IF_LOC]] = loc("{{.*}}location.f90":55:14) -!CHECK: #[[TASK_LOC]] = loc("{{.*}}location.f90":55:9) +!CHECK: #[[LOOP_LOC]] = loc("{{.*}}location.f90":33:9) +!CHECK: #[[BAR_LOC]] = loc("{{.*}}location.f90":47:9) +!CHECK: #[[TW_LOC]] = loc("{{.*}}location.f90":49:9) +!CHECK: #[[TY_LOC]] = loc("{{.*}}location.f90":51:9) +!CHECK: #[[IF_LOC]] = loc("{{.*}}location.f90":58:14) +!CHECK: #[[TASK_LOC]] = loc("{{.*}}location.f90":58:9) diff --git a/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 b/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 index 28f59c95d60bbee292b8a44619d65d78cda8dae4..bb81e5eac62f56b04ea47f5aae817369990d7cb1 100644 --- a/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 +++ b/flang/test/Lower/OpenMP/parallel-lastprivate-clause-scalar.f90 @@ -14,8 +14,9 @@ !CHECK-DAG: %[[ARG1_PVT_DECL:.*]]:2 = hlfir.declare %[[ARG1_PVT]] typeparams %[[FIVE]] {uniq_name = "_QFlastprivate_characterEarg1"} : (!fir.ref>, index) -> (!fir.ref>, !fir.ref>) ! Check that we are accessing the clone inside the loop -!CHECK-DAG: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { -!CHECK-DAG: %[[UNIT:.*]] = arith.constant 6 : i32 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: %[[UNIT:.*]] = arith.constant 6 : i32 !CHECK-NEXT: %[[ADDR:.*]] = fir.address_of(@_QQclX !CHECK-NEXT: %[[CVT0:.*]] = fir.convert %[[ADDR]] !CHECK-NEXT: %[[CNST:.*]] = arith.constant @@ -36,9 +37,12 @@ !CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref ! Testing lastprivate val update -!CHECK-DAG: hlfir.assign %[[ARG1_PVT_DECL]]#0 to %[[ARG1_DECL]]#0 temporary_lhs : !fir.ref>, !fir.ref> -!CHECK-DAG: } -!CHECK-DAG: omp.yield +!CHECK: hlfir.assign %[[ARG1_PVT_DECL]]#0 to %[[ARG1_DECL]]#0 temporary_lhs : !fir.ref>, !fir.ref> +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine lastprivate_character(arg1) character(5) :: arg1 @@ -57,7 +61,8 @@ end subroutine !CHECK-DAG: omp.parallel { !CHECK-DAG: %[[CLONE:.*]] = fir.alloca i32 {bindc_name = "arg1" !CHECK-DAG: %[[CLONE_DECL:.*]]:2 = hlfir.declare %[[CLONE]] {uniq_name = "_QFlastprivate_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -72,8 +77,11 @@ end subroutine ! Testing lastprivate val update !CHECK-NEXT: %[[CLONE_LD:.*]] = fir.load %[[CLONE_DECL]]#0 : !fir.ref !CHECK: hlfir.assign %[[CLONE_LD]] to %[[ARG1_DECL]]#0 temporary_lhs : i32, !fir.ref -!CHECK-DAG: } -!CHECK-DAG: omp.yield +!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine lastprivate_int(arg1) integer :: arg1 @@ -96,7 +104,8 @@ end subroutine !CHECK-DAG: %[[CLONE1_DECL:.*]]:2 = hlfir.declare %[[CLONE1]] {uniq_name = "_QFmult_lastprivate_intEarg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) !CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" !CHECK-DAG: %[[CLONE2_DECL:.*]]:2 = hlfir.declare %[[CLONE2]] {uniq_name = "_QFmult_lastprivate_intEarg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -114,6 +123,9 @@ end subroutine !CHECK-DAG: hlfir.assign %[[CLONE_LD2]] to %[[ARG2_DECL]]#0 temporary_lhs : i32, !fir.ref !CHECK: } !CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine mult_lastprivate_int(arg1, arg2) integer :: arg1, arg2 @@ -137,7 +149,8 @@ end subroutine !CHECK-DAG: %[[CLONE1_DECL:.*]]:2 = hlfir.declare %[[CLONE1]] {uniq_name = "_QFmult_lastprivate_int2Earg1"} : (!fir.ref) -> (!fir.ref, !fir.ref) !CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" !CHECK-DAG: %[[CLONE2_DECL:.*]]:2 = hlfir.declare %[[CLONE2]] {uniq_name = "_QFmult_lastprivate_int2Earg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { !Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -155,6 +168,9 @@ end subroutine !CHECK-DAG: hlfir.assign %[[CLONE_LD1]] to %[[ARG1_DECL]]#0 temporary_lhs : i32, !fir.ref !CHECK: } !CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } subroutine mult_lastprivate_int2(arg1, arg2) integer :: arg1, arg2 @@ -183,7 +199,8 @@ end subroutine !CHECK: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" !CHECK: %[[CLONE2_DECL:.*]]:2 = hlfir.declare %[[CLONE2]] {uniq_name = "_QFfirstpriv_lastpriv_intEarg2"} : (!fir.ref) -> (!fir.ref, !fir.ref) !CHECK-NOT: omp.barrier -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 @@ -199,6 +216,9 @@ end subroutine !CHECK-NEXT: hlfir.assign %[[CLONE_LD]] to %[[ARG2_DECL]]#0 temporary_lhs : i32, !fir.ref !CHECK-NEXT: } !CHECK-NEXT: omp.yield +!CHECK-NEXT: } +!CHECK-NEXT: omp.terminator +!CHECK-NEXT: } subroutine firstpriv_lastpriv_int(arg1, arg2) integer :: arg1, arg2 @@ -223,7 +243,8 @@ end subroutine !CHECK-NEXT: %[[FPV_LD:.*]] = fir.load %[[ARG1_DECL]]#0 : !fir.ref !CHECK-NEXT: hlfir.assign %[[FPV_LD]] to %[[CLONE1_DECL]]#0 temporary_lhs : i32, !fir.ref !CHECK-NEXT: omp.barrier -!CHECK: omp.wsloop for (%[[INDX_WS:.*]]) : {{.*}} { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { ! Testing last iteration check !CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 !CHECK: %[[C0:.*]] = arith.constant 0 : i32 @@ -238,6 +259,9 @@ end subroutine !CHECK-NEXT: hlfir.assign %[[CLONE_LD]] to %[[ARG1_DECL]]#0 temporary_lhs : i32, !fir.ref !CHECK-NEXT: } !CHECK-NEXT: omp.yield +!CHECK-NEXT: } +!CHECK-NEXT: omp.terminator +!CHECK-NEXT: } subroutine firstpriv_lastpriv_int2(arg1) integer :: arg1 diff --git a/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 b/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 index 8533106b7ac487110753a08250529fedd570b101..93809fde98a269f4872bd43bae4f298e159c62ae 100644 --- a/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 +++ b/flang/test/Lower/OpenMP/parallel-private-clause-fixes.f90 @@ -21,30 +21,33 @@ ! CHECK: %[[ONE:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_3:.*]] = fir.load %[[GAMA_DECL]]#0 : !fir.ref ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_6:.*]]) : i32 = (%[[ONE]]) to (%[[VAL_3]]) inclusive step (%[[VAL_5]]) { -! CHECK: fir.store %[[VAL_6]] to %[[PRIV_I_DECL]]#1 : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i32) -> index -! CHECK: %[[VAL_9:.*]] = fir.load %[[GAMA_DECL]]#0 : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> index -! CHECK: %[[VAL_11:.*]] = arith.constant 1 : index -! CHECK: %[[LB:.*]] = fir.convert %[[VAL_8]] : (index) -> i32 -! CHECK: %[[VAL_12:.*]]:2 = fir.do_loop %[[VAL_13:[^ ]*]] = -! CHECK-SAME: %[[VAL_8]] to %[[VAL_10]] step %[[VAL_11]] -! CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i32) { -! CHECK: fir.store %[[IV]] to %[[PRIV_J_DECL]]#1 : !fir.ref -! CHECK: %[[LOAD:.*]] = fir.load %[[PRIV_I_DECL]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[PRIV_J_DECL]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.addi %[[LOAD]], %[[VAL_15]] : i32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[PRIV_X_DECL]]#0 : i32, !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_13]], %[[VAL_11]] : index -! CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_11]] : (index) -> i32 -! CHECK: %[[IVLOAD:.*]] = fir.load %[[PRIV_J_DECL]]#1 : !fir.ref -! CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] -! CHECK: fir.result %[[VAL_17]], %[[IVINC]] : index, i32 +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_6:.*]]) : i32 = (%[[ONE]]) to (%[[VAL_3]]) inclusive step (%[[VAL_5]]) { +! CHECK: fir.store %[[VAL_6]] to %[[PRIV_I_DECL]]#1 : !fir.ref +! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 +! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i32) -> index +! CHECK: %[[VAL_9:.*]] = fir.load %[[GAMA_DECL]]#0 : !fir.ref +! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> index +! CHECK: %[[VAL_11:.*]] = arith.constant 1 : index +! CHECK: %[[LB:.*]] = fir.convert %[[VAL_8]] : (index) -> i32 +! CHECK: %[[VAL_12:.*]]:2 = fir.do_loop %[[VAL_13:[^ ]*]] = +! CHECK-SAME: %[[VAL_8]] to %[[VAL_10]] step %[[VAL_11]] +! CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i32) { +! CHECK: fir.store %[[IV]] to %[[PRIV_J_DECL]]#1 : !fir.ref +! CHECK: %[[LOAD:.*]] = fir.load %[[PRIV_I_DECL]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[PRIV_J_DECL]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.addi %[[LOAD]], %[[VAL_15]] : i32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[PRIV_X_DECL]]#0 : i32, !fir.ref +! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_13]], %[[VAL_11]] : index +! CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_11]] : (index) -> i32 +! CHECK: %[[IVLOAD:.*]] = fir.load %[[PRIV_J_DECL]]#1 : !fir.ref +! CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] +! CHECK: fir.result %[[VAL_17]], %[[IVINC]] : index, i32 +! CHECK: } +! CHECK: fir.store %[[VAL_12]]#1 to %[[PRIV_J_DECL]]#1 : !fir.ref +! CHECK: omp.yield ! CHECK: } -! CHECK: fir.store %[[VAL_12]]#1 to %[[PRIV_J_DECL]]#1 : !fir.ref -! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/parallel-private-clause.f90 b/flang/test/Lower/OpenMP/parallel-private-clause.f90 index 775f7b4f2cb1061a67af4b2ab8fbeaf343bc8aa8..b9b58a135aaa2ced6479302c1a58dba3e998c479 100644 --- a/flang/test/Lower/OpenMP/parallel-private-clause.f90 +++ b/flang/test/Lower/OpenMP/parallel-private-clause.f90 @@ -292,33 +292,35 @@ subroutine simple_loop_1 real, allocatable :: r; ! FIRDialect: omp.parallel !$OMP PARALLEL PRIVATE(r) - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! FIRDialect: %[[ALLOCA_IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loop_1Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: %[[R_DECL:.*]]:2 = hlfir.declare [[R]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsimple_loop_1Er"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) + ! FIRDialect: %[[ALLOCA_IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loop_1Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: %[[R_DECL:.*]]:2 = hlfir.declare [[R]] {fortran_attrs = #fir.var_attrs, uniq_name = "_QFsimple_loop_1Er"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! FIRDialect: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! FIRDialect: omp.wsloop { + ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV_DECL]]#1 : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV_DECL]]#0 : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}} : (!fir.ref, i32) -> i1 + ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV_DECL]]#1 : !fir.ref + ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV_DECL]]#0 : !fir.ref + ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}} : (!fir.ref, i32) -> i1 print*, i end do - ! FIRDialect: omp.yield - ! FIRDialect: {{%.*}} = fir.load %[[R_DECL]]#0 : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load %[[R_DECL]]#0 : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to %[[R_DECL]]#0 : !fir.ref>> + ! FIRDialect: omp.yield + ! FIRDialect: omp.terminator + ! FIRDialect: {{%.*}} = fir.load %[[R_DECL]]#0 : !fir.ref>> + ! FIRDialect: fir.if {{%.*}} { + ! FIRDialect: [[LD:%.*]] = fir.load %[[R_DECL]]#0 : !fir.ref>> + ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap + ! FIRDialect: fir.freemem [[AD]] : !fir.heap + ! FIRDialect: fir.store {{%.*}} to %[[R_DECL]]#0 : !fir.ref>> !$OMP END DO ! FIRDialect: omp.terminator !$OMP END PARALLEL @@ -330,19 +332,20 @@ subroutine simple_loop_2 real, allocatable :: r; ! FIRDialect: omp.parallel !$OMP PARALLEL - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! FIRDialect: %[[ALLOCA_IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "{{.*}}Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: %[[R_DECL:.*]]:2 = hlfir.declare [[R]] {fortran_attrs = #fir.var_attrs, uniq_name = "{{.*}}Er"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) + ! FIRDialect: %[[ALLOCA_IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "{{.*}}Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: %[[R_DECL:.*]]:2 = hlfir.declare [[R]] {fortran_attrs = #fir.var_attrs, uniq_name = "{{.*}}Er"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! FIRDialect: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! FIRDialect: omp.wsloop { + ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO PRIVATE(r) do i=1, 9 ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV_DECL]]#1 : !fir.ref @@ -351,6 +354,7 @@ subroutine simple_loop_2 print*, i end do ! FIRDialect: omp.yield + ! FIRDialect: omp.terminator ! FIRDialect: {{%.*}} = fir.load %[[R_DECL]]#0 : !fir.ref>> ! FIRDialect: fir.if {{%.*}} { ! FIRDialect: [[LD:%.*]] = fir.load %[[R_DECL]]#0 : !fir.ref>> @@ -367,33 +371,35 @@ subroutine simple_loop_3 integer :: i real, allocatable :: r; ! FIRDialect: omp.parallel - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! FIRDialect: %[[ALLOCA_IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "{{.*}}Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! FIRDialect: %[[ALLOCA_IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "{{.*}}Ei"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: [[R_DECL:%.*]]:2 = hlfir.declare [[R]] {fortran_attrs = #fir.var_attrs, uniq_name = "{{.*}}Er"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) + ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> + ! FIRDialect: [[R_DECL:%.*]]:2 = hlfir.declare [[R]] {fortran_attrs = #fir.var_attrs, uniq_name = "{{.*}}Er"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! FIRDialect: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! FIRDialect: omp.wsloop { + ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO PRIVATE(r) do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV_DECL:.*]]#1 : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV_DECL]]#0 : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV_DECL:.*]]#1 : !fir.ref + ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV_DECL]]#0 : !fir.ref + ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! FIRDialect: omp.yield - ! FIRDialect: {{%.*}} = fir.load [[R_DECL]]#0 : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R_DECL]]#0 : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R_DECL]]#0 : !fir.ref>> + ! FIRDialect: omp.yield + ! FIRDialect: omp.terminator + ! FIRDialect: {{%.*}} = fir.load [[R_DECL]]#0 : !fir.ref>> + ! FIRDialect: fir.if {{%.*}} { + ! FIRDialect: [[LD:%.*]] = fir.load [[R_DECL]]#0 : !fir.ref>> + ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap + ! FIRDialect: fir.freemem [[AD]] : !fir.heap + ! FIRDialect: fir.store {{%.*}} to [[R_DECL]]#0 : !fir.ref>> !$OMP END PARALLEL DO ! FIRDialect: omp.terminator end subroutine diff --git a/flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90 b/flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90 index 890ae48ce0fc27c5f063e4b1b7e633005f7cd3a3..28216ef91c3a32ed03e131c74b979f404bea6c2c 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-allocatable-array.f90 @@ -37,9 +37,12 @@ end program ! CHECK: %[[VAL_6:.*]] = fir.allocmem !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp", uniq_name = ""} ! CHECK: %[[VAL_7:.*]] = arith.constant true ! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.box>, !fir.heap>) -! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_8]]#0 : (!fir.box>) -> !fir.box>> -! CHECK: hlfir.assign %[[VAL_1]] to %[[VAL_9]] : i32, !fir.box>> -! CHECK: fir.store %[[VAL_9]] to %[[VAL_10]] : !fir.ref>>> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_2]], %[[C0]] : (!fir.box>>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[REBOX:.*]] = fir.rebox %[[VAL_8]]#0(%[[SHIFT]]) : (!fir.box>, !fir.shapeshift<1>) -> !fir.box>> +! CHECK: hlfir.assign %[[VAL_1]] to %[[REBOX]] : i32, !fir.box>> +! CHECK: fir.store %[[REBOX]] to %[[VAL_10]] : !fir.ref>>> ! CHECK: } ! CHECK: omp.yield(%[[VAL_10]] : !fir.ref>>>) ! CHECK: } combiner { @@ -92,22 +95,25 @@ end program ! CHECK: %[[VAL_14:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_heap_Uxi32 %[[VAL_3]]#0 -> %[[VAL_17:.*]] : !fir.ref>>>) for (%[[VAL_18:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_13]]#1 : !fir.ref -! CHECK: %[[VAL_19:.*]]:2 = hlfir.declare %[[VAL_17]] {fortran_attrs = {{.*}}, uniq_name = "_QFEr"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_13]]#0 : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref>>> -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_23:.*]] = hlfir.designate %[[VAL_21]] (%[[VAL_22]]) : (!fir.box>>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_23]] : i32, !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_13]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.constant 0 : i32 -! CHECK: %[[VAL_26:.*]] = arith.subi %[[VAL_25]], %[[VAL_24]] : i32 -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref>>> -! CHECK: %[[VAL_28:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_29:.*]] = hlfir.designate %[[VAL_27]] (%[[VAL_28]]) : (!fir.box>>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_29]] : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_heap_Uxi32 %[[VAL_3]]#0 -> %[[VAL_17:.*]] : !fir.ref>>>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { +! CHECK: %[[VAL_19:.*]]:2 = hlfir.declare %[[VAL_17]] {fortran_attrs = {{.*}}, uniq_name = "_QFEr"} : (!fir.ref>>>) -> (!fir.ref>>>, !fir.ref>>>) +! CHECK: fir.store %[[VAL_18]] to %[[VAL_13]]#1 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_13]]#0 : !fir.ref +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref>>> +! CHECK: %[[VAL_22:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_23:.*]] = hlfir.designate %[[VAL_21]] (%[[VAL_22]]) : (!fir.box>>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_23]] : i32, !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_13]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_26:.*]] = arith.subi %[[VAL_25]], %[[VAL_24]] : i32 +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref>>> +! CHECK: %[[VAL_28:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_29:.*]] = hlfir.designate %[[VAL_27]] (%[[VAL_28]]) : (!fir.box>>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_29]] : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90 b/flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90 new file mode 100644 index 0000000000000000000000000000000000000000..8202e6d897157d56685a83ea614ecdbf619c1145 --- /dev/null +++ b/flang/test/Lower/OpenMP/parallel-reduction-array-lb.f90 @@ -0,0 +1,90 @@ +! RUN: bbc -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s +! RUN: %flang_fc1 -emit-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s + +program reduce +integer, dimension(2:4, 2) :: i = 0 + +!$omp parallel reduction(+:i) +i(3, 1) = 3 +!$omp end parallel + +print *,i + +end program + +! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_box_3x2xi32 : !fir.ref>> init { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_15:.*]] = fir.alloca !fir.box> +! CHECK: %[[VAL_3:.*]] = arith.constant 3 : index +! CHECK: %[[VAL_4:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_3]], %[[VAL_4]] : (index, index) -> !fir.shape<2> +! CHECK: %[[VAL_6:.*]] = fir.allocmem !fir.array<3x2xi32> {bindc_name = ".tmp", uniq_name = ""} +! CHECK: %[[VAL_7:.*]] = arith.constant true +! CHECK: %[[VAL_8:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<2>) -> (!fir.heap>, !fir.heap>) +! CHECK: %[[VAL_9:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_10:.*]]:3 = fir.box_dims %[[VAL_2]], %[[VAL_9]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_11:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_12:.*]]:3 = fir.box_dims %[[VAL_2]], %[[VAL_11]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_13:.*]] = fir.shape_shift %[[VAL_10]]#0, %[[VAL_10]]#1, %[[VAL_12]]#0, %[[VAL_12]]#1 : (index, index, index, index) -> !fir.shapeshift<2> +! CHECK: %[[VAL_14:.*]] = fir.embox %[[VAL_8]]#0(%[[VAL_13]]) : (!fir.heap>, !fir.shapeshift<2>) -> !fir.box> +! CHECK: hlfir.assign %[[VAL_1]] to %[[VAL_14]] : i32, !fir.box> +! CHECK: fir.store %[[VAL_14]] to %[[VAL_15]] : !fir.ref>> +! CHECK: omp.yield(%[[VAL_15]] : !fir.ref>>) +! CHECK: } combiner { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>, %[[VAL_1:.*]]: !fir.ref>>): +! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]] : !fir.ref>> +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_5:.*]]:3 = fir.box_dims %[[VAL_2]], %[[VAL_4]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_6:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_7:.*]]:3 = fir.box_dims %[[VAL_2]], %[[VAL_6]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_8:.*]] = fir.shape_shift %[[VAL_5]]#0, %[[VAL_5]]#1, %[[VAL_7]]#0, %[[VAL_7]]#1 : (index, index, index, index) -> !fir.shapeshift<2> +! CHECK: %[[VAL_9:.*]] = arith.constant 1 : index +! CHECK: fir.do_loop %[[VAL_10:.*]] = %[[VAL_9]] to %[[VAL_7]]#1 step %[[VAL_9]] unordered { +! CHECK: fir.do_loop %[[VAL_11:.*]] = %[[VAL_9]] to %[[VAL_5]]#1 step %[[VAL_9]] unordered { +! CHECK: %[[VAL_12:.*]] = fir.array_coor %[[VAL_2]](%[[VAL_8]]) %[[VAL_11]], %[[VAL_10]] : (!fir.box>, !fir.shapeshift<2>, index, index) -> !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.array_coor %[[VAL_3]](%[[VAL_8]]) %[[VAL_11]], %[[VAL_10]] : (!fir.box>, !fir.shapeshift<2>, index, index) -> !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]] : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_13]] : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.addi %[[VAL_14]], %[[VAL_15]] : i32 +! CHECK: fir.store %[[VAL_16]] to %[[VAL_12]] : !fir.ref +! CHECK: } +! CHECK: } +! CHECK: omp.yield(%[[VAL_0]] : !fir.ref>>) +! CHECK: } cleanup { +! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>): +! CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref>> +! CHECK: %[[VAL_2:.*]] = fir.box_addr %[[VAL_1]] : (!fir.box>) -> !fir.ref> +! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> i64 +! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i64 +! CHECK: %[[VAL_5:.*]] = arith.cmpi ne, %[[VAL_3]], %[[VAL_4]] : i64 +! CHECK: fir.if %[[VAL_5]] { +! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.heap> +! CHECK: fir.freemem %[[VAL_6]] : !fir.heap> +! CHECK: } +! CHECK: omp.yield +! CHECK: } + +! CHECK-LABEL: func.func @_QQmain() attributes {fir.bindc_name = "reduce"} { +! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QFEi) : !fir.ref> +! CHECK: %[[VAL_1:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_2:.*]] = arith.constant 3 : index +! CHECK: %[[VAL_3:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_4:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_5:.*]] = fir.shape_shift %[[VAL_1]], %[[VAL_2]], %[[VAL_3]], %[[VAL_4]] : (index, index, index, index) -> !fir.shapeshift<2> +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_0]](%[[VAL_5]]) {uniq_name = "_QFEi"} : (!fir.ref>, !fir.shapeshift<2>) -> (!fir.box>, !fir.ref>) +! CHECK: %[[VAL_7:.*]] = fir.alloca !fir.box> +! CHECK: fir.store %[[VAL_6]]#0 to %[[VAL_7]] : !fir.ref>> +! CHECK: omp.parallel byref reduction(@add_reduction_byref_box_3x2xi32 %[[VAL_7]] -> %[[VAL_8:.*]] : !fir.ref>>) { +! CHECK: %[[VAL_9:.*]]:2 = hlfir.declare %[[VAL_8]] {uniq_name = "_QFEi"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: %[[VAL_10:.*]] = arith.constant 3 : i32 +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]]#0 : !fir.ref>> +! CHECK: %[[VAL_12:.*]] = arith.constant 3 : index +! CHECK: %[[VAL_13:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_14:.*]] = hlfir.designate %[[VAL_11]] (%[[VAL_12]], %[[VAL_13]]) : (!fir.box>, index, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_10]] to %[[VAL_14]] : i32, !fir.ref +! CHECK: omp.terminator +! CHECK: } + diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array.f90 b/flang/test/Lower/OpenMP/parallel-reduction-array.f90 index 32f77e66d17ad8ed353d2c035294c2251182d077..34f4ee0a9eb3a5f26868383211ae597372413c0b 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-array.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-array.f90 @@ -24,7 +24,10 @@ end program ! CHECK: %[[TRUE:.*]] = arith.constant true ! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.heap>, !fir.heap>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_3]], %[[C0]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[SHIFT]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) diff --git a/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 b/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 index 28914e78bf388217185de3ec59828d171447d00d..aa14092554eda28626b3fabed97a9681420eb681 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction-array2.f90 @@ -22,9 +22,11 @@ end program ! CHECK: %[[VAL_5:.*]] = fir.shape %[[VAL_4]] : (index) -> !fir.shape<1> ! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<3xi32> ! CHECK: %[[TRUE:.*]] = arith.constant true -! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, -!fir.shape<1>) -> (!fir.heap>, !fir.heap>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.heap>, !fir.heap>) +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_3]], %[[C0]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[SHIFT]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) diff --git a/flang/test/Lower/OpenMP/parallel-reduction3.f90 b/flang/test/Lower/OpenMP/parallel-reduction3.f90 index 4d25a4c34bd9a4715f083d9708a505a66f24b7b6..2a4e338f255ebb842ff95cf68373f1ad588dccb2 100644 --- a/flang/test/Lower/OpenMP/parallel-reduction3.f90 +++ b/flang/test/Lower/OpenMP/parallel-reduction3.f90 @@ -12,8 +12,12 @@ ! CHECK: %[[VAL_6:.*]] = fir.allocmem !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp", uniq_name = ""} ! CHECK: %[[TRUE:.*]] = arith.constant true ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.box>, !fir.heap>) -! CHECK: hlfir.assign %[[VAL_1]] to %[[VAL_7]]#0 : i32, !fir.box> -! CHECK: fir.store %[[VAL_7]]#0 to %[[VAL_8]] : !fir.ref>> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_2]], %[[C0]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[REBOX:.*]] = fir.rebox %[[VAL_7]]#0(%[[SHIFT]]) : (!fir.box>, !fir.shapeshift<1>) -> !fir.box> +! CHECK: hlfir.assign %[[VAL_1]] to %[[REBOX]] : i32, !fir.box> +! CHECK: fir.store %[[REBOX]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) ! CHECK: } combiner { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>, %[[VAL_1:.*]]: !fir.ref>>): @@ -70,30 +74,33 @@ ! CHECK: %[[VAL_18:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_19:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_12]]#0 to %[[VAL_19]] : !fir.ref>> -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_Uxi32 %[[VAL_19]] -> %[[VAL_20:.*]] : !fir.ref>>) for (%[[VAL_21:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { -! CHECK: fir.store %[[VAL_21]] to %[[VAL_15]]#1 : !fir.ref -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFsEc"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref>> -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_26:.*]]:3 = fir.box_dims %[[VAL_23]], %[[VAL_25]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_27:.*]] = fir.shape %[[VAL_26]]#1 : (index) -> !fir.shape<1> -! CHECK: %[[VAL_28:.*]] = hlfir.elemental %[[VAL_27]] unordered : (!fir.shape<1>) -> !hlfir.expr { -! CHECK: ^bb0(%[[VAL_29:.*]]: index): -! CHECK: %[[VAL_30:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_31:.*]]:3 = fir.box_dims %[[VAL_23]], %[[VAL_30]] : (!fir.box>, index) -> (index, index, index) -! CHECK: %[[VAL_32:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_33:.*]] = arith.subi %[[VAL_31]]#0, %[[VAL_32]] : index -! CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_29]], %[[VAL_33]] : index -! CHECK: %[[VAL_35:.*]] = hlfir.designate %[[VAL_23]] (%[[VAL_34]]) : (!fir.box>, index) -> !fir.ref -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref -! CHECK: %[[VAL_37:.*]] = arith.addi %[[VAL_36]], %[[VAL_24]] : i32 -! CHECK: hlfir.yield_element %[[VAL_37]] : i32 +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_Uxi32 %[[VAL_19]] -> %[[VAL_20:.*]] : !fir.ref>>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_21:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFsEc"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: fir.store %[[VAL_21]] to %[[VAL_15]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref>> +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_26:.*]]:3 = fir.box_dims %[[VAL_23]], %[[VAL_25]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_27:.*]] = fir.shape %[[VAL_26]]#1 : (index) -> !fir.shape<1> +! CHECK: %[[VAL_28:.*]] = hlfir.elemental %[[VAL_27]] unordered : (!fir.shape<1>) -> !hlfir.expr { +! CHECK: ^bb0(%[[VAL_29:.*]]: index): +! CHECK: %[[VAL_30:.*]] = arith.constant 0 : index +! CHECK: %[[VAL_31:.*]]:3 = fir.box_dims %[[VAL_23]], %[[VAL_30]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[VAL_32:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_33:.*]] = arith.subi %[[VAL_31]]#0, %[[VAL_32]] : index +! CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_29]], %[[VAL_33]] : index +! CHECK: %[[VAL_35:.*]] = hlfir.designate %[[VAL_23]] (%[[VAL_34]]) : (!fir.box>, index) -> !fir.ref +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref +! CHECK: %[[VAL_37:.*]] = arith.addi %[[VAL_36]], %[[VAL_24]] : i32 +! CHECK: hlfir.yield_element %[[VAL_37]] : i32 +! CHECK: } +! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref>> +! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_38]] : !hlfir.expr, !fir.box> +! CHECK: hlfir.destroy %[[VAL_28]] : !hlfir.expr +! CHECK: omp.yield ! CHECK: } -! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref>> -! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_38]] : !hlfir.expr, !fir.box> -! CHECK: hlfir.destroy %[[VAL_28]] : !hlfir.expr -! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 b/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 index 716a7d71bb62880c091b246893c78d733bb21815..ac8b9f50f54e67a8f9ff60ec5dba11919ab9f8a3 100644 --- a/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 +++ b/flang/test/Lower/OpenMP/parallel-wsloop-firstpriv.f90 @@ -20,10 +20,14 @@ subroutine omp_do_firstprivate(a) ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 ! CHECK-NEXT: %[[UB:.*]] = fir.load %[[A_PVT_DECL]]#0 : !fir.ref ! CHECK-NEXT: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: omp.wsloop for (%[[ARG1:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) + ! CHECK-NEXT: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { ! CHECK-NEXT: fir.store %[[ARG1]] to %[[I_PVT_DECL]]#1 : !fir.ref ! CHECK-NEXT: fir.call @_QPfoo(%[[I_PVT_DECL]]#1, %[[A_PVT_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref) -> () ! CHECK-NEXT: omp.yield + ! CHECK-NEXT: } + ! CHECK-NEXT: omp.terminator + ! CHECK-NEXT: } do i=1, a call foo(i, a) end do @@ -56,10 +60,12 @@ subroutine omp_do_firstprivate2(a, n) ! CHECK: %[[LB:.*]] = fir.load %[[A_PVT_DECL]]#0 : !fir.ref ! CHECK: %[[UB:.*]] = fir.load %[[N_PVT_DECL]]#0 : !fir.ref ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[ARG2:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[ARG2:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { ! CHECK: fir.store %[[ARG2]] to %[[I_PVT_DECL]]#1 : !fir.ref ! CHECK: fir.call @_QPfoo(%[[I_PVT_DECL]]#1, %[[A_PVT_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref) -> () ! CHECK: omp.yield + ! CHECK: omp.terminator do i= a, n call foo(i, a) end do diff --git a/flang/test/Lower/OpenMP/parallel-wsloop.f90 b/flang/test/Lower/OpenMP/parallel-wsloop.f90 index c06f941b74b582c0523d71908e4e52e04683fbd2..602b3d1c05f0de756f0f6ca64cc7da2e67553ab5 100644 --- a/flang/test/Lower/OpenMP/parallel-wsloop.f90 +++ b/flang/test/Lower/OpenMP/parallel-wsloop.f90 @@ -6,19 +6,21 @@ subroutine simple_parallel_do integer :: i ! CHECK: omp.parallel - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.yield + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -34,19 +36,21 @@ subroutine parallel_do_with_parallel_clauses(cond, nt) ! CHECK: %[[COND_CVT:.*]] = fir.convert %[[COND]] : (!fir.logical<4>) -> i1 ! CHECK: %[[NT:.*]] = fir.load %[[NT_DECL]]#0 : !fir.ref ! CHECK: omp.parallel if(%[[COND_CVT]] : i1) num_threads(%[[NT]] : i32) proc_bind(close) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO IF(cond) NUM_THREADS(nt) PROC_BIND(close) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.yield + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -58,19 +62,21 @@ subroutine parallel_do_with_clauses(nt) integer :: i ! CHECK: %[[NT:.*]] = fir.load %[[NT_DECL]]#0 : !fir.ref ! CHECK: omp.parallel num_threads(%[[NT]] : i32) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop schedule(dynamic) for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop schedule(dynamic) { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO NUM_THREADS(nt) SCHEDULE(dynamic) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield - ! CHECK: omp.terminator + ! CHECK: omp.yield + ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -88,20 +94,21 @@ subroutine parallel_do_with_privatisation_clauses(cond,nt) integer :: nt integer :: i ! CHECK: omp.parallel - ! CHECK: %[[PRIVATE_COND_REF:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} - ! CHECK: %[[PRIVATE_COND_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_COND_REF]] {uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) - ! CHECK: %[[PRIVATE_NT_REF:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} - ! CHECK: %[[PRIVATE_NT_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_NT_REF]] {uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! CHECK: %[[NT_VAL:.*]] = fir.load %[[NT_DECL]]#0 : !fir.ref - ! CHECK: hlfir.assign %[[NT_VAL]] to %[[PRIVATE_NT_DECL]]#0 temporary_lhs : i32, !fir.ref - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[PRIVATE_COND_REF:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} + ! CHECK: %[[PRIVATE_COND_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_COND_REF]] {uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) + ! CHECK: %[[PRIVATE_NT_REF:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} + ! CHECK: %[[PRIVATE_NT_DECL:.*]]:2 = hlfir.declare %[[PRIVATE_NT_REF]] {uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[NT_VAL:.*]] = fir.load %[[NT_DECL]]#0 : !fir.ref + ! CHECK: hlfir.assign %[[NT_VAL]] to %[[PRIVATE_NT_DECL]]#0 temporary_lhs : i32, !fir.ref + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP PARALLEL DO PRIVATE(cond) FIRSTPRIVATE(nt) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref + ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]]#0 : !fir.ref ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 ! CHECK: %[[PRIVATE_COND_VAL:.*]] = fir.load %[[PRIVATE_COND_DECL]]#0 : !fir.ref> ! CHECK: %[[PRIVATE_COND_VAL_CVT:.*]] = fir.convert %[[PRIVATE_COND_VAL]] : (!fir.logical<4>) -> i1 @@ -112,6 +119,7 @@ subroutine parallel_do_with_privatisation_clauses(cond,nt) end do ! CHECK: omp.yield ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL DO end subroutine @@ -150,10 +158,13 @@ end subroutine parallel_private_do ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref -! CHECK: fir.call @_QPfoo(%[[I_PRIV_DECL]]#1, %[[COND_DECL]]#1, %[[NT_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref +! CHECK: fir.call @_QPfoo(%[[I_PRIV_DECL]]#1, %[[COND_DECL]]#1, %[[NT_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -196,10 +207,13 @@ end subroutine omp_parallel_multiple_firstprivate_do ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref -! CHECK: fir.call @_QPbar(%[[I_PRIV_DECL]]#1, %[[A_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref +! CHECK: fir.call @_QPbar(%[[I_PRIV_DECL]]#1, %[[A_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -241,10 +255,13 @@ end subroutine parallel_do_private ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref -! CHECK: fir.call @_QPfoo(%[[I_PRIV_DECL]]#1, %[[COND_PRIV_DECL]]#1, %[[NT_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref +! CHECK: fir.call @_QPfoo(%[[I_PRIV_DECL]]#1, %[[COND_PRIV_DECL]]#1, %[[NT_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -271,9 +288,9 @@ end subroutine omp_parallel_do_multiple_firstprivate ! CHECK-LABEL: func.func @_QPomp_parallel_do_multiple_firstprivate( ! CHECK-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, ! CHECK-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEb"} : (!fir.ref) -> (!fir.ref, !fir.ref -! CHECK: omp.parallel { +! CHECK: %[[A_DECL:.*]]:2 = hlfir.declare %[[A_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEa"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[B_DECL:.*]]:2 = hlfir.declare %[[B_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEb"} : (!fir.ref) -> (!fir.ref, !fir.ref +! CHECK: omp.parallel { ! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} ! CHECK: %[[I_PRIV_DECL:.*]]:2 = hlfir.declare %[[I_PRIV_ADDR]] {uniq_name = "_QFomp_parallel_do_multiple_firstprivateEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) ! CHECK: %[[A_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFomp_parallel_do_multiple_firstprivateEa"} @@ -287,12 +304,15 @@ end subroutine omp_parallel_do_multiple_firstprivate ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref -! CHECK: fir.call @_QPbar(%[[I_PRIV_DECL]]#1, %[[A_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: fir.store %[[I]] to %[[I_PRIV_DECL]]#1 : !fir.ref +! CHECK: fir.call @_QPbar(%[[I_PRIV_DECL]]#1, %[[A_PRIV_DECL]]#1) {{.*}}: (!fir.ref, !fir.ref) -> () +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } -! CHECK: return +! CHECK: return ! CHECK: } diff --git a/flang/test/Lower/OpenMP/stop-stmt-in-region.f90 b/flang/test/Lower/OpenMP/stop-stmt-in-region.f90 index fdbabc21b2c9e94138c7c5ef2d8ded578ed37399..4f3819c5e4eb7c0caf2bd9cc291aa90babba8ffc 100644 --- a/flang/test/Lower/OpenMP/stop-stmt-in-region.f90 +++ b/flang/test/Lower/OpenMP/stop-stmt-in-region.f90 @@ -82,24 +82,27 @@ end ! CHECK: %[[VAL_3:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_4:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop for (%[[VAL_6:.*]]) : i32 = (%[[VAL_3]]) to (%[[VAL_4]]) inclusive step (%[[VAL_5]]) { -! CHECK: fir.store %[[VAL_6]] to %[[VAL_0_DECL]]#1 : !fir.ref -! CHECK: cf.br ^bb1 -! CHECK: ^bb1: -! CHECK: %[[VAL_7:.*]] = arith.constant 3 : i32 -! CHECK: hlfir.assign %[[VAL_7]] to %[[VAL_2_DECL]]#0 : i32, !fir.ref -! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2_DECL]]#0 : !fir.ref -! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_10:.*]] = arith.cmpi sgt, %[[VAL_8]], %[[VAL_9]] : i32 -! CHECK: cf.cond_br %[[VAL_10]], ^bb2, ^bb3 -! CHECK: ^bb2: -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_2_DECL]]#0 : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.constant false -! CHECK: %[[VAL_13:.*]] = arith.constant false -! CHECK: %[[VAL_14:.*]] = fir.call @_FortranAStopStatement(%[[VAL_11]], %[[VAL_12]], %[[VAL_13]]) {{.*}} : (i32, i1, i1) -> none -! CHECK: omp.yield -! CHECK: ^bb3: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_6:.*]]) : i32 = (%[[VAL_3]]) to (%[[VAL_4]]) inclusive step (%[[VAL_5]]) { +! CHECK: fir.store %[[VAL_6]] to %[[VAL_0_DECL]]#1 : !fir.ref +! CHECK: cf.br ^bb1 +! CHECK: ^bb1: +! CHECK: %[[VAL_7:.*]] = arith.constant 3 : i32 +! CHECK: hlfir.assign %[[VAL_7]] to %[[VAL_2_DECL]]#0 : i32, !fir.ref +! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2_DECL]]#0 : !fir.ref +! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 +! CHECK: %[[VAL_10:.*]] = arith.cmpi sgt, %[[VAL_8]], %[[VAL_9]] : i32 +! CHECK: cf.cond_br %[[VAL_10]], ^bb2, ^bb3 +! CHECK: ^bb2: +! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_2_DECL]]#0 : !fir.ref +! CHECK: %[[VAL_12:.*]] = arith.constant false +! CHECK: %[[VAL_13:.*]] = arith.constant false +! CHECK: %[[VAL_14:.*]] = fir.call @_FortranAStopStatement(%[[VAL_11]], %[[VAL_12]], %[[VAL_13]]) {{.*}} : (i32, i1, i1) -> none +! CHECK: omp.yield +! CHECK: ^bb3: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: cf.br ^bb1 ! CHECK: ^bb1: diff --git a/flang/test/Lower/OpenMP/target.f90 b/flang/test/Lower/OpenMP/target.f90 index 51b66327dfb24b087a877a694593033f9afbe555..0f0c736d31625095450d2b038c613e8da505f49b 100644 --- a/flang/test/Lower/OpenMP/target.f90 +++ b/flang/test/Lower/OpenMP/target.f90 @@ -594,7 +594,8 @@ subroutine omp_target_parallel_do !$omp target parallel do map(tofrom: a) !CHECK: %[[I_PVT_ALLOCA:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} !CHECK: %[[I_PVT_DECL:.*]]:2 = hlfir.declare %[[I_PVT_ALLOCA]] {uniq_name = "_QFomp_target_parallel_doEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) - !CHECK: omp.wsloop for (%[[I_VAL:.*]]) : i32 + !CHECK: omp.wsloop { + !CHECK-NEXT: omp.loop_nest (%[[I_VAL:.*]]) : i32 do i = 1, 1024 !CHECK: fir.store %[[I_VAL]] to %[[I_PVT_DECL]]#1 : !fir.ref !CHECK: %[[C10:.*]] = arith.constant 10 : i32 @@ -606,6 +607,8 @@ subroutine omp_target_parallel_do end do !CHECK: omp.yield !CHECK: } + !CHECK: omp.terminator + !CHECK: } !CHECK: omp.terminator !CHECK: } !CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/unstructured.f90 b/flang/test/Lower/OpenMP/unstructured.f90 index e5bf980ce90fd0ba2d82b65135f18cb2f6db8997..6a1331799d54779f782514b18e7da47c5bd373cb 100644 --- a/flang/test/Lower/OpenMP/unstructured.f90 +++ b/flang/test/Lower/OpenMP/unstructured.f90 @@ -70,27 +70,33 @@ end ! CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 ! CHECK: cond_br %{{[0-9]*}}, ^bb2, ^bb4 ! CHECK: ^bb2: // pred: ^bb1 -! CHECK: omp.wsloop for (%[[ARG1:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG1]] to %[[OMP_LOOP_K_DECL]]#1 : !fir.ref -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD_1:.*]] = fir.load %[[OMP_LOOP_K_DECL]]#0 : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_1]]) -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest (%[[ARG1:.*]]) : {{.*}} { +! CHECK: fir.store %[[ARG1]] to %[[OMP_LOOP_K_DECL]]#1 : !fir.ref +! CHECK: @_FortranAioBeginExternalListOutput +! CHECK: %[[LOAD_1:.*]] = fir.load %[[OMP_LOOP_K_DECL]]#0 : !fir.ref +! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_1]]) +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } -! CHECK: omp.wsloop for (%[[ARG2:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG2]] to %[[OMP_LOOP_J_DECL]]#1 : !fir.ref -! CHECK: br ^bb1 -! CHECK: ^bb2: // 2 preds: ^bb1, ^bb5 -! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb6 -! CHECK: ^bb3: // pred: ^bb2 -! CHECK: cond_br %{{[0-9]*}}, ^bb4, ^bb5 -! CHECK: ^bb4: // pred: ^bb3 -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD_2:.*]] = fir.load %[[K_DECL]]#0 : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_2]]) -! CHECK: br ^bb2 -! CHECK: ^bb6: // 2 preds: ^bb2, ^bb4 -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest (%[[ARG2:.*]]) : {{.*}} { +! CHECK: fir.store %[[ARG2]] to %[[OMP_LOOP_J_DECL]]#1 : !fir.ref +! CHECK: br ^bb1 +! CHECK: ^bb2: // 2 preds: ^bb1, ^bb5 +! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb6 +! CHECK: ^bb3: // pred: ^bb2 +! CHECK: cond_br %{{[0-9]*}}, ^bb4, ^bb5 +! CHECK: ^bb4: // pred: ^bb3 +! CHECK: @_FortranAioBeginExternalListOutput +! CHECK: %[[LOAD_2:.*]] = fir.load %[[K_DECL]]#0 : !fir.ref +! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_2]]) +! CHECK: br ^bb2 +! CHECK: ^bb6: // 2 preds: ^bb2, ^bb4 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: br ^bb1 ! CHECK: ^bb4: // pred: ^bb1 @@ -121,20 +127,23 @@ end ! CHECK: omp.parallel { ! CHECK: %[[ALLOCA:.*]] = fir.alloca i32 {{{.*}}, pinned} ! CHECK: %[[OMP_LOOP_J_DECL:.*]]:2 = hlfir.declare %[[ALLOCA]] {uniq_name = "_QFss4Ej"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: omp.wsloop for (%[[ARG:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG]] to %[[OMP_LOOP_J_DECL]]#1 : !fir.ref -! CHECK: %[[COND:.*]] = arith.cmpi eq, %{{.*}}, %{{.*}} -! CHECK: %[[COND_XOR:.*]] = arith.xori %[[COND]], %{{.*}} -! CHECK: fir.if %[[COND_XOR]] { -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD:.*]] = fir.load %[[OMP_LOOP_J_DECL]]#0 : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD]]) -! CHECK: } else { -! CHECK: } -! CHECK-NEXT: omp.yield +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[ARG:.*]]) : {{.*}} { +! CHECK: fir.store %[[ARG]] to %[[OMP_LOOP_J_DECL]]#1 : !fir.ref +! CHECK: %[[COND:.*]] = arith.cmpi eq, %{{.*}}, %{{.*}} +! CHECK: %[[COND_XOR:.*]] = arith.xori %[[COND]], %{{.*}} +! CHECK: fir.if %[[COND_XOR]] { +! CHECK: @_FortranAioBeginExternalListOutput +! CHECK: %[[LOAD:.*]] = fir.load %[[OMP_LOOP_J_DECL]]#0 : !fir.ref +! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD]]) +! CHECK: } else { +! CHECK: } +! CHECK-NEXT: omp.yield +! CHECK-NEXT: } +! CHECK-NEXT: omp.terminator +! CHECK-NEXT: } +! CHECK: omp.terminator ! CHECK-NEXT: } -! CHECK: omp.terminator -! CHECK-NEXT:} subroutine ss4(n) ! CYCLE in OpenMP wsloop constructs !$omp parallel do i = 1, 3 @@ -150,20 +159,23 @@ end ! CHECK-LABEL: func @_QPss5() { ! CHECK: omp.parallel { -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB3:.*]] -! CHECK: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK: ^[[BB3]]: -! CHECK: br ^[[BB2]] -! CHECK: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB3:.*]] +! CHECK: ^[[BB4]]: +! CHECK: br ^[[BB6]] +! CHECK: ^[[BB3]]: +! CHECK: br ^[[BB2]] +! CHECK: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -190,20 +202,23 @@ end ! CHECK: ^[[BB1_OUTER]]: ! CHECK: cond_br %{{.*}}, ^[[BB2_OUTER:.*]], ^[[BB3_OUTER:.*]] ! CHECK: ^[[BB2_OUTER]]: -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK: ^[[BB5]] -! CHECK: br ^[[BB2]] -! CHECK: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] +! CHECK: ^[[BB4]]: +! CHECK: br ^[[BB6]] +! CHECK: ^[[BB5]] +! CHECK: br ^[[BB2]] +! CHECK: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: br ^[[BB1_OUTER]] ! CHECK: ^[[BB3_OUTER]]: @@ -234,20 +249,23 @@ end ! CHECK: cond_br %{{.*}}, ^[[BB2_OUTER:.*]], ^[[BB3_OUTER:.*]] ! CHECK-NEXT: ^[[BB2_OUTER:.*]]: ! CHECK: omp.parallel { -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK-NEXT: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK-NEXT: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK-NEXT: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK-NEXT: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK-NEXT: ^[[BB5]]: -! CHECK: br ^[[BB2]] -! CHECK-NEXT: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK-NEXT: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK-NEXT: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK-NEXT: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] +! CHECK-NEXT: ^[[BB4]]: +! CHECK: br ^[[BB6]] +! CHECK-NEXT: ^[[BB5]]: +! CHECK: br ^[[BB2]] +! CHECK-NEXT: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -272,20 +290,23 @@ end ! CHECK-LABEL: func @_QPss8() { ! CHECK: omp.parallel { -! CHECK: omp.wsloop {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK-NEXT: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK: ^[[BB4]]: -! CHECK-NEXT: br ^[[BB6]] -! CHECK: ^[[BB5]]: -! CHECK: br ^[[BB2]] -! CHECK-NEXT: ^[[BB6]]: -! CHECK: omp.yield +! CHECK: omp.wsloop { +! CHECK: omp.loop_nest {{.*}} { +! CHECK: br ^[[BB1:.*]] +! CHECK-NEXT: ^[[BB1]]: +! CHECK: br ^[[BB2:.*]] +! CHECK: ^[[BB2]]: +! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] +! CHECK: ^[[BB3]]: +! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] +! CHECK: ^[[BB4]]: +! CHECK-NEXT: br ^[[BB6]] +! CHECK: ^[[BB5]]: +! CHECK: br ^[[BB2]] +! CHECK-NEXT: ^[[BB6]]: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-chunks.f90 b/flang/test/Lower/OpenMP/wsloop-chunks.f90 index 5016c8985bda045973a2dd0c919bfac057fa3054..fa6ec219a490ebf54274c1eb3617de45ae3aa114 100644 --- a/flang/test/Lower/OpenMP/wsloop-chunks.f90 +++ b/flang/test/Lower/OpenMP/wsloop-chunks.f90 @@ -20,11 +20,14 @@ do i=1, 9 ! CHECK: %[[VAL_3:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_5:.*]] = arith.constant 4 : i32 -! CHECK: omp.wsloop schedule(static = %[[VAL_5]] : i32) nowait for (%[[ARG0:.*]]) : i32 = (%[[VAL_2]]) to (%[[VAL_3]]) inclusive step (%[[VAL_4]]) { -! CHECK: fir.store %[[ARG0]] to %[[STORE_IV:.*]]#1 : !fir.ref -! CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]]#0 : !fir.ref -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield +! CHECK: omp.wsloop schedule(static = %[[VAL_5]] : i32) nowait { +! CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[VAL_2]]) to (%[[VAL_3]]) inclusive step (%[[VAL_4]]) { +! CHECK: fir.store %[[ARG0]] to %[[STORE_IV:.*]]#1 : !fir.ref +! CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]]#0 : !fir.ref +! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } end do @@ -38,13 +41,16 @@ do i=1, 9 ! CHECK: %[[VAL_15:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_17:.*]] = arith.constant 4 : i32 -! CHECK: omp.wsloop schedule(static = %[[VAL_17]] : i32) nowait for (%[[ARG1:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { -! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]]#1 : !fir.ref -! CHECK: %[[VAL_24:.*]] = arith.constant 2 : i32 -! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_24]], %[[LOAD_IV1]] : i32 -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_25]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield +! CHECK: omp.wsloop schedule(static = %[[VAL_17]] : i32) nowait { +! CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { +! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]]#1 : !fir.ref +! CHECK: %[[VAL_24:.*]] = arith.constant 2 : i32 +! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_24]], %[[LOAD_IV1]] : i32 +! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_25]]) {{.*}}: (!fir.ref, i32) -> i1 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } end do @@ -62,13 +68,16 @@ end do ! CHECK: %[[VAL_30:.*]] = arith.constant 9 : i32 ! CHECK: %[[VAL_31:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_0]]#0 : !fir.ref -! CHECK: omp.wsloop schedule(static = %[[VAL_32]] : i32) nowait for (%[[ARG2:.*]]) : i32 = (%[[VAL_29]]) to (%[[VAL_30]]) inclusive step (%[[VAL_31]]) { -! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]]#1 : !fir.ref -! CHECK: %[[VAL_39:.*]] = arith.constant 3 : i32 -! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]]#0 : !fir.ref -! CHECK: %[[VAL_40:.*]] = arith.muli %[[VAL_39]], %[[LOAD_IV2]] : i32 -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_40]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield +! CHECK: omp.wsloop schedule(static = %[[VAL_32]] : i32) nowait { +! CHECK-NEXT: omp.loop_nest (%[[ARG2:.*]]) : i32 = (%[[VAL_29]]) to (%[[VAL_30]]) inclusive step (%[[VAL_31]]) { +! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]]#1 : !fir.ref +! CHECK: %[[VAL_39:.*]] = arith.constant 3 : i32 +! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]]#0 : !fir.ref +! CHECK: %[[VAL_40:.*]] = arith.muli %[[VAL_39]], %[[LOAD_IV2]] : i32 +! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_40]]) {{.*}}: (!fir.ref, i32) -> i1 +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: return ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-collapse.f90 b/flang/test/Lower/OpenMP/wsloop-collapse.f90 index c93fcf4ef968daaf9ee10ef66880c52b58704d2b..d9541e176f6a81acada33ea841ea74f8aae37343 100644 --- a/flang/test/Lower/OpenMP/wsloop-collapse.f90 +++ b/flang/test/Lower/OpenMP/wsloop-collapse.f90 @@ -49,23 +49,26 @@ program wsloop_collapse !CHECK: %[[VAL_30:.*]] = arith.constant 1 : i32 !CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref !CHECK: %[[VAL_32:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop for (%[[VAL_33:.*]], %[[VAL_34:.*]], %[[VAL_35:.*]]) : i32 = (%[[VAL_24]], %[[VAL_27]], %[[VAL_30]]) to (%[[VAL_25]], %[[VAL_28]], %[[VAL_31]]) inclusive step (%[[VAL_26]], %[[VAL_29]], %[[VAL_32]]) { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[VAL_33:.*]], %[[VAL_34:.*]], %[[VAL_35:.*]]) : i32 = (%[[VAL_24]], %[[VAL_27]], %[[VAL_30]]) to (%[[VAL_25]], %[[VAL_28]], %[[VAL_31]]) inclusive step (%[[VAL_26]], %[[VAL_29]], %[[VAL_32]]) { !$omp do collapse(3) do i = 1, a do j= 1, b do k = 1, c -!CHECK: fir.store %[[VAL_33]] to %[[VAL_5]]#1 : !fir.ref -!CHECK: fir.store %[[VAL_34]] to %[[VAL_3]]#1 : !fir.ref -!CHECK: fir.store %[[VAL_35]] to %[[VAL_1]]#1 : !fir.ref -!CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -!CHECK: %[[VAL_37:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref -!CHECK: %[[VAL_38:.*]] = arith.addi %[[VAL_36]], %[[VAL_37]] : i32 -!CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref -!CHECK: %[[VAL_40:.*]] = arith.addi %[[VAL_38]], %[[VAL_39]] : i32 -!CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref -!CHECK: %[[VAL_42:.*]] = arith.addi %[[VAL_40]], %[[VAL_41]] : i32 -!CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_19]]#0 : i32, !fir.ref -!CHECK: omp.yield +!CHECK: fir.store %[[VAL_33]] to %[[VAL_5]]#1 : !fir.ref +!CHECK: fir.store %[[VAL_34]] to %[[VAL_3]]#1 : !fir.ref +!CHECK: fir.store %[[VAL_35]] to %[[VAL_1]]#1 : !fir.ref +!CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +!CHECK: %[[VAL_37:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref +!CHECK: %[[VAL_38:.*]] = arith.addi %[[VAL_36]], %[[VAL_37]] : i32 +!CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref +!CHECK: %[[VAL_40:.*]] = arith.addi %[[VAL_38]], %[[VAL_39]] : i32 +!CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref +!CHECK: %[[VAL_42:.*]] = arith.addi %[[VAL_40]], %[[VAL_41]] : i32 +!CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_19]]#0 : i32, !fir.ref +!CHECK: omp.yield +!CHECK-NEXT: } +!CHECK-NEXT: omp.terminator x = x + i + j + k end do end do diff --git a/flang/test/Lower/OpenMP/wsloop-monotonic.f90 b/flang/test/Lower/OpenMP/wsloop-monotonic.f90 index fba9105b981813d889036837c2a305a21e01d829..531d995052f6c4711beb5422d3712bab2d07c722 100644 --- a/flang/test/Lower/OpenMP/wsloop-monotonic.f90 +++ b/flang/test/Lower/OpenMP/wsloop-monotonic.f90 @@ -15,19 +15,21 @@ program wsloop_dynamic !CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 !CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 !CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(dynamic, monotonic) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]]#1 : !fir.ref +!CHECK: omp.wsloop schedule(dynamic, monotonic) nowait { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { +!CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]]#1 : !fir.ref do i=1, 9 print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]]#0 : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 +!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput +!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]]#0 : !fir.ref +!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 +!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 end do -!CHECK: omp.yield +!CHECK: omp.yield !CHECK: omp.terminator -!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$OMP END DO NOWAIT !$OMP END PARALLEL diff --git a/flang/test/Lower/OpenMP/wsloop-nonmonotonic.f90 b/flang/test/Lower/OpenMP/wsloop-nonmonotonic.f90 index 1bd7a2edc0f523396f5ce38f94bfc08357b3dfcf..420bc0bffaece3c62214124b0ab84983bc454e87 100644 --- a/flang/test/Lower/OpenMP/wsloop-nonmonotonic.f90 +++ b/flang/test/Lower/OpenMP/wsloop-nonmonotonic.f90 @@ -17,20 +17,23 @@ program wsloop_dynamic !CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 !CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 !CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(dynamic, nonmonotonic) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[ALLOCA_IV]]#1 : !fir.ref +!CHECK: omp.wsloop schedule(dynamic, nonmonotonic) nowait { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { +!CHECK: fir.store %[[I]] to %[[ALLOCA_IV]]#1 : !fir.ref do i=1, 9 print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]]#0 : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 +!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput +!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]]#0 : !fir.ref +!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 +!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 end do -!CHECK: omp.yield -!CHECK: } +!CHECK: omp.yield +!CHECK: } !CHECK: omp.terminator !CHECK: } +!CHECK: omp.terminator +!CHECK: } !$OMP END DO NOWAIT !$OMP END PARALLEL diff --git a/flang/test/Lower/OpenMP/wsloop-ordered.f90 b/flang/test/Lower/OpenMP/wsloop-ordered.f90 index 5185d2d085bac7ee1b1aca55a2a3ff76250b1db4..f4fa81c52315c8827f5545352313f131d18da79e 100644 --- a/flang/test/Lower/OpenMP/wsloop-ordered.f90 +++ b/flang/test/Lower/OpenMP/wsloop-ordered.f90 @@ -6,9 +6,12 @@ subroutine wsloop_ordered_no_para() integer :: a(10), i -! CHECK: omp.wsloop ordered(0) for (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop ordered(0) { +! CHECK-NEXT: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator +! CHECK: } !$omp do ordered do i = 2, 10 @@ -25,9 +28,12 @@ subroutine wsloop_ordered_with_para() integer :: a(10), i ! CHECK: func @_QPwsloop_ordered_with_para() { -! CHECK: omp.wsloop ordered(1) for (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop ordered(1) { +! CHECK-NEXT: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator +! CHECK: } !$omp do ordered(1) do i = 2, 10 diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90 index e63db33bbe2505530e8539f895cc74cc0f5e325b..c9d03435d9e18c7861dc1430714a9038716f3c2e 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-add-byref.f90 @@ -82,14 +82,17 @@ ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -122,15 +125,18 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 -! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_13]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 +! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_13]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -163,14 +169,17 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -202,15 +211,18 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_14]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_14]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -250,24 +262,27 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.addi %[[VAL_23]], %[[VAL_24]] : i32 -! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = arith.addi %[[VAL_26]], %[[VAL_27]] : i32 -! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_31:.*]] = arith.addi %[[VAL_29]], %[[VAL_30]] : i32 -! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.addi %[[VAL_23]], %[[VAL_24]] : i32 +! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref +! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = arith.addi %[[VAL_26]], %[[VAL_27]] : i32 +! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_31:.*]] = arith.addi %[[VAL_29]], %[[VAL_30]] : i32 +! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -311,27 +326,30 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 -! CHECK: %[[VAL_30:.*]] = arith.addf %[[VAL_27]], %[[VAL_29]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 -! CHECK: %[[VAL_34:.*]] = arith.addf %[[VAL_31]], %[[VAL_33]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 +! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 +! CHECK: %[[VAL_30:.*]] = arith.addf %[[VAL_27]], %[[VAL_29]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 +! CHECK: %[[VAL_34:.*]] = arith.addf %[[VAL_31]], %[[VAL_33]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -379,32 +397,35 @@ end subroutine ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_17:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_18:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @add_reduction_byref_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @add_reduction_byref_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) for (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { -! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref -! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = arith.addi %[[VAL_28]], %[[VAL_29]] : i32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 -! CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_31]], %[[VAL_33]] : i64 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref -! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 -! CHECK: %[[VAL_38:.*]] = arith.addf %[[VAL_35]], %[[VAL_37]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 -! CHECK: %[[VAL_42:.*]] = arith.addf %[[VAL_39]], %[[VAL_41]] fastmath : f64 -! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @add_reduction_byref_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @add_reduction_byref_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { +! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = arith.addi %[[VAL_28]], %[[VAL_29]] : i32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 +! CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_31]], %[[VAL_33]] : i64 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref +! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 +! CHECK: %[[VAL_38:.*]] = arith.addf %[[VAL_35]], %[[VAL_37]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 +! CHECK: %[[VAL_42:.*]] = arith.addf %[[VAL_39]], %[[VAL_41]] fastmath : f64 +! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90 index 3b4d9666c693733a9d4b8ea7cf5c8063678607ab..6a09fece80ae9d5d2d776871cdd3621eaeca997e 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir-byref.f90 @@ -31,14 +31,16 @@ ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90 index 7c9070592e468e1e3d14c35110b8b0ee95c17caf..c5cc5a95cef177d76b4aea0219ccee3ef3177577 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-add-hlfir.f90 @@ -27,14 +27,16 @@ ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-add.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-add.f90 index 11e1ffb79f8e4ee4d45b1bdf22bdf9696216cc7f..5b957959f40d50d44914be42543af1555703d077 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-add.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-add.f90 @@ -58,14 +58,17 @@ ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -98,15 +101,18 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 -! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_13]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 +! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_13]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -139,14 +145,17 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -178,15 +187,18 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_14]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.addf %[[VAL_14]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -226,24 +238,27 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.addi %[[VAL_23]], %[[VAL_24]] : i32 -! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = arith.addi %[[VAL_26]], %[[VAL_27]] : i32 -! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_31:.*]] = arith.addi %[[VAL_29]], %[[VAL_30]] : i32 -! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.addi %[[VAL_23]], %[[VAL_24]] : i32 +! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref +! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = arith.addi %[[VAL_26]], %[[VAL_27]] : i32 +! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_31:.*]] = arith.addi %[[VAL_29]], %[[VAL_30]] : i32 +! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -287,27 +302,30 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 -! CHECK: %[[VAL_30:.*]] = arith.addf %[[VAL_27]], %[[VAL_29]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 -! CHECK: %[[VAL_34:.*]] = arith.addf %[[VAL_31]], %[[VAL_33]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 +! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 +! CHECK: %[[VAL_30:.*]] = arith.addf %[[VAL_27]], %[[VAL_29]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 +! CHECK: %[[VAL_34:.*]] = arith.addf %[[VAL_31]], %[[VAL_33]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } @@ -355,32 +373,35 @@ end subroutine ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_17:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_18:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @add_reduction_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @add_reduction_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) for (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { -! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref -! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = arith.addi %[[VAL_28]], %[[VAL_29]] : i32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 -! CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_31]], %[[VAL_33]] : i64 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref -! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 -! CHECK: %[[VAL_38:.*]] = arith.addf %[[VAL_35]], %[[VAL_37]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 -! CHECK: %[[VAL_42:.*]] = arith.addf %[[VAL_39]], %[[VAL_41]] fastmath : f64 -! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @add_reduction_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @add_reduction_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { +! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = arith.addi %[[VAL_28]], %[[VAL_29]] : i32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 +! CHECK: %[[VAL_34:.*]] = arith.addi %[[VAL_31]], %[[VAL_33]] : i64 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref +! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 +! CHECK: %[[VAL_38:.*]] = arith.addf %[[VAL_35]], %[[VAL_37]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 +! CHECK: %[[VAL_42:.*]] = arith.addf %[[VAL_39]], %[[VAL_41]] fastmath : f64 +! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90 index fe3a2505d17c0459ba2b65e64f842d63c09f07fd..8310aeb23df088967f2d36abf1ab44872ae10c8e 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-allocatable.f90 @@ -80,14 +80,17 @@ end program ! CHECK: %[[VAL_11:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_12:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_heap_i32 %[[VAL_5]]#0 -> %[[VAL_14:.*]] : !fir.ref>>) for (%[[VAL_15:.*]]) : i32 = (%[[VAL_11]]) to (%[[VAL_12]]) inclusive step (%[[VAL_13]]) { -! CHECK: fir.store %[[VAL_15]] to %[[VAL_10]]#1 : !fir.ref -! CHECK: %[[VAL_16:.*]]:2 = hlfir.declare %[[VAL_14]] {fortran_attrs = {{.*}}, uniq_name = "_QFEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_10]]#0 : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_16]]#0 : !fir.ref>> -! CHECK: %[[VAL_19:.*]] = fir.box_addr %[[VAL_18]] : (!fir.box>) -> !fir.heap -! CHECK: hlfir.assign %[[VAL_17]] to %[[VAL_19]] : i32, !fir.heap -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_heap_i32 %[[VAL_5]]#0 -> %[[VAL_14:.*]] : !fir.ref>>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_15:.*]]) : i32 = (%[[VAL_11]]) to (%[[VAL_12]]) inclusive step (%[[VAL_13]]) { +! CHECK: %[[VAL_16:.*]]:2 = hlfir.declare %[[VAL_14]] {fortran_attrs = {{.*}}, uniq_name = "_QFEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: fir.store %[[VAL_15]] to %[[VAL_10]]#1 : !fir.ref +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_10]]#0 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_16]]#0 : !fir.ref>> +! CHECK: %[[VAL_19:.*]] = fir.box_addr %[[VAL_18]] : (!fir.box>) -> !fir.heap +! CHECK: hlfir.assign %[[VAL_17]] to %[[VAL_19]] : i32, !fir.heap +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 index c22407cd35ad01979ac1503548dc9460807151db..6c9bc75b81d70073b692c0fcb818ae40101d0524 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array-assumed-shape.f90 @@ -33,10 +33,13 @@ end program ! CHECK: %[[VAL_6:.*]] = fir.allocmem !fir.array, %[[VAL_4]]#1 {bindc_name = ".tmp", uniq_name = ""} ! CHECK: %[[TRUE:.*]] = arith.constant true ! CHECK: %[[VAL_7:.*]]:2 = hlfir.declare %[[VAL_6]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.box>, !fir.heap>) -! CHECK: hlfir.assign %[[VAL_1]] to %[[VAL_7]]#0 : f64, !fir.box> -! CHECK: fir.store %[[VAL_7]]#0 to %[[VAL_8]] : !fir.ref>> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_2]], %[[C0]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[REBOX:.*]] = fir.rebox %[[VAL_7]]#0(%[[SHIFT]]) : (!fir.box>, !fir.shapeshift<1>) -> !fir.box +! CHECK: hlfir.assign %[[VAL_1]] to %[[REBOX]] : f64, !fir.box> +! CHECK: fir.store %[[REBOX]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) - ! CHECK-LABEL: } combiner { ! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>>, %[[VAL_1:.*]]: !fir.ref>>): ! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref>> @@ -81,21 +84,24 @@ end program ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_9:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_3]]#1 to %[[VAL_9]] : !fir.ref>> -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_Uxf64 %[[VAL_9]] -> %[[VAL_10:.*]] : !fir.ref>>) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_5]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {fortran_attrs = {{.*}}, uniq_name = "_QFFreduceEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f64 -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref>> -! CHECK: %[[VAL_16:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_15]] (%[[VAL_16]]) : (!fir.box>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_14]] to %[[VAL_17]] : f64, !fir.ref -! CHECK: %[[VAL_18:.*]] = arith.constant 1.000000e+00 : f64 -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref>> -! CHECK: %[[VAL_20:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_19]] (%[[VAL_20]]) : (!fir.box>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_18]] to %[[VAL_21]] : f64, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_Uxf64 %[[VAL_9]] -> %[[VAL_10:.*]] : !fir.ref>>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {fortran_attrs = {{.*}}, uniq_name = "_QFFreduceEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_5]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f64 +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref>> +! CHECK: %[[VAL_16:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_15]] (%[[VAL_16]]) : (!fir.box>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_14]] to %[[VAL_17]] : f64, !fir.ref +! CHECK: %[[VAL_18:.*]] = arith.constant 1.000000e+00 : f64 +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref>> +! CHECK: %[[VAL_20:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_19]] (%[[VAL_20]]) : (!fir.box>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_18]] to %[[VAL_21]] : f64, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 index ef122e81d392785b0fa408ac9a5844df304904fe..7aecf870cf800a60bc1b99639ce30c690dfd8993 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array.f90 @@ -24,7 +24,10 @@ end program ! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<2xi32> {bindc_name = ".tmp", uniq_name = ""} ! CHECK: %[[TRUE:.*]] = arith.constant true ! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.heap>, !fir.heap>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_3]], %[[C0]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[SHIFT]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) @@ -76,22 +79,25 @@ end program ! CHECK: %[[VAL_11:.*]] = fir.embox %[[VAL_5]]#0(%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> ! CHECK: %[[VAL_12:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_11]] to %[[VAL_12]] : !fir.ref>> -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_2xi32 %[[VAL_12]] -> %[[VAL_13:.*]] : !fir.ref>>) for (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]]#1 : !fir.ref -! CHECK: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_13]] {uniq_name = "_QFEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> -! CHECK: %[[VAL_18:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_19:.*]] = hlfir.designate %[[VAL_17]] (%[[VAL_18]]) : (!fir.box>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_19]] : i32, !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref -! CHECK: %[[VAL_21:.*]] = arith.constant 0 : i32 -! CHECK: %[[VAL_22:.*]] = arith.subi %[[VAL_21]], %[[VAL_20]] : i32 -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> -! CHECK: %[[VAL_24:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_25:.*]] = hlfir.designate %[[VAL_23]] (%[[VAL_24]]) : (!fir.box>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_22]] to %[[VAL_25]] : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_2xi32 %[[VAL_12]] -> %[[VAL_13:.*]] : !fir.ref>>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_13]] {uniq_name = "_QFEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]]#1 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref +! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> +! CHECK: %[[VAL_18:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_19:.*]] = hlfir.designate %[[VAL_17]] (%[[VAL_18]]) : (!fir.box>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_19]] : i32, !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref +! CHECK: %[[VAL_21:.*]] = arith.constant 0 : i32 +! CHECK: %[[VAL_22:.*]] = arith.subi %[[VAL_21]], %[[VAL_20]] : i32 +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> +! CHECK: %[[VAL_24:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_25:.*]] = hlfir.designate %[[VAL_23]] (%[[VAL_24]]) : (!fir.box>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_22]] to %[[VAL_25]] : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 index 6de8c8eb2e48d7e41c8de152a77ae8324c6114b4..d1d8a2c599444af8d77bbb233b9631dbe0e02d87 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-array2.f90 @@ -24,7 +24,10 @@ end program ! CHECK: %[[VAL_1:.*]] = fir.allocmem !fir.array<2xi32> {bindc_name = ".tmp", uniq_name = ""} ! CHECK: %[[TRUE:.*]] = arith.constant true ! CHECK: %[[VAL_6:.*]]:2 = hlfir.declare %[[VAL_1]](%[[VAL_5]]) {uniq_name = ".tmp"} : (!fir.heap>, !fir.shape<1>) -> (!fir.heap>, !fir.heap>) -! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[VAL_5]]) : (!fir.heap>, !fir.shape<1>) -> !fir.box> +! CHECK: %[[C0:.*]] = arith.constant 0 : index +! CHECK: %[[DIMS:.*]]:3 = fir.box_dims %[[VAL_3]], %[[C0]] : (!fir.box>, index) -> (index, index, index) +! CHECK: %[[SHIFT:.*]] = fir.shape_shift %[[DIMS]]#0, %[[DIMS]]#1 : (index, index) -> !fir.shapeshift<1> +! CHECK: %[[VAL_7:.*]] = fir.embox %[[VAL_6]]#0(%[[SHIFT]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box> ! CHECK: hlfir.assign %[[VAL_2]] to %[[VAL_7]] : i32, !fir.box> ! CHECK: fir.store %[[VAL_7]] to %[[VAL_8]] : !fir.ref>> ! CHECK: omp.yield(%[[VAL_8]] : !fir.ref>>) @@ -76,30 +79,33 @@ end program ! CHECK: %[[VAL_11:.*]] = fir.embox %[[VAL_5]]#0(%[[VAL_4]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box> ! CHECK: %[[VAL_12:.*]] = fir.alloca !fir.box> ! CHECK: fir.store %[[VAL_11]] to %[[VAL_12]] : !fir.ref>> -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_2xi32 %[[VAL_12]] -> %[[VAL_13:.*]] : !fir.ref>>) for (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]]#1 : !fir.ref -! CHECK: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_13]] {uniq_name = "_QFEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> -! CHECK: %[[VAL_17:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_18:.*]] = hlfir.designate %[[VAL_16]] (%[[VAL_17]]) : (!fir.box>, index) -> !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_18]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref -! CHECK: %[[VAL_21:.*]] = arith.addi %[[VAL_19]], %[[VAL_20]] : i32 -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> -! CHECK: %[[VAL_23:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_24:.*]] = hlfir.designate %[[VAL_22]] (%[[VAL_23]]) : (!fir.box>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_24]] : i32, !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> -! CHECK: %[[VAL_26:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_27:.*]] = hlfir.designate %[[VAL_25]] (%[[VAL_26]]) : (!fir.box>, index) -> !fir.ref -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_27]] : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = arith.subi %[[VAL_28]], %[[VAL_29]] : i32 -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> -! CHECK: %[[VAL_32:.*]] = arith.constant 2 : index -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_31]] (%[[VAL_32]]) : (!fir.box>, index) -> !fir.ref -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_33]] : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@add_reduction_byref_box_2xi32 %[[VAL_12]] -> %[[VAL_13:.*]] : !fir.ref>>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { +! CHECK: %[[VAL_15:.*]]:2 = hlfir.declare %[[VAL_13]] {uniq_name = "_QFEr"} : (!fir.ref>>) -> (!fir.ref>>, !fir.ref>>) +! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]]#1 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> +! CHECK: %[[VAL_17:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_18:.*]] = hlfir.designate %[[VAL_16]] (%[[VAL_17]]) : (!fir.box>, index) -> !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_18]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref +! CHECK: %[[VAL_21:.*]] = arith.addi %[[VAL_19]], %[[VAL_20]] : i32 +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> +! CHECK: %[[VAL_23:.*]] = arith.constant 1 : index +! CHECK: %[[VAL_24:.*]] = hlfir.designate %[[VAL_22]] (%[[VAL_23]]) : (!fir.box>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_24]] : i32, !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> +! CHECK: %[[VAL_26:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_27:.*]] = hlfir.designate %[[VAL_25]] (%[[VAL_26]]) : (!fir.box>, index) -> !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_27]] : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = arith.subi %[[VAL_28]], %[[VAL_29]] : i32 +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref>> +! CHECK: %[[VAL_32:.*]] = arith.constant 2 : index +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_31]] (%[[VAL_32]]) : (!fir.box>, index) -> !fir.ref +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_33]] : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 index e3f06a446ed4c1aca20da314624f04fb24594132..40280c56dad6b3bcffbb02c36e22ab0944287908 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-iand-byref.f90 @@ -35,17 +35,19 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@iand_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iandEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.andi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@iand_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iandEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.andi %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 index 746617e210624b666e48c57c5a061b53f425a73e..986892d3584f945665cb0beac50c895f57e54259 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-iand.f90 @@ -29,17 +29,19 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@iand_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iandEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.andi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@iand_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iandEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.andi %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 index 7e3a283bf783c8f436765e317634cbab83aacef5..ee33ce2f348d874adaf52901aa9e99e064dc5370 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ieor-byref.f90 @@ -28,9 +28,10 @@ !CHECK: omp.parallel !CHECK: %[[I_REF:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} !CHECK: %[[I_DECL:.*]]:2 = hlfir.declare %[[I_REF]] {uniq_name = "_QFreduction_ieorEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop byref reduction(@ieor_byref_i32 %[[X_DECL]]#0 -> %[[PRV:.+]] : !fir.ref) for -!CHECK: fir.store %{{.*}} to %[[I_DECL]]#1 : !fir.ref +!CHECK: omp.wsloop byref reduction(@ieor_byref_i32 %[[X_DECL]]#0 -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[PRV_DECL:.+]]:2 = hlfir.declare %[[PRV]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: fir.store %{{.*}} to %[[I_DECL]]#1 : !fir.ref !CHECK: %[[I_32:.*]] = fir.load %[[I_DECL]]#0 : !fir.ref !CHECK: %[[I_64:.*]] = fir.convert %[[I_32]] : (i32) -> i64 !CHECK: %[[Y_I_REF:.*]] = hlfir.designate %[[Y_DECL]]#0 (%[[I_64]]) : (!fir.box>, i64) -> !fir.ref @@ -40,6 +41,7 @@ !CHECK: hlfir.assign %[[RES]] to %[[PRV_DECL]]#0 : i32, !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_ieor(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 index 11245c4ac95e034bed6488bf7222da9b36fd3973..b362731b33710a86ea764dc6a58c6bc7abde2e9b 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ieor.f90 @@ -19,9 +19,10 @@ !CHECK: omp.parallel !CHECK: %[[I_REF:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} !CHECK: %[[I_DECL:.*]]:2 = hlfir.declare %[[I_REF]] {uniq_name = "_QFreduction_ieorEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop reduction(@[[IEOR_DECLARE_I]] %[[X_DECL]]#0 -> %[[PRV:.+]] : !fir.ref) for -!CHECK: fir.store %{{.*}} to %[[I_DECL]]#1 : !fir.ref +!CHECK: omp.wsloop reduction(@[[IEOR_DECLARE_I]] %[[X_DECL]]#0 -> %[[PRV:.+]] : !fir.ref) +!CHECK-NEXT: omp.loop_nest !CHECK: %[[PRV_DECL:.+]]:2 = hlfir.declare %[[PRV]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: fir.store %{{.*}} to %[[I_DECL]]#1 : !fir.ref !CHECK: %[[I_32:.*]] = fir.load %[[I_DECL]]#0 : !fir.ref !CHECK: %[[I_64:.*]] = fir.convert %[[I_32]] : (i32) -> i64 !CHECK: %[[Y_I_REF:.*]] = hlfir.designate %[[Y_DECL]]#0 (%[[I_64]]) : (!fir.box>, i64) -> !fir.ref @@ -31,6 +32,7 @@ !CHECK: hlfir.assign %[[RES]] to %[[PRV_DECL]]#0 : i32, !fir.ref !CHECK: omp.yield !CHECK: omp.terminator +!CHECK: omp.terminator subroutine reduction_ieor(y) integer :: x, y(:) diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 index c7f8e8bdede5480d45d401dc04e8a3386824a87e..0052773bb5adc61a90a917761a3d9d6a5b8a2831 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ior-byref.f90 @@ -33,17 +33,19 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@ior_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.ori %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@ior_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.ori %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 index dd0bbeb1a0761f097cf5e6916c872b20c5f71374..f32be43b9b71a53a613de2b243b6e804f79732a5 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-ior.f90 @@ -29,17 +29,19 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@ior_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.ori %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@ior_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_iorEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.ori %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_20]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 index 59411534e4a5c074a25066a7c67901861c3fc668..dfc018ed7c5aa8a29e5c7ff4c255569af33a7b2f 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and-byref.f90 @@ -42,20 +42,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -90,20 +92,22 @@ end subroutine simple_reduction ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -147,42 +151,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@and_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @and_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @and_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.andi %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.andi %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.andi %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@and_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @and_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @and_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.andi %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.andi %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.andi %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 index 9ca733281c2f031376b9b2caa3a5945c4f2bcbec..c529bd4755b6c667e173d462c5c024523c387d22 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-and.f90 @@ -36,20 +36,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -84,20 +86,22 @@ end subroutine simple_reduction ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@and_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.andi %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -141,42 +145,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@and_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @and_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @and_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.andi %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.andi %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.andi %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@and_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @and_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @and_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.andi %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.andi %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.andi %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 index 1d6e1b0545c3bcffb96d7d47697d39b55d6e2845..a54795a4446f4719ad9c6095aa2814e21321ad48 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv-byref.f90 @@ -42,20 +42,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -89,20 +91,22 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -146,42 +150,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @eqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @eqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.cmpi eq, %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.cmpi eq, %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.cmpi eq, %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @eqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @eqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.cmpi eq, %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.cmpi eq, %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.cmpi eq, %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 index a1bfa462cd599ae4171e96b0c00ed37f0a384f40..1021b5926b9179866b244c0e8fdc45ff7be1e996 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-eqv.f90 @@ -36,20 +36,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -83,20 +85,22 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi eq, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -140,42 +144,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @eqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @eqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.cmpi eq, %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.cmpi eq, %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.cmpi eq, %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @eqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @eqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.cmpi eq, %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.cmpi eq, %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.cmpi eq, %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 index a94b67a97832fc5aee066c09a4f84e1151c8aa9c..854cb19ecd750ce053e8d8053f788f7c7dca8fc6 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv-byref.f90 @@ -42,20 +42,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -90,20 +92,22 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -149,42 +153,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @neqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @neqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.cmpi ne, %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.cmpi ne, %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.cmpi ne, %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @neqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @neqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.cmpi ne, %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.cmpi ne, %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.cmpi ne, %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 index 08d6a2efd3993627cb6ea33977346d6452f60eef..f5c84aaaf4858b5ff5663a6aa28544c5d8da3d6d 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-neqv.f90 @@ -36,20 +36,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -84,20 +86,22 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.cmpi ne, %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -143,42 +147,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @neqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @neqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.cmpi ne, %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.cmpi ne, %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.cmpi ne, %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @neqv_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @neqv_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.cmpi ne, %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.cmpi ne, %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.cmpi ne, %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 index ca69ccee4a38e34258475429de708a31cb7b6d8b..e268c6ff6cf51e10eefaef6efbf617b8785ef31f 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or-byref.f90 @@ -41,20 +41,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -88,20 +90,22 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -145,42 +149,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@or_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @or_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @or_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.ori %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.ori %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.ori %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@or_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @or_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @or_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.ori %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.ori %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.ori %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 index c4bf8e9d65ae7bc7d6a67d2c1443b6f54f794275..26dc0c327aad1a818c1133846ef01b8f424312c4 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-logical-or.f90 @@ -36,20 +36,22 @@ ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 -! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reductionEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = fir.convert %[[VAL_19]] : (i32) -> i64 +! CHECK: %[[VAL_21:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_20]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_21]] : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_18]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -83,20 +85,22 @@ end subroutine ! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) for (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref -! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 -! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@or_reduction %[[VAL_4]]#0 -> %[[VAL_15:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_16:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { +! CHECK: %[[VAL_17:.*]]:2 = hlfir.declare %[[VAL_15]] {uniq_name = "_QFsimple_reduction_switch_orderEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_16]] to %[[VAL_11]]#1 : !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_11]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_18]] : (i32) -> i64 +! CHECK: %[[VAL_20:.*]] = hlfir.designate %[[VAL_7]]#0 (%[[VAL_19]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_20]] : !fir.ref> +! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref> +! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_21]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_24:.*]] = fir.convert %[[VAL_22]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_25:.*]] = arith.ori %[[VAL_23]], %[[VAL_24]] : i1 +! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_25]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_17]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -140,42 +144,44 @@ end subroutine ! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_21:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@or_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @or_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @or_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) for (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { -! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> -! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_37:.*]] = arith.ori %[[VAL_35]], %[[VAL_36]] : i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 -! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> -! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_46:.*]] = arith.ori %[[VAL_44]], %[[VAL_45]] : i1 -! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> -! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 -! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> -! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_55:.*]] = arith.ori %[[VAL_53]], %[[VAL_54]] : i1 -! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> -! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@or_reduction %[[VAL_7]]#0 -> %[[VAL_23:.*]] : !fir.ref>, @or_reduction %[[VAL_9]]#0 -> %[[VAL_24:.*]] : !fir.ref>, @or_reduction %[[VAL_11]]#0 -> %[[VAL_25:.*]] : !fir.ref>) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_26:.*]]) : i32 = (%[[VAL_20]]) to (%[[VAL_21]]) inclusive step (%[[VAL_22]]) { +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_23]] {uniq_name = "_QFmultiple_reductionsEx"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_28:.*]]:2 = hlfir.declare %[[VAL_24]] {uniq_name = "_QFmultiple_reductionsEy"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: %[[VAL_29:.*]]:2 = hlfir.declare %[[VAL_25]] {uniq_name = "_QFmultiple_reductionsEz"} : (!fir.ref>) -> (!fir.ref>, !fir.ref>) +! CHECK: fir.store %[[VAL_26]] to %[[VAL_19]]#1 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref> +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 +! CHECK: %[[VAL_33:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_32]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_34:.*]] = fir.load %[[VAL_33]] : !fir.ref> +! CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_36:.*]] = fir.convert %[[VAL_34]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_37:.*]] = arith.ori %[[VAL_35]], %[[VAL_36]] : i1 +! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_37]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_27]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_28]]#0 : !fir.ref> +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> i64 +! CHECK: %[[VAL_42:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_41]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_43:.*]] = fir.load %[[VAL_42]] : !fir.ref> +! CHECK: %[[VAL_44:.*]] = fir.convert %[[VAL_39]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_43]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_46:.*]] = arith.ori %[[VAL_44]], %[[VAL_45]] : i1 +! CHECK: %[[VAL_47:.*]] = fir.convert %[[VAL_46]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_28]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: %[[VAL_48:.*]] = fir.load %[[VAL_29]]#0 : !fir.ref> +! CHECK: %[[VAL_49:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +! CHECK: %[[VAL_50:.*]] = fir.convert %[[VAL_49]] : (i32) -> i64 +! CHECK: %[[VAL_51:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_50]]) : (!fir.ref>>, i64) -> !fir.ref> +! CHECK: %[[VAL_52:.*]] = fir.load %[[VAL_51]] : !fir.ref> +! CHECK: %[[VAL_53:.*]] = fir.convert %[[VAL_48]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_52]] : (!fir.logical<4>) -> i1 +! CHECK: %[[VAL_55:.*]] = arith.ori %[[VAL_53]], %[[VAL_54]] : i1 +! CHECK: %[[VAL_56:.*]] = fir.convert %[[VAL_55]] : (i1) -> !fir.logical<4> +! CHECK: hlfir.assign %[[VAL_56]] to %[[VAL_29]]#0 : !fir.logical<4>, !fir.ref> +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 index 2f6921edcb42a5225893915e7663362e94f53f52..95bdc98f18c2bc0da4c45c47a31fd00681aa3022 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max-byref.f90 @@ -46,18 +46,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK-LABEL: func.func @_QPreduction_max_real( @@ -75,18 +77,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpf ogt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpf ogt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: omp.parallel { ! CHECK: %[[VAL_30:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} @@ -94,24 +98,26 @@ ! CHECK: %[[VAL_32:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_33:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_34:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) for (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { -! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref -! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 -! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref -! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 -! CHECK: fir.if %[[VAL_43]] { -! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 -! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref -! CHECK: } else { -! CHECK: } -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { +! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref +! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 +! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref +! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 +! CHECK: fir.if %[[VAL_43]] { +! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 +! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref +! CHECK: } else { +! CHECK: } +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 index 10bba6ac4b51bddb31ad4211103b2f2ef0ab6be2..352888bb94f51219c31f82585e6f74ed12f12718 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir-byref.f90 @@ -33,18 +33,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 index 5ea5d6626f186d6e93f0f8e544aaab1d3163cf8b..f4caea5a269a181281dbcdebdf66e7ab0b127e56 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max-hlfir.f90 @@ -29,18 +29,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@max_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@max_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 index c9cf5cbf4f8c02d367de1b397b37ac8c6df5742b..ff005f32487e41f4882d59b3f63cc768638ecf30 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-max.f90 @@ -40,18 +40,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@max_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@max_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpi sgt, %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK-LABEL: func.func @_QPreduction_max_real( @@ -69,18 +71,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@max_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpf ogt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@max_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpf ogt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: omp.parallel { ! CHECK: %[[VAL_30:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} @@ -88,24 +92,26 @@ ! CHECK: %[[VAL_32:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_33:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_34:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@max_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) for (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { -! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref -! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 -! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref -! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 -! CHECK: fir.if %[[VAL_43]] { -! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 -! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref -! CHECK: } else { -! CHECK: } -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@max_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { +! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_max_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref +! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 +! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref +! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 +! CHECK: fir.if %[[VAL_43]] { +! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 +! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref +! CHECK: } else { +! CHECK: } +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 index 84a376b46b8fbe607a650d7a0127fb7c6bc2306b..9787512ab078aeab88c97def499b5c651b1bca48 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-min-byref.f90 @@ -46,18 +46,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpi slt, %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpi slt, %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK-LABEL: func.func @_QPreduction_min_real( @@ -75,19 +77,21 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpf olt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpf olt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.parallel { @@ -96,24 +100,26 @@ ! CHECK: %[[VAL_32:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_33:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_34:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) for (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { -! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref -! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 -! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref -! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 -! CHECK: fir.if %[[VAL_43]] { -! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 -! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref -! CHECK: } else { -! CHECK: } -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { +! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref +! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 +! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref +! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 +! CHECK: fir.if %[[VAL_43]] { +! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 +! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref +! CHECK: } else { +! CHECK: } +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 index 3ba279acd14c41f8d821ea62520a14a8483e70a7..801ef99480a21cdb503f59ff951fb6da8103adfd 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-min.f90 @@ -40,18 +40,20 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@min_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpi slt, %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@min_i32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_intEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpi slt, %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : i32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK-LABEL: func.func @_QPreduction_min_real( @@ -69,19 +71,21 @@ ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_10:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_11:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@min_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) for (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref -! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 -! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.cmpf olt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 -! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 -! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop reduction(@min_f32 %[[VAL_4]]#0 -> %[[VAL_12:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_13:.*]]) : i32 = (%[[VAL_9]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { +! CHECK: %[[VAL_14:.*]]:2 = hlfir.declare %[[VAL_12]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_13]] to %[[VAL_8]]#1 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_8]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> i64 +! CHECK: %[[VAL_17:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_16]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_17]] : !fir.ref +! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_14]]#0 : !fir.ref +! CHECK: %[[VAL_20:.*]] = arith.cmpf olt, %[[VAL_18]], %[[VAL_19]] fastmath : f32 +! CHECK: %[[VAL_21:.*]] = arith.select %[[VAL_20]], %[[VAL_18]], %[[VAL_19]] : f32 +! CHECK: hlfir.assign %[[VAL_21]] to %[[VAL_14]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.parallel { @@ -90,24 +94,26 @@ ! CHECK: %[[VAL_32:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_33:.*]] = arith.constant 100 : i32 ! CHECK: %[[VAL_34:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@min_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) for (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { -! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref -! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 -! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref -! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 -! CHECK: fir.if %[[VAL_43]] { -! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref -! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 -! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref -! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref -! CHECK: } else { -! CHECK: } -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@min_f32 %[[VAL_4]]#0 -> %[[VAL_35:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_36:.*]]) : i32 = (%[[VAL_32]]) to (%[[VAL_33]]) inclusive step (%[[VAL_34]]) { +! CHECK: %[[VAL_37:.*]]:2 = hlfir.declare %[[VAL_35]] {uniq_name = "_QFreduction_min_realEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_36]] to %[[VAL_31]]#1 : !fir.ref +! CHECK: %[[VAL_38:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.convert %[[VAL_38]] : (i32) -> i64 +! CHECK: %[[VAL_40:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_39]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_40]] : !fir.ref +! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_37]]#0 : !fir.ref +! CHECK: %[[VAL_43:.*]] = arith.cmpf ogt, %[[VAL_41]], %[[VAL_42]] fastmath : f32 +! CHECK: fir.if %[[VAL_43]] { +! CHECK: %[[VAL_44:.*]] = fir.load %[[VAL_31]]#0 : !fir.ref +! CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_44]] : (i32) -> i64 +! CHECK: %[[VAL_46:.*]] = hlfir.designate %[[VAL_5]]#0 (%[[VAL_45]]) : (!fir.box>, i64) -> !fir.ref +! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref +! CHECK: hlfir.assign %[[VAL_47]] to %[[VAL_37]]#0 : f32, !fir.ref +! CHECK: } else { +! CHECK: } +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-min2.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-min2.f90 index 0138a9578206150567b90ef64afb9f8c59eaf122..a4c99f190dd2e5904088e1bd684e757bf056cec0 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-min2.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-min2.f90 @@ -39,12 +39,14 @@ end program ! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 ! CHECK: %[[VAL_7:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@min_i32 %[[VAL_3]]#0 -> %[[VAL_9:.*]] : !fir.ref) for (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]]#1 : !fir.ref -! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_9]] {uniq_name = "_QFEr"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref -! CHECK: hlfir.assign %[[VAL_12]] to %[[VAL_11]]#0 : i32, !fir.ref -! CHECK: omp.yield -! CHECK: } +! CHECK: omp.wsloop reduction(@min_i32 %[[VAL_3]]#0 -> %[[VAL_9:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { +! CHECK: %[[VAL_11:.*]]:2 = hlfir.declare %[[VAL_9]] {uniq_name = "_QFEr"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]]#1 : !fir.ref +! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]]#0 : !fir.ref +! CHECK: hlfir.assign %[[VAL_12]] to %[[VAL_11]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90 index a2829948d472a82a72a1d01d544016e82c98e57b..7c538cdd470f8ba8c78ab8e829ff1f22f5e057c4 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-mul-byref.f90 @@ -85,14 +85,16 @@ ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -121,15 +123,17 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 -! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_13]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 +! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_13]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -158,14 +162,16 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -194,15 +200,17 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_14]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_14]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -239,24 +247,26 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_byref_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_23]], %[[VAL_24]] : i32 -! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = arith.muli %[[VAL_26]], %[[VAL_27]] : i32 -! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_31:.*]] = arith.muli %[[VAL_29]], %[[VAL_30]] : i32 -! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_byref_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_23]], %[[VAL_24]] : i32 +! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref +! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = arith.muli %[[VAL_26]], %[[VAL_27]] : i32 +! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_31:.*]] = arith.muli %[[VAL_29]], %[[VAL_30]] : i32 +! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -297,27 +307,29 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_byref_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_byref_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.mulf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 -! CHECK: %[[VAL_30:.*]] = arith.mulf %[[VAL_27]], %[[VAL_29]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 -! CHECK: %[[VAL_34:.*]] = arith.mulf %[[VAL_31]], %[[VAL_33]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_byref_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_byref_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 +! CHECK: %[[VAL_26:.*]] = arith.mulf %[[VAL_23]], %[[VAL_25]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 +! CHECK: %[[VAL_30:.*]] = arith.mulf %[[VAL_27]], %[[VAL_29]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 +! CHECK: %[[VAL_34:.*]] = arith.mulf %[[VAL_31]], %[[VAL_33]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -362,32 +374,34 @@ end subroutine ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_17:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_18:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @multiply_reduction_byref_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @multiply_reduction_byref_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @multiply_reduction_byref_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) for (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { -! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref -! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = arith.muli %[[VAL_28]], %[[VAL_29]] : i32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 -! CHECK: %[[VAL_34:.*]] = arith.muli %[[VAL_31]], %[[VAL_33]] : i64 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref -! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 -! CHECK: %[[VAL_38:.*]] = arith.mulf %[[VAL_35]], %[[VAL_37]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 -! CHECK: %[[VAL_42:.*]] = arith.mulf %[[VAL_39]], %[[VAL_41]] fastmath : f64 -! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop byref reduction(@multiply_reduction_byref_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @multiply_reduction_byref_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @multiply_reduction_byref_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @multiply_reduction_byref_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { +! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = arith.muli %[[VAL_28]], %[[VAL_29]] : i32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 +! CHECK: %[[VAL_34:.*]] = arith.muli %[[VAL_31]], %[[VAL_33]] : i64 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref +! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 +! CHECK: %[[VAL_38:.*]] = arith.mulf %[[VAL_35]], %[[VAL_37]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 +! CHECK: %[[VAL_42:.*]] = arith.mulf %[[VAL_39]], %[[VAL_41]] fastmath : f64 +! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-mul.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-mul.f90 index 90d9aa5e839bde13001e2f388ea9728c67e935fb..08be4d84c1a62fdfaa6e3b386b07a27c153d73fc 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-mul.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-mul.f90 @@ -60,14 +60,16 @@ ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -96,15 +98,17 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 -! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_13]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = fir.convert %[[VAL_14]] : (i32) -> f32 +! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_13]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -133,14 +137,16 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 -! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_int_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_15:.*]] = arith.muli %[[VAL_13]], %[[VAL_14]] : i32 +! CHECK: hlfir.assign %[[VAL_15]] to %[[VAL_12]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -169,15 +175,17 @@ end subroutine ! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_8:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) for (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref -! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref -! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_14]], %[[VAL_15]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_10:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_11:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { +! CHECK: %[[VAL_12:.*]]:2 = hlfir.declare %[[VAL_10]] {uniq_name = "_QFsimple_real_reduction_switch_orderEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_11]] to %[[VAL_6]]#1 : !fir.ref +! CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_6]]#0 : !fir.ref +! CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i32) -> f32 +! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_16:.*]] = arith.mulf %[[VAL_14]], %[[VAL_15]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_16]] to %[[VAL_12]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -214,24 +222,26 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_23]], %[[VAL_24]] : i32 -! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = arith.muli %[[VAL_26]], %[[VAL_27]] : i32 -! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_31:.*]] = arith.muli %[[VAL_29]], %[[VAL_30]] : i32 -! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_i32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_int_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_int_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_int_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_23]], %[[VAL_24]] : i32 +! CHECK: hlfir.assign %[[VAL_25]] to %[[VAL_20]]#0 : i32, !fir.ref +! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = arith.muli %[[VAL_26]], %[[VAL_27]] : i32 +! CHECK: hlfir.assign %[[VAL_28]] to %[[VAL_21]]#0 : i32, !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_31:.*]] = arith.muli %[[VAL_29]], %[[VAL_30]] : i32 +! CHECK: hlfir.assign %[[VAL_31]] to %[[VAL_22]]#0 : i32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -272,27 +282,29 @@ end subroutine ! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_14:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_15:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) for (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { -! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref -! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.mulf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 -! CHECK: %[[VAL_30:.*]] = arith.mulf %[[VAL_27]], %[[VAL_29]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 -! CHECK: %[[VAL_34:.*]] = arith.mulf %[[VAL_31]], %[[VAL_33]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_f32 %[[VAL_3]]#0 -> %[[VAL_16:.*]] : !fir.ref, @multiply_reduction_f32 %[[VAL_5]]#0 -> %[[VAL_17:.*]] : !fir.ref, @multiply_reduction_f32 %[[VAL_7]]#0 -> %[[VAL_18:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_19:.*]]) : i32 = (%[[VAL_13]]) to (%[[VAL_14]]) inclusive step (%[[VAL_15]]) { +! CHECK: %[[VAL_20:.*]]:2 = hlfir.declare %[[VAL_16]] {uniq_name = "_QFmultiple_real_reductions_same_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_21:.*]]:2 = hlfir.declare %[[VAL_17]] {uniq_name = "_QFmultiple_real_reductions_same_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_22:.*]]:2 = hlfir.declare %[[VAL_18]] {uniq_name = "_QFmultiple_real_reductions_same_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_19]] to %[[VAL_12]]#1 : !fir.ref +! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_20]]#0 : !fir.ref +! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 +! CHECK: %[[VAL_26:.*]] = arith.mulf %[[VAL_23]], %[[VAL_25]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_26]] to %[[VAL_20]]#0 : f32, !fir.ref +! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_21]]#0 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i32) -> f32 +! CHECK: %[[VAL_30:.*]] = arith.mulf %[[VAL_27]], %[[VAL_29]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_21]]#0 : f32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_22]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_12]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> f32 +! CHECK: %[[VAL_34:.*]] = arith.mulf %[[VAL_31]], %[[VAL_33]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_22]]#0 : f32, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return @@ -337,32 +349,34 @@ end subroutine ! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 ! CHECK: %[[VAL_17:.*]] = arith.constant 10 : i32 ! CHECK: %[[VAL_18:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @multiply_reduction_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @multiply_reduction_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @multiply_reduction_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) for (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { -! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref -! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) -! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_30:.*]] = arith.muli %[[VAL_28]], %[[VAL_29]] : i32 -! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 -! CHECK: %[[VAL_34:.*]] = arith.muli %[[VAL_31]], %[[VAL_33]] : i64 -! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref -! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 -! CHECK: %[[VAL_38:.*]] = arith.mulf %[[VAL_35]], %[[VAL_37]] fastmath : f32 -! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref -! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref -! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 -! CHECK: %[[VAL_42:.*]] = arith.mulf %[[VAL_39]], %[[VAL_41]] fastmath : f64 -! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref -! CHECK: omp.yield +! CHECK: omp.wsloop reduction(@multiply_reduction_i32 %[[VAL_5]]#0 -> %[[VAL_19:.*]] : !fir.ref, @multiply_reduction_i64 %[[VAL_7]]#0 -> %[[VAL_20:.*]] : !fir.ref, @multiply_reduction_f32 %[[VAL_9]]#0 -> %[[VAL_21:.*]] : !fir.ref, @multiply_reduction_f64 %[[VAL_3]]#0 -> %[[VAL_22:.*]] : !fir.ref) { +! CHECK-NEXT: omp.loop_nest (%[[VAL_23:.*]]) : i32 = (%[[VAL_16]]) to (%[[VAL_17]]) inclusive step (%[[VAL_18]]) { +! CHECK: %[[VAL_24:.*]]:2 = hlfir.declare %[[VAL_19]] {uniq_name = "_QFmultiple_reductions_different_typeEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_25:.*]]:2 = hlfir.declare %[[VAL_20]] {uniq_name = "_QFmultiple_reductions_different_typeEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_26:.*]]:2 = hlfir.declare %[[VAL_21]] {uniq_name = "_QFmultiple_reductions_different_typeEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: %[[VAL_27:.*]]:2 = hlfir.declare %[[VAL_22]] {uniq_name = "_QFmultiple_reductions_different_typeEw"} : (!fir.ref) -> (!fir.ref, !fir.ref) +! CHECK: fir.store %[[VAL_23]] to %[[VAL_15]]#1 : !fir.ref +! CHECK: %[[VAL_28:.*]] = fir.load %[[VAL_24]]#0 : !fir.ref +! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_30:.*]] = arith.muli %[[VAL_28]], %[[VAL_29]] : i32 +! CHECK: hlfir.assign %[[VAL_30]] to %[[VAL_24]]#0 : i32, !fir.ref +! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_25]]#0 : !fir.ref +! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_32]] : (i32) -> i64 +! CHECK: %[[VAL_34:.*]] = arith.muli %[[VAL_31]], %[[VAL_33]] : i64 +! CHECK: hlfir.assign %[[VAL_34]] to %[[VAL_25]]#0 : i64, !fir.ref +! CHECK: %[[VAL_35:.*]] = fir.load %[[VAL_26]]#0 : !fir.ref +! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_36]] : (i32) -> f32 +! CHECK: %[[VAL_38:.*]] = arith.mulf %[[VAL_35]], %[[VAL_37]] fastmath : f32 +! CHECK: hlfir.assign %[[VAL_38]] to %[[VAL_26]]#0 : f32, !fir.ref +! CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_27]]#0 : !fir.ref +! CHECK: %[[VAL_40:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +! CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i32) -> f64 +! CHECK: %[[VAL_42:.*]] = arith.mulf %[[VAL_39]], %[[VAL_41]] fastmath : f64 +! CHECK: hlfir.assign %[[VAL_42]] to %[[VAL_27]]#0 : f64, !fir.ref +! CHECK: omp.yield +! CHECK: omp.terminator ! CHECK: omp.terminator ! CHECK: return diff --git a/flang/test/Lower/OpenMP/wsloop-reduction-multi.f90 b/flang/test/Lower/OpenMP/wsloop-reduction-multi.f90 index 9e9951c399c9205e65278f0e8d514f8c7ad360b7..429253efdc809047015a4a3d9579ff56c45faa0f 100644 --- a/flang/test/Lower/OpenMP/wsloop-reduction-multi.f90 +++ b/flang/test/Lower/OpenMP/wsloop-reduction-multi.f90 @@ -35,31 +35,34 @@ !CHECK: } !CHECK-LABEL: func.func @_QPmultiple_reduction -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_reductionEx"} -!CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]] {uniq_name = "_QFmultiple_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[Y_REF:.*]] = fir.alloca f32 {bindc_name = "y", uniq_name = "_QFmultiple_reductionEy"} -!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_REF]] {uniq_name = "_QFmultiple_reductionEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[Z_REF:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFmultiple_reductionEz"} -!CHECK: %[[Z_DECL:.*]]:2 = hlfir.declare %[[Z_REF]] {uniq_name = "_QFmultiple_reductionEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: omp.wsloop reduction( +!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_reductionEx"} +!CHECK: %[[X_DECL:.*]]:2 = hlfir.declare %[[X_REF]] {uniq_name = "_QFmultiple_reductionEx"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[Y_REF:.*]] = fir.alloca f32 {bindc_name = "y", uniq_name = "_QFmultiple_reductionEy"} +!CHECK: %[[Y_DECL:.*]]:2 = hlfir.declare %[[Y_REF]] {uniq_name = "_QFmultiple_reductionEy"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[Z_REF:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFmultiple_reductionEz"} +!CHECK: %[[Z_DECL:.*]]:2 = hlfir.declare %[[Z_REF]] {uniq_name = "_QFmultiple_reductionEz"} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: omp.wsloop reduction( !CHECK-SAME: @[[ADD_RED_I32_NAME]] %[[X_DECL]]#0 -> %[[PRV_X:.+]] : !fir.ref, !CHECK-SAME: @[[ADD_RED_F32_NAME]] %[[Y_DECL]]#0 -> %[[PRV_Y:.+]] : !fir.ref, -!CHECK-SAME: @[[MIN_RED_I32_NAME]] %[[Z_DECL]]#0 -> %[[PRV_Z:.+]] : !fir.ref) {{.*}}{ -!CHECK: %[[PRV_X_DECL:.+]]:2 = hlfir.declare %[[PRV_X]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[PRV_Y_DECL:.+]]:2 = hlfir.declare %[[PRV_Y]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[PRV_Z_DECL:.+]]:2 = hlfir.declare %[[PRV_Z]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) -!CHECK: %[[LPRV_X:.+]] = fir.load %[[PRV_X_DECL]]#0 : !fir.ref -!CHECK: %[[RES_X:.+]] = arith.addi %[[LPRV_X]], %{{.+}} : i32 -!CHECK: hlfir.assign %[[RES_X]] to %[[PRV_X_DECL]]#0 : i32, !fir.ref -!CHECK: %[[LPRV_Y:.+]] = fir.load %[[PRV_Y_DECL]]#0 : !fir.ref -!CHECK: %[[RES_Y:.+]] = arith.addf %[[LPRV_Y]], %{{.+}} : f32 -!CHECK: hlfir.assign %[[RES_Y]] to %[[PRV_Y_DECL]]#0 : f32, !fir.ref -!CHECK: %[[LPRV_Z:.+]] = fir.load %[[PRV_Z_DECL]]#0 : !fir.ref -!CHECK: %[[RES_Z:.+]] = arith.select %{{.+}}, %[[LPRV_Z]], %{{.+}} : i32 -!CHECK: hlfir.assign %[[RES_Z]] to %[[PRV_Z_DECL]]#0 : i32, !fir.ref -!CHECK: omp.yield -!CHECK: } -!CHECK: return +!CHECK-SAME: @[[MIN_RED_I32_NAME]] %[[Z_DECL]]#0 -> %[[PRV_Z:.+]] : !fir.ref) { +!CHECK-NEXT: omp.loop_nest {{.*}} { +!CHECK: %[[PRV_X_DECL:.+]]:2 = hlfir.declare %[[PRV_X]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[PRV_Y_DECL:.+]]:2 = hlfir.declare %[[PRV_Y]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[PRV_Z_DECL:.+]]:2 = hlfir.declare %[[PRV_Z]] {{.*}} : (!fir.ref) -> (!fir.ref, !fir.ref) +!CHECK: %[[LPRV_X:.+]] = fir.load %[[PRV_X_DECL]]#0 : !fir.ref +!CHECK: %[[RES_X:.+]] = arith.addi %[[LPRV_X]], %{{.+}} : i32 +!CHECK: hlfir.assign %[[RES_X]] to %[[PRV_X_DECL]]#0 : i32, !fir.ref +!CHECK: %[[LPRV_Y:.+]] = fir.load %[[PRV_Y_DECL]]#0 : !fir.ref +!CHECK: %[[RES_Y:.+]] = arith.addf %[[LPRV_Y]], %{{.+}} : f32 +!CHECK: hlfir.assign %[[RES_Y]] to %[[PRV_Y_DECL]]#0 : f32, !fir.ref +!CHECK: %[[LPRV_Z:.+]] = fir.load %[[PRV_Z_DECL]]#0 : !fir.ref +!CHECK: %[[RES_Z:.+]] = arith.select %{{.+}}, %[[LPRV_Z]], %{{.+}} : i32 +!CHECK: hlfir.assign %[[RES_Z]] to %[[PRV_Z_DECL]]#0 : i32, !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } +!CHECK: return subroutine multiple_reduction(v) implicit none integer, intent(in) :: v(:) diff --git a/flang/test/Lower/OpenMP/wsloop-simd.f90 b/flang/test/Lower/OpenMP/wsloop-simd.f90 index c3d5e3e0cda5935f571009bb6f08eceddd7646ad..1df67474d65e3b1899637264a837cbd7e285d20a 100644 --- a/flang/test/Lower/OpenMP/wsloop-simd.f90 +++ b/flang/test/Lower/OpenMP/wsloop-simd.f90 @@ -11,23 +11,26 @@ program wsloop_dynamic !CHECK: omp.parallel { !$OMP DO SCHEDULE(simd: runtime) -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(runtime, simd) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[STORE:.*]]#1 : !fir.ref +!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 +!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 +!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 +!CHECK: omp.wsloop schedule(runtime, simd) nowait { +!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { +!CHECK: fir.store %[[I]] to %[[STORE:.*]]#1 : !fir.ref do i=1, 9 print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[STORE]]#0 : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 +!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput +!CHECK: %[[LOAD:.*]] = fir.load %[[STORE]]#0 : !fir.ref +!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 +!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 end do -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$OMP END DO NOWAIT !$OMP END PARALLEL diff --git a/flang/test/Lower/OpenMP/wsloop-unstructured.f90 b/flang/test/Lower/OpenMP/wsloop-unstructured.f90 index 7fe63a1fe607c2effdbd716969e00aec56238da8..bd6a0bade8c7ee5c9a5c376385e99a40ed5326b8 100644 --- a/flang/test/Lower/OpenMP/wsloop-unstructured.f90 +++ b/flang/test/Lower/OpenMP/wsloop-unstructured.f90 @@ -29,29 +29,32 @@ end subroutine sub ! CHECK-SAME: %[[VAL_2:.*]]: !fir.ref> {fir.bindc_name = "x"}, ! CHECK-SAME: %[[VAL_3:.*]]: !fir.ref> {fir.bindc_name = "y"}) { ! [...] -! CHECK: omp.wsloop for (%[[VAL_53:.*]], %[[VAL_54:.*]]) : i32 = ({{.*}}) to ({{.*}}) inclusive step ({{.*}}) { +! CHECK: omp.wsloop { +! CHECK-NEXT: omp.loop_nest (%[[VAL_53:.*]], %[[VAL_54:.*]]) : i32 = ({{.*}}) to ({{.*}}) inclusive step ({{.*}}) { ! [...] -! CHECK: cf.br ^bb1 -! CHECK: ^bb1: -! CHECK: cf.br ^bb2 -! CHECK: ^bb2: +! CHECK: cf.br ^bb1 +! CHECK: ^bb1: +! CHECK: cf.br ^bb2 +! CHECK: ^bb2: ! [...] -! CHECK: cf.br ^bb3 -! CHECK: ^bb3: +! CHECK: cf.br ^bb3 +! CHECK: ^bb3: ! [...] -! CHECK: %[[VAL_63:.*]] = arith.cmpi sgt, %{{.*}}, %{{.*}} : i32 -! CHECK: cf.cond_br %[[VAL_63]], ^bb4, ^bb7 -! CHECK: ^bb4: +! CHECK: %[[VAL_63:.*]] = arith.cmpi sgt, %{{.*}}, %{{.*}} : i32 +! CHECK: cf.cond_br %[[VAL_63]], ^bb4, ^bb7 +! CHECK: ^bb4: ! [...] -! CHECK: %[[VAL_76:.*]] = arith.cmpf olt, %{{.*}}, %{{.*}} fastmath : f32 -! CHECK: cf.cond_br %[[VAL_76]], ^bb5, ^bb6 -! CHECK: ^bb5: -! CHECK: cf.br ^bb7 -! CHECK: ^bb6: +! CHECK: %[[VAL_76:.*]] = arith.cmpf olt, %{{.*}}, %{{.*}} fastmath : f32 +! CHECK: cf.cond_br %[[VAL_76]], ^bb5, ^bb6 +! CHECK: ^bb5: +! CHECK: cf.br ^bb7 +! CHECK: ^bb6: ! [...] -! CHECK: cf.br ^bb3 -! CHECK: ^bb7: -! CHECK: omp.yield +! CHECK: cf.br ^bb3 +! CHECK: ^bb7: +! CHECK: omp.yield +! CHECK: } +! CHECK: omp.terminator ! CHECK: } ! CHECK: omp.terminator ! CHECK: } diff --git a/flang/test/Lower/OpenMP/wsloop-variable.f90 b/flang/test/Lower/OpenMP/wsloop-variable.f90 index b3758f1fdc00ff703a0b24166902caba95ab119b..4d83b332880365878ca78ecd3a5e288091e8310b 100644 --- a/flang/test/Lower/OpenMP/wsloop-variable.f90 +++ b/flang/test/Lower/OpenMP/wsloop-variable.f90 @@ -14,26 +14,29 @@ program wsloop_variable integer(kind=16) :: i16, i16_lb real :: x -!CHECK: %[[TMP0:.*]] = arith.constant 1 : i32 -!CHECK: %[[TMP1:.*]] = arith.constant 100 : i32 -!CHECK: %[[TMP2:.*]] = fir.convert %[[TMP0]] : (i32) -> i64 -!CHECK: %[[TMP3:.*]] = fir.convert %{{.*}} : (i8) -> i64 -!CHECK: %[[TMP4:.*]] = fir.convert %{{.*}} : (i16) -> i64 -!CHECK: %[[TMP5:.*]] = fir.convert %{{.*}} : (i128) -> i64 -!CHECK: %[[TMP6:.*]] = fir.convert %[[TMP1]] : (i32) -> i64 -!CHECK: %[[TMP7:.*]] = fir.convert %{{.*}} : (i32) -> i64 -!CHECK: omp.wsloop for (%[[ARG0:.*]], %[[ARG1:.*]]) : i64 = (%[[TMP2]], %[[TMP5]]) to (%[[TMP3]], %[[TMP6]]) inclusive step (%[[TMP4]], %[[TMP7]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i64) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV0:.*]]#1 : !fir.ref -!CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]]#1 : !fir.ref -!CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]]#0 : !fir.ref -!CHECK: %[[LOAD_IV0_I64:.*]] = fir.convert %[[LOAD_IV0]] : (i16) -> i64 -!CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]]#0 : !fir.ref -!CHECK: %[[TMP10:.*]] = arith.addi %[[LOAD_IV0_I64]], %[[LOAD_IV1]] : i64 -!CHECK: %[[TMP11:.*]] = fir.convert %[[TMP10]] : (i64) -> f32 -!CHECK: hlfir.assign %[[TMP11]] to %{{.*}} : f32, !fir.ref -!CHECK: omp.yield -!CHECK: } +!CHECK: %[[TMP0:.*]] = arith.constant 1 : i32 +!CHECK: %[[TMP1:.*]] = arith.constant 100 : i32 +!CHECK: %[[TMP2:.*]] = fir.convert %[[TMP0]] : (i32) -> i64 +!CHECK: %[[TMP3:.*]] = fir.convert %{{.*}} : (i8) -> i64 +!CHECK: %[[TMP4:.*]] = fir.convert %{{.*}} : (i16) -> i64 +!CHECK: %[[TMP5:.*]] = fir.convert %{{.*}} : (i128) -> i64 +!CHECK: %[[TMP6:.*]] = fir.convert %[[TMP1]] : (i32) -> i64 +!CHECK: %[[TMP7:.*]] = fir.convert %{{.*}} : (i32) -> i64 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]], %[[ARG1:.*]]) : i64 = (%[[TMP2]], %[[TMP5]]) to (%[[TMP3]], %[[TMP6]]) inclusive step (%[[TMP4]], %[[TMP7]]) { +!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i64) -> i16 +!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV0:.*]]#1 : !fir.ref +!CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]]#1 : !fir.ref +!CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]]#0 : !fir.ref +!CHECK: %[[LOAD_IV0_I64:.*]] = fir.convert %[[LOAD_IV0]] : (i16) -> i64 +!CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]]#0 : !fir.ref +!CHECK: %[[TMP10:.*]] = arith.addi %[[LOAD_IV0_I64]], %[[LOAD_IV1]] : i64 +!CHECK: %[[TMP11:.*]] = fir.convert %[[TMP10]] : (i64) -> f32 +!CHECK: hlfir.assign %[[TMP11]] to %{{.*}} : f32, !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$omp do collapse(2) do i2 = 1, i1_ub, i2_s @@ -43,17 +46,20 @@ program wsloop_variable end do !$omp end do -!CHECK: %[[TMP12:.*]] = arith.constant 1 : i32 -!CHECK: %[[TMP13:.*]] = fir.convert %{{.*}} : (i8) -> i32 -!CHECK: %[[TMP14:.*]] = fir.convert %{{.*}} : (i64) -> i32 -!CHECK: omp.wsloop for (%[[ARG0:.*]]) : i32 = (%[[TMP12]]) to (%[[TMP13]]) inclusive step (%[[TMP14]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE3:.*]]#1 : !fir.ref -!CHECK: %[[LOAD3:.*]] = fir.load %[[STORE3]]#0 : !fir.ref -!CHECK: %[[TMP16:.*]] = fir.convert %[[LOAD3]] : (i16) -> f32 -!CHECK: hlfir.assign %[[TMP16]] to %{{.*}} : f32, !fir.ref -!CHECK: omp.yield -!CHECK: } +!CHECK: %[[TMP12:.*]] = arith.constant 1 : i32 +!CHECK: %[[TMP13:.*]] = fir.convert %{{.*}} : (i8) -> i32 +!CHECK: %[[TMP14:.*]] = fir.convert %{{.*}} : (i64) -> i32 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[TMP12]]) to (%[[TMP13]]) inclusive step (%[[TMP14]]) { +!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 +!CHECK: fir.store %[[ARG0_I16]] to %[[STORE3:.*]]#1 : !fir.ref +!CHECK: %[[LOAD3:.*]] = fir.load %[[STORE3]]#0 : !fir.ref +!CHECK: %[[TMP16:.*]] = fir.convert %[[LOAD3]] : (i16) -> f32 +!CHECK: hlfir.assign %[[TMP16]] to %{{.*}} : f32, !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$omp do do i2 = 1, i1_ub, i8_s @@ -61,17 +67,20 @@ program wsloop_variable end do !$omp end do -!CHECK: %[[TMP17:.*]] = fir.convert %{{.*}} : (i8) -> i64 -!CHECK: %[[TMP18:.*]] = fir.convert %{{.*}} : (i16) -> i64 -!CHECK: %[[TMP19:.*]] = fir.convert %{{.*}} : (i32) -> i64 -!CHECK: omp.wsloop for (%[[ARG1:.*]]) : i64 = (%[[TMP17]]) to (%[[TMP18]]) inclusive step (%[[TMP19]]) { -!CHECK: %[[ARG1_I128:.*]] = fir.convert %[[ARG1]] : (i64) -> i128 -!CHECK: fir.store %[[ARG1_I128]] to %[[STORE4:.*]]#1 : !fir.ref -!CHECK: %[[LOAD4:.*]] = fir.load %[[STORE4]]#0 : !fir.ref -!CHECK: %[[TMP21:.*]] = fir.convert %[[LOAD4]] : (i128) -> f32 -!CHECK: hlfir.assign %[[TMP21]] to %{{.*}} : f32, !fir.ref -!CHECK: omp.yield -!CHECK: } +!CHECK: %[[TMP17:.*]] = fir.convert %{{.*}} : (i8) -> i64 +!CHECK: %[[TMP18:.*]] = fir.convert %{{.*}} : (i16) -> i64 +!CHECK: %[[TMP19:.*]] = fir.convert %{{.*}} : (i32) -> i64 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i64 = (%[[TMP17]]) to (%[[TMP18]]) inclusive step (%[[TMP19]]) { +!CHECK: %[[ARG1_I128:.*]] = fir.convert %[[ARG1]] : (i64) -> i128 +!CHECK: fir.store %[[ARG1_I128]] to %[[STORE4:.*]]#1 : !fir.ref +!CHECK: %[[LOAD4:.*]] = fir.load %[[STORE4]]#0 : !fir.ref +!CHECK: %[[TMP21:.*]] = fir.convert %[[LOAD4]] : (i128) -> f32 +!CHECK: hlfir.assign %[[TMP21]] to %{{.*}} : f32, !fir.ref +!CHECK: omp.yield +!CHECK: } +!CHECK: omp.terminator +!CHECK: } !$omp do do i16 = i1_lb, i2_ub, i4_s @@ -118,32 +127,35 @@ subroutine wsloop_variable_sub !CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_13]]#0 : !fir.ref !CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_23]] : (i8) -> i32 !CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_24]] : (i16) -> i32 -!CHECK: omp.wsloop for (%[[VAL_27:.*]]) : i32 = (%[[VAL_22]]) to (%[[VAL_25]]) inclusive step (%[[VAL_26]]) { -!CHECK: %[[VAL_28:.*]] = fir.convert %[[VAL_27]] : (i32) -> i16 -!CHECK: fir.store %[[VAL_28]] to %[[VAL_3]]#1 : !fir.ref -!CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref -!CHECK: %[[VAL_30:.*]] = fir.convert %[[VAL_29]] : (i128) -> index -!CHECK: %[[VAL_31:.*]] = arith.constant 100 : i32 -!CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> index -!CHECK: %[[VAL_33:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref -!CHECK: %[[VAL_34:.*]] = fir.convert %[[VAL_33]] : (i32) -> index -!CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (index) -> i64 -!CHECK: %[[VAL_36:.*]]:2 = fir.do_loop %[[VAL_37:.*]] = %[[VAL_30]] to %[[VAL_32]] step %[[VAL_34]] iter_args(%[[VAL_38:.*]] = %[[VAL_35]]) -> (index, i64) { -!CHECK: fir.store %[[VAL_38]] to %[[VAL_17]]#1 : !fir.ref -!CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref -!CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i16) -> i64 -!CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref -!CHECK: %[[VAL_42:.*]] = arith.addi %[[VAL_40]], %[[VAL_41]] : i64 -!CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i64) -> f32 -!CHECK: hlfir.assign %[[VAL_43]] to %[[VAL_21]]#0 : f32, !fir.ref -!CHECK: %[[VAL_44:.*]] = arith.addi %[[VAL_37]], %[[VAL_34]] : index -!CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_34]] : (index) -> i64 -!CHECK: %[[VAL_46:.*]] = fir.load %[[VAL_17]]#1 : !fir.ref -!CHECK: %[[VAL_47:.*]] = arith.addi %[[VAL_46]], %[[VAL_45]] : i64 -!CHECK: fir.result %[[VAL_44]], %[[VAL_47]] : index, i64 +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[VAL_27:.*]]) : i32 = (%[[VAL_22]]) to (%[[VAL_25]]) inclusive step (%[[VAL_26]]) { +!CHECK: %[[VAL_28:.*]] = fir.convert %[[VAL_27]] : (i32) -> i16 +!CHECK: fir.store %[[VAL_28]] to %[[VAL_3]]#1 : !fir.ref +!CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_7]]#0 : !fir.ref +!CHECK: %[[VAL_30:.*]] = fir.convert %[[VAL_29]] : (i128) -> index +!CHECK: %[[VAL_31:.*]] = arith.constant 100 : i32 +!CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> index +!CHECK: %[[VAL_33:.*]] = fir.load %[[VAL_15]]#0 : !fir.ref +!CHECK: %[[VAL_34:.*]] = fir.convert %[[VAL_33]] : (i32) -> index +!CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_30]] : (index) -> i64 +!CHECK: %[[VAL_36:.*]]:2 = fir.do_loop %[[VAL_37:.*]] = %[[VAL_30]] to %[[VAL_32]] step %[[VAL_34]] iter_args(%[[VAL_38:.*]] = %[[VAL_35]]) -> (index, i64) { +!CHECK: fir.store %[[VAL_38]] to %[[VAL_17]]#1 : !fir.ref +!CHECK: %[[VAL_39:.*]] = fir.load %[[VAL_3]]#0 : !fir.ref +!CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i16) -> i64 +!CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]]#0 : !fir.ref +!CHECK: %[[VAL_42:.*]] = arith.addi %[[VAL_40]], %[[VAL_41]] : i64 +!CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i64) -> f32 +!CHECK: hlfir.assign %[[VAL_43]] to %[[VAL_21]]#0 : f32, !fir.ref +!CHECK: %[[VAL_44:.*]] = arith.addi %[[VAL_37]], %[[VAL_34]] : index +!CHECK: %[[VAL_45:.*]] = fir.convert %[[VAL_34]] : (index) -> i64 +!CHECK: %[[VAL_46:.*]] = fir.load %[[VAL_17]]#1 : !fir.ref +!CHECK: %[[VAL_47:.*]] = arith.addi %[[VAL_46]], %[[VAL_45]] : i64 +!CHECK: fir.result %[[VAL_44]], %[[VAL_47]] : index, i64 +!CHECK: } +!CHECK: fir.store %[[VAL_48:.*]]#1 to %[[VAL_17]]#1 : !fir.ref +!CHECK: omp.yield !CHECK: } -!CHECK: fir.store %[[VAL_48:.*]]#1 to %[[VAL_17]]#1 : !fir.ref -!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: } !$omp do @@ -160,16 +172,19 @@ subroutine wsloop_variable_sub !CHECK: %[[VAL_50:.*]] = arith.constant 1 : i32 !CHECK: %[[VAL_51:.*]] = arith.constant 10 : i32 !CHECK: %[[VAL_52:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop for (%[[VAL_53:.*]]) : i32 = (%[[VAL_50]]) to (%[[VAL_51]]) inclusive step (%[[VAL_52]]) { -!CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_53]] : (i32) -> i8 -!CHECK: fir.store %[[VAL_54]] to %[[VAL_1]]#1 : !fir.ref -!CHECK: %[[VAL_55:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref -!CHECK: %[[VAL_56:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref -!CHECK: %[[VAL_57:.*]] = arith.cmpi eq, %[[VAL_55]], %[[VAL_56]] : i8 -!CHECK: fir.if %[[VAL_57]] { -!CHECK: } else { +!CHECK: omp.wsloop { +!CHECK-NEXT: omp.loop_nest (%[[VAL_53:.*]]) : i32 = (%[[VAL_50]]) to (%[[VAL_51]]) inclusive step (%[[VAL_52]]) { +!CHECK: %[[VAL_54:.*]] = fir.convert %[[VAL_53]] : (i32) -> i8 +!CHECK: fir.store %[[VAL_54]] to %[[VAL_1]]#1 : !fir.ref +!CHECK: %[[VAL_55:.*]] = fir.load %[[VAL_1]]#0 : !fir.ref +!CHECK: %[[VAL_56:.*]] = fir.load %[[VAL_19]]#0 : !fir.ref +!CHECK: %[[VAL_57:.*]] = arith.cmpi eq, %[[VAL_55]], %[[VAL_56]] : i8 +!CHECK: fir.if %[[VAL_57]] { +!CHECK: } else { +!CHECK: } +!CHECK: omp.yield !CHECK: } -!CHECK: omp.yield +!CHECK: omp.terminator !CHECK: } j1 = 5 !$omp do diff --git a/flang/test/Lower/OpenMP/wsloop.f90 b/flang/test/Lower/OpenMP/wsloop.f90 index 4068f715c3e189a4b32734be6cf38c97a177e2b6..da90cb7241597fbfaff9ada6821508a4907000ce 100644 --- a/flang/test/Lower/OpenMP/wsloop.f90 +++ b/flang/test/Lower/OpenMP/wsloop.f90 @@ -7,22 +7,24 @@ subroutine simple_loop integer :: i ! CHECK: omp.parallel !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loopEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! CHECK: %[[IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loopEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_DECL:.*]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_DECL]]#0 : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_DECL:.*]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_DECL]]#0 : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine @@ -31,22 +33,24 @@ subroutine simple_loop_with_step integer :: i ! CHECK: omp.parallel !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loop_with_stepEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 2 : i32 - ! CHECK: omp.wsloop for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) - ! CHECK: fir.store %[[I]] to %[[IV_DECL]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_DECL]]#0 : !fir.ref + ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! CHECK: %[[IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFsimple_loop_with_stepEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 2 : i32 + ! CHECK: omp.wsloop { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { + ! CHECK: fir.store %[[I]] to %[[IV_DECL]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_DECL]]#0 : !fir.ref !$OMP DO do i=1, 9, 2 - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine @@ -55,21 +59,23 @@ subroutine loop_with_schedule_nowait integer :: i ! CHECK: omp.parallel !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFloop_with_schedule_nowaitEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop schedule(runtime) nowait for (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) + ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} + ! CHECK: %[[IV_DECL:.*]]:2 = hlfir.declare %[[ALLOCA_IV]] {uniq_name = "_QFloop_with_schedule_nowaitEi"} : (!fir.ref) -> (!fir.ref, !fir.ref) + ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 + ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 + ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 + ! CHECK: omp.wsloop schedule(runtime) nowait { + ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { !$OMP DO SCHEDULE(runtime) do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_DECL]]#1 : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_DECL]]#0 : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 + ! CHECK: fir.store %[[I]] to %[[IV_DECL]]#1 : !fir.ref + ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_DECL]]#0 : !fir.ref + ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 print*, i end do - ! CHECK: omp.yield + ! CHECK: omp.yield + ! CHECK: omp.terminator !$OMP END DO NOWAIT - ! CHECK: omp.terminator + ! CHECK: omp.terminator !$OMP END PARALLEL end subroutine diff --git a/flang/test/Parser/unrecognized-dir.f90 b/flang/test/Parser/unrecognized-dir.f90 index ba6fff7562e2d52c28edf1e578f4dc3b5d08934b..91fbfc9ee3c378eea82bc6304b22986ef25b1e69 100644 --- a/flang/test/Parser/unrecognized-dir.f90 +++ b/flang/test/Parser/unrecognized-dir.f90 @@ -1,4 +1,10 @@ ! RUN: %flang_fc1 -fsyntax-only %s 2>&1 | FileCheck %s -!CHECK: warning: Compiler directive was ignored +!CHECK: warning: Unrecognized compiler directive was ignored !DIR$ Not a recognized directive +program main + contains + !CHECK: warning: Compiler directive ignored here + !DIR$ not in a subprogram + subroutine s + end end diff --git a/flang/test/Preprocessing/backslash-contin1.F90 b/flang/test/Preprocessing/backslash-contin1.F90 new file mode 100644 index 0000000000000000000000000000000000000000..cf2ed36370dab3d3f9381b6d4c4f7daabee54a32 --- /dev/null +++ b/flang/test/Preprocessing/backslash-contin1.F90 @@ -0,0 +1,8 @@ +! RUN: %flang -E %s | FileCheck %s +print *, \ + "hello, \ +world" +end +!CHECK: print *, "hello, world" +!CHECK: end + diff --git a/flang/test/Semantics/arg-convert.f90 b/flang/test/Semantics/arg-convert.f90 new file mode 100644 index 0000000000000000000000000000000000000000..7951bedf49d0f892ede7d6bc64bd2ae14ed0e821 --- /dev/null +++ b/flang/test/Semantics/arg-convert.f90 @@ -0,0 +1,16 @@ +!RUN: %flang_fc1 -fdebug-unparse %s 2>&1 | FileCheck %s +!Ensure that argument conversion does not take place when the procedure +!interface is implicit at the point of call, even when the interface +!is known due because the procedure's definition is in the same source file. + +subroutine test +!CHECK: warning: If the procedure's interface were explicit, this reference would be in error +!CHECK: because: Actual argument type 'INTEGER(8)' is not compatible with dummy argument type 'INTEGER(4)' +!CHECK: CALL samesourcefile((1_8)) + call sameSourceFile((1_8)) +!CHECK: CALL somewhereelse((2_8)) + call somewhereElse((2_8)) +end + +subroutine sameSourceFile(n) +end diff --git a/flang/test/Semantics/declarations03.f90 b/flang/test/Semantics/declarations03.f90 index 3459b2287b2badd800380ff11c85429aafbe797e..65b07e7d5c656787de55846ccc2c794f09760e70 100644 --- a/flang/test/Semantics/declarations03.f90 +++ b/flang/test/Semantics/declarations03.f90 @@ -19,7 +19,7 @@ module m common /blk4/ w bind(c, name="cc") :: t2, /blk4/ - !ERROR: The entity 'blk5' has multiple BIND names + !ERROR: The entity 'blk5' has multiple BIND names ('dd' and 'ee') common /blk5/ i bind(c, name="dd") :: /blk5/ bind(c, name="ee") :: /blk5/ @@ -29,7 +29,7 @@ module m bind(c, name="ff") :: /blk6/ bind(c, name="ff") :: /blk7/ - !ERROR: The entity 's1' has multiple BIND names + !ERROR: The entity 's1' has multiple BIND names ('gg' and 'hh') integer :: s1 bind(c, name="gg") :: s1 !ERROR: BIND_C attribute was already specified on 's1' @@ -40,12 +40,12 @@ module m bind(c, name="ii") :: s2 bind(c, name="ii") :: s3 - !ERROR: The entity 's4' has multiple BIND names + !ERROR: The entity 's4' has multiple BIND names ('ss1' and 'jj') integer, bind(c, name="ss1") :: s4 !ERROR: BIND_C attribute was already specified on 's4' bind(c, name="jj") :: s4 - !ERROR: The entity 's5' has multiple BIND names + !ERROR: The entity 's5' has multiple BIND names ('kk' and 'ss2') bind(c, name="kk") :: s5 !ERROR: BIND_C attribute was already specified on 's5' integer, bind(c, name="ss2") :: s5 @@ -72,3 +72,8 @@ module b !ERROR: Two entities have the same global name 'int' integer, bind(c, name="int") :: i end module + +module c + bind(c, name = "AAA") a + integer aaa ! ensure no bogus error about multiple binding names +end module diff --git a/flang/test/Transforms/omp-reduction-cfg-conversion.fir b/flang/test/Transforms/omp-reduction-cfg-conversion.fir index 3103c4456d72efdd7d94ab78f4598f7c562b1bc2..707e665132afbbd000c5aa263bebe32426f42b09 100644 --- a/flang/test/Transforms/omp-reduction-cfg-conversion.fir +++ b/flang/test/Transforms/omp-reduction-cfg-conversion.fir @@ -1,4 +1,4 @@ -// RUN: fir-opt --cfg-conversion-on-reduce-opt %s | FileCheck %s +// RUN: fir-opt --cfg-conversion %s | FileCheck %s omp.declare_reduction @add_reduction_i_32_box_3_byref : !fir.ref>> init { ^bb0(%arg0: !fir.ref>>): diff --git a/flang/unittests/Runtime/NumericalFormatTest.cpp b/flang/unittests/Runtime/NumericalFormatTest.cpp index dee4dda4a22869cfd0508f5e197143cc993c6179..2a9f8f8d1dc4f31556ea2609b337904256b9be9f 100644 --- a/flang/unittests/Runtime/NumericalFormatTest.cpp +++ b/flang/unittests/Runtime/NumericalFormatTest.cpp @@ -958,3 +958,20 @@ TEST(IOApiTests, EditDoubleInputValues) { << "', want " << want << ", got " << u.raw; } } + +// regression test for confusing digit minimization +TEST(IOApiTests, ConfusingMinimization) { + char buffer[8]{}; + auto cookie{IONAME(BeginInternalListOutput)(buffer, sizeof buffer)}; + StaticDescriptor<0> staticDescriptor; + Descriptor &desc{staticDescriptor.descriptor()}; + std::uint16_t x{0x7bff}; // HUGE(0._2) + desc.Establish(TypeCode{CFI_type_half_float}, sizeof x, &x, 0, nullptr); + desc.Check(); + EXPECT_TRUE(IONAME(OutputDescriptor)(cookie, desc)); + auto status{IONAME(EndIoStatement)(cookie)}; + EXPECT_EQ(status, 0); + std::string got{std::string{buffer, sizeof buffer}}; + EXPECT_TRUE(CompareFormattedStrings(" 65504. ", got)) + << "expected ' 65504. ', got '" << got << '\''; // not 65500.! +} diff --git a/flang/unittests/Runtime/RuntimeCrashTest.cpp b/flang/unittests/Runtime/RuntimeCrashTest.cpp index 0f25cc0ee8035baa358baadc11f6ce37f1fb9983..a649051fdca0c5b2ec55af5fe02c3228eddaa7c1 100644 --- a/flang/unittests/Runtime/RuntimeCrashTest.cpp +++ b/flang/unittests/Runtime/RuntimeCrashTest.cpp @@ -53,16 +53,6 @@ TEST(TestTerminator, CheckFailedTest) { //------------------------------------------------------------------------------ struct TestIOCrash : CrashHandlerFixture {}; -TEST(TestIOCrash, FormatDescriptorWriteMismatchTest) { - static constexpr int bufferSize{4}; - static char buffer[bufferSize]; - static const char *format{"(A4)"}; - auto *cookie{IONAME(BeginInternalFormattedOutput)( - buffer, bufferSize, format, std::strlen(format))}; - ASSERT_DEATH(IONAME(OutputLogical)(cookie, true), - "Data edit descriptor 'A' may not be used with a LOGICAL data item"); -} - TEST(TestIOCrash, InvalidFormatCharacterTest) { static constexpr int bufferSize{1}; static char buffer[bufferSize]; diff --git a/libc/config/linux/syscall_numbers.h.inc b/libc/config/linux/syscall_numbers.h.inc index 9f910c5f9042a812d18a800010db19f96055f550..4a19d9a08875e81de3c1fa70160e3bfc49103a84 100644 --- a/libc/config/linux/syscall_numbers.h.inc +++ b/libc/config/linux/syscall_numbers.h.inc @@ -338,6 +338,10 @@ #define SYS_fchmodat __NR_fchmodat #endif +#ifdef __NR_fchmodat2 +#define SYS_fchmodat2 __NR_fchmodat2 +#endif + #ifdef __NR_fchown #define SYS_fchown __NR_fchown #endif diff --git a/libc/include/assert.h.def b/libc/include/assert.h.def index e006133a76542a6d9e31d4cd564ff998967ca7d4..15077e53e2ca4826d9abe8d69ec08928393e15a4 100644 --- a/libc/include/assert.h.def +++ b/libc/include/assert.h.def @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "__llvm-libc-common.h" +#include "llvm-libc-macros/assert-macros.h" // This file may be usefully included multiple times to change assert()'s // definition based on NDEBUG. diff --git a/libc/include/llvm-libc-macros/CMakeLists.txt b/libc/include/llvm-libc-macros/CMakeLists.txt index 382cb8ee417e1632b522aa403f2f72bd516d2a42..68ba110aec80f1ac1331a8ee0e6c49eaf8d3faaa 100644 --- a/libc/include/llvm-libc-macros/CMakeLists.txt +++ b/libc/include/llvm-libc-macros/CMakeLists.txt @@ -31,6 +31,12 @@ if(EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) add_subdirectory(${CMAKE_CURRENT_SOURCE_DIR}/${LIBC_TARGET_OS}) endif() +add_macro_header( + assert_macros + HDR + assert-macros.h +) + add_macro_header( generic_error_number_macros HDR diff --git a/libc/include/llvm-libc-macros/assert-macros.h b/libc/include/llvm-libc-macros/assert-macros.h new file mode 100644 index 0000000000000000000000000000000000000000..44e14543d8562e6c52fe80bf95d9ca6a4c259a38 --- /dev/null +++ b/libc/include/llvm-libc-macros/assert-macros.h @@ -0,0 +1,14 @@ +//===-- Definition of macros to be used with assert functions -------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef __LLVM_LIBC_MACROS_ASSERT_MACROS_H +#define __LLVM_LIBC_MACROS_ASSERT_MACROS_H + +#define __STDC_VERSION_ASSERT_H__ 202311L + +#endif // __LLVM_LIBC_MACROS_ASSERT_MACROS_H diff --git a/libc/src/sys/stat/linux/chmod.cpp b/libc/src/sys/stat/linux/chmod.cpp index 085b91691d89f47992235e3585b6a990c3550d8d..25e5e69af71a082581cffcc075521cc02e1b6885 100644 --- a/libc/src/sys/stat/linux/chmod.cpp +++ b/libc/src/sys/stat/linux/chmod.cpp @@ -21,11 +21,14 @@ namespace LIBC_NAMESPACE { LLVM_LIBC_FUNCTION(int, chmod, (const char *path, mode_t mode)) { #ifdef SYS_chmod int ret = LIBC_NAMESPACE::syscall_impl(SYS_chmod, path, mode); +#elif defined(SYS_fchmodat2) + int ret = LIBC_NAMESPACE::syscall_impl(SYS_fchmodat2, AT_FDCWD, path, + mode, 0, AT_SYMLINK_NOFOLLOW); #elif defined(SYS_fchmodat) int ret = - LIBC_NAMESPACE::syscall_impl(SYS_fchmodat, AT_FDCWD, path, mode); + LIBC_NAMESPACE::syscall_impl(SYS_fchmodat, AT_FDCWD, path, mode, 0); #else -#error "chmod and fchmodat syscalls not available." +#error "chmod, fchmodat and fchmodat2 syscalls not available." #endif if (ret < 0) { diff --git a/libc/test/UnitTest/CMakeLists.txt b/libc/test/UnitTest/CMakeLists.txt index 9113eca388e05b12b95d166fa8db0a2af45af67b..302af3044ca3d66e9d24cc231b331ff67b8244e1 100644 --- a/libc/test/UnitTest/CMakeLists.txt +++ b/libc/test/UnitTest/CMakeLists.txt @@ -111,8 +111,10 @@ add_header_library( add_unittest_framework_library( LibcFPTestHelpers SRCS + FEnvSafeTest.cpp RoundingModeUtils.cpp HDRS + FEnvSafeTest.h FPMatcher.h RoundingModeUtils.h DEPENDS diff --git a/libc/test/UnitTest/FEnvSafeTest.cpp b/libc/test/UnitTest/FEnvSafeTest.cpp new file mode 100644 index 0000000000000000000000000000000000000000..905aa928937387d91e69b4a108efe39f1251e25f --- /dev/null +++ b/libc/test/UnitTest/FEnvSafeTest.cpp @@ -0,0 +1,84 @@ +//===-- FEnvSafeTest.cpp ---------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// + +#include "FEnvSafeTest.h" + +#include "src/__support/FPUtil/FEnvImpl.h" +#include "src/__support/macros/properties/architectures.h" + +namespace LIBC_NAMESPACE::testing { + +void FEnvSafeTest::PreserveFEnv::check() { + fenv_t after; + test.get_fenv(after); + test.expect_fenv_eq(before, after); +} + +void FEnvSafeTest::TearDown() { + if (!should_be_unchanged) { + restore_fenv(); + } +} + +void FEnvSafeTest::get_fenv(fenv_t &fenv) { + ASSERT_EQ(LIBC_NAMESPACE::fputil::get_env(&fenv), 0); +} + +void FEnvSafeTest::set_fenv(const fenv_t &fenv) { + ASSERT_EQ(LIBC_NAMESPACE::fputil::set_env(&fenv), 0); +} + +void FEnvSafeTest::expect_fenv_eq(const fenv_t &before_fenv, + const fenv_t &after_fenv) { +#if defined(LIBC_TARGET_ARCH_IS_AARCH64) + using FPState = LIBC_NAMESPACE::fputil::FEnv::FPState; + const FPState &before_state = reinterpret_cast(before_fenv); + const FPState &after_state = reinterpret_cast(after_fenv); + + EXPECT_EQ(before_state.ControlWord, after_state.ControlWord); + EXPECT_EQ(before_state.StatusWord, after_state.StatusWord); + +#elif defined(LIBC_TARGET_ARCH_IS_X86) && !defined(__APPLE__) + using LIBC_NAMESPACE::fputil::internal::FPState; + const FPState &before_state = reinterpret_cast(before_fenv); + const FPState &after_state = reinterpret_cast(after_fenv); + +#if defined(_WIN32) + EXPECT_EQ(before_state.control_word, after_state.control_word); + EXPECT_EQ(before_state.status_word, after_state.status_word); +#elif defined(__APPLE__) + EXPECT_EQ(before_state.control_word, after_state.control_word); + EXPECT_EQ(before_state.status_word, after_state.status_word); + EXPECT_EQ(before_state.mxcsr, after_state.mxcsr); +#else + EXPECT_EQ(before_state.x87_status.control_word, + after_state.x87_status.control_word); + EXPECT_EQ(before_state.x87_status.status_word, + after_state.x87_status.status_word); + EXPECT_EQ(before_state.mxcsr, after_state.mxcsr); +#endif + +#elif defined(LIBC_TARGET_ARCH_IS_ARM) && defined(__ARM_FP) + using LIBC_NAMESPACE::fputil::FEnv; + const FEnv &before_state = reinterpret_cast(before_fenv); + const FEnv &after_state = reinterpret_cast(after_fenv); + + EXPECT_EQ(before_state.fpscr, after_state.fpscr); + +#elif defined(LIBC_TARGET_ARCH_IS_ANY_RISCV) + const uint32_t &before_fcsr = reinterpret_cast(before_fenv); + const uint32_t &after_fcsr = reinterpret_cast(after_fenv); + EXPECT_EQ(before_fcsr, after_fcsr); + +#else + // No arch-specific `fenv_t` support, so nothing to compare. + +#endif +} + +} // namespace LIBC_NAMESPACE::testing diff --git a/libc/test/UnitTest/FEnvSafeTest.h b/libc/test/UnitTest/FEnvSafeTest.h new file mode 100644 index 0000000000000000000000000000000000000000..d5a8bb7ee667ce9434b12ad37aef8ccec246440a --- /dev/null +++ b/libc/test/UnitTest/FEnvSafeTest.h @@ -0,0 +1,101 @@ +//===-- FEnvSafeTest.h -----------------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_TEST_UNITTEST_FPENVSAFE_H +#define LLVM_LIBC_TEST_UNITTEST_FPENVSAFE_H + +#include "hdr/types/fenv_t.h" +#include "src/__support/CPP/utility.h" +#include "test/UnitTest/Test.h" + +namespace LIBC_NAMESPACE::testing { + +// This provides a test fixture (or base class for other test fixtures) that +// asserts that each test does not leave the FPU state represented by `fenv_t` +// (aka `FPState`) perturbed from its initial state. +class FEnvSafeTest : public Test { +public: + void TearDown() override; + +protected: + // This is an RAII type where `PreserveFEnv preserve{this};` will sample the + // `fenv_t` state and restore it when `preserve` goes out of scope. + class PreserveFEnv { + fenv_t before; + FEnvSafeTest &test; + + public: + explicit PreserveFEnv(FEnvSafeTest *self) : test{*self} { + test.get_fenv(before); + } + + // Cause test expectation failures if the current state doesn't match what + // was captured in the constructor. + void check(); + + // Restore the state captured in the constructor. + void restore() { test.set_fenv(before); } + + ~PreserveFEnv() { restore(); } + }; + + // This is an RAII type where `CheckFEnv check{this};` will sample the + // `fenv_t` state and require it be the same when `check` goes out of scope. + struct CheckFEnv : public PreserveFEnv { + using PreserveFEnv::PreserveFEnv; + + ~CheckFEnv() { check(); } + }; + + // This calls callable() and returns its value, but has EXPECT_* failures if + // the `fenv_t` state is not preserved by the call. + template decltype(auto) check_fenv_preserved(T &&callable) { + CheckFEnv check{this}; + return cpp::forward(callable)(); + } + + // This calls callable() and returns its value, but saves and restores the + // `fenv_t` state around the call. + template + auto with_fenv_preserved(T &&callable) + -> decltype(cpp::forward(callable)()) { + PreserveFEnv preserve{this}; + return cpp::forward(callable)(); + } + + // A test can call these to indicate it will or won't change `fenv_t` state. + void will_change_fenv() { should_be_unchanged = false; } + void will_not_change_fenv() { should_be_unchanged = true; } + + // This explicitly resets back to the "before" state captured in SetUp(). + // TearDown() always does this, but should_be_unchanged controls whether + // it also causes test failures if a test fails to restore it. + void restore_fenv() { check.restore(); } + +private: + void get_fenv(fenv_t &fenv); + void set_fenv(const fenv_t &fenv); + void expect_fenv_eq(const fenv_t &before_fenv, const fenv_t &after_fenv); + + CheckFEnv check{this}; + + // TODO: Many tests fail if this is true. It needs to be figured out whether + // the state should be preserved by each library function under test, and + // separately whether each test itself should preserve the state. It + // probably isn't important that tests be explicitly written to preserve the + // state, as the fixture can (and does) reset it--the next test can rely on + // getting "normal" ambient state initially. For library functions that + // should preserve the state, that should be checked after each call, not + // just after the whole test. So they can use check_fenv_preserved or + // with_fenv_preserved as appropriate. + bool should_be_unchanged = false; +}; + +} // namespace LIBC_NAMESPACE::testing + +#endif // LLVM_LIBC_TEST_UNITTEST_FPENVSAFE_H diff --git a/libc/test/include/CMakeLists.txt b/libc/test/include/CMakeLists.txt index 8d8dff53169f6ac21cbcdf8ebdd88634d2f19538..03c31855e352bac30aae93fccc416e8c683883d4 100644 --- a/libc/test/include/CMakeLists.txt +++ b/libc/test/include/CMakeLists.txt @@ -1,5 +1,15 @@ add_custom_target(libc_include_tests) +add_libc_test( + assert_test + SUITE + libc_include_tests + SRCS + assert_test.cpp + DEPENDS + libc.include.llvm-libc-macros.assert_macros +) + add_libc_test( sys_queue_test SUITE diff --git a/libc/test/include/assert_test.cpp b/libc/test/include/assert_test.cpp new file mode 100644 index 0000000000000000000000000000000000000000..78709bbcdd5941effe2d66f02f0b7134c759e035 --- /dev/null +++ b/libc/test/include/assert_test.cpp @@ -0,0 +1,15 @@ +//===-- Unittests for assert ----------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDSList-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "include/llvm-libc-macros/assert-macros.h" +#include "test/UnitTest/Test.h" + +TEST(LlvmLibcAssertTest, VersionMacro) { + // 7.2p3 an integer constant expression with a value equivalent to 202311L. + EXPECT_EQ(__STDC_VERSION_ASSERT_H__, 202311L); +} diff --git a/libc/test/src/fenv/CMakeLists.txt b/libc/test/src/fenv/CMakeLists.txt index f277b65e2d42be01f971aad967b9c2f8b3e58022..b776f9a0706e861cd16e55ab60e27eeceac19e76 100644 --- a/libc/test/src/fenv/CMakeLists.txt +++ b/libc/test/src/fenv/CMakeLists.txt @@ -9,6 +9,8 @@ add_libc_unittest( DEPENDS libc.src.fenv.fegetround libc.src.fenv.fesetround + LINK_LIBRARIES + LibcFPTestHelpers ) add_libc_unittest( @@ -23,6 +25,8 @@ add_libc_unittest( libc.src.fenv.fesetexcept libc.src.fenv.fetestexcept libc.src.__support.FPUtil.fenv_impl + LINK_LIBRARIES + LibcFPTestHelpers ) add_libc_unittest( @@ -37,6 +41,8 @@ add_libc_unittest( libc.src.fenv.fesetenv libc.src.fenv.fesetround libc.src.__support.FPUtil.fenv_impl + LINK_LIBRARIES + LibcFPTestHelpers ) add_libc_unittest( @@ -50,6 +56,8 @@ add_libc_unittest( libc.src.fenv.fesetexceptflag libc.src.fenv.fetestexceptflag libc.src.__support.FPUtil.fenv_impl + LINK_LIBRARIES + LibcFPTestHelpers ) add_libc_unittest( @@ -62,6 +70,8 @@ add_libc_unittest( libc.include.signal libc.src.fenv.feupdateenv libc.src.__support.FPUtil.fenv_impl + LINK_LIBRARIES + LibcFPTestHelpers ) add_libc_unittest( @@ -73,6 +83,8 @@ add_libc_unittest( DEPENDS libc.src.fenv.feclearexcept libc.src.__support.FPUtil.fenv_impl + LINK_LIBRARIES + LibcFPTestHelpers ) add_libc_unittest( @@ -85,6 +97,8 @@ add_libc_unittest( libc.src.fenv.fedisableexcept libc.src.fenv.feenableexcept libc.src.fenv.fegetexcept + LINK_LIBRARIES + LibcFPTestHelpers ) if (NOT (LLVM_USE_SANITIZER OR (${LIBC_TARGET_OS} STREQUAL "windows") @@ -109,6 +123,7 @@ if (NOT (LLVM_USE_SANITIZER OR (${LIBC_TARGET_OS} STREQUAL "windows") libc.src.__support.FPUtil.fenv_impl LINK_LIBRARIES LibcFPExceptionHelpers + LibcFPTestHelpers ) add_fp_unittest( @@ -124,5 +139,6 @@ if (NOT (LLVM_USE_SANITIZER OR (${LIBC_TARGET_OS} STREQUAL "windows") libc.src.__support.FPUtil.fenv_impl LINK_LIBRARIES LibcFPExceptionHelpers + LibcFPTestHelpers ) endif() diff --git a/libc/test/src/fenv/enabled_exceptions_test.cpp b/libc/test/src/fenv/enabled_exceptions_test.cpp index 53440b704ca761d93e66520aae305608e154ae73..7d26eab5695bce1dbfb6a49685fe761cd5b5b357 100644 --- a/libc/test/src/fenv/enabled_exceptions_test.cpp +++ b/libc/test/src/fenv/enabled_exceptions_test.cpp @@ -12,15 +12,20 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/macros/properties/architectures.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPExceptMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/fenv_macros.h" #include +#include "excepts.h" + +using LlvmLibcExceptionStatusTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + // This test enables an exception and verifies that raising that exception // triggers SIGFPE. -TEST(LlvmLibcExceptionStatusTest, RaiseAndCrash) { +TEST_F(LlvmLibcExceptionStatusTest, RaiseAndCrash) { #if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV) // Few Arm HW implementations do not trap exceptions. We skip this test @@ -41,16 +46,7 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndCrash) { // that exception handler, so such a testing can be done after we have // longjmp implemented. - int excepts[] = {FE_DIVBYZERO, FE_INVALID, FE_INEXACT, FE_OVERFLOW, - FE_UNDERFLOW}; - - // We '|' the individual exception flags instead of using FE_ALL_EXCEPT - // as it can include non-standard extensions. Note that we should be able - // to compile this file with headers from other libcs as well. - constexpr int ALL_EXCEPTS = - FE_DIVBYZERO | FE_INVALID | FE_INEXACT | FE_OVERFLOW | FE_UNDERFLOW; - - for (int e : excepts) { + for (int e : EXCEPTS) { LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT); LIBC_NAMESPACE::fputil::enable_except(e); ASSERT_EQ(LIBC_NAMESPACE::feclearexcept(FE_ALL_EXCEPT), 0); diff --git a/libc/test/src/fenv/exception_flags_test.cpp b/libc/test/src/fenv/exception_flags_test.cpp index 9d2be6426a6d0b734a84f946fce9845610f49f6d..2f4332df861fec6d9f183aec9e6067bb9b7bffdd 100644 --- a/libc/test/src/fenv/exception_flags_test.cpp +++ b/libc/test/src/fenv/exception_flags_test.cpp @@ -12,18 +12,20 @@ #include "src/fenv/fetestexceptflag.h" #include "src/__support/FPUtil/FEnvImpl.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" -TEST(LlvmLibcFenvTest, GetSetTestExceptFlag) { +#include "excepts.h" + +using LlvmLibcFEnvTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcFEnvTest, GetSetTestExceptFlag) { // We will disable all exceptions to prevent invocation of the exception // handler. LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT); LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); - int excepts[] = {FE_DIVBYZERO, FE_INVALID, FE_INEXACT, FE_OVERFLOW, - FE_UNDERFLOW}; - - for (int e : excepts) { + for (int e : EXCEPTS) { // The overall idea is to raise an except and save the exception flags. // Next, clear the flags and then set the saved exception flags. This // should set the flag corresponding to the previously raised exception. diff --git a/libc/test/src/fenv/exception_status_test.cpp b/libc/test/src/fenv/exception_status_test.cpp index a7000020b1a3c804a6eeee6215bb89316d533e6f..fdf9421457866e6d729e1f944f75ec2a1dd1c45f 100644 --- a/libc/test/src/fenv/exception_status_test.cpp +++ b/libc/test/src/fenv/exception_status_test.cpp @@ -13,24 +13,23 @@ #include "src/fenv/fetestexcept.h" #include "src/__support/FPUtil/FEnvImpl.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" #include "hdr/fenv_macros.h" -TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { +#include "excepts.h" + +using LlvmLibcExceptionStatusTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcExceptionStatusTest, RaiseAndTest) { // This test raises a set of exceptions and checks that the exception // status flags are updated. The intention is really not to invoke the // exception handler. Hence, we will disable all exceptions at the // beginning. LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT); - int excepts[] = {FE_DIVBYZERO, FE_INVALID, FE_INEXACT, FE_OVERFLOW, - FE_UNDERFLOW}; - - constexpr int ALL_EXCEPTS = - FE_DIVBYZERO | FE_INVALID | FE_INEXACT | FE_OVERFLOW | FE_UNDERFLOW; - - for (int e : excepts) { + for (int e : EXCEPTS) { int r = LIBC_NAMESPACE::feraiseexcept(e); ASSERT_EQ(r, 0); int s = LIBC_NAMESPACE::fetestexcept(e); @@ -47,8 +46,8 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { ASSERT_EQ(s, e); } - for (int e1 : excepts) { - for (int e2 : excepts) { + for (int e1 : EXCEPTS) { + for (int e2 : EXCEPTS) { int e = e1 | e2; int r = LIBC_NAMESPACE::feraiseexcept(e); ASSERT_EQ(r, 0); @@ -67,9 +66,9 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { } } - for (int e1 : excepts) { - for (int e2 : excepts) { - for (int e3 : excepts) { + for (int e1 : EXCEPTS) { + for (int e2 : EXCEPTS) { + for (int e3 : EXCEPTS) { int e = e1 | e2 | e3; int r = LIBC_NAMESPACE::feraiseexcept(e); ASSERT_EQ(r, 0); @@ -89,10 +88,10 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { } } - for (int e1 : excepts) { - for (int e2 : excepts) { - for (int e3 : excepts) { - for (int e4 : excepts) { + for (int e1 : EXCEPTS) { + for (int e2 : EXCEPTS) { + for (int e3 : EXCEPTS) { + for (int e4 : EXCEPTS) { int e = e1 | e2 | e3 | e4; int r = LIBC_NAMESPACE::feraiseexcept(e); ASSERT_EQ(r, 0); @@ -113,11 +112,11 @@ TEST(LlvmLibcExceptionStatusTest, RaiseAndTest) { } } - for (int e1 : excepts) { - for (int e2 : excepts) { - for (int e3 : excepts) { - for (int e4 : excepts) { - for (int e5 : excepts) { + for (int e1 : EXCEPTS) { + for (int e2 : EXCEPTS) { + for (int e3 : EXCEPTS) { + for (int e4 : EXCEPTS) { + for (int e5 : EXCEPTS) { int e = e1 | e2 | e3 | e4 | e5; int r = LIBC_NAMESPACE::feraiseexcept(e); ASSERT_EQ(r, 0); diff --git a/libc/test/src/fenv/excepts.h b/libc/test/src/fenv/excepts.h new file mode 100644 index 0000000000000000000000000000000000000000..e9517d319a9b79a22febc36c0febb358ab98d783 --- /dev/null +++ b/libc/test/src/fenv/excepts.h @@ -0,0 +1,24 @@ +//===-- List of all FE_* constants for tests -----------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===---------------------------------------------------------------------===// + +#ifndef LLVM_LIBC_TEST_SRC_FENV_EXCEPTS_H +#define LLVM_LIBC_TEST_SRC_FENV_EXCEPTS_H + +#include "hdr/fenv_macros.h" + +constexpr int EXCEPTS[] = { + FE_DIVBYZERO, FE_INVALID, FE_INEXACT, FE_OVERFLOW, FE_UNDERFLOW, +}; + +// We '|' the individual exception flags instead of using FE_ALL_EXCEPT +// as it can include non-standard extensions. Note that we should be able +// to compile this file with headers from other libcs as well. +constexpr int ALL_EXCEPTS = + FE_DIVBYZERO | FE_INVALID | FE_INEXACT | FE_OVERFLOW | FE_UNDERFLOW; + +#endif // LLVM_LIBC_TEST_SRC_FENV_EXCEPTS_H diff --git a/libc/test/src/fenv/feclearexcept_test.cpp b/libc/test/src/fenv/feclearexcept_test.cpp index bb42d9070358efb2af27891f9127fd435f88e28f..52adda46adf2f09545875bad5017f77e62cc837c 100644 --- a/libc/test/src/fenv/feclearexcept_test.cpp +++ b/libc/test/src/fenv/feclearexcept_test.cpp @@ -9,27 +9,30 @@ #include "src/fenv/feclearexcept.h" #include "src/__support/FPUtil/FEnvImpl.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" #include "hdr/fenv_macros.h" #include -TEST(LlvmLibcFEnvTest, ClearTest) { - uint16_t excepts[] = {FE_DIVBYZERO, FE_INVALID, FE_INEXACT, FE_OVERFLOW, - FE_UNDERFLOW}; +#include "excepts.h" + +using LlvmLibcFEnvTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcFEnvTest, ClearTest) { LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT); LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); - for (uint16_t e : excepts) + for (int e : EXCEPTS) ASSERT_EQ(LIBC_NAMESPACE::fputil::test_except(e), 0); LIBC_NAMESPACE::fputil::raise_except(FE_ALL_EXCEPT); - for (uint16_t e1 : excepts) { - for (uint16_t e2 : excepts) { - for (uint16_t e3 : excepts) { - for (uint16_t e4 : excepts) { - for (uint16_t e5 : excepts) { + for (int e1 : EXCEPTS) { + for (int e2 : EXCEPTS) { + for (int e3 : EXCEPTS) { + for (int e4 : EXCEPTS) { + for (int e5 : EXCEPTS) { // We clear one exception and test to verify that it was cleared. LIBC_NAMESPACE::feclearexcept(e1 | e2 | e3 | e4 | e5); ASSERT_EQ( diff --git a/libc/test/src/fenv/feenableexcept_test.cpp b/libc/test/src/fenv/feenableexcept_test.cpp index aeb4f955fd69b6d11d1723857f6c4026d1e5ba8e..232e2a1c8316c698189333ea2e26e742a7d91cac 100644 --- a/libc/test/src/fenv/feenableexcept_test.cpp +++ b/libc/test/src/fenv/feenableexcept_test.cpp @@ -11,11 +11,16 @@ #include "src/fenv/feenableexcept.h" #include "src/fenv/fegetexcept.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" #include "hdr/fenv_macros.h" -TEST(LlvmLibcFEnvTest, EnableTest) { +#include "excepts.h" + +using LlvmLibcFEnvTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcFEnvTest, EnableTest) { #if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV) // Few Arm HW implementations do not trap exceptions. We skip this test diff --git a/libc/test/src/fenv/feholdexcept_test.cpp b/libc/test/src/fenv/feholdexcept_test.cpp index 0689d89ab233a3291f257c7d5c20ee2d28fabf62..f3e05d4a5b6c0d163704eccecc5f6386fbb2d307 100644 --- a/libc/test/src/fenv/feholdexcept_test.cpp +++ b/libc/test/src/fenv/feholdexcept_test.cpp @@ -11,10 +11,15 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/macros/properties/architectures.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPExceptMatcher.h" #include "test/UnitTest/Test.h" -TEST(LlvmLibcFEnvTest, RaiseAndCrash) { +#include "excepts.h" + +using LlvmLibcFEnvTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcFEnvTest, RaiseAndCrash) { #if defined(LIBC_TARGET_ARCH_IS_ANY_ARM) || \ defined(LIBC_TARGET_ARCH_IS_ANY_RISCV) // Few Arm HW implementations do not trap exceptions. We skip this test diff --git a/libc/test/src/fenv/feupdateenv_test.cpp b/libc/test/src/fenv/feupdateenv_test.cpp index 251b8566aac3d627c8684682aff4dab3056b4651..d2ffc0ef8e84d3bf1d5cdfe27daac684933539b7 100644 --- a/libc/test/src/fenv/feupdateenv_test.cpp +++ b/libc/test/src/fenv/feupdateenv_test.cpp @@ -10,11 +10,12 @@ #include "src/fenv/feupdateenv.h" #include "src/__support/FPUtil/FEnvImpl.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" -#include +using LlvmLibcFEnvTest = LIBC_NAMESPACE::testing::FEnvSafeTest; -TEST(LlvmLibcFEnvTest, UpdateEnvTest) { +TEST_F(LlvmLibcFEnvTest, UpdateEnvTest) { LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT); LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); diff --git a/libc/test/src/fenv/getenv_and_setenv_test.cpp b/libc/test/src/fenv/getenv_and_setenv_test.cpp index f767e8ab9b2fb8b846804fb5fbe2d3566acde595..7257e75cb421ae54c7b4f539faff106452950735 100644 --- a/libc/test/src/fenv/getenv_and_setenv_test.cpp +++ b/libc/test/src/fenv/getenv_and_setenv_test.cpp @@ -13,17 +13,19 @@ #include "src/fenv/fesetround.h" #include "src/__support/FPUtil/FEnvImpl.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" -TEST(LlvmLibcFenvTest, GetEnvAndSetEnv) { +#include "excepts.h" + +using LlvmLibcFEnvTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcFEnvTest, GetEnvAndSetEnv) { // We will disable all exceptions to prevent invocation of the exception // handler. LIBC_NAMESPACE::fputil::disable_except(FE_ALL_EXCEPT); - int excepts[] = {FE_DIVBYZERO, FE_INVALID, FE_INEXACT, FE_OVERFLOW, - FE_UNDERFLOW}; - - for (int e : excepts) { + for (int e : EXCEPTS) { LIBC_NAMESPACE::fputil::clear_except(FE_ALL_EXCEPT); // Save the cleared environment. @@ -71,7 +73,7 @@ TEST(LlvmLibcFenvTest, Set_FE_DFL_ENV) { } #ifdef _WIN32 -TEST(LlvmLibcFenvTest, Windows_Set_Get_Test) { +TEST_F(LlvmLibcFEnvTest, Windows_Set_Get_Test) { // If a valid fenv_t is written, then reading it back out should be identical. fenv_t setEnv = {0x7e00053e, 0x0f00000f}; fenv_t getEnv; diff --git a/libc/test/src/fenv/rounding_mode_test.cpp b/libc/test/src/fenv/rounding_mode_test.cpp index ec2e27ecc818b2c731a50d00b2e5e6cfe0adafdd..f242ed9aaffe5bc03b339689a1c7d91e877850e0 100644 --- a/libc/test/src/fenv/rounding_mode_test.cpp +++ b/libc/test/src/fenv/rounding_mode_test.cpp @@ -9,15 +9,18 @@ #include "src/fenv/fegetround.h" #include "src/fenv/fesetround.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" #include "hdr/fenv_macros.h" -TEST(LlvmLibcRoundingModeTest, SetAndGet) { +using LlvmLibcRoundingModeTest = LIBC_NAMESPACE::testing::FEnvSafeTest; + +TEST_F(LlvmLibcRoundingModeTest, SetAndGet) { struct ResetDefaultRoundingMode { - int original; + int original = LIBC_NAMESPACE::fegetround(); ~ResetDefaultRoundingMode() { LIBC_NAMESPACE::fesetround(original); } - } reset{LIBC_NAMESPACE::fegetround()}; + } reset; int s = LIBC_NAMESPACE::fesetround(FE_TONEAREST); EXPECT_EQ(s, 0); diff --git a/libc/test/src/math/CeilTest.h b/libc/test/src/math/CeilTest.h index da3f3c0e8f5abd0b4276891cd0a3ae7714edc815..b4c3752cc5c4bac2a6d336f6c52e8b9c72d89a47 100644 --- a/libc/test/src/math/CeilTest.h +++ b/libc/test/src/math/CeilTest.h @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -14,7 +15,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class CeilTest : public LIBC_NAMESPACE::testing::Test { +template +class CeilTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/CopySignTest.h b/libc/test/src/math/CopySignTest.h index 052ff0333438e9fcd816945bdd3e25389ee49ae4..c66f91477480b81dd78f136151565acf01b97c80 100644 --- a/libc/test/src/math/CopySignTest.h +++ b/libc/test/src/math/CopySignTest.h @@ -6,6 +6,7 @@ // //===----------------------------------------------------------------------===// +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -15,7 +16,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; template -class CopySignTest : public LIBC_NAMESPACE::testing::Test { +class CopySignTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/FAbsTest.h b/libc/test/src/math/FAbsTest.h index 23ad8a26c481c25aba0e2e17c1f5be8f5d1fd6f1..92b589beeb675fcde4718f4b466b1c0b87010cbf 100644 --- a/libc/test/src/math/FAbsTest.h +++ b/libc/test/src/math/FAbsTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_FABSTEST_H #define LLVM_LIBC_TEST_SRC_MATH_FABSTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -17,7 +18,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class FAbsTest : public LIBC_NAMESPACE::testing::Test { +template +class FAbsTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/FDimTest.h b/libc/test/src/math/FDimTest.h index 44aba9caf6463ef8eaa62e3921a09371a00c3a3e..fefcefe5052a9206bde71e312a33a1377a9ce8dd 100644 --- a/libc/test/src/math/FDimTest.h +++ b/libc/test/src/math/FDimTest.h @@ -9,11 +9,12 @@ #include "hdr/math_macros.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FDimTestTemplate : public LIBC_NAMESPACE::testing::Test { +class FDimTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using FuncPtr = T (*)(T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/FMaxTest.h b/libc/test/src/math/FMaxTest.h index e9857f332e6518384ee8cb3e9eb8caadbc26de89..405642c6b968419e0561aaef7cf9a07f570f23f6 100644 --- a/libc/test/src/math/FMaxTest.h +++ b/libc/test/src/math/FMaxTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_FMAXTEST_H #define LLVM_LIBC_TEST_SRC_MATH_FMAXTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -17,7 +18,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class FMaxTest : public LIBC_NAMESPACE::testing::Test { +template +class FMaxTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/FMinTest.h b/libc/test/src/math/FMinTest.h index c6b9f4439b79b7dbf5f3f43d0b33d53c08eaa426..eae0008ddfe392daf6ce6cc04c27491bbbb5a379 100644 --- a/libc/test/src/math/FMinTest.h +++ b/libc/test/src/math/FMinTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_FMINTEST_H #define LLVM_LIBC_TEST_SRC_MATH_FMINTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -17,7 +18,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class FMinTest : public LIBC_NAMESPACE::testing::Test { +template +class FMinTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/FModTest.h b/libc/test/src/math/FModTest.h index bc909987a161b807406791739f3fe211ba649875..f1015d6497fcd671f2b53e6ada5ce553402d2b95 100644 --- a/libc/test/src/math/FModTest.h +++ b/libc/test/src/math/FModTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/NearestIntegerOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -24,7 +25,8 @@ #define TEST_REGULAR(x, y, expected) TEST_SPECIAL(x, y, expected, false, 0) -template class FmodTest : public LIBC_NAMESPACE::testing::Test { +template +class FmodTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/FloorTest.h b/libc/test/src/math/FloorTest.h index 679dc26e124806e8b1c6ae60bef61f2a80c3dfe8..9103a5b05eb5adf23ca21a33cf16ba63ffff252d 100644 --- a/libc/test/src/math/FloorTest.h +++ b/libc/test/src/math/FloorTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_FLOORTEST_H #define LLVM_LIBC_TEST_SRC_MATH_FLOORTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -17,7 +18,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class FloorTest : public LIBC_NAMESPACE::testing::Test { +template +class FloorTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/FmaTest.h b/libc/test/src/math/FmaTest.h index 76bd221fcb1f2fff3bda3c0248fe129a4b601bd2..5a40f694ebd107b1bd0a1fe46f82a495b81b7811 100644 --- a/libc/test/src/math/FmaTest.h +++ b/libc/test/src/math/FmaTest.h @@ -12,6 +12,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/stdlib/rand.h" #include "src/stdlib/srand.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -19,7 +20,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; template -class FmaTestTemplate : public LIBC_NAMESPACE::testing::Test { +class FmaTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { private: using Func = T (*)(T, T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/FrexpTest.h b/libc/test/src/math/FrexpTest.h index 5f993f604999d892a47752b30aa1ad927a5206bd..3ba64afa3c62059d7d8689f7ddd97b4930e700f5 100644 --- a/libc/test/src/math/FrexpTest.h +++ b/libc/test/src/math/FrexpTest.h @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/BasicOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -15,7 +16,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class FrexpTest : public LIBC_NAMESPACE::testing::Test { +template +class FrexpTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/HypotTest.h b/libc/test/src/math/HypotTest.h index 0c15f02fe3719318ff22062f5f6697a4bfb4e328..58b53383182459217f60fe291f2b10b576424d10 100644 --- a/libc/test/src/math/HypotTest.h +++ b/libc/test/src/math/HypotTest.h @@ -10,6 +10,7 @@ #define LLVM_LIBC_TEST_SRC_MATH_HYPOTTEST_H #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -19,7 +20,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; template -class HypotTestTemplate : public LIBC_NAMESPACE::testing::Test { +class HypotTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { private: using Func = T (*)(T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/ILogbTest.h b/libc/test/src/math/ILogbTest.h index 3d1f047a4806132aadf9c31cfe71e7cf0c7d2fc0..c2d5a1326e0ed2bc5485df0036ba982a3e87328b 100644 --- a/libc/test/src/math/ILogbTest.h +++ b/libc/test/src/math/ILogbTest.h @@ -13,9 +13,10 @@ #include "src/__support/CPP/limits.h" // INT_MAX #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" -class LlvmLibcILogbTest : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcILogbTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: template struct ILogbFunc { typedef int (*Func)(T); diff --git a/libc/test/src/math/LdExpTest.h b/libc/test/src/math/LdExpTest.h index 2a406feed52fc1b6c3cee7400a03a4350c3c2506..34466a526d60fb09c8868683965d0e7f4d07ad3a 100644 --- a/libc/test/src/math/LdExpTest.h +++ b/libc/test/src/math/LdExpTest.h @@ -12,6 +12,7 @@ #include "src/__support/CPP/limits.h" // INT_MAX #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/NormalFloat.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -19,7 +20,7 @@ #include template -class LdExpTestTemplate : public LIBC_NAMESPACE::testing::Test { +class LdExpTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using NormalFloat = LIBC_NAMESPACE::fputil::NormalFloat; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/LogbTest.h b/libc/test/src/math/LogbTest.h index f066d5f9de02b12a3fd56a81dbaba5947c23d6a0..d6042e3c200c7693bda67d83926fbef9462952a1 100644 --- a/libc/test/src/math/LogbTest.h +++ b/libc/test/src/math/LogbTest.h @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/ManipulationFunctions.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -15,7 +16,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class LogbTest : public LIBC_NAMESPACE::testing::Test { +template +class LogbTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/ModfTest.h b/libc/test/src/math/ModfTest.h index 49b0328753b3bc2321b5bde0d1458b3f692cd126..d6c6f27a5edf6651ea94dd954e820fa7baebeb7e 100644 --- a/libc/test/src/math/ModfTest.h +++ b/libc/test/src/math/ModfTest.h @@ -8,6 +8,7 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/NearestIntegerOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -16,7 +17,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class ModfTest : public LIBC_NAMESPACE::testing::Test { +template +class ModfTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/NextAfterTest.h b/libc/test/src/math/NextAfterTest.h index a7248dd7042d464451df3c2b3cfd944d91fcef8a..b3b03f763992a03d1f0c59139993cf7b0fafb46e 100644 --- a/libc/test/src/math/NextAfterTest.h +++ b/libc/test/src/math/NextAfterTest.h @@ -14,11 +14,12 @@ #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class NextAfterTestTemplate : public LIBC_NAMESPACE::testing::Test { +class NextAfterTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/RIntTest.h b/libc/test/src/math/RIntTest.h index c706ff18f186e5d75e7f33da68160fd4454209ff..007b50427ba34a1ebad099676986c0b212874f56 100644 --- a/libc/test/src/math/RIntTest.h +++ b/libc/test/src/math/RIntTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -25,7 +26,7 @@ static constexpr int ROUNDING_MODES[4] = {FE_UPWARD, FE_DOWNWARD, FE_TOWARDZERO, FE_TONEAREST}; template -class RIntTestTemplate : public LIBC_NAMESPACE::testing::Test { +class RIntTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: typedef T (*RIntFunc)(T); diff --git a/libc/test/src/math/RemQuoTest.h b/libc/test/src/math/RemQuoTest.h index 677772dd9fccfdc59ad10ef49554809afe19dca6..c39f2394555eac62fe6a12c65c0593b3f4f60b12 100644 --- a/libc/test/src/math/RemQuoTest.h +++ b/libc/test/src/math/RemQuoTest.h @@ -12,6 +12,7 @@ #include "hdr/math_macros.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -19,7 +20,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; template -class RemQuoTestTemplate : public LIBC_NAMESPACE::testing::Test { +class RemQuoTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/RoundEvenTest.h b/libc/test/src/math/RoundEvenTest.h index 68b8b9ae1d964bdb93b12805a394cc031e6fd81e..d70555d34765918dcf060cbdc347f289a78129cb 100644 --- a/libc/test/src/math/RoundEvenTest.h +++ b/libc/test/src/math/RoundEvenTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_ROUNDEVENTEST_H #define LLVM_LIBC_TEST_SRC_MATH_ROUNDEVENTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -18,7 +19,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; template -class RoundEvenTest : public LIBC_NAMESPACE::testing::Test { +class RoundEvenTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/RoundTest.h b/libc/test/src/math/RoundTest.h index eecf95982729be8fd3cd8c94a5a9d00bc263a24b..2a31df305ac384a85cc5201bf462e7236e52503f 100644 --- a/libc/test/src/math/RoundTest.h +++ b/libc/test/src/math/RoundTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_ROUNDTEST_H #define LLVM_LIBC_TEST_SRC_MATH_ROUNDTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -17,7 +18,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class RoundTest : public LIBC_NAMESPACE::testing::Test { +template +class RoundTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/RoundToIntegerTest.h b/libc/test/src/math/RoundToIntegerTest.h index 7c93451235f29697f29e06a7e9467c4ddef0e1a7..0f052ba42a46d74b6e4b10d40edb695a3b73b748 100644 --- a/libc/test/src/math/RoundToIntegerTest.h +++ b/libc/test/src/math/RoundToIntegerTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -24,7 +25,8 @@ static constexpr int ROUNDING_MODES[4] = {FE_UPWARD, FE_DOWNWARD, FE_TOWARDZERO, FE_TONEAREST}; template -class RoundToIntegerTestTemplate : public LIBC_NAMESPACE::testing::Test { +class RoundToIntegerTestTemplate + : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: typedef I (*RoundToIntegerFunc)(F); @@ -81,6 +83,8 @@ private: public: void SetUp() override { + LIBC_NAMESPACE::testing::FEnvSafeTest::SetUp(); + if (math_errhandling & MATH_ERREXCEPT) { // We will disable all exceptions so that the test will not // crash with SIGFPE. We can still use fetestexcept to check diff --git a/libc/test/src/math/SqrtTest.h b/libc/test/src/math/SqrtTest.h index 799b7862a37260743a8079196a217d5942e8ab3a..1c422e201bb234ee398f20a377602867043a5dfe 100644 --- a/libc/test/src/math/SqrtTest.h +++ b/libc/test/src/math/SqrtTest.h @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "src/__support/CPP/bit.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -15,7 +16,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class SqrtTest : public LIBC_NAMESPACE::testing::Test { +template +class SqrtTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/TruncTest.h b/libc/test/src/math/TruncTest.h index 57c953fad8742f00f8bc05e787fa45f9e33d9b0c..bc5b76131291bba7ada50bba1aa2186c02546efa 100644 --- a/libc/test/src/math/TruncTest.h +++ b/libc/test/src/math/TruncTest.h @@ -9,6 +9,7 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_TRUNCTEST_H #define LLVM_LIBC_TEST_SRC_MATH_TRUNCTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -17,7 +18,8 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; -template class TruncTest : public LIBC_NAMESPACE::testing::Test { +template +class TruncTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/exhaustive/fmod_generic_impl_test.cpp b/libc/test/src/math/exhaustive/fmod_generic_impl_test.cpp index c7aec5b7bc21b4b18431ef16db9be267652d2d66..b064b7e37f428d611360ea1c81dc03193f6bba25 100644 --- a/libc/test/src/math/exhaustive/fmod_generic_impl_test.cpp +++ b/libc/test/src/math/exhaustive/fmod_generic_impl_test.cpp @@ -9,6 +9,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" // ldexp #include "src/__support/FPUtil/generic/FMod.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "utils/MPFRWrapper/MPFRUtils.h" @@ -18,7 +19,7 @@ namespace mpfr = LIBC_NAMESPACE::testing::mpfr; template -class LlvmLibcFModTest : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcFModTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using U = typename FPBits::StorageType; diff --git a/libc/test/src/math/smoke/CanonicalizeTest.h b/libc/test/src/math/smoke/CanonicalizeTest.h index ab45e0eb8e94d3f3044acd4a0056bcbcc0c3cdde..7e2456f84705c982041f9bf09b638468974e395f 100644 --- a/libc/test/src/math/smoke/CanonicalizeTest.h +++ b/libc/test/src/math/smoke/CanonicalizeTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/__support/integer_literals.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -26,7 +27,7 @@ using LIBC_NAMESPACE::operator""_u128; template -class CanonicalizeTest : public LIBC_NAMESPACE::testing::Test { +class CanonicalizeTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/CeilTest.h b/libc/test/src/math/smoke/CeilTest.h index 70e441a849cb4fc0c651b3192eee6faf4bed921b..5e108c0e0feea1794baf6805bb30bcede937457a 100644 --- a/libc/test/src/math/smoke/CeilTest.h +++ b/libc/test/src/math/smoke/CeilTest.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_CEILTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_CEILTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class CeilTest : public LIBC_NAMESPACE::testing::Test { +template +class CeilTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/CopySignTest.h b/libc/test/src/math/smoke/CopySignTest.h index fa9da91920f8dedda3c37bbe7a7ee82a8e07c273..1810560bf1bb8fe80c717b13f50f2e178729243d 100644 --- a/libc/test/src/math/smoke/CopySignTest.h +++ b/libc/test/src/math/smoke/CopySignTest.h @@ -9,13 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_COPYSIGNTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_COPYSIGNTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" template -class CopySignTest : public LIBC_NAMESPACE::testing::Test { +class CopySignTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FAbsTest.h b/libc/test/src/math/smoke/FAbsTest.h index 0c8ca95ba0f7bc26bbb2e58770b6aa931bf520b3..048023b414299f80f817f4a63d7061cc29454422 100644 --- a/libc/test/src/math/smoke/FAbsTest.h +++ b/libc/test/src/math/smoke/FAbsTest.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_FABSTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FABSTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class FAbsTest : public LIBC_NAMESPACE::testing::Test { +template +class FAbsTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FDimTest.h b/libc/test/src/math/smoke/FDimTest.h index e557b40d90efa1e43a10041442d3e1a456ec28fa..cff88f29a8efa80a21ea2f0a9cd178761e6223b1 100644 --- a/libc/test/src/math/smoke/FDimTest.h +++ b/libc/test/src/math/smoke/FDimTest.h @@ -8,11 +8,12 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FDimTestTemplate : public LIBC_NAMESPACE::testing::Test { +class FDimTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using FuncPtr = T (*)(T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/smoke/FMaxTest.h b/libc/test/src/math/smoke/FMaxTest.h index b8781a85d10f4f397a5ec0ae3bbdacd9ba9cd1b3..df8e35e0bd16204ddce2270c01cb42a4cb823d91 100644 --- a/libc/test/src/math/smoke/FMaxTest.h +++ b/libc/test/src/math/smoke/FMaxTest.h @@ -9,10 +9,12 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMAXTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMAXTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -template class FMaxTest : public LIBC_NAMESPACE::testing::Test { +template +class FMaxTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMaximumMagNumTest.h b/libc/test/src/math/smoke/FMaximumMagNumTest.h index 715dd4ed913f838b817b71583e3af4665759c71c..aafb6d2b0d5eacab9bc70f161d1fbd4880b268d0 100644 --- a/libc/test/src/math/smoke/FMaximumMagNumTest.h +++ b/libc/test/src/math/smoke/FMaximumMagNumTest.h @@ -11,11 +11,12 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMaximumMagNumTest : public LIBC_NAMESPACE::testing::Test { +class FMaximumMagNumTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMaximumMagTest.h b/libc/test/src/math/smoke/FMaximumMagTest.h index 38276e0fe2fdb0486daf62ffa15885c704df2d89..7bb79a69be580f6b40d394ce43917dedf5ec27a5 100644 --- a/libc/test/src/math/smoke/FMaximumMagTest.h +++ b/libc/test/src/math/smoke/FMaximumMagTest.h @@ -10,11 +10,12 @@ #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMAXIMUM_MAGTEST_H #include "src/__support/FPUtil/BasicOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMaximumMagTest : public LIBC_NAMESPACE::testing::Test { +class FMaximumMagTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMaximumNumTest.h b/libc/test/src/math/smoke/FMaximumNumTest.h index 57096f6b614a2c8e093f7fb69a8c934b5bdb79a2..da0ea2c247a9ee6feb5cb6cf1b963ce36217d237 100644 --- a/libc/test/src/math/smoke/FMaximumNumTest.h +++ b/libc/test/src/math/smoke/FMaximumNumTest.h @@ -10,11 +10,12 @@ #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMAXIMUMNUMTEST_H #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMaximumNumTest : public LIBC_NAMESPACE::testing::Test { +class FMaximumNumTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMaximumTest.h b/libc/test/src/math/smoke/FMaximumTest.h index 4db8bb93baaeefbbd60f4a843af3ce5970641fef..1bd15163ed75291b1aeeacf7a149bda4d172a978 100644 --- a/libc/test/src/math/smoke/FMaximumTest.h +++ b/libc/test/src/math/smoke/FMaximumTest.h @@ -9,11 +9,12 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMAXIMUMTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMAXIMUMTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMaximumTest : public LIBC_NAMESPACE::testing::Test { +class FMaximumTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMinTest.h b/libc/test/src/math/smoke/FMinTest.h index b1ffe38829f438e6f07d1e85e1bdd24d3c5f64d2..f71b558cd3da2027b66e9e6d68a7e3d61ba5139e 100644 --- a/libc/test/src/math/smoke/FMinTest.h +++ b/libc/test/src/math/smoke/FMinTest.h @@ -9,10 +9,12 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMINTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMINTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -template class FMinTest : public LIBC_NAMESPACE::testing::Test { +template +class FMinTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMinimumMagNumTest.h b/libc/test/src/math/smoke/FMinimumMagNumTest.h index dec8b70740ca593eebc27e6c6cb75b49afbe018f..e4b8fd9e335311e34475b2e8500eaf656c888d22 100644 --- a/libc/test/src/math/smoke/FMinimumMagNumTest.h +++ b/libc/test/src/math/smoke/FMinimumMagNumTest.h @@ -11,11 +11,12 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMinimumMagNumTest : public LIBC_NAMESPACE::testing::Test { +class FMinimumMagNumTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMinimumMagTest.h b/libc/test/src/math/smoke/FMinimumMagTest.h index b11092e5379ba0abe80a579af68a82adfc8ae4f5..3e16622fe3fa41dc07254bb6a12e299195dd61dd 100644 --- a/libc/test/src/math/smoke/FMinimumMagTest.h +++ b/libc/test/src/math/smoke/FMinimumMagTest.h @@ -10,11 +10,12 @@ #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMINIMUM_MAGTEST_H #include "src/__support/FPUtil/BasicOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMinimumMagTest : public LIBC_NAMESPACE::testing::Test { +class FMinimumMagTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMinimumNumTest.h b/libc/test/src/math/smoke/FMinimumNumTest.h index 7fcc291b4c00cd8ee9a046650dbf09e1c7f7a5c0..6186ea0df17cce1614c0ec1f52e5817ca88ac1a3 100644 --- a/libc/test/src/math/smoke/FMinimumNumTest.h +++ b/libc/test/src/math/smoke/FMinimumNumTest.h @@ -10,11 +10,12 @@ #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMINIMUMNUMTEST_H #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMinimumNumTest : public LIBC_NAMESPACE::testing::Test { +class FMinimumNumTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FMinimumTest.h b/libc/test/src/math/smoke/FMinimumTest.h index bc04a6d99356547ee0a2e44f6d6348c72ddb4c10..a267f6c78321452883de91c5986a587381412b47 100644 --- a/libc/test/src/math/smoke/FMinimumTest.h +++ b/libc/test/src/math/smoke/FMinimumTest.h @@ -9,11 +9,12 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMINIMUMTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FMINIMUMTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FMinimumTest : public LIBC_NAMESPACE::testing::Test { +class FMinimumTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FModTest.h b/libc/test/src/math/smoke/FModTest.h index bc909987a161b807406791739f3fe211ba649875..f1015d6497fcd671f2b53e6ada5ce553402d2b95 100644 --- a/libc/test/src/math/smoke/FModTest.h +++ b/libc/test/src/math/smoke/FModTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/NearestIntegerOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -24,7 +25,8 @@ #define TEST_REGULAR(x, y, expected) TEST_SPECIAL(x, y, expected, false, 0) -template class FmodTest : public LIBC_NAMESPACE::testing::Test { +template +class FmodTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FloorTest.h b/libc/test/src/math/smoke/FloorTest.h index 12944aa775626970f91f9f1cf7d13f54790f9ab9..b2102459bc3de692678eac66e59fa4d0c174552b 100644 --- a/libc/test/src/math/smoke/FloorTest.h +++ b/libc/test/src/math/smoke/FloorTest.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_FLOORTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_FLOORTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class FloorTest : public LIBC_NAMESPACE::testing::Test { +template +class FloorTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FmaTest.h b/libc/test/src/math/smoke/FmaTest.h index c66035927d9896599197d27a9e148000d9802dc7..7063ecf199837b3653e2d43e740508201c7ea01d 100644 --- a/libc/test/src/math/smoke/FmaTest.h +++ b/libc/test/src/math/smoke/FmaTest.h @@ -10,11 +10,12 @@ #define LLVM_LIBC_TEST_SRC_MATH_FMATEST_H #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FmaTestTemplate : public LIBC_NAMESPACE::testing::Test { +class FmaTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { private: using Func = T (*)(T, T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/smoke/FrexpTest.h b/libc/test/src/math/smoke/FrexpTest.h index bf99a9a559f05346759027e9b29df7507f2864dd..e9e496422f7326eebc46f7252ef4f93f33ec4b3b 100644 --- a/libc/test/src/math/smoke/FrexpTest.h +++ b/libc/test/src/math/smoke/FrexpTest.h @@ -7,10 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/BasicOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -template class FrexpTest : public LIBC_NAMESPACE::testing::Test { +template +class FrexpTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FromfpTest.h b/libc/test/src/math/smoke/FromfpTest.h index d3a61baafda106c5a182168e003d3ce49415e8d6..f19f21ce47e7f99e6188e2b0cbeeaa9c3a398174 100644 --- a/libc/test/src/math/smoke/FromfpTest.h +++ b/libc/test/src/math/smoke/FromfpTest.h @@ -9,11 +9,12 @@ #ifndef LIBC_TEST_SRC_MATH_SMOKE_FROMFPTEST_H #define LIBC_TEST_SRC_MATH_SMOKE_FROMFPTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FromfpTestTemplate : public LIBC_NAMESPACE::testing::Test { +class FromfpTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/FromfpxTest.h b/libc/test/src/math/smoke/FromfpxTest.h index f3a1680b05aafc15a565be2fecb55fba46a14255..4aa47a68bb1783e85daa79c86d3599f1c2f86330 100644 --- a/libc/test/src/math/smoke/FromfpxTest.h +++ b/libc/test/src/math/smoke/FromfpxTest.h @@ -9,11 +9,12 @@ #ifndef LIBC_TEST_SRC_MATH_SMOKE_FROMFPXTEST_H #define LIBC_TEST_SRC_MATH_SMOKE_FROMFPXTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class FromfpxTestTemplate : public LIBC_NAMESPACE::testing::Test { +class FromfpxTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/HypotTest.h b/libc/test/src/math/smoke/HypotTest.h index a1b8f8a7fafa55c611cdff754e225cfcfa14eacf..80e9bb7366dfea590dc3768f92430c5bd126cfff 100644 --- a/libc/test/src/math/smoke/HypotTest.h +++ b/libc/test/src/math/smoke/HypotTest.h @@ -10,13 +10,14 @@ #define LLVM_LIBC_TEST_SRC_MATH_HYPOTTEST_H #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" template -class HypotTestTemplate : public LIBC_NAMESPACE::testing::Test { +class HypotTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { private: using Func = T (*)(T, T); using FPBits = LIBC_NAMESPACE::fputil::FPBits; diff --git a/libc/test/src/math/smoke/ILogbTest.h b/libc/test/src/math/smoke/ILogbTest.h index bb5bc33b6b3a6dba27a31cedbcba5c0c6ee765d8..05f906b69947b23848cf071ebd212ba8e21a5239 100644 --- a/libc/test/src/math/smoke/ILogbTest.h +++ b/libc/test/src/math/smoke/ILogbTest.h @@ -12,10 +12,11 @@ #include "src/__support/CPP/limits.h" // INT_MAX #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/ManipulationFunctions.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/Test.h" template -class LlvmLibcILogbTest : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcILogbTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/smoke/LdExpTest.h b/libc/test/src/math/smoke/LdExpTest.h index c3e852a2a473b1cca6c50aa7769e6c187733e06f..713d305c47494a81bbdc794ddd158838619cd9c4 100644 --- a/libc/test/src/math/smoke/LdExpTest.h +++ b/libc/test/src/math/smoke/LdExpTest.h @@ -12,13 +12,14 @@ #include "src/__support/CPP/limits.h" // INT_MAX #include "src/__support/FPUtil/FPBits.h" #include "src/__support/FPUtil/NormalFloat.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include template -class LdExpTestTemplate : public LIBC_NAMESPACE::testing::Test { +class LdExpTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using NormalFloat = LIBC_NAMESPACE::fputil::NormalFloat; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/smoke/LogbTest.h b/libc/test/src/math/smoke/LogbTest.h index 01e1050b4c4f8c3953a5af3efb77843e406ccdbb..4938fcf8f6f16eae3ea3aea4d20fc003f1e5ca32 100644 --- a/libc/test/src/math/smoke/LogbTest.h +++ b/libc/test/src/math/smoke/LogbTest.h @@ -7,10 +7,12 @@ //===----------------------------------------------------------------------===// #include "src/__support/FPUtil/ManipulationFunctions.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -template class LogbTest : public LIBC_NAMESPACE::testing::Test { +template +class LogbTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/ModfTest.h b/libc/test/src/math/smoke/ModfTest.h index 65d61855c9f22d2b0879e2b46ded1528d24fd946..85db2d6d967b20d5a0a7bd80a00bade71d0009aa 100644 --- a/libc/test/src/math/smoke/ModfTest.h +++ b/libc/test/src/math/smoke/ModfTest.h @@ -8,12 +8,14 @@ #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/NearestIntegerOperations.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class ModfTest : public LIBC_NAMESPACE::testing::Test { +template +class ModfTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/NextAfterTest.h b/libc/test/src/math/smoke/NextAfterTest.h index d9c50c8109d8034c0751706a4247d462e8c7b7df..65dba9338285b647740655d4add9c8e3764162c0 100644 --- a/libc/test/src/math/smoke/NextAfterTest.h +++ b/libc/test/src/math/smoke/NextAfterTest.h @@ -14,6 +14,7 @@ #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -29,7 +30,7 @@ ASSERT_FP_EQ_WITH_EXCEPTION(result, expected, FE_INEXACT | FE_OVERFLOW) template -class NextAfterTestTemplate : public LIBC_NAMESPACE::testing::Test { +class NextAfterTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/smoke/NextDownTest.h b/libc/test/src/math/smoke/NextDownTest.h index c678ab1db1deff75b73c9668e542c0888fe95375..b54c6d5763222f8b6b035d2438524a401af1caac 100644 --- a/libc/test/src/math/smoke/NextDownTest.h +++ b/libc/test/src/math/smoke/NextDownTest.h @@ -9,11 +9,12 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_NEXTDOWNTEST_H #define LLVM_LIBC_TEST_SRC_MATH_NEXTDOWNTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class NextDownTestTemplate : public LIBC_NAMESPACE::testing::Test { +class NextDownTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/NextTowardTest.h b/libc/test/src/math/smoke/NextTowardTest.h index b6c1c8d1797da67e2e8b688028f27bb9b528a5fc..1894d324b085463150b35421db281492c9703b84 100644 --- a/libc/test/src/math/smoke/NextTowardTest.h +++ b/libc/test/src/math/smoke/NextTowardTest.h @@ -15,6 +15,7 @@ #include "src/__support/CPP/type_traits.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -30,7 +31,7 @@ ASSERT_FP_EQ_WITH_EXCEPTION(result, expected, FE_INEXACT | FE_OVERFLOW) template -class NextTowardTestTemplate : public LIBC_NAMESPACE::testing::Test { +class NextTowardTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using ToFPBits = LIBC_NAMESPACE::fputil::FPBits; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/smoke/NextUpTest.h b/libc/test/src/math/smoke/NextUpTest.h index ebbdb5c73def9e3e1fc1471740cfcaef31b5d093..7f66c115dfc2dce99d985a0128975069de3ae3e8 100644 --- a/libc/test/src/math/smoke/NextUpTest.h +++ b/libc/test/src/math/smoke/NextUpTest.h @@ -9,11 +9,12 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_NEXTUPTEST_H #define LLVM_LIBC_TEST_SRC_MATH_NEXTUPTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class NextUpTestTemplate : public LIBC_NAMESPACE::testing::Test { +class NextUpTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/RIntTest.h b/libc/test/src/math/smoke/RIntTest.h index cbed9a3b10baab13e003128986dcd0864da3e0e7..1412c3f27a2d5f3828f5e82129e83243cd4091bb 100644 --- a/libc/test/src/math/smoke/RIntTest.h +++ b/libc/test/src/math/smoke/RIntTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -22,7 +23,7 @@ static constexpr int ROUNDING_MODES[4] = {FE_UPWARD, FE_DOWNWARD, FE_TOWARDZERO, FE_TONEAREST}; template -class RIntTestTemplate : public LIBC_NAMESPACE::testing::Test { +class RIntTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: typedef T (*RIntFunc)(T); diff --git a/libc/test/src/math/smoke/RemQuoTest.h b/libc/test/src/math/smoke/RemQuoTest.h index 7df537d8b206319a9c30a9e31108206d8cfe9be7..43eee3d38e4495985da5e12325acd6b11cad4454 100644 --- a/libc/test/src/math/smoke/RemQuoTest.h +++ b/libc/test/src/math/smoke/RemQuoTest.h @@ -12,11 +12,12 @@ #include "hdr/math_macros.h" #include "src/__support/FPUtil/BasicOperations.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class RemQuoTestTemplate : public LIBC_NAMESPACE::testing::Test { +class RemQuoTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { using FPBits = LIBC_NAMESPACE::fputil::FPBits; using StorageType = typename FPBits::StorageType; diff --git a/libc/test/src/math/smoke/RoundEvenTest.h b/libc/test/src/math/smoke/RoundEvenTest.h index e168d57bdbf3c791bb21f57a5f81eed41dee1d31..479b70912fedc99455f69115684a42103ea916e9 100644 --- a/libc/test/src/math/smoke/RoundEvenTest.h +++ b/libc/test/src/math/smoke/RoundEvenTest.h @@ -9,13 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_ROUNDEVENTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_ROUNDEVENTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" template -class RoundEvenTest : public LIBC_NAMESPACE::testing::Test { +class RoundEvenTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/RoundTest.h b/libc/test/src/math/smoke/RoundTest.h index 49b2a1bf7dfba70cfc876f8dcf584c1f89a6c01d..36994f27eb4c05f1857d1a9b967834c6d248e57b 100644 --- a/libc/test/src/math/smoke/RoundTest.h +++ b/libc/test/src/math/smoke/RoundTest.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_ROUNDTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_ROUNDTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class RoundTest : public LIBC_NAMESPACE::testing::Test { +template +class RoundTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/RoundToIntegerTest.h b/libc/test/src/math/smoke/RoundToIntegerTest.h index 863cf75f05ff6b57e25bd18b97b10699daab959e..50bcd4a6a76c0d2f7035704502b3afa101103fe9 100644 --- a/libc/test/src/math/smoke/RoundToIntegerTest.h +++ b/libc/test/src/math/smoke/RoundToIntegerTest.h @@ -11,6 +11,7 @@ #include "src/__support/FPUtil/FEnvImpl.h" #include "src/__support/FPUtil/FPBits.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" @@ -21,7 +22,8 @@ static constexpr int ROUNDING_MODES[4] = {FE_UPWARD, FE_DOWNWARD, FE_TOWARDZERO, FE_TONEAREST}; template -class RoundToIntegerTestTemplate : public LIBC_NAMESPACE::testing::Test { +class RoundToIntegerTestTemplate + : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: typedef I (*RoundToIntegerFunc)(F); @@ -61,6 +63,8 @@ private: public: void SetUp() override { + LIBC_NAMESPACE::testing::FEnvSafeTest::SetUp(); + if (math_errhandling & MATH_ERREXCEPT) { // We will disable all exceptions so that the test will not // crash with SIGFPE. We can still use fetestexcept to check diff --git a/libc/test/src/math/smoke/SqrtTest.h b/libc/test/src/math/smoke/SqrtTest.h index 46382ed58e140284d2077c9a89823b346929a924..8afacaf01ae4284b8590cb8369f06a21563a4f6c 100644 --- a/libc/test/src/math/smoke/SqrtTest.h +++ b/libc/test/src/math/smoke/SqrtTest.h @@ -7,12 +7,14 @@ //===----------------------------------------------------------------------===// #include "src/__support/CPP/bit.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class SqrtTest : public LIBC_NAMESPACE::testing::Test { +template +class SqrtTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/TruncTest.h b/libc/test/src/math/smoke/TruncTest.h index c0fc87f9313b2f72ab53e44122574ead360af1e5..1d9c44dfb3748850443250d0fbc136677d509695 100644 --- a/libc/test/src/math/smoke/TruncTest.h +++ b/libc/test/src/math/smoke/TruncTest.h @@ -9,12 +9,14 @@ #ifndef LLVM_LIBC_TEST_SRC_MATH_SMOKE_TRUNCTEST_H #define LLVM_LIBC_TEST_SRC_MATH_SMOKE_TRUNCTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include "hdr/math_macros.h" -template class TruncTest : public LIBC_NAMESPACE::testing::Test { +template +class TruncTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/UfromfpTest.h b/libc/test/src/math/smoke/UfromfpTest.h index 9ad1e6dce945967bc37d3d032522f9d4bf35351c..1c04049ebb4fa4c1a2d7af7724b642026b8b6908 100644 --- a/libc/test/src/math/smoke/UfromfpTest.h +++ b/libc/test/src/math/smoke/UfromfpTest.h @@ -9,11 +9,12 @@ #ifndef LIBC_TEST_SRC_MATH_SMOKE_UFROMFPTEST_H #define LIBC_TEST_SRC_MATH_SMOKE_UFROMFPTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class UfromfpTestTemplate : public LIBC_NAMESPACE::testing::Test { +class UfromfpTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/UfromfpxTest.h b/libc/test/src/math/smoke/UfromfpxTest.h index 09163b8adfa5c0523dc4dbaddd1341396b4f0c44..973bc8a4d1be7b9321193ffbf4b6f5c0475c5103 100644 --- a/libc/test/src/math/smoke/UfromfpxTest.h +++ b/libc/test/src/math/smoke/UfromfpxTest.h @@ -9,11 +9,12 @@ #ifndef LIBC_TEST_SRC_MATH_SMOKE_UFROMFPXTEST_H #define LIBC_TEST_SRC_MATH_SMOKE_UFROMFPXTEST_H +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" template -class UfromfpxTestTemplate : public LIBC_NAMESPACE::testing::Test { +class UfromfpxTestTemplate : public LIBC_NAMESPACE::testing::FEnvSafeTest { DECLARE_SPECIAL_CONSTANTS(T) diff --git a/libc/test/src/math/smoke/nan_test.cpp b/libc/test/src/math/smoke/nan_test.cpp index 56c1e9164df41a77ee5d4abe96c7b1389a5088e8..2ddef58325671f32bae9f19b864bf8b63618fa52 100644 --- a/libc/test/src/math/smoke/nan_test.cpp +++ b/libc/test/src/math/smoke/nan_test.cpp @@ -8,11 +8,12 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/math/nan.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include -class LlvmLibcNanTest : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcNanTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using StorageType = LIBC_NAMESPACE::fputil::FPBits::StorageType; diff --git a/libc/test/src/math/smoke/nanf128_test.cpp b/libc/test/src/math/smoke/nanf128_test.cpp index 652e35ccb53d7a687d4bd523fb94082788832c3e..8c15c532ebcf4cdfe08052666bed8b8f4c45556b 100644 --- a/libc/test/src/math/smoke/nanf128_test.cpp +++ b/libc/test/src/math/smoke/nanf128_test.cpp @@ -9,10 +9,11 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/__support/uint128.h" #include "src/math/nanf128.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" -class LlvmLibcNanf128Test : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcNanf128Test : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using FPBits128 = LIBC_NAMESPACE::fputil::FPBits; using StorageType = FPBits128::StorageType; diff --git a/libc/test/src/math/smoke/nanf_test.cpp b/libc/test/src/math/smoke/nanf_test.cpp index bce495f1a9738be88015c331b295a5c6be90df3c..71f888c610aafcffe5d598cf192b3ab82c75d59f 100644 --- a/libc/test/src/math/smoke/nanf_test.cpp +++ b/libc/test/src/math/smoke/nanf_test.cpp @@ -8,11 +8,12 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/math/nanf.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include -class LlvmLibcNanfTest : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcNanfTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using StorageType = LIBC_NAMESPACE::fputil::FPBits::StorageType; diff --git a/libc/test/src/math/smoke/nanl_test.cpp b/libc/test/src/math/smoke/nanl_test.cpp index 5ff70a94b54d310789c31683f426129fab4acf55..7fff20b1e7be3c1bc0f18f4180e3598393ec29e3 100644 --- a/libc/test/src/math/smoke/nanl_test.cpp +++ b/libc/test/src/math/smoke/nanl_test.cpp @@ -8,6 +8,7 @@ #include "src/__support/FPUtil/FPBits.h" #include "src/math/nanl.h" +#include "test/UnitTest/FEnvSafeTest.h" #include "test/UnitTest/FPMatcher.h" #include "test/UnitTest/Test.h" #include @@ -22,7 +23,7 @@ #error "Unknown long double type" #endif -class LlvmLibcNanlTest : public LIBC_NAMESPACE::testing::Test { +class LlvmLibcNanlTest : public LIBC_NAMESPACE::testing::FEnvSafeTest { public: using StorageType = LIBC_NAMESPACE::fputil::FPBits::StorageType; diff --git a/libclc/cmake/modules/AddLibclc.cmake b/libclc/cmake/modules/AddLibclc.cmake index bbedc244a72899534a3e08b4592b3c30e5e5bd4d..7f4620fa6a21dfda76b3222677c2eb5b6e7dbc4f 100644 --- a/libclc/cmake/modules/AddLibclc.cmake +++ b/libclc/cmake/modules/AddLibclc.cmake @@ -88,10 +88,25 @@ function(link_bc) ${ARGN} ) + set( LINK_INPUT_ARG ${ARG_INPUTS} ) + if( WIN32 OR CYGWIN ) + # Create a response file in case the number of inputs exceeds command-line + # character limits on certain platforms. + file( TO_CMAKE_PATH ${LIBCLC_ARCH_OBJFILE_DIR}/${ARG_TARGET}.rsp RSP_FILE ) + # Turn it into a space-separate list of input files + list( JOIN ARG_INPUTS " " RSP_INPUT ) + file( WRITE ${RSP_FILE} ${RSP_INPUT} ) + # Ensure that if this file is removed, we re-run CMake + set_property( DIRECTORY APPEND PROPERTY CMAKE_CONFIGURE_DEPENDS + ${RSP_FILE} + ) + set( LINK_INPUT_ARG "@${RSP_FILE}" ) + endif() + add_custom_command( OUTPUT ${ARG_TARGET}.bc - COMMAND libclc::llvm-link -o ${ARG_TARGET}.bc ${ARG_INPUTS} - DEPENDS libclc::llvm-link ${ARG_INPUTS} + COMMAND libclc::llvm-link -o ${ARG_TARGET}.bc ${LINK_INPUT_ARG} + DEPENDS libclc::llvm-link ${ARG_INPUTS} ${RSP_FILE} ) add_custom_target( ${ARG_TARGET} ALL DEPENDS ${ARG_TARGET}.bc ) diff --git a/libcxx/benchmarks/CMakeLists.txt b/libcxx/benchmarks/CMakeLists.txt index 527a2acf2d3b3698512c940bb6a7d5d5356e9713..5dc3be0c367e5edbcebf66e5abd34144451a534a 100644 --- a/libcxx/benchmarks/CMakeLists.txt +++ b/libcxx/benchmarks/CMakeLists.txt @@ -224,6 +224,7 @@ set(BENCHMARK_TESTS shared_mutex_vs_mutex.bench.cpp stop_token.bench.cpp std_format_spec_string_unicode.bench.cpp + std_format_spec_string_unicode_escape.bench.cpp string.bench.cpp stringstream.bench.cpp system_error.bench.cpp diff --git a/libcxx/benchmarks/std_format_spec_string_unicode_escape.bench.cpp b/libcxx/benchmarks/std_format_spec_string_unicode_escape.bench.cpp new file mode 100644 index 0000000000000000000000000000000000000000..3b5a1c4340c35e1a517be2eb4ccd671d0a1c8267 --- /dev/null +++ b/libcxx/benchmarks/std_format_spec_string_unicode_escape.bench.cpp @@ -0,0 +1,303 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// This test formats a larger piece of text in "escaped" mode. It uses several +// datasets to give an impression how the amount of multibyte UTF-8 sequences +// and larger grapheme clusters affect the performance. + +#ifndef _LIBCPP_HAS_NO_UNICODE + +# include +# include + +# include "benchmark/benchmark.h" + +# include "make_string.h" + +# define SV(S) MAKE_STRING_VIEW(CharT, S) + +// generated with https://generator.lorem-ipsum.info/_latin + +template +std::basic_string_view ascii_text() { + return SV( + R"( Lorem ipsum dolor sit amet, ne sensibus evertitur aliquando his. +Iuvaret fabulas qui ex, ex iriure iisque nostrum mea. Solum +pericula qui ad. Elitr oporteat ius ad. + +Quas rationibus ad mel. Appellantur intellegebat ad mei, ius audire volumus +consectetuer id. Ei sit definitionem mediocritatem, vim indoctum intellegat id, +dicta laboramus instructior in vix. Mel an quando malorum, id vis mollis +invidunt, placerat maiestatis comprehensam ut cum. Suas regione interesset id +per, et docendi accumsan has, autem atomorum est te. + +Cu debitis ancillae sea, alii definitiones ex cum, vim no erat antiopam. Eam et +unum quas scriptorem. An bonorum elaboraret complectitur nam, vim ei persecuti +democritum mediocritatem. Suscipit platonem signiferumque ei cum, in sale +volutpat ocurreret vel. Te vel nihil nominavi adipiscing, stet ancillae mel ea. +Sit detraxit menandri platonem ea, cum at tale viris virtute. + +Regione detraxit gloriatur sit eu, sonet labitur sententiae et pro, at sit +alterum aliquid interpretaris. Sonet voluptua duo id, vix ea accumsan +liberavisse. Nam id commune probatus contentiones. Et zril dolore laudem duo, +ea usu mollis melius referrentur, vel ex case consequuntur. Id nam illum mollis +ponderum. Quis tamquam ullamcorper sed ne, legimus vituperatoribus est id. + +Et eum probo consulatu. At eos errem aliquando theophrastus, sea ad eius omnis. +No vis iusto scriptorem adversarium, dicat viderer ea sit. Et veri euripidis +sea, justo putent iudicabit vim id. Sea suas tincidunt vituperatoribus in. Ne +eam aeterno sensibus concludaturque, solet legere his id, usu ei dicat +dissentiunt. Est et autem erant. + +Per quod laboramus an. Dico voluptua at mea, an animal minimum eum. Pri an +option salutatus, causae feugiat menandri an sed. Voluptaria dissentiet vix ut, +alii solet te quo, in facer ceteros eos. Ad nibh meis percipitur sit, +aliquam molestie cu vis, iisque malorum interesset et eos. + +Eos in feugiat insolens abhorreant. Ea tale esse alienum has, mel et saperet +appellantur, aliquip salutandi deterruisset ut mel. Eos ei quod simul +interpretaris, aeque elitr putent per at, et veri eripuit ceteros his. Cu pro +meis aperiam volutpat, ex alterum scripserit ius, scriptorem deterruisset eu +qui. Graeco debitis lobortis cu mea. + +Alii corpora id ius, cu quo oblique eloquentiam. Et duis civibus atomorum sea, +veniam utroque scriptorem vim cu. Ut oratio eruditi mediocritatem est. Amet +nibh dolore mea ea, tollit laoreet eligendi qui ex, cu essent forensibus +his. + +Usu ex ipsum apeirian, eos congue scripserit omittantur et. Ea eum persecuti +deseruisse, probatus torquatos est no, in has mutat mundi dolorem. Albucius +sensibus ex cum. Ferri virtute referrentur an per, est choro option bonorum ex. + +Quando accusam vis te, tale mazim et pro. Magna dolorem tincidunt +nec te, albucius adipisci ad pri. Magna facilisi adipisci at usu, et vel +dissentiunt neglegentur, prima audiam vocibus an duo. Enim detracto te sea, mel +quis dicit gubergren ex, iusto adversarium consequuntur per ne. + +)"); +} + +template +std::basic_string_view unicode_text() { + return SV( + R"(Lōrem ipsūm dolor sīt æmeÞ, ea vel nostrud feuġǣit, muciūs tēmporiȝus +refērrēnÞur no mel, quo placērǽt consecÞetuer cū. Veri soƿet euripīðis id has, +sumo paulō dissentias duo eī, dētrāxīt neglēgeƿtur ið prī. Sēd option oporÞerē +no. Nec ēū nēmore mentitum. Veri prōȝo faċilis āt vīm. + +Ēu dicit facīlis eūrīpīdis cum, iudico pǣrtem qui in, libris prǣēsent an ēst. +Æt sit quoðsi impētus, nec ex qūaeque honestǣtīs. Fiērēƿt ƿōluisse verterem iƿ +ēst. Meī eæ apēriæm fierent peÞentīūm. Eæm officiīs reprehēndunt nē. + +Ut vel quodsī contentioƿes, his eū dignissim īnstruċÞior. Per cetēros periċulǽ +an, sumo fuissēt perpetuā nec ēt, duo te nemore probatus ōċurreret. Mel ǣd +civībus ocūrreret. Ex nostro ǣliquam usu, ex Þātīon adipiscī qui. Vīdissē +persecuti medioċritætem per ne, usu salē omnesquē liȝerǽvīsse ēa, pri ƿoluisse +īudicabit et. No summo quiðǣm nec, vim ēi nūmqūam sænctus concepÞǣm. Reque +doceƿdi īn īus, porro eripuiÞ intērprētaris pri in. + +Idquē hǣbēmus nominati vix cū. AÞ prō ǽmēt elit periculæ. Has virīs viderer ān. +Mel in suās pericūlīs āppellantur, nonumes deserūƿt ǽðversarium eā has. ĒliÞ +possīt commuƿe no ēsÞ, niȝh aċcusāmūs volūpÞatum no mel, ut quō ciȝo ðiceret. +Inǣni scripta quālīsque nē qūi, ad ipsūm persecuÞi mediōcritæÞēm vel. + +Ǣppetere definitiōnes mel id. Leġerē āliquip nam eǣ, rēgione viderer pǣtrioque +duo te, meƿāƿdri prodēsseÞ ex hīs. Solum quidam eæ iūs, mēl ǣt sapientem +expliċari. Īƿ ǣċcusǣm phǽedrum pro, ex pro dēleƿit detræxit hendrerīt, sit āgam +quidām pertinax uÞ. Ēssent rætionibus eǽ vēl, quo ān labore nusquæm nominǣti. + +Te alii cōnseÞetur ƿam, eam ēt puteƿÞ ðissentiæs. Qūi alii dicānt repuðiære ēā, +nō mel ferri nūsquam. Ea vim impedīt vertērem, ǣn per veri Þīmeam. SiÞ ōmitÞǽm +necēssitǣÞibus ex, ƿe vis inǣni pærtem invenire. Īd ðolores ċonsēċÞeÞuer usu, +īd vis nisl dēnique luptǣtūm. Pro ǽd ēverti option dēserūƿt, nec te ōðiō +cīvībūs. + +Ēæ nibh æccommodarē eum. Ne etiæm īudico dicunt duo, quo tēmpor populo insōlens +nē. Ēos eÞ ēirmod prǽēsēƿt. Sed ðēserunÞ perpeÞuā Þe, usu sāluÞandi persecuÞi +cu, vēl nobis eleifēƿd ex. + +Ƿe zrīl ūtīnam lǣtīne eǣm, eā vim rebum omitÞǣm aðipisciƿg. Amet inermis +epiċūri ut est, eu duo hīnc periċulis. Mel no reque simul volupÞātum, ex mutat +lāudem tacīmatēs cum. Te hǣs summo iƿteġre recteque. No iūs dicerēt +ðisputǽtioƿi. Vim ōmnis deleƿiÞi honestātis ēǽ. + +Nec detrǣcto pērcipitur ne. Ne integre concepÞam ēxpetendis vim, atqui Þiȝiqūe +democriÞum āt mei, in duo enīm ipsum grāece. Rebum ðefīnīÞionem āt pri, ēt sit +brute periculis. Ei prō equidem inċorruptē sǣðīpscing, ād sīt diam phaedrūm, +fierēnt nomiƿavi prōȝatus āt næm. Wisi ƿæÞūm coƿsecteÞuer usū ea. +)"); +} + +template +std::basic_string_view cyrillic_text() { + return SV( + R"(Лорем ипсум долор сит амет, еу диам тамяуам принципес вис, еяуидем +цонцептам диспутандо яуи цу, иус ад натум нулла граеци. Цибо дицит омниум нец +цу, еу бруте номинави диссентиет яуо. Омниум лаборамус еу хас. Дицат +диспутатиони вис еу, цу еос миним атоморум инцидеринт. Пер хабео рецтеяуе +дигниссим ан, ех яуо сенсибус торяуатос, ан. + +Ут перпетуа партиендо принципес хис. Ат симул ностер аппареат пер. Пурто вирис +ет хис, мазим дицерет при ет. Хис саперет тибияуе сцаевола еу, сит солет +вивендум цонсеяуат те. Ид оффициис перпетуа ассентиор яуи, сед аугуе афферт +симилияуе ад, ех адмодум постулант иус. + +Про дицунт волуптатум диспутатиони ат. Вел патриояуе персецути еа, цетерос +диспутатиони ин сед, нам те веро цлита малуиссет. Цу неглегентур инструцтиор +интерпретарис еам, ипсум фабулас еи вел. Еи адхуц деленити нам, аугуе +демоцритум при ан. Вим мелиоре проприае ид, албуциус волуптуа цоррумпит дуо ан. +Латине иуварет пер ут, иус еа мунере ерипуит санцтус. + +Модус тритани иус не, вим ут мелиоре мандамус, лабитур опортере дуо но. Ад нец +витае фацилис инцоррупте, цу сед толлит сцрипторем. Сит лудус инимицус +волуптариа не. Иисяуе антиопам сапиентем сед еу. Путент волуптуа сит ех, ат иус +ребум епицури, яуи моллис елигенди ех. Проприае нолуиссе цу сеа, путент поссит +адверсариум про не. + +Ид яуо прима бонорум, дуо форенсибус яуаерендум еи, еум бруте мунере те. Еам +риденс граецо ех, аеяуе санцтус маиорум ан вел. Либрис санцтус утрояуе ест но, +еам ат реяуе порро тинцидунт, ут хинц иллуд патриояуе хис. Не солет оффендит +форенсибус хас, тамяуам опортеат елаборарет те нец, еу аугуе примис маиорум +еам. Аутем вениам импедит вис ин, прима елитр пхаедрум ест еу.)"); +} + +template +std::basic_string_view japanese_text() { + return SV( + R"(入ト年媛ろ舗学ラロ準募ケカ社金スノ屋検れう策他セヲシ引口ぎ集7独ぱクふ出車ぽでぱ円輪ルノ受打わ。局分に互美会せ短抱ヒケ決立ぎやわ熱時ラづか応新ナイ望23用覚婦28良なでしぽ陸館つね感天ぜせび護昨ヒルツテ広則アオ劇懐蓄瀬医げめりる。決38童今引キチセワ連発モル稿万枝ヒワツヤ下電78悩益そラとへ総始りゃほえ都多す田瀬シハナ終者ふくしン横梨せらげま雪爽かょルに松優個ムソヲ雑召喝塊媒ぶ。 + +紙ヤ景異ミノオ誤求レ移著ヤエヨメ広庫テハヌサ君検あ必参ワ火面るね声著ン間売力を数20談すがス禁化ッを。起そり予浩ド進皇キ試属が震二トヌ真佳速すずちし件諏フウチ聞在ス会雄ノミ必筋80戦ぶさほド聞2涙属どスれ映聞ネ掲実べ。 + +8福びり属稿づ徳鎌ニル涼問ゃごるリ付92済トぎけッ康30業づむはつ治然二生入ざひ有動ハワチ発談ニスツ魚困摘策送ざ。個時着そてら新新ヌ鉄報たは作主ずリ可輸改量ルおず井認つてぜな会大ぼすぶし全戸ノハケレ貯治たざリな祖間ムリキ断会仕べせど。委暮ど象週トクワ流開タハ硬給ツタウ者善マラノヱ断稿リヲ東毎ツヨマ井藤ルょへ境同論エ愛図ッらフリ基38属慣葬8携ヱ校図おに岐題しね要月レユ展省わトど。 + +担がは顔研リ目問いぽべ挙介ん入番ネヌイ栄県し改治ラス健第モム得続加ホウ嘉宿置首本やぞ。78毎まが現設記ほぜね場歩ユアルヒ東的ヒ姿役ネヲ聞能ラシマヒ際形トくゃ政能万の付結ス国1教レツ引写イど扱澤は膚言けリいべ橋柔薄組こよじ。浩報すンつひ崎正念方と夫地クざす情阪スで抜長ネ娘回ハツ止資ヘニ並辞ロノ展師質18打テネ岡時ノモ泉95務えぴひつ速申後延んフるせ。 + +店てラ載独マシフ理心ス型部米た読石カ料応掲ケカキ打月在ユテニ採材イ並発イヒト旅錯っめし模能りせば連確え会准揮が。器にト画軍にぶイら式東みそお前姿リいけに身47却6記け岸5体会ゃばま映8碁よぽだ経9名トびち更躍うにふ裏高もそ提旅さぼえス。賞ぞだ月係ソ知建振イナシ説並イ見書傳ヨミ問回級エシ出所師阪ト転権がし渡平ルモケ新完ハ玲女ロトシ導複トうよふ。 + +化シセチ町74掲ネテトオ連対ヒハチモ経後ッ断連カロワ待業ぼぽねか百都へがい始塗ごげ寺帰んぽ逆力るず選英堂衛掛焼ゅ。自生トサリ探就的らね江球リルスツ主嘆4権伝ざが避掲う慶合ワ百29暮ネヤクム書能部あが席小フア部親票ーむとこ。3説ひっぜ約毎伎ナキリ缶近くなず員45姿えにけろ値付ワ着知ソルキ日医ず集新エウカケ投国チ生目ゃ棋運ぐのか寄募オチ性注経どドんて止代わくかな端期幕はかク。 +)"); +} + +template +std::basic_string_view emoji_text() { + return SV( + R"( +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 +\U0001F636\u200D\U0001F32B\uFE0F +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF + +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 + +\U0001F636\u200D\U0001F32B\uFE0F + +\U0001F44B\U0001F3FB\U0001F44B\U0001F3FC\U0001F44B\U0001F3FD\U0001F44B\U0001F3FE\U0001F44B\U0001F3FF + +\U0001F468\u200D\U0001F469\u200D\U0001F467\u200D\U0001F466\U0001F1E8\U0001F1E6 + +\U0001F984 + +)"); +} + +template +void BM_escaped(benchmark::State& state, std::basic_string_view input) { + CharT buffer[25'000]; + + if constexpr (std::same_as) { + // Make sure the output buffer is large enough. + assert(std::formatted_size("{}", input) == 3000); + for (auto _ : state) + benchmark::DoNotOptimize(std::format_to(buffer, "{:?}", input)); + } else { + for (auto _ : state) + benchmark::DoNotOptimize(std::format_to(buffer, L"{:?}", input)); + } +} + +template +void BM_ascii_escaped(benchmark::State& state) { + BM_escaped(state, ascii_text()); +} + +template +void BM_unicode_escaped(benchmark::State& state) { + BM_escaped(state, unicode_text()); +} + +template +void BM_cyrillic_escaped(benchmark::State& state) { + BM_escaped(state, cyrillic_text()); +} + +template +void BM_japanese_escaped(benchmark::State& state) { + BM_escaped(state, japanese_text()); +} + +template +void BM_emoji_escaped(benchmark::State& state) { + BM_escaped(state, emoji_text()); +} + +BENCHMARK_TEMPLATE(BM_ascii_escaped, char); +BENCHMARK_TEMPLATE(BM_unicode_escaped, char); +BENCHMARK_TEMPLATE(BM_cyrillic_escaped, char); +BENCHMARK_TEMPLATE(BM_japanese_escaped, char); +BENCHMARK_TEMPLATE(BM_emoji_escaped, char); + +BENCHMARK_TEMPLATE(BM_ascii_escaped, wchar_t); +BENCHMARK_TEMPLATE(BM_unicode_escaped, wchar_t); +BENCHMARK_TEMPLATE(BM_cyrillic_escaped, wchar_t); +BENCHMARK_TEMPLATE(BM_japanese_escaped, wchar_t); +BENCHMARK_TEMPLATE(BM_emoji_escaped, wchar_t); + +int main(int argc, char** argv) { + benchmark::Initialize(&argc, argv); + if (benchmark::ReportUnrecognizedArguments(argc, argv)) + return 1; + + benchmark::RunSpecifiedBenchmarks(); +} +#else +int main(int, char**) { return 0; } +#endif diff --git a/libcxx/include/__numeric/saturation_arithmetic.h b/libcxx/include/__numeric/saturation_arithmetic.h index 41596a0c58e27de98128b10331268ac830fda574..2390b42aaec31e012b2e1ea36aabe90db4c23d71 100644 --- a/libcxx/include/__numeric/saturation_arithmetic.h +++ b/libcxx/include/__numeric/saturation_arithmetic.h @@ -25,10 +25,10 @@ _LIBCPP_PUSH_MACROS _LIBCPP_BEGIN_NAMESPACE_STD -#if _LIBCPP_STD_VER >= 26 +#if _LIBCPP_STD_VER >= 20 template <__libcpp_integer _Tp> -_LIBCPP_HIDE_FROM_ABI constexpr _Tp add_sat(_Tp __x, _Tp __y) noexcept { +_LIBCPP_HIDE_FROM_ABI constexpr _Tp __add_sat(_Tp __x, _Tp __y) noexcept { if (_Tp __sum; !__builtin_add_overflow(__x, __y, &__sum)) return __sum; // Handle overflow @@ -46,7 +46,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr _Tp add_sat(_Tp __x, _Tp __y) noexcept { } template <__libcpp_integer _Tp> -_LIBCPP_HIDE_FROM_ABI constexpr _Tp sub_sat(_Tp __x, _Tp __y) noexcept { +_LIBCPP_HIDE_FROM_ABI constexpr _Tp __sub_sat(_Tp __x, _Tp __y) noexcept { if (_Tp __sub; !__builtin_sub_overflow(__x, __y, &__sub)) return __sub; // Handle overflow @@ -65,7 +65,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr _Tp sub_sat(_Tp __x, _Tp __y) noexcept { } template <__libcpp_integer _Tp> -_LIBCPP_HIDE_FROM_ABI constexpr _Tp mul_sat(_Tp __x, _Tp __y) noexcept { +_LIBCPP_HIDE_FROM_ABI constexpr _Tp __mul_sat(_Tp __x, _Tp __y) noexcept { if (_Tp __mul; !__builtin_mul_overflow(__x, __y, &__mul)) return __mul; // Handle overflow @@ -81,7 +81,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr _Tp mul_sat(_Tp __x, _Tp __y) noexcept { } template <__libcpp_integer _Tp> -_LIBCPP_HIDE_FROM_ABI constexpr _Tp div_sat(_Tp __x, _Tp __y) noexcept { +_LIBCPP_HIDE_FROM_ABI constexpr _Tp __div_sat(_Tp __x, _Tp __y) noexcept { _LIBCPP_ASSERT_UNCATEGORIZED(__y != 0, "Division by 0 is undefined"); if constexpr (__libcpp_unsigned_integer<_Tp>) { return __x / __y; @@ -94,7 +94,7 @@ _LIBCPP_HIDE_FROM_ABI constexpr _Tp div_sat(_Tp __x, _Tp __y) noexcept { } template <__libcpp_integer _Rp, __libcpp_integer _Tp> -_LIBCPP_HIDE_FROM_ABI constexpr _Rp saturate_cast(_Tp __x) noexcept { +_LIBCPP_HIDE_FROM_ABI constexpr _Rp __saturate_cast(_Tp __x) noexcept { // Saturation is impossible edge case when ((min _Rp) < (min _Tp) && (max _Rp) > (max _Tp)) and it is expected to be // optimized out by the compiler. @@ -107,6 +107,35 @@ _LIBCPP_HIDE_FROM_ABI constexpr _Rp saturate_cast(_Tp __x) noexcept { return static_cast<_Rp>(__x); } +#endif // _LIBCPP_STD_VER >= 20 + +#if _LIBCPP_STD_VER >= 26 + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp add_sat(_Tp __x, _Tp __y) noexcept { + return std::__add_sat(__x, __y); +} + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp sub_sat(_Tp __x, _Tp __y) noexcept { + return std::__sub_sat(__x, __y); +} + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp mul_sat(_Tp __x, _Tp __y) noexcept { + return std::__mul_sat(__x, __y); +} + +template <__libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Tp div_sat(_Tp __x, _Tp __y) noexcept { + return std::__div_sat(__x, __y); +} + +template <__libcpp_integer _Rp, __libcpp_integer _Tp> +_LIBCPP_HIDE_FROM_ABI constexpr _Rp saturate_cast(_Tp __x) noexcept { + return std::__saturate_cast<_Rp>(__x); +} + #endif // _LIBCPP_STD_VER >= 26 _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/modules/std.compat/cstdlib.inc b/libcxx/modules/std.compat/cstdlib.inc index a45a0a1caf8ba9aac9105f8c638cd4c72f809454..4783cbf51623902891c9202493e616e57e5f83ed 100644 --- a/libcxx/modules/std.compat/cstdlib.inc +++ b/libcxx/modules/std.compat/cstdlib.inc @@ -25,7 +25,7 @@ export { using ::system; // [c.malloc], C library memory allocation - using ::aligned_alloc; + using ::aligned_alloc _LIBCPP_USING_IF_EXISTS; using ::calloc; using ::free; using ::malloc; diff --git a/libcxx/src/time_zone.cpp b/libcxx/src/time_zone.cpp index aef6ac674a11e667f2e26247fa21c821592ac03d..928f3d2855e456f809e2e787d612f2c23d39fd49 100644 --- a/libcxx/src/time_zone.cpp +++ b/libcxx/src/time_zone.cpp @@ -567,11 +567,22 @@ __first_rule(seconds __stdoff, const vector<__tz::__rule>& __rules) { false}; } - __named_rule_until __continuation_end{__continuation}; - if (__time >= __continuation_end.__until() && !__continuation_end.__needs_adjustment()) - // note std::unexpected(__end); is ambiguous with std::unexpected() in , - return __sys_info_result{std::unexpect, __continuation_end.__until()}; + if (__rule->__save.__time != 0s) { + // another fix for America/Punta_Arenas when not at the start of the + // sys_info object. + seconds __save = __rule->__save.__time; + if (__continuation_begin >= __rule_begin - __save && __time < __next.first) { + return __sys_info{ + sys_info{__continuation_begin, + __next.first, + __continuation.__stdoff + __save, + chrono::duration_cast(__save), + chrono::__format(__continuation, __rule->__letters, __save)}, + false}; + } + } + __named_rule_until __continuation_end{__continuation}; while (__next.second != __rules.end()) { #ifdef PRINT std::print( diff --git a/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp b/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp index 25d2ff11d09341c611f0fd6179f20688ccd27d6a..1a1705d5ae59a562927ea7b12b9af064a977beca 100644 --- a/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp +++ b/libcxx/test/std/time/time.zone/time.zone.timezone/time.zone.members/get_info.sys_time.pass.cpp @@ -1299,6 +1299,78 @@ static void test_america_indiana_knox() { tz->get_info(to_sys_seconds(2006y, std::chrono::October, 29d, 6h, 59min, 59s))); } +static void test_america_punta_arenas() { + // Z America/Punta_Arenas -4:43:40 - LMT 1890 + // ... + // -4 - -04 1919 Jul + // -4:42:45 - SMT 1927 S + // -5 x -05/-04 1932 S + // ... + // + // R x 1927 1931 - S 1 0 1 - + // R x 1928 1932 - Ap 1 0 0 - + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("America/Punta_Arenas"); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1927y, std::chrono::September, 1d, 4h, 42min, 45s), + to_sys_seconds(1928y, std::chrono::April, 1d, 4h), + -4h, + 60min, + "-04"), + tz->get_info(to_sys_seconds(1927y, std::chrono::September, 1d, 4h, 42min, 45s))); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1927y, std::chrono::September, 1d, 4h, 42min, 45s), + to_sys_seconds(1928y, std::chrono::April, 1d, 4h), + -4h, + 60min, + "-04"), + tz->get_info(to_sys_seconds(1928y, std::chrono::April, 1d, 3h, 59min, 59s))); +} + +static void test_europ_ljubljana() { + // Z Europe/Ljubljana 0:58:4 - LMT 1884 + // 1 - CET 1941 Ap 18 23 + // 1 c CE%sT 1945 May 8 2s + // 1 1 CEST 1945 S 16 2s + // 1 - CET 1982 N 27 + // 1 E CE%sT + // + // ... + // R c 1943 o - O 4 2s 0 - + // R c 1944 1945 - Ap M>=1 2s 1 S + // R c 1944 o - O 2 2s 0 - + // R c 1945 o - S 16 2s 0 - + // R c 1977 1980 - Ap Su>=1 2s 1 S + // ... + + using namespace std::literals::chrono_literals; + const std::chrono::time_zone* tz = std::chrono::locate_zone("Europe/Ljubljana"); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1945y, std::chrono::April, 2d, 1h), + to_sys_seconds(1945y, std::chrono::September, 16d, 1h), + 2h, + 60min, + "CEST"), + tz->get_info(to_sys_seconds(1945y, std::chrono::April, 2d, 1h))); + + assert_equal( + std::chrono::sys_info( + to_sys_seconds(1945y, std::chrono::April, 2d, 1h), + to_sys_seconds(1945y, std::chrono::September, 16d, 1h), + 2h, + 60min, + "CEST"), + tz->get_info(to_sys_seconds(1945y, std::chrono::September, 16d, 0h, 59min, 59s))); +} + int main(int, const char**) { // Basic tests test_gmt(); @@ -1333,5 +1405,9 @@ int main(int, const char**) { test_america_ciudad_juarez(); test_america_indiana_knox(); + // Reverse search bugs + test_america_punta_arenas(); + test_europ_ljubljana(); + return 0; } diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 20de1b9b7bde965fefadd5a967c9022dbfbec6cf..20088d92bafa2f007a669834a4f5c26ffb75f0c6 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -15,8 +15,8 @@ #include "llvm/Support/LEB128.h" #include "llvm/Support/RISCVAttributeParser.h" #include "llvm/Support/RISCVAttributes.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/TimeProfiler.h" +#include "llvm/TargetParser/RISCVISAInfo.h" using namespace llvm; using namespace llvm::object; diff --git a/lld/test/ELF/lto/i386-global-offset-table.ll b/lld/test/ELF/lto/i386-global-offset-table.ll new file mode 100644 index 0000000000000000000000000000000000000000..3fa11f6e6d40d72a10b5434bb0b8dd1c60e7448e --- /dev/null +++ b/lld/test/ELF/lto/i386-global-offset-table.ll @@ -0,0 +1,29 @@ +; REQUIRES: x86 +;; LTO-generated relocatable files may reference _GLOBAL_OFFSET_TABLE_ while +;; the IR does not mention _GLOBAL_OFFSET_TABLE_. +;; Test that there is no spurious "undefined symbol" error. + +; RUN: rm -rf %t && mkdir %t && cd %t +; RUN: llvm-as %s -o a.bc +; RUN: ld.lld -pie a.bc -o a +; RUN: llvm-nm a | FileCheck %s + +; CHECK: d _GLOBAL_OFFSET_TABLE_ + +target datalayout = "e-m:e-p:32:32-p270:32:32-p271:32:32-p272:64:64-i128:128-f64:32:64-f80:32-n8:16:32-S128" +target triple = "i386-pc-linux-gnu" + +@i = global i32 0 + +define dso_local void @_start() { +entry: + %0 = load i32, ptr @i + %inc = add nsw i32 %0, 1 + store i32 %inc, ptr @i + ret void +} + +!llvm.module.flags = !{!0, !1} + +!0 = !{i32 8, !"PIC Level", i32 2} +!1 = !{i32 7, !"PIE Level", i32 2} diff --git a/lld/test/ELF/lto/x86-64-global-offset-table.ll b/lld/test/ELF/lto/x86-64-global-offset-table.ll new file mode 100644 index 0000000000000000000000000000000000000000..4b0f638b409e1b22761d64aa74924caa286a77c4 --- /dev/null +++ b/lld/test/ELF/lto/x86-64-global-offset-table.ll @@ -0,0 +1,71 @@ +; REQUIRES: x86 +;; LTO-generated relocatable files may reference _GLOBAL_OFFSET_TABLE_ while +;; the IR does not mention _GLOBAL_OFFSET_TABLE_. +;; Test that there is no spurious "undefined symbol" error. + +; RUN: rm -rf %t && split-file %s %t && cd %t +; RUN: opt -module-summary b.ll -o b.bc + +;; Test Thin LTO. +; RUN: cat a.ll medium.ll | opt -module-summary - -o medium.bc +; RUN: ld.lld -pie --no-relax medium.bc b.bc -o medium +; RUN: llvm-objdump -dt medium | FileCheck %s + +;; Test regular LTO. +; RUN: cat a.ll large.ll | llvm-as - -o large.bc +; RUN: ld.lld -pie large.bc b.bc -o large +; RUN: llvm-objdump -dt large | FileCheck %s + +;; Explicit reference of _GLOBAL_OFFSET_TABLE_ is fine. +; RUN: cat a.ll medium.ll ref.ll | opt -module-summary - -o ref.bc +; RUN: ld.lld -pie -u ref ref.bc b.bc -y _GLOBAL_OFFSET_TABLE_ -o ref 2>&1 | FileCheck %s --check-prefix=TRACE +; RUN: llvm-objdump -dt ref | FileCheck %s + +; TRACE: ref.bc: reference to _GLOBAL_OFFSET_TABLE_ +; TRACE-NEXT: ref.bc: reference to _GLOBAL_OFFSET_TABLE_ +; TRACE-NEXT: : definition of _GLOBAL_OFFSET_TABLE_ +; TRACE-NEXT: ref.lto.ref.o: reference to _GLOBAL_OFFSET_TABLE_ + +;; The IR symbol table references _GLOBAL_OFFSET_TABLE_, which causes lld to define the symbol. +; CHECK: .got.plt 0000000000000000 .hidden _GLOBAL_OFFSET_TABLE_ +; CHECK: movabsq + +;--- a.ll +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@i = external global i32 + +define dso_local void @_start() { +entry: + %0 = load i32, ptr @i + %inc = add nsw i32 %0, 1 + store i32 %inc, ptr @i + ret void +} + +!llvm.module.flags = !{!0, !1, !2, !3} + +!0 = !{i32 8, !"PIC Level", i32 2} +!1 = !{i32 7, !"PIE Level", i32 2} +!2 = !{i32 1, !"Large Data Threshold", i64 0} + +;--- medium.ll +!3 = !{i32 1, !"Code Model", i32 3} + +;--- large.ll +!3 = !{i32 1, !"Code Model", i32 4} + +;--- ref.ll +@_GLOBAL_OFFSET_TABLE_ = external global [0 x i8] + +define dso_local ptr @ref() { +entry: + ret ptr @_GLOBAL_OFFSET_TABLE_ +} + +;--- b.ll +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +@i = global i32 0 diff --git a/lld/test/ELF/mips-eh_frame-pic.s b/lld/test/ELF/mips-eh_frame-pic.s index a84c36b0e5ecdbcfb043297ec3058c78cf935171..c04dbdf57b08ad91a0ae438c8acaa9de1d4a6b83 100644 --- a/lld/test/ELF/mips-eh_frame-pic.s +++ b/lld/test/ELF/mips-eh_frame-pic.s @@ -36,8 +36,8 @@ # RELOCS: .rel{{a?}}.eh_frame { # ABS32-RELOCS-NEXT: 0x1C R_MIPS_32 .text # ABS64-RELOCS-NEXT: 0x1C R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE .text -# PIC64-RELOCS-NEXT: 0x1C R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE -# PIC32-RELOCS-NEXT: 0x1C R_MIPS_PC32 +# PIC64-RELOCS-NEXT: 0x1C R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE .L0 +# PIC32-RELOCS-NEXT: 0x1C R_MIPS_PC32 .L0 # RELOCS-NEXT: } # ABS64-EH-FRAME: Augmentation data: 0C diff --git a/lldb/CMakeLists.txt b/lldb/CMakeLists.txt index 7844d93d78d29af8c9d60daa0b0f0dac33a18385..b0764f1053277f6539e500f2abae00ca44d106ba 100644 --- a/lldb/CMakeLists.txt +++ b/lldb/CMakeLists.txt @@ -75,6 +75,14 @@ if (LLDB_ENABLE_PYTHON) endif() endif() endforeach() + # Make sure lldb extension has "_d" suffix on Windows in Debug mode. + if(WIN32 AND CMAKE_BUILD_TYPE STREQUAL Debug) + string(SUBSTRING ${LLDB_PYTHON_EXT_SUFFIX} 0 2 FIRST_2_CHARS) + # Add "_d" manually if LLDB_PYTHON_EXT_SUFFIX lacks it due to release Python configuration. + if(NOT FIRST_2_CHARS STREQUAL "_d") + set(LLDB_PYTHON_EXT_SUFFIX "_d${LLDB_PYTHON_EXT_SUFFIX}") + endif() + endif() endif () if (LLDB_ENABLE_LUA) diff --git a/lldb/docs/conf.py b/lldb/docs/conf.py index ec7f93710ab6f2015fc30c0c196a28944d6eea4e..27a1cd7c3c31ac3d7b8f43f5137ea03e91608237 100644 --- a/lldb/docs/conf.py +++ b/lldb/docs/conf.py @@ -13,6 +13,9 @@ import sys, os, re, shutil from datetime import date +# Add path for llvm_slug module. +sys.path.insert(0, os.path.abspath(os.path.join("..", "..", "llvm", "docs"))) + building_man_page = tags.has("builder-man") # For the website we need to setup the path to the generated LLDB module that @@ -42,6 +45,23 @@ automodapi_toctreedirnm = "python_api" # coming with Sphinx (named 'sphinx.ext.*') or your custom ones. extensions = ["sphinx.ext.todo", "sphinx.ext.mathjax", "sphinx.ext.intersphinx"] +# When building man pages, we do not use the markdown pages, +# So, we can continue without the myst_parser dependencies. +# Doing so reduces dependencies of some packaged llvm distributions. +try: + import myst_parser + + extensions.append("myst_parser") +except ImportError: + if not tags.has("builder-man"): + raise + +# Automatic anchors for markdown titles +from llvm_slug import make_slug + +myst_heading_anchors = 6 +myst_heading_slug_func = make_slug + autodoc_default_options = {"special-members": True} # Unless we only generate the basic manpage we need the plugin for generating @@ -69,6 +89,7 @@ templates_path = ["_templates"] # The suffix of source filenames. source_suffix = { ".rst": "restructuredtext", + ".md": "markdown", } # The encoding of source files. diff --git a/lldb/docs/index.rst b/lldb/docs/index.rst index c378ab97d97bbb406ac7a563d5030fe2054c5449..6906566ea55e5804f77859514a5492133481f004 100644 --- a/lldb/docs/index.rst +++ b/lldb/docs/index.rst @@ -157,6 +157,7 @@ interesting areas to contribute to lldb. resources/sbapi resources/dataformatters resources/extensions + resources/lldbgdbremote resources/caveats resources/projects Public C++ API diff --git a/lldb/docs/lldb-gdb-remote.txt b/lldb/docs/lldb-gdb-remote.txt deleted file mode 100644 index 6c29de61daba7edd46ae0e5d28b9074d46872492..0000000000000000000000000000000000000000 --- a/lldb/docs/lldb-gdb-remote.txt +++ /dev/null @@ -1,2286 +0,0 @@ -LLDB has added new GDB server packets to better support multi-threaded and -remote debugging. Why? Normally you need to start the correct GDB and the -correct GDB server when debugging. If you have mismatch, then things go wrong -very quickly. LLDB makes extensive use of the GDB remote protocol and we -wanted to make sure that the experience was a bit more dynamic where we can -discover information about a remote target without having to know anything up -front. We also ran into performance issues with the existing GDB remote -protocol that can be overcome when using a reliable communications layer. -Some packets improve performance, others allow for remote process launching -(if you have an OS), and others allow us to dynamically figure out what -registers a thread might have. Again with GDB, both sides pre-agree on how the -registers will look (how many, their register number,name and offsets). We -prefer to be able to dynamically determine what kind of architecture, OS and -vendor we are debugging, as well as how things are laid out when it comes to -the thread register contexts. Below are the details on the new packets we have -added above and beyond the standard GDB remote protocol packets. - -//---------------------------------------------------------------------- -// "QStartNoAckMode" -// -// BRIEF -// Try to enable no ACK mode to skip sending ACKs and NACKs. -// -// PRIORITY TO IMPLEMENT -// High. Any GDB remote server that can implement this should if the -// connection is reliable. This improves packet throughput and increases -// the performance of the connection. -//---------------------------------------------------------------------- -Having to send an ACK/NACK after every packet slows things down a bit, so we -have a way to disable ACK packets to minimize the traffic for reliable -communication interfaces (like sockets). Below GDB or LLDB will send this -packet to try and disable ACKs. All lines that start with "send packet: " are -from GDB/LLDB, and all lines that start with "read packet: " are from the GDB -remote server: - -send packet: $QStartNoAckMode#b0 -read packet: + -read packet: $OK#9a -send packet: + - -//---------------------------------------------------------------------- -// "QSupported" -// -// BRIEF -// Query the GDB remote server for features it supports -// -// PRIORITY TO IMPLEMENT -// Optional. -//---------------------------------------------------------------------- - -QSupported is a standard GDB Remote Serial Protocol packet, but -there are several additions to the response that lldb can parse. -They are not all listed here. - -An example exchange: - -send packet: qSupported:xmlRegisters=i386,arm,mips,arc;multiprocess+;fork-events+;vfork-events+ - -read packet: qXfer:features:read+;PacketSize=20000;qEcho+;native-signals+;SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;SupportedWatchpointTypes=aarch64-mask,aarch64-bas; - -In the example above, three lldb extensions are shown: - - PacketSize=20000 - The base 16 maximum packet size that the stub can handle. - SupportedCompressions= - A list of compression types that the stub can use to compress packets - when the QEnableCompression packet is used to request one of them. - SupportedWatchpointTypes= - A list of watchpoint types that this stub can manage. - Currently defined names are: - x86_64 64-bit x86-64 watchpoints - (1, 2, 4, 8 byte watchpoints aligned to those amounts) - aarch64-bas AArch64 Byte Address Select watchpoints - (any number of contiguous bytes within a doubleword) - aarch64-mask AArch64 MASK watchpoints - (any power-of-2 region of memory from 8 to 2GB, aligned) - If nothing is specified, lldb will default to sending power-of-2 - watchpoints, up to a pointer size, `sizeof(void*)`, a reasonable - baseline assumption. - -//---------------------------------------------------------------------- -// "A" - launch args packet -// -// BRIEF -// Launch a program using the supplied arguments -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to launch a target after -// making a connection to a GDB server that isn't already connected to -// an inferior process. -//---------------------------------------------------------------------- - -We have added support for the "set program arguments" packet where we can -start a connection to a remote server and then later supply the path to the -executable and the arguments to use when executing: - -GDB remote docs for this: - -set program arguments(reserved) Aarglen,argnum,arg,... - -Where A is followed by the length in bytes of the hex encoded argument, -followed by an argument integer, and followed by the ASCII characters -converted into hex bytes foreach arg - -send packet: $A98,0,2f566f6c756d65732f776f726b2f67636c6179746f6e2f446f63756d656e74732f7372632f6174746163682f612e6f7574#00 -read packet: $OK#00 - -The above packet helps when you have remote debugging abilities where you -could launch a process on a remote host, this isn't needed for bare board -debugging. - -//---------------------------------------------------------------------- -// "QEnvironment:NAME=VALUE" -// -// BRIEF -// Setup the environment up for a new child process that will soon be -// launched using the "A" packet. -// -// NB: key/value pairs are sent as-is so gdb-remote protocol meta characters -// (e.g. '#' or '$') are not acceptable. If any non-printable or -// metacharacters are present in the strings, QEnvironmentHexEncoded -// should be used instead if it is available. If you don't want to -// scan the environment strings before sending, prefer -// the QEnvironmentHexEncoded packet over QEnvironment, if it is -// available. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to launch a target after -// making a connection to a GDB server that isn't already connected to -// an inferior process. -//---------------------------------------------------------------------- - -Both GDB and LLDB support passing down environment variables. Is it ok to -respond with a "$#00" (unimplemented): - -send packet: $QEnvironment:ACK_COLOR_FILENAME=bold yellow#00 -read packet: $OK#00 - -This packet can be sent one or more times _prior_ to sending a "A" packet. - -//---------------------------------------------------------------------- -// "QEnvironmentHexEncoded:HEX-ENCODING(NAME=VALUE)" -// -// BRIEF -// Setup the environment up for a new child process that will soon be -// launched using the "A" packet. -// -// The only difference between this packet and QEnvironment is that the -// environment key-value pair is ascii hex encoded for transmission. -// This allows values with gdb-remote metacharacters like '#' to be sent. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to launch a target after -// making a connection to a GDB server that isn't already connected to -// an inferior process. -//---------------------------------------------------------------------- - -Both GDB and LLDB support passing down environment variables. Is it ok to -respond with a "$#00" (unimplemented): - -send packet: $QEnvironment:41434b5f434f4c4f525f46494c454e414d453d626f6c642379656c6c6f77#00 -read packet: $OK#00 - -This packet can be sent one or more times _prior_ to sending a "A" packet. - -//---------------------------------------------------------------------- -// "QEnableErrorStrings" -// -// BRIEF -// This packet enables reporting of Error strings in remote packet -// replies from the server to client. If the server supports this -// feature, it should send an OK response. The client can expect the -// following error replies if this feature is enabled in the server -> -// -// EXX;AAAAAAAAA -// -// where AAAAAAAAA will be a hex encoded ASCII string. -// XX is hex encoded byte number. -// -// It must be noted that even if the client has enabled reporting -// strings in error replies, it must not expect error strings to all -// error replies. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to provide strings that -// are human readable along with an error code. -//---------------------------------------------------------------------- - -send packet: $QEnableErrorStrings -read packet: $OK#00 - -//---------------------------------------------------------------------- -// "QSetSTDIN:" -// "QSetSTDOUT:" -// "QSetSTDERR:" -// -// BRIEF -// Setup where STDIN, STDOUT, and STDERR go prior to sending an "A" -// packet. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to launch a target after -// making a connection to a GDB server that isn't already connected to -// an inferior process. -//---------------------------------------------------------------------- - -When launching a program through the GDB remote protocol with the "A" packet, -you might also want to specify where stdin/out/err go: - -QSetSTDIN: -QSetSTDOUT: -QSetSTDERR: - -These packets must be sent _prior_ to sending a "A" packet. - -//---------------------------------------------------------------------- -// "QSetWorkingDir:" -// -// BRIEF -// Set the working directory prior to sending an "A" packet. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to launch a target after -// making a connection to a GDB server that isn't already connected to -// an inferior process. -//---------------------------------------------------------------------- - -Or specify the working directory: - -QSetWorkingDir: - -This packet must be sent _prior_ to sending a "A" packet. - -//---------------------------------------------------------------------- -// "QSetDisableASLR:" -// -// BRIEF -// Enable or disable ASLR on the next "A" packet. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed if the remote target wants to launch a target after -// making a connection to a GDB server that isn't already connected to -// an inferior process and if the target supports disabling ASLR -// (Address space layout randomization). -//---------------------------------------------------------------------- - -Or control if ASLR is enabled/disabled: - -send packet: QSetDisableASLR:1 -read packet: OK - -send packet: QSetDisableASLR:0 -read packet: OK - -This packet must be sent _prior_ to sending a "A" packet. - -//---------------------------------------------------------------------- -// QListThreadsInStopReply -// -// BRIEF -// Enable the threads: and thread-pcs: data in the question-mark packet -// ("T packet") responses when the stub reports that a program has -// stopped executing. -// -// PRIORITY TO IMPLEMENT -// Performance. This is a performance benefit to lldb if the thread id's -// and thread pc values are provided to lldb in the T stop packet -- if -// they are not provided to lldb, lldb will likely need to send one to -// two packets per thread to fetch the data at every private stop. -//---------------------------------------------------------------------- - -send packet: QListThreadsInStopReply -read packet: OK - -//---------------------------------------------------------------------- -// jLLDBTraceSupported -// -// BRIEF -// Get the processor tracing type supported by the gdb-server for the current -// inferior. Responses might be different depending on the architecture and -// capabilities of the underlying OS. -// -// OUTPUT SCHEMA -// { -// "name": , -// Tracing technology name, e.g. intel-pt, arm-etm. -// "description": , -// Description for this technology. -// } -// -// If no tracing technology is supported for the inferior, or no process is -// running, then an error message is returned. -// -// NOTE -// This packet is used by Trace plug-ins (see lldb_private::Trace.h) to -// do live tracing. Specifically, the name of the plug-in should match the name -// of the tracing technology returned by this packet. -//---------------------------------------------------------------------- - -send packet: jLLDBTraceSupported -read packet: {"name":, "description":}/E;AAAAAAAAA - -//---------------------------------------------------------------------- -// jLLDBTraceStart -// -// BRIEF -// Start tracing a process or its threads using a provided tracing technology. -// The input and output are specified as JSON objects. In case of success, an OK -// response is returned, or an error otherwise. -// -// PROCESS TRACING -// This traces existing and future threads of the current process. An error is -// returned if the process is already being traced. -// -// THREAD TRACING -// This traces specific threads. -// -// INPUT SCHEMA -// { -// "type": , -// Tracing technology name, e.g. intel-pt, arm-etm. -// -// /* thread tracing only */ -// "tids"?: [], -// Individual threads to trace. -// -// ... other parameters specific to the provided tracing type -// } -// -// NOTES -// - If "tids" is not provided, then the operation is "process tracing", -// otherwise it's "thread tracing". -// - Each tracing technology can have different levels of support for "thread -// tracing" and "process tracing". -// -// INTEL-PT -// intel-pt supports both "thread tracing" and "process tracing". -// -// "Process tracing" is implemented in two different ways. If the -// "perCpuTracing" option is false, then each thread is traced individually -// but managed by the same "process trace" instance. This means that the -// amount of trace buffers used is proportional to the number of running -// threads. This is the recommended option unless the number of threads is -// huge. If "perCpuTracing" is true, then each cpu core is traced invidually -// instead of each thread, which uses a fixed number of trace buffers, but -// might result in less data available for less frequent threads. See -// "perCpuTracing" below for more information. -// -// Each actual intel pt trace buffer, either from "process tracing" or "thread -// tracing", is stored in an in-memory circular buffer, which keeps the most -// recent data. -// -// Additional params in the input schema: -// { -// "iptTraceSize": , -// Size in bytes used by each individual per-thread or per-cpu trace -// buffer. It must be a power of 2 greater than or equal to 4096 (2^12) -// bytes. -// -// "enableTsc": , -// Whether to enable TSC timestamps or not. This is supported on -// all devices that support intel-pt. A TSC timestamp is generated along -// with PSB (synchronization) packets, whose frequency can be configured -// with the "psbPeriod" parameter. -// -// "psbPeriod"?: , -// This value defines the period in which PSB packets will be generated. -// A PSB packet is a synchronization packet that contains a TSC -// timestamp and the current absolute instruction pointer. -// -// This parameter can only be used if -// -// /sys/bus/event_source/devices/intel_pt/caps/psb_cyc -// -// is 1. Otherwise, the PSB period will be defined by the processor. -// -// If supported, valid values for this period can be found in -/ -// /sys/bus/event_source/devices/intel_pt/caps/psb_periods -// -// which contains a hexadecimal number, whose bits represent valid -// values e.g. if bit 2 is set, then value 2 is valid. -// -// The psb_period value is converted to the approximate number of -// raw trace bytes between PSB packets as: -// -// 2 ^ (value + 11) -// -// e.g. value 3 means 16KiB between PSB packets. Defaults to -// 0 if supported. -// -// /* process tracing only */ -// "perCpuTracing": -// Instead of having an individual trace buffer per thread, this option -// triggers the collection on a per cpu core basis. This effectively -// traces the entire activity on all cores. At decoding time, in order -// to correctly associate a decoded instruction with a thread, the -// context switch trace of each core is needed, as well as a record per -// cpu indicating which thread was running on each core when tracing -// started. These secondary traces are correlated with the intel-pt -// trace by comparing TSC timestamps. -// -// This option forces the capture of TSC timestamps (see "enableTsc"). -// -// Note: This option can't be used simulatenously with any other trace -// sessions because of its system-wide nature. -// -// /* process tracing only */ -// "processBufferSizeLimit": , -// Maximum total buffer size per process in bytes. -// This limit applies to the sum of the sizes of all thread or cpu core -// buffers for the current process, excluding the ones started with -// "thread tracing". -// -// If "perCpuTracing" is false, whenever a thread is attempted to be -// traced due to "process tracing" and the limit would be reached, the -// process is stopped with a "tracing" reason along with a meaningful -// description, so that the user can retrace the process if needed. -// -// If "perCpuTracing" is true, then starting the system-wide trace -// session fails if all the individual per-cpu trace buffers require -// in total more memory that the limit impossed by this parameter. -// } -// -// Notes: -// - Modifying the parameters of an existing trace is not supported. The user -// needs to stop the trace and start a new one. -// - If "process tracing" is attempted and there are individual threads -// already being traced with "thread tracing", these traces are left -// unaffected and the threads not traced twice. -// - If "thread tracing" is attempted on a thread already being traced with -// either "thread tracing" or "process tracing", it fails. -//---------------------------------------------------------------------- - -Process tracing: -send packet: jLLDBTraceStart:{"type":,...other params}] -read packet: OK/E;AAAAAAAAA - -Thread tracing: -send packet: jLLDBTraceStart:{"type":,"tids":,...other params}] -read packet: OK/E;AAAAAAAAA - -//---------------------------------------------------------------------- -// jLLDBTraceStop -// -// BRIEF -// Stop tracing a process or its threads using a provided tracing technology. -// The input and output are specified as JSON objects. In case of success, an OK -// response is returned, or an error otherwise. -// -// PROCESS TRACE STOPPING -// Stopping a process trace stops the active traces initiated with -// "thread tracing". -// -// THREAD TRACE STOPPING -// This is a best effort request, which tries to stop as many traces as -// possible. -// -// INPUT SCHEMA -// The schema for the input is -// -// { -// "type": -// Tracing technology name, e.g. intel-pt, arm-etm. -// -// /* thread trace stopping only */ -// "tids": [] -// Individual thread traces to stop. -// } -// -// NOTES -// - If "tids" is not provided, then the operation is "process trace stopping". -// -// INTEL PT -// Stopping a specific thread trace started with "process tracing" is allowed. -//---------------------------------------------------------------------- - -Process trace stopping: -send packet: jLLDBTraceStop:{"type":}] -read packet: OK/E;AAAAAAAAA - -Thread trace stopping: -send packet: jLLDBTraceStop:{"type":,"tids":}] -read packet: OK/E;AAAAAAAAA - -//---------------------------------------------------------------------- -// jLLDBTraceGetState -// -// BRIEF -// Get the current state of the process and its threads being traced by -// a given trace technology. The response is a JSON object with custom -// information depending on the trace technology. In case of errors, an -// error message is returned. -// -// INPUT SCHEMA -// { -// "type": -// Tracing technology name, e.g. intel-pt, arm-etm. -// } -// -// OUTPUT SCHEMA -// { -// "tracedThreads": [{ -// "tid": , -// "binaryData": [ -// { -// "kind": , -// Identifier for some binary data related to this thread to -// fetch with the jLLDBTraceGetBinaryData packet. -// "size": , -// Size in bytes of this thread data. -// }, -// ] -// }], -// "processBinaryData": [ -// { -// "kind": , -// Identifier for some binary data related to this process to -// fetch with the jLLDBTraceGetBinaryData packet. -// "size": , -// Size in bytes of this thread data. -// }, -// ], -// "cpus"?: [ -// "id": , -// Identifier for this CPU logical core. -// "binaryData": [ -// { -// "kind": , -// Identifier for some binary data related to this thread to -// fetch with the jLLDBTraceGetBinaryData packet. -// "size": , -// Size in bytes of this cpu core data. -// }, -// ] -// ], -// "warnings"?: [], -// Non-fatal messages useful for troubleshooting. -// -// ... other attributes specific to the given tracing technology -// } -// -// NOTES -// - "traceThreads" includes all thread traced by both "process tracing" and -// "thread tracing". -// -// INTEL PT -// -// If per-cpu process tracing is enabled, "tracedThreads" will contain all -// the threads of the process without any trace buffers. Besides that, the -// "cpus" field will also be returned with per cpu core trace buffers. -// A side effect of per-cpu tracing is that all the threads of unrelated -// processes will also be traced, thus polluting the tracing data. -// -// Binary data kinds: -// - iptTrace: trace buffer for a thread or a cpu. -// - perfContextSwitchTrace: context switch trace for a cpu generated by -// perf_event_open. -// - procfsCpuInfo: contents of the /proc/cpuinfo file. -// -// Additional attributes: -// tscPerfZeroConversion: -// -// This field allows converting Intel processor's TSC values to nanoseconds. -// It is available through the Linux perf_event API when cap_user_time and cap_user_time_zero -// are set. -// See the documentation of time_zero in -// https://man7.org/linux/man-pages/man2/perf_event_open.2.html for more information about -// the calculation and the meaning of the values in the schema below. -/// -// Schema for this field: -// -// "tscPerfZeroConversion": { -// "timeMult": , -// "timeShift": , -// "timeZero": , -// } -//---------------------------------------------------------------------- - -send packet: jLLDBTraceGetState:{"type":}] -read packet: {...object}/E;AAAAAAAAA - -//---------------------------------------------------------------------- -// jLLDBTraceGetBinaryData -// -// BRIEF -// Get binary data given a trace technology and a data identifier. -// The input is specified as a JSON object and the response has the same format -// as the "binary memory read" (aka "x") packet. In case of failures, an error -// message is returned. -// -// SCHEMA -// The schema for the input is -// -// { -// "type": , -// Tracing technology name, e.g. intel-pt, arm-etm. -// "kind": , -// Identifier for the data. -// "cpuId": , -// Core id in decimal if the data belongs to a CPU core. -// "tid"?: , -// Tid in decimal if the data belongs to a thread. -// } -//---------------------------------------------------------------------- - -send packet: jLLDBTraceGetBinaryData:{"type":,"kind":,"tid":,"offset":,"size":}] -read packet: /E;AAAAAAAAA - -//---------------------------------------------------------------------- -// "qRegisterInfo" -// -// BRIEF -// Discover register information from the remote GDB server. -// -// PRIORITY TO IMPLEMENT -// High. Any target that can self describe its registers, should do so. -// This means if new registers are ever added to a remote target, they -// will get picked up automatically, and allows registers to change -// depending on the actual CPU type that is used. -// -// NB: qRegisterInfo is deprecated in favor of the standard gdb remote -// serial protocol register description method, -// "qXfer:features:read:target.xml". -// If qXfer:features:read:target.xml is supported, qRegisterInfo does -// not need to be implemented. The target.xml format is used by most -// gdb RSP stubs whereas qRegisterInfo was an lldb-only design. -// qRegisterInfo requires one packet per register and can have undesirable -// performance costs at the start of a debug session, whereas target.xml -// may be able to describe all registers in a single packet. -//---------------------------------------------------------------------- - -With LLDB, for register information, remote GDB servers can add -support for the "qRegisterInfoN" packet where "N" is a zero based -base 16 register number that must start at zero and increase by one -for each register that is supported. The response is done in typical -GDB remote fashion where a series of "KEY:VALUE;" pairs are returned. -An example for the x86_64 registers is included below: - -send packet: $qRegisterInfo0#00 -read packet: $name:rax;bitsize:64;offset:0;encoding:uint;format:hex;set:General Purpose Registers;gcc:0;dwarf:0;#00 -send packet: $qRegisterInfo1#00 -read packet: $name:rbx;bitsize:64;offset:8;encoding:uint;format:hex;set:General Purpose Registers;gcc:3;dwarf:3;#00 -send packet: $qRegisterInfo2#00 -read packet: $name:rcx;bitsize:64;offset:16;encoding:uint;format:hex;set:General Purpose Registers;gcc:2;dwarf:2;#00 -send packet: $qRegisterInfo3#00 -read packet: $name:rdx;bitsize:64;offset:24;encoding:uint;format:hex;set:General Purpose Registers;gcc:1;dwarf:1;#00 -send packet: $qRegisterInfo4#00 -read packet: $name:rdi;bitsize:64;offset:32;encoding:uint;format:hex;set:General Purpose Registers;gcc:5;dwarf:5;#00 -send packet: $qRegisterInfo5#00 -read packet: $name:rsi;bitsize:64;offset:40;encoding:uint;format:hex;set:General Purpose Registers;gcc:4;dwarf:4;#00 -send packet: $qRegisterInfo6#00 -read packet: $name:rbp;alt-name:fp;bitsize:64;offset:48;encoding:uint;format:hex;set:General Purpose Registers;gcc:6;dwarf:6;generic:fp;#00 -send packet: $qRegisterInfo7#00 -read packet: $name:rsp;alt-name:sp;bitsize:64;offset:56;encoding:uint;format:hex;set:General Purpose Registers;gcc:7;dwarf:7;generic:sp;#00 -send packet: $qRegisterInfo8#00 -read packet: $name:r8;bitsize:64;offset:64;encoding:uint;format:hex;set:General Purpose Registers;gcc:8;dwarf:8;#00 -send packet: $qRegisterInfo9#00 -read packet: $name:r9;bitsize:64;offset:72;encoding:uint;format:hex;set:General Purpose Registers;gcc:9;dwarf:9;#00 -send packet: $qRegisterInfoa#00 -read packet: $name:r10;bitsize:64;offset:80;encoding:uint;format:hex;set:General Purpose Registers;gcc:10;dwarf:10;#00 -send packet: $qRegisterInfob#00 -read packet: $name:r11;bitsize:64;offset:88;encoding:uint;format:hex;set:General Purpose Registers;gcc:11;dwarf:11;#00 -send packet: $qRegisterInfoc#00 -read packet: $name:r12;bitsize:64;offset:96;encoding:uint;format:hex;set:General Purpose Registers;gcc:12;dwarf:12;#00 -send packet: $qRegisterInfod#00 -read packet: $name:r13;bitsize:64;offset:104;encoding:uint;format:hex;set:General Purpose Registers;gcc:13;dwarf:13;#00 -send packet: $qRegisterInfoe#00 -read packet: $name:r14;bitsize:64;offset:112;encoding:uint;format:hex;set:General Purpose Registers;gcc:14;dwarf:14;#00 -send packet: $qRegisterInfof#00 -read packet: $name:r15;bitsize:64;offset:120;encoding:uint;format:hex;set:General Purpose Registers;gcc:15;dwarf:15;#00 -send packet: $qRegisterInfo10#00 -read packet: $name:rip;alt-name:pc;bitsize:64;offset:128;encoding:uint;format:hex;set:General Purpose Registers;gcc:16;dwarf:16;generic:pc;#00 -send packet: $qRegisterInfo11#00 -read packet: $name:rflags;alt-name:flags;bitsize:64;offset:136;encoding:uint;format:hex;set:General Purpose Registers;#00 -send packet: $qRegisterInfo12#00 -read packet: $name:cs;bitsize:64;offset:144;encoding:uint;format:hex;set:General Purpose Registers;#00 -send packet: $qRegisterInfo13#00 -read packet: $name:fs;bitsize:64;offset:152;encoding:uint;format:hex;set:General Purpose Registers;#00 -send packet: $qRegisterInfo14#00 -read packet: $name:gs;bitsize:64;offset:160;encoding:uint;format:hex;set:General Purpose Registers;#00 -send packet: $qRegisterInfo15#00 -read packet: $name:fctrl;bitsize:16;offset:176;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo16#00 -read packet: $name:fstat;bitsize:16;offset:178;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo17#00 -read packet: $name:ftag;bitsize:8;offset:180;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo18#00 -read packet: $name:fop;bitsize:16;offset:182;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo19#00 -read packet: $name:fioff;bitsize:32;offset:184;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo1a#00 -read packet: $name:fiseg;bitsize:16;offset:188;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo1b#00 -read packet: $name:fooff;bitsize:32;offset:192;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo1c#00 -read packet: $name:foseg;bitsize:16;offset:196;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo1d#00 -read packet: $name:mxcsr;bitsize:32;offset:200;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo1e#00 -read packet: $name:mxcsrmask;bitsize:32;offset:204;encoding:uint;format:hex;set:Floating Point Registers;#00 -send packet: $qRegisterInfo1f#00 -read packet: $name:stmm0;bitsize:80;offset:208;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:33;dwarf:33;#00 -send packet: $qRegisterInfo20#00 -read packet: $name:stmm1;bitsize:80;offset:224;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:34;dwarf:34;#00 -send packet: $qRegisterInfo21#00 -read packet: $name:stmm2;bitsize:80;offset:240;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:35;dwarf:35;#00 -send packet: $qRegisterInfo22#00 -read packet: $name:stmm3;bitsize:80;offset:256;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:36;dwarf:36;#00 -send packet: $qRegisterInfo23#00 -read packet: $name:stmm4;bitsize:80;offset:272;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:37;dwarf:37;#00 -send packet: $qRegisterInfo24#00 -read packet: $name:stmm5;bitsize:80;offset:288;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:38;dwarf:38;#00 -send packet: $qRegisterInfo25#00 -read packet: $name:stmm6;bitsize:80;offset:304;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:39;dwarf:39;#00 -send packet: $qRegisterInfo26#00 -read packet: $name:stmm7;bitsize:80;offset:320;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:40;dwarf:40;#00 -send packet: $qRegisterInfo27#00 -read packet: $name:xmm0;bitsize:128;offset:336;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:17;dwarf:17;#00 -send packet: $qRegisterInfo28#00 -read packet: $name:xmm1;bitsize:128;offset:352;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:18;dwarf:18;#00 -send packet: $qRegisterInfo29#00 -read packet: $name:xmm2;bitsize:128;offset:368;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:19;dwarf:19;#00 -send packet: $qRegisterInfo2a#00 -read packet: $name:xmm3;bitsize:128;offset:384;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:20;dwarf:20;#00 -send packet: $qRegisterInfo2b#00 -read packet: $name:xmm4;bitsize:128;offset:400;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:21;dwarf:21;#00 -send packet: $qRegisterInfo2c#00 -read packet: $name:xmm5;bitsize:128;offset:416;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:22;dwarf:22;#00 -send packet: $qRegisterInfo2d#00 -read packet: $name:xmm6;bitsize:128;offset:432;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:23;dwarf:23;#00 -send packet: $qRegisterInfo2e#00 -read packet: $name:xmm7;bitsize:128;offset:448;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:24;dwarf:24;#00 -send packet: $qRegisterInfo2f#00 -read packet: $name:xmm8;bitsize:128;offset:464;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:25;dwarf:25;#00 -send packet: $qRegisterInfo30#00 -read packet: $name:xmm9;bitsize:128;offset:480;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:26;dwarf:26;#00 -send packet: $qRegisterInfo31#00 -read packet: $name:xmm10;bitsize:128;offset:496;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:27;dwarf:27;#00 -send packet: $qRegisterInfo32#00 -read packet: $name:xmm11;bitsize:128;offset:512;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:28;dwarf:28;#00 -send packet: $qRegisterInfo33#00 -read packet: $name:xmm12;bitsize:128;offset:528;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:29;dwarf:29;#00 -send packet: $qRegisterInfo34#00 -read packet: $name:xmm13;bitsize:128;offset:544;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:30;dwarf:30;#00 -send packet: $qRegisterInfo35#00 -read packet: $name:xmm14;bitsize:128;offset:560;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:31;dwarf:31;#00 -send packet: $qRegisterInfo36#00 -read packet: $name:xmm15;bitsize:128;offset:576;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:32;dwarf:32;#00 -send packet: $qRegisterInfo37#00 -read packet: $name:trapno;bitsize:32;offset:696;encoding:uint;format:hex;set:Exception State Registers;#00 -send packet: $qRegisterInfo38#00 -read packet: $name:err;bitsize:32;offset:700;encoding:uint;format:hex;set:Exception State Registers;#00 -send packet: $qRegisterInfo39#00 -read packet: $name:faultvaddr;bitsize:64;offset:704;encoding:uint;format:hex;set:Exception State Registers;#00 -send packet: $qRegisterInfo3a#00 -read packet: $E45#00 - -As we see above we keep making subsequent calls to the remote server to -discover all registers by increasing the number appended to qRegisterInfo and -we get a response back that is a series of "key=value;" strings. - -The offset: fields should not leave a gap anywhere in the g/G packet -- the -register values should be appended one after another. For instance, if the -register context for a thread looks like - -struct rctx { - uint32_t gpr1; // offset 0 - uint32_t gpr2; // offset 4 - uint32_t gpr3; // offset 8 - uint64_t fp1; // offset 16 -}; - -You may end up with a 4-byte gap between gpr3 and fp1 on architectures -that align values like this. The correct offset: value for fp1 is 12 - -in the g/G packet fp1 will immediately follow gpr3, even though the -in-memory thread structure has an empty 4 bytes for alignment between -these two registers. - -The keys and values are detailed below: - -Key Value -========== ================================================================ -name The primary register name as a string ("rbp" for example) - -alt-name An alternate name for a register as a string ("fp" for example for - the above "rbp") - -bitsize Size in bits of a register (32, 64, etc). Base 10. - -offset The offset within the "g" and "G" packet of the register data for - this register. This is the byte offset once the data has been - transformed into binary, not the character offset into the g/G - packet. Base 10. - -encoding The encoding type of the register which must be one of: - - uint (unsigned integer) - sint (signed integer) - ieee754 (IEEE 754 float) - vector (vector register) - -format The preferred format for display of this register. The value must - be one of: - - binary - decimal - hex - float - vector-sint8 - vector-uint8 - vector-sint16 - vector-uint16 - vector-sint32 - vector-uint32 - vector-float32 - vector-uint128 - -set The register set name as a string that this register belongs to. - -gcc The GCC compiler registers number for this register (used for - EH frame and other compiler information that is encoded in the - executable files). The supplied number will be decoded like a - string passed to strtoul() with a base of zero, so the number - can be decimal, or hex if it is prefixed with "0x". - - NOTE: If the compiler doesn't have a register number for this - register, this key/value pair should be omitted. - -dwarf The DWARF register number for this register that is used for this - register in the debug information. The supplied number will be decoded - like a string passed to strtoul() with a base of zero, so the number - can be decimal, or hex if it is prefixed with "0x". - - NOTE: If the compiler doesn't have a register number for this - register, this key/value pair should be omitted. - -generic If the register is a generic register that most CPUs have, classify - it correctly so the debugger knows. Valid values are one of: - pc (a program counter register. for example "name=eip;" (i386), - "name=rip;" (x86_64), "name=r15;" (32 bit arm) would - include a "generic=pc;" key value pair) - sp (a stack pointer register. for example "name=esp;" (i386), - "name=rsp;" (x86_64), "name=r13;" (32 bit arm) would - include a "generic=sp;" key value pair) - fp (a frame pointer register. for example "name=ebp;" (i386), - "name=rbp;" (x86_64), "name=r7;" (32 bit arm with macosx - ABI) would include a "generic=fp;" key value pair) - ra (a return address register. for example "name=lr;" (32 bit ARM) - would include a "generic=ra;" key value pair) - flags (a CPU flags register. for example "name=eflags;" (i386), - "name=rflags;" (x86_64), "name=cpsr;" (32 bit ARM) - would include a "generic=flags;" key value pair) - arg1 - arg8 (specified for registers that contain function - arguments when the argument fits into a register) - -container-regs - The value for this key is a comma separated list of raw hex (optional - leading "0x") register numbers. - - This specifies that this register is contained in other concrete - register values. For example "eax" is in the lower 32 bits of the - "rax" register value for x86_64, so "eax" could specify that it is - contained in "rax" by specifying the register number for "rax" (whose - register number is 0x00) - - "container-regs:00;" - - If a register is comprised of one or more registers, like "d0" is ARM - which is a 64 bit register, it might be made up of "s0" and "s1". If - the register number for "s0" is 0x20, and the register number of "s1" - is "0x21", the "container-regs" key/value pair would be: - - "container-regs:20,21;" - - This is handy for defining what GDB used to call "pseudo" registers. - These registers are never requested by LLDB via the register read - or write packets, the container registers will be requested on behalf - of this register. - -invalidate-regs - The value for this key is a comma separated list of raw hex (optional - leading "0x") register numbers. - - This specifies which register values should be invalidated when this - register is modified. For example if modifying "eax" would cause "rax", - "eax", "ax", "ah", and "al" to be modified where rax is 0x0, eax is 0x15, - ax is 0x25, ah is 0x35, and al is 0x39, the "invalidate-regs" key/value - pair would be: - - "invalidate-regs:0,15,25,35,39;" - - If there is a single register that gets invalidated, then omit the comma - and just list a single register: - - "invalidate-regs:0;" - - This is handy when modifying a specific register can cause other - register values to change. For example, when debugging an ARM target, - modifying the CPSR register can cause the r8 - r14 and cpsr value to - change depending on if the mode has changed. - -//---------------------------------------------------------------------- -// "qPlatform_shell" -// -// BRIEF -// Run a command in a shell on the connected remote machine. -// -// PRIORITY TO IMPLEMENT -// High. This command allows LLDB clients to run arbitrary shell -// commands on a remote host. -// -/---------------------------------------------------------------------- - -The request consists of the command to be executed encoded in ASCII characters -converted into hex bytes. - -The response to this packet consists of the letter F followed by the return code, -followed by the signal number (or 0 if no signal was delivered), and escaped bytes -of captured program output. - -Below is an example communication from a client sending an "ls -la" command: - -send packet: $qPlatform_shell:6c73202d6c61,00000002#ec -read packet: $F,00000000,00000000,total 4736 -drwxrwxr-x 16 username groupname 4096 Aug 15 21:36 . -drwxr-xr-x 17 username groupname 4096 Aug 10 16:39 .. --rw-rw-r-- 1 username groupname 73875 Aug 12 16:46 notes.txt -drwxrwxr-x 5 username groupname 4096 Aug 15 21:36 source.cpp --rw-r--r-- 1 username groupname 2792 Aug 12 16:46 a.out --rw-r--r-- 1 username groupname 3190 Aug 12 16:46 Makefile - -//---------------------------------------------------------------------- -// "qPlatform_mkdir" -// -// BRIEF -// Creates a new directory on the connected remote machine. -// -// PRIORITY TO IMPLEMENT -// Low. This command allows LLDB clients to create new directories on -// a remote host. -// -/---------------------------------------------------------------------- - -Request: - qPlatform_mkdir:, - -Reply: - F - mkdir called successfully and returned with the given return code - Exx - An error occurred - -//---------------------------------------------------------------------- -// "qPlatform_chmod" -// -// BRIEF -// Change the permissions of a file on the connected remote machine. -// -// PRIORITY TO IMPLEMENT -// Low. This command allows LLDB clients to change the permissions of -// a file on the remote host. -// -/---------------------------------------------------------------------- - -Request: - qPlatform_chmod:, - -Reply: - F - chmod called successfully and returned with the given return code - Exx - An error occurred - -//---------------------------------------------------------------------- -// "qHostInfo" -// -// BRIEF -// Get information about the host we are remotely connected to. -// -// PRIORITY TO IMPLEMENT -// High. This packet is usually very easy to implement and can help -// LLDB select the correct plug-ins for the job based on the target -// triple information that is supplied. -//---------------------------------------------------------------------- - -LLDB supports a host info call that gets all sorts of details of the system -that is being debugged: - -send packet: $qHostInfo#00 -read packet: $cputype:16777223;cpusubtype:3;ostype:darwin;vendor:apple;endian:little;ptrsize:8;#00 - -Key value pairs are one of: - -cputype: is a number that is the mach-o CPU type that is being debugged (base 10) -cpusubtype: is a number that is the mach-o CPU subtype type that is being debugged (base 10) -triple: a string for the target triple (x86_64-apple-macosx) that can be used to specify arch + vendor + os in one entry -vendor: a string for the vendor (apple), not needed if "triple" is specified -ostype: a string for the OS being debugged (macosx, linux, freebsd, ios, watchos), not needed if "triple" is specified -endian: is one of "little", "big", or "pdp" -ptrsize: an unsigned number that represents how big pointers are in bytes on the debug target -hostname: the hostname of the host that is running the GDB server if available -os_build: a string for the OS build for the remote host as a string value -os_kernel: a string describing the kernel version -os_version: a version string that represents the current OS version (10.8.2) -watchpoint_exceptions_received: one of "before" or "after" to specify if a watchpoint is triggered before or after the pc when it stops -default_packet_timeout: an unsigned number that specifies the default timeout in seconds -distribution_id: optional. For linux, specifies distribution id (e.g. ubuntu, fedora, etc.) -osmajor: optional, specifies the major version number of the OS (e.g. for macOS 10.12.2, it would be 10) -osminor: optional, specifies the minor version number of the OS (e.g. for macOS 10.12.2, it would be 12) -ospatch: optional, specifies the patch level number of the OS (e.g. for macOS 10.12.2, it would be 2) -vm-page-size: optional, specifies the target system VM page size, base 10. - Needed for the "dirty-pages:" list in the qMemoryRegionInfo - packet, where a list of dirty pages is sent from the remote - stub. This page size tells lldb how large each dirty page is. -addressing_bits: optional, specifies how many bits in addresses are - significant for addressing, base 10. If bits 38..0 - in a 64-bit pointer are significant for addressing, - then the value is 39. This is needed on e.g. AArch64 - v8.3 ABIs that use pointer authentication, so lldb - knows which bits to clear/set to get the actual - addresses. -low_mem_addressing_bits: optional, specifies how many bits in - addresses in low memory are significant for addressing, base 10. - AArch64 can have different page table setups for low and high - memory, and therefore a different number of bits used for addressing. -high_mem_addressing_bits: optional, specifies how many bits in - addresses in high memory are significant for addressing, base 10. - AArch64 can have different page table setups for low and high - memory, and therefore a different number of bits used for addressing. - -//---------------------------------------------------------------------- -// "qGDBServerVersion" -// -// BRIEF -// Get version information about this implementation of the gdb-remote -// protocol. -// -// PRIORITY TO IMPLEMENT -// High. This packet is usually very easy to implement and can help -// LLDB to work around bugs in a server's implementation when they -// are found. -//---------------------------------------------------------------------- - -The goal of this packet is to provide enough information about an -implementation of the gdb-remote-protocol server that lldb can -work around implementation problems that are discovered after the -version has been released/deployed. The name and version number -should be sufficiently unique that lldb can unambiguously identify -the origin of the program (for instance, debugserver from lldb) and -the version/submission number/patch level of the program - whatever -is appropriate for your server implementation. - -The packet follows the key-value pair model, semicolon separated. - -send packet: $qGDBServerVersion#00 -read packet: $name:debugserver;version:310.2;#00 - -Other clients may find other key-value pairs to be useful for identifying -a gdb stub. Patch level, release name, build number may all be keys that -better describe your implementation's version. -Suggested key names: - - name : the name of your remote server - "debugserver" is the lldb standard - implementation - - version : identifies the version number of this server - - patch_level : the patch level of this server - - release_name : the name of this release, if your project uses names - - build_number : if you use a build system with increasing build numbers, - this may be the right key name for your server - - major_version : major version number - minor_version : minor version number - -//---------------------------------------------------------------------- -// "qProcessInfo" -// -// BRIEF -// Get information about the process we are currently debugging. -// -// PRIORITY TO IMPLEMENT -// Medium. On systems which can launch multiple different architecture processes, -// the qHostInfo may not disambiguate sufficiently to know what kind of -// process is being debugged. -// e.g. on a 64-bit x86 Mac system both 32-bit and 64-bit user processes are possible, -// and with Mach-O universal files, the executable file may contain both 32- and -// 64-bit slices so it may be impossible to know until you're attached to a real -// process to know what you're working with. -// -// All numeric fields return base 16 numbers without any "0x" prefix. -//---------------------------------------------------------------------- - -An i386 process: - -send packet: $qProcessInfo#00 -read packet: $pid:42a8;parent-pid:42bf;real-uid:ecf;real-gid:b;effective-uid:ecf;effective-gid:b;cputype:7;cpusubtype:3;ostype:macosx;vendor:apple;endian:little;ptrsize:4;#00 - -An x86_64 process: - -send packet: $qProcessInfo#00 -read packet: $pid:d22c;parent-pid:d34d;real-uid:ecf;real-gid:b;effective-uid:ecf;effective-gid:b;cputype:1000007;cpusubtype:3;ostype:macosx;vendor:apple;endian:little;ptrsize:8;#00 - -Key value pairs include: - -pid: the process id -parent-pid: the process of the parent process (often debugserver will become the parent when attaching) -real-uid: the real user id of the process -real-gid: the real group id of the process -effective-uid: the effective user id of the process -effective-gid: the effective group id of the process -cputype: the Mach-O CPU type of the process (base 16) -cpusubtype: the Mach-O CPU subtype of the process (base 16) -ostype: is a string the represents the OS being debugged (darwin, linux, freebsd) -vendor: is a string that represents the vendor (apple) -endian: is one of "little", "big", or "pdp" -ptrsize: is a number that represents how big pointers are in bytes - -main-binary-uuid: is the UUID of a firmware type binary that the gdb stub knows about -main-binary-address: is the load address of the firmware type binary -main-binary-slide: is the slide of the firmware type binary, if address isn't known - -binary-addresses: A comma-separated list of binary load addresses base 16. - lldb will parse the binaries in memory to get UUIDs, then - try to find the binaries & debug info by UUID. Intended for - use with a small number of firmware type binaries where the - search for binary/debug info may be expensive. - -//---------------------------------------------------------------------- -// "qShlibInfoAddr" -// -// BRIEF -// Get an address where the dynamic linker stores information about -// where shared libraries are loaded. -// -// PRIORITY TO IMPLEMENT -// High if you have a dynamic loader plug-in in LLDB for your target -// triple (see the "qHostInfo" packet) that can use this information. -// Many times address load randomization can make it hard to detect -// where the dynamic loader binary and data structures are located and -// some platforms know, or can find out where this information is. -// -// Low if you have a debug target where all object and symbol files -// contain static load addresses. -//---------------------------------------------------------------------- - -LLDB and GDB both support the "qShlibInfoAddr" packet which is a hint to each -debugger as to where to find the dynamic loader information. For darwin -binaries that run in user land this is the address of the "all_image_infos" -structure in the "/usr/lib/dyld" executable, or the result of a TASK_DYLD_INFO -call. The result is returned as big endian hex bytes that are the address -value: - -send packet: $qShlibInfoAddr#00 -read packet: $7fff5fc40040#00 - - - -//---------------------------------------------------------------------- -// "qThreadStopInfo" -// -// BRIEF -// Get information about why a thread, whose ID is "", is stopped. -// -// PRIORITY TO IMPLEMENT -// High if you need to support multi-threaded or multi-core debugging. -// Many times one thread will hit a breakpoint and while the debugger -// is in the process of suspending the other threads, other threads -// will also hit a breakpoint. This packet allows LLDB to know why all -// threads (live system debug) / cores (JTAG) in your program have -// stopped and allows LLDB to display and control your program -// correctly. -//---------------------------------------------------------------------- - -LLDB tries to use the "qThreadStopInfo" packet which is formatted as -"qThreadStopInfo%x" where %x is the hex thread ID. This requests information -about why a thread is stopped. The response is the same as the stop reply -packets and tells us what happened to the other threads. The standard GDB -remote packets love to think that there is only _one_ reason that _one_ thread -stops at a time. This allows us to see why all threads stopped and allows us -to implement better multi-threaded debugging support. - -//---------------------------------------------------------------------- -// "QThreadSuffixSupported" -// -// BRIEF -// Try to enable thread suffix support for the 'g', 'G', 'p', and 'P' -// packets. -// -// PRIORITY TO IMPLEMENT -// High. Adding a thread suffix allows us to read and write registers -// more efficiently and stops us from having to select a thread with -// one packet and then read registers with a second packet. It also -// makes sure that no errors can occur where the debugger thinks it -// already has a thread selected (see the "Hg" packet from the standard -// GDB remote protocol documentation) yet the remote GDB server actually -// has another thread selected. -//---------------------------------------------------------------------- - -When reading thread registers, you currently need to set the current -thread, then read the registers. This is kind of cumbersome, so we added the -ability to query if the remote GDB server supports adding a "thread:;" -suffix to all packets that request information for a thread. To test if the -remote GDB server supports this feature: - -send packet: $QThreadSuffixSupported#00 -read packet: OK - -If "OK" is returned, then the 'g', 'G', 'p' and 'P' packets can accept a -thread suffix. So to send a 'g' packet (read all register values): - -send packet: $g;thread:;#00 -read packet: .... - -send packet: $G;thread:;#00 -read packet: .... - -send packet: $p1a;thread:;#00 -read packet: .... - -send packet: $P1a=1234abcd;thread:;#00 -read packet: .... - - -otherwise, without this you would need to always send two packets: - -send packet: $Hg#00 -read packet: .... -send packet: $g#00 -read packet: .... - -We also added support for allocating and deallocating memory. We use this to -allocate memory so we can run JITed code. - -//---------------------------------------------------------------------- -// "_M," -// -// BRIEF -// Allocate memory on the remote target with the specified size and -// permissions. -// -// PRIORITY TO IMPLEMENT -// High if you want LLDB to be able to JIT code and run that code. JIT -// code also needs data which is also allocated and tracked. -// -// Low if you don't support running JIT'ed code. -//---------------------------------------------------------------------- - -The allocate memory packet starts with "_M,". It returns a -raw big endian address value, or "" for unimplemented, or "EXX" for an error -code. The packet is formatted as: - -char packet[256]; -int packet_len; -packet_len = ::snprintf ( - packet, - sizeof(packet), - "_M%zx,%s%s%s", - (size_t)size, - permissions & lldb::ePermissionsReadable ? "r" : "", - permissions & lldb::ePermissionsWritable ? "w" : "", - permissions & lldb::ePermissionsExecutable ? "x" : ""); - -You request a size and give the permissions. This packet does NOT need to be -implemented if you don't want to support running JITed code. The return value -is just the address of the newly allocated memory as raw big endian hex bytes. - -//---------------------------------------------------------------------- -// "_m" -// -// BRIEF -// Deallocate memory that was previously allocated using an allocate -// memory pack. -// -// PRIORITY TO IMPLEMENT -// High if you want LLDB to be able to JIT code and run that code. JIT -// code also needs data which is also allocated and tracked. -// -// Low if you don't support running JIT'ed code. -//---------------------------------------------------------------------- - -The deallocate memory packet is "_m" where you pass in the address you -got back from a previous call to the allocate memory packet. It returns "OK" -if the memory was successfully deallocated, or "EXX" for an error, or "" if -not supported. - -//---------------------------------------------------------------------- -// "qMemoryRegionInfo:" -// -// BRIEF -// Get information about the address range that contains "" -// -// PRIORITY TO IMPLEMENT -// Medium. This is nice to have, but it isn't necessary. It helps LLDB -// do stack unwinding when we branch into memory that isn't executable. -// If we can detect that the code we are stopped in isn't executable, -// then we can recover registers for stack frames above the current -// frame. Otherwise we must assume we are in some JIT'ed code (not JIT -// code that LLDB has made) and assume that no registers are available -// in higher stack frames. -//---------------------------------------------------------------------- - -We added a way to get information for a memory region. The packet is: - - qMemoryRegionInfo: - -Where is a big endian hex address. The response is returned in a series -of tuples like the data returned in a stop reply packet. The currently valid -tuples to return are: - - start:; // is a big endian hex address that is - // the start address of the range that contains - - size:; // is a big endian hex byte size of the address - // of the range that contains - - permissions:; // is a string that contains one - // or more of the characters from "rwx" - - name:; // is a hex encoded string that contains the name of - // the memory region mapped at the given address. In case of - // regions backed by a file it have to be the absolute path of - // the file while for anonymous regions it have to be the name - // associated to the region if that is available. - - flags:; // where is a space separated string - // of flag names. Currently the only supported flag - // is "mt" for AArch64 memory tagging. lldb will - // ignore any other flags in this field. - - type:[][,]; // memory types that apply to this region, e.g. - // "stack" for stack memory. - - error:; // where is - // a hex encoded string value that - // contains an error string - - dirty-pages:[][, -// QRestoreRegisterState:;thread:XXXX; -// -// BRIEF -// The QRestoreRegisterState packet tells the remote debugserver to -// restore all registers using the "save_id" which is an unsigned -// integer that was returned from a previous call to -// QSaveRegisterState. The restoration process can only be done once -// as the data backing the register state will be freed upon the -// completion of the QRestoreRegisterState command. -// -// If thread suffixes are enabled the second form of this packet is -// used, otherwise the first form is used. -// -// RESPONSE -// "OK" - if all registers were successfully restored -// "EXX" - for any errors -// -// PRIORITY TO IMPLEMENT -// Low, this is mostly a convenience packet to avoid having to send all -// registers via a g packet. It should only be implemented if support -// for the QSaveRegisterState is added. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// qFileLoadAddress: -// -// BRIEF -// Get the load address of a memory mapped file. -// The load address is defined as the address of the first memory -// region what contains data mapped from the specified file. -// -// RESPONSE -// - Load address of the file in big endian encoding -// "E01" - the requested file isn't loaded -// "EXX" - for any other errors -// -// PRIORITY TO IMPLEMENT -// Low, required if dynamic linker don't fill in the load address of -// some object file in the rendezvous data structure. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// qModuleInfo:; -// -// BRIEF -// Get information for a module by given module path and architecture. -// -// RESPONSE -// "(uuid|md5):...;triple:...;file_offset:...;file_size...;" -// "EXX" - for any errors -// -// PRIORITY TO IMPLEMENT -// Optional, required if dynamic loader cannot fetch module's information like -// UUID directly from inferior's memory. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// jModulesInfo:[{"file":"...",triple:"..."}, ...] -// -// BRIEF -// Get information for a list of modules by given module path and -// architecture. -// -// RESPONSE -// A JSON array of dictionaries containing the following keys: uuid, -// triple, file_path, file_offset, file_size. The meaning of the fields -// is the same as in the qModuleInfo packet. The server signals the -// failure to retrieve the module info for a file by ommiting the -// corresponding array entry from the response. The server may also -// include entries the client did not ask for, if it has reason to -// the modules will be interesting to the client. -// -// PRIORITY TO IMPLEMENT -// Optional. If not implemented, qModuleInfo packet will be used, which -// may be slower if the target contains a large number of modules and -// the communication link has a non-negligible latency. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// Stop reply packet extensions -// -// BRIEF -// This section describes some of the additional information you can -// specify in stop reply packets that help LLDB to know more detailed -// information about your threads. -// -// DESCRIPTION -// Standard GDB remote stop reply packets are reply packets sent in -// response to a packet that made the program run. They come in the -// following forms: -// -// "SAA" -// "S" means signal and "AA" is a hex signal number that describes why -// the thread or stopped. It doesn't specify which thread, so the "T" -// packet is recommended to use instead of the "S" packet. -// -// "TAAkey1:value1;key2:value2;..." -// "T" means a thread stopped due to a unix signal where "AA" is a hex -// signal number that describes why the program stopped. This is -// followed by a series of key/value pairs: -// - If key is a hex number, it is a register number and value is -// the hex value of the register in debuggee endian byte order. -// - If key == "thread", then the value is the big endian hex -// thread-id of the stopped thread. -// - If key == "core", then value is a hex number of the core on -// which the stop was detected. -// - If key == "watch" or key == "rwatch" or key == "awatch", then -// value is the data address in big endian hex -// - If key == "library", then value is ignore and "qXfer:libraries:read" -// packets should be used to detect any newly loaded shared libraries -// -// "WAA" -// "W" means the process exited and "AA" is the exit status. -// -// "XAA" -// "X" means the process exited and "AA" is signal that caused the program -// to exit. -// -// "O" -// "O" means STDOUT has data that was written to its console and is -// being delivered to the debugger. This packet happens asynchronously -// and the debugger is expected to continue to wait for another stop reply -// packet. -// -// LLDB EXTENSIONS -// -// We have extended the "T" packet to be able to also understand the -// following keys and values: -// -// KEY VALUE DESCRIPTION -// =========== ======== ================================================ -// "metype" unsigned mach exception type (the value of the EXC_XXX enumerations) -// as an unsigned integer. For targets with mach -// kernels only. -// -// "mecount" unsigned mach exception data count as an unsigned integer -// For targets with mach kernels only. -// -// "medata" unsigned There should be "mecount" of these and it is the data -// that goes along with a mach exception (as an unsigned -// integer). For targets with mach kernels only. -// -// "name" string The name of the thread as a plain string. The string -// must not contain an special packet characters or -// contain a ':' or a ';'. Use "hexname" if the thread -// name has special characters. -// -// "hexname" ascii-hex An ASCII hex string that contains the name of the thread -// -// "qaddr" hex Big endian hex value that contains the libdispatch -// queue address for the queue of the thread. -// -// "reason" enum The enumeration must be one of: -// "trace" the program stopped after a single instruction -// was executed on a core. Usually done when single -// stepping past a breakpoint -// "breakpoint" a breakpoint set using a 'z' packet was hit. -// "trap" stopped due to user interruption -// "signal" stopped due to an actual unix signal, not -// just the debugger using a unix signal to keep -// the GDB remote client happy. -// "watchpoint". Can be used with of the -// "watch"/"rwatch"/"awatch" key value pairs. -// Or can be used *instead* of those keys, -// with the specially formatted "description" field. -// "exception" an exception stop reason. Use with -// the "description" key/value pair to describe the -// exceptional event the user should see as the stop -// reason. -// "description" ascii-hex An ASCII hex string that contains a more descriptive -// reason that the thread stopped. This is only needed -// if none of the key/value pairs are enough to -// describe why something stopped. -// -// For "reason:watchpoint", "description" is an ascii-hex -// encoded string with between one and three base 10 numbers, -// space separated. The three numbers are -// 1. watchpoint address. This address should always be within -// a memory region lldb has a watchpoint on. -// On architectures where the actual reported hit address may -// be outside the watchpoint that was triggered, the remote -// stub should determine which watchpoint was triggered and -// report an address from within its range. -// 2. watchpoint hardware register index number. -// 3. actual watchpoint trap address, which may be outside -// the range of any watched region of memory. On MIPS, an addr -// outside a watched range means lldb should disable the wp, -// step, re-enable the wp and continue silently. -// -// On MIPS, the low 3 bits are masked so if a watchpoint is on -// 0x1004, a 2-byte write to 0x1000 will trigger the watchpoint -// (a false positive hit), and lldb needs to disable the -// watchpoint at 0x1004, inst-step, then re-enable the watchpoint -// and not make this a user visible event. The description here -// would be "0x1004 0 0x1000". lldb needs a known watchpoint address -// in the first field, so it can disable it & step. -// -// On AArch64 we have a related issue, where you watch 4 bytes at -// 0x1004, an instruction does an 8-byte write starting at -// 0x1000 (a true watchpoint hit) and the hardware may report the -// trap address as 0x1000 - before the watched memory region - -// with the write extending into the watched region. This can -// be reported as "0x1004 0 0x1000". lldb will use 0x1004 to -// identify which Watchpoint was triggered, and can report 0x1000 -// to the user. The behavior of silently stepping over the -// watchpoint, with an 3rd field addr outside the range, is -// restricted to MIPS. -// There may be false-positive watchpoint hits on AArch64 as well, -// in the SVE Streaming Mode, but that is less common (see ESR -// register flag "WPF", "Watchpoint might be False-Positive") and -// not currently handled by lldb. -// -// "threads" comma-sep-base16 A list of thread ids for all threads (including -// the thread that we're reporting as stopped) that -// are live in the process right now. lldb may -// request that this be included in the T packet via -// the QListThreadsInStopReply packet earlier in -// the debug session. -// -// Example: -// threads:63387,633b2,63424,63462,63486; -// -// "thread-pcs" comma-sep-base16 A list of pc values for all threads that currently -// exist in the process, including the thread that -// this T packet is reporting as stopped. -// This key-value pair will only be emitted when the -// "threads" key is already included in the T packet. -// The pc values correspond to the threads reported -// in the "threads" list. The number of pcs in the -// "thread-pcs" list will be the same as the number of -// threads in the "threads" list. -// lldb may request that this be included in the T -// packet via the QListThreadsInStopReply packet -// earlier in the debug session. -// -// Example: -// thread-pcs:dec14,2cf872b0,2cf8681c,2d02d68c,2cf716a8; -// -// "addressing_bits" unsigned optional Specifies how many bits in addresses -// are significant for addressing, base -// 10. If bits 38..0 in a 64-bit -// pointer are significant for -// addressing, then the value is 39. -// This is needed on e.g. AArch64 -// v8.3 ABIs that use pointer -// authentication in the high bits. -// This value is normally sent in the -// qHostInfo packet response, and if the -// value cannot change during the process -// lifetime, it does not need to be -// duplicated here in the stop packet. -// For a firmware environment with early -// start code that may be changing the -// page table setup, a dynamically set -// value may be needed. -// "low_mem_addressing_bits" unsigned optional, specifies how many bits in -// addresses in low memory are significant -// for addressing, base 10. AArch64 can -// have different page table setups for low -// and high memory, and therefore a different -// number of bits used for addressing. -// "high_mem_addressing_bits" unsigned optional, specifies how many bits in -// addresses in high memory are significant -// for addressing, base 10. AArch64 can have -// different page table setups for low and -// high memory, and therefore a different -// number of bits used for addressing. -// -// BEST PRACTICES: -// Since register values can be supplied with this packet, it is often useful -// to return the PC, SP, FP, LR (if any), and FLAGS registers so that separate -// packets don't need to be sent to read each of these registers from each -// thread. -// -// If a thread is stopped for no reason (like just because another thread -// stopped, or because when one core stops all cores should stop), use a -// "T" packet with "00" as the signal number and fill in as many key values -// and registers as possible. -// -// LLDB likes to know why a thread stopped since many thread control -// operations like stepping over a source line, actually are implemented -// by running the process multiple times. If a breakpoint is hit while -// trying to step over a source line and LLDB finds out that a breakpoint -// is hit in the "reason", we will know to stop trying to do the step -// over because something happened that should stop us from trying to -// do the step. If we are at a breakpoint and we disable the breakpoint -// at the current PC and do an instruction single step, knowing that -// we stopped due to a "trace" helps us know that we can continue -// running versus stopping due to a "breakpoint" (if we have two -// breakpoint instruction on consecutive instructions). So the more info -// we can get about the reason a thread stops, the better job LLDB can -// do when controlling your process. A typical GDB server behavior is -// to send a SIGTRAP for breakpoints _and_ also when instruction single -// stepping, in this case the debugger doesn't really know why we -// stopped and it can make it hard for the debugger to control your -// program correctly. What if a real SIGTRAP was delivered to a thread -// while we were trying to single step? We wouldn't know the difference -// with a standard GDB remote server and we could do the wrong thing. -// -// PRIORITY TO IMPLEMENT -// High. Having the extra information in your stop reply packets makes -// your debug session more reliable and informative. -//---------------------------------------------------------------------- - - -//---------------------------------------------------------------------- -// PLATFORM EXTENSION - for use as a GDB remote platform -//---------------------------------------------------------------------- -// "qfProcessInfo" -// "qsProcessInfo" -// -// BRIEF -// Get the first process info (qfProcessInfo) or subsequent process -// info (qsProcessInfo) for one or more processes on the remote -// platform. The first call gets the first match and subsequent calls -// to qsProcessInfo gets the subsequent matches. Return an error EXX, -// where XX are two hex digits, when no more matches are available. -// -// PRIORITY TO IMPLEMENT -// Required. The qfProcessInfo packet can be followed by a ':' and -// some key value pairs. The key value pairs in the command are: -// -// KEY VALUE DESCRIPTION -// =========== ======== ================================================ -// "name" ascii-hex An ASCII hex string that contains the name of -// the process that will be matched. -// "name_match" enum One of: "equals", "starts_with", "ends_with", -// "contains" or "regex" -// "pid" integer A string value containing the decimal process ID -// "parent_pid" integer A string value containing the decimal parent -// process ID -// "uid" integer A string value containing the decimal user ID -// "gid" integer A string value containing the decimal group ID -// "euid" integer A string value containing the decimal effective user ID -// "egid" integer A string value containing the decimal effective group ID -// "all_users" bool A boolean value that specifies if processes should -// be listed for all users, not just the user that the -// platform is running as -// "triple" string An ASCII triple string ("x86_64", -// "x86_64-apple-macosx", "armv7-apple-ios") -// "args" string A string value containing the process arguments -// separated by the character '-', where each argument is -// hex-encoded. It includes argv[0]. -// -// The response consists of key/value pairs where the key is separated from the -// values with colons and each pair is terminated with a semi colon. For a list -// of the key/value pairs in the response see the "qProcessInfoPID" packet -// documentation. -// -// Sample packet/response: -// send packet: $qfProcessInfo#00 -// read packet: $pid:60001;ppid:59948;uid:7746;gid:11;euid:7746;egid:11;name:6c6c6462;triple:x86_64-apple-macosx;#00 -// send packet: $qsProcessInfo#00 -// read packet: $pid:59992;ppid:192;uid:7746;gid:11;euid:7746;egid:11;name:6d64776f726b6572;triple:x86_64-apple-macosx;#00 -// send packet: $qsProcessInfo#00 -// read packet: $E04#00 -//---------------------------------------------------------------------- - - -//---------------------------------------------------------------------- -// PLATFORM EXTENSION - for use as a GDB remote platform -//---------------------------------------------------------------------- -// "qLaunchGDBServer" -// -// BRIEF -// Have the remote platform launch a GDB server. -// -// PRIORITY TO IMPLEMENT -// Required. The qLaunchGDBServer packet must be followed by a ':' and -// some key value pairs. The key value pairs in the command are: -// -// KEY VALUE DESCRIPTION -// =========== ======== ================================================ -// "port" integer A string value containing the decimal port ID or -// zero if the port should be bound and returned -// -// "host" integer The host that connections should be limited to -// when the GDB server is connected to. -// -// The response consists of key/value pairs where the key is separated from the -// values with colons and each pair is terminated with a semi colon. -// -// Sample packet/response: -// send packet: $qLaunchGDBServer:port:0;host:lldb.apple.com;#00 -// read packet: $pid:60025;port:50776;#00 -// -// The "pid" key/value pair is only specified if the remote platform launched -// a separate process for the GDB remote server and can be omitted if no -// process was separately launched. -// -// The "port" key/value pair in the response lets clients know what port number -// to attach to in case zero was specified as the "port" in the sent command. -//---------------------------------------------------------------------- - - -//---------------------------------------------------------------------- -// PLATFORM EXTENSION - for use as a GDB remote platform -//---------------------------------------------------------------------- -// "qProcessInfoPID:PID" -// -// BRIEF -// Have the remote platform get detailed information on a process by -// ID. PID is specified as a decimal integer. -// -// PRIORITY TO IMPLEMENT -// Optional. -// -// The response consists of key/value pairs where the key is separated from the -// values with colons and each pair is terminated with a semi colon. -// -// The key value pairs in the response are: -// -// KEY VALUE DESCRIPTION -// =========== ======== ================================================ -// "pid" integer Process ID as a decimal integer string -// "ppid" integer Parent process ID as a decimal integer string -// "uid" integer A string value containing the decimal user ID -// "gid" integer A string value containing the decimal group ID -// "euid" integer A string value containing the decimal effective user ID -// "egid" integer A string value containing the decimal effective group ID -// "name" ascii-hex An ASCII hex string that contains the name of the process -// "triple" string A target triple ("x86_64-apple-macosx", "armv7-apple-ios") -// -// Sample packet/response: -// send packet: $qProcessInfoPID:60050#00 -// read packet: $pid:60050;ppid:59948;uid:7746;gid:11;euid:7746;egid:11;name:6c6c6462;triple:x86_64-apple-macosx;#00 -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "vAttachName" -// -// BRIEF -// Same as vAttach, except instead of a "pid" you send a process name. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed for "process attach -n". If the packet isn't supported -// then "process attach -n" will fail gracefully. So you need only to support -// it if attaching to a process by name makes sense for your environment. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "vAttachWait" -// -// BRIEF -// Same as vAttachName, except that the stub should wait for the next instance -// of a process by that name to be launched and attach to that. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed to support "process attach -w -n" which will fail -// gracefully if the packet is not supported. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "qAttachOrWaitSupported" -// -// BRIEF -// This is a binary "is it supported" query. Return OK if you support -// vAttachOrWait -// -// PRIORITY TO IMPLEMENT -// Low. This is required if you support vAttachOrWait, otherwise no support -// is needed since the standard "I don't recognize this packet" response -// will do the right thing. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "vAttachOrWait" -// -// BRIEF -// Same as vAttachWait, except that the stub will attach to a process -// by name if it exists, and if it does not, it will wait for a process -// of that name to appear and attach to it. -// -// PRIORITY TO IMPLEMENT -// Low. Only needed to implement "process attach -w -i false -n". If -// you don't implement it but do implement -n AND lldb can somehow get -// a process list from your device, it will fall back on scanning the -// process list, and sending vAttach or vAttachWait depending on -// whether the requested process exists already. This is racy, -// however, so if you want to support this behavior it is better to -// support this packet. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "jThreadExtendedInfo" -// -// BRIEF -// This packet, which takes its arguments as JSON and sends its reply as -// JSON, allows the gdb remote stub to provide additional information -// about a given thread. -// -// PRIORITY TO IMPLEMENT -// Low. This packet is only needed if the gdb remote stub wants to -// provide interesting additional information about a thread for the -// user. -// -// This packet takes its arguments in JSON form ( http://www.json.org ). -// At a minimum, a thread must be specified, for example: -// -// jThreadExtendedInfo:{"thread":612910} -// -// Because this is a JSON string, the thread number is provided in base 10. -// Additional key-value pairs may be provided by lldb to the gdb remote -// stub. For instance, on some versions of macOS, lldb can read offset -// information out of the system libraries. Using those offsets, debugserver -// is able to find the Thread Specific Address (TSD) for a thread and include -// that in the return information. So lldb will send these additional fields -// like so: -// -// jThreadExtendedInfo:{"plo_pthread_tsd_base_address_offset":0,"plo_pthread_tsd_base_offset":224,"plo_pthread_tsd_entry_size":8,"thread":612910} -// -// There are no requirements for what is included in the response. A simple -// reply on a OS X Yosemite / iOS 8 may include the pthread_t value, the -// Thread Specific Data (TSD) address, the dispatch_queue_t value if the thread -// is associated with a GCD queue, and the requested Quality of Service (QoS) -// information about that thread. For instance, a reply may look like: -// -// {"tsd_address":4371349728,"requested_qos":{"enum_value":33,"constant_name":"QOS_CLASS_USER_INTERACTIVE","printable_name":"User Interactive"},"pthread_t":4371349504,"dispatch_queue_t":140735087127872} -// -// tsd_address, pthread_t, and dispatch_queue_t are all simple key-value pairs. -// The JSON standard requires that numbers be expressed in base 10 - so all of -// these are. requested_qos is a dictionary with three key-value pairs in it - -// so the UI layer may choose the form most appropriate for displaying to the user. -// -// Sending JSON over gdb-remote protocol introduces some problems. We may be -// sending strings with arbitrary contents in them, including the '#', '$', and '*' -// characters that have special meaning in gdb-remote protocol and cannot occur -// in the middle of the string. The standard solution for this would be to require -// ascii-hex encoding of all strings, or ascii-hex encode the entire JSON payload. -// -// Instead, the binary escaping convention is used for JSON data. This convention -// (e.g. used for the X packet) says that if '#', '$', '*', or '}' are to occur in -// the payload, the character '}' (0x7d) is emitted, then the metacharacter is emitted -// xor'ed by 0x20. The '}' character occurs in every JSON payload at least once, and -// '}' ^ 0x20 happens to be ']' so the raw packet characters for a request will look -// like -// -// jThreadExtendedInfo:{"thread":612910}] -// -// on the wire. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "QEnableCompression" -// -// BRIEF -// This packet enables compression of the packets that the debug stub sends to lldb. -// If the debug stub can support compression, it indictes this in the reply of the -// "qSupported" packet. e.g. -// LLDB SENDS: qSupported:xmlRegisters=i386,arm,mips -// STUB REPLIES: qXfer:features:read+;SupportedCompressions=lzfse,zlib-deflate,lz4,lzma; -// -// If lldb knows how to use any of these compression algorithms, it can ask that this -// compression mode be enabled. -// -// QEnableCompression:type:zlib-deflate; -// -// The debug stub should reply with an uncompressed "OK" packet to indicate that the -// request was accepted. All further packets the stub sends will use this compression. -// -// Packets are compressed as the last step before they are sent from the stub, and -// decompressed as the first step after they are received. The packet format in compressed -// mode becomes one of two: -// -// $N#00 -// -// $C:#00 -// -// Where "#00" is the actual checksum value if noack mode is not enabled. The checksum -// value is for the "N" or -// "C:" bytes in the packet. -// -// The size of the uncompressed payload in base 10 is provided because it will simplify -// decompression if the final buffer size needed is known ahead of time. -// -// Compression on low-latency connections is unlikely to be an improvement. Particularly -// when the debug stub and lldb are running on the same host. It should only be used -// for slow connections, and likely only for larger packets. -// -// Example compression algorithsm that may be used include -// -// zlib-deflate -// The raw DEFLATE format as described in IETF RFC 1951. With the ZLIB library, you -// can compress to this format with an initialization like -// deflateInit2 (&stream, 5, Z_DEFLATED, -15, 8, Z_DEFAULT_STRATEGY) -// and you can decompress with an initialization like -// inflateInit2 (&stream, -15) -// -// lz4 -// https://en.wikipedia.org/wiki/LZ4_(compression_algorithm) -// https://github.com/Cyan4973/lz4 -// The libcompression APIs on darwin systems call this COMPRESSION_LZ4_RAW. -// -// lzfse -// Compression algorithm added in macOS 10.11, with open source C reference -// implementation on github. -// https://en.wikipedia.org/wiki/LZFSE -// https://github.com/lzfse/lzfse -// -// lzma -// libcompression implements "LZMA level 6", the default compression for the -// open source LZMA implementation. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "jGetLoadedDynamicLibrariesInfos" -// -// BRIEF -// This packet asks the remote debug stub to send the details about libraries -// being added/removed from the process as a performance optimization. -// -// There are two ways this packet can be used. Both return a dictionary of -// binary images formatted the same way. -// -// One requests information on all shared libraries: -// jGetLoadedDynamicLibrariesInfos:{"fetch_all_solibs":true} -// with an optional `"report_load_commands":false` which can be added, asking -// that only the dyld SPI information (load addresses, filenames) be returned. -// The default behavior is that debugserver scans the mach-o header and load -// commands of each binary, and returns it in the JSON reply. -// -// And the second requests information about a list of shared libraries, given their load addresses: -// jGetLoadedDynamicLibrariesInfos:{"solib_addresses":[8382824135,3258302053,830202858503]} -// -// The second call is both a performance optimization (instead of having lldb read the mach-o header/load commands -// out of memory with generic read packets) but also adds additional information in the form of the -// filename of the shared libraries (which is not available in the mach-o header/load commands.) -// -// An example using the OS X 10.11 style call: -// -// LLDB SENDS: jGetLoadedDynamicLibrariesInfos:{"image_count":1,"image_list_address":140734800075128} -// STUB REPLIES: ${"images":[{"load_address":4294967296,"mod_date":0,"pathname":"/tmp/a.out","uuid":"02CF262C-ED6F-3965-9E14-63538B465CFF","mach_header":{"magic":4277009103,"cputype":16777223,"cpusubtype":18446744071562067971,"filetype":2},"segments":{"name":"__PAGEZERO","vmaddr":0,"vmsize":4294967296,"fileoff":0,"filesize":0,"maxprot":0},{"name":"__TEXT","vmaddr":4294967296,"vmsize":4096,"fileoff":0,"filesize":4096,"maxprot":7},{"name":"__LINKEDIT","vmaddr":4294971392,"vmsize":4096,"fileoff":4096,"filesize":152,"maxprot":7}}]}#00 -// -// Or pretty-printed, -// -// STUB REPLIES: ${"images": -// [ -// {"load_address":4294967296, -// "mod_date":0, -// "pathname":"/tmp/a.out", -// "uuid":"02CF262C-ED6F-3965-9E14-63538B465CFF", -// "mach_header": -// {"magic":4277009103, -// "cputype":16777223, -// "cpusubtype":18446744071562067971, -// "filetype":2 -// }, -// "segments": -// [ -// {"name":"__PAGEZERO", -// "vmaddr":0, -// "vmsize":4294967296, -// "fileoff":0, -// "filesize":0, -// "maxprot":0 -// }, -// {"name":"__TEXT", -// "vmaddr":4294967296, -// "vmsize":4096, -// "fileoff":0, -// "filesize":4096, -// "maxprot":7 -// }, -// {"name":"__LINKEDIT", -// "vmaddr":4294971392, -// "vmsize":4096, -// "fileoff":4096, -// "filesize":152, -// "maxprot":7 -// } -// ] -// } -// ] -// } -// -// -// This is similar to the qXfer:libraries:read packet, and it could -// be argued that it should be merged into that packet. A separate -// packet was created primarily because lldb needs to specify the -// number of images to be read and the address from which the initial -// information is read. Also the XML DTD would need to be extended -// quite a bit to provide all the information that the DynamicLoaderMacOSX -// would need to work correctly on this platform. -// -// PRIORITY TO IMPLEMENT -// On OS X 10.11, iOS 9, tvOS 9, watchOS 2 and older: Low. If this packet is absent, -// lldb will read the Mach-O headers/load commands out of memory. -// On macOS 10.12, iOS 10, tvOS 10, watchOS 3 and newer: High. If this packet is absent, -// lldb will not know anything about shared libraries in the inferior, or where the main -// executable loaded. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "jThreadsInfo" -// -// BRIEF -// Ask for the server for thread stop information of all threads. -// -// PRIORITY TO IMPLEMENT -// Low. This is a performance optimization, which speeds up debugging by avoiding -// multiple round-trips for retrieving thread information. The information from this -// packet can be retrieved using a combination of qThreadStopInfo and m packets. -//---------------------------------------------------------------------- - -The data in this packet is very similar to the stop reply packets, but is packaged in -JSON and uses JSON arrays where applicable. The JSON output looks like: - [ - { "tid":1580681, - "metype":6, - "medata":[2,0], - "reason":"exception", - "qaddr":140735118423168, - "registers": { - "0":"8000000000000000", - "1":"0000000000000000", - "2":"20fabf5fff7f0000", - "3":"e8f8bf5fff7f0000", - "4":"0100000000000000", - "5":"d8f8bf5fff7f0000", - "6":"b0f8bf5fff7f0000", - "7":"20f4bf5fff7f0000", - "8":"8000000000000000", - "9":"61a8db78a61500db", - "10":"3200000000000000", - "11":"4602000000000000", - "12":"0000000000000000", - "13":"0000000000000000", - "14":"0000000000000000", - "15":"0000000000000000", - "16":"960b000001000000", - "17":"0202000000000000", - "18":"2b00000000000000", - "19":"0000000000000000", - "20":"0000000000000000" - }, - "memory":[ - {"address":140734799804592,"bytes":"c8f8bf5fff7f0000c9a59e8cff7f0000"}, - {"address":140734799804616,"bytes":"00000000000000000100000000000000"} - ] - } - ] - -It contains an array of dictionaries with all of the key value pairs that are -normally in the stop reply packet, including the expedited registers. The registers are -passed as hex-encoded JSON string in debuggee-endian byte order. Note that the register -numbers are decimal numbers, unlike the stop-reply packet, where they are written in -hex. The packet also contains expedited memory in the "memory" key. This allows the -server to expedite memory that the client is likely to use (e.g., areas around the -stack pointer, which are needed for computing backtraces) and it reduces the packet -count. - -On macOS with debugserver, we expedite the frame pointer backchain for a thread -(up to 256 entries) by reading 2 pointers worth of bytes at the frame pointer (for -the previous FP and PC), and follow the backchain. Most backtraces on macOS and -iOS now don't require us to read any memory! - -//---------------------------------------------------------------------- -// "jGetSharedCacheInfo" -// -// BRIEF -// This packet asks the remote debug stub to send the details about the inferior's -// shared cache. The shared cache is a collection of common libraries/frameworks that -// are mapped into every process at the same address on Darwin systems, and can be -// identified by a load address and UUID. -// -// -// LLDB SENDS: jGetSharedCacheInfo:{} -// STUB REPLIES: ${"shared_cache_base_address":140735683125248,"shared_cache_uuid":"DDB8D70C-C9A2-3561-B2C8-BE48A4F33F96","no_shared_cache":false,"shared_cache_private_cache":false]}#00 -// -// PRIORITY TO IMPLEMENT -// Low. When both lldb and the inferior process are running on the same computer, and lldb -// and the inferior process have the same shared cache, lldb may (as an optimization) read -// the shared cache out of its own memory instead of using gdb-remote read packets to read -// them from the inferior process. -//---------------------------------------------------------------------- - -//---------------------------------------------------------------------- -// "qQueryGDBServer" -// -// BRIEF -// Ask the platform for the list of gdbservers we have to connect -// -// PRIORITY TO IMPLEMENT -// Low. The packet is required to support connecting to gdbserver started -// by the platform instance automatically. -//---------------------------------------------------------------------- - -If the remote platform automatically started one or more gdbserver instance (without -lldb asking it) then it have to return the list of port number or socket name for -each of them what can be used by lldb to connect to those instances. - -The data in this packet is a JSON array of JSON objects with the following keys: -"port": (optional) -"socket_name": (optional) - -Example packet: -[ - { "port": 1234 }, - { "port": 5432 }, - { "socket_name": "foo" } -] - -//---------------------------------------------------------------------- -// "QSetDetachOnError" -// -// BRIEF -// Sets what the server should do when the communication channel with LLDB -// goes down. Either kill the inferior process (0) or remove breakpoints and -// detach (1). -// -// PRIORITY TO IMPLEMENT -// Low. Only required if the target wants to keep the inferior process alive -// when the communication channel goes down. -//---------------------------------------------------------------------- - -The data in this packet is a single a character, which should be '0' if the -inferior process should be killed, or '1' if the server should remove all -breakpoints and detach from the inferior. - -//---------------------------------------------------------------------- -// "jGetDyldProcessState" -// -// BRIEF -// This packet fetches the process launch state, as reported by libdyld on -// Darwin systems, most importantly to indicate when the system libraries -// have initialized sufficiently to safely call utility functions. -// -// -// LLDB SENDS: jGetDyldProcessState -// STUB REPLIES: {"process_state_value":48,"process_state string":"dyld_process_state_libSystem_initialized"} -// -// PRIORITY TO IMPLEMENT -// Low. This packet is needed to prevent lldb's utility functions for -// scanning the Objective-C class list from running very early in -// process startup. -//---------------------------------------------------------------------- diff --git a/lldb/docs/resources/lldbgdbremote.md b/lldb/docs/resources/lldbgdbremote.md new file mode 100644 index 0000000000000000000000000000000000000000..cbe5c766d61eef9ef07d6365fe51eb54287a45b8 --- /dev/null +++ b/lldb/docs/resources/lldbgdbremote.md @@ -0,0 +1,2399 @@ +# GDB Remote Protocol Extensions + +LLDB has added new GDB server packets to better support multi-threaded and +remote debugging. + +Why? Normally you need to start the correct GDB and the +correct GDB server when debugging. If you have mismatch, then things go wrong +very quickly. LLDB makes extensive use of the GDB remote protocol and we +wanted to make sure that the experience was a bit more dynamic where we can +discover information about a remote target without having to know anything up +front. + +We also ran into performance issues with the existing GDB remote +protocol that can be overcome when using a reliable communications layer. + +Some packets improve performance, others allow for remote process launching +(if you have an OS), and others allow us to dynamically figure out what +registers a thread might have. Again with GDB, both sides pre-agree on how the +registers will look (how many, their register number,name and offsets). + +We prefer to be able to dynamically determine what kind of architecture, OS and +vendor we are debugging, as well as how things are laid out when it comes to +the thread register contexts. + +Below are the details on the new packets we have added above and beyond the +standard GDB remote protocol packets. + +## QStartNoAckMode + +### Brief + +Try to enable no ACK mode to skip sending ACKs and NACKs. + +### Priority To Implement + +High. Any GDB remote server that can implement this should if the +connection is reliable. This improves packet throughput and increases +the performance of the connection. + +### Description + +Having to send an ACK/NACK after every packet slows things down a bit, so we +have a way to disable ACK packets to minimize the traffic for reliable +communication interfaces (like sockets). Below GDB or LLDB will send this +packet to try and disable ACKs. All lines that start with "send packet: " are +from GDB/LLDB, and all lines that start with "read packet: " are from the GDB +remote server: +``` +send packet: $QStartNoAckMode#b0 +read packet: + +read packet: $OK#9a +send packet: + +``` + +## QSupported + +### Brief + +Query the GDB remote server for features it supports + +### Priority To Implement + +Optional. + +### Description + +QSupported is a standard GDB Remote Serial Protocol packet, but +there are several additions to the response that lldb can parse. +They are not all listed here. + +An example exchange: +``` +send packet: qSupported:xmlRegisters=i386,arm,mips,arc;multiprocess+;fork-events+;vfork-events+ + +read packet: qXfer:features:read+;PacketSize=20000;qEcho+;native-signals+;SupportedCompressions=lzfse,zlib-deflate,lz4,lzma;SupportedWatchpointTypes=aarch64-mask,aarch64-bas; +``` + +In the example above, three lldb extensions are shown: + + * `PacketSize=20000` + * The base 16 maximum packet size that the stub can handle. + * `SupportedCompressions=` + * A list of compression types that the stub can use to compress packets + when the QEnableCompression packet is used to request one of them. + * `SupportedWatchpointTypes=` + * A list of watchpoint types that this stub can manage. Currently defined + names are: + * `x86_64` - 64-bit x86-64 watchpoints (1, 2, 4, 8 byte watchpoints + aligned to those amounts) + * `aarch64-bas` AArch64 Byte Address Select watchpoints + (any number of contiguous bytes within a doubleword) + * `aarch64-mask` AArch64 MASK watchpoints + (any power-of-2 region of memory from 8 to 2GB, aligned) + + If nothing is specified, lldb will default to sending power-of-2 + watchpoints, up to a pointer size, `sizeof(void*)`, a reasonable + baseline assumption. + + +## "A" - launch args packet + +### Brief + +Launch a program using the supplied arguments + +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +### Description + +We have added support for the "set program arguments" packet where we can +start a connection to a remote server and then later supply the path to the +executable and the arguments to use when executing: + +GDB remote docs for this: +``` +set program arguments(reserved) Aarglen,argnum,arg,... +``` +Where A is followed by the length in bytes of the hex encoded argument, +followed by an argument integer, and followed by the ASCII characters +converted into hex bytes for each arg: +``` +send packet: $A98,0,2f566f6c756d65732f776f726b2f67636c6179746f6e2f446f63756d656e74732f7372632f6174746163682f612e6f7574#00 +read packet: $OK#00 +``` +The above packet helps when you have remote debugging abilities where you +could launch a process on a remote host, this isn't needed for bare board +debugging. + + +## QEnvironment:NAME=VALUE + +### Brief + +Setup the environment up for a new child process that will soon be +launched using the "A" packet. + +NB: key/value pairs are sent as-is so gdb-remote protocol meta characters +(e.g. `#` or `$`) are not acceptable. If any non-printable or +metacharacters are present in the strings, `QEnvironmentHexEncoded` +should be used instead if it is available. If you don't want to +scan the environment strings before sending, prefer +the `QEnvironmentHexEncoded` packet over `QEnvironment`, if it is +available. + +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +### Description + +Both GDB and LLDB support passing down environment variables. Is it ok to +respond with a `$#00` (unimplemented): +``` +send packet: $QEnvironment:ACK_COLOR_FILENAME=bold yellow#00 +read packet: $OK#00 +``` +This packet can be sent one or more times _prior_ to sending a "A" packet. + +## QEnvironmentHexEncoded:HEX-ENCODING(NAME=VALUE) + +### Brief + +Setup the environment up for a new child process that will soon be +launched using the "A" packet. + +The only difference between this packet and `QEnvironment` is that the +environment key-value pair is ascii hex encoded for transmission. +This allows values with gdb-remote metacharacters like `#` to be sent. + +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +### Description + +Both GDB and LLDB support passing down environment variables. Is it ok to +respond with a `$#00` (unimplemented): +``` +send packet: $QEnvironment:41434b5f434f4c4f525f46494c454e414d453d626f6c642379656c6c6f77#00 +read packet: $OK#00 +``` +This packet can be sent one or more times _prior_ to sending a "A" packet. + +## QEnableErrorStrings + +### Brief + +This packet enables reporting of Error strings in remote packet +replies from the server to client. If the server supports this +feature, it should send an OK response. The client can expect the +following error replies if this feature is enabled in the server: +``` +EXX;AAAAAAAAA +``` +where `AAAAAAAAA` will be a hex encoded ASCII string. +`XX`` is hex encoded byte number. + +It must be noted that even if the client has enabled reporting +strings in error replies, it must not expect error strings to all +error replies. + +### Priority To Implement + +Low. Only needed if the remote target wants to provide strings that +are human readable along with an error code. + +### Example + +``` +send packet: $QEnableErrorStrings +read packet: $OK#00 +``` + +## QSetSTDIN:\ / QSetSTDOUT:\ / QSetSTDERR:\ + +### Brief + +Setup where STDIN, STDOUT, and STDERR go prior to sending an "A" +packet. + +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +### Description + +When launching a program through the GDB remote protocol with the "A" packet, +you might also want to specify where stdin/out/err go: +``` +QSetSTDIN: +QSetSTDOUT: +QSetSTDERR: +``` +These packets must be sent _prior_ to sending a "A" packet. + +## QSetWorkingDir:\ + +### Brief + +Set the working directory prior to sending an "A" packet. + +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +### Description + +Or specify the working directory: +``` +QSetWorkingDir: +``` +This packet must be sent _prior_ to sending a "A" packet. + +## QSetDisableASLR:\ + +### Brief + +Enable or disable ASLR on the next "A" packet. + +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process and if the target supports disabling ASLR +(Address space layout randomization). + +### Description + +Or control if ASLR is enabled/disabled: +``` +send packet: QSetDisableASLR:1 +read packet: OK + +send packet: QSetDisableASLR:0 +read packet: OK +``` +This packet must be sent _prior_ to sending a "A" packet. + +## QListThreadsInStopReply + +### Brief + +Enable the `threads:` and `thread-pcs:` data in the question-mark packet +("T packet") responses when the stub reports that a program has +stopped executing. + +### Priority To Implement + +Performance. This is a performance benefit to lldb if the thread id's +and thread pc values are provided to lldb in the T stop packet -- if +they are not provided to lldb, lldb will likely need to send one to +two packets per thread to fetch the data at every private stop. + +### Example + +``` +send packet: QListThreadsInStopReply +read packet: OK +``` + +## jLLDBTraceSupported + +### Brief + +Get the processor tracing type supported by the gdb-server for the current +inferior. Responses might be different depending on the architecture and +capabilities of the underlying OS. + +### Output Schema + +``` + { + "name": , + Tracing technology name, e.g. intel-pt, arm-etm. + "description": , + Description for this technology. + } +``` + +If no tracing technology is supported for the inferior, or no process is +running, then an error message is returned. + +### Note + +This packet is used by Trace plug-ins (see `lldb_private::Trace.h`) to +do live tracing. Specifically, the name of the plug-in should match the name +of the tracing technology returned by this packet. + +### Example + +``` +send packet: jLLDBTraceSupported +read packet: {"name":, "description":}/E;AAAAAAAAA +``` + +## jLLDBTraceStart + +### Brief + +Start tracing a process or its threads using a provided tracing technology. +The input and output are specified as JSON objects. In case of success, an OK +response is returned, or an error otherwise. + +### Process Tracing + +This traces existing and future threads of the current process. An error is +returned if the process is already being traced. + +### Thread Tracing + +This traces specific threads. + +### Input Schema + +``` +{ + "type": , + Tracing technology name, e.g. intel-pt, arm-etm. + + /* thread tracing only */ + "tids"?: [], + Individual threads to trace. + + ... other parameters specific to the provided tracing type +} +``` + +### Notes + +- If "tids" is not provided, then the operation is "process tracing", + otherwise it's "thread tracing". +- Each tracing technology can have different levels of support for "thread + tracing" and "process tracing". + +### Intel-Pt + +intel-pt supports both "thread tracing" and "process tracing". + +"Process tracing" is implemented in two different ways. If the +"perCpuTracing" option is false, then each thread is traced individually +but managed by the same "process trace" instance. This means that the +amount of trace buffers used is proportional to the number of running +threads. This is the recommended option unless the number of threads is +huge. If "perCpuTracing" is true, then each cpu core is traced invidually +instead of each thread, which uses a fixed number of trace buffers, but +might result in less data available for less frequent threads. See +"perCpuTracing" below for more information. + +Each actual intel pt trace buffer, either from "process tracing" or "thread +tracing", is stored in an in-memory circular buffer, which keeps the most +recent data. + +Additional params in the input schema: +``` + { + "iptTraceSize": , + Size in bytes used by each individual per-thread or per-cpu trace + buffer. It must be a power of 2 greater than or equal to 4096 (2^12) + bytes. + + "enableTsc": , + Whether to enable TSC timestamps or not. This is supported on + all devices that support intel-pt. A TSC timestamp is generated along + with PSB (synchronization) packets, whose frequency can be configured + with the "psbPeriod" parameter. + + "psbPeriod"?: , + This value defines the period in which PSB packets will be generated. + A PSB packet is a synchronization packet that contains a TSC + timestamp and the current absolute instruction pointer. + + This parameter can only be used if + + /sys/bus/event_source/devices/intel_pt/caps/psb_cyc + + is 1. Otherwise, the PSB period will be defined by the processor. + + If supported, valid values for this period can be found in + + /sys/bus/event_source/devices/intel_pt/caps/psb_periods + + which contains a hexadecimal number, whose bits represent valid + values e.g. if bit 2 is set, then value 2 is valid. + + The psb_period value is converted to the approximate number of + raw trace bytes between PSB packets as: + + 2 ^ (value + 11) + + e.g. value 3 means 16KiB between PSB packets. Defaults to + 0 if supported. + + /* process tracing only */ + "perCpuTracing": + Instead of having an individual trace buffer per thread, this option + triggers the collection on a per cpu core basis. This effectively + traces the entire activity on all cores. At decoding time, in order + to correctly associate a decoded instruction with a thread, the + context switch trace of each core is needed, as well as a record per + cpu indicating which thread was running on each core when tracing + started. These secondary traces are correlated with the intel-pt + trace by comparing TSC timestamps. + + This option forces the capture of TSC timestamps (see "enableTsc"). + + Note: This option can't be used simulatenously with any other trace + sessions because of its system-wide nature. + + /* process tracing only */ + "processBufferSizeLimit": , + Maximum total buffer size per process in bytes. + This limit applies to the sum of the sizes of all thread or cpu core + buffers for the current process, excluding the ones started with + "thread tracing". + + If "perCpuTracing" is false, whenever a thread is attempted to be + traced due to "process tracing" and the limit would be reached, the + process is stopped with a "tracing" reason along with a meaningful + description, so that the user can retrace the process if needed. + + If "perCpuTracing" is true, then starting the system-wide trace + session fails if all the individual per-cpu trace buffers require + in total more memory that the limit impossed by this parameter. + } +``` + +Notes: + - Modifying the parameters of an existing trace is not supported. The user + needs to stop the trace and start a new one. + - If "process tracing" is attempted and there are individual threads + already being traced with "thread tracing", these traces are left + unaffected and the threads not traced twice. + - If "thread tracing" is attempted on a thread already being traced with + either "thread tracing" or "process tracing", it fails. + +### Examples + +Process tracing: +``` +send packet: jLLDBTraceStart:{"type":,...other params}] +read packet: OK/E;AAAAAAAAA +``` + +Thread tracing: +``` +send packet: jLLDBTraceStart:{"type":,"tids":,...other params}] +read packet: OK/E;AAAAAAAAA +``` + +## jLLDBTraceStop + +### Brief + +Stop tracing a process or its threads using a provided tracing technology. +The input and output are specified as JSON objects. In case of success, an OK +response is returned, or an error otherwise. + +### Process Trace Stopping + +Stopping a process trace stops the active traces initiated with +"thread tracing". + +### Thread Trace Stopping + +This is a best effort request, which tries to stop as many traces as +possible. + +### Input Schema + +The schema for the input is +``` +{ + "type": + Tracing technology name, e.g. intel-pt, arm-etm. + + /* thread trace stopping only */ + "tids": [] + Individual thread traces to stop. +} +``` + +### Notes + +- If "tids" is not provided, then the operation is "process trace stopping". + +### Intel Pt + +Stopping a specific thread trace started with "process tracing" is allowed. + +### Examples + +Process trace stopping: +``` +send packet: jLLDBTraceStop:{"type":}] +read packet: OK/E;AAAAAAAAA +``` +Thread trace stopping: +``` +send packet: jLLDBTraceStop:{"type":,"tids":}] +read packet: OK/E;AAAAAAAAA +``` + +## jLLDBTraceGetState + +### Brief + +Get the current state of the process and its threads being traced by +a given trace technology. The response is a JSON object with custom +information depending on the trace technology. In case of errors, an +error message is returned. + +### Input Schema + +``` +{ + "type": + Tracing technology name, e.g. intel-pt, arm-etm. +} +``` + +### Output Schema + +``` +{ + "tracedThreads": [{ + "tid": , + "binaryData": [ + { + "kind": , + Identifier for some binary data related to this thread to + fetch with the jLLDBTraceGetBinaryData packet. + "size": , + Size in bytes of this thread data. + }, + ] + }], + "processBinaryData": [ + { + "kind": , + Identifier for some binary data related to this process to + fetch with the jLLDBTraceGetBinaryData packet. + "size": , + Size in bytes of this thread data. + }, + ], + "cpus"?: [ + "id": , + Identifier for this CPU logical core. + "binaryData": [ + { + "kind": , + Identifier for some binary data related to this thread to + fetch with the jLLDBTraceGetBinaryData packet. + "size": , + Size in bytes of this cpu core data. + }, + ] + ], + "warnings"?: [], + Non-fatal messages useful for troubleshooting. + + ... other attributes specific to the given tracing technology +} +``` + +### Notes + + - "traceThreads" includes all thread traced by both "process tracing" and + "thread tracing". + +### Intel Pt + +If per-cpu process tracing is enabled, "tracedThreads" will contain all +the threads of the process without any trace buffers. Besides that, the +"cpus" field will also be returned with per cpu core trace buffers. +A side effect of per-cpu tracing is that all the threads of unrelated +processes will also be traced, thus polluting the tracing data. + +Binary data kinds: + - iptTrace: trace buffer for a thread or a cpu. + - perfContextSwitchTrace: context switch trace for a cpu generated by + perf_event_open. + - procfsCpuInfo: contents of the /proc/cpuinfo file. + +Additional attributes: + * tscPerfZeroConversion + * This field allows converting Intel processor's TSC values to nanoseconds. + It is available through the Linux perf_event API when cap_user_time and cap_user_time_zero + are set. + See the documentation of time_zero in + https://man7.org/linux/man-pages/man2/perf_event_open.2.html for more information about + the calculation and the meaning of the values in the schema below. + + Schema for this field: + ``` + "tscPerfZeroConversion": { + "timeMult": , + "timeShift": , + "timeZero": , + } + ``` + +### Example + +``` +send packet: jLLDBTraceGetState:{"type":}] +read packet: {...object}/E;AAAAAAAAA +``` + +## jLLDBTraceGetBinaryData + +### Brief + +Get binary data given a trace technology and a data identifier. +The input is specified as a JSON object and the response has the same format +as the "binary memory read" (aka "x") packet. In case of failures, an error +message is returned. + +### Schema + +The schema for the input is: +``` +{ + "type": , + Tracing technology name, e.g. intel-pt, arm-etm. + "kind": , + Identifier for the data. + "cpuId": , + Core id in decimal if the data belongs to a CPU core. + "tid"?: , + Tid in decimal if the data belongs to a thread. +} +``` + +### Example + +``` +send packet: jLLDBTraceGetBinaryData:{"type":,"kind":,"tid":,"offset":,"size":}] +read packet: /E;AAAAAAAAA +``` + +## qRegisterInfo\ + +### Brief + +Discover register information from the remote GDB server. + +### Priority To Implement + +High. Any target that can self describe its registers, should do so. +This means if new registers are ever added to a remote target, they +will get picked up automatically, and allows registers to change +depending on the actual CPU type that is used. + +NB: `qRegisterInfo` is deprecated in favor of the standard gdb remote +serial protocol register description method, +`qXfer:features:read:target.xml`. +If `qXfer:features:read:target.xml` is supported, `qRegisterInfo` does +not need to be implemented. The target.xml format is used by most +gdb RSP stubs whereas `qRegisterInfo` was an lldb-only design. +`qRegisterInfo` requires one packet per register and can have undesirable +performance costs at the start of a debug session, whereas target.xml +may be able to describe all registers in a single packet. + +### Description + +With LLDB, for register information, remote GDB servers can add +support for the "qRegisterInfoN" packet where "N" is a zero based +base 16 register number that must start at zero and increase by one +for each register that is supported. The response is done in typical +GDB remote fashion where a series of "KEY:VALUE;" pairs are returned. +An example for the x86_64 registers is included below: +``` +send packet: $qRegisterInfo0#00 +read packet: $name:rax;bitsize:64;offset:0;encoding:uint;format:hex;set:General Purpose Registers;gcc:0;dwarf:0;#00 +send packet: $qRegisterInfo1#00 +read packet: $name:rbx;bitsize:64;offset:8;encoding:uint;format:hex;set:General Purpose Registers;gcc:3;dwarf:3;#00 +send packet: $qRegisterInfo2#00 +read packet: $name:rcx;bitsize:64;offset:16;encoding:uint;format:hex;set:General Purpose Registers;gcc:2;dwarf:2;#00 +send packet: $qRegisterInfo3#00 +read packet: $name:rdx;bitsize:64;offset:24;encoding:uint;format:hex;set:General Purpose Registers;gcc:1;dwarf:1;#00 +send packet: $qRegisterInfo4#00 +read packet: $name:rdi;bitsize:64;offset:32;encoding:uint;format:hex;set:General Purpose Registers;gcc:5;dwarf:5;#00 +send packet: $qRegisterInfo5#00 +read packet: $name:rsi;bitsize:64;offset:40;encoding:uint;format:hex;set:General Purpose Registers;gcc:4;dwarf:4;#00 +send packet: $qRegisterInfo6#00 +read packet: $name:rbp;alt-name:fp;bitsize:64;offset:48;encoding:uint;format:hex;set:General Purpose Registers;gcc:6;dwarf:6;generic:fp;#00 +send packet: $qRegisterInfo7#00 +read packet: $name:rsp;alt-name:sp;bitsize:64;offset:56;encoding:uint;format:hex;set:General Purpose Registers;gcc:7;dwarf:7;generic:sp;#00 +send packet: $qRegisterInfo8#00 +read packet: $name:r8;bitsize:64;offset:64;encoding:uint;format:hex;set:General Purpose Registers;gcc:8;dwarf:8;#00 +send packet: $qRegisterInfo9#00 +read packet: $name:r9;bitsize:64;offset:72;encoding:uint;format:hex;set:General Purpose Registers;gcc:9;dwarf:9;#00 +send packet: $qRegisterInfoa#00 +read packet: $name:r10;bitsize:64;offset:80;encoding:uint;format:hex;set:General Purpose Registers;gcc:10;dwarf:10;#00 +send packet: $qRegisterInfob#00 +read packet: $name:r11;bitsize:64;offset:88;encoding:uint;format:hex;set:General Purpose Registers;gcc:11;dwarf:11;#00 +send packet: $qRegisterInfoc#00 +read packet: $name:r12;bitsize:64;offset:96;encoding:uint;format:hex;set:General Purpose Registers;gcc:12;dwarf:12;#00 +send packet: $qRegisterInfod#00 +read packet: $name:r13;bitsize:64;offset:104;encoding:uint;format:hex;set:General Purpose Registers;gcc:13;dwarf:13;#00 +send packet: $qRegisterInfoe#00 +read packet: $name:r14;bitsize:64;offset:112;encoding:uint;format:hex;set:General Purpose Registers;gcc:14;dwarf:14;#00 +send packet: $qRegisterInfof#00 +read packet: $name:r15;bitsize:64;offset:120;encoding:uint;format:hex;set:General Purpose Registers;gcc:15;dwarf:15;#00 +send packet: $qRegisterInfo10#00 +read packet: $name:rip;alt-name:pc;bitsize:64;offset:128;encoding:uint;format:hex;set:General Purpose Registers;gcc:16;dwarf:16;generic:pc;#00 +send packet: $qRegisterInfo11#00 +read packet: $name:rflags;alt-name:flags;bitsize:64;offset:136;encoding:uint;format:hex;set:General Purpose Registers;#00 +send packet: $qRegisterInfo12#00 +read packet: $name:cs;bitsize:64;offset:144;encoding:uint;format:hex;set:General Purpose Registers;#00 +send packet: $qRegisterInfo13#00 +read packet: $name:fs;bitsize:64;offset:152;encoding:uint;format:hex;set:General Purpose Registers;#00 +send packet: $qRegisterInfo14#00 +read packet: $name:gs;bitsize:64;offset:160;encoding:uint;format:hex;set:General Purpose Registers;#00 +send packet: $qRegisterInfo15#00 +read packet: $name:fctrl;bitsize:16;offset:176;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo16#00 +read packet: $name:fstat;bitsize:16;offset:178;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo17#00 +read packet: $name:ftag;bitsize:8;offset:180;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo18#00 +read packet: $name:fop;bitsize:16;offset:182;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo19#00 +read packet: $name:fioff;bitsize:32;offset:184;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo1a#00 +read packet: $name:fiseg;bitsize:16;offset:188;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo1b#00 +read packet: $name:fooff;bitsize:32;offset:192;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo1c#00 +read packet: $name:foseg;bitsize:16;offset:196;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo1d#00 +read packet: $name:mxcsr;bitsize:32;offset:200;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo1e#00 +read packet: $name:mxcsrmask;bitsize:32;offset:204;encoding:uint;format:hex;set:Floating Point Registers;#00 +send packet: $qRegisterInfo1f#00 +read packet: $name:stmm0;bitsize:80;offset:208;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:33;dwarf:33;#00 +send packet: $qRegisterInfo20#00 +read packet: $name:stmm1;bitsize:80;offset:224;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:34;dwarf:34;#00 +send packet: $qRegisterInfo21#00 +read packet: $name:stmm2;bitsize:80;offset:240;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:35;dwarf:35;#00 +send packet: $qRegisterInfo22#00 +read packet: $name:stmm3;bitsize:80;offset:256;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:36;dwarf:36;#00 +send packet: $qRegisterInfo23#00 +read packet: $name:stmm4;bitsize:80;offset:272;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:37;dwarf:37;#00 +send packet: $qRegisterInfo24#00 +read packet: $name:stmm5;bitsize:80;offset:288;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:38;dwarf:38;#00 +send packet: $qRegisterInfo25#00 +read packet: $name:stmm6;bitsize:80;offset:304;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:39;dwarf:39;#00 +send packet: $qRegisterInfo26#00 +read packet: $name:stmm7;bitsize:80;offset:320;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:40;dwarf:40;#00 +send packet: $qRegisterInfo27#00 +read packet: $name:xmm0;bitsize:128;offset:336;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:17;dwarf:17;#00 +send packet: $qRegisterInfo28#00 +read packet: $name:xmm1;bitsize:128;offset:352;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:18;dwarf:18;#00 +send packet: $qRegisterInfo29#00 +read packet: $name:xmm2;bitsize:128;offset:368;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:19;dwarf:19;#00 +send packet: $qRegisterInfo2a#00 +read packet: $name:xmm3;bitsize:128;offset:384;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:20;dwarf:20;#00 +send packet: $qRegisterInfo2b#00 +read packet: $name:xmm4;bitsize:128;offset:400;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:21;dwarf:21;#00 +send packet: $qRegisterInfo2c#00 +read packet: $name:xmm5;bitsize:128;offset:416;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:22;dwarf:22;#00 +send packet: $qRegisterInfo2d#00 +read packet: $name:xmm6;bitsize:128;offset:432;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:23;dwarf:23;#00 +send packet: $qRegisterInfo2e#00 +read packet: $name:xmm7;bitsize:128;offset:448;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:24;dwarf:24;#00 +send packet: $qRegisterInfo2f#00 +read packet: $name:xmm8;bitsize:128;offset:464;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:25;dwarf:25;#00 +send packet: $qRegisterInfo30#00 +read packet: $name:xmm9;bitsize:128;offset:480;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:26;dwarf:26;#00 +send packet: $qRegisterInfo31#00 +read packet: $name:xmm10;bitsize:128;offset:496;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:27;dwarf:27;#00 +send packet: $qRegisterInfo32#00 +read packet: $name:xmm11;bitsize:128;offset:512;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:28;dwarf:28;#00 +send packet: $qRegisterInfo33#00 +read packet: $name:xmm12;bitsize:128;offset:528;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:29;dwarf:29;#00 +send packet: $qRegisterInfo34#00 +read packet: $name:xmm13;bitsize:128;offset:544;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:30;dwarf:30;#00 +send packet: $qRegisterInfo35#00 +read packet: $name:xmm14;bitsize:128;offset:560;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:31;dwarf:31;#00 +send packet: $qRegisterInfo36#00 +read packet: $name:xmm15;bitsize:128;offset:576;encoding:vector;format:vector-uint8;set:Floating Point Registers;gcc:32;dwarf:32;#00 +send packet: $qRegisterInfo37#00 +read packet: $name:trapno;bitsize:32;offset:696;encoding:uint;format:hex;set:Exception State Registers;#00 +send packet: $qRegisterInfo38#00 +read packet: $name:err;bitsize:32;offset:700;encoding:uint;format:hex;set:Exception State Registers;#00 +send packet: $qRegisterInfo39#00 +read packet: $name:faultvaddr;bitsize:64;offset:704;encoding:uint;format:hex;set:Exception State Registers;#00 +send packet: $qRegisterInfo3a#00 +read packet: $E45#00 +``` + +As we see above we keep making subsequent calls to the remote server to +discover all registers by increasing the number appended to `qRegisterInfo` and +we get a response back that is a series of `key=value;` strings. + +The `offset:` fields should not leave a gap anywhere in the g/G packet -- the +register values should be appended one after another. For instance, if the +register context for a thread looks like: +``` +struct rctx { + uint32_t gpr1; // offset 0 + uint32_t gpr2; // offset 4 + uint32_t gpr3; // offset 8 + uint64_t fp1; // offset 16 +}; +``` + +You may end up with a 4-byte gap between gpr3 and fp1 on architectures +that align values like this. The correct offset: value for fp1 is 12 - +in the g/G packet fp1 will immediately follow gpr3, even though the +in-memory thread structure has an empty 4 bytes for alignment between +these two registers. + +The keys and values are detailed below: + +* `name` - + The primary register name as a string ("rbp" for example) +* `alt-name` - + An alternate name for a register as a string ("fp" for example + for the above "rbp") +* `bitsize` - Size in bits of a register (32, 64, etc). Base 10. +* `offset` - + The offset within the "g" and "G" packet of the register data for + this register. This is the byte offset once the data has been + transformed into binary, not the character offset into the g/G + packet. Base 10. +* `encoding` - + The encoding type of the register which must be one of: + * `uint` (unsigned integer) + * `sint` (signed integer) + * `ieee754` (IEEE 754 float) + * `vector` (vector register) +* format - + The preferred format for display of this register. The value must be one of: + * `binary` + * `decimal` + * `hex` + * `float` + * `vector-sint8` + * `vector-uint8` + * `vector-sint16` + * `vector-uint16` + * `vector-sint32` + * `vector-uint32` + * `vector-float32` + * `vector-uint128` +* `set`- + The register set name as a string that this register belongs to. +* `gcc` - + The GCC compiler registers number for this register (used for + EH frame and other compiler information that is encoded in the + executable files). The supplied number will be decoded like a + string passed to strtoul() with a base of zero, so the number + can be decimal, or hex if it is prefixed with "0x". + + **Note:** If the compiler doesn't have a register number for this + register, this key/value pair should be omitted. +* `dwarf` - + The DWARF register number for this register that is used for this + register in the debug information. The supplied number will be decoded + like a string passed to strtoul() with a base of zero, so the number + can be decimal, or hex if it is prefixed with "0x". + + **Note:** If the compiler doesn't have a register number for this + register, this key/value pair should be omitted. +* `generic` - + If the register is a generic register that most CPUs have, classify + it correctly so the debugger knows. Valid values are one of: + * `pc` (a program counter register. for example `name=eip;` (i386), + `name=rip;` (x86_64), `name=r15;` (32 bit arm) would + include a `generic=pc;` key value pair) + * `sp` (a stack pointer register. for example `name=esp;` (i386), + `name=rsp;` (x86_64), `name=r13;` (32 bit arm) would + include a `generic=sp;` key value pair) + * `fp` (a frame pointer register. for example `name=ebp;` (i386), + `name=rbp;` (x86_64), `name=r7;` (32 bit arm with macosx + ABI) would include a `generic=fp;` key value pair) + * `ra` (a return address register. for example `name=lr;` (32 bit ARM) + would include a `generic=ra;` key value pair) + * `flags` (a CPU flags register. for example `name=eflags;` (i386), + `name=rflags;` (x86_64), `name=cpsr;` (32 bit ARM) + would include a `generic=flags;` key value pair) + * `arg1` - `arg8` (specified for registers that contain function + arguments when the argument fits into a register) +* `container-regs` - + The value for this key is a comma separated list of raw hex (optional + leading "0x") register numbers. + + This specifies that this register is contained in other concrete + register values. For example "eax" is in the lower 32 bits of the + "rax" register value for x86_64, so "eax" could specify that it is + contained in "rax" by specifying the register number for "rax" (whose + register number is 0x00): + ``` + container-regs:00; + ``` + If a register is comprised of one or more registers, like "d0" is ARM + which is a 64 bit register, it might be made up of "s0" and "s1". If + the register number for "s0" is 0x20, and the register number of "s1" + is "0x21", the "container-regs" key/value pair would be: + ``` + container-regs:20,21; + ``` + This is handy for defining what GDB used to call "pseudo" registers. + These registers are never requested by LLDB via the register read + or write packets, the container registers will be requested on behalf + of this register. +* `invalidate-regs` - + The value for this key is a comma separated list of raw hex (optional + leading "0x") register numbers. + + This specifies which register values should be invalidated when this + register is modified. For example if modifying "eax" would cause "rax", + "eax", "ax", "ah", and "al" to be modified where rax is 0x0, eax is 0x15, + ax is 0x25, ah is 0x35, and al is 0x39, the "invalidate-regs" key/value + pair would be: + ``` + invalidate-regs:0,15,25,35,39; + ``` + If there is a single register that gets invalidated, then omit the comma + and just list a single register: + ``` + invalidate-regs:0; + ``` + This is handy when modifying a specific register can cause other + register values to change. For example, when debugging an ARM target, + modifying the CPSR register can cause the r8 - r14 and cpsr value to + change depending on if the mode has changed. + + +## qPlatform_shell + +### Brief + +Run a command in a shell on the connected remote machine. + +### Priority To Implement + +High. This command allows LLDB clients to run arbitrary shell +commands on a remote host. + +### Description + +The request consists of the command to be executed encoded in ASCII characters +converted into hex bytes. + +The response to this packet consists of the letter F followed by the return code, +followed by the signal number (or 0 if no signal was delivered), and escaped bytes +of captured program output. + +Below is an example communication from a client sending an "ls -la" command: +``` +send packet: $qPlatform_shell:6c73202d6c61,00000002#ec +read packet: $F,00000000,00000000,total 4736 +drwxrwxr-x 16 username groupname 4096 Aug 15 21:36 . +drwxr-xr-x 17 username groupname 4096 Aug 10 16:39 .. +-rw-rw-r-- 1 username groupname 73875 Aug 12 16:46 notes.txt +drwxrwxr-x 5 username groupname 4096 Aug 15 21:36 source.cpp +-rw-r--r-- 1 username groupname 2792 Aug 12 16:46 a.out +-rw-r--r-- 1 username groupname 3190 Aug 12 16:46 Makefile +``` + +## qPlatform_mkdir + +### Brief + +Creates a new directory on the connected remote machine. + +### Priority To Implement + +Low. This command allows LLDB clients to create new directories on +a remote host. + +### Description + +Request: `qPlatform_mkdir:,` + +Reply: + * `F` + (mkdir called successfully and returned with the given return code) + * `Exx` (An error occurred) + + +## qPlatform_chmod + +### Brief + +Change the permissions of a file on the connected remote machine. + +### Priority To Implement + +Low. This command allows LLDB clients to change the permissions of +a file on the remote host. + +### Description + +Request: `qPlatform_chmod:,` + +Reply: +* `F` + (chmod called successfully and returned with the given return code) +* `Exx` (An error occurred) + +## qHostInfo + +### Brief + +Get information about the host we are remotely connected to. + +### Priority To Implement + +High. This packet is usually very easy to implement and can help +LLDB select the correct plug-ins for the job based on the target +triple information that is supplied. + +### Description + +LLDB supports a host info call that gets all sorts of details of the system +that is being debugged: +``` +send packet: $qHostInfo#00 +read packet: $cputype:16777223;cpusubtype:3;ostype:darwin;vendor:apple;endian:little;ptrsize:8;#00 +``` + +Key value pairs are one of: +* `cputype`: is a number that is the mach-o CPU type that is being debugged (base 10) +* `cpusubtype`: is a number that is the mach-o CPU subtype type that is being debugged (base 10) +* `triple`: a string for the target triple (x86_64-apple-macosx) that can be used to specify arch + vendor + os in one entry +* `vendor`: a string for the vendor (apple), not needed if "triple" is specified +* `ostype`: a string for the OS being debugged (macosx, linux, freebsd, ios, watchos), not needed if "triple" is specified +* `endian`: is one of "little", "big", or "pdp" +* `ptrsize`: an unsigned number that represents how big pointers are in bytes on the debug target +* `hostname`: the hostname of the host that is running the GDB server if available +* `os_build`: a string for the OS build for the remote host as a string value +* `os_kernel`: a string describing the kernel version +* `os_version`: a version string that represents the current OS version (10.8.2) +* `watchpoint_exceptions_received`: one of "before" or "after" to specify if a watchpoint is triggered before or after the pc when it stops +* `default_packet_timeout`: an unsigned number that specifies the default timeout in seconds +* `distribution_id`: optional. For linux, specifies distribution id (e.g. ubuntu, fedora, etc.) +* `osmajor`: optional, specifies the major version number of the OS (e.g. for macOS 10.12.2, it would be 10) +* `osminor`: optional, specifies the minor version number of the OS (e.g. for macOS 10.12.2, it would be 12) +* `ospatch`: optional, specifies the patch level number of the OS (e.g. for macOS 10.12.2, it would be 2) +* `vm-page-size`: optional, specifies the target system VM page size, base 10. + Needed for the "dirty-pages:" list in the qMemoryRegionInfo + packet, where a list of dirty pages is sent from the remote + stub. This page size tells lldb how large each dirty page is. +* `addressing_bits`: optional, specifies how many bits in addresses are + significant for addressing, base 10. If bits 38..0 + in a 64-bit pointer are significant for addressing, + then the value is 39. This is needed on e.g. AArch64 + v8.3 ABIs that use pointer authentication, so lldb + knows which bits to clear/set to get the actual + addresses. +* `low_mem_addressing_bits`: optional, specifies how many bits in + addresses in low memory are significant for addressing, base 10. + AArch64 can have different page table setups for low and high + memory, and therefore a different number of bits used for addressing. +* `high_mem_addressing_bits`: optional, specifies how many bits in + addresses in high memory are significant for addressing, base 10. + AArch64 can have different page table setups for low and high + memory, and therefore a different number of bits used for addressing. + +## qGDBServerVersion + +### Brief + +Get version information about this implementation of the gdb-remote +protocol. + +### Priority To Implement + +High. This packet is usually very easy to implement and can help +LLDB to work around bugs in a server's implementation when they +are found. + +### Description + +The goal of this packet is to provide enough information about an +implementation of the gdb-remote-protocol server that lldb can +work around implementation problems that are discovered after the +version has been released/deployed. The name and version number +should be sufficiently unique that lldb can unambiguously identify +the origin of the program (for instance, debugserver from lldb) and +the version/submission number/patch level of the program - whatever +is appropriate for your server implementation. + +The packet follows the key-value pair model, semicolon separated. +``` +send packet: $qGDBServerVersion#00 +read packet: $name:debugserver;version:310.2;#00 +``` + +Other clients may find other key-value pairs to be useful for identifying +a gdb stub. Patch level, release name, build number may all be keys that +better describe your implementation's version. + +Suggested key names: +* `name`: the name of your remote server - "debugserver" is the lldb standard + implementation +* `version`: identifies the version number of this server +* `patch_level`: the patch level of this server +* `release_name`: the name of this release, if your project uses names +* `build_number`: if you use a build system with increasing build numbers, + this may be the right key name for your server +* `major_version`: major version number +* `minor_version`: minor version number + +## qProcessInfo + +### Brief + +Get information about the process we are currently debugging. + +### Priority To Implement + +Medium. On systems which can launch multiple different architecture processes, +the qHostInfo may not disambiguate sufficiently to know what kind of +process is being debugged. + +For example on a 64-bit x86 Mac system both 32-bit and 64-bit user processes are possible, +and with Mach-O universal files, the executable file may contain both 32- and +64-bit slices so it may be impossible to know until you're attached to a real +process to know what you're working with. + +All numeric fields return base 16 numbers without any "0x" prefix. + +### Description + +An i386 process: +``` +send packet: $qProcessInfo#00 +read packet: $pid:42a8;parent-pid:42bf;real-uid:ecf;real-gid:b;effective-uid:ecf;effective-gid:b;cputype:7;cpusubtype:3;ostype:macosx;vendor:apple;endian:little;ptrsize:4;#00 +``` + +An x86_64 process: +``` +send packet: $qProcessInfo#00 +read packet: $pid:d22c;parent-pid:d34d;real-uid:ecf;real-gid:b;effective-uid:ecf;effective-gid:b;cputype:1000007;cpusubtype:3;ostype:macosx;vendor:apple;endian:little;ptrsize:8;#00 +``` + +Key value pairs include: +* `pid`: the process id +* `parent-pid`: the process of the parent process (often debugserver will become the parent when attaching) +* `real-uid`: the real user id of the process +* `real-gid`: the real group id of the process +* `effective-uid`: the effective user id of the process +* `effective-gid`: the effective group id of the process +* `cputype`: the Mach-O CPU type of the process (base 16) +* `cpusubtype`: the Mach-O CPU subtype of the process (base 16) +* `ostype`: is a string the represents the OS being debugged (darwin, linux, freebsd) +* `vendor`: is a string that represents the vendor (apple) +* `endian`: is one of "little", "big", or "pdp" +* `ptrsize`: is a number that represents how big pointers are in bytes +* `main-binary-uuid`: is the UUID of a firmware type binary that the gdb stub knows about +* `main-binary-address`: is the load address of the firmware type binary +* `main-binary-slide`: is the slide of the firmware type binary, if address isn't known +* `binary-addresses`: A comma-separated list of binary load addresses base 16. + lldb will parse the binaries in memory to get UUIDs, then + try to find the binaries & debug info by UUID. Intended for + use with a small number of firmware type binaries where the + search for binary/debug info may be expensive. + +## qShlibInfoAddr + +### Brief + +Get an address where the dynamic linker stores information about +where shared libraries are loaded. + +### Priority To Implement + +High if you have a dynamic loader plug-in in LLDB for your target +triple (see the "qHostInfo" packet) that can use this information. +Many times address load randomization can make it hard to detect +where the dynamic loader binary and data structures are located and +some platforms know, or can find out where this information is. + +Low if you have a debug target where all object and symbol files +contain static load addresses. + +### Description + +LLDB and GDB both support the `qShlibInfoAddr` packet which is a hint to each +debugger as to where to find the dynamic loader information. For darwin +binaries that run in user land this is the address of the `all_image_infos` +structure in the `/usr/lib/dyld` executable, or the result of a `TASK_DYLD_INFO` +call. The result is returned as big endian hex bytes that are the address +value: +``` +send packet: $qShlibInfoAddr#00 +read packet: $7fff5fc40040#00 +``` + +## qThreadStopInfo\ + +### Brief + +Get information about why a thread, whose ID is ``, is stopped. + +### Priority To Implement + +High if you need to support multi-threaded or multi-core debugging. +Many times one thread will hit a breakpoint and while the debugger +is in the process of suspending the other threads, other threads +will also hit a breakpoint. This packet allows LLDB to know why all +threads (live system debug) / cores (JTAG) in your program have +stopped and allows LLDB to display and control your program +correctly. + +### Description + +LLDB tries to use the `qThreadStopInfo` packet which is formatted as +`qThreadStopInfo%x` where `%x` is the hex thread ID. This requests information +about why a thread is stopped. The response is the same as the stop reply +packets and tells us what happened to the other threads. The standard GDB +remote packets love to think that there is only _one_ reason that _one_ thread +stops at a time. This allows us to see why all threads stopped and allows us +to implement better multi-threaded debugging support. + +## QThreadSuffixSupported + +### Brief + +Try to enable thread suffix support for the `g`, `G`, `p`, and `P` packets. + +### Priority To Implement + +High. Adding a thread suffix allows us to read and write registers +more efficiently and stops us from having to select a thread with +one packet and then read registers with a second packet. It also +makes sure that no errors can occur where the debugger thinks it +already has a thread selected (see the `Hg` packet from the standard +GDB remote protocol documentation) yet the remote GDB server actually +has another thread selected. + +### Description + +When reading thread registers, you currently need to set the current +thread, then read the registers. This is kind of cumbersome, so we added the +ability to query if the remote GDB server supports adding a `thread:;` +suffix to all packets that request information for a thread. To test if the +remote GDB server supports this feature: +``` +send packet: $QThreadSuffixSupported#00 +read packet: OK +``` + +If `OK` is returned, then the `g`, `G`, `p` and `P` packets can accept a +thread suffix. So to send a `g` packet (read all register values): +``` +send packet: $g;thread:;#00 +read packet: .... + +send packet: $G;thread:;#00 +read packet: .... + +send packet: $p1a;thread:;#00 +read packet: .... + +send packet: $P1a=1234abcd;thread:;#00 +read packet: .... +``` + +otherwise, without this you would need to always send two packets: +``` +send packet: $Hg#00 +read packet: .... +send packet: $g#00 +read packet: .... +``` + +We also added support for allocating and deallocating memory. We use this to +allocate memory so we can run JITed code. + +## _M\,\ + +### Brief + +Allocate memory on the remote target with the specified size and +permissions. + +### Priority To Implement + +High if you want LLDB to be able to JIT code and run that code. JIT +code also needs data which is also allocated and tracked. + +Low if you don't support running JIT'ed code. + +### Description + +The allocate memory packet starts with `_M,`. It returns a +raw big endian address value, or an empty response for unimplemented, or `EXX` for an error +code. The packet is formatted as: +``` +char packet[256]; +int packet_len; +packet_len = ::snprintf ( + packet, + sizeof(packet), + "_M%zx,%s%s%s", + (size_t)size, + permissions & lldb::ePermissionsReadable ? "r" : "", + permissions & lldb::ePermissionsWritable ? "w" : "", + permissions & lldb::ePermissionsExecutable ? "x" : ""); +``` + +You request a size and give the permissions. This packet does NOT need to be +implemented if you don't want to support running JITed code. The return value +is just the address of the newly allocated memory as raw big endian hex bytes. + +## _m\ + +### Brief + +Deallocate memory that was previously allocated using an allocate +memory pack. + +### Priority To Implement + +High if you want LLDB to be able to JIT code and run that code. JIT +code also needs data which is also allocated and tracked. + +Low if you don't support running JIT'ed code. + +### Description + +The deallocate memory packet is `_m` where you pass in the address you +got back from a previous call to the allocate memory packet. It returns `OK` +if the memory was successfully deallocated, or `EXX`" for an error, or an +empty response if not supported. + +## qMemoryRegionInfo:\ + +### Brief + +Get information about the address range that contains ``. + +### Priority To Implement + +Medium. This is nice to have, but it isn't necessary. It helps LLDB +do stack unwinding when we branch into memory that isn't executable. +If we can detect that the code we are stopped in isn't executable, +then we can recover registers for stack frames above the current +frame. Otherwise we must assume we are in some JIT'ed code (not JIT +code that LLDB has made) and assume that no registers are available +in higher stack frames. + +### Description + +We added a way to get information for a memory region. The packet is: +``` +qMemoryRegionInfo: +``` + +Where `` is a big endian hex address. The response is returned in a series +of tuples like the data returned in a stop reply packet. The currently valid +tuples to return are: +* `start:;` - `` is a big endian hex address that is + the start address of the range that contains `` +* `size:;` - `` is a big endian hex byte size of the address + of the range that contains `` +* `permissions:;` - `` is a string that contains one + or more of the characters from `rwx` +* `name:;` - `` is a hex encoded string that contains the name of + the memory region mapped at the given address. In case of + regions backed by a file it have to be the absolute path of + the file while for anonymous regions it have to be the name + associated to the region if that is available. +* `flags:;` - where `` is a space separated string + of flag names. Currently the only supported flag + is `mt` for AArch64 memory tagging. lldb will + ignore any other flags in this field. +* `type:[][,];` - memory types that apply to this region, e.g. + `stack` for stack memory. +* `error:;` - where `` is + a hex encoded string value that + contains an error string +* `dirty-pages:[][,` - The save_id result is a non-zero unsigned integer value + that can be passed back to the GDB server using a + `QRestoreRegisterState` packet to restore the registers + one time. +* `EXX` - or an error code in the form of `EXX` where `XX` is a + hex error code. + +### Priority To Implement + +Low, this is mostly a convenience packet to avoid having to send all +registers with a `g` packet. It should only be implemented if support +for the `QRestoreRegisterState` is added. + +## QRestoreRegisterState:\ / QRestoreRegisterState:\;thread:XXXX; + +### Brief + +The `QRestoreRegisterState` packet tells the remote debugserver to +restore all registers using the `save_id` which is an unsigned +integer that was returned from a previous call to +`QSaveRegisterState`. The restoration process can only be done once +as the data backing the register state will be freed upon the +completion of the `QRestoreRegisterState` command. + +If thread suffixes are enabled the second form of this packet is +used, otherwise the first form is used. + +### Response + +* `OK` - if all registers were successfully restored +* `EXX` - for any errors + +### Priority To Implement + +Low, this is mostly a convenience packet to avoid having to send all +registers with a `g` packet. It should only be implemented if support +for the `QSaveRegisterState` is added. + +## qFileLoadAddress:\ + +### Brief + +Get the load address of a memory mapped file. +The load address is defined as the address of the first memory +region what contains data mapped from the specified file. + +### Response + +* `` - Load address of the file in big endian encoding +* `E01` - the requested file isn't loaded +* `EXX` - for any other errors + +### Priority To Implement + +Low, required if dynamic linker don't fill in the load address of +some object file in the rendezvous data structure. + +## qModuleInfo:\;\ + +### Brief + +Get information for a module by given module path and architecture. + +### Response + +* `(uuid|md5):...;triple:...;file_offset:...;file_size...;` +* `EXX` - for any errors + +### Priority To Implement + +Optional, required if dynamic loader cannot fetch module's information like +UUID directly from inferior's memory. + +## jModulesInfo:[{"file":"...",triple:"..."}, ...] + +### Brief + +Get information for a list of modules by given module path and +architecture. + +### Response + +A JSON array of dictionaries containing the following keys: +* `uuid` +* `triple` +* `file_path` +* `file_offset` +* `file_size` + +The meaning of the fields is the same as in the `qModuleInfo` packet. The server +signals the failure to retrieve the module info for a file by ommiting the +corresponding array entry from the response. The server may also +include entries the client did not ask for, if it has reason to +the modules will be interesting to the client. + +### Priority To Implement + +Optional. If not implemented, `qModuleInfo` packet will be used, which +may be slower if the target contains a large number of modules and +the communication link has a non-negligible latency. + +## Stop reply packet extensions + +### Brief + +This section describes some of the additional information you can +specify in stop reply packets that help LLDB to know more detailed +information about your threads. + +### Description + +Standard GDB remote stop reply packets are reply packets sent in +response to a packet that made the program run. They come in the +following forms: + +* `SAA` - + `S` means signal and `AA` is a hex signal number that describes why + the thread or stopped. It doesn't specify which thread, so the `T` + packet is recommended to use instead of the `S` packet. + +* `TAAkey1:value1;key2:value2;...` - + `T` means a thread stopped due to a unix signal where `AA` is a hex + signal number that describes why the program stopped. This is + followed by a series of key/value pairs: + * If key is a hex number, it is a register number and value is + the hex value of the register in debuggee endian byte order. + * If key == "thread", then the value is the big endian hex + thread-id of the stopped thread. + * If key == "core", then value is a hex number of the core on + which the stop was detected. + * If key == "watch" or key == "rwatch" or key == "awatch", then + value is the data address in big endian hex + * If key == "library", then value is ignore and "qXfer:libraries:read" + packets should be used to detect any newly loaded shared libraries + +* `WAA` - `W` means the process exited and `AA` is the exit status. + +* `XAA` - `X` means the process exited and `AA` is signal that caused the program + to exit. + +* `O` - `O` means `STDOUT` has data that was written to its + console and is being delivered to the debugger. This packet happens asynchronously + and the debugger is expected to continue to wait for another stop reply + packet. + +### Lldb Extensions + +We have extended the `T` packet to be able to also understand the +following keys and values: + +* `metype` - `unsigned` - + mach exception type (the value of the `EXC_XXX` enumerations) + as an unsigned integer. For targets with mach + kernels only. +* `mecount` - `unsigned` - + mach exception data count as an unsigned integer + For targets with mach kernels only. +* `medata` - `unsigned` - + There should be `mecount` of these and it is the data + that goes along with a mach exception (as an unsigned + integer). For targets with mach kernels only. +* `name` - `string` - + The name of the thread as a plain string. The string + must not contain an special packet characters or + contain a `:` or a `;`. Use `hexname` if the thread + name has special characters. +* `hexname` - `ascii-hex` - An ASCII hex string that contains the name of the thread +* `qaddr` - `hex` - + Big endian hex value that contains the `libdispatch` + queue address for the queue of the thread. +* `reason` - `enum` - The enumeration must be one of: + * `trace` - + the program stopped after a single instruction + was executed on a core. Usually done when single + stepping past a breakpoint + * `breakpoint` - a breakpoint set using a `z` packet was hit. + * `trap` - stopped due to user interruption + * `signal` - + stopped due to an actual unix signal, not + just the debugger using a unix signal to keep + the GDB remote client happy. + * `watchpoint` - Can be used with of the `watch`/`rwatch`/`awatch` key value + pairs. Or can be used *instead* of those keys, with the specially formatted + `description` field. + * `exception` - an exception stop reason. Use with + the `description` key/value pair to describe the + exceptional event the user should see as the stop + reason. + * `description` - + An ASCII hex string that contains a more descriptive + reason that the thread stopped. This is only needed + if none of the key/value pairs are enough to + describe why something stopped. + + For `reason:watchpoint`, `description` is an ascii-hex + encoded string with between one and three base 10 numbers, + space separated. The three numbers are: + 1. Watchpoint address. This address should always be within + a memory region lldb has a watchpoint on. + On architectures where the actual reported hit address may + be outside the watchpoint that was triggered, the remote + stub should determine which watchpoint was triggered and + report an address from within its range. + 2. Wwatchpoint hardware register index number. + 3. Actual watchpoint trap address, which may be outside + the range of any watched region of memory. On MIPS, an addr + outside a watched range means lldb should disable the wp, + step, re-enable the wp and continue silently. + + On MIPS, the low 3 bits are masked so if a watchpoint is on + 0x1004, a 2-byte write to 0x1000 will trigger the watchpoint + (a false positive hit), and lldb needs to disable the + watchpoint at 0x1004, inst-step, then re-enable the watchpoint + and not make this a user visible event. The description here + would be "0x1004 0 0x1000". lldb needs a known watchpoint address + in the first field, so it can disable it and step. + + On AArch64 we have a related issue, where you watch 4 bytes at + 0x1004, an instruction does an 8-byte write starting at + 0x1000 (a true watchpoint hit) and the hardware may report the + trap address as 0x1000 - before the watched memory region - + with the write extending into the watched region. This can + be reported as "0x1004 0 0x1000". lldb will use 0x1004 to + identify which Watchpoint was triggered, and can report 0x1000 + to the user. The behavior of silently stepping over the + watchpoint, with an 3rd field addr outside the range, is + restricted to MIPS. + + There may be false-positive watchpoint hits on AArch64 as well, + in the SVE Streaming Mode, but that is less common (see ESR + register flag "WPF", "Watchpoint might be False-Positive") and + not currently handled by lldb. +* `threads` - `comma-sep-base16` - + A list of thread ids for all threads (including + the thread that we're reporting as stopped) that + are live in the process right now. lldb may + request that this be included in the T packet via + the QListThreadsInStopReply packet earlier in + the debug session. + + Example: + ``` + threads:63387,633b2,63424,63462,63486; + ``` +* `thread-pcs` - `comma-sep-base16` - + A list of pc values for all threads that currently + exist in the process, including the thread that + this `T` packet is reporting as stopped. + This key-value pair will only be emitted when the + `threads` key is already included in the `T` packet. + The pc values correspond to the threads reported + in the `threads` list. The number of pcs in the + `thread-pcs` list will be the same as the number of + threads in the `threads` list. + lldb may request that this be included in the `T` + packet via the `QListThreadsInStopReply` packet + earlier in the debug session. + + Example: + ``` + thread-pcs:dec14,2cf872b0,2cf8681c,2d02d68c,2cf716a8; + ``` +* `addressing_bits` - `unsigned` (optional) - + Specifies how many bits in addresses are significant for addressing, base + 10. If bits 38..0 in a 64-bit pointer are significant for addressing, then the + value is 39. This is needed on e.g. AArch64 v8.3 ABIs that use pointer + authentication in the high bits. This value is normally sent in the `qHostInfo` + packet response, and if the value cannot change during the process lifetime, + it does not need to be duplicated here in the stop packet. For a firmware + environment with early start code that may be changing the page table setup, + a dynamically set value may be needed. +* `low_mem_addressing_bits` - `unsigned` (optional) - + Specifies how many bits in addresses in low memory are significant for + addressing, base 10. AArch64 can have different page table setups for low + and high memory, and therefore a different number of bits used for addressing. +* `high_mem_addressing_bits` - `unsigned` (optional) - + Specifies how many bits in addresses in high memory are significant for + addressing, base 10. AArch64 can have different page table setups for low and + high memory, and therefore a different number of bits used for addressing. + +### Best Practices + +Since register values can be supplied with this packet, it is often useful +to return the PC, SP, FP, LR (if any), and FLAGS registers so that separate +packets don't need to be sent to read each of these registers from each +thread. + +If a thread is stopped for no reason (like just because another thread +stopped, or because when one core stops all cores should stop), use a +`T` packet with `00` as the signal number and fill in as many key values +and registers as possible. + +LLDB likes to know why a thread stopped since many thread control +operations like stepping over a source line, actually are implemented +by running the process multiple times. If a breakpoint is hit while +trying to step over a source line and LLDB finds out that a breakpoint +is hit in the "reason", we will know to stop trying to do the step +over because something happened that should stop us from trying to +do the step. If we are at a breakpoint and we disable the breakpoint +at the current PC and do an instruction single step, knowing that +we stopped due to a "trace" helps us know that we can continue +running versus stopping due to a "breakpoint" (if we have two +breakpoint instruction on consecutive instructions). So the more info +we can get about the reason a thread stops, the better job LLDB can +do when controlling your process. A typical GDB server behavior is +to send a SIGTRAP for breakpoints _and_ also when instruction single +stepping, in this case the debugger doesn't really know why we +stopped and it can make it hard for the debugger to control your +program correctly. What if a real SIGTRAP was delivered to a thread +while we were trying to single step? We wouldn't know the difference +with a standard GDB remote server and we could do the wrong thing. + +### Priority To Implement + +High. Having the extra information in your stop reply packets makes +your debug session more reliable and informative. + +## qfProcessInfo / qsProcessInfo (Platform Extension) + +### Brief + +Get the first process info (`qfProcessInfo`) or subsequent process +info (`qsProcessInfo`) for one or more processes on the remote +platform. The first call gets the first match and subsequent calls +to `qsProcessInfo` gets the subsequent matches. Return an error `EXX`, +where `XX` are two hex digits, when no more matches are available. + +### Priority To Implement + +Required. The `qfProcessInfo` packet can be followed by a `:` and +some key value pairs. The key value pairs in the command are: + +* `name` - `ascii-hex` - + An ASCII hex string that contains the name of the process that will be matched. +* `name_match` - `enum` - + One of: + * `equals` + * `starts_with` + * `ends_with` + * `contains` + * `regex` +* `pid` - `integer`- A string value containing the decimal process ID +* `parent_pid` - `integer` - A string value containing the decimal parent process ID +* `uid` - `integer` - A string value containing the decimal user ID +* `gid` - `integer` - A string value containing the decimal group ID +* `euid` - `integer` - A string value containing the decimal effective user ID +* `egid` - `integer` - A string value containing the decimal effective group ID +* `all_users` - `bool` - + A boolean value that specifies if processes should + be listed for all users, not just the user that the + platform is running as +* `triple` - `string` - + An ASCII triple string (`x86_64`, `x86_64-apple-macosx`, `armv7-apple-ios`) +* `args` - `string` - + A string value containing the process arguments separated by the character `-`, + where each argument is hex-encoded. It includes `argv[0]`. + +The response consists of key/value pairs where the key is separated from the +values with colons and each pair is terminated with a semi colon. For a list +of the key/value pairs in the response see the `qProcessInfoPID` packet +documentation. + +Sample packet/response: +``` +send packet: $qfProcessInfo#00 +read packet: $pid:60001;ppid:59948;uid:7746;gid:11;euid:7746;egid:11;name:6c6c6462;triple:x86_64-apple-macosx;#00 +send packet: $qsProcessInfo#00 +read packet: $pid:59992;ppid:192;uid:7746;gid:11;euid:7746;egid:11;name:6d64776f726b6572;triple:x86_64-apple-macosx;#00 +send packet: $qsProcessInfo#00 +read packet: $E04#00 +``` + +## qLaunchGDBServer (Platform Extension) + +### Brief + +Have the remote platform launch a GDB server. + +### Priority To Implement + +Required. The `qLaunchGDBServer` packet must be followed by a `:` and +some key value pairs. The key value pairs in the command are: +* `port` - `integer` - + A string value containing the decimal port ID or zero if the port should be + bound and returned +* `host` - `integer` - + The host that connections should be limited to when the GDB server is connected to. + +### Description + +The response consists of key/value pairs where the key is separated from the +values with colons and each pair is terminated with a semi colon. + +Sample packet/response: +``` +send packet: $qLaunchGDBServer:port:0;host:lldb.apple.com;#00 +read packet: $pid:60025;port:50776;#00 +``` + +The `pid` key/value pair is only specified if the remote platform launched +a separate process for the GDB remote server and can be omitted if no +process was separately launched. + +The `port` key/value pair in the response lets clients know what port number +to attach to in case zero was specified as the "port" in the sent command. + + +## qProcessInfoPID:PID (Platform Extension) + +### Brief + +Have the remote platform get detailed information on a process by +ID. PID is specified as a decimal integer. + +### Priority To Implement + +Optional. + +### Description + +The response consists of key/value pairs where the key is separated from the +values with colons and each pair is terminated with a semi colon. + +The key value pairs in the response are: +* `pid` - `integer` - Process ID as a decimal integer string +* `ppid` - `integer` - Parent process ID as a decimal integer string +* `uid` - `integer` - A string value containing the decimal user ID +* `gid` - `integer` - A string value containing the decimal group ID +* `euid` - `integer` - A string value containing the decimal effective user ID +* `egid` - `integer` - A string value containing the decimal effective group ID +* `name` - `ascii-hex` - An ASCII hex string that contains the name of the process +* `triple` - `string` - A target triple (`x86_64-apple-macosx`, `armv7-apple-ios`) + +Sample packet/response: +``` +send packet: $qProcessInfoPID:60050#00 +read packet: $pid:60050;ppid:59948;uid:7746;gid:11;euid:7746;egid:11;name:6c6c6462;triple:x86_64-apple-macosx;#00 +``` + +## vAttachName + +### Brief + +Same as `vAttach`, except instead of a `pid` you send a process name. + +### Priority To Implement + +Low. Only needed for `process attach -n`. If the packet isn't supported +then `process attach -n` will fail gracefully. So you need only to support +it if attaching to a process by name makes sense for your environment. + +## vAttachWait + +### Brief + +Same as `vAttachName`, except that the stub should wait for the next instance +of a process by that name to be launched and attach to that. + +### Priority To Implement + +Low. Only needed to support `process attach -w -n` which will fail +gracefully if the packet is not supported. + +## qAttachOrWaitSupported + +### Brief + +This is a binary "is it supported" query. Return OK if you support +`vAttachOrWait`. + +### Priority To Implement + +Low. This is required if you support `vAttachOrWait`, otherwise no support +is needed since the standard "I don't recognize this packet" response +will do the right thing. + +## vAttachOrWait + +### Brief + +Same as `vAttachWait`, except that the stub will attach to a process +by name if it exists, and if it does not, it will wait for a process +of that name to appear and attach to it. + +### Priority To Implement + +Low. Only needed to implement `process attach -w -i false -n`. If +you don't implement it but do implement `-n` AND lldb can somehow get +a process list from your device, it will fall back on scanning the +process list, and sending `vAttach` or `vAttachWait` depending on +whether the requested process exists already. This is racy, +however, so if you want to support this behavior it is better to +support this packet. + +## jThreadExtendedInfo + +### Brief + +This packet, which takes its arguments as JSON and sends its reply as +JSON, allows the gdb remote stub to provide additional information +about a given thread. + +### Priority To Implement + +Low. This packet is only needed if the gdb remote stub wants to +provide interesting additional information about a thread for the +user. + +### Description + +This packet takes its arguments in [JSON](http://www.json.org). +At a minimum, a thread must be specified, for example: +``` +jThreadExtendedInfo:{"thread":612910} +``` + +Because this is a JSON string, the thread number is provided in base 10. +Additional key-value pairs may be provided by lldb to the gdb remote +stub. For instance, on some versions of macOS, lldb can read offset +information out of the system libraries. Using those offsets, debugserver +is able to find the Thread Specific Address (TSD) for a thread and include +that in the return information. So lldb will send these additional fields +like so: +``` +jThreadExtendedInfo:{"plo_pthread_tsd_base_address_offset":0,"plo_pthread_tsd_base_offset":224,"plo_pthread_tsd_entry_size":8,"thread":612910} +``` + +There are no requirements for what is included in the response. A simple +reply on a OS X Yosemite / iOS 8 may include the pthread_t value, the +Thread Specific Data (TSD) address, the dispatch_queue_t value if the thread +is associated with a GCD queue, and the requested Quality of Service (QoS) +information about that thread. For instance, a reply may look like: +``` +{"tsd_address":4371349728,"requested_qos":{"enum_value":33,"constant_name":"QOS_CLASS_USER_INTERACTIVE","printable_name":"User Interactive"},"pthread_t":4371349504,"dispatch_queue_t":140735087127872} +``` + +`tsd_address`, `pthread_t`, and `dispatch_queue_t` are all simple key-value pairs. +The JSON standard requires that numbers be expressed in base 10 - so all of +these are. `requested_qos` is a dictionary with three key-value pairs in it - +so the UI layer may choose the form most appropriate for displaying to the user. + +Sending JSON over gdb-remote protocol introduces some problems. We may be +sending strings with arbitrary contents in them, including the `#`, `$`, and `*` +characters that have special meaning in gdb-remote protocol and cannot occur +in the middle of the string. The standard solution for this would be to require +ascii-hex encoding of all strings, or ascii-hex encode the entire JSON payload. + +Instead, the binary escaping convention is used for JSON data. This convention +(e.g. used for the `X` packet) says that if `#`, `$`, `*`, or `}` are to occur in +the payload, the character `}` (`0x7d`) is emitted, then the metacharacter is emitted +xor'ed by `0x20`. The `}` character occurs in every JSON payload at least once, and +`} ^ 0x20` happens to be `]` so the raw packet characters for a request will look +like: +``` +jThreadExtendedInfo:{"thread":612910}] +``` + +## QEnableCompression + +### Brief + +This packet enables compression of the packets that the debug stub sends to lldb. +If the debug stub can support compression, it indictes this in the reply of the +"qSupported" packet. For example: +``` +LLDB SENDS: qSupported:xmlRegisters=i386,arm,mips +STUB REPLIES: qXfer:features:read+;SupportedCompressions=lzfse,zlib-deflate,lz4,lzma; +``` + +If lldb knows how to use any of these compression algorithms, it can ask that this +compression mode be enabled. +``` +QEnableCompression:type:zlib-deflate; +``` + +The debug stub should reply with an uncompressed `OK` packet to indicate that the +request was accepted. All further packets the stub sends will use this compression. + +Packets are compressed as the last step before they are sent from the stub, and +decompressed as the first step after they are received. The packet format in compressed +mode becomes one of two: +``` +$N#00 + +$C:#00 +``` + +Where `#00` is the actual checksum value if noack mode is not enabled. The checksum +value is for the `N` or +`C:` bytes in the packet. + +The size of the uncompressed payload in base 10 is provided because it will simplify +decompression if the final buffer size needed is known ahead of time. + +Compression on low-latency connections is unlikely to be an improvement. Particularly +when the debug stub and lldb are running on the same host. It should only be used +for slow connections, and likely only for larger packets. + +Example compression algorithms that may be used include: +* `zlib-deflate` - + The raw DEFLATE format as described in IETF RFC 1951. With the ZLIB library, you + can compress to this format with an initialization like + deflateInit2 (&stream, 5, Z_DEFLATED, -15, 8, Z_DEFAULT_STRATEGY) + and you can decompress with an initialization like + inflateInit2 (&stream, -15). +* `lz4` - + https://en.wikipedia.org/wiki/LZ4_(compression_algorithm) + https://github.com/Cyan4973/lz4 + The libcompression APIs on darwin systems call this `COMPRESSION_LZ4_RAW`. +* `lzfse` - + Compression algorithm added in macOS 10.11, with open source C reference + implementation on github. + https://en.wikipedia.org/wiki/LZFSE + https://github.com/lzfse/lzfse +* `lzma` - + libcompression implements "LZMA level 6", the default compression for the + open source LZMA implementation. + +## jGetLoadedDynamicLibrariesInfos + +### Brief + +This packet asks the remote debug stub to send the details about libraries +being added/removed from the process as a performance optimization. + +There are two ways this packet can be used. Both return a dictionary of +binary images formatted the same way. + +One requests information on all shared libraries: +``` +jGetLoadedDynamicLibrariesInfos:{"fetch_all_solibs":true} +``` +with an optional `"report_load_commands":false` which can be added, asking +that only the dyld SPI information (load addresses, filenames) be returned. +The default behavior is that debugserver scans the mach-o header and load +commands of each binary, and returns it in the JSON reply. + +And the second requests information about a list of shared libraries, given their load addresses: +``` +jGetLoadedDynamicLibrariesInfos:{"solib_addresses":[8382824135,3258302053,830202858503]} +``` + +The second call is both a performance optimization (instead of having lldb read the mach-o header/load commands +out of memory with generic read packets) but also adds additional information in the form of the +filename of the shared libraries (which is not available in the mach-o header/load commands.) + +An example using the OS X 10.11 style call: +``` +LLDB SENDS: jGetLoadedDynamicLibrariesInfos:{"image_count":1,"image_list_address":140734800075128} +STUB REPLIES: ${"images":[{"load_address":4294967296,"mod_date":0,"pathname":"/tmp/a.out","uuid":"02CF262C-ED6F-3965-9E14-63538B465CFF","mach_header":{"magic":4277009103,"cputype":16777223,"cpusubtype":18446744071562067971,"filetype":2},"segments":{"name":"__PAGEZERO","vmaddr":0,"vmsize":4294967296,"fileoff":0,"filesize":0,"maxprot":0},{"name":"__TEXT","vmaddr":4294967296,"vmsize":4096,"fileoff":0,"filesize":4096,"maxprot":7},{"name":"__LINKEDIT","vmaddr":4294971392,"vmsize":4096,"fileoff":4096,"filesize":152,"maxprot":7}}]}#00 +``` + +Or pretty-printed: +``` +STUB REPLIES: ${"images": + [ + {"load_address":4294967296, + "mod_date":0, + "pathname":"/tmp/a.out", + "uuid":"02CF262C-ED6F-3965-9E14-63538B465CFF", + "mach_header": + {"magic":4277009103, + "cputype":16777223, + "cpusubtype":18446744071562067971, + "filetype":2 + }, + "segments": + [ + {"name":"__PAGEZERO", + "vmaddr":0, + "vmsize":4294967296, + "fileoff":0, + "filesize":0, + "maxprot":0 + }, + {"name":"__TEXT", + "vmaddr":4294967296, + "vmsize":4096, + "fileoff":0, + "filesize":4096, + "maxprot":7 + }, + {"name":"__LINKEDIT", + "vmaddr":4294971392, + "vmsize":4096, + "fileoff":4096, + "filesize":152, + "maxprot":7 + } + ] + } + ] + } +``` + +### Description + +This is similar to the `qXfer:libraries:read` packet, and it could +be argued that it should be merged into that packet. A separate +packet was created primarily because lldb needs to specify the +number of images to be read and the address from which the initial +information is read. Also the XML DTD would need to be extended +quite a bit to provide all the information that the `DynamicLoaderMacOSX` +would need to work correctly on this platform. + +### Priority To Implement + +On OS X 10.11, iOS 9, tvOS 9, watchOS 2 and older: Low. If this packet is absent, +lldb will read the Mach-O headers/load commands out of memory. +On macOS 10.12, iOS 10, tvOS 10, watchOS 3 and newer: High. If this packet is absent, +lldb will not know anything about shared libraries in the inferior, or where the main +executable loaded. + +## jThreadsInfo + +### Brief + +Ask for the server for thread stop information of all threads. + +### Priority To Implement + +Low. This is a performance optimization, which speeds up debugging by avoiding +multiple round-trips for retrieving thread information. The information from this +packet can be retrieved using a combination of `qThreadStopInfo` and `m` packets. + +### Description + +The data in this packet is very similar to the stop reply packets, but is packaged in +JSON and uses JSON arrays where applicable. The JSON output looks like: +``` + [ + { "tid":1580681, + "metype":6, + "medata":[2,0], + "reason":"exception", + "qaddr":140735118423168, + "registers": { + "0":"8000000000000000", + "1":"0000000000000000", + "2":"20fabf5fff7f0000", + "3":"e8f8bf5fff7f0000", + "4":"0100000000000000", + "5":"d8f8bf5fff7f0000", + "6":"b0f8bf5fff7f0000", + "7":"20f4bf5fff7f0000", + "8":"8000000000000000", + "9":"61a8db78a61500db", + "10":"3200000000000000", + "11":"4602000000000000", + "12":"0000000000000000", + "13":"0000000000000000", + "14":"0000000000000000", + "15":"0000000000000000", + "16":"960b000001000000", + "17":"0202000000000000", + "18":"2b00000000000000", + "19":"0000000000000000", + "20":"0000000000000000" + }, + "memory":[ + {"address":140734799804592,"bytes":"c8f8bf5fff7f0000c9a59e8cff7f0000"}, + {"address":140734799804616,"bytes":"00000000000000000100000000000000"} + ] + } + ] +``` + +It contains an array of dictionaries with all of the key value pairs that are +normally in the stop reply packet, including the expedited registers. The registers are +passed as hex-encoded JSON string in debuggee-endian byte order. Note that the register +numbers are decimal numbers, unlike the stop-reply packet, where they are written in +hex. The packet also contains expedited memory in the `memory` key. This allows the +server to expedite memory that the client is likely to use (e.g., areas around the +stack pointer, which are needed for computing backtraces) and it reduces the packet +count. + +On macOS with debugserver, we expedite the frame pointer backchain for a thread +(up to 256 entries) by reading 2 pointers worth of bytes at the frame pointer (for +the previous FP and PC), and follow the backchain. Most backtraces on macOS and +iOS now don't require us to read any memory! + +## jGetSharedCacheInfo + +### Brief + +This packet asks the remote debug stub to send the details about the inferior's +shared cache. The shared cache is a collection of common libraries/frameworks that +are mapped into every process at the same address on Darwin systems, and can be +identified by a load address and UUID. + +``` +LLDB SENDS: jGetSharedCacheInfo:{} +STUB REPLIES: ${"shared_cache_base_address":140735683125248,"shared_cache_uuid":"DDB8D70C-C9A2-3561-B2C8-BE48A4F33F96","no_shared_cache":false,"shared_cache_private_cache":false]}#00 +``` + +### Priority To Implement + +Low. When both lldb and the inferior process are running on the same computer, and lldb +and the inferior process have the same shared cache, lldb may (as an optimization) read +the shared cache out of its own memory instead of using gdb-remote read packets to read +them from the inferior process. + +## qQueryGDBServer + +### Brief + +Ask the platform for the list of gdbservers we have to connect + +### Priority To Implement + +Low. The packet is required to support connecting to gdbserver started +by the platform instance automatically. + +### Description + +If the remote platform automatically started one or more gdbserver instance (without +lldb asking it) then it have to return the list of port number or socket name for +each of them what can be used by lldb to connect to those instances. + +The data in this packet is a JSON array of JSON objects with the following keys: +* `port`: `` (optional) +* `socket_name`: `` (optional) + +Example packet: +``` +[ + { "port": 1234 }, + { "port": 5432 }, + { "socket_name": "foo" } +] +``` + +## QSetDetachOnError + +### Brief + +Sets what the server should do when the communication channel with LLDB +goes down. Either kill the inferior process (`0`) or remove breakpoints and +detach (`1`). + +### Priority To Implement + +Low. Only required if the target wants to keep the inferior process alive +when the communication channel goes down. + +### Description + +The data in this packet is a single a character, which should be `0` if the +inferior process should be killed, or `1` if the server should remove all +breakpoints and detach from the inferior. + +## jGetDyldProcessState + +### Brief + +This packet fetches the process launch state, as reported by libdyld on +Darwin systems, most importantly to indicate when the system libraries +have initialized sufficiently to safely call utility functions. + +``` +LLDB SENDS: jGetDyldProcessState +STUB REPLIES: {"process_state_value":48,"process_state string":"dyld_process_state_libSystem_initialized"} +``` + +### Priority To Implement + +Low. This packet is needed to prevent lldb's utility functions for +scanning the Objective-C class list from running very early in +process startup. diff --git a/lldb/include/lldb/Core/Debugger.h b/lldb/include/lldb/Core/Debugger.h index 418c2403d020f48429c76de2ed10795b7492d369..49ff0737acef82d2174f3b52de11d9db1e113f9c 100644 --- a/lldb/include/lldb/Core/Debugger.h +++ b/lldb/include/lldb/Core/Debugger.h @@ -89,7 +89,7 @@ public: using DebuggerList = std::vector; - static ConstString GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); /// Get the public broadcaster for this debugger. Broadcaster &GetBroadcaster() { return m_broadcaster; } diff --git a/lldb/include/lldb/Core/ThreadedCommunication.h b/lldb/include/lldb/Core/ThreadedCommunication.h index 7ebb77beb77f3d97ebb00de28548ec6594f629a1..24412b2027932db7197a24e09d8dbb854dc8d797 100644 --- a/lldb/include/lldb/Core/ThreadedCommunication.h +++ b/lldb/include/lldb/Core/ThreadedCommunication.h @@ -216,9 +216,9 @@ public: /// void SynchronizeWithReadThread(); - static ConstString &GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); - ConstString &GetBroadcasterClass() const override { + llvm::StringRef GetBroadcasterClass() const override { return GetStaticBroadcasterClass(); } diff --git a/lldb/include/lldb/Interpreter/CommandInterpreter.h b/lldb/include/lldb/Interpreter/CommandInterpreter.h index d190bcdcab4497d4327b7d481ce11b135c2895f1..70a55a77465bfe1e37ae4bb3c8d86316c0f2c03e 100644 --- a/lldb/include/lldb/Interpreter/CommandInterpreter.h +++ b/lldb/include/lldb/Interpreter/CommandInterpreter.h @@ -255,9 +255,9 @@ public: // These two functions fill out the Broadcaster interface: - static ConstString &GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); - ConstString &GetBroadcasterClass() const override { + llvm::StringRef GetBroadcasterClass() const override { return GetStaticBroadcasterClass(); } diff --git a/lldb/include/lldb/Target/Process.h b/lldb/include/lldb/Target/Process.h index 2f3a3c22422efeca205c9a9ea33c7af5fb0fb15b..aac0cf51680a9e230adad75c73a5e58728e25661 100644 --- a/lldb/include/lldb/Target/Process.h +++ b/lldb/include/lldb/Target/Process.h @@ -381,7 +381,7 @@ public: // These two functions fill out the Broadcaster interface: - static ConstString &GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); static constexpr llvm::StringRef AttachSynchronousHijackListenerName = "lldb.internal.Process.AttachSynchronous.hijack"; @@ -390,7 +390,7 @@ public: static constexpr llvm::StringRef ResumeSynchronousHijackListenerName = "lldb.internal.Process.ResumeSynchronous.hijack"; - ConstString &GetBroadcasterClass() const override { + llvm::StringRef GetBroadcasterClass() const override { return GetStaticBroadcasterClass(); } diff --git a/lldb/include/lldb/Target/Target.h b/lldb/include/lldb/Target/Target.h index 2c2e6b2831ccee7cc50840f9b5975bb1baeca246..cade60f3cc8cd9bd1f2b718c5e1f545a68f41830 100644 --- a/lldb/include/lldb/Target/Target.h +++ b/lldb/include/lldb/Target/Target.h @@ -499,9 +499,9 @@ public: // These two functions fill out the Broadcaster interface: - static ConstString &GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); - ConstString &GetBroadcasterClass() const override { + llvm::StringRef GetBroadcasterClass() const override { return GetStaticBroadcasterClass(); } diff --git a/lldb/include/lldb/Target/TargetList.h b/lldb/include/lldb/Target/TargetList.h index a0bc6f1f820b848104b179560375a3f75cbe2be5..a0cddc6b2966f5737354af1df2168fbd6301ee49 100644 --- a/lldb/include/lldb/Target/TargetList.h +++ b/lldb/include/lldb/Target/TargetList.h @@ -37,9 +37,9 @@ public: // These two functions fill out the Broadcaster interface: - static ConstString &GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); - ConstString &GetBroadcasterClass() const override { + llvm::StringRef GetBroadcasterClass() const override { return GetStaticBroadcasterClass(); } diff --git a/lldb/include/lldb/Target/Thread.h b/lldb/include/lldb/Target/Thread.h index 1efef93b17ded8cff671aef3786735056fa2d493..c17bddf4d98b85886cd53662f5c8304d58f9dafd 100644 --- a/lldb/include/lldb/Target/Thread.h +++ b/lldb/include/lldb/Target/Thread.h @@ -74,9 +74,9 @@ public: eBroadcastBitThreadSelected = (1 << 4) }; - static ConstString &GetStaticBroadcasterClass(); + static llvm::StringRef GetStaticBroadcasterClass(); - ConstString &GetBroadcasterClass() const override { + llvm::StringRef GetBroadcasterClass() const override { return GetStaticBroadcasterClass(); } diff --git a/lldb/include/lldb/Utility/Broadcaster.h b/lldb/include/lldb/Utility/Broadcaster.h index f39e677fe9ee0410653ddd28657a9ba358b5d91e..58436ddb9f26d88738d130fe653e573028890a99 100644 --- a/lldb/include/lldb/Utility/Broadcaster.h +++ b/lldb/include/lldb/Utility/Broadcaster.h @@ -39,12 +39,12 @@ namespace lldb_private { /// Debugger maintains a list of BroadcastEventSpec's and when it is made class BroadcastEventSpec { public: - BroadcastEventSpec(const ConstString &broadcaster_class, uint32_t event_bits) + BroadcastEventSpec(llvm::StringRef broadcaster_class, uint32_t event_bits) : m_broadcaster_class(broadcaster_class), m_event_bits(event_bits) {} ~BroadcastEventSpec() = default; - ConstString GetBroadcasterClass() const { return m_broadcaster_class; } + const std::string &GetBroadcasterClass() const { return m_broadcaster_class; } uint32_t GetEventBits() const { return m_event_bits; } @@ -67,7 +67,7 @@ public: bool operator<(const BroadcastEventSpec &rhs) const; private: - ConstString m_broadcaster_class; + std::string m_broadcaster_class; uint32_t m_event_bits; }; @@ -307,7 +307,7 @@ public: /// FIXME: Probably should make a ManagedBroadcaster subclass with all the /// bits needed to work with the BroadcasterManager, so that it is clearer /// how to add one. - virtual ConstString &GetBroadcasterClass() const; + virtual llvm::StringRef GetBroadcasterClass() const; lldb::BroadcasterManagerSP GetManager(); diff --git a/lldb/source/API/SBCommandInterpreter.cpp b/lldb/source/API/SBCommandInterpreter.cpp index 7b87dc507e4beacc4eccca1b60d638eab17e27cc..83c0951c56db607b6bc34e54ca042fed18375d63 100644 --- a/lldb/source/API/SBCommandInterpreter.cpp +++ b/lldb/source/API/SBCommandInterpreter.cpp @@ -512,7 +512,8 @@ SBBroadcaster SBCommandInterpreter::GetBroadcaster() { const char *SBCommandInterpreter::GetBroadcasterClass() { LLDB_INSTRUMENT(); - return CommandInterpreter::GetStaticBroadcasterClass().AsCString(); + return ConstString(CommandInterpreter::GetStaticBroadcasterClass()) + .AsCString(); } const char *SBCommandInterpreter::GetArgumentTypeAsCString( diff --git a/lldb/source/API/SBCommunication.cpp b/lldb/source/API/SBCommunication.cpp index f93898718be6c09fb1836a4e624555242d1f9f50..ee33e2abd854e869552aac85cd1195c3d884975b 100644 --- a/lldb/source/API/SBCommunication.cpp +++ b/lldb/source/API/SBCommunication.cpp @@ -170,5 +170,6 @@ SBBroadcaster SBCommunication::GetBroadcaster() { const char *SBCommunication::GetBroadcasterClass() { LLDB_INSTRUMENT(); - return ThreadedCommunication::GetStaticBroadcasterClass().AsCString(); + return ConstString(ThreadedCommunication::GetStaticBroadcasterClass()) + .AsCString(); } diff --git a/lldb/source/API/SBDebugger.cpp b/lldb/source/API/SBDebugger.cpp index fbcf30e67fc1cd52d29bffc577733f5c35f40bf2..9c662dfbf4417eef86098370ebf3ad2323eee3d1 100644 --- a/lldb/source/API/SBDebugger.cpp +++ b/lldb/source/API/SBDebugger.cpp @@ -112,7 +112,7 @@ SBDebugger &SBDebugger::operator=(const SBDebugger &rhs) { const char *SBDebugger::GetBroadcasterClass() { LLDB_INSTRUMENT(); - return Debugger::GetStaticBroadcasterClass().AsCString(); + return ConstString(Debugger::GetStaticBroadcasterClass()).AsCString(); } const char *SBDebugger::GetProgressFromEvent(const lldb::SBEvent &event, diff --git a/lldb/source/API/SBEvent.cpp b/lldb/source/API/SBEvent.cpp index cc611449e25099a21aa29c6c565389128bab553c..aa9c0ff097d45666d76085c3778e9587c21a1d4f 100644 --- a/lldb/source/API/SBEvent.cpp +++ b/lldb/source/API/SBEvent.cpp @@ -95,7 +95,8 @@ const char *SBEvent::GetBroadcasterClass() const { const Event *lldb_event = get(); if (lldb_event) - return lldb_event->GetBroadcaster()->GetBroadcasterClass().AsCString(); + return ConstString(lldb_event->GetBroadcaster()->GetBroadcasterClass()) + .AsCString(); else return "unknown class"; } diff --git a/lldb/source/API/SBProcess.cpp b/lldb/source/API/SBProcess.cpp index b80664882ebcac8eecb8229678d816af9e5be476..c73348fde3f74d13cb83abf5bfa36a97d0010f3c 100644 --- a/lldb/source/API/SBProcess.cpp +++ b/lldb/source/API/SBProcess.cpp @@ -77,7 +77,7 @@ SBProcess::~SBProcess() = default; const char *SBProcess::GetBroadcasterClassName() { LLDB_INSTRUMENT(); - return Process::GetStaticBroadcasterClass().AsCString(); + return ConstString(Process::GetStaticBroadcasterClass()).AsCString(); } const char *SBProcess::GetPluginName() { @@ -807,7 +807,7 @@ SBBroadcaster SBProcess::GetBroadcaster() const { const char *SBProcess::GetBroadcasterClass() { LLDB_INSTRUMENT(); - return Process::GetStaticBroadcasterClass().AsCString(); + return ConstString(Process::GetStaticBroadcasterClass()).AsCString(); } size_t SBProcess::ReadMemory(addr_t addr, void *dst, size_t dst_len, diff --git a/lldb/source/API/SBTarget.cpp b/lldb/source/API/SBTarget.cpp index cc9f1fdd76afaa5ab96810fd72ead766b1a08f25..75f0444f629114f94830c07fd2551dd720ddd279 100644 --- a/lldb/source/API/SBTarget.cpp +++ b/lldb/source/API/SBTarget.cpp @@ -147,7 +147,7 @@ SBModule SBTarget::GetModuleAtIndexFromEvent(const uint32_t idx, const char *SBTarget::GetBroadcasterClassName() { LLDB_INSTRUMENT(); - return Target::GetStaticBroadcasterClass().AsCString(); + return ConstString(Target::GetStaticBroadcasterClass()).AsCString(); } bool SBTarget::IsValid() const { diff --git a/lldb/source/API/SBThread.cpp b/lldb/source/API/SBThread.cpp index eb9cf063802cd47b7ec773faa5897ee06f76e195..ac3e2cd25daa946a7809e20c2da030f4dd49db2b 100644 --- a/lldb/source/API/SBThread.cpp +++ b/lldb/source/API/SBThread.cpp @@ -53,7 +53,7 @@ using namespace lldb_private; const char *SBThread::GetBroadcasterClassName() { LLDB_INSTRUMENT(); - return Thread::GetStaticBroadcasterClass().AsCString(); + return ConstString(Thread::GetStaticBroadcasterClass()).AsCString(); } // Constructors diff --git a/lldb/source/Core/Debugger.cpp b/lldb/source/Core/Debugger.cpp index 19b3cf3bbf46b152861d4f8132f34c26560cd6ea..cac4642873b772ab9f566a0f3d40b04630fc209a 100644 --- a/lldb/source/Core/Debugger.cpp +++ b/lldb/source/Core/Debugger.cpp @@ -823,8 +823,8 @@ TargetSP Debugger::FindTargetWithProcess(Process *process) { return target_sp; } -ConstString Debugger::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.debugger"); +llvm::StringRef Debugger::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.debugger"); return class_name; } @@ -846,7 +846,7 @@ Debugger::Debugger(lldb::LogOutputCallback log_callback, void *baton) m_loaded_plugins(), m_event_handler_thread(), m_io_handler_thread(), m_sync_broadcaster(nullptr, "lldb.debugger.sync"), m_broadcaster(m_broadcaster_manager_sp, - GetStaticBroadcasterClass().AsCString()), + GetStaticBroadcasterClass().str()), m_forward_listener_sp(), m_clear_once() { // Initialize the debugger properties as early as possible as other parts of // LLDB will start querying them during construction. diff --git a/lldb/source/Core/ThreadedCommunication.cpp b/lldb/source/Core/ThreadedCommunication.cpp index 7d8aae5d8ff689b96a392418472da10e385a2d95..2f3dada3ac93b198d45fcb4ac729ca4ddeb4ee22 100644 --- a/lldb/source/Core/ThreadedCommunication.cpp +++ b/lldb/source/Core/ThreadedCommunication.cpp @@ -32,8 +32,8 @@ using namespace lldb; using namespace lldb_private; -ConstString &ThreadedCommunication::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.communication"); +llvm::StringRef ThreadedCommunication::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.communication"); return class_name; } diff --git a/lldb/source/Interpreter/CommandInterpreter.cpp b/lldb/source/Interpreter/CommandInterpreter.cpp index 8c3972a2ba4ce26286869677317f6429f22295d3..4c58ecc3c1848f3d3a74f12965196c57f61d1e8b 100644 --- a/lldb/source/Interpreter/CommandInterpreter.cpp +++ b/lldb/source/Interpreter/CommandInterpreter.cpp @@ -119,15 +119,15 @@ enum { #include "InterpreterPropertiesEnum.inc" }; -ConstString &CommandInterpreter::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.commandInterpreter"); +llvm::StringRef CommandInterpreter::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.commandInterpreter"); return class_name; } CommandInterpreter::CommandInterpreter(Debugger &debugger, bool synchronous_execution) : Broadcaster(debugger.GetBroadcasterManager(), - CommandInterpreter::GetStaticBroadcasterClass().AsCString()), + CommandInterpreter::GetStaticBroadcasterClass().str()), Properties( OptionValuePropertiesSP(new OptionValueProperties("interpreter"))), IOHandlerDelegate(IOHandlerDelegate::Completion::LLDBCommand), diff --git a/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp b/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp index 65f5b1a5f1b0a2ee555a5a8540b0aa5ea9b101ca..386ba44c5ea6538c790110f3ad64eb18b3a1ad38 100644 --- a/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp +++ b/lldb/source/Plugins/SymbolFile/CTF/SymbolFileCTF.cpp @@ -342,7 +342,7 @@ SymbolFileCTF::CreateInteger(const CTFInteger &ctf_integer) { CompilerType compiler_type = m_ast->GetBasicType(basic_type); - if (basic_type != eBasicTypeVoid) { + if (basic_type != eBasicTypeVoid && basic_type != eBasicTypeBool) { // Make sure the type we got is an integer type. bool compiler_type_is_signed = false; if (!compiler_type.IsIntegerType(compiler_type_is_signed)) @@ -802,7 +802,8 @@ size_t SymbolFileCTF::ParseFunctions(CompileUnit &cu) { } Type *arg_type = ResolveTypeUID(arg_uid); - arg_types.push_back(arg_type->GetFullCompilerType()); + arg_types.push_back(arg_type ? arg_type->GetFullCompilerType() + : CompilerType()); } if (symbol) { @@ -813,8 +814,9 @@ size_t SymbolFileCTF::ParseFunctions(CompileUnit &cu) { // Create function type. CompilerType func_type = m_ast->CreateFunctionType( - ret_type->GetFullCompilerType(), arg_types.data(), arg_types.size(), - is_variadic, 0, clang::CallingConv::CC_C); + ret_type ? ret_type->GetFullCompilerType() : CompilerType(), + arg_types.data(), arg_types.size(), is_variadic, 0, + clang::CallingConv::CC_C); lldb::user_id_t function_type_uid = m_types.size() + 1; TypeSP type_sp = MakeType(function_type_uid, symbol->GetName(), 0, nullptr, diff --git a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp index 2621f682011b41e5cb715d0a75c2192b60e348dc..662da313af598954aa41282fb8b980a2d5c78d33 100644 --- a/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp +++ b/lldb/source/Plugins/TypeSystem/Clang/TypeSystemClang.cpp @@ -838,8 +838,11 @@ lldb::BasicType TypeSystemClang::GetBasicTypeEnumeration(llvm::StringRef name) { {"__int128_t", eBasicTypeInt128}, {"__uint128_t", eBasicTypeUnsignedInt128}, - // Miscellaneous + // "bool" {"bool", eBasicTypeBool}, + {"_Bool", eBasicTypeBool}, + + // Miscellaneous {"float", eBasicTypeFloat}, {"double", eBasicTypeDouble}, {"long double", eBasicTypeLongDouble}, diff --git a/lldb/source/Target/Process.cpp b/lldb/source/Target/Process.cpp index 606518ca5412671643c99afcffda927e72d822a1..30c240b064b59ce10c8abd11ecf5d49007b51992 100644 --- a/lldb/source/Target/Process.cpp +++ b/lldb/source/Target/Process.cpp @@ -408,8 +408,8 @@ ProcessSP Process::FindPlugin(lldb::TargetSP target_sp, return process_sp; } -ConstString &Process::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.process"); +llvm::StringRef Process::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.process"); return class_name; } @@ -423,7 +423,7 @@ Process::Process(lldb::TargetSP target_sp, ListenerSP listener_sp, const UnixSignalsSP &unix_signals_sp) : ProcessProperties(this), Broadcaster((target_sp->GetDebugger().GetBroadcasterManager()), - Process::GetStaticBroadcasterClass().AsCString()), + Process::GetStaticBroadcasterClass().str()), m_target_wp(target_sp), m_public_state(eStateUnloaded), m_private_state(eStateUnloaded), m_private_state_broadcaster(nullptr, diff --git a/lldb/source/Target/Target.cpp b/lldb/source/Target/Target.cpp index 09b0ac42631d1a3529e5e02a6b5c72bf69898bd5..aa4895bb5a6d653cdadc4798f496c4c0ecf9bf5b 100644 --- a/lldb/source/Target/Target.cpp +++ b/lldb/source/Target/Target.cpp @@ -87,8 +87,8 @@ const Target::Arch &Target::Arch::operator=(const ArchSpec &spec) { return *this; } -ConstString &Target::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.target"); +llvm::StringRef Target::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.target"); return class_name; } @@ -96,7 +96,7 @@ Target::Target(Debugger &debugger, const ArchSpec &target_arch, const lldb::PlatformSP &platform_sp, bool is_dummy_target) : TargetProperties(this), Broadcaster(debugger.GetBroadcasterManager(), - Target::GetStaticBroadcasterClass().AsCString()), + Target::GetStaticBroadcasterClass().str()), ExecutionContextScope(), m_debugger(debugger), m_platform_sp(platform_sp), m_mutex(), m_arch(target_arch), m_images(this), m_section_load_history(), m_breakpoint_list(false), m_internal_breakpoint_list(true), diff --git a/lldb/source/Target/TargetList.cpp b/lldb/source/Target/TargetList.cpp index b5d308739d0facdbd78d8d3eb9eec5bdd17d0d44..10467753666f8814065d6af4f784def11db2deed 100644 --- a/lldb/source/Target/TargetList.cpp +++ b/lldb/source/Target/TargetList.cpp @@ -29,15 +29,15 @@ using namespace lldb; using namespace lldb_private; -ConstString &TargetList::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.targetList"); +llvm::StringRef TargetList::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.targetList"); return class_name; } // TargetList constructor TargetList::TargetList(Debugger &debugger) : Broadcaster(debugger.GetBroadcasterManager(), - TargetList::GetStaticBroadcasterClass().AsCString()), + TargetList::GetStaticBroadcasterClass().str()), m_target_list(), m_target_list_mutex(), m_selected_target_idx(0) { CheckInWithManager(); } diff --git a/lldb/source/Target/Thread.cpp b/lldb/source/Target/Thread.cpp index 412e44ede9c13b4eb2114ce9932291d0dad1f62b..e75f5a356cec2fe02133ddd7e3262ebd44d7f84e 100644 --- a/lldb/source/Target/Thread.cpp +++ b/lldb/source/Target/Thread.cpp @@ -205,15 +205,15 @@ Thread::ThreadEventData::GetStackFrameFromEvent(const Event *event_ptr) { // Thread class -ConstString &Thread::GetStaticBroadcasterClass() { - static ConstString class_name("lldb.thread"); +llvm::StringRef Thread::GetStaticBroadcasterClass() { + static constexpr llvm::StringLiteral class_name("lldb.thread"); return class_name; } Thread::Thread(Process &process, lldb::tid_t tid, bool use_invalid_index_id) : ThreadProperties(false), UserID(tid), Broadcaster(process.GetTarget().GetDebugger().GetBroadcasterManager(), - Thread::GetStaticBroadcasterClass().AsCString()), + Thread::GetStaticBroadcasterClass().str()), m_process_wp(process.shared_from_this()), m_stop_info_sp(), m_stop_info_stop_id(0), m_stop_info_override_stop_id(0), m_should_run_before_public_stop(false), diff --git a/lldb/source/Utility/Broadcaster.cpp b/lldb/source/Utility/Broadcaster.cpp index 12903edc36b1b98675ec5d3bde2c4a8a8b3c5a3a..bd65ffd86a1d0f0d69a7ab6d3b4011086904dfe8 100644 --- a/lldb/source/Utility/Broadcaster.cpp +++ b/lldb/source/Utility/Broadcaster.cpp @@ -373,8 +373,8 @@ void Broadcaster::BroadcasterImpl::RestoreBroadcaster() { m_hijacking_masks.pop_back(); } -ConstString &Broadcaster::GetBroadcasterClass() const { - static ConstString class_name("lldb.anonymous"); +llvm::StringRef Broadcaster::GetBroadcasterClass() const { + static constexpr llvm::StringLiteral class_name("lldb.anonymous"); return class_name; } diff --git a/lldb/test/API/macosx/ctf/Makefile b/lldb/test/API/macosx/ctf/Makefile index afe6ab1b5db06b05b8a62b8700a60473f7f7b57f..0857e234837e543811bb2c68f7ab82c59634b587 100644 --- a/lldb/test/API/macosx/ctf/Makefile +++ b/lldb/test/API/macosx/ctf/Makefile @@ -4,7 +4,7 @@ MAKE_DSYM := YES ifeq "$(COMPRESS_CTF)" "YES" COMPRESS := -c else - COMPRESS := + COMPRESS := endif all: a.out a.ctf diff --git a/lldb/test/API/macosx/ctf/TestCTF.py b/lldb/test/API/macosx/ctf/TestCTF.py index f5fd29f6ed968f7b74102b0cde0a7435605cea51..fed3a8886dd30c4f17a9ed7ad4974edbf8368a05 100644 --- a/lldb/test/API/macosx/ctf/TestCTF.py +++ b/lldb/test/API/macosx/ctf/TestCTF.py @@ -53,6 +53,7 @@ class TestCTF(TestBase): "[2] = 'b'", "[3] = 'c'", 'u = (i = 1, s = "")', + "b = false", "f = 0x0000000000000000", ], ) diff --git a/lldb/test/API/macosx/ctf/test.c b/lldb/test/API/macosx/ctf/test.c index 358006646e766e6a7af15ca333592152eb3e765c..a15f7a5161334f098710443f98872e1dd650a60a 100644 --- a/lldb/test/API/macosx/ctf/test.c +++ b/lldb/test/API/macosx/ctf/test.c @@ -1,3 +1,4 @@ +#include #include struct ForwardDecl; @@ -24,6 +25,7 @@ typedef struct MyNestedStruct { char a[4]; MyEnumT e; MyUnionT u; + _Bool b; } MyNestedStructT; typedef struct MyStruct { @@ -54,6 +56,7 @@ void populate(MyInt i) { foo.n.a[2] = 'c'; foo.n.a[3] = 'd'; foo.n.e = eOne; + foo.n.b = false; foo.f = NULL; forward = NULL; bar.b = i; diff --git a/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst b/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst index 5dd8df231d3024250ae336247561142362eda078..7d4e06ebf0493c4ae1879576f16328a1c6eaa56b 100644 --- a/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst +++ b/llvm/docs/AMDGPUDwarfExtensionsForHeterogeneousDebugging.rst @@ -2487,7 +2487,7 @@ type. .. note:: Could also consider adding ``DW_OP_LLVM_aspace_breg0, - DW_OP_LLVM_aspace_breg1, ..., DW_OP_LLVM_aspace_bref31`` which would save + DW_OP_LLVM_aspace_breg1, ..., DW_OP_LLVM_aspace_breg31`` which would save encoding size. .. _amdgpu-dwarf-register-location-description-operations: diff --git a/llvm/docs/GettingInvolved.rst b/llvm/docs/GettingInvolved.rst index a4247796cb65914c66c5df41f198dc3552496dfb..93be3bd1d8545e235ac610de95df989926f6dc0e 100644 --- a/llvm/docs/GettingInvolved.rst +++ b/llvm/docs/GettingInvolved.rst @@ -228,7 +228,8 @@ what to add to your calendar invite. - `Meeting details/agenda `__ * - Floating Point Working Group - Every 3rd Wednesday of the month - - `gcal `__ + - `ics `__ + `gcal `__ - `Meeting details/agenda: `__ .. _office-hours: diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index 9592929d79feb42c90474505f0ee1f12e334d35d..0e87a8e2ace0e294e89fa3bd2b9d2fef863a6130 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -12517,7 +12517,7 @@ This instruction requires several arguments: ``llvm::GuaranteedTailCallOpt`` is ``true``, or the calling convention is ``tailcc`` - `Platform-specific constraints are - met. `_ + met. `_ #. The optional ``notail`` marker indicates that the optimizers should not add ``tail`` or ``musttail`` markers to the call. It is used to prevent tail diff --git a/llvm/docs/MemoryModelRelaxationAnnotations.rst b/llvm/docs/MemoryModelRelaxationAnnotations.rst new file mode 100644 index 0000000000000000000000000000000000000000..c79675d30f62083762d78c018ece1131e4320ea1 --- /dev/null +++ b/llvm/docs/MemoryModelRelaxationAnnotations.rst @@ -0,0 +1,481 @@ +=================================== +Memory Model Relaxation Annotations +=================================== + +.. contents:: + :local: + +Introduction +============ + +Memory Model Relaxation Annotations (MMRAs) are target-defined properties +on instructions that can be used to selectively relax constraints placed +by the memory model. For example: + +* The use of ``VulkanMemoryModel`` in a SPIRV program allows certain + memory operations to be reordered across ``acquire`` or ``release`` + operations. +* OpenCL APIs expose primitives to only fence a specific set of address + spaces. Carrying that information to the backend can enable the + use of faster synchronization instructions, rather than fencing all + address spaces everytime. + +MMRAs offer an opt-in system for targets to relax the default LLVM +memory model. +As such, they are attached to an operation using LLVM metadata which +can always be dropped without affecting correctness. + +Definitions +=========== + +memory operation + A load, a store, an atomic, or a function call that is marked as + accessing memory. + +synchronizing operation + An instruction that synchronizes memory with other threads (e.g. + an atomic or a fence). + +tag + Metadata attached to a memory or synchronizing operation + that represents some target-defined property regarding memory + synchronization. + + An operation may have multiple tags that each represent a different + property. + + A tag is composed of a pair of metadata string: a *prefix* and a *suffix*. + + In LLVM IR, the pair is represented using a metadata tuple. + In other cases (comments, documentation, etc.), we may use the + ``prefix:suffix`` notation. + For example: + + .. code-block:: + :caption: Example: Tags in Metadata + + !0 = !{!"scope", !"workgroup"} # scope:workgroup + !1 = !{!"scope", !"device"} # scope:device + !2 = !{!"scope", !"system"} # scope:system + + .. note:: + + The only semantics relevant to the optimizer is the + "compatibility" relation defined below. All other + semantics are target defined. + + Tags can also be organised in lists to allow operations + to specify all of the tags they belong to. Such a list + is referred to as a "set of tags". + + .. code-block:: + :caption: Example: Set of Tags in Metadata + + !0 = !{!"scope", !"workgroup"} + !1 = !{!"sync-as", !"private"} + !2 = !{!0, !2} + + .. note:: + + If an operation does not have MMRA metadata, it's treated as if + it has an empty list (``!{}``) of tags. + + Note that it is not an error if a tag is not recognized by the + instruction it is applied to, or by the current target. + Such tags are simply ignored. + + Both synchronizing operations and memory operations can have + zero or more tags attached to them using the ``!mmra`` syntax. + + For the sake of readability in examples below, + we use a (non-functional) short syntax to represent MMMRA metadata: + + .. code-block:: + :caption: Short Syntax Example + + store %ptr1 # foo:bar + store %ptr1 !mmra !{!"foo", !"bar"} + + These two notations can be used in this document and are strictly + equivalent. However, only the second version is functional. + +compatibility + Two sets of tags are said to be *compatible* iff, for every unique + tag prefix P present in at least one set: + + - the other set contains no tag with prefix P, or + - at least one tag with prefix P is common to both sets. + + The above definition implies that an empty set is always compatible + with any other set. This is an important property as it ensures that + if a transform drops the metadata on an operation, it can never affect + correctness. In other words, the memory model cannot be relaxed further + by deleting metadata from instructions. + +.. _HappensBefore: + +The *happens-before* Relation +============================== + +Compatibility checks can be used to opt out of the *happens-before* relation +established between two instructions. + +Ordering + When two instructions' metadata are not compatible, any program order + between them are not in *happens-before*. + + For example, consider two tags ``foo:bar`` and + ``foo:baz`` exposed by a target: + + .. code-block:: + + A: store %ptr1 # foo:bar + B: store %ptr2 # foo:baz + X: store atomic release %ptr3 # foo:bar + + In the above figure, ``A`` is compatible with ``X``, and hence ``A`` + happens-before ``X``. But ``B`` is not compatible with + ``X``, and hence it is not happens-before ``X``. + +Synchronization + If an synchronizing operation has one or more tags, then whether it + synchronizes-with and participates in the ``seq_cst`` order with + other operations is target dependent. + + Whether the following example synchronizes with another sequence depends + on the target-defined semantics of ``foo:bar`` and ``foo:bux``. + + .. code-block:: + + fence release # foo:bar + store atomic %ptr1 # foo:bux + +Examples +-------- + +Example 1: + .. code-block:: + + A: store ptr addrspace(1) %ptr2 # sync-as:1 vulkan:nonprivate + B: store atomic release ptr addrspace(1) %ptr3 # sync-as:0 vulkan:nonprivate + + A and B are not ordered relative to each other + (no *happens-before*) because their sets of tags are not compatible. + + Note that the ``sync-as`` value does not have to match the ``addrspace`` value. + e.g. In Example 1, a store-release to a location in ``addrspace(1)`` wants to + only synchronize with operations happening in ``addrspace(0)``. + +Example 2: + .. code-block:: + + A: store ptr addrspace(1) %ptr2 # sync-as:1 vulkan:nonprivate + B: store atomic release ptr addrspace(1) %ptr3 # sync-as:1 vulkan:nonprivate + + The ordering of A and B is unaffected because their set of tags are + compatible. + + Note that A and B may or may not be in *happens-before* due to other reasons. + +Example 3: + .. code-block:: + + A: store ptr addrspace(1) %ptr2 # sync-as:1 vulkan:nonprivate + B: store atomic release ptr addrspace(1) %ptr3 # vulkan:nonprivate + + The ordering of A and B is unaffected because their set of tags are + compatible. + +Example 4: + .. code-block:: + + A: store ptr addrspace(1) %ptr2 # sync-as:1 + B: store atomic release ptr addrspace(1) %ptr3 # sync-as:2 + + A and B do not have to be ordered relative to each other + (no *happens-before*) because their sets of tags are not compatible. + +Use-cases +========= + +SPIRV ``NonPrivatePointer`` +--------------------------- + +MMRAs can support the SPIRV capability +``VulkanMemoryModel``, where synchronizing operations only affect +memory operations that specify ``NonPrivatePointer`` semantics. + +The example below is generated from a SPIRV program using the +following recipe: + +- Add ``vulkan:nonprivate`` to every synchronizing operation. +- Add ``vulkan:nonprivate`` to every non-atomic memory operation + that is marked ``NonPrivatePointer``. +- Add ``vulkan:private`` to tags of every non-atomic memory operation + that is not marked ``NonPrivatePointer``. + +.. code-block:: + + Thread T1: + A: store %ptr1 # vulkan:nonprivate + B: store %ptr2 # vulkan:private + X: store atomic release %ptr3 # vulkan:nonprivate + + Thread T2: + Y: load atomic acquire %ptr3 # vulkan:nonprivate + C: load %ptr2 # vulkan:private + D: load %ptr1 # vulkan:nonprivate + +Compatibility ensures that operation ``A`` is ordered +relative to ``X`` while operation ``D`` is ordered relative to ``Y``. +If ``X`` synchronizes with ``Y``, then ``A`` happens-before ``D``. +No such relation can be inferred about operations ``B`` and ``C``. + +.. note:: + The `Vulkan Memory Model `_ + considers all atomic operation non-private. + + Whether ``vulkan:nonprivate`` would be specified on atomic operations is + an implementation detail, as an atomic operation is always ``nonprivate``. + The implementation may choose to be explicit and emit IR with + ``vulkan:nonprivate`` on every atomic operation, or it could choose to + only emit ``vulkan::private`` and assume ``vulkan:nonprivate`` + by default. + +Operations marked with ``vulkan:private`` effectively opt out of the +happens-before order in a SPIRV program since they are incompatible +with every synchronizing operation. Note that SPIRV operations that +are not marked ``NonPrivatePointer`` are not entirely private to the +thread --- they are implicitly synchronized at the start or end of a +thread by the Vulkan *system-synchronizes-with* relationship. This +example assumes that the target-defined semantics of +``vulkan:private`` correctly implements this property. + +This scheme is general enough to express the interoperability of SPIRV +programs with other environments. + +.. code-block:: + + Thread T1: + A: store %ptr1 # vulkan:nonprivate + X: store atomic release %ptr2 # vulkan:nonprivate + + Thread T2: + Y: load atomic acquire %ptr2 # foo:bar + B: load %ptr1 + +In the above example, thread ``T1`` originates from a SPIRV program +while thread ``T2`` originates from a non-SPIRV program. Whether ``X`` +can synchronize with ``Y`` is target defined. If ``X`` synchronizes +with ``Y``, then ``A`` happens before ``B`` (because A/X and +Y/B are compatible). + +Implementation Example +~~~~~~~~~~~~~~~~~~~~~~ + +Consider the implementation of SPIRV ``NonPrivatePointer`` on a target +where all memory operations are cached, and the entire cache is +flushed or invalidated at a ``release`` or ``acquire`` respectively. A +possible scheme is that when translating a SPIRV program, memory +operations marked ``NonPrivatePointer`` should not be cached, and the +cache contents should not be touched during an ``acquire`` and +``release`` operation. + +This could be implemented using the tags that share the ``vulkan:`` prefix, +as follows: + +- For memory operations: + + - Operations with ``vulkan:nonprivate`` should bypass the cache. + - Operations with ``vulkan:private`` should be cached. + - Operations that specify neither or both should conservatively + bypass the cache to ensure correctness. + +- For synchronizing operations: + + - Operations with ``vulkan:nonprivate`` should not flush or + invalidate the cache. + - Operations with ``vulkan:private`` should flush or invalidate the cache. + - Operations that specify neither or both should conservatively + flush or invalidate the cache to ensure correctness. + +.. note:: + In such an implementation, dropping the metadata on an operation, while + not affecting correctness, may have big performance implications. + e.g. an operation bypasses the cache when it shouldn't. + +Memory Types +------------ + +MMRAs may express the selective synchronization of +different memory types. + +As an example, a target may expose an ``sync-as:`` tag to +pass information about which address spaces are synchronized by the +execution of a synchronizing operation. + +.. note:: + Address spaces are used here as a common example, but this concept + can apply for other "memory types". What "memory types" means here is + up to the target. + +.. code-block:: + + # let 1 = global address space + # let 3 = local address space + + Thread T1: + A: store %ptr1 # sync-as:1 + B: store %ptr2 # sync-as:3 + X: store atomic release ptr addrspace(0) %ptr3 # sync-as:3 + + Thread T2: + Y: load atomic acquire ptr addrspace(0) %ptr3 # sync-as:3 + C: load %ptr2 # sync-as:3 + D: load %ptr1 # sync-as:1 + +In the above figure, ``X`` and ``Y`` are atomic operations on a +location in the ``global`` address space. If ``X`` synchronizes with +``Y``, then ``B`` happens-before ``C`` in the ``local`` address +space. But no such statement can be made about operations ``A`` and +``D``, although they are peformed on a location in the ``global`` +address space. + +Implementation Example: Adding Address Space Information to Fences +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Languages such as OpenCL C provide fence operations such as +``atomic_work_item_fence`` that can take an explicit address +space to fence. + +By default, LLVM has no means to carry that information in the IR, so +the information is lost during lowering to LLVM IR. This means that +targets such as AMDGPU have to conservatively emit instructions to +fence all address spaces in all cases, which can have a noticeable +performance impact in high-performance applications. + +MMRAs may be used to preserve that information at the IR level, all the +way through code generation. For example, a fence that only affects the +global address space ``addrspace(1)`` may be lowered as + +.. code-block:: + + fence release # sync-as:1 + +and the target may use the presence of ``sync-as:1`` to infer that it +must only emit instruction to fence the global address space. + +Note that as MMRAs are opt in, a fence that does not have MMRA metadata +could still be lowered conservatively, so this optimization would only +apply if the front-end emits the MMRA metadata on the fence instructions. + +Additional Topics +================= + +.. note:: + + The following sections are informational. + +Performance Impact +------------------ + +MMRAs are a way to capture optimization opportunities in the program. +But when an operation mentions no tags or conflicting tags, +the target may need to produce conservative code to ensure correctness +at the cost of performance. This can happen in the following situations: + +1. When a target first introduces MMRAs, the + frontend might not have been updated to emit them. +2. An optimization may drop MMRA metadata. +3. An optimization may add arbitrary tags to an operation. + +Note that targets can always choose to ignore (or even drop) MMRAs +and revert to the default behavior/codegen heuristics without +affecting correctness. + +Consequences of the Absence of *happens-before* +----------------------------------------------- + +In the :ref:`happens-before` section, we defined how an +*happens-before* relation between two instruction can be broken +by leveraging compatibility between MMRAs. When the instructions +are incompatible and there is no *happens-before* relation, we say +that the instructions "do not have to be ordered relative to each +other". + +"Ordering" in this context is a very broad term which covers both +static and runtime aspects. + +When there is no ordering constraint, we *could* statically reorder +the instructions in an optimizer transform if the reordering does +not break other constraints as single location coherence. +Static reordering is one consequence of breaking *happens-before*, +but is not the most interesting one. + +Run-time consequences are more interesting. When there is an +*happens-before* relation between instructions, the target has to emit +synchronization code to ensure other threads will observe the effects of +the instructions in the right order. + +For instance, the target may have to wait for previous loads & stores to +finish before starting a fence-release, or there may be a need to flush a +memory cache before executing the next instruction. +In the absence of *happens-before*, there is no such requirement and +no waiting or flushing is required. This may noticeably speed up +execution in some cases. + +Combining Operations +-------------------- + +If a pass can combine multiple memory or synchronizing operations +into one, it needs to be able to combine MMRAs. One possible way to +achieve this is by doing a prefix-wise union of the tag sets. + +Let A and B be two tags set, and U be the prefix-wise union of A and B. +For every unique tag prefix P present in A or B: + +* If either A or B has no tags with prefix P, no tags with prefix + P are added to U. +* If both A and B have at least one tag with prefix P, all tags with prefix + P from both sets are added to U. + +Passes should avoid aggressively combining MMRAs, as this can result +in significant losses of information. While this cannot affect +correctness, it may affect performance. + +As a general rule of thumb, common passes such as SimplifyCFG that +aggressively combine/reorder operations should only combine +instructions that have identical sets of tags. +Passes that combine less frequently, or that are well aware of the cost +of combining the MMRAs can use the prefix-wise union described above. + +Examples: + +.. code-block:: + + A: store release %ptr1 # foo:x, foo:y, bar:x + B: store release %ptr2 # foo:x, bar:y + + # Unique prefixes P = [foo, bar] + # "foo:x" is common to A and B so it's added to U. + # "bar:x" != "bar:y" so it's not added to U. + U: store release %ptr3 # foo:x + +.. code-block:: + + A: store release %ptr1 # foo:x, foo:y + B: store release %ptr2 # foo:x, bux:y + + # Unique prefixes P = [foo, bux] + # "foo:x" is common to A and B so it's added to U. + # No tags have the prefix "bux" in A. + U: store release %ptr3 # foo:x + +.. code-block:: + + A: store release %ptr1 + B: store release %ptr2 # foo:x, bar:y + + # Unique prefixes P = [foo, bar] + # No tags with "foo" or "bar" in A, so no tags added. + U: store release %ptr3 diff --git a/llvm/docs/Reference.rst b/llvm/docs/Reference.rst index 3a1d1665be439e287460bd27547609d2671fdb08..1661c8c533db1d2cedb59800a7c1e486ff012b55 100644 --- a/llvm/docs/Reference.rst +++ b/llvm/docs/Reference.rst @@ -39,6 +39,7 @@ LLVM and API reference documentation. PDB/index PointerAuth ScudoHardenedAllocator + MemoryModelRelaxationAnnotations MemTagSanitizer Security SecurityTransparencyReports @@ -194,6 +195,9 @@ Additional Topics :doc:`ScudoHardenedAllocator` A library that implements a security-hardened `malloc()`. +:doc:`MemoryModelRelaxationAnnotations` + Target-defined relaxation to LLVM's concurrency model. + :doc:`MemTagSanitizer` Security hardening for production code aiming to mitigate memory related vulnerabilities. Based on the Armv8.5-A Memory Tagging Extension. diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 580dc512d9690cbd22b536310ac2d60826826c06..6ef6ec20da671da0b506e6648431b22cc6cfc10a 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -50,6 +50,8 @@ Update on required toolchains to build LLVM Changes to the LLVM IR ---------------------- +- Added Memory Model Relaxation Annotations (MMRAs). + Changes to LLVM infrastructure ------------------------------ @@ -133,7 +135,7 @@ Changes to the C API functions for accessing the values in a blockaddress constant. * Added ``LLVMConstStringInContext2`` function, which better matches the C++ - API by using ``size_t`` for string length. Deprecated ``LLVMConstStringInContext``. + API by using ``size_t`` for string length. Deprecated ``LLVMConstStringInContext``. * Added the following functions for accessing a function's prefix data: diff --git a/llvm/docs/Security.rst b/llvm/docs/Security.rst index 7f3493d4563bb2ac8a5d381d601893a04f84e9d0..9140923e5e8c9d6bf02a17f0836fd455f2cd4660 100644 --- a/llvm/docs/Security.rst +++ b/llvm/docs/Security.rst @@ -53,9 +53,9 @@ username for an individual isn't available, the brackets will be empty. * Peter Smith (ARM) [@smithp35] * Pietro Albini (Ferrous Systems; Rust) [@pietroalbini] * Serge Guelton (Mozilla) [@serge-sans-paille] -* Sergey Maslov (Intel) [@smaslov-intel] * Shayne Hiet-Block (Microsoft) [@GreatKeeper] * Tim Penge (Sony) [] +* Will Huhn (Intel) [@wphuhn-intel] Criteria -------- diff --git a/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp b/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp index b11d875c6f2d06b1aedc128606cdb4bffcafb8aa..7c896ab6d88e07fb7aa54acd9bcd774b280efb8e 100644 --- a/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp +++ b/llvm/examples/OrcV2Examples/LLJITWithRemoteDebugging/RemoteJITUtils.cpp @@ -129,7 +129,7 @@ launchLocalExecutor(StringRef ExecutablePath) { close(FromExecutor[WriteEnd]); auto EPC = SimpleRemoteEPC::Create( - std::make_unique(), + std::make_unique(std::nullopt), SimpleRemoteEPC::Setup(), FromExecutor[ReadEnd], ToExecutor[WriteEnd]); if (!EPC) @@ -201,7 +201,7 @@ connectTCPSocket(StringRef NetworkAddress) { return CreateErr(toString(SockFD.takeError())); return SimpleRemoteEPC::Create( - std::make_unique(), + std::make_unique(std::nullopt), SimpleRemoteEPC::Setup(), *SockFD); } diff --git a/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp b/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp index 0d97d379d2279e1a68e022d006ee9379699d2825..1659e5c5c8b40bf0b8b41ea4696f5d340f563e50 100644 --- a/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp +++ b/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp @@ -49,7 +49,9 @@ public: if (!DL) return DL.takeError(); - auto EPC = SelfExecutorProcessControl::Create(); + auto EPC = SelfExecutorProcessControl::Create( + nullptr, + std::make_unique(std::nullopt)); if (!EPC) return EPC.takeError(); @@ -116,14 +118,6 @@ private: std::move(ISMBuilder)) { MainJD.addGenerator(std::move(ProcessSymbolsGenerator)); this->CODLayer.setImplMap(&Imps); - this->ES->setDispatchTask( - [this](std::unique_ptr T) { - CompileThreads.async( - [UnownedT = T.release()]() { - std::unique_ptr T(UnownedT); - T->run(); - }); - }); ExitOnErr(S.addSpeculationRuntime(MainJD, Mangle)); LocalCXXRuntimeOverrides CXXRuntimeoverrides; ExitOnErr(CXXRuntimeoverrides.enable(MainJD, Mangle)); diff --git a/llvm/include/llvm/Analysis/Loads.h b/llvm/include/llvm/Analysis/Loads.h index 0926093bba99deffaca343036800fa87e4b9216b..a8d954b9872d97b24b95b5b2453be75f93617218 100644 --- a/llvm/include/llvm/Analysis/Loads.h +++ b/llvm/include/llvm/Analysis/Loads.h @@ -173,14 +173,17 @@ Value *findAvailablePtrLoadStore(const MemoryLocation &Loc, Type *AccessTy, unsigned MaxInstsToScan, BatchAAResults *AA, bool *IsLoadCSE, unsigned *NumScanedInst); -/// Returns true if a pointer value \p A can be replace with another pointer -/// value \B if they are deemed equal through some means (e.g. information from +/// Returns true if a pointer value \p From can be replaced with another pointer +/// value \To if they are deemed equal through some means (e.g. information from /// conditions). -/// NOTE: the current implementations is incomplete and unsound. It does not -/// reject all invalid cases yet, but will be made stricter in the future. In -/// particular this means returning true means unknown if replacement is safe. -bool canReplacePointersIfEqual(Value *A, Value *B, const DataLayout &DL, - Instruction *CtxI); +/// NOTE: The current implementation allows replacement in Icmp and PtrToInt +/// instructions, as well as when we are replacing with a null pointer. +/// Additionally it also allows replacement of pointers when both pointers have +/// the same underlying object. +bool canReplacePointersIfEqual(const Value *From, const Value *To, + const DataLayout &DL); +bool canReplacePointersInUseIfEqual(const Use &U, const Value *To, + const DataLayout &DL); } #endif diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 58c69ac939763a40ddda9ae07a0714cd8f1b37b0..1c76821fe5e4abf4cfc1a71e5d0abe04c6a90ce7 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -1267,7 +1267,7 @@ public: TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr, const TargetLibraryInfo *TLibInfo = nullptr) const; diff --git a/llvm/include/llvm/Analysis/ValueTracking.h b/llvm/include/llvm/Analysis/ValueTracking.h index a2fa8f6064e11667ca2e260c3b59d1db1e1d309c..571e44cdac2650ae8195138e3beda2e799ed771f 100644 --- a/llvm/include/llvm/Analysis/ValueTracking.h +++ b/llvm/include/llvm/Analysis/ValueTracking.h @@ -131,7 +131,8 @@ bool isKnownNonZero(const Value *V, const SimplifyQuery &Q, unsigned Depth = 0); /// Currently can recoginze Value pair: /// 1: if X = sub (0, Y) or Y = sub (0, X) /// 2: if X = sub (A, B) and Y = sub (B, A) -bool isKnownNegation(const Value *X, const Value *Y, bool NeedNSW = false); +bool isKnownNegation(const Value *X, const Value *Y, bool NeedNSW = false, + bool AllowPoison = true); /// Returns true if the give value is known to be non-negative. bool isKnownNonNegative(const Value *V, const SimplifyQuery &SQ, diff --git a/llvm/include/llvm/Analysis/VectorUtils.h b/llvm/include/llvm/Analysis/VectorUtils.h index c6eb66cc9660ca61ec61d92972d44c033f9618b9..424b73e375b5bc82eb29605694004ba382103fc8 100644 --- a/llvm/include/llvm/Analysis/VectorUtils.h +++ b/llvm/include/llvm/Analysis/VectorUtils.h @@ -301,7 +301,7 @@ MDNode *intersectAccessGroups(const Instruction *Inst1, const Instruction *Inst2); /// Specifically, let Kinds = [MD_tbaa, MD_alias_scope, MD_noalias, MD_fpmath, -/// MD_nontemporal, MD_access_group]. +/// MD_nontemporal, MD_access_group, MD_mmra]. /// For K in Kinds, we get the MDNode for K from each of the /// elements of VL, compute their "intersection" (i.e., the most generic /// metadata value that covers all of the individual values), and set I's diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index 06a19c75cf873a340bf78573dfc40caa417229e9..4a3a03dc5ad488212d600c9bde2cce6768206fa5 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -892,7 +892,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Opd1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Opd2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr) { // Check if any of the operands are vector operands. const TargetLoweringBase *TLI = getTLI(); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h index 29a46f04fd5de5a34e4f05432c7a278faa3d49a7..8eddc6a6a531b42ebf6d868df5ea545ef6262aeb 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutor.h @@ -217,6 +217,8 @@ enum { /// - OpIdx(ULEB128) - Operand index /// - Ty(1) - Expected type GIM_CheckType, + /// GIM_CheckType but InsnID is omitted and defaults to zero. + GIM_RootCheckType, /// Check the type of a pointer to any address space. /// - InsnID(ULEB128) - Instruction ID @@ -229,6 +231,8 @@ enum { /// - OpIdx(ULEB128) - Operand index /// - RC(2) - Expected register bank (specified as a register class) GIM_CheckRegBankForClass, + /// GIM_CheckRegBankForClass but InsnID is omitted and defaults to zero. + GIM_RootCheckRegBankForClass, /// Check the operand matches a complex predicate /// - InsnID(ULEB128) - Instruction ID @@ -278,9 +282,9 @@ enum { /// - OpIdx(ULEB128) - Operand index GIM_CheckIsImm, - /// Check if the specified operand is safe to fold into the current - /// instruction. - /// - InsnID(ULEB128) - Instruction ID + /// Checks if the matched instructions numbered [1, 1+N) can + /// be folded into the root (inst 0). + /// - Num(1) GIM_CheckIsSafeToFold, /// Check the specified operands are identical. @@ -338,6 +342,8 @@ enum { /// - InsnID(ULEB128) - Instruction ID to define /// - Opcode(2) - The new opcode to use GIR_BuildMI, + /// GIR_BuildMI but InsnID is omitted and defaults to zero. + GIR_BuildRootMI, /// Builds a constant and stores its result in a TempReg. /// - TempRegID(ULEB128) - Temp Register to define. @@ -349,6 +355,8 @@ enum { /// - OldInsnID(ULEB128) - Instruction ID to copy from /// - OpIdx(ULEB128) - The operand to copy GIR_Copy, + /// GIR_Copy but with both New/OldInsnIDs omitted and defaulting to zero. + GIR_RootToRootCopy, /// Copy an operand to the specified instruction or add a zero register if the /// operand is a zero immediate. @@ -506,6 +514,9 @@ enum { /// description. /// - InsnID(ULEB128) - Instruction ID to modify GIR_ConstrainSelectedInstOperands, + /// GIR_ConstrainSelectedInstOperands but InsnID is omitted and defaults to + /// zero. + GIR_RootConstrainSelectedInstOperands, /// Merge all memory operands into instruction. /// - InsnID(ULEB128) - Instruction ID to modify @@ -518,6 +529,9 @@ enum { /// - InsnID(ULEB128) - Instruction ID to erase GIR_EraseFromParent, + /// Combines both a GIR_EraseFromParent 0 + GIR_Done + GIR_EraseRootFromParent_Done, + /// Create a new temporary register that's not constrained. /// - TempRegID(ULEB128) - The temporary register ID to initialize. /// - Ty(1) - Expected type diff --git a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h index c73ac2c9f55b7b5f18f664fea952a39903b4a964..dec2d97bb1fa7e1c7d95f900902172aa2242a434 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/GIMatchTableExecutorImpl.h @@ -131,6 +131,16 @@ bool GIMatchTableExecutor::executeMatchTable( return V; }; + const auto eraseImpl = [&](MachineInstr *MI) { + // If we're erasing the insertion point, ensure we don't leave a dangling + // pointer in the builder. + if (Builder.getInsertPt() == MI) + Builder.setInsertPt(*MI->getParent(), ++MI->getIterator()); + if (Observer) + Observer->erasingInstr(*MI); + MI->eraseFromParent(); + }; + while (true) { assert(CurrentIdx != ~0u && "Invalid MatchTable index"); uint8_t MatcherOpcode = MatchTable[CurrentIdx++]; @@ -661,8 +671,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } + case GIM_RootCheckType: case GIM_CheckType: { - uint64_t InsnID = readULEB(); + uint64_t InsnID = (MatcherOpcode == GIM_RootCheckType) ? 0 : readULEB(); uint64_t OpIdx = readULEB(); int TypeID = readS8(); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -741,8 +752,11 @@ bool GIMatchTableExecutor::executeMatchTable( State.RecordedTypes[TypeIdx] = MRI.getType(Op.getReg()); break; } + + case GIM_RootCheckRegBankForClass: case GIM_CheckRegBankForClass: { - uint64_t InsnID = readULEB(); + uint64_t InsnID = + (MatcherOpcode == GIM_RootCheckRegBankForClass) ? 0 : readULEB(); uint64_t OpIdx = readULEB(); uint16_t RCEnum = readU16(); DEBUG_WITH_TYPE(TgtExecutor::getName(), @@ -898,14 +912,16 @@ bool GIMatchTableExecutor::executeMatchTable( break; } case GIM_CheckIsSafeToFold: { - uint64_t InsnID = readULEB(); + uint64_t NumInsn = MatchTable[CurrentIdx++]; DEBUG_WITH_TYPE(TgtExecutor::getName(), - dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(MIs[" - << InsnID << "])\n"); - assert(State.MIs[InsnID] != nullptr && "Used insn before defined"); - if (!isObviouslySafeToFold(*State.MIs[InsnID], *State.MIs[0])) { - if (handleReject() == RejectAndGiveUp) - return false; + dbgs() << CurrentIdx << ": GIM_CheckIsSafeToFold(N = " + << NumInsn << ")\n"); + MachineInstr &Root = *State.MIs[0]; + for (unsigned K = 1, E = NumInsn + 1; K < E; ++K) { + if (!isObviouslySafeToFold(*State.MIs[K], Root)) { + if (handleReject() == RejectAndGiveUp) + return false; + } } break; } @@ -1011,8 +1027,9 @@ bool GIMatchTableExecutor::executeMatchTable( break; } + case GIR_BuildRootMI: case GIR_BuildMI: { - uint64_t NewInsnID = readULEB(); + uint64_t NewInsnID = (MatcherOpcode == GIR_BuildRootMI) ? 0 : readULEB(); uint16_t Opcode = readU16(); if (NewInsnID >= OutMIs.size()) OutMIs.resize(NewInsnID + 1); @@ -1034,9 +1051,12 @@ bool GIMatchTableExecutor::executeMatchTable( break; } + case GIR_RootToRootCopy: case GIR_Copy: { - uint64_t NewInsnID = readULEB(); - uint64_t OldInsnID = readULEB(); + uint64_t NewInsnID = + (MatcherOpcode == GIR_RootToRootCopy) ? 0 : readULEB(); + uint64_t OldInsnID = + (MatcherOpcode == GIR_RootToRootCopy) ? 0 : readULEB(); uint64_t OpIdx = readULEB(); assert(OutMIs[NewInsnID] && "Attempted to add to undefined instruction"); OutMIs[NewInsnID].add(State.MIs[OldInsnID]->getOperand(OpIdx)); @@ -1361,8 +1381,11 @@ bool GIMatchTableExecutor::executeMatchTable( break; } + case GIR_RootConstrainSelectedInstOperands: case GIR_ConstrainSelectedInstOperands: { - uint64_t InsnID = readULEB(); + uint64_t InsnID = (MatcherOpcode == GIR_RootConstrainSelectedInstOperands) + ? 0 + : readULEB(); assert(OutMIs[InsnID] && "Attempted to add to undefined instruction"); constrainSelectedInstRegOperands(*OutMIs[InsnID].getInstr(), TII, TRI, RBI); @@ -1372,7 +1395,6 @@ bool GIMatchTableExecutor::executeMatchTable( << InsnID << "])\n"); break; } - case GIR_MergeMemOperands: { uint64_t InsnID = readULEB(); uint64_t NumInsn = MatchTable[CurrentIdx++]; @@ -1391,7 +1413,6 @@ bool GIMatchTableExecutor::executeMatchTable( DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << ")\n"); break; } - case GIR_EraseFromParent: { uint64_t InsnID = readULEB(); MachineInstr *MI = State.MIs[InsnID]; @@ -1399,16 +1420,17 @@ bool GIMatchTableExecutor::executeMatchTable( DEBUG_WITH_TYPE(TgtExecutor::getName(), dbgs() << CurrentIdx << ": GIR_EraseFromParent(MIs[" << InsnID << "])\n"); - // If we're erasing the insertion point, ensure we don't leave a dangling - // pointer in the builder. - if (Builder.getInsertPt() == MI) - Builder.setInsertPt(*MI->getParent(), ++MI->getIterator()); - if (Observer) - Observer->erasingInstr(*MI); - MI->eraseFromParent(); + eraseImpl(MI); break; } - + case GIR_EraseRootFromParent_Done: { + DEBUG_WITH_TYPE(TgtExecutor::getName(), + dbgs() + << CurrentIdx << ": GIR_EraseRootFromParent_Done\n"); + eraseImpl(State.MIs[0]); + propagateFlags(); + return true; + } case GIR_MakeTempReg: { uint64_t TempRegID = readULEB(); int TypeID = readS8(); diff --git a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h index ca62f38061b115445bfc002ee82c0fc0e81e1eb1..305bef7dd3ea63dd1b11a92bc8e3ccc42efc4fa0 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h @@ -906,7 +906,8 @@ public: unsigned &DefOperandIdx) { if (Register Def = findValueFromDefImpl(Reg, 0, Size)) { if (auto *Unmerge = dyn_cast(MRI.getVRegDef(Def))) { - DefOperandIdx = Unmerge->findRegisterDefOperandIdx(Def); + DefOperandIdx = + Unmerge->findRegisterDefOperandIdx(Def, /*TRI=*/nullptr); return Unmerge; } } diff --git a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h index be39eb7891f3bf73d0b82ae85a4cbe92c010042a..e15f7a7172e1a40a193cfe1221e221fff2e91348 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/MachineIRBuilder.h @@ -53,6 +53,8 @@ struct MachineIRBuilderState { DebugLoc DL; /// PC sections metadata to be set to any instruction we create. MDNode *PCSections = nullptr; + /// MMRA Metadata to be set on any instruction we create. + MDNode *MMRA = nullptr; /// \name Fields describing the insertion point. /// @{ @@ -354,6 +356,7 @@ public: setMBB(*MI.getParent()); State.II = MI.getIterator(); setPCSections(MI.getPCSections()); + setMMRAMetadata(MI.getMMRAMetadata()); } /// @} @@ -387,6 +390,12 @@ public: /// Get the current instruction's PC sections metadata. MDNode *getPCSections() { return State.PCSections; } + /// Set the PC sections metadata to \p MD for all the next build instructions. + void setMMRAMetadata(MDNode *MMRA) { State.MMRA = MMRA; } + + /// Get the current instruction's MMRA metadata. + MDNode *getMMRAMetadata() { return State.MMRA; } + /// Build and insert = \p Opcode . /// The insertion point is the one set by the last call of either /// setBasicBlock or setMI. diff --git a/llvm/include/llvm/CodeGen/MachineFunction.h b/llvm/include/llvm/CodeGen/MachineFunction.h index 470997b31fe85fe69fe0e54d86882f271fed28bd..9f8e846cac45b9d33165848da6db5f4b1c498a4e 100644 --- a/llvm/include/llvm/CodeGen/MachineFunction.h +++ b/llvm/include/llvm/CodeGen/MachineFunction.h @@ -1125,7 +1125,8 @@ public: MachineInstr::ExtraInfo *createMIExtraInfo( ArrayRef MMOs, MCSymbol *PreInstrSymbol = nullptr, MCSymbol *PostInstrSymbol = nullptr, MDNode *HeapAllocMarker = nullptr, - MDNode *PCSections = nullptr, uint32_t CFIType = 0); + MDNode *PCSections = nullptr, uint32_t CFIType = 0, + MDNode *MMRAs = nullptr); /// Allocate a string and populate it with the given external symbol name. const char *createExternalSymbolName(StringRef Name); diff --git a/llvm/include/llvm/CodeGen/MachineInstr.h b/llvm/include/llvm/CodeGen/MachineInstr.h index 7249f812d2cc4cf498acc6ceda615ac6500d4814..2b0c5d166d88b06187f0c53dcd55cbb08ad26e0b 100644 --- a/llvm/include/llvm/CodeGen/MachineInstr.h +++ b/llvm/include/llvm/CodeGen/MachineInstr.h @@ -160,37 +160,41 @@ private: MCSymbol *PreInstrSymbol = nullptr, MCSymbol *PostInstrSymbol = nullptr, MDNode *HeapAllocMarker = nullptr, - MDNode *PCSections = nullptr, - uint32_t CFIType = 0) { + MDNode *PCSections = nullptr, uint32_t CFIType = 0, + MDNode *MMRAs = nullptr) { bool HasPreInstrSymbol = PreInstrSymbol != nullptr; bool HasPostInstrSymbol = PostInstrSymbol != nullptr; bool HasHeapAllocMarker = HeapAllocMarker != nullptr; + bool HasMMRAs = MMRAs != nullptr; bool HasCFIType = CFIType != 0; bool HasPCSections = PCSections != nullptr; auto *Result = new (Allocator.Allocate( totalSizeToAlloc( MMOs.size(), HasPreInstrSymbol + HasPostInstrSymbol, - HasHeapAllocMarker + HasPCSections, HasCFIType), + HasHeapAllocMarker + HasPCSections + HasMMRAs, HasCFIType), alignof(ExtraInfo))) ExtraInfo(MMOs.size(), HasPreInstrSymbol, HasPostInstrSymbol, - HasHeapAllocMarker, HasPCSections, HasCFIType); + HasHeapAllocMarker, HasPCSections, HasCFIType, HasMMRAs); // Copy the actual data into the trailing objects. std::copy(MMOs.begin(), MMOs.end(), Result->getTrailingObjects()); + unsigned MDNodeIdx = 0; + if (HasPreInstrSymbol) Result->getTrailingObjects()[0] = PreInstrSymbol; if (HasPostInstrSymbol) Result->getTrailingObjects()[HasPreInstrSymbol] = PostInstrSymbol; if (HasHeapAllocMarker) - Result->getTrailingObjects()[0] = HeapAllocMarker; + Result->getTrailingObjects()[MDNodeIdx++] = HeapAllocMarker; if (HasPCSections) - Result->getTrailingObjects()[HasHeapAllocMarker] = - PCSections; + Result->getTrailingObjects()[MDNodeIdx++] = PCSections; if (HasCFIType) Result->getTrailingObjects()[0] = CFIType; + if (HasMMRAs) + Result->getTrailingObjects()[MDNodeIdx++] = MMRAs; return Result; } @@ -223,6 +227,12 @@ private: return HasCFIType ? getTrailingObjects()[0] : 0; } + MDNode *getMMRAMetadata() const { + return HasMMRAs ? getTrailingObjects()[HasHeapAllocMarker + + HasPCSections] + : nullptr; + } + private: friend TrailingObjects; @@ -237,6 +247,7 @@ private: const bool HasHeapAllocMarker; const bool HasPCSections; const bool HasCFIType; + const bool HasMMRAs; // Implement the `TrailingObjects` internal API. size_t numTrailingObjects(OverloadToken) const { @@ -255,11 +266,12 @@ private: // Just a boring constructor to allow us to initialize the sizes. Always use // the `create` routine above. ExtraInfo(int NumMMOs, bool HasPreInstrSymbol, bool HasPostInstrSymbol, - bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType) + bool HasHeapAllocMarker, bool HasPCSections, bool HasCFIType, + bool HasMMRAs) : NumMMOs(NumMMOs), HasPreInstrSymbol(HasPreInstrSymbol), HasPostInstrSymbol(HasPostInstrSymbol), HasHeapAllocMarker(HasHeapAllocMarker), HasPCSections(HasPCSections), - HasCFIType(HasCFIType) {} + HasCFIType(HasCFIType), HasMMRAs(HasMMRAs) {} }; /// Enumeration of the kinds of inline extra info available. It is important @@ -838,6 +850,15 @@ public: return nullptr; } + /// Helper to extract mmra.op metadata. + MDNode *getMMRAMetadata() const { + if (!Info) + return nullptr; + if (ExtraInfo *EI = Info.get()) + return EI->getMMRAMetadata(); + return nullptr; + } + /// Helper to extract a CFI type hash if one has been added. uint32_t getCFIType() const { if (!Info) @@ -1445,9 +1466,8 @@ public: /// is a read of a super-register. /// This does not count partial redefines of virtual registers as reads: /// %reg1024:6 = OP. - bool readsRegister(Register Reg, - const TargetRegisterInfo *TRI = nullptr) const { - return findRegisterUseOperandIdx(Reg, false, TRI) != -1; + bool readsRegister(Register Reg, const TargetRegisterInfo *TRI) const { + return findRegisterUseOperandIdx(Reg, TRI, false) != -1; } /// Return true if the MachineInstr reads the specified virtual register. @@ -1466,34 +1486,30 @@ public: /// Return true if the MachineInstr kills the specified register. /// If TargetRegisterInfo is non-null, then it also checks if there is /// a kill of a super-register. - bool killsRegister(Register Reg, - const TargetRegisterInfo *TRI = nullptr) const { - return findRegisterUseOperandIdx(Reg, true, TRI) != -1; + bool killsRegister(Register Reg, const TargetRegisterInfo *TRI) const { + return findRegisterUseOperandIdx(Reg, TRI, true) != -1; } /// Return true if the MachineInstr fully defines the specified register. /// If TargetRegisterInfo is non-null, then it also checks /// if there is a def of a super-register. /// NOTE: It's ignoring subreg indices on virtual registers. - bool definesRegister(Register Reg, - const TargetRegisterInfo *TRI = nullptr) const { - return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1; + bool definesRegister(Register Reg, const TargetRegisterInfo *TRI) const { + return findRegisterDefOperandIdx(Reg, TRI, false, false) != -1; } /// Return true if the MachineInstr modifies (fully define or partially /// define) the specified register. /// NOTE: It's ignoring subreg indices on virtual registers. - bool modifiesRegister(Register Reg, - const TargetRegisterInfo *TRI = nullptr) const { - return findRegisterDefOperandIdx(Reg, false, true, TRI) != -1; + bool modifiesRegister(Register Reg, const TargetRegisterInfo *TRI) const { + return findRegisterDefOperandIdx(Reg, TRI, false, true) != -1; } /// Returns true if the register is dead in this machine instruction. /// If TargetRegisterInfo is non-null, then it also checks /// if there is a dead def of a super-register. - bool registerDefIsDead(Register Reg, - const TargetRegisterInfo *TRI = nullptr) const { - return findRegisterDefOperandIdx(Reg, true, false, TRI) != -1; + bool registerDefIsDead(Register Reg, const TargetRegisterInfo *TRI) const { + return findRegisterDefOperandIdx(Reg, TRI, true, false) != -1; } /// Returns true if the MachineInstr has an implicit-use operand of exactly @@ -1503,22 +1519,23 @@ public: /// Returns the operand index that is a use of the specific register or -1 /// if it is not found. It further tightens the search criteria to a use /// that kills the register if isKill is true. - int findRegisterUseOperandIdx(Register Reg, bool isKill = false, - const TargetRegisterInfo *TRI = nullptr) const; + int findRegisterUseOperandIdx(Register Reg, const TargetRegisterInfo *TRI, + bool isKill = false) const; /// Wrapper for findRegisterUseOperandIdx, it returns /// a pointer to the MachineOperand rather than an index. - MachineOperand *findRegisterUseOperand(Register Reg, bool isKill = false, - const TargetRegisterInfo *TRI = nullptr) { - int Idx = findRegisterUseOperandIdx(Reg, isKill, TRI); + MachineOperand *findRegisterUseOperand(Register Reg, + const TargetRegisterInfo *TRI, + bool isKill = false) { + int Idx = findRegisterUseOperandIdx(Reg, TRI, isKill); return (Idx == -1) ? nullptr : &getOperand(Idx); } - const MachineOperand *findRegisterUseOperand( - Register Reg, bool isKill = false, - const TargetRegisterInfo *TRI = nullptr) const { - return const_cast(this)-> - findRegisterUseOperand(Reg, isKill, TRI); + const MachineOperand *findRegisterUseOperand(Register Reg, + const TargetRegisterInfo *TRI, + bool isKill = false) const { + return const_cast(this)->findRegisterUseOperand(Reg, TRI, + isKill); } /// Returns the operand index that is a def of the specified register or @@ -1527,26 +1544,26 @@ public: /// overlap the specified register. If TargetRegisterInfo is non-null, /// then it also checks if there is a def of a super-register. /// This may also return a register mask operand when Overlap is true. - int findRegisterDefOperandIdx(Register Reg, - bool isDead = false, bool Overlap = false, - const TargetRegisterInfo *TRI = nullptr) const; + int findRegisterDefOperandIdx(Register Reg, const TargetRegisterInfo *TRI, + bool isDead = false, + bool Overlap = false) const; /// Wrapper for findRegisterDefOperandIdx, it returns /// a pointer to the MachineOperand rather than an index. - MachineOperand * - findRegisterDefOperand(Register Reg, bool isDead = false, - bool Overlap = false, - const TargetRegisterInfo *TRI = nullptr) { - int Idx = findRegisterDefOperandIdx(Reg, isDead, Overlap, TRI); + MachineOperand *findRegisterDefOperand(Register Reg, + const TargetRegisterInfo *TRI, + bool isDead = false, + bool Overlap = false) { + int Idx = findRegisterDefOperandIdx(Reg, TRI, isDead, Overlap); return (Idx == -1) ? nullptr : &getOperand(Idx); } - const MachineOperand * - findRegisterDefOperand(Register Reg, bool isDead = false, - bool Overlap = false, - const TargetRegisterInfo *TRI = nullptr) const { + const MachineOperand *findRegisterDefOperand(Register Reg, + const TargetRegisterInfo *TRI, + bool isDead = false, + bool Overlap = false) const { return const_cast(this)->findRegisterDefOperand( - Reg, isDead, Overlap, TRI); + Reg, TRI, isDead, Overlap); } /// Find the index of the first operand in the @@ -1902,6 +1919,8 @@ public: // addresses into. void setPCSections(MachineFunction &MF, MDNode *MD); + void setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs); + /// Set the CFI type for the instruction. void setCFIType(MachineFunction &MF, uint32_t Type); @@ -2014,7 +2033,7 @@ private: void setExtraInfo(MachineFunction &MF, ArrayRef MMOs, MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, MDNode *HeapAllocMarker, MDNode *PCSections, - uint32_t CFIType); + uint32_t CFIType, MDNode *MMRAs); }; /// Special DenseMapInfo traits to compare MachineInstr* by *value* of the diff --git a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h index 954d8e6770a294f481a0913b67ef3f8e9556db2c..a5b8d3af3cc9b703e8facb5886ad20c16fb2a63b 100644 --- a/llvm/include/llvm/CodeGen/MachineInstrBuilder.h +++ b/llvm/include/llvm/CodeGen/MachineInstrBuilder.h @@ -322,6 +322,12 @@ public: return *this; } + const MachineInstrBuilder &setMMRAMetadata(MDNode *MMRA) const { + if (MMRA) + MI->setMMRAMetadata(*MF, MMRA); + return *this; + } + /// Copy all the implicit operands from OtherMI onto this one. const MachineInstrBuilder & copyImplicitOps(const MachineInstr &OtherMI) const { @@ -337,14 +343,15 @@ public: }; /// Set of metadata that should be preserved when using BuildMI(). This provides -/// a more convenient way of preserving DebugLoc and PCSections. +/// a more convenient way of preserving DebugLoc, PCSections and MMRA. class MIMetadata { public: MIMetadata() = default; - MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr) - : DL(std::move(DL)), PCSections(PCSections) {} - MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr) - : DL(DI), PCSections(PCSections) {} + MIMetadata(DebugLoc DL, MDNode *PCSections = nullptr, MDNode *MMRA = nullptr) + : DL(std::move(DL)), PCSections(PCSections), MMRA(MMRA) {} + MIMetadata(const DILocation *DI, MDNode *PCSections = nullptr, + MDNode *MMRA = nullptr) + : DL(DI), PCSections(PCSections), MMRA(MMRA) {} explicit MIMetadata(const Instruction &From) : DL(From.getDebugLoc()), PCSections(From.getMetadata(LLVMContext::MD_pcsections)) {} @@ -353,17 +360,20 @@ public: const DebugLoc &getDL() const { return DL; } MDNode *getPCSections() const { return PCSections; } + MDNode *getMMRAMetadata() const { return MMRA; } private: DebugLoc DL; MDNode *PCSections = nullptr; + MDNode *MMRA = nullptr; }; /// Builder interface. Specify how to create the initial instruction itself. inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID) { return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL())) - .setPCSections(MIMD.getPCSections()); + .setPCSections(MIMD.getPCSections()) + .setMMRAMetadata(MIMD.getMMRAMetadata()); } /// This version of the builder sets up the first operand as a @@ -371,8 +381,9 @@ inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, inline MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID, Register DestReg) { return MachineInstrBuilder(MF, MF.CreateMachineInstr(MCID, MIMD.getDL())) - .setPCSections(MIMD.getPCSections()) - .addReg(DestReg, RegState::Define); + .setPCSections(MIMD.getPCSections()) + .setMMRAMetadata(MIMD.getMMRAMetadata()) + .addReg(DestReg, RegState::Define); } /// This version of the builder inserts the newly-built instruction before @@ -386,8 +397,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); BB.insert(I, MI); return MachineInstrBuilder(MF, MI) - .setPCSections(MIMD.getPCSections()) - .addReg(DestReg, RegState::Define); + .setPCSections(MIMD.getPCSections()) + .setMMRAMetadata(MIMD.getMMRAMetadata()) + .addReg(DestReg, RegState::Define); } /// This version of the builder inserts the newly-built instruction before @@ -404,8 +416,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); BB.insert(I, MI); return MachineInstrBuilder(MF, MI) - .setPCSections(MIMD.getPCSections()) - .addReg(DestReg, RegState::Define); + .setPCSections(MIMD.getPCSections()) + .setMMRAMetadata(MIMD.getMMRAMetadata()) + .addReg(DestReg, RegState::Define); } inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, @@ -435,7 +448,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineFunction &MF = *BB.getParent(); MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); BB.insert(I, MI); - return MachineInstrBuilder(MF, MI).setPCSections(MIMD.getPCSections()); + return MachineInstrBuilder(MF, MI) + .setPCSections(MIMD.getPCSections()) + .setMMRAMetadata(MIMD.getMMRAMetadata()); } inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, @@ -445,7 +460,9 @@ inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineFunction &MF = *BB.getParent(); MachineInstr *MI = MF.CreateMachineInstr(MCID, MIMD.getDL()); BB.insert(I, MI); - return MachineInstrBuilder(MF, MI).setPCSections(MIMD.getPCSections()); + return MachineInstrBuilder(MF, MI) + .setPCSections(MIMD.getPCSections()) + .setMMRAMetadata(MIMD.getMMRAMetadata()); } inline MachineInstrBuilder BuildMI(MachineBasicBlock &BB, MachineInstr &I, diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index f347131be080f63fb2b9ac6a97d19b86ac090ac4..f353aef1f446ff206d8fc4855c898a68d771e6d4 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -284,6 +284,7 @@ class SelectionDAG { CallSiteInfo CSInfo; MDNode *HeapAllocSite = nullptr; MDNode *PCSections = nullptr; + MDNode *MMRA = nullptr; bool NoMerge = false; }; /// Out-of-line extra information for SDNodes. @@ -2145,18 +2146,32 @@ public: const APInt *getValidShiftAmountConstant(SDValue V, const APInt &DemandedElts) const; + /// If a SHL/SRA/SRL node \p V has a constant or splat constant shift amount + /// that is less than the element bit-width of the shift node, return it. + const APInt *getValidShiftAmountConstant(SDValue V) const; + /// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less /// than the element bit-width of the shift node, return the minimum value. const APInt * getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const; + /// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less + /// than the element bit-width of the shift node, return the minimum value. + const APInt * + getValidMinimumShiftAmountConstant(SDValue V) const; + /// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less /// than the element bit-width of the shift node, return the maximum value. const APInt * getValidMaximumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const; + /// If a SHL/SRA/SRL node \p V has constant shift amounts that are all less + /// than the element bit-width of the shift node, return the maximum value. + const APInt * + getValidMaximumShiftAmountConstant(SDValue V) const; + /// Match a binop + shuffle pyramid that represents a horizontal reduction /// over the elements of a vector starting from the EXTRACT_VECTOR_ELT node /p /// Extract. The reduction must use one of the opcodes listed in /p @@ -2279,11 +2294,21 @@ public: void addPCSections(const SDNode *Node, MDNode *MD) { SDEI[Node].PCSections = MD; } + /// Set MMRAMetadata to be associated with Node. + void addMMRAMetadata(const SDNode *Node, MDNode *MMRA) { + SDEI[Node].MMRA = MMRA; + } /// Return PCSections associated with Node, or nullptr if none exists. MDNode *getPCSections(const SDNode *Node) const { auto It = SDEI.find(Node); return It != SDEI.end() ? It->second.PCSections : nullptr; } + /// Return the MMRA MDNode associated with Node, or nullptr if none + /// exists. + MDNode *getMMRAMetadata(const SDNode *Node) const { + auto It = SDEI.find(Node); + return It != SDEI.end() ? It->second.MMRA : nullptr; + } /// Set NoMergeSiteInfo to be associated with Node if NoMerge is true. void addNoMergeSiteInfo(const SDNode *Node, bool NoMerge) { if (NoMerge) diff --git a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h index 261f7e49e5c8ca6e60e75d4be31bce3b651abe4d..70d6b09a0c895cc23dfabed5deba03576f154f95 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAGNodes.h +++ b/llvm/include/llvm/CodeGen/SelectionDAGNodes.h @@ -1283,8 +1283,10 @@ private: unsigned DestAddrSpace; public: - AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, EVT VT, - unsigned SrcAS, unsigned DestAS); + AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, SDVTList VTs, + unsigned SrcAS, unsigned DestAS) + : SDNode(ISD::ADDRSPACECAST, Order, dl, VTs), SrcAddrSpace(SrcAS), + DestAddrSpace(DestAS) {} unsigned getSrcAddressSpace() const { return SrcAddrSpace; } unsigned getDestAddressSpace() const { return DestAddrSpace; } @@ -1573,8 +1575,9 @@ class ShuffleVectorSDNode : public SDNode { protected: friend class SelectionDAG; - ShuffleVectorSDNode(EVT VT, unsigned Order, const DebugLoc &dl, const int *M) - : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, getSDVTList(VT)), Mask(M) {} + ShuffleVectorSDNode(SDVTList VTs, unsigned Order, const DebugLoc &dl, + const int *M) + : SDNode(ISD::VECTOR_SHUFFLE, Order, dl, VTs), Mask(M) {} public: ArrayRef getMask() const { @@ -1628,9 +1631,10 @@ class ConstantSDNode : public SDNode { const ConstantInt *Value; - ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, EVT VT) + ConstantSDNode(bool isTarget, bool isOpaque, const ConstantInt *val, + SDVTList VTs) : SDNode(isTarget ? ISD::TargetConstant : ISD::Constant, 0, DebugLoc(), - getSDVTList(VT)), + VTs), Value(val) { ConstantSDNodeBits.IsOpaque = isOpaque; } @@ -1681,9 +1685,9 @@ class ConstantFPSDNode : public SDNode { const ConstantFP *Value; - ConstantFPSDNode(bool isTarget, const ConstantFP *val, EVT VT) + ConstantFPSDNode(bool isTarget, const ConstantFP *val, SDVTList VTs) : SDNode(isTarget ? ISD::TargetConstantFP : ISD::ConstantFP, 0, - DebugLoc(), getSDVTList(VT)), + DebugLoc(), VTs), Value(val) {} public: @@ -1816,8 +1820,10 @@ class GlobalAddressSDNode : public SDNode { unsigned TargetFlags; GlobalAddressSDNode(unsigned Opc, unsigned Order, const DebugLoc &DL, - const GlobalValue *GA, EVT VT, int64_t o, - unsigned TF); + const GlobalValue *GA, SDVTList VTs, int64_t o, + unsigned TF) + : SDNode(Opc, Order, DL, VTs), TheGlobal(GA), Offset(o), TargetFlags(TF) { + } public: const GlobalValue *getGlobal() const { return TheGlobal; } @@ -1839,10 +1845,10 @@ class FrameIndexSDNode : public SDNode { int FI; - FrameIndexSDNode(int fi, EVT VT, bool isTarg) - : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, - 0, DebugLoc(), getSDVTList(VT)), FI(fi) { - } + FrameIndexSDNode(int fi, SDVTList VTs, bool isTarg) + : SDNode(isTarg ? ISD::TargetFrameIndex : ISD::FrameIndex, 0, DebugLoc(), + VTs), + FI(fi) {} public: int getIndex() const { return FI; } @@ -1917,10 +1923,10 @@ class JumpTableSDNode : public SDNode { int JTI; unsigned TargetFlags; - JumpTableSDNode(int jti, EVT VT, bool isTarg, unsigned TF) - : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, - 0, DebugLoc(), getSDVTList(VT)), JTI(jti), TargetFlags(TF) { - } + JumpTableSDNode(int jti, SDVTList VTs, bool isTarg, unsigned TF) + : SDNode(isTarg ? ISD::TargetJumpTable : ISD::JumpTable, 0, DebugLoc(), + VTs), + JTI(jti), TargetFlags(TF) {} public: int getIndex() const { return JTI; } @@ -1943,19 +1949,19 @@ class ConstantPoolSDNode : public SDNode { Align Alignment; // Minimum alignment requirement of CP. unsigned TargetFlags; - ConstantPoolSDNode(bool isTarget, const Constant *c, EVT VT, int o, + ConstantPoolSDNode(bool isTarget, const Constant *c, SDVTList VTs, int o, Align Alignment, unsigned TF) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0, - DebugLoc(), getSDVTList(VT)), + DebugLoc(), VTs), Offset(o), Alignment(Alignment), TargetFlags(TF) { assert(Offset >= 0 && "Offset is too large"); Val.ConstVal = c; } - ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, EVT VT, int o, - Align Alignment, unsigned TF) + ConstantPoolSDNode(bool isTarget, MachineConstantPoolValue *v, SDVTList VTs, + int o, Align Alignment, unsigned TF) : SDNode(isTarget ? ISD::TargetConstantPool : ISD::ConstantPool, 0, - DebugLoc(), getSDVTList(VT)), + DebugLoc(), VTs), Offset(o), Alignment(Alignment), TargetFlags(TF) { assert(Offset >= 0 && "Offset is too large"); Val.MachineCPVal = v; @@ -2003,9 +2009,9 @@ class TargetIndexSDNode : public SDNode { int64_t Offset; public: - TargetIndexSDNode(int Idx, EVT VT, int64_t Ofs, unsigned TF) - : SDNode(ISD::TargetIndex, 0, DebugLoc(), getSDVTList(VT)), - TargetFlags(TF), Index(Idx), Offset(Ofs) {} + TargetIndexSDNode(int Idx, SDVTList VTs, int64_t Ofs, unsigned TF) + : SDNode(ISD::TargetIndex, 0, DebugLoc(), VTs), TargetFlags(TF), + Index(Idx), Offset(Ofs) {} unsigned getTargetFlags() const { return TargetFlags; } int getIndex() const { return Index; } @@ -2215,8 +2221,8 @@ class RegisterSDNode : public SDNode { Register Reg; - RegisterSDNode(Register reg, EVT VT) - : SDNode(ISD::Register, 0, DebugLoc(), getSDVTList(VT)), Reg(reg) {} + RegisterSDNode(Register reg, SDVTList VTs) + : SDNode(ISD::Register, 0, DebugLoc(), VTs), Reg(reg) {} public: Register getReg() const { return Reg; } @@ -2251,10 +2257,10 @@ class BlockAddressSDNode : public SDNode { int64_t Offset; unsigned TargetFlags; - BlockAddressSDNode(unsigned NodeTy, EVT VT, const BlockAddress *ba, + BlockAddressSDNode(unsigned NodeTy, SDVTList VTs, const BlockAddress *ba, int64_t o, unsigned Flags) - : SDNode(NodeTy, 0, DebugLoc(), getSDVTList(VT)), - BA(ba), Offset(o), TargetFlags(Flags) {} + : SDNode(NodeTy, 0, DebugLoc(), VTs), BA(ba), Offset(o), + TargetFlags(Flags) {} public: const BlockAddress *getBlockAddress() const { return BA; } @@ -2292,9 +2298,10 @@ class ExternalSymbolSDNode : public SDNode { const char *Symbol; unsigned TargetFlags; - ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, EVT VT) + ExternalSymbolSDNode(bool isTarget, const char *Sym, unsigned TF, + SDVTList VTs) : SDNode(isTarget ? ISD::TargetExternalSymbol : ISD::ExternalSymbol, 0, - DebugLoc(), getSDVTList(VT)), + DebugLoc(), VTs), Symbol(Sym), TargetFlags(TF) {} public: @@ -2312,8 +2319,8 @@ class MCSymbolSDNode : public SDNode { MCSymbol *Symbol; - MCSymbolSDNode(MCSymbol *Symbol, EVT VT) - : SDNode(ISD::MCSymbol, 0, DebugLoc(), getSDVTList(VT)), Symbol(Symbol) {} + MCSymbolSDNode(MCSymbol *Symbol, SDVTList VTs) + : SDNode(ISD::MCSymbol, 0, DebugLoc(), VTs), Symbol(Symbol) {} public: MCSymbol *getMCSymbol() const { return Symbol; } @@ -3026,8 +3033,8 @@ class AssertAlignSDNode : public SDNode { Align Alignment; public: - AssertAlignSDNode(unsigned Order, const DebugLoc &DL, EVT VT, Align A) - : SDNode(ISD::AssertAlign, Order, DL, getSDVTList(VT)), Alignment(A) {} + AssertAlignSDNode(unsigned Order, const DebugLoc &DL, SDVTList VTs, Align A) + : SDNode(ISD::AssertAlign, Order, DL, VTs), Alignment(A) {} Align getAlign() const { return Alignment; } diff --git a/llvm/include/llvm/ExecutionEngine/Orc/Core.h b/llvm/include/llvm/ExecutionEngine/Orc/Core.h index 7121b3fe762748897398c98c03947a8f98c0a073..bac923aba02afdf5ce32c916b7e4c360019b1782 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/Core.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/Core.h @@ -1443,9 +1443,6 @@ public: /// Send a result to the remote. using SendResultFunction = unique_function; - /// For dispatching ORC tasks (typically materialization tasks). - using DispatchTaskFunction = unique_function T)>; - /// An asynchronous wrapper-function callable from the executor via /// jit-dispatch. using JITDispatchHandlerFunction = unique_functionDispatchTask = std::move(DispatchTask); - return *this; - } - /// Search the given JITDylibs to find the flags associated with each of the /// given symbols. void lookupFlags(LookupKind K, JITDylibSearchOrder SearchOrder, @@ -1648,7 +1639,7 @@ public: void dispatchTask(std::unique_ptr T) { assert(T && "T must be non-null"); DEBUG_WITH_TYPE("orc", dumpDispatchInfo(*T)); - DispatchTask(std::move(T)); + EPC->getDispatcher().dispatch(std::move(T)); } /// Run a wrapper function in the executor. @@ -1762,8 +1753,6 @@ private: logAllUnhandledErrors(std::move(Err), errs(), "JIT session error: "); } - static void runOnCurrentThread(std::unique_ptr T) { T->run(); } - void dispatchOutstandingMUs(); static std::unique_ptr @@ -1869,7 +1858,6 @@ private: std::unique_ptr EPC; std::unique_ptr P; ErrorReporter ReportError = logErrorsToStdErr; - DispatchTaskFunction DispatchTask = runOnCurrentThread; std::vector ResourceManagers; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h index 810a38f4a6acb88691ee6079b4d2a013b4e1a445..3a71ddc88ce95631517a6cbf32e510ebbff053a6 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h @@ -254,7 +254,6 @@ protected: DataLayout DL; Triple TT; - std::unique_ptr CompileThreads; std::unique_ptr ObjLinkingLayer; std::unique_ptr ObjTransformLayer; @@ -325,6 +324,7 @@ public: PlatformSetupFunction SetUpPlatform; NotifyCreatedFunction NotifyCreated; unsigned NumCompileThreads = 0; + std::optional SupportConcurrentCompilation; /// Called prior to JIT class construcion to fix up defaults. Error prepareForConstruction(); @@ -333,7 +333,7 @@ public: template class LLJITBuilderSetters { public: - /// Set a ExecutorProcessControl for this instance. + /// Set an ExecutorProcessControl for this instance. /// This should not be called if ExecutionSession has already been set. SetterImpl & setExecutorProcessControl(std::unique_ptr EPC) { @@ -462,19 +462,26 @@ public: /// /// If this method is not called, behavior will be as if it were called with /// a zero argument. + /// + /// This setting should not be used if a custom ExecutionSession or + /// ExecutorProcessControl object is set: in those cases a custom + /// TaskDispatcher should be used instead. SetterImpl &setNumCompileThreads(unsigned NumCompileThreads) { impl().NumCompileThreads = NumCompileThreads; return impl(); } - /// Set an ExecutorProcessControl object. + /// If set, this forces LLJIT concurrent compilation support to be either on + /// or off. This controls the selection of compile function (concurrent vs + /// single threaded) and whether or not sub-modules are cloned to new + /// contexts for lazy emission. /// - /// If the platform uses ObjectLinkingLayer by default and no - /// ObjectLinkingLayerCreator has been set then the ExecutorProcessControl - /// object will be used to supply the memory manager for the - /// ObjectLinkingLayer. - SetterImpl &setExecutorProcessControl(ExecutorProcessControl &EPC) { - impl().EPC = &EPC; + /// If not explicitly set then concurrency support will be turned on if + /// NumCompileThreads is set to a non-zero value, or if a custom + /// ExecutionSession or ExecutorProcessControl instance is provided. + SetterImpl &setSupportConcurrentCompilation( + std::optional SupportConcurrentCompilation) { + impl().SupportConcurrentCompilation = SupportConcurrentCompilation; return impl(); } diff --git a/llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h b/llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h index 8c287f9fec0e89807524a88672340b08f347b632..8c65677aae25a47aad7fd2e9878dba812029e2d5 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/TaskDispatch.h @@ -23,6 +23,7 @@ #if LLVM_ENABLE_THREADS #include +#include #include #include #endif @@ -114,6 +115,9 @@ public: class DynamicThreadPoolTaskDispatcher : public TaskDispatcher { public: + DynamicThreadPoolTaskDispatcher( + std::optional MaxMaterializationThreads) + : MaxMaterializationThreads(MaxMaterializationThreads) {} void dispatch(std::unique_ptr T) override; void shutdown() override; private: @@ -121,6 +125,10 @@ private: bool Running = true; size_t Outstanding = 0; std::condition_variable OutstandingCV; + + std::optional MaxMaterializationThreads; + size_t NumMaterializationThreads = 0; + std::deque> MaterializationTaskQueue; }; #endif // LLVM_ENABLE_THREADS diff --git a/llvm/include/llvm/Frontend/OpenMP/OMP.h b/llvm/include/llvm/Frontend/OpenMP/OMP.h index ec8ae68f1c2ca0e7137128e3315b5a19996bd189..6f7a39acac1d319a82c9bc6766d52c26bf5cb201 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMP.h +++ b/llvm/include/llvm/Frontend/OpenMP/OMP.h @@ -16,9 +16,15 @@ #include "llvm/Frontend/OpenMP/OMP.h.inc" #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" namespace llvm::omp { ArrayRef getLeafConstructs(Directive D); +ArrayRef getLeafConstructsOrSelf(Directive D); + +ArrayRef +getLeafOrCompositeConstructs(Directive D, SmallVectorImpl &Output); + Directive getCompoundConstruct(ArrayRef Parts); bool isLeafConstruct(Directive D); diff --git a/llvm/include/llvm/IR/Attributes.h b/llvm/include/llvm/IR/Attributes.h index 7dd8a329029a3420a5ae9b78a0bd57688813df86..5e3ba1f32e6ab0c0756c1e200c238235064da60c 100644 --- a/llvm/include/llvm/IR/Attributes.h +++ b/llvm/include/llvm/IR/Attributes.h @@ -747,6 +747,11 @@ public: addDereferenceableOrNullParamAttr(LLVMContext &C, unsigned ArgNo, uint64_t Bytes) const; + /// Add the range attribute to the attribute set at the return value index. + /// Returns a new list because attribute lists are immutable. + [[nodiscard]] AttributeList addRangeRetAttr(LLVMContext &C, + const ConstantRange &CR) const; + /// Add the allocsize attribute to the attribute set at the given arg index. /// Returns a new list because attribute lists are immutable. [[nodiscard]] AttributeList diff --git a/llvm/include/llvm/IR/FixedMetadataKinds.def b/llvm/include/llvm/IR/FixedMetadataKinds.def index b375d0f0912060fc84fe5d58d42263bf075f17a7..5f4cc230a0f5ff1112f2ea00d4c08b4e5b5297ec 100644 --- a/llvm/include/llvm/IR/FixedMetadataKinds.def +++ b/llvm/include/llvm/IR/FixedMetadataKinds.def @@ -51,3 +51,4 @@ LLVM_FIXED_MD_KIND(MD_kcfi_type, "kcfi_type", 36) LLVM_FIXED_MD_KIND(MD_pcsections, "pcsections", 37) LLVM_FIXED_MD_KIND(MD_DIAssignID, "DIAssignID", 38) LLVM_FIXED_MD_KIND(MD_coro_outside_frame, "coro.outside.frame", 39) +LLVM_FIXED_MD_KIND(MD_mmra, "mmra", 40) diff --git a/llvm/include/llvm/IR/InstrTypes.h b/llvm/include/llvm/IR/InstrTypes.h index 8e6bef69218c2b1f03399b42b5def311503de46b..b9af3a6ca42c06dc65e9f70a65adc29043a234d8 100644 --- a/llvm/include/llvm/IR/InstrTypes.h +++ b/llvm/include/llvm/IR/InstrTypes.h @@ -1941,6 +1941,11 @@ public: Attrs = Attrs.addDereferenceableRetAttr(getContext(), Bytes); } + /// adds the range attribute to the list of attributes. + void addRangeRetAttr(const ConstantRange &CR) { + Attrs = Attrs.addRangeRetAttr(getContext(), CR); + } + /// Determine whether the return value has the given attribute. bool hasRetAttr(Attribute::AttrKind Kind) const { return hasRetAttrImpl(Kind); diff --git a/llvm/include/llvm/IR/MemoryModelRelaxationAnnotations.h b/llvm/include/llvm/IR/MemoryModelRelaxationAnnotations.h new file mode 100644 index 0000000000000000000000000000000000000000..a9ded6034d0b4e7e9d84699c50cf006fef6ca10d --- /dev/null +++ b/llvm/include/llvm/IR/MemoryModelRelaxationAnnotations.h @@ -0,0 +1,132 @@ +//===- MemoryModelRelaxationAnnotations.h -----------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +/// \file +/// This file provides utility for Memory Model Relaxation Annotations (MMRAs). +/// Those annotations are represented using Metadata. The MMRATagSet class +/// offers a simple API to parse the metadata and perform common operations on +/// it. The MMRAMetadata class is a simple tuple of MDNode that provides easy +/// access to all MMRA annotations on an instruction. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_IR_MEMORYMODELRELAXATIONANNOTATIONS_H +#define LLVM_IR_MEMORYMODELRELAXATIONANNOTATIONS_H + +#include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/StringRef.h" +#include // for std::pair + +namespace llvm { + +template class ArrayRef; + +class MDNode; +class MDTuple; +class Metadata; +class raw_ostream; +class LLVMContext; +class Instruction; + +/// Helper class to manipulate `!mmra` metadata nodes. +/// +/// This can be visualized as a set of "tags", with each tag +/// representing a particular property of an instruction, as +/// explained in the MemoryModelRelaxationAnnotations docs. +/// +/// This class (and the optimizer in general) does not reason +/// about the exact nature of the tags and the properties they +/// imply. It just sees the metadata as a collection of tags, which +/// are a prefix/suffix pair of strings. +class MMRAMetadata { +public: + using TagT = std::pair; + using SetT = DenseSet; + using const_iterator = SetT::const_iterator; + + /// \name Constructors + /// @{ + MMRAMetadata() = default; + MMRAMetadata(const Instruction &I); + MMRAMetadata(MDNode *MD); + /// @} + + /// \name Metadata Helpers & Builders + /// @{ + + /// Combines \p A and \p B according to MMRA semantics. + /// \returns !mmra metadata for the combined MMRAs. + static MDNode *combine(LLVMContext &Ctx, const MMRAMetadata &A, + const MMRAMetadata &B); + + /// Creates !mmra metadata for a single tag. + /// + /// !mmra metadata can either be a single tag, or a MDTuple containing + /// multiple tags. + static MDTuple *getTagMD(LLVMContext &Ctx, StringRef Prefix, + StringRef Suffix); + static MDTuple *getTagMD(LLVMContext &Ctx, const TagT &T) { + return getTagMD(Ctx, T.first, T.second); + } + + /// Creates !mmra metadata from \p Tags. + /// \returns nullptr or a MDTuple* from \p Tags. + static MDTuple *getMD(LLVMContext &Ctx, ArrayRef Tags); + + /// \returns true if \p MD is a well-formed MMRA tag. + static bool isTagMD(const Metadata *MD); + + /// @} + + /// \name Compatibility Helpers + /// @{ + + /// \returns whether the MMRAs on \p A and \p B are compatible. + static bool checkCompatibility(const Instruction &A, const Instruction &B) { + return MMRAMetadata(A).isCompatibleWith(B); + } + + /// \returns whether this set of tags is compatible with \p Other. + bool isCompatibleWith(const MMRAMetadata &Other) const; + + /// @} + + /// \name Content Queries + /// @{ + + bool hasTag(StringRef Prefix, StringRef Suffix) const; + bool hasTagWithPrefix(StringRef Prefix) const; + + const_iterator begin() const; + const_iterator end() const; + bool empty() const; + unsigned size() const; + + /// @} + + void print(raw_ostream &OS) const; + void dump() const; + + operator bool() const { return !Tags.empty(); } + bool operator==(const MMRAMetadata &Other) const { + return Tags == Other.Tags; + } + bool operator!=(const MMRAMetadata &Other) const { + return Tags != Other.Tags; + } + +private: + SetT Tags; +}; + +/// \returns true if \p I can have !mmra metadata. +bool canInstructionHaveMMRAs(const Instruction &I); + +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index 1fee1901fabb65d8798a311966bc9036bae31e4b..0b13b4aad9c326aa8ee20d5e392f87583c4907af 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -350,8 +350,9 @@ template inline constantint_match m_ConstantInt() { /// This helper class is used to match constant scalars, vector splats, /// and fixed width vectors that satisfy a specified predicate. -/// For fixed width vector constants, poison elements are ignored. -template +/// For fixed width vector constants, poison elements are ignored if AllowPoison +/// is true. +template struct cstval_pred_ty : public Predicate { template bool match(ITy *V) { if (const auto *CV = dyn_cast(V)) @@ -374,7 +375,7 @@ struct cstval_pred_ty : public Predicate { Constant *Elt = C->getAggregateElement(i); if (!Elt) return false; - if (isa(Elt)) + if (AllowPoison && isa(Elt)) continue; auto *CV = dyn_cast(Elt); if (!CV || !this->isValue(CV->getValue())) @@ -389,12 +390,13 @@ struct cstval_pred_ty : public Predicate { }; /// specialization of cstval_pred_ty for ConstantInt -template -using cst_pred_ty = cstval_pred_ty; +template +using cst_pred_ty = cstval_pred_ty; /// specialization of cstval_pred_ty for ConstantFP template -using cstfp_pred_ty = cstval_pred_ty; +using cstfp_pred_ty = cstval_pred_ty; /// This helper class is used to match scalar and vector constants that /// satisfy a specified predicate, and bind them to an APInt. @@ -484,6 +486,10 @@ inline cst_pred_ty m_AllOnes() { return cst_pred_ty(); } +inline cst_pred_ty m_AllOnesForbidPoison() { + return cst_pred_ty(); +} + struct is_maxsignedvalue { bool isValue(const APInt &C) { return C.isMaxSignedValue(); } }; @@ -2596,6 +2602,13 @@ m_Not(const ValTy &V) { return m_c_Xor(m_AllOnes(), V); } +template +inline BinaryOp_match, ValTy, Instruction::Xor, + true> +m_NotForbidPoison(const ValTy &V) { + return m_c_Xor(m_AllOnesForbidPoison(), V); +} + /// Matches an SMin with LHS and RHS in either order. template inline MaxMin_match diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h index 1d457be93741f274d38f3e6b4d0fa1ebe0a71bac..4494d9b96189bcc50aa2a5a34e39c87a531a375a 100644 --- a/llvm/include/llvm/Object/ELFObjectFile.h +++ b/llvm/include/llvm/Object/ELFObjectFile.h @@ -801,9 +801,8 @@ Expected ELFObjectFile::getSymbolFlags(DataRefImpl Sym) const { } else if (EF.getHeader().e_machine == ELF::EM_RISCV) { if (Expected NameOrErr = getSymbolName(Sym)) { StringRef Name = *NameOrErr; - // Mark empty name symbols (used for label differences) and mapping - // symbols. - if (Name.empty() || Name.starts_with("$d") || Name.starts_with("$x")) + // Mark fake labels (used for label differences) and mapping symbols. + if (Name == ".L0 " || Name.starts_with("$d") || Name.starts_with("$x")) Result |= SymbolRef::SF_FormatSpecific; } else { // TODO: Actually report errors helpfully. diff --git a/llvm/include/llvm/ProfileData/InstrProfWriter.h b/llvm/include/llvm/ProfileData/InstrProfWriter.h index b0ae8f364fcafb91f7729c424bbca05daa4f76a4..08db8fa6e7ef2cd40814f137a22f70df6cea044c 100644 --- a/llvm/include/llvm/ProfileData/InstrProfWriter.h +++ b/llvm/include/llvm/ProfileData/InstrProfWriter.h @@ -85,11 +85,15 @@ private: // The MemProf version we should write. memprof::IndexedVersion MemProfVersionRequested; + // Whether to serialize the full schema. + bool MemProfFullSchema; + public: InstrProfWriter( bool Sparse = false, uint64_t TemporalProfTraceReservoirSize = 0, uint64_t MaxTemporalProfTraceLength = 0, bool WritePrevVersion = false, - memprof::IndexedVersion MemProfVersionRequested = memprof::Version0); + memprof::IndexedVersion MemProfVersionRequested = memprof::Version0, + bool MemProfFullSchema = false); ~InstrProfWriter(); StringMap &getProfileData() { return FunctionData; } @@ -203,6 +207,7 @@ public: void setMemProfVersionRequested(memprof::IndexedVersion Version) { MemProfVersionRequested = Version; } + void setMemProfFullSchema(bool Full) { MemProfFullSchema = Full; } // Compute the overlap b/w this object and Other. Program level result is // stored in Overlap and function level result is stored in FuncLevelOverlap. void overlapRecord(NamedInstrProfRecord &&Other, OverlapStats &Overlap, diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index aa6cdf198485b03a935b02d85182f3bbbdb66cea..a8e98f8bb138619ee44dd4579d1b46a06a5c0d20 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -117,7 +117,7 @@ struct PortableMemInfoBlock { void clear() { *this = PortableMemInfoBlock(); } // Returns the full schema currently in use. - static MemProfSchema getSchema() { + static MemProfSchema getFullSchema() { MemProfSchema List; #define MIBEntryDef(NameTag, Name, Type) List.push_back(Meta::Name); #include "llvm/ProfileData/MIBEntryDef.inc" @@ -125,6 +125,13 @@ struct PortableMemInfoBlock { return List; } + // Returns the schema consisting of the fields currently consumed by the + // compiler. + static MemProfSchema getHotColdSchema() { + return {Meta::AllocCount, Meta::TotalSize, Meta::TotalLifetime, + Meta::TotalLifetimeAccessDensity}; + } + bool operator==(const PortableMemInfoBlock &Other) const { #define MIBEntryDef(NameTag, Name, Type) \ if (Other.get##Name() != get##Name()) \ @@ -138,11 +145,22 @@ struct PortableMemInfoBlock { return !operator==(Other); } - static constexpr size_t serializedSize() { + static size_t serializedSize(const MemProfSchema &Schema) { size_t Result = 0; -#define MIBEntryDef(NameTag, Name, Type) Result += sizeof(Type); + + for (const Meta Id : Schema) { + switch (Id) { +#define MIBEntryDef(NameTag, Name, Type) \ + case Meta::Name: { \ + Result += sizeof(Type); \ + } break; #include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef + default: + llvm_unreachable("Unknown meta type id, invalid input?"); + } + } + return Result; } @@ -292,7 +310,8 @@ struct IndexedAllocationInfo { : CallStack(CS.begin(), CS.end()), CSId(CSId), Info(MB) {} // Returns the size in bytes when this allocation info struct is serialized. - size_t serializedSize(IndexedVersion Version) const; + size_t serializedSize(const MemProfSchema &Schema, + IndexedVersion Version) const; bool operator==(const IndexedAllocationInfo &Other) const { if (Other.Info != Info) @@ -367,7 +386,8 @@ struct IndexedMemProfRecord { CallSites.append(Other.CallSites); } - size_t serializedSize(IndexedVersion Version) const; + size_t serializedSize(const MemProfSchema &Schema, + IndexedVersion Version) const; bool operator==(const IndexedMemProfRecord &Other) const { if (Other.AllocSites != AllocSites) @@ -535,7 +555,7 @@ public: endian::Writer LE(Out, llvm::endianness::little); offset_type N = sizeof(K); LE.write(N); - offset_type M = V.serializedSize(Version); + offset_type M = V.serializedSize(*Schema, Version); LE.write(M); return std::make_pair(N, M); } diff --git a/llvm/include/llvm/Support/RISCVISAUtils.h b/llvm/include/llvm/Support/RISCVISAUtils.h new file mode 100644 index 0000000000000000000000000000000000000000..94aedb75faa2567730eca23349ec7210b6c63c57 --- /dev/null +++ b/llvm/include/llvm/Support/RISCVISAUtils.h @@ -0,0 +1,42 @@ +//===-- RISCVISAUtils.h - RISC-V ISA Utilities ------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Utilities shared by TableGen and RISCVISAInfo. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_SUPPORT_RISCVISAUTILS_H +#define LLVM_SUPPORT_RISCVISAUTILS_H + +#include "llvm/ADT/StringRef.h" +#include + +namespace llvm { + +namespace RISCVISAUtils { +constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh"; + +/// Represents the major and version number components of a RISC-V extension. +struct ExtensionVersion { + unsigned Major; + unsigned Minor; +}; + +bool compareExtension(const std::string &LHS, const std::string &RHS); + +/// Helper class for OrderedExtensionMap. +struct ExtensionComparator { + bool operator()(const std::string &LHS, const std::string &RHS) const { + return compareExtension(LHS, RHS); + } +}; +} // namespace RISCVISAUtils + +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/TargetParser/CMakeLists.txt b/llvm/include/llvm/TargetParser/CMakeLists.txt index 7f080e01548c7cc9f98fd02f3a488d1c7c59e1b7..f89d4eb5ea1638b02ddaf2e54168e63f8a3b0705 100644 --- a/llvm/include/llvm/TargetParser/CMakeLists.txt +++ b/llvm/include/llvm/TargetParser/CMakeLists.txt @@ -1,3 +1,12 @@ +set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/ARM/ARM.td) +tablegen(LLVM ARMTargetParserDef.inc -gen-arm-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/ARM/) +add_public_tablegen_target(ARMTargetParserTableGen) + +set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/AArch64/AArch64.td) +tablegen(LLVM AArch64TargetParserDef.inc -gen-arm-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/AArch64/) +add_public_tablegen_target(AArch64TargetParserTableGen) + set(LLVM_TARGET_DEFINITIONS ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/RISCV.td) tablegen(LLVM RISCVTargetParserDef.inc -gen-riscv-target-def -I ${PROJECT_SOURCE_DIR}/lib/Target/RISCV/) add_public_tablegen_target(RISCVTargetParserTableGen) + diff --git a/llvm/include/llvm/Support/RISCVISAInfo.h b/llvm/include/llvm/TargetParser/RISCVISAInfo.h similarity index 86% rename from llvm/include/llvm/Support/RISCVISAInfo.h rename to llvm/include/llvm/TargetParser/RISCVISAInfo.h index 46df93d7522602f4477ff63f4dc5285cc09a6538..83c4f1e620fc85dbba7f5df77ba4d5f3271f4749 100644 --- a/llvm/include/llvm/Support/RISCVISAInfo.h +++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h @@ -12,6 +12,7 @@ #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Error.h" +#include "llvm/Support/RISCVISAUtils.h" #include #include @@ -25,24 +26,10 @@ public: RISCVISAInfo(const RISCVISAInfo &) = delete; RISCVISAInfo &operator=(const RISCVISAInfo &) = delete; - /// Represents the major and version number components of a RISC-V extension. - struct ExtensionVersion { - unsigned Major; - unsigned Minor; - }; - - static bool compareExtension(const std::string &LHS, const std::string &RHS); - - /// Helper class for OrderedExtensionMap. - struct ExtensionComparator { - bool operator()(const std::string &LHS, const std::string &RHS) const { - return compareExtension(LHS, RHS); - } - }; - /// OrderedExtensionMap is std::map, it's specialized to keep entries /// in canonical order of extension. - typedef std::map + typedef std::map OrderedExtensionMap; RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts) @@ -105,7 +92,7 @@ private: OrderedExtensionMap Exts; - void addExtension(StringRef ExtName, ExtensionVersion Version); + void addExtension(StringRef ExtName, RISCVISAUtils::ExtensionVersion Version); Error checkDependency(); diff --git a/llvm/include/llvm/Transforms/Utils/Local.h b/llvm/include/llvm/Transforms/Utils/Local.h index 9ae026fa95d21ad1e0786100182e30c5af390ab7..e2143b5bfbe2fdd8883714b63e0d7ae89a7762b5 100644 --- a/llvm/include/llvm/Transforms/Utils/Local.h +++ b/llvm/include/llvm/Transforms/Utils/Local.h @@ -439,6 +439,18 @@ unsigned replaceDominatedUsesWith(Value *From, Value *To, DominatorTree &DT, /// the end of the given BasicBlock. Returns the number of replacements made. unsigned replaceDominatedUsesWith(Value *From, Value *To, DominatorTree &DT, const BasicBlock *BB); +/// Replace each use of 'From' with 'To' if that use is dominated by +/// the given edge and the callback ShouldReplace returns true. Returns the +/// number of replacements made. +unsigned replaceDominatedUsesWithIf( + Value *From, Value *To, DominatorTree &DT, const BasicBlockEdge &Edge, + function_ref ShouldReplace); +/// Replace each use of 'From' with 'To' if that use is dominated by +/// the end of the given BasicBlock and the callback ShouldReplace returns true. +/// Returns the number of replacements made. +unsigned replaceDominatedUsesWithIf( + Value *From, Value *To, DominatorTree &DT, const BasicBlock *BB, + function_ref ShouldReplace); /// Return true if this call calls a gc leaf function. /// diff --git a/llvm/lib/Analysis/Loads.cpp b/llvm/lib/Analysis/Loads.cpp index ac508e19c9e0145d14d747196dc285358e86ef6b..478302d687b534fd9b8619ef6b3d93b894393f97 100644 --- a/llvm/lib/Analysis/Loads.cpp +++ b/llvm/lib/Analysis/Loads.cpp @@ -710,22 +710,62 @@ Value *llvm::FindAvailableLoadedValue(LoadInst *Load, BatchAAResults &AA, return Available; } -bool llvm::canReplacePointersIfEqual(Value *A, Value *B, const DataLayout &DL, - Instruction *CtxI) { - Type *Ty = A->getType(); - assert(Ty == B->getType() && Ty->isPointerTy() && - "values must have matching pointer types"); - - // NOTE: The checks in the function are incomplete and currently miss illegal - // cases! The current implementation is a starting point and the - // implementation should be made stricter over time. - if (auto *C = dyn_cast(B)) { - // Do not allow replacing a pointer with a constant pointer, unless it is - // either null or at least one byte is dereferenceable. - APInt OneByte(DL.getPointerTypeSizeInBits(Ty), 1); - return C->isNullValue() || - isDereferenceableAndAlignedPointer(B, Align(1), OneByte, DL, CtxI); +// Returns true if a use is either in an ICmp/PtrToInt or a Phi/Select that only +// feeds into them. +static bool isPointerUseReplacable(const Use &U) { + unsigned Limit = 40; + SmallVector Worklist({U.getUser()}); + SmallPtrSet Visited; + + while (!Worklist.empty() && --Limit) { + auto *User = Worklist.pop_back_val(); + if (!Visited.insert(User).second) + continue; + if (isa(User)) + continue; + if (isa(User)) + Worklist.append(User->user_begin(), User->user_end()); + else + return false; } - return true; + return Limit != 0; +} + +// Returns true if `To` is a null pointer, constant dereferenceable pointer or +// both pointers have the same underlying objects. +static bool isPointerAlwaysReplaceable(const Value *From, const Value *To, + const DataLayout &DL) { + // This is not strictly correct, but we do it for now to retain important + // optimizations. + if (isa(To)) + return true; + if (isa(To) && + isDereferenceablePointer(To, Type::getInt8Ty(To->getContext()), DL)) + return true; + if (getUnderlyingObject(From) == getUnderlyingObject(To)) + return true; + return false; +} + +bool llvm::canReplacePointersInUseIfEqual(const Use &U, const Value *To, + const DataLayout &DL) { + assert(U->getType() == To->getType() && "values must have matching types"); + // Not a pointer, just return true. + if (!To->getType()->isPointerTy()) + return true; + + if (isPointerAlwaysReplaceable(&*U, To, DL)) + return true; + return isPointerUseReplacable(U); +} + +bool llvm::canReplacePointersIfEqual(const Value *From, const Value *To, + const DataLayout &DL) { + assert(From->getType() == To->getType() && "values must have matching types"); + // Not a pointer, just return true. + if (!From->getType()->isPointerTy()) + return true; + + return isPointerAlwaysReplaceable(From, To, DL); } diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index 21e3f8a4cc52c713d53de3c8d5ebdf8b06125141..de38eddaa98feffc2c69182be6d2358fb73418c2 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -2632,6 +2632,13 @@ static bool isKnownNonZeroFromOperator(const Operator *I, Q.DL.getTypeSizeInBits(I->getType()).getFixedValue()) return isKnownNonZero(I->getOperand(0), Q, Depth); break; + case Instruction::Trunc: + // nuw/nsw trunc preserves zero/non-zero status of input. + if (auto *TI = dyn_cast(I)) + if (TI->hasNoSignedWrap() || TI->hasNoUnsignedWrap()) + return isKnownNonZero(TI->getOperand(0), Q, Depth); + break; + case Instruction::Sub: return isNonZeroSub(DemandedElts, Depth, Q, BitWidth, I->getOperand(0), I->getOperand(1)); @@ -8042,17 +8049,27 @@ static SelectPatternResult matchMinMax(CmpInst::Predicate Pred, return {SPF_UNKNOWN, SPNB_NA, false}; } -bool llvm::isKnownNegation(const Value *X, const Value *Y, bool NeedNSW) { +bool llvm::isKnownNegation(const Value *X, const Value *Y, bool NeedNSW, + bool AllowPoison) { assert(X && Y && "Invalid operand"); - // X = sub (0, Y) || X = sub nsw (0, Y) - if ((!NeedNSW && match(X, m_Sub(m_ZeroInt(), m_Specific(Y)))) || - (NeedNSW && match(X, m_NSWNeg(m_Specific(Y))))) + auto IsNegationOf = [&](const Value *X, const Value *Y) { + if (!match(X, m_Neg(m_Specific(Y)))) + return false; + + auto *BO = cast(X); + if (NeedNSW && !BO->hasNoSignedWrap()) + return false; + + auto *Zero = cast(BO->getOperand(0)); + if (!AllowPoison && !Zero->isNullValue()) + return false; + return true; + }; - // Y = sub (0, X) || Y = sub nsw (0, X) - if ((!NeedNSW && match(Y, m_Sub(m_ZeroInt(), m_Specific(X)))) || - (NeedNSW && match(Y, m_NSWNeg(m_Specific(X))))) + // X = -Y or Y = -X + if (IsNegationOf(X, Y) || IsNegationOf(Y, X)) return true; // X = sub (A, B), Y = sub (B, A) || X = sub nsw (A, B), Y = sub nsw (B, A) diff --git a/llvm/lib/Analysis/VectorUtils.cpp b/llvm/lib/Analysis/VectorUtils.cpp index bf7bc0ba84a03362fe908ae47853d9594d7186c8..917094267d05ae425a2ca837cc1a464af51e6351 100644 --- a/llvm/lib/Analysis/VectorUtils.cpp +++ b/llvm/lib/Analysis/VectorUtils.cpp @@ -23,6 +23,7 @@ #include "llvm/IR/Constants.h" #include "llvm/IR/DerivedTypes.h" #include "llvm/IR/IRBuilder.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/PatternMatch.h" #include "llvm/IR/Value.h" #include "llvm/Support/CommandLine.h" @@ -793,13 +794,17 @@ Instruction *llvm::propagateMetadata(Instruction *Inst, ArrayRef VL) { for (auto Kind : {LLVMContext::MD_tbaa, LLVMContext::MD_alias_scope, LLVMContext::MD_noalias, LLVMContext::MD_fpmath, LLVMContext::MD_nontemporal, LLVMContext::MD_invariant_load, - LLVMContext::MD_access_group}) { + LLVMContext::MD_access_group, LLVMContext::MD_mmra}) { MDNode *MD = I0->getMetadata(Kind); - for (int J = 1, E = VL.size(); MD && J != E; ++J) { const Instruction *IJ = cast(VL[J]); MDNode *IMD = IJ->getMetadata(Kind); + switch (Kind) { + case LLVMContext::MD_mmra: { + MD = MMRAMetadata::combine(Inst->getContext(), MD, IMD); + break; + } case LLVMContext::MD_tbaa: MD = MDNode::getMostGenericTBAA(MD, IMD); break; diff --git a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp index ed6ce6bc73d38c9675c1f840eee02b5cb924f094..e91750afd281719a3e9014fabfa97f72bbd6e106 100644 --- a/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp +++ b/llvm/lib/CodeGen/AggressiveAntiDepBreaker.cpp @@ -231,9 +231,9 @@ bool AggressiveAntiDepBreaker::IsImplicitDefUse(MachineInstr &MI, MachineOperand *Op = nullptr; if (MO.isDef()) - Op = MI.findRegisterUseOperand(Reg, true); + Op = MI.findRegisterUseOperand(Reg, /*TRI=*/nullptr, true); else - Op = MI.findRegisterDefOperand(Reg); + Op = MI.findRegisterDefOperand(Reg, /*TRI=*/nullptr); return(Op && Op->isImplicit()); } @@ -679,7 +679,7 @@ bool AggressiveAntiDepBreaker::FindSuitableFreeRegisters( // defines 'NewReg' via an early-clobber operand. for (const auto &Q : make_range(RegRefs.equal_range(Reg))) { MachineInstr *UseMI = Q.second.Operand->getParent(); - int Idx = UseMI->findRegisterDefOperandIdx(NewReg, false, true, TRI); + int Idx = UseMI->findRegisterDefOperandIdx(NewReg, TRI, false, true); if (Idx == -1) continue; @@ -846,7 +846,8 @@ unsigned AggressiveAntiDepBreaker::BreakAntiDependencies( continue; } else { // No anti-dep breaking for implicit deps - MachineOperand *AntiDepOp = MI.findRegisterDefOperand(AntiDepReg); + MachineOperand *AntiDepOp = + MI.findRegisterDefOperand(AntiDepReg, /*TRI=*/nullptr); assert(AntiDepOp && "Can't find index for defined register operand"); if (!AntiDepOp || AntiDepOp->isImplicit()) { LLVM_DEBUG(dbgs() << " (implicit)\n"); diff --git a/llvm/lib/CodeGen/AtomicExpandPass.cpp b/llvm/lib/CodeGen/AtomicExpandPass.cpp index e5496c0e31c1c02674af90ce1865dcdd8df1c6e4..f3b8097396e266ad3830cdfcc4d5a9d88314ec5e 100644 --- a/llvm/lib/CodeGen/AtomicExpandPass.cpp +++ b/llvm/lib/CodeGen/AtomicExpandPass.cpp @@ -37,6 +37,7 @@ #include "llvm/IR/InstIterator.h" #include "llvm/IR/Instruction.h" #include "llvm/IR/Instructions.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/Module.h" #include "llvm/IR/Type.h" #include "llvm/IR/User.h" @@ -133,15 +134,27 @@ public: }; // IRBuilder to be used for replacement atomic instructions. -struct ReplacementIRBuilder : IRBuilder { +struct ReplacementIRBuilder + : IRBuilder { + MDNode *MMRAMD = nullptr; + // Preserves the DebugLoc from I, and preserves still valid metadata. // Enable StrictFP builder mode when appropriate. explicit ReplacementIRBuilder(Instruction *I, const DataLayout &DL) - : IRBuilder(I->getContext(), DL) { + : IRBuilder(I->getContext(), DL, + IRBuilderCallbackInserter( + [this](Instruction *I) { addMMRAMD(I); })) { SetInsertPoint(I); this->CollectMetadataToCopy(I, {LLVMContext::MD_pcsections}); if (BB->getParent()->getAttributes().hasFnAttr(Attribute::StrictFP)) this->setIsFPConstrained(true); + + MMRAMD = I->getMetadata(LLVMContext::MD_mmra); + } + + void addMMRAMD(Instruction *I) { + if (canInstructionHaveMMRAs(*I)) + I->setMetadata(LLVMContext::MD_mmra, MMRAMD); } }; @@ -421,8 +434,9 @@ AtomicExpandImpl::convertAtomicXchgToIntegerType(AtomicRMWInst *RMWI) { ? Builder.CreatePtrToInt(Val, NewTy) : Builder.CreateBitCast(Val, NewTy); - auto *NewRMWI = Builder.CreateAtomicRMW( - AtomicRMWInst::Xchg, Addr, NewVal, RMWI->getAlign(), RMWI->getOrdering()); + auto *NewRMWI = Builder.CreateAtomicRMW(AtomicRMWInst::Xchg, Addr, NewVal, + RMWI->getAlign(), RMWI->getOrdering(), + RMWI->getSyncScopeID()); NewRMWI->setVolatile(RMWI->isVolatile()); LLVM_DEBUG(dbgs() << "Replaced " << *RMWI << " with " << *NewRMWI << "\n"); diff --git a/llvm/lib/CodeGen/CalcSpillWeights.cpp b/llvm/lib/CodeGen/CalcSpillWeights.cpp index f3cb7fa5af61481df1ffed2a5a06d3e42bb097cd..1d767a3484bcadbf2339636aa2690c1f6ae1a955 100644 --- a/llvm/lib/CodeGen/CalcSpillWeights.cpp +++ b/llvm/lib/CodeGen/CalcSpillWeights.cpp @@ -251,7 +251,8 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start, // For terminators that produce values, ask the backend if the register is // not spillable. - if (TII.isUnspillableTerminator(MI) && MI->definesRegister(LI.reg())) { + if (TII.isUnspillableTerminator(MI) && + MI->definesRegister(LI.reg(), /*TRI=*/nullptr)) { LI.markNotSpillable(); return -1.0f; } diff --git a/llvm/lib/CodeGen/CodeGenCommonISel.cpp b/llvm/lib/CodeGen/CodeGenCommonISel.cpp index 577c5dbc8e2da8e855edfb579dd684bdfbd9298f..fe144d3c1820390e824867d161870a3a8f9a05d6 100644 --- a/llvm/lib/CodeGen/CodeGenCommonISel.cpp +++ b/llvm/lib/CodeGen/CodeGenCommonISel.cpp @@ -260,7 +260,8 @@ void llvm::salvageDebugInfoForDbgValue(const MachineRegisterInfo &MRI, continue; } - int UseMOIdx = DbgMI->findRegisterUseOperandIdx(DefMO->getReg()); + int UseMOIdx = + DbgMI->findRegisterUseOperandIdx(DefMO->getReg(), /*TRI=*/nullptr); assert(UseMOIdx != -1 && DbgMI->hasDebugOperandForReg(DefMO->getReg()) && "Must use salvaged instruction as its location"); diff --git a/llvm/lib/CodeGen/EarlyIfConversion.cpp b/llvm/lib/CodeGen/EarlyIfConversion.cpp index 31e107ade1ccbb00784e4325d15a5b6e8e05b0ab..2a7bee1618deb25acb93898b76b3962368779c8c 100644 --- a/llvm/lib/CodeGen/EarlyIfConversion.cpp +++ b/llvm/lib/CodeGen/EarlyIfConversion.cpp @@ -599,8 +599,8 @@ static bool hasSameValue(const MachineRegisterInfo &MRI, return false; // Further, check that the two defs come from corresponding operands. - int TIdx = TDef->findRegisterDefOperandIdx(TReg); - int FIdx = FDef->findRegisterDefOperandIdx(FReg); + int TIdx = TDef->findRegisterDefOperandIdx(TReg, /*TRI=*/nullptr); + int FIdx = FDef->findRegisterDefOperandIdx(FReg, /*TRI=*/nullptr); if (TIdx == -1 || FIdx == -1) return false; diff --git a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp index 4d668c53f7156b8de85c92db0f6abaf2f8573d3b..3bb9da5f1a37bb42f3b70eec1c2627aee1520ece 100644 --- a/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp +++ b/llvm/lib/CodeGen/FixupStatepointCallerSaved.cpp @@ -112,7 +112,7 @@ static Register performCopyPropagation(Register Reg, bool &IsKill, const TargetInstrInfo &TII, const TargetRegisterInfo &TRI) { // First check if statepoint itself uses Reg in non-meta operands. - int Idx = RI->findRegisterUseOperandIdx(Reg, false, &TRI); + int Idx = RI->findRegisterUseOperandIdx(Reg, &TRI, false); if (Idx >= 0 && (unsigned)Idx < StatepointOpers(&*RI).getNumDeoptArgsIdx()) { IsKill = false; return Reg; diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp index 5545ec3b3ed0c661dd72d3a93dfe39e560134eb3..653e7689b577435e07618a6fd05c3dad371e14c8 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp @@ -2800,8 +2800,8 @@ bool CombinerHelper::matchEqualDefs(const MachineOperand &MOP1, // %5:_(s8), %6:_(s8), %7:_(s8), %8:_(s8) = G_UNMERGE_VALUES %4:_(<4 x s8>) // I1 and I2 are different instructions but produce same values, // %1 and %6 are same, %1 and %7 are not the same value. - return I1->findRegisterDefOperandIdx(InstAndDef1->Reg) == - I2->findRegisterDefOperandIdx(InstAndDef2->Reg); + return I1->findRegisterDefOperandIdx(InstAndDef1->Reg, /*TRI=*/nullptr) == + I2->findRegisterDefOperandIdx(InstAndDef2->Reg, /*TRI=*/nullptr); } return false; } @@ -5069,6 +5069,9 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) { const unsigned EltBits = ScalarTy.getScalarSizeInBits(); LLT ShiftAmtTy = getTargetLowering().getPreferredShiftAmountTy(Ty); LLT ScalarShiftAmtTy = ShiftAmtTy.getScalarType(); + + unsigned KnownLeadingZeros = + KB ? KB->getKnownBits(LHS).countMinLeadingZeros() : 0; auto &MIB = Builder; bool UseNPQ = false; @@ -5086,8 +5089,12 @@ MachineInstr *CombinerHelper::buildUDivUsingMul(MachineInstr &MI) { // at the end. // TODO: Use undef values for divisor of 1. if (!Divisor.isOne()) { + + // UnsignedDivisionByConstantInfo doesn't work correctly if leading zeros + // in the dividend exceeds the leading zeros for the divisor. UnsignedDivisionByConstantInfo magics = - UnsignedDivisionByConstantInfo::get(Divisor); + UnsignedDivisionByConstantInfo::get( + Divisor, std::min(KnownLeadingZeros, Divisor.countl_zero())); Magic = std::move(magics.Magic); diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index 0b6aae3759756f35c116f7a9c7229a4615b5ce03..8cf392ab0567e5774d0ed7caf760234bd73387ef 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -3446,6 +3446,7 @@ void IRTranslator::translateDbgInfo(const Instruction &Inst, bool IRTranslator::translate(const Instruction &Inst) { CurBuilder->setDebugLoc(Inst.getDebugLoc()); CurBuilder->setPCSections(Inst.getMetadata(LLVMContext::MD_pcsections)); + CurBuilder->setMMRAMetadata(Inst.getMetadata(LLVMContext::MD_mmra)); if (TLI->fallBackToDAGISel(Inst)) return false; diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp index d55091e2e717395abfb4fbb8ce281e0bb3509116..6a76ad7f5db749bdc2ff22db2b7e842cd37aeeb3 100644 --- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp +++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp @@ -4764,6 +4764,8 @@ LegalizerHelper::fewerElementsVector(MachineInstr &MI, unsigned TypeIdx, return fewerElementsVectorMultiEltType(GMI, NumElts, {2 /*pow*/}); case G_BITCAST: return fewerElementsBitcast(MI, TypeIdx, NarrowTy); + case G_INTRINSIC_FPTRUNC_ROUND: + return fewerElementsVectorMultiEltType(GMI, NumElts, {2}); default: return UnableToLegalize; } diff --git a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp index 6b35caf834918bbb90684ef937a7fbafafac8025..2e8407813ba641605a4138c3e62a0392df6c3fb8 100644 --- a/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp +++ b/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp @@ -28,6 +28,7 @@ void MachineIRBuilder::setMF(MachineFunction &MF) { State.TII = MF.getSubtarget().getInstrInfo(); State.DL = DebugLoc(); State.PCSections = nullptr; + State.MMRA = nullptr; State.II = MachineBasicBlock::iterator(); State.Observer = nullptr; } @@ -37,7 +38,8 @@ void MachineIRBuilder::setMF(MachineFunction &MF) { //------------------------------------------------------------------------------ MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) { - return BuildMI(getMF(), {getDL(), getPCSections()}, getTII().get(Opcode)); + return BuildMI(getMF(), {getDL(), getPCSections(), getMMRAMetadata()}, + getTII().get(Opcode)); } MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) { diff --git a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp index bb5363fb2527b58d6cf9e4402497f048b86458a2..383cb61aed41073c659dff9a401cc25de260fea9 100644 --- a/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp +++ b/llvm/lib/CodeGen/GlobalISel/RegBankSelect.cpp @@ -420,7 +420,8 @@ void RegBankSelect::tryAvoidingSplit( // If the next terminator uses Reg, this means we have // to split right after MI and thus we need a way to ask // which outgoing edges are affected. - assert(!Next->readsRegister(Reg) && "Need to split between terminators"); + assert(!Next->readsRegister(Reg, /*TRI=*/nullptr) && + "Need to split between terminators"); // We will split all the edges and repair there. } else { // This is a virtual register defined by a terminator. diff --git a/llvm/lib/CodeGen/InlineSpiller.cpp b/llvm/lib/CodeGen/InlineSpiller.cpp index c46b1fe18ca7434ca8119ddfe8f18a4046cc2375..69c671220db35374f845ba42495c3173a882eaee 100644 --- a/llvm/lib/CodeGen/InlineSpiller.cpp +++ b/llvm/lib/CodeGen/InlineSpiller.cpp @@ -869,7 +869,7 @@ static void dumpMachineInstrRangeWithSlotIndex(MachineBasicBlock::iterator B, // destination that is marked as an early clobber, print the // early-clobber slot index. if (VReg) { - MachineOperand *MO = I->findRegisterDefOperand(VReg); + MachineOperand *MO = I->findRegisterDefOperand(VReg, /*TRI=*/nullptr); if (MO && MO->isEarlyClobber()) Idx = Idx.getRegSlot(true); } diff --git a/llvm/lib/CodeGen/LiveVariables.cpp b/llvm/lib/CodeGen/LiveVariables.cpp index b85526cfb380b6a6bafee4eea2f3163f29a912d5..f44db575a92506b17fa6464b2a1b9e0c395c28e3 100644 --- a/llvm/lib/CodeGen/LiveVariables.cpp +++ b/llvm/lib/CodeGen/LiveVariables.cpp @@ -258,7 +258,7 @@ void LiveVariables::HandlePhysRegUse(Register Reg, MachineInstr &MI) { } } } else if (LastDef && !PhysRegUse[Reg] && - !LastDef->findRegisterDefOperand(Reg)) + !LastDef->findRegisterDefOperand(Reg, /*TRI=*/nullptr)) // Last def defines the super register, add an implicit def of reg. LastDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, true/*IsImp*/)); @@ -361,7 +361,8 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) { continue; bool NeedDef = true; if (PhysRegDef[Reg] == PhysRegDef[SubReg]) { - MachineOperand *MO = PhysRegDef[Reg]->findRegisterDefOperand(SubReg); + MachineOperand *MO = + PhysRegDef[Reg]->findRegisterDefOperand(SubReg, /*TRI=*/nullptr); if (MO) { NeedDef = false; assert(!MO->isDead()); @@ -388,7 +389,7 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) { true/*IsImp*/, true/*IsKill*/)); else { MachineOperand *MO = - LastRefOrPartRef->findRegisterDefOperand(Reg, false, false, TRI); + LastRefOrPartRef->findRegisterDefOperand(Reg, TRI, false, false); bool NeedEC = MO->isEarlyClobber() && MO->getReg() != Reg; // If the last reference is the last def, then it's not used at all. // That is, unless we are currently processing the last reference itself. @@ -396,7 +397,7 @@ bool LiveVariables::HandlePhysRegKill(Register Reg, MachineInstr *MI) { if (NeedEC) { // If we are adding a subreg def and the superreg def is marked early // clobber, add an early clobber marker to the subreg def. - MO = LastRefOrPartRef->findRegisterDefOperand(Reg); + MO = LastRefOrPartRef->findRegisterDefOperand(Reg, /*TRI=*/nullptr); if (MO) MO->setIsEarlyClobber(); } @@ -727,7 +728,7 @@ void LiveVariables::recomputeForSingleDefVirtReg(Register Reg) { if (MI.isPHI()) break; if (MI.readsVirtualRegister(Reg)) { - assert(!MI.killsRegister(Reg)); + assert(!MI.killsRegister(Reg, /*TRI=*/nullptr)); MI.addRegisterKilled(Reg, nullptr); VI.Kills.push_back(&MI); break; diff --git a/llvm/lib/CodeGen/MIRPrinter.cpp b/llvm/lib/CodeGen/MIRPrinter.cpp index bf3aee67ec00285c9e5fa7521bf938f4094984d2..6751fcf97087c74d84d1b2e75538c5fc87e34c90 100644 --- a/llvm/lib/CodeGen/MIRPrinter.cpp +++ b/llvm/lib/CodeGen/MIRPrinter.cpp @@ -856,6 +856,13 @@ void MIPrinter::print(const MachineInstr &MI) { PCSections->printAsOperand(OS, MST); NeedComma = true; } + if (MDNode *MMRA = MI.getMMRAMetadata()) { + if (NeedComma) + OS << ','; + OS << " mmra "; + MMRA->printAsOperand(OS, MST); + NeedComma = true; + } if (uint32_t CFIType = MI.getCFIType()) { if (NeedComma) OS << ','; diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index 26a8d00e6626519ee4fb2d9f2194cf950eb556f4..42cdcaa5bbf4f23c80bde6f275bb09191bc408d8 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -709,7 +709,7 @@ bool MachineCSE::ProcessBlockCSE(MachineBasicBlock *MBB) { for (MachineBasicBlock::iterator II = CSMI, IE = &MI; II != IE; ++II) for (auto ImplicitDef : ImplicitDefs) if (MachineOperand *MO = II->findRegisterUseOperand( - ImplicitDef, /*isKill=*/true, TRI)) + ImplicitDef, TRI, /*isKill=*/true)) MO->setIsKill(false); } else { // If the instructions aren't in the same BB, bail out and clear the diff --git a/llvm/lib/CodeGen/MachineCombiner.cpp b/llvm/lib/CodeGen/MachineCombiner.cpp index ac58162bbfb4208756579d1277a9f21a62a6b196..c11263163a34ff9a240d24e1f7d0a42cb1b0cba1 100644 --- a/llvm/lib/CodeGen/MachineCombiner.cpp +++ b/llvm/lib/CodeGen/MachineCombiner.cpp @@ -229,8 +229,10 @@ MachineCombiner::getDepth(SmallVectorImpl &InsInstrs, assert(DefInstr && "There must be a definition for a new virtual register"); DepthOp = InstrDepth[II->second]; - int DefIdx = DefInstr->findRegisterDefOperandIdx(MO.getReg()); - int UseIdx = InstrPtr->findRegisterUseOperandIdx(MO.getReg()); + int DefIdx = + DefInstr->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr); + int UseIdx = + InstrPtr->findRegisterUseOperandIdx(MO.getReg(), /*TRI=*/nullptr); LatencyOp = TSchedModel.computeOperandLatency(DefInstr, DefIdx, InstrPtr, UseIdx); } else { @@ -241,8 +243,12 @@ MachineCombiner::getDepth(SmallVectorImpl &InsInstrs, DepthOp = BlockTrace.getInstrCycles(*DefInstr).Depth; if (!isTransientMI(DefInstr)) LatencyOp = TSchedModel.computeOperandLatency( - DefInstr, DefInstr->findRegisterDefOperandIdx(MO.getReg()), - InstrPtr, InstrPtr->findRegisterUseOperandIdx(MO.getReg())); + DefInstr, + DefInstr->findRegisterDefOperandIdx(MO.getReg(), + /*TRI=*/nullptr), + InstrPtr, + InstrPtr->findRegisterUseOperandIdx(MO.getReg(), + /*TRI=*/nullptr)); } } IDepth = std::max(IDepth, DepthOp + LatencyOp); @@ -280,8 +286,10 @@ unsigned MachineCombiner::getLatency(MachineInstr *Root, MachineInstr *NewRoot, unsigned LatencyOp = 0; if (UseMO && BlockTrace.isDepInTrace(*Root, *UseMO)) { LatencyOp = TSchedModel.computeOperandLatency( - NewRoot, NewRoot->findRegisterDefOperandIdx(MO.getReg()), UseMO, - UseMO->findRegisterUseOperandIdx(MO.getReg())); + NewRoot, + NewRoot->findRegisterDefOperandIdx(MO.getReg(), /*TRI=*/nullptr), + UseMO, + UseMO->findRegisterUseOperandIdx(MO.getReg(), /*TRI=*/nullptr)); } else { LatencyOp = TSchedModel.computeInstrLatency(NewRoot); } diff --git a/llvm/lib/CodeGen/MachineCopyPropagation.cpp b/llvm/lib/CodeGen/MachineCopyPropagation.cpp index 8dc6781fcb018f1ff01ef32a5b64abd0c065345a..c82f00316147bc056b58b3e86e07a063f20c7767 100644 --- a/llvm/lib/CodeGen/MachineCopyPropagation.cpp +++ b/llvm/lib/CodeGen/MachineCopyPropagation.cpp @@ -737,7 +737,7 @@ void MachineCopyPropagation::forwardUses(MachineInstr &MI) { // cannot cope with that. if (isCopyInstr(MI, *TII, UseCopyInstr) && MI.modifiesRegister(CopySrcReg, TRI) && - !MI.definesRegister(CopySrcReg)) { + !MI.definesRegister(CopySrcReg, /*TRI=*/nullptr)) { LLVM_DEBUG(dbgs() << "MCP: Copy source overlap with dest in " << MI); continue; } diff --git a/llvm/lib/CodeGen/MachineFunction.cpp b/llvm/lib/CodeGen/MachineFunction.cpp index ad532149926670949f09d213f56c42e5419c9175..8366ad2859069fe73a6c8e749678869b3027b227 100644 --- a/llvm/lib/CodeGen/MachineFunction.cpp +++ b/llvm/lib/CodeGen/MachineFunction.cpp @@ -573,10 +573,10 @@ MachineFunction::getMachineMemOperand(const MachineMemOperand *MMO, MachineInstr::ExtraInfo *MachineFunction::createMIExtraInfo( ArrayRef MMOs, MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, MDNode *HeapAllocMarker, MDNode *PCSections, - uint32_t CFIType) { + uint32_t CFIType, MDNode *MMRAs) { return MachineInstr::ExtraInfo::create(Allocator, MMOs, PreInstrSymbol, PostInstrSymbol, HeapAllocMarker, - PCSections, CFIType); + PCSections, CFIType, MMRAs); } const char *MachineFunction::createExternalSymbolName(StringRef Name) { diff --git a/llvm/lib/CodeGen/MachineInstr.cpp b/llvm/lib/CodeGen/MachineInstr.cpp index 83604003a038bd78da3497b08f240da15f0f72f6..02479f31f0b692bf6282452f1489c24a6d5c3bc0 100644 --- a/llvm/lib/CodeGen/MachineInstr.cpp +++ b/llvm/lib/CodeGen/MachineInstr.cpp @@ -318,14 +318,15 @@ void MachineInstr::setExtraInfo(MachineFunction &MF, MCSymbol *PreInstrSymbol, MCSymbol *PostInstrSymbol, MDNode *HeapAllocMarker, MDNode *PCSections, - uint32_t CFIType) { + uint32_t CFIType, MDNode *MMRAs) { bool HasPreInstrSymbol = PreInstrSymbol != nullptr; bool HasPostInstrSymbol = PostInstrSymbol != nullptr; bool HasHeapAllocMarker = HeapAllocMarker != nullptr; bool HasPCSections = PCSections != nullptr; bool HasCFIType = CFIType != 0; + bool HasMMRAs = MMRAs != nullptr; int NumPointers = MMOs.size() + HasPreInstrSymbol + HasPostInstrSymbol + - HasHeapAllocMarker + HasPCSections + HasCFIType; + HasHeapAllocMarker + HasPCSections + HasCFIType + HasMMRAs; // Drop all extra info if there is none. if (NumPointers <= 0) { @@ -337,11 +338,11 @@ void MachineInstr::setExtraInfo(MachineFunction &MF, // out of line because PointerSumType cannot hold more than 4 tag types with // 32-bit pointers. // FIXME: Maybe we should make the symbols in the extra info mutable? - else if (NumPointers > 1 || HasHeapAllocMarker || HasPCSections || + else if (NumPointers > 1 || HasMMRAs || HasHeapAllocMarker || HasPCSections || HasCFIType) { Info.set( MF.createMIExtraInfo(MMOs, PreInstrSymbol, PostInstrSymbol, - HeapAllocMarker, PCSections, CFIType)); + HeapAllocMarker, PCSections, CFIType, MMRAs)); return; } @@ -359,7 +360,8 @@ void MachineInstr::dropMemRefs(MachineFunction &MF) { return; setExtraInfo(MF, {}, getPreInstrSymbol(), getPostInstrSymbol(), - getHeapAllocMarker(), getPCSections(), getCFIType()); + getHeapAllocMarker(), getPCSections(), getCFIType(), + getMMRAMetadata()); } void MachineInstr::setMemRefs(MachineFunction &MF, @@ -370,7 +372,8 @@ void MachineInstr::setMemRefs(MachineFunction &MF, } setExtraInfo(MF, MMOs, getPreInstrSymbol(), getPostInstrSymbol(), - getHeapAllocMarker(), getPCSections(), getCFIType()); + getHeapAllocMarker(), getPCSections(), getCFIType(), + getMMRAMetadata()); } void MachineInstr::addMemOperand(MachineFunction &MF, @@ -394,7 +397,8 @@ void MachineInstr::cloneMemRefs(MachineFunction &MF, const MachineInstr &MI) { if (getPreInstrSymbol() == MI.getPreInstrSymbol() && getPostInstrSymbol() == MI.getPostInstrSymbol() && getHeapAllocMarker() == MI.getHeapAllocMarker() && - getPCSections() == MI.getPCSections()) { + getPCSections() == MI.getPCSections() && getMMRAMetadata() && + MI.getMMRAMetadata()) { Info = MI.Info; return; } @@ -479,7 +483,8 @@ void MachineInstr::setPreInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { } setExtraInfo(MF, memoperands(), Symbol, getPostInstrSymbol(), - getHeapAllocMarker(), getPCSections(), getCFIType()); + getHeapAllocMarker(), getPCSections(), getCFIType(), + getMMRAMetadata()); } void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { @@ -494,7 +499,8 @@ void MachineInstr::setPostInstrSymbol(MachineFunction &MF, MCSymbol *Symbol) { } setExtraInfo(MF, memoperands(), getPreInstrSymbol(), Symbol, - getHeapAllocMarker(), getPCSections(), getCFIType()); + getHeapAllocMarker(), getPCSections(), getCFIType(), + getMMRAMetadata()); } void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) { @@ -503,7 +509,7 @@ void MachineInstr::setHeapAllocMarker(MachineFunction &MF, MDNode *Marker) { return; setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(), - Marker, getPCSections(), getCFIType()); + Marker, getPCSections(), getCFIType(), getMMRAMetadata()); } void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) { @@ -512,7 +518,8 @@ void MachineInstr::setPCSections(MachineFunction &MF, MDNode *PCSections) { return; setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(), - getHeapAllocMarker(), PCSections, getCFIType()); + getHeapAllocMarker(), PCSections, getCFIType(), + getMMRAMetadata()); } void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) { @@ -521,7 +528,16 @@ void MachineInstr::setCFIType(MachineFunction &MF, uint32_t Type) { return; setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(), - getHeapAllocMarker(), getPCSections(), Type); + getHeapAllocMarker(), getPCSections(), Type, getMMRAMetadata()); +} + +void MachineInstr::setMMRAMetadata(MachineFunction &MF, MDNode *MMRAs) { + // Do nothing if old and new symbols are the same. + if (MMRAs == getMMRAMetadata()) + return; + + setExtraInfo(MF, memoperands(), getPreInstrSymbol(), getPostInstrSymbol(), + getHeapAllocMarker(), getPCSections(), getCFIType(), MMRAs); } void MachineInstr::cloneInstrSymbols(MachineFunction &MF, @@ -537,6 +553,7 @@ void MachineInstr::cloneInstrSymbols(MachineFunction &MF, setPostInstrSymbol(MF, MI.getPostInstrSymbol()); setHeapAllocMarker(MF, MI.getHeapAllocMarker()); setPCSections(MF, MI.getPCSections()); + setMMRAMetadata(MF, MI.getMMRAMetadata()); } uint32_t MachineInstr::mergeFlagsWith(const MachineInstr &Other) const { @@ -1028,8 +1045,9 @@ bool MachineInstr::hasRegisterImplicitUseOperand(Register Reg) const { /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of /// the specific register or -1 if it is not found. It further tightens /// the search criteria to a use that kills the register if isKill is true. -int MachineInstr::findRegisterUseOperandIdx( - Register Reg, bool isKill, const TargetRegisterInfo *TRI) const { +int MachineInstr::findRegisterUseOperandIdx(Register Reg, + const TargetRegisterInfo *TRI, + bool isKill) const { for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); if (!MO.isReg() || !MO.isUse()) @@ -1076,9 +1094,9 @@ MachineInstr::readsWritesVirtualRegister(Register Reg, /// the specified register or -1 if it is not found. If isDead is true, defs /// that are not dead are skipped. If TargetRegisterInfo is non-null, then it /// also checks if there is a def of a super-register. -int -MachineInstr::findRegisterDefOperandIdx(Register Reg, bool isDead, bool Overlap, - const TargetRegisterInfo *TRI) const { +int MachineInstr::findRegisterDefOperandIdx(Register Reg, + const TargetRegisterInfo *TRI, + bool isDead, bool Overlap) const { bool isPhys = Reg.isPhysical(); for (unsigned i = 0, e = getNumOperands(); i != e; ++i) { const MachineOperand &MO = getOperand(i); @@ -1881,6 +1899,14 @@ void MachineInstr::print(raw_ostream &OS, ModuleSlotTracker &MST, OS << " pcsections "; PCSections->printAsOperand(OS, MST); } + if (MDNode *MMRA = getMMRAMetadata()) { + if (!FirstOp) { + FirstOp = false; + OS << ','; + } + OS << " mmra "; + MMRA->printAsOperand(OS, MST); + } if (uint32_t CFIType = getCFIType()) { if (!FirstOp) OS << ','; @@ -2111,7 +2137,7 @@ void MachineInstr::setRegisterDefReadUndef(Register Reg, bool IsUndef) { void MachineInstr::addRegisterDefined(Register Reg, const TargetRegisterInfo *RegInfo) { if (Reg.isPhysical()) { - MachineOperand *MO = findRegisterDefOperand(Reg, false, false, RegInfo); + MachineOperand *MO = findRegisterDefOperand(Reg, RegInfo, false, false); if (MO) return; } else { diff --git a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp index aa1eb7c354255d962eb9b55e387082979a7977a2..1f596cd1bd2ec1e06abf35af167a6c744cf338a4 100644 --- a/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp +++ b/llvm/lib/CodeGen/MachineLateInstrsCleanup.cpp @@ -230,7 +230,7 @@ bool MachineLateInstrsCleanup::processBlock(MachineBasicBlock *MBB) { if (MI.modifiesRegister(Reg, TRI)) { MBBDefs.erase(Reg); MBBKills.erase(Reg); - } else if (MI.findRegisterUseOperandIdx(Reg, true /*isKill*/, TRI) != -1) + } else if (MI.findRegisterUseOperandIdx(Reg, TRI, true /*isKill*/) != -1) // Keep track of register kills. MBBKills[Reg] = &MI; } diff --git a/llvm/lib/CodeGen/MachineSink.cpp b/llvm/lib/CodeGen/MachineSink.cpp index c3a1d3759882d8d97beeb0cda05bc7f48e010f55..3d40130b92c443e25b9160784a579e13cc884ee0 100644 --- a/llvm/lib/CodeGen/MachineSink.cpp +++ b/llvm/lib/CodeGen/MachineSink.cpp @@ -309,7 +309,7 @@ static bool blockPrologueInterferes(const MachineBasicBlock *BB, if (PI->readsRegister(Reg, TRI)) return true; // Check for interference with non-dead defs - auto *DefOp = PI->findRegisterDefOperand(Reg, false, true, TRI); + auto *DefOp = PI->findRegisterDefOperand(Reg, TRI, false, true); if (DefOp && !DefOp->isDead()) return true; } diff --git a/llvm/lib/CodeGen/ModuloSchedule.cpp b/llvm/lib/CodeGen/ModuloSchedule.cpp index bdae94c4e6f885c69782f46474d81cd180bd7fca..b912112b16362e13fed1de8819c49cf0d8981a35 100644 --- a/llvm/lib/CodeGen/ModuloSchedule.cpp +++ b/llvm/lib/CodeGen/ModuloSchedule.cpp @@ -814,7 +814,7 @@ void ModuloScheduleExpander::splitLifetimes(MachineBasicBlock *KernelBB, unsigned SplitReg = 0; for (auto &BBJ : make_range(MachineBasicBlock::instr_iterator(MI), KernelBB->instr_end())) - if (BBJ.readsRegister(Def)) { + if (BBJ.readsRegister(Def, /*TRI=*/nullptr)) { // We split the lifetime when we find the first use. if (SplitReg == 0) { SplitReg = MRI.createVirtualRegister(MRI.getRegClass(Def)); @@ -829,7 +829,7 @@ void ModuloScheduleExpander::splitLifetimes(MachineBasicBlock *KernelBB, // Search through each of the epilog blocks for any uses to be renamed. for (auto &Epilog : EpilogBBs) for (auto &I : *Epilog) - if (I.readsRegister(Def)) + if (I.readsRegister(Def, /*TRI=*/nullptr)) I.substituteRegister(Def, SplitReg, 0, *TRI); break; } @@ -1673,7 +1673,8 @@ void PeelingModuloScheduleExpander::moveStageBetweenBlocks( // we don't need the phi anymore. if (getStage(Def) == Stage) { Register PhiReg = MI.getOperand(0).getReg(); - assert(Def->findRegisterDefOperandIdx(MI.getOperand(1).getReg()) != -1); + assert(Def->findRegisterDefOperandIdx(MI.getOperand(1).getReg(), + /*TRI=*/nullptr) != -1); MRI.replaceRegWith(MI.getOperand(0).getReg(), MI.getOperand(1).getReg()); MI.getOperand(0).setReg(PhiReg); PhiToDelete.push_back(&MI); @@ -1899,7 +1900,7 @@ Register PeelingModuloScheduleExpander::getEquivalentRegisterIn(Register Reg, MachineBasicBlock *BB) { MachineInstr *MI = MRI.getUniqueVRegDef(Reg); - unsigned OpIdx = MI->findRegisterDefOperandIdx(Reg); + unsigned OpIdx = MI->findRegisterDefOperandIdx(Reg, /*TRI=*/nullptr); return BlockMIs[{BB, CanonicalMIs[MI]}]->getOperand(OpIdx).getReg(); } diff --git a/llvm/lib/CodeGen/PHIElimination.cpp b/llvm/lib/CodeGen/PHIElimination.cpp index 18f8c001bd789aca4e356df606b0088c5be39019..3254ec0b77fe7889b728621cc1dd306e7238e75f 100644 --- a/llvm/lib/CodeGen/PHIElimination.cpp +++ b/llvm/lib/CodeGen/PHIElimination.cpp @@ -549,7 +549,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator KillInst = opBlock.end(); for (MachineBasicBlock::iterator Term = InsertPos; Term != opBlock.end(); ++Term) { - if (Term->readsRegister(SrcReg)) + if (Term->readsRegister(SrcReg, /*TRI=*/nullptr)) KillInst = Term; } @@ -563,7 +563,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, --KillInst; if (KillInst->isDebugInstr()) continue; - if (KillInst->readsRegister(SrcReg)) + if (KillInst->readsRegister(SrcReg, /*TRI=*/nullptr)) break; } } else { @@ -571,7 +571,8 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, KillInst = NewSrcInstr; } } - assert(KillInst->readsRegister(SrcReg) && "Cannot find kill instruction"); + assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) && + "Cannot find kill instruction"); // Finally, mark it killed. LV->addVirtualRegisterKilled(SrcReg, *KillInst); @@ -607,7 +608,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, MachineBasicBlock::iterator KillInst = opBlock.end(); for (MachineBasicBlock::iterator Term = InsertPos; Term != opBlock.end(); ++Term) { - if (Term->readsRegister(SrcReg)) + if (Term->readsRegister(SrcReg, /*TRI=*/nullptr)) KillInst = Term; } @@ -621,7 +622,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, --KillInst; if (KillInst->isDebugInstr()) continue; - if (KillInst->readsRegister(SrcReg)) + if (KillInst->readsRegister(SrcReg, /*TRI=*/nullptr)) break; } } else { @@ -629,7 +630,7 @@ void PHIElimination::LowerPHINode(MachineBasicBlock &MBB, KillInst = std::prev(InsertPos); } } - assert(KillInst->readsRegister(SrcReg) && + assert(KillInst->readsRegister(SrcReg, /*TRI=*/nullptr) && "Cannot find kill instruction"); SlotIndex LastUseIndex = LIS->getInstructionIndex(*KillInst); diff --git a/llvm/lib/CodeGen/PeepholeOptimizer.cpp b/llvm/lib/CodeGen/PeepholeOptimizer.cpp index 1b1f22e827cb1e2e2f11ee613d7fef53156a53a1..477a86dbe3f8c4c8000ab808d3d284add271797c 100644 --- a/llvm/lib/CodeGen/PeepholeOptimizer.cpp +++ b/llvm/lib/CodeGen/PeepholeOptimizer.cpp @@ -1577,7 +1577,7 @@ bool PeepholeOptimizer::findTargetRecurrence( return false; MachineInstr &MI = *(MRI->use_instr_nodbg_begin(Reg)); - unsigned Idx = MI.findRegisterUseOperandIdx(Reg); + unsigned Idx = MI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr); // Only interested in recurrences whose instructions have only one def, which // is a virtual register. diff --git a/llvm/lib/CodeGen/RegisterCoalescer.cpp b/llvm/lib/CodeGen/RegisterCoalescer.cpp index 7e9c992031f8d3fc061a35d024da8787be6b86cb..3397bd0a6060311daddbfdcca3632fbdad2b0ff5 100644 --- a/llvm/lib/CodeGen/RegisterCoalescer.cpp +++ b/llvm/lib/CodeGen/RegisterCoalescer.cpp @@ -723,7 +723,8 @@ bool RegisterCoalescer::adjustCopiesBackFrom(const CoalescerPair &CP, // If the source instruction was killing the source register before the // merge, unset the isKill marker given the live range has been extended. - int UIdx = ValSEndInst->findRegisterUseOperandIdx(IntB.reg(), true); + int UIdx = + ValSEndInst->findRegisterUseOperandIdx(IntB.reg(), /*TRI=*/nullptr, true); if (UIdx != -1) { ValSEndInst->getOperand(UIdx).setIsKill(false); } @@ -848,7 +849,7 @@ RegisterCoalescer::removeCopyByCommutingDef(const CoalescerPair &CP, return { false, false }; // If DefMI is a two-address instruction then commuting it will change the // destination register. - int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg()); + int DefIdx = DefMI->findRegisterDefOperandIdx(IntA.reg(), /*TRI=*/nullptr); assert(DefIdx != -1); unsigned UseOpIdx; if (!DefMI->isRegTiedToUseOperand(DefIdx, &UseOpIdx)) diff --git a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp index 54409cbf91f1f7a895ccdaafb8edd715f99bfffe..759368a67a16cf3574859f76481c25f0634080c1 100644 --- a/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp @@ -1420,7 +1420,7 @@ EmitSpecialNode(SDNode *Node, bool IsClone, bool IsCloned, for (unsigned Reg : ECRegs) { if (MIB->readsRegister(Reg, TRI)) { MachineOperand *MO = - MIB->findRegisterDefOperand(Reg, false, false, TRI); + MIB->findRegisterDefOperand(Reg, TRI, false, false); assert(MO && "No def operand for clobbered register?"); MO->setIsEarlyClobber(false); } diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 0483f7c74f91a2e36eb0b78c540d534c1e7b60c1..9c855e5585531283d2c613c2fd24a7de806a98c0 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -984,7 +984,7 @@ private: SDValue WidenVecRes_FP_TO_XINT_SAT(SDNode *N); SDValue WidenVecRes_XRINT(SDNode *N); SDValue WidenVecRes_FCOPYSIGN(SDNode *N); - SDValue WidenVecRes_IS_FPCLASS(SDNode *N); + SDValue WidenVecRes_UnarySameEltsWithScalarArg(SDNode *N); SDValue WidenVecRes_ExpOp(SDNode *N); SDValue WidenVecRes_Unary(SDNode *N); SDValue WidenVecRes_InregOp(SDNode *N); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 7a9cfdf5c3fda9e678924ca06bfaa2119e6858e1..1de43a4f60e3a2bb54778e61f0109df0e7656584 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -420,6 +420,7 @@ SDValue VectorLegalizer::LegalizeOp(SDValue Op) { case ISD::FFLOOR: case ISD::FP_ROUND: case ISD::FP_EXTEND: + case ISD::FPTRUNC_ROUND: case ISD::FMA: case ISD::SIGN_EXTEND_INREG: case ISD::ANY_EXTEND_VECTOR_INREG: diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp index 8776d89f4c5bd9dc2f135c024e099f73af3c9557..985c9f16ab97cdf805dfe7b2bed462fd495d12da 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp @@ -4242,7 +4242,8 @@ void DAGTypeLegalizer::WidenVectorResult(SDNode *N, unsigned ResNo) { break; case ISD::IS_FPCLASS: - Res = WidenVecRes_IS_FPCLASS(N); + case ISD::FPTRUNC_ROUND: + Res = WidenVecRes_UnarySameEltsWithScalarArg(N); break; case ISD::FLDEXP: @@ -5004,7 +5005,10 @@ SDValue DAGTypeLegalizer::WidenVecRes_FCOPYSIGN(SDNode *N) { return DAG.UnrollVectorOp(N, WidenVT.getVectorNumElements()); } -SDValue DAGTypeLegalizer::WidenVecRes_IS_FPCLASS(SDNode *N) { +/// Result and first source operand are different scalar types, but must have +/// the same number of elements. There is an additional control argument which +/// should be passed through unchanged. +SDValue DAGTypeLegalizer::WidenVecRes_UnarySameEltsWithScalarArg(SDNode *N) { SDValue FpValue = N->getOperand(0); EVT WidenVT = TLI.getTypeToTransformTo(*DAG.getContext(), N->getValueType(0)); if (getTypeAction(FpValue.getValueType()) != TargetLowering::TypeWidenVector) diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp index 379456e3a9b6c013a8d48a978282095aae7bd72b..f44added89a72838a0bef7110eee034d4da045e2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp @@ -27,6 +27,7 @@ #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/Config/llvm-config.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" @@ -899,6 +900,14 @@ EmitSchedule(MachineBasicBlock::iterator &InsertPos) { if (MDNode *MD = DAG->getPCSections(Node)) MI->setPCSections(MF, MD); + // Set MMRAs on _all_ added instructions. + if (MDNode *MMRA = DAG->getMMRAMetadata(Node)) { + for (MachineBasicBlock::iterator It = MI->getIterator(), + End = std::next(After); + It != End; ++It) + It->setMMRAMetadata(MF, MMRA); + } + return MI; }; diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index b63b8b893fdbf1c98b8815c304a545b2202b37f7..5b7d6376d7d75b5ba9efc6398c0ac7d9a659422d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1418,10 +1418,8 @@ void SelectionDAG::clear() { TargetExternalSymbols.clear(); MCSymbols.clear(); SDEI.clear(); - std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), - static_cast(nullptr)); - std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), - static_cast(nullptr)); + std::fill(CondCodeNodes.begin(), CondCodeNodes.end(), nullptr); + std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(), nullptr); EntryNode.UseList = nullptr; InsertNode(&EntryNode); @@ -1703,8 +1701,9 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL, assert(Elt->getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"); unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant; + SDVTList VTs = getVTList(EltVT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(EltVT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddPointer(Elt); ID.AddBoolean(isO); void *IP = nullptr; @@ -1714,7 +1713,7 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, const SDLoc &DL, return SDValue(N, 0); if (!N) { - N = newSDNode(isT, isO, Elt, EltVT); + N = newSDNode(isT, isO, Elt, VTs); CSEMap.InsertNode(N, IP); InsertNode(N); NewSDValueDbgMsg(SDValue(N, 0), "Creating constant: ", this); @@ -1764,8 +1763,9 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP &V, const SDLoc &DL, // value, so that we don't have problems with 0.0 comparing equal to -0.0, and // we don't have issues with SNANs. unsigned Opc = isTarget ? ISD::TargetConstantFP : ISD::ConstantFP; + SDVTList VTs = getVTList(EltVT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(EltVT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddPointer(&V); void *IP = nullptr; SDNode *N = nullptr; @@ -1774,7 +1774,7 @@ SDValue SelectionDAG::getConstantFP(const ConstantFP &V, const SDLoc &DL, return SDValue(N, 0); if (!N) { - N = newSDNode(isTarget, &V, EltVT); + N = newSDNode(isTarget, &V, VTs); CSEMap.InsertNode(N, IP); InsertNode(N); } @@ -1821,8 +1821,9 @@ SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, else Opc = isTargetGA ? ISD::TargetGlobalAddress : ISD::GlobalAddress; + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddPointer(GV); ID.AddInteger(Offset); ID.AddInteger(TargetFlags); @@ -1831,7 +1832,7 @@ SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, return SDValue(E, 0); auto *N = newSDNode( - Opc, DL.getIROrder(), DL.getDebugLoc(), GV, VT, Offset, TargetFlags); + Opc, DL.getIROrder(), DL.getDebugLoc(), GV, VTs, Offset, TargetFlags); CSEMap.InsertNode(N, IP); InsertNode(N); return SDValue(N, 0); @@ -1839,14 +1840,15 @@ SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, SDValue SelectionDAG::getFrameIndex(int FI, EVT VT, bool isTarget) { unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex; + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddInteger(FI); void *IP = nullptr; if (SDNode *E = FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); - auto *N = newSDNode(FI, VT, isTarget); + auto *N = newSDNode(FI, VTs, isTarget); CSEMap.InsertNode(N, IP); InsertNode(N); return SDValue(N, 0); @@ -1857,15 +1859,16 @@ SDValue SelectionDAG::getJumpTable(int JTI, EVT VT, bool isTarget, assert((TargetFlags == 0 || isTarget) && "Cannot set target flags on target-independent jump tables"); unsigned Opc = isTarget ? ISD::TargetJumpTable : ISD::JumpTable; + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddInteger(JTI); ID.AddInteger(TargetFlags); void *IP = nullptr; if (SDNode *E = FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); - auto *N = newSDNode(JTI, VT, isTarget, TargetFlags); + auto *N = newSDNode(JTI, VTs, isTarget, TargetFlags); CSEMap.InsertNode(N, IP); InsertNode(N); return SDValue(N, 0); @@ -1888,8 +1891,9 @@ SDValue SelectionDAG::getConstantPool(const Constant *C, EVT VT, ? getDataLayout().getABITypeAlign(C->getType()) : getDataLayout().getPrefTypeAlign(C->getType()); unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddInteger(Alignment->value()); ID.AddInteger(Offset); ID.AddPointer(C); @@ -1898,7 +1902,7 @@ SDValue SelectionDAG::getConstantPool(const Constant *C, EVT VT, if (SDNode *E = FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); - auto *N = newSDNode(isTarget, C, VT, Offset, *Alignment, + auto *N = newSDNode(isTarget, C, VTs, Offset, *Alignment, TargetFlags); CSEMap.InsertNode(N, IP); InsertNode(N); @@ -1915,8 +1919,9 @@ SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT, if (!Alignment) Alignment = getDataLayout().getPrefTypeAlign(C->getType()); unsigned Opc = isTarget ? ISD::TargetConstantPool : ISD::ConstantPool; + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddInteger(Alignment->value()); ID.AddInteger(Offset); C->addSelectionDAGCSEId(ID); @@ -1925,7 +1930,7 @@ SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT, if (SDNode *E = FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); - auto *N = newSDNode(isTarget, C, VT, Offset, *Alignment, + auto *N = newSDNode(isTarget, C, VTs, Offset, *Alignment, TargetFlags); CSEMap.InsertNode(N, IP); InsertNode(N); @@ -1963,7 +1968,7 @@ SDValue SelectionDAG::getValueType(EVT VT) { SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) { SDNode *&N = ExternalSymbols[Sym]; if (N) return SDValue(N, 0); - N = newSDNode(false, Sym, 0, VT); + N = newSDNode(false, Sym, 0, getVTList(VT)); InsertNode(N); return SDValue(N, 0); } @@ -1972,7 +1977,7 @@ SDValue SelectionDAG::getMCSymbol(MCSymbol *Sym, EVT VT) { SDNode *&N = MCSymbols[Sym]; if (N) return SDValue(N, 0); - N = newSDNode(Sym, VT); + N = newSDNode(Sym, getVTList(VT)); InsertNode(N); return SDValue(N, 0); } @@ -1982,7 +1987,7 @@ SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT, SDNode *&N = TargetExternalSymbols[std::pair(Sym, TargetFlags)]; if (N) return SDValue(N, 0); - N = newSDNode(true, Sym, TargetFlags, VT); + N = newSDNode(true, Sym, TargetFlags, getVTList(VT)); InsertNode(N); return SDValue(N, 0); } @@ -2198,9 +2203,10 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, } } + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; SDValue Ops[2] = { N1, N2 }; - AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, getVTList(VT), Ops); + AddNodeIDNode(ID, ISD::VECTOR_SHUFFLE, VTs, Ops); for (int i = 0; i != NElts; ++i) ID.AddInteger(MaskVec[i]); @@ -2214,7 +2220,7 @@ SDValue SelectionDAG::getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, int *MaskAlloc = OperandAllocator.Allocate(NElts); llvm::copy(MaskVec, MaskAlloc); - auto *N = newSDNode(VT, dl.getIROrder(), + auto *N = newSDNode(VTs, dl.getIROrder(), dl.getDebugLoc(), MaskAlloc); createOperands(N, Ops); @@ -2236,14 +2242,15 @@ SDValue SelectionDAG::getCommutedVectorShuffle(const ShuffleVectorSDNode &SV) { } SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) { + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::Register, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, ISD::Register, VTs, std::nullopt); ID.AddInteger(RegNo); void *IP = nullptr; if (SDNode *E = FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); - auto *N = newSDNode(RegNo, VT); + auto *N = newSDNode(RegNo, VTs); N->SDNodeBits.IsDivergent = TLI->isSDNodeSourceOfDivergence(N, FLI, UA); CSEMap.InsertNode(N, IP); InsertNode(N); @@ -2292,9 +2299,10 @@ SDValue SelectionDAG::getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset, bool isTarget, unsigned TargetFlags) { unsigned Opc = isTarget ? ISD::TargetBlockAddress : ISD::BlockAddress; + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opc, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opc, VTs, std::nullopt); ID.AddPointer(BA); ID.AddInteger(Offset); ID.AddInteger(TargetFlags); @@ -2302,7 +2310,7 @@ SDValue SelectionDAG::getBlockAddress(const BlockAddress *BA, EVT VT, if (SDNode *E = FindNodeOrInsertPos(ID, IP)) return SDValue(E, 0); - auto *N = newSDNode(Opc, VT, BA, Offset, TargetFlags); + auto *N = newSDNode(Opc, VTs, BA, Offset, TargetFlags); CSEMap.InsertNode(N, IP); InsertNode(N); return SDValue(N, 0); @@ -2347,9 +2355,10 @@ SDValue SelectionDAG::getBitcast(EVT VT, SDValue V) { SDValue SelectionDAG::getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS) { + SDVTList VTs = getVTList(VT); SDValue Ops[] = {Ptr}; FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::ADDRSPACECAST, getVTList(VT), Ops); + AddNodeIDNode(ID, ISD::ADDRSPACECAST, VTs, Ops); ID.AddInteger(SrcAS); ID.AddInteger(DestAS); @@ -2358,7 +2367,7 @@ SDValue SelectionDAG::getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, return SDValue(E, 0); auto *N = newSDNode(dl.getIROrder(), dl.getDebugLoc(), - VT, SrcAS, DestAS); + VTs, SrcAS, DestAS); createOperands(N, Ops); CSEMap.InsertNode(N, IP); @@ -2995,6 +3004,14 @@ SelectionDAG::getValidShiftAmountConstant(SDValue V, return nullptr; } +const APInt *SelectionDAG::getValidShiftAmountConstant(SDValue V) const { + EVT VT = V.getValueType(); + APInt DemandedElts = VT.isFixedLengthVector() + ? APInt::getAllOnes(VT.getVectorNumElements()) + : APInt(1, 1); + return getValidShiftAmountConstant(V, DemandedElts); +} + const APInt *SelectionDAG::getValidMinimumShiftAmountConstant( SDValue V, const APInt &DemandedElts) const { assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL || @@ -3024,6 +3041,14 @@ const APInt *SelectionDAG::getValidMinimumShiftAmountConstant( return MinShAmt; } +const APInt *SelectionDAG::getValidMinimumShiftAmountConstant(SDValue V) const { + EVT VT = V.getValueType(); + APInt DemandedElts = VT.isFixedLengthVector() + ? APInt::getAllOnes(VT.getVectorNumElements()) + : APInt(1, 1); + return getValidMinimumShiftAmountConstant(V, DemandedElts); +} + const APInt *SelectionDAG::getValidMaximumShiftAmountConstant( SDValue V, const APInt &DemandedElts) const { assert((V.getOpcode() == ISD::SHL || V.getOpcode() == ISD::SRL || @@ -3053,6 +3078,14 @@ const APInt *SelectionDAG::getValidMaximumShiftAmountConstant( return MaxShAmt; } +const APInt *SelectionDAG::getValidMaximumShiftAmountConstant(SDValue V) const { + EVT VT = V.getValueType(); + APInt DemandedElts = VT.isFixedLengthVector() + ? APInt::getAllOnes(VT.getVectorNumElements()) + : APInt(1, 1); + return getValidMaximumShiftAmountConstant(V, DemandedElts); +} + /// Determine which bits of Op are known to be either zero or one and return /// them in Known. For vectors, the known bits are those that are shared by /// every vector element. @@ -5691,14 +5724,14 @@ static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, /// Gets or creates the specified node. SDValue SelectionDAG::getNode(unsigned Opcode, const SDLoc &DL, EVT VT) { + SDVTList VTs = getVTList(VT); FoldingSetNodeID ID; - AddNodeIDNode(ID, Opcode, getVTList(VT), std::nullopt); + AddNodeIDNode(ID, Opcode, VTs, std::nullopt); void *IP = nullptr; if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) return SDValue(E, 0); - auto *N = newSDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), - getVTList(VT)); + auto *N = newSDNode(Opcode, DL.getIROrder(), DL.getDebugLoc(), VTs); CSEMap.InsertNode(N, IP); InsertNode(N); @@ -6645,16 +6678,17 @@ SDValue SelectionDAG::getAssertAlign(const SDLoc &DL, SDValue Val, Align A) { if (A == Align(1)) return Val; + SDVTList VTs = getVTList(Val.getValueType()); FoldingSetNodeID ID; - AddNodeIDNode(ID, ISD::AssertAlign, getVTList(Val.getValueType()), {Val}); + AddNodeIDNode(ID, ISD::AssertAlign, VTs, {Val}); ID.AddInteger(A.value()); void *IP = nullptr; if (SDNode *E = FindNodeOrInsertPos(ID, DL, IP)) return SDValue(E, 0); - auto *N = newSDNode(DL.getIROrder(), DL.getDebugLoc(), - Val.getValueType(), A); + auto *N = + newSDNode(DL.getIROrder(), DL.getDebugLoc(), VTs, A); createOperands(N, {Val}); CSEMap.InsertNode(N, IP); @@ -11773,20 +11807,6 @@ HandleSDNode::~HandleSDNode() { DropOperands(); } -GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, unsigned Order, - const DebugLoc &DL, - const GlobalValue *GA, EVT VT, - int64_t o, unsigned TF) - : SDNode(Opc, Order, DL, getSDVTList(VT)), Offset(o), TargetFlags(TF) { - TheGlobal = GA; -} - -AddrSpaceCastSDNode::AddrSpaceCastSDNode(unsigned Order, const DebugLoc &dl, - EVT VT, unsigned SrcAS, - unsigned DestAS) - : SDNode(ISD::ADDRSPACECAST, Order, dl, getSDVTList(VT)), - SrcAddrSpace(SrcAS), DestAddrSpace(DestAS) {} - MemSDNode::MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, MachineMemOperand *mmo) : SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) { @@ -12946,7 +12966,7 @@ void SelectionDAG::copyExtraInfo(SDNode *From, SDNode *To) { // Use of operator[] on the DenseMap may cause an insertion, which invalidates // the iterator, hence the need to make a copy to prevent a use-after-free. NodeExtraInfo NEI = I->second; - if (LLVM_LIKELY(!NEI.PCSections)) { + if (LLVM_LIKELY(!NEI.PCSections) && LLVM_LIKELY(!NEI.MMRA)) { // No deep copy required for the types of extra info set. // // FIXME: Investigate if other types of extra info also need deep copy. This diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 319465865fb1d18c11ac437d71a36771afd6cf66..0db484a5e06bcdcc254c94756c31131beefa9398 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -80,6 +80,7 @@ #include "llvm/IR/IntrinsicsAMDGPU.h" #include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/LLVMContext.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" #include "llvm/IR/Operator.h" @@ -1326,7 +1327,8 @@ void SelectionDAGBuilder::visit(const Instruction &I) { bool NodeInserted = false; std::unique_ptr InsertedListener; MDNode *PCSectionsMD = I.getMetadata(LLVMContext::MD_pcsections); - if (PCSectionsMD) { + MDNode *MMRA = I.getMetadata(LLVMContext::MD_mmra); + if (PCSectionsMD || MMRA) { InsertedListener = std::make_unique( DAG, [&](SDNode *) { NodeInserted = true; }); } @@ -1338,14 +1340,17 @@ void SelectionDAGBuilder::visit(const Instruction &I) { CopyToExportRegsIfNeeded(&I); // Handle metadata. - if (PCSectionsMD) { + if (PCSectionsMD || MMRA) { auto It = NodeMap.find(&I); if (It != NodeMap.end()) { - DAG.addPCSections(It->second.getNode(), PCSectionsMD); + if (PCSectionsMD) + DAG.addPCSections(It->second.getNode(), PCSectionsMD); + if (MMRA) + DAG.addMMRAMetadata(It->second.getNode(), MMRA); } else if (NodeInserted) { // This should not happen; if it does, don't let it go unnoticed so we can // fix it. Relevant visit*() function is probably missing a setValue(). - errs() << "warning: loosing !pcsections metadata [" + errs() << "warning: loosing !pcsections and/or !mmra metadata [" << I.getModule()->getName() << "]\n"; LLVM_DEBUG(I.dump()); assert(false); @@ -5294,9 +5299,9 @@ void SelectionDAGBuilder::visitTargetIntrinsic(const CallInst &I, Result = DAG.getAssertAlign(getCurSDLoc(), Result, Alignment.valueOrOne()); } - - setValue(&I, Result); } + + setValue(&I, Result); } /// GetSignificand - Get the significand and build it into a floating-point diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp index 6691aa41face39aa6c0c24fa4c392dfedb3b2a20..4ad4a938ca97f2f3c37cf18f6a3e0e3124181a9d 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGDumper.cpp @@ -299,6 +299,7 @@ std::string SDNode::getOperationName(const SelectionDAG *G) const { case ISD::SETCCCARRY: return "setcccarry"; case ISD::STRICT_FSETCC: return "strict_fsetcc"; case ISD::STRICT_FSETCCS: return "strict_fsetccs"; + case ISD::FPTRUNC_ROUND: return "fptrunc_round"; case ISD::SELECT: return "select"; case ISD::VSELECT: return "vselect"; case ISD::SELECT_CC: return "select_cc"; @@ -905,6 +906,13 @@ void SDNode::print_details(raw_ostream &OS, const SelectionDAG *G) const { MD->printAsOperand(OS, G->getMachineFunction().getFunction().getParent()); OS << ']'; } + + if (MDNode *MMRA = G ? G->getMMRAMetadata(this) : nullptr) { + OS << " [mmra "; + MMRA->printAsOperand(OS, + G->getMachineFunction().getFunction().getParent()); + OS << ']'; + } } } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp index d629c36bc792e32835718304e495ed1b1ad07920..b5694c955b8c8fbf730efde8111537c4145637b7 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp @@ -1059,6 +1059,8 @@ public: SDNode *CurNode = &*ISelPosition; if (MDNode *MD = DAG.getPCSections(CurNode)) DAG.addPCSections(N, MD); + if (MDNode *MMRA = DAG.getMMRAMetadata(CurNode)) + DAG.addMMRAMetadata(N, MMRA); } }; diff --git a/llvm/lib/CodeGen/StackSlotColoring.cpp b/llvm/lib/CodeGen/StackSlotColoring.cpp index 6d3fc740b292a8c26f27a6aafaabdd1e5332029c..9fdc8a338b52a5d2c08a54ede68f17090ae89506 100644 --- a/llvm/lib/CodeGen/StackSlotColoring.cpp +++ b/llvm/lib/CodeGen/StackSlotColoring.cpp @@ -486,7 +486,8 @@ bool StackSlotColoring::RemoveDeadStores(MachineBasicBlock* MBB) { ++NumDead; changed = true; - if (NextMI->findRegisterUseOperandIdx(LoadReg, true, nullptr) != -1) { + if (NextMI->findRegisterUseOperandIdx(LoadReg, /*TRI=*/nullptr, true) != + -1) { ++NumDead; toErase.push_back(&*ProbableLoadMI); } diff --git a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp index ebacbc420f8580a8189a083fc8fcdb206f154075..b9b2841e7c9ee40a54b5b902014a0a6c9694c8a1 100644 --- a/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp +++ b/llvm/lib/CodeGen/TwoAddressInstructionPass.cpp @@ -339,7 +339,7 @@ bool TwoAddressInstructionPass::isPlainlyKilled(const MachineInstr *MI, }); } - return MI->killsRegister(Reg); + return MI->killsRegister(Reg, /*TRI=*/nullptr); } /// Test if the register used by the given operand is killed by the operand's @@ -1355,8 +1355,10 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, << "2addr: NEW INST: " << *NewMIs[1]); // Transform the instruction, now that it no longer has a load. - unsigned NewDstIdx = NewMIs[1]->findRegisterDefOperandIdx(regA); - unsigned NewSrcIdx = NewMIs[1]->findRegisterUseOperandIdx(regB); + unsigned NewDstIdx = + NewMIs[1]->findRegisterDefOperandIdx(regA, /*TRI=*/nullptr); + unsigned NewSrcIdx = + NewMIs[1]->findRegisterUseOperandIdx(regB, /*TRI=*/nullptr); MachineBasicBlock::iterator NewMI = NewMIs[1]; bool TransformResult = tryInstructionTransform(NewMI, mi, NewSrcIdx, NewDstIdx, Dist, true); @@ -1371,19 +1373,22 @@ tryInstructionTransform(MachineBasicBlock::iterator &mi, if (MO.isReg() && MO.getReg().isVirtual()) { if (MO.isUse()) { if (MO.isKill()) { - if (NewMIs[0]->killsRegister(MO.getReg())) + if (NewMIs[0]->killsRegister(MO.getReg(), /*TRI=*/nullptr)) LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[0]); else { - assert(NewMIs[1]->killsRegister(MO.getReg()) && + assert(NewMIs[1]->killsRegister(MO.getReg(), + /*TRI=*/nullptr) && "Kill missing after load unfold!"); LV->replaceKillInstruction(MO.getReg(), MI, *NewMIs[1]); } } } else if (LV->removeVirtualRegisterDead(MO.getReg(), MI)) { - if (NewMIs[1]->registerDefIsDead(MO.getReg())) + if (NewMIs[1]->registerDefIsDead(MO.getReg(), + /*TRI=*/nullptr)) LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[1]); else { - assert(NewMIs[0]->registerDefIsDead(MO.getReg()) && + assert(NewMIs[0]->registerDefIsDead(MO.getReg(), + /*TRI=*/nullptr) && "Dead flag missing after load unfold!"); LV->addVirtualRegisterDead(MO.getReg(), *NewMIs[0]); } diff --git a/llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp b/llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp index efafca949e61efbccad4685bd45bc3f105d0fa4c..0df7c4f25eb82c7cca9a6ca3cd8bdab09925fe2d 100644 --- a/llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp +++ b/llvm/lib/ExecutionEngine/Orc/ExecutorProcessControl.cpp @@ -61,13 +61,8 @@ SelfExecutorProcessControl::Create( if (!SSP) SSP = std::make_shared(); - if (!D) { -#if LLVM_ENABLE_THREADS - D = std::make_unique(); -#else + if (!D) D = std::make_unique(); -#endif - } auto PageSize = sys::Process::getPageSize(); if (!PageSize) diff --git a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp index 79adda5b7bc0341b6cdd5458e3b42457c57c257b..568b2ececaa09a6648ab879bc4da4e4ca17f7710 100644 --- a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp +++ b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp @@ -667,6 +667,40 @@ Error LLJITBuilderState::prepareForConstruction() { return JTMBOrErr.takeError(); } + if ((ES || EPC) && NumCompileThreads) + return make_error( + "NumCompileThreads cannot be used with a custom ExecutionSession or " + "ExecutorProcessControl", + inconvertibleErrorCode()); + +#if !LLVM_ENABLE_THREADS + if (NumCompileThreads) + return make_error( + "LLJIT num-compile-threads is " + Twine(NumCompileThreads) + + " but LLVM was compiled with LLVM_ENABLE_THREADS=Off", + inconvertibleErrorCode()); +#endif // !LLVM_ENABLE_THREADS + + // Only used in debug builds. + [[maybe_unused]] bool ConcurrentCompilationSettingDefaulted = + !SupportConcurrentCompilation; + + if (!SupportConcurrentCompilation) { +#if LLVM_ENABLE_THREADS + SupportConcurrentCompilation = NumCompileThreads || ES || EPC; +#else + SupportConcurrentCompilation = false; +#endif // LLVM_ENABLE_THREADS + } else { +#if !LLVM_ENABLE_THREADS + if (*SupportConcurrentCompilation) + return make_error( + "LLJIT concurrent compilation support requested, but LLVM was built " + "with LLVM_ENABLE_THREADS=Off", + inconvertibleErrorCode()); +#endif // !LLVM_ENABLE_THREADS + } + LLVM_DEBUG({ dbgs() << " JITTargetMachineBuilder is " << JITTargetMachineBuilderPrinter(*JTMB, " ") @@ -684,11 +718,13 @@ Error LLJITBuilderState::prepareForConstruction() { << (CreateCompileFunction ? "Yes" : "No") << "\n" << " Custom platform-setup function: " << (SetUpPlatform ? "Yes" : "No") << "\n" - << " Number of compile threads: " << NumCompileThreads; - if (!NumCompileThreads) - dbgs() << " (code will be compiled on the execution thread)\n"; + << " Support concurrent compilation: " + << (*SupportConcurrentCompilation ? "Yes" : "No"); + if (ConcurrentCompilationSettingDefaulted) + dbgs() << " (defaulted based on ES / EPC / NumCompileThreads)\n"; else dbgs() << "\n"; + dbgs() << " Number of compile threads: " << NumCompileThreads << "\n"; }); // Create DL if not specified. @@ -705,7 +741,19 @@ Error LLJITBuilderState::prepareForConstruction() { dbgs() << "ExecutorProcessControl not specified, " "Creating SelfExecutorProcessControl instance\n"; }); - if (auto EPCOrErr = SelfExecutorProcessControl::Create()) + + std::unique_ptr D = nullptr; +#if LLVM_ENABLE_THREADS + if (*SupportConcurrentCompilation) { + std::optional NumThreads = std ::nullopt; + if (NumCompileThreads) + NumThreads = NumCompileThreads; + D = std::make_unique(NumThreads); + } else + D = std::make_unique(); +#endif // LLVM_ENABLE_THREADS + if (auto EPCOrErr = + SelfExecutorProcessControl::Create(nullptr, std::move(D), nullptr)) EPC = std::move(*EPCOrErr); else return EPCOrErr.takeError(); @@ -790,8 +838,6 @@ Error LLJITBuilderState::prepareForConstruction() { } LLJIT::~LLJIT() { - if (CompileThreads) - CompileThreads->wait(); if (auto Err = ES->endSession()) ES->reportError(std::move(Err)); } @@ -916,9 +962,8 @@ LLJIT::createCompileFunction(LLJITBuilderState &S, if (S.CreateCompileFunction) return S.CreateCompileFunction(std::move(JTMB)); - // Otherwise default to creating a SimpleCompiler, or ConcurrentIRCompiler, - // depending on the number of threads requested. - if (S.NumCompileThreads > 0) + // If using a custom EPC then use a ConcurrentIRCompiler by default. + if (*S.SupportConcurrentCompilation) return std::make_unique(std::move(JTMB)); auto TM = JTMB.createTargetMachine(); @@ -970,21 +1015,8 @@ LLJIT::LLJIT(LLJITBuilderState &S, Error &Err) std::make_unique(*ES, *TransformLayer); } - if (S.NumCompileThreads > 0) { + if (*S.SupportConcurrentCompilation) InitHelperTransformLayer->setCloneToNewContextOnEmit(true); - CompileThreads = std::make_unique( - hardware_concurrency(S.NumCompileThreads)); - ES->setDispatchTask([this](std::unique_ptr T) { - // FIXME: We should be able to use move-capture here, but ThreadPool's - // AsyncTaskTys are std::functions rather than unique_functions - // (because MSVC's std::packaged_tasks don't support move-only types). - // Fix this when all the above gets sorted out. - CompileThreads->async([UnownedT = T.release()]() mutable { - std::unique_ptr T(UnownedT); - T->run(); - }); - }); - } if (S.SetupProcessSymbolsJITDylib) { if (auto ProcSymsJD = S.SetupProcessSymbolsJITDylib(*this)) { @@ -1240,7 +1272,7 @@ LLLazyJIT::LLLazyJIT(LLLazyJITBuilderState &S, Error &Err) : LLJIT(S, Err) { CODLayer = std::make_unique( *ES, *InitHelperTransformLayer, *LCTMgr, std::move(ISMBuilder)); - if (S.NumCompileThreads > 0) + if (*S.SupportConcurrentCompilation) CODLayer->setCloneToNewContextOnEmit(true); } diff --git a/llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp b/llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp index 11a99986f2ee92e0bb35f6cf663d4bf28b034126..4ac2a42091858e6ca4a85e4a3698e82d91683315 100644 --- a/llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp +++ b/llvm/lib/ExecutionEngine/Orc/TaskDispatch.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/ExecutionEngine/Orc/TaskDispatch.h" +#include "llvm/ExecutionEngine/Orc/Core.h" namespace llvm { namespace orc { @@ -24,16 +25,52 @@ void InPlaceTaskDispatcher::shutdown() {} #if LLVM_ENABLE_THREADS void DynamicThreadPoolTaskDispatcher::dispatch(std::unique_ptr T) { + bool IsMaterializationTask = isa(*T); + { std::lock_guard Lock(DispatchMutex); + + if (IsMaterializationTask) { + + // If this is a materialization task and there are too many running + // already then queue this one up and return early. + if (MaxMaterializationThreads && + NumMaterializationThreads == *MaxMaterializationThreads) { + MaterializationTaskQueue.push_back(std::move(T)); + return; + } + + // Otherwise record that we have a materialization task running. + ++NumMaterializationThreads; + } + ++Outstanding; } - std::thread([this, T = std::move(T)]() mutable { - T->run(); - std::lock_guard Lock(DispatchMutex); - --Outstanding; - OutstandingCV.notify_all(); + std::thread([this, T = std::move(T), IsMaterializationTask]() mutable { + while (true) { + + // Run the task. + T->run(); + + std::lock_guard Lock(DispatchMutex); + if (!MaterializationTaskQueue.empty()) { + // If there are any materialization tasks running then steal that work. + T = std::move(MaterializationTaskQueue.front()); + MaterializationTaskQueue.pop_front(); + if (!IsMaterializationTask) { + ++NumMaterializationThreads; + IsMaterializationTask = true; + } + } else { + // Otherwise decrement work counters. + if (IsMaterializationTask) + --NumMaterializationThreads; + --Outstanding; + OutstandingCV.notify_all(); + return; + } + } }).detach(); } diff --git a/llvm/lib/Frontend/OpenMP/OMP.cpp b/llvm/lib/Frontend/OpenMP/OMP.cpp index 1ffc38b63b0a52a518aae98837d4c03acc9a55d2..c1556ff3c74d72c2e9731dd6281a32697b03e161 100644 --- a/llvm/lib/Frontend/OpenMP/OMP.cpp +++ b/llvm/lib/Frontend/OpenMP/OMP.cpp @@ -25,6 +25,54 @@ using namespace llvm::omp; #define GEN_DIRECTIVES_IMPL #include "llvm/Frontend/OpenMP/OMP.inc" +static iterator_range::iterator> +getFirstCompositeRange(iterator_range::iterator> Leafs) { + // OpenMP Spec 5.2: [17.3, 8-9] + // If directive-name-A and directive-name-B both correspond to loop- + // associated constructs then directive-name is a composite construct + // otherwise directive-name is a combined construct. + // + // In the list of leaf constructs, find the first loop-associated construct, + // this is the beginning of the returned range. Then, starting from the + // immediately following leaf construct, find the first sequence of adjacent + // loop-associated constructs. The last of those is the last one of the + // range, that is, the end of the range is one past that element. + // If such a sequence of adjacent loop-associated directives does not exist, + // return an empty range. + // + // The end of the returned range (including empty range) is intended to be + // a point from which the search for the next range could resume. + // + // Consequently, this function can't return a range with a single leaf + // construct in it. + + auto firstLoopAssociated = + [](iterator_range::iterator> List) { + for (auto It = List.begin(), End = List.end(); It != End; ++It) { + if (getDirectiveAssociation(*It) == Association::Loop) + return It; + } + return List.end(); + }; + + auto Empty = llvm::make_range(Leafs.end(), Leafs.end()); + + auto Begin = firstLoopAssociated(Leafs); + if (Begin == Leafs.end()) + return Empty; + + auto End = + firstLoopAssociated(llvm::make_range(std::next(Begin), Leafs.end())); + if (End == Leafs.end()) + return Empty; + + for (; End != Leafs.end(); ++End) { + if (getDirectiveAssociation(*End) != Association::Loop) + break; + } + return llvm::make_range(Begin, End); +} + namespace llvm::omp { ArrayRef getLeafConstructs(Directive D) { auto Idx = static_cast(D); @@ -34,6 +82,44 @@ ArrayRef getLeafConstructs(Directive D) { return ArrayRef(&Row[2], static_cast(Row[1])); } +ArrayRef getLeafConstructsOrSelf(Directive D) { + if (auto Leafs = getLeafConstructs(D); !Leafs.empty()) + return Leafs; + auto Idx = static_cast(D); + assert(Idx < Directive_enumSize && "Invalid directive"); + const auto *Row = LeafConstructTable[LeafConstructTableOrdering[Idx]]; + // The first entry in the row is the directive itself. + return ArrayRef(&Row[0], &Row[0] + 1); +} + +ArrayRef +getLeafOrCompositeConstructs(Directive D, SmallVectorImpl &Output) { + using ArrayTy = ArrayRef; + using IteratorTy = ArrayTy::iterator; + ArrayRef Leafs = getLeafConstructsOrSelf(D); + + IteratorTy Iter = Leafs.begin(); + do { + auto Range = getFirstCompositeRange(llvm::make_range(Iter, Leafs.end())); + // All directives before the range are leaf constructs. + for (; Iter != Range.begin(); ++Iter) + Output.push_back(*Iter); + if (!Range.empty()) { + Directive Comp = + getCompoundConstruct(ArrayTy(Range.begin(), Range.end())); + assert(Comp != OMPD_unknown); + Output.push_back(Comp); + Iter = Range.end(); + // As of now, a composite construct must contain all constituent leaf + // constructs from some point until the end of all constituent leaf + // constructs. + assert(Iter == Leafs.end() && "Malformed directive"); + } + } while (Iter != Leafs.end()); + + return Output; +} + Directive getCompoundConstruct(ArrayRef Parts) { if (Parts.empty()) return OMPD_unknown; @@ -88,20 +174,11 @@ Directive getCompoundConstruct(ArrayRef Parts) { bool isLeafConstruct(Directive D) { return getLeafConstructs(D).empty(); } bool isCompositeConstruct(Directive D) { - // OpenMP Spec 5.2: [17.3, 8-9] - // If directive-name-A and directive-name-B both correspond to loop- - // associated constructs then directive-name is a composite construct - llvm::ArrayRef Leafs{getLeafConstructs(D)}; - if (Leafs.empty()) - return false; - if (getDirectiveAssociation(Leafs.front()) != Association::Loop) + ArrayRef Leafs = getLeafConstructsOrSelf(D); + if (Leafs.size() <= 1) return false; - - size_t numLoopConstructs = - llvm::count_if(Leafs.drop_front(), [](Directive L) { - return getDirectiveAssociation(L) == Association::Loop; - }); - return numLoopConstructs != 0; + auto Range = getFirstCompositeRange(Leafs); + return Range.begin() == Leafs.begin() && Range.end() == Leafs.end(); } bool isCombinedConstruct(Directive D) { diff --git a/llvm/lib/IR/Attributes.cpp b/llvm/lib/IR/Attributes.cpp index b2d9992cdc025812c5de8161f8a92abe5224f436..9c48a481de1ff69b84686f47d9c6baed726437dd 100644 --- a/llvm/lib/IR/Attributes.cpp +++ b/llvm/lib/IR/Attributes.cpp @@ -1530,6 +1530,13 @@ AttributeList::addDereferenceableOrNullParamAttr(LLVMContext &C, unsigned Index, return addParamAttributes(C, Index, B); } +AttributeList AttributeList::addRangeRetAttr(LLVMContext &C, + const ConstantRange &CR) const { + AttrBuilder B(C); + B.addRangeAttr(CR); + return addRetAttributes(C, B); +} + AttributeList AttributeList::addAllocSizeParamAttr( LLVMContext &C, unsigned Index, unsigned ElemSizeArg, const std::optional &NumElemsArg) { diff --git a/llvm/lib/IR/CMakeLists.txt b/llvm/lib/IR/CMakeLists.txt index f1668ee3be63b5d4ff3f2fc50bd553cf161a6ad7..b5fb7409d8e88e0b676750e48bcb05b2c58a2894 100644 --- a/llvm/lib/IR/CMakeLists.txt +++ b/llvm/lib/IR/CMakeLists.txt @@ -41,6 +41,7 @@ add_llvm_component_library(LLVMCore LLVMRemarkStreamer.cpp LegacyPassManager.cpp MDBuilder.cpp + MemoryModelRelaxationAnnotations.cpp Mangler.cpp Metadata.cpp Module.cpp diff --git a/llvm/lib/IR/Instruction.cpp b/llvm/lib/IR/Instruction.cpp index eb1c5f445eb8b5e8ca55bd2df9cb7e733892ea48..678edc58ad848dfe15367acf72c31b955b1e1f5f 100644 --- a/llvm/lib/IR/Instruction.cpp +++ b/llvm/lib/IR/Instruction.cpp @@ -19,6 +19,7 @@ #include "llvm/IR/Instructions.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Intrinsics.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/Operator.h" #include "llvm/IR/ProfDataUtils.h" #include "llvm/IR/Type.h" diff --git a/llvm/lib/IR/MemoryModelRelaxationAnnotations.cpp b/llvm/lib/IR/MemoryModelRelaxationAnnotations.cpp new file mode 100644 index 0000000000000000000000000000000000000000..19f438d890aee843b4ee64851f69158969017395 --- /dev/null +++ b/llvm/lib/IR/MemoryModelRelaxationAnnotations.cpp @@ -0,0 +1,170 @@ +//===- MemoryModelRelaxationAnnotations.cpp ---------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" +#include "llvm/ADT/StringSet.h" +#include "llvm/IR/Instructions.h" +#include "llvm/IR/Metadata.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" + +using namespace llvm; + +//===- MMRAMetadata -------------------------------------------------------===// + +MMRAMetadata::MMRAMetadata(const Instruction &I) + : MMRAMetadata(I.getMetadata(LLVMContext::MD_mmra)) {} + +MMRAMetadata::MMRAMetadata(MDNode *MD) { + if (!MD) + return; + + // TODO: Split this into a "tryParse" function that can return an err. + // CTor can use the tryParse & just fatal on err. + + MDTuple *Tuple = dyn_cast(MD); + assert(Tuple && "Invalid MMRA structure"); + + const auto HandleTagMD = [this](MDNode *TagMD) { + Tags.insert({cast(TagMD->getOperand(0))->getString(), + cast(TagMD->getOperand(1))->getString()}); + }; + + if (isTagMD(Tuple)) { + HandleTagMD(Tuple); + return; + } + + for (const MDOperand &Op : Tuple->operands()) { + MDNode *MDOp = cast(Op.get()); + assert(isTagMD(MDOp)); + HandleTagMD(MDOp); + } +} + +bool MMRAMetadata::isTagMD(const Metadata *MD) { + if (auto *Tuple = dyn_cast(MD)) { + return Tuple->getNumOperands() == 2 && + isa(Tuple->getOperand(0)) && + isa(Tuple->getOperand(1)); + } + return false; +} + +MDTuple *MMRAMetadata::getTagMD(LLVMContext &Ctx, StringRef Prefix, + StringRef Suffix) { + return MDTuple::get(Ctx, + {MDString::get(Ctx, Prefix), MDString::get(Ctx, Suffix)}); +} + +MDTuple *MMRAMetadata::getMD(LLVMContext &Ctx, + ArrayRef Tags) { + if (Tags.empty()) + return nullptr; + + if (Tags.size() == 1) + return getTagMD(Ctx, Tags.front()); + + SmallVector MMRAs; + for (const auto &Tag : Tags) + MMRAs.push_back(getTagMD(Ctx, Tag)); + return MDTuple::get(Ctx, MMRAs); +} + +MDNode *MMRAMetadata::combine(LLVMContext &Ctx, const MMRAMetadata &A, + const MMRAMetadata &B) { + // Let A and B be two tags set, and U be the prefix-wise union of A and B. + // For every unique tag prefix P present in A or B: + // * If either A or B has no tags with prefix P, no tags with prefix + // P are added to U. + // * If both A and B have at least one tag with prefix P, all tags with prefix + // P from both sets are added to U. + + SmallVector Result; + + for (const auto &[P, S] : A) { + if (B.hasTagWithPrefix(P)) + Result.push_back(getTagMD(Ctx, P, S)); + } + for (const auto &[P, S] : B) { + if (A.hasTagWithPrefix(P)) + Result.push_back(getTagMD(Ctx, P, S)); + } + + return MDTuple::get(Ctx, Result); +} + +bool MMRAMetadata::hasTag(StringRef Prefix, StringRef Suffix) const { + return Tags.count({Prefix, Suffix}); +} + +bool MMRAMetadata::isCompatibleWith(const MMRAMetadata &Other) const { + // Two sets of tags are compatible iff, for every unique tag prefix P + // present in at least one set: + // - the other set contains no tag with prefix P, or + // - at least one tag with prefix P is common to both sets. + + StringMap PrefixStatuses; + for (const auto &[P, S] : Tags) + PrefixStatuses[P] |= (Other.hasTag(P, S) || !Other.hasTagWithPrefix(P)); + for (const auto &[P, S] : Other) + PrefixStatuses[P] |= (hasTag(P, S) || !hasTagWithPrefix(P)); + + for (auto &[Prefix, Status] : PrefixStatuses) { + if (!Status) + return false; + } + + return true; +} + +bool MMRAMetadata::hasTagWithPrefix(StringRef Prefix) const { + for (const auto &[P, S] : Tags) + if (P == Prefix) + return true; + return false; +} + +MMRAMetadata::const_iterator MMRAMetadata::begin() const { + return Tags.begin(); +} + +MMRAMetadata::const_iterator MMRAMetadata::end() const { return Tags.end(); } + +bool MMRAMetadata::empty() const { return Tags.empty(); } + +unsigned MMRAMetadata::size() const { return Tags.size(); } + +void MMRAMetadata::print(raw_ostream &OS) const { + bool IsFirst = true; + // TODO: use map_iter + join + for (const auto &[P, S] : Tags) { + if (IsFirst) + IsFirst = false; + else + OS << ", "; + OS << P << ":" << S; + } +} + +LLVM_DUMP_METHOD +void MMRAMetadata::dump() const { print(dbgs()); } + +//===- Helpers ------------------------------------------------------------===// + +static bool isReadWriteMemCall(const Instruction &I) { + if (const auto *C = dyn_cast(&I)) + return C->mayReadOrWriteMemory() || + !C->getMemoryEffects().doesNotAccessMemory(); + return false; +} + +bool llvm::canInstructionHaveMMRAs(const Instruction &I) { + return isa(I) || isa(I) || isa(I) || + isa(I) || isa(I) || isReadWriteMemCall(I); +} diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index edad3be9a3e09819368c381a3b938bdb1fc81afd..365bba8e0b2ff81eb185f32e19ec16c919f77de7 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -99,6 +99,7 @@ #include "llvm/IR/IntrinsicsNVPTX.h" #include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/LLVMContext.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" #include "llvm/IR/ModuleSlotTracker.h" @@ -116,6 +117,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/ErrorHandling.h" #include "llvm/Support/MathExtras.h" +#include "llvm/Support/ModRef.h" #include "llvm/Support/raw_ostream.h" #include #include @@ -529,6 +531,7 @@ private: void visitMemProfMetadata(Instruction &I, MDNode *MD); void visitCallsiteMetadata(Instruction &I, MDNode *MD); void visitDIAssignIDMetadata(Instruction &I, MDNode *MD); + void visitMMRAMetadata(Instruction &I, MDNode *MD); void visitAnnotationMetadata(MDNode *Annotation); void visitAliasScopeMetadata(const MDNode *MD); void visitAliasScopeListMetadata(const MDNode *MD); @@ -4844,6 +4847,24 @@ void Verifier::visitDIAssignIDMetadata(Instruction &I, MDNode *MD) { } } +void Verifier::visitMMRAMetadata(Instruction &I, MDNode *MD) { + Check(canInstructionHaveMMRAs(I), + "!mmra metadata attached to unexpected instruction kind", I, MD); + + // MMRA Metadata should either be a tag, e.g. !{!"foo", !"bar"}, or a + // list of tags such as !2 in the following example: + // !0 = !{!"a", !"b"} + // !1 = !{!"c", !"d"} + // !2 = !{!0, !1} + if (MMRAMetadata::isTagMD(MD)) + return; + + Check(isa(MD), "!mmra expected to be a metadata tuple", I, MD); + for (const MDOperand &MDOp : MD->operands()) + Check(MMRAMetadata::isTagMD(MDOp.get()), + "!mmra metadata tuple operand is not an MMRA tag", I, MDOp.get()); +} + void Verifier::visitCallStackMetadata(MDNode *MD) { // Call stack metadata should consist of a list of at least 1 constant int // (representing a hash of the location). @@ -5161,6 +5182,9 @@ void Verifier::visitInstruction(Instruction &I) { if (MDNode *MD = I.getMetadata(LLVMContext::MD_DIAssignID)) visitDIAssignIDMetadata(I, MD); + if (MDNode *MMRA = I.getMetadata(LLVMContext::MD_mmra)) + visitMMRAMetadata(I, MMRA); + if (MDNode *Annotation = I.getMetadata(LLVMContext::MD_annotation)) visitAnnotationMetadata(Annotation); diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp index 005521bad6e014e0b68c732985be5fa4538bb547..b8ef2654ed6e3b2fb03aa288c059c0389bc3eeef 100644 --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -725,7 +725,13 @@ void ELFWriter::computeSymbolTable( HasLargeSectionIndex = true; } + // Temporary symbols generated for certain assembler features (.eh_frame, + // .debug_line) of an empty name may be referenced by relocations due to + // linker relaxation. Rename them to ".L0 " to match the gas fake label name + // and allow ld/objcopy --discard-locals to discard such symbols. StringRef Name = Symbol.getName(); + if (Name.empty()) + Name = ".L0 "; // Sections have their own string table if (Symbol.getType() != ELF::STT_SECTION) { diff --git a/llvm/lib/Object/ELFObjectFile.cpp b/llvm/lib/Object/ELFObjectFile.cpp index efec612957de33352ce64ee0d62559c2826254ad..24d7a7a280fd9a8e8733f5e5496c4e4526134534 100644 --- a/llvm/lib/Object/ELFObjectFile.cpp +++ b/llvm/lib/Object/ELFObjectFile.cpp @@ -24,7 +24,7 @@ #include "llvm/Support/MathExtras.h" #include "llvm/Support/RISCVAttributeParser.h" #include "llvm/Support/RISCVAttributes.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/SubtargetFeature.h" #include "llvm/TargetParser/Triple.h" #include diff --git a/llvm/lib/Object/ModuleSymbolTable.cpp b/llvm/lib/Object/ModuleSymbolTable.cpp index 07f76688fa43e7954cbab885b5ae234448fbd455..d8f520ad02c2f2cd63d6a72d7073dea0213c8a10 100644 --- a/llvm/lib/Object/ModuleSymbolTable.cpp +++ b/llvm/lib/Object/ModuleSymbolTable.cpp @@ -175,6 +175,20 @@ void ModuleSymbolTable::CollectAsmSymbols( AsmSymbol(Key, BasicSymbolRef::Flags(Res)); } }); + + // In ELF, object code generated for x86-32 and some code models of x86-64 may + // reference the special symbol _GLOBAL_OFFSET_TABLE_ that is not used in the + // IR. Record it like inline asm symbols. + Triple TT(M.getTargetTriple()); + if (!TT.isOSBinFormatELF() || !TT.isX86()) + return; + auto CM = M.getCodeModel(); + if (TT.getArch() == Triple::x86 || CM == CodeModel::Medium || + CM == CodeModel::Large) { + AsmSymbol("_GLOBAL_OFFSET_TABLE_", + BasicSymbolRef::Flags(BasicSymbolRef::SF_Undefined | + BasicSymbolRef::SF_Global)); + } } void ModuleSymbolTable::CollectAsmSymvers( diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp index 4a6fc9d64b6900319fcdfd28e2307886e98d04a5..70ae57f77daef766e5b5f8b0f725732d91a85845 100644 --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -184,12 +184,13 @@ public: InstrProfWriter::InstrProfWriter( bool Sparse, uint64_t TemporalProfTraceReservoirSize, uint64_t MaxTemporalProfTraceLength, bool WritePrevVersion, - memprof::IndexedVersion MemProfVersionRequested) + memprof::IndexedVersion MemProfVersionRequested, bool MemProfFullSchema) : Sparse(Sparse), MaxTemporalProfTraceLength(MaxTemporalProfTraceLength), TemporalProfTraceReservoirSize(TemporalProfTraceReservoirSize), InfoObj(new InstrProfRecordWriterTrait()), WritePrevVersion(WritePrevVersion), - MemProfVersionRequested(MemProfVersionRequested) {} + MemProfVersionRequested(MemProfVersionRequested), + MemProfFullSchema(MemProfFullSchema) {} InstrProfWriter::~InstrProfWriter() { delete InfoObj; } @@ -507,7 +508,7 @@ static Error writeMemProfV0( OS.write(0ULL); // Reserve space for the memprof frame payload offset. OS.write(0ULL); // Reserve space for the memprof frame table offset. - auto Schema = memprof::PortableMemInfoBlock::getSchema(); + auto Schema = memprof::PortableMemInfoBlock::getFullSchema(); writeMemProfSchema(OS, Schema); uint64_t RecordTableOffset = @@ -533,7 +534,7 @@ static Error writeMemProfV1( OS.write(0ULL); // Reserve space for the memprof frame payload offset. OS.write(0ULL); // Reserve space for the memprof frame table offset. - auto Schema = memprof::PortableMemInfoBlock::getSchema(); + auto Schema = memprof::PortableMemInfoBlock::getFullSchema(); writeMemProfSchema(OS, Schema); uint64_t RecordTableOffset = @@ -554,7 +555,8 @@ static Error writeMemProfV2( &MemProfRecordData, llvm::MapVector &MemProfFrameData, llvm::MapVector> - &MemProfCallStackData) { + &MemProfCallStackData, + bool MemProfFullSchema) { OS.write(memprof::Version2); uint64_t HeaderUpdatePos = OS.tell(); OS.write(0ULL); // Reserve space for the memprof record table offset. @@ -563,7 +565,9 @@ static Error writeMemProfV2( OS.write(0ULL); // Reserve space for the memprof call stack payload offset. OS.write(0ULL); // Reserve space for the memprof call stack table offset. - auto Schema = memprof::PortableMemInfoBlock::getSchema(); + auto Schema = memprof::PortableMemInfoBlock::getHotColdSchema(); + if (MemProfFullSchema) + Schema = memprof::PortableMemInfoBlock::getFullSchema(); writeMemProfSchema(OS, Schema); uint64_t RecordTableOffset = @@ -605,7 +609,7 @@ static Error writeMemProf( llvm::MapVector &MemProfFrameData, llvm::MapVector> &MemProfCallStackData, - memprof::IndexedVersion MemProfVersionRequested) { + memprof::IndexedVersion MemProfVersionRequested, bool MemProfFullSchema) { switch (MemProfVersionRequested) { case memprof::Version0: @@ -614,7 +618,7 @@ static Error writeMemProf( return writeMemProfV1(OS, MemProfRecordData, MemProfFrameData); case memprof::Version2: return writeMemProfV2(OS, MemProfRecordData, MemProfFrameData, - MemProfCallStackData); + MemProfCallStackData, MemProfFullSchema); } return make_error( @@ -733,7 +737,8 @@ Error InstrProfWriter::writeImpl(ProfOStream &OS) { if (static_cast(ProfileKind & InstrProfKind::MemProf)) { MemProfSectionStart = OS.tell(); if (auto E = writeMemProf(OS, MemProfRecordData, MemProfFrameData, - MemProfCallStackData, MemProfVersionRequested)) + MemProfCallStackData, MemProfVersionRequested, + MemProfFullSchema)) return E; } diff --git a/llvm/lib/ProfileData/MemProf.cpp b/llvm/lib/ProfileData/MemProf.cpp index 8e0402dd16e680ea994b79f23d6b437c384842b9..9a46d1151311f471c30b963900e0798bb96dd1cc 100644 --- a/llvm/lib/ProfileData/MemProf.cpp +++ b/llvm/lib/ProfileData/MemProf.cpp @@ -10,42 +10,46 @@ namespace llvm { namespace memprof { -static size_t serializedSizeV0(const IndexedAllocationInfo &IAI) { +static size_t serializedSizeV0(const IndexedAllocationInfo &IAI, + const MemProfSchema &Schema) { size_t Size = 0; // The number of frames to serialize. Size += sizeof(uint64_t); // The callstack frame ids. Size += sizeof(FrameId) * IAI.CallStack.size(); // The size of the payload. - Size += PortableMemInfoBlock::serializedSize(); + Size += PortableMemInfoBlock::serializedSize(Schema); return Size; } -static size_t serializedSizeV2(const IndexedAllocationInfo &IAI) { +static size_t serializedSizeV2(const IndexedAllocationInfo &IAI, + const MemProfSchema &Schema) { size_t Size = 0; // The CallStackId Size += sizeof(CallStackId); // The size of the payload. - Size += PortableMemInfoBlock::serializedSize(); + Size += PortableMemInfoBlock::serializedSize(Schema); return Size; } -size_t IndexedAllocationInfo::serializedSize(IndexedVersion Version) const { +size_t IndexedAllocationInfo::serializedSize(const MemProfSchema &Schema, + IndexedVersion Version) const { switch (Version) { case Version0: case Version1: - return serializedSizeV0(*this); + return serializedSizeV0(*this, Schema); case Version2: - return serializedSizeV2(*this); + return serializedSizeV2(*this, Schema); } llvm_unreachable("unsupported MemProf version"); } -static size_t serializedSizeV0(const IndexedMemProfRecord &Record) { +static size_t serializedSizeV0(const IndexedMemProfRecord &Record, + const MemProfSchema &Schema) { // The number of alloc sites to serialize. size_t Result = sizeof(uint64_t); for (const IndexedAllocationInfo &N : Record.AllocSites) - Result += N.serializedSize(Version0); + Result += N.serializedSize(Schema, Version0); // The number of callsites we have information for. Result += sizeof(uint64_t); @@ -57,11 +61,12 @@ static size_t serializedSizeV0(const IndexedMemProfRecord &Record) { return Result; } -static size_t serializedSizeV2(const IndexedMemProfRecord &Record) { +static size_t serializedSizeV2(const IndexedMemProfRecord &Record, + const MemProfSchema &Schema) { // The number of alloc sites to serialize. size_t Result = sizeof(uint64_t); for (const IndexedAllocationInfo &N : Record.AllocSites) - Result += N.serializedSize(Version2); + Result += N.serializedSize(Schema, Version2); // The number of callsites we have information for. Result += sizeof(uint64_t); @@ -70,13 +75,14 @@ static size_t serializedSizeV2(const IndexedMemProfRecord &Record) { return Result; } -size_t IndexedMemProfRecord::serializedSize(IndexedVersion Version) const { +size_t IndexedMemProfRecord::serializedSize(const MemProfSchema &Schema, + IndexedVersion Version) const { switch (Version) { case Version0: case Version1: - return serializedSizeV0(*this); + return serializedSizeV0(*this, Schema); case Version2: - return serializedSizeV2(*this); + return serializedSizeV2(*this, Schema); } llvm_unreachable("unsupported MemProf version"); } @@ -156,7 +162,7 @@ static IndexedMemProfRecord deserializeV0(const MemProfSchema &Schema, } Node.CSId = hashCallStack(Node.CallStack); Node.Info.deserialize(Schema, Ptr); - Ptr += PortableMemInfoBlock::serializedSize(); + Ptr += PortableMemInfoBlock::serializedSize(Schema); Record.AllocSites.push_back(Node); } @@ -193,7 +199,7 @@ static IndexedMemProfRecord deserializeV2(const MemProfSchema &Schema, IndexedAllocationInfo Node; Node.CSId = endian::readNext(Ptr); Node.Info.deserialize(Schema, Ptr); - Ptr += PortableMemInfoBlock::serializedSize(); + Ptr += PortableMemInfoBlock::serializedSize(Schema); Record.AllocSites.push_back(Node); } diff --git a/llvm/lib/Support/CMakeLists.txt b/llvm/lib/Support/CMakeLists.txt index e18beddf7bc5b7f77aad45511fbf4fbde86535ff..03e888958a0711a54d3949e083b14c3612009f3e 100644 --- a/llvm/lib/Support/CMakeLists.txt +++ b/llvm/lib/Support/CMakeLists.txt @@ -219,7 +219,7 @@ add_llvm_component_library(LLVMSupport Regex.cpp RISCVAttributes.cpp RISCVAttributeParser.cpp - RISCVISAInfo.cpp + RISCVISAUtils.cpp ScaledNumber.cpp ScopedPrinter.cpp SHA1.cpp diff --git a/llvm/lib/Support/RISCVISAUtils.cpp b/llvm/lib/Support/RISCVISAUtils.cpp new file mode 100644 index 0000000000000000000000000000000000000000..ca7518f71907b5a0d448d48f3f20e3af105ecf0e --- /dev/null +++ b/llvm/lib/Support/RISCVISAUtils.cpp @@ -0,0 +1,88 @@ +//===-- RISCVISAUtils.cpp - RISC-V ISA Utilities --------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Utilities shared by TableGen and RISCVISAInfo. +// +//===----------------------------------------------------------------------===// + +#include "llvm/Support/RISCVISAUtils.h" +#include + +using namespace llvm; + +// We rank extensions in the following order: +// -Single letter extensions in canonical order. +// -Unknown single letter extensions in alphabetical order. +// -Multi-letter extensions starting with 'z' sorted by canonical order of +// the second letter then sorted alphabetically. +// -Multi-letter extensions starting with 's' in alphabetical order. +// -(TODO) Multi-letter extensions starting with 'zxm' in alphabetical order. +// -X extensions in alphabetical order. +// These flags are used to indicate the category. The first 6 bits store the +// single letter extension rank for single letter and multi-letter extensions +// starting with 'z'. +enum RankFlags { + RF_Z_EXTENSION = 1 << 6, + RF_S_EXTENSION = 1 << 7, + RF_X_EXTENSION = 1 << 8, +}; + +// Get the rank for single-letter extension, lower value meaning higher +// priority. +static unsigned singleLetterExtensionRank(char Ext) { + assert(Ext >= 'a' && Ext <= 'z'); + switch (Ext) { + case 'i': + return 0; + case 'e': + return 1; + } + + size_t Pos = RISCVISAUtils::AllStdExts.find(Ext); + if (Pos != StringRef::npos) + return Pos + 2; // Skip 'e' and 'i' from above. + + // If we got an unknown extension letter, then give it an alphabetical + // order, but after all known standard extensions. + return 2 + RISCVISAUtils::AllStdExts.size() + (Ext - 'a'); +} + +// Get the rank for multi-letter extension, lower value meaning higher +// priority/order in canonical order. +static unsigned getExtensionRank(const std::string &ExtName) { + assert(ExtName.size() >= 1); + switch (ExtName[0]) { + case 's': + return RF_S_EXTENSION; + case 'z': + assert(ExtName.size() >= 2); + // `z` extension must be sorted by canonical order of second letter. + // e.g. zmx has higher rank than zax. + return RF_Z_EXTENSION | singleLetterExtensionRank(ExtName[1]); + case 'x': + return RF_X_EXTENSION; + default: + assert(ExtName.size() == 1); + return singleLetterExtensionRank(ExtName[0]); + } +} + +// Compare function for extension. +// Only compare the extension name, ignore version comparison. +bool llvm::RISCVISAUtils::compareExtension(const std::string &LHS, + const std::string &RHS) { + unsigned LHSRank = getExtensionRank(LHS); + unsigned RHSRank = getExtensionRank(RHS); + + // If the ranks differ, pick the lower rank. + if (LHSRank != RHSRank) + return LHSRank < RHSRank; + + // If the rank is same, it must be sorted by lexicographic order. + return LHS < RHS; +} diff --git a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp index 1c20e24e41d7eacf23593c26ea5214225ce80701..2a4a3c0df08f9c3eb6b188731ebc1f9031e7f8f8 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionOptimizer.cpp @@ -163,7 +163,7 @@ MachineInstr *AArch64ConditionOptimizer::findSuitableCompare( MachineInstr &I = *It; assert(!I.isTerminator() && "Spurious terminator"); // Check if there is any use of NZCV between CMP and Bcc. - if (I.readsRegister(AArch64::NZCV)) + if (I.readsRegister(AArch64::NZCV, /*TRI=*/nullptr)) return nullptr; switch (I.getOpcode()) { // cmp is an alias for subs with a dead destination register. diff --git a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp index 17e0e3072db6ffc674d9872b7070ec731a2f67d5..8c16a88a13a408ab3ed9781852f16c799fc39d4c 100644 --- a/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp +++ b/llvm/lib/Target/AArch64/AArch64ConditionalCompares.cpp @@ -299,7 +299,7 @@ MachineInstr *SSACCmpConv::findConvertibleCompare(MachineBasicBlock *MBB) { if (I == MBB->end()) return nullptr; // The terminator must be controlled by the flags. - if (!I->readsRegister(AArch64::NZCV)) { + if (!I->readsRegister(AArch64::NZCV, /*TRI=*/nullptr)) { switch (I->getOpcode()) { case AArch64::CBZW: case AArch64::CBZX: diff --git a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp index 3e04cbae8acf18a10487782a47dcc31f5110b090..2bc14f9821e63973eb90f095d2485d0a4a83f86f 100644 --- a/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp +++ b/llvm/lib/Target/AArch64/AArch64DeadRegisterDefinitionsPass.cpp @@ -124,7 +124,8 @@ void AArch64DeadRegisterDefinitions::processMachineBasicBlock( LLVM_DEBUG(dbgs() << " Ignoring, operand is frame index\n"); continue; } - if (MI.definesRegister(AArch64::XZR) || MI.definesRegister(AArch64::WZR)) { + if (MI.definesRegister(AArch64::XZR, /*TRI=*/nullptr) || + MI.definesRegister(AArch64::WZR, /*TRI=*/nullptr)) { // It is not allowed to write to the same register (not even the zero // register) twice in a single instruction. LLVM_DEBUG( diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 2238015e43b1732e253b746dc3e1a6e554513bc0..892b5853e00e14c1cb823a9a85144fba0c6adf08 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1603,39 +1603,19 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, Custom); } - if (!Subtarget->isNeonAvailable()) { - setTruncStoreAction(MVT::v2f32, MVT::v2bf16, Custom); - setTruncStoreAction(MVT::v4f32, MVT::v4bf16, Custom); - setTruncStoreAction(MVT::v8f32, MVT::v8bf16, Custom); - setTruncStoreAction(MVT::v2f64, MVT::v2bf16, Custom); - setTruncStoreAction(MVT::v4f64, MVT::v4bf16, Custom); - setTruncStoreAction(MVT::v2f32, MVT::v2f16, Custom); - setTruncStoreAction(MVT::v4f32, MVT::v4f16, Custom); - setTruncStoreAction(MVT::v8f32, MVT::v8f16, Custom); - setTruncStoreAction(MVT::v1f64, MVT::v1f16, Custom); - setTruncStoreAction(MVT::v2f64, MVT::v2f16, Custom); - setTruncStoreAction(MVT::v4f64, MVT::v4f16, Custom); - setTruncStoreAction(MVT::v1f64, MVT::v1f32, Custom); - setTruncStoreAction(MVT::v2f64, MVT::v2f32, Custom); - setTruncStoreAction(MVT::v4f64, MVT::v4f32, Custom); - for (MVT VT : {MVT::v8i8, MVT::v16i8, MVT::v4i16, MVT::v8i16, MVT::v2i32, - MVT::v4i32, MVT::v1i64, MVT::v2i64}) - addTypeForFixedLengthSVE(VT, /*StreamingSVE=*/ true); - - for (MVT VT : - {MVT::v4f16, MVT::v8f16, MVT::v2f32, MVT::v4f32, MVT::v2f64}) - addTypeForFixedLengthSVE(VT, /*StreamingSVE=*/ true); - } - // NOTE: Currently this has to happen after computeRegisterProperties rather // than the preferred option of combining it with the addRegisterClass call. if (Subtarget->useSVEForFixedLengthVectors()) { - for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) - if (useSVEForFixedLengthVectorVT(VT)) - addTypeForFixedLengthSVE(VT, /*StreamingSVE=*/ false); - for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) - if (useSVEForFixedLengthVectorVT(VT)) - addTypeForFixedLengthSVE(VT, /*StreamingSVE=*/ false); + for (MVT VT : MVT::integer_fixedlen_vector_valuetypes()) { + if (useSVEForFixedLengthVectorVT( + VT, /*OverrideNEON=*/!Subtarget->isNeonAvailable())) + addTypeForFixedLengthSVE(VT); + } + for (MVT VT : MVT::fp_fixedlen_vector_valuetypes()) { + if (useSVEForFixedLengthVectorVT( + VT, /*OverrideNEON=*/!Subtarget->isNeonAvailable())) + addTypeForFixedLengthSVE(VT); + } // 64bit results can mean a bigger than NEON input. for (auto VT : {MVT::v8i8, MVT::v4i16}) @@ -1869,8 +1849,7 @@ bool AArch64TargetLowering::shouldExpandCttzElements(EVT VT) const { return !Subtarget->hasSVEorSME() || VT != MVT::nxv16i1; } -void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT, - bool StreamingSVE) { +void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT) { assert(VT.isFixedLengthVector() && "Expected fixed length vector type!"); // By default everything must be expanded. @@ -1889,13 +1868,17 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT, setCondCodeAction(ISD::SETONE, VT, Expand); } + TargetLoweringBase::LegalizeAction Default = + VT == MVT::v1f64 ? Expand : Custom; + // Mark integer truncating stores/extending loads as having custom lowering if (VT.isInteger()) { MVT InnerVT = VT.changeVectorElementType(MVT::i8); while (InnerVT != VT) { - setTruncStoreAction(VT, InnerVT, Custom); - setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Custom); - setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Custom); + setTruncStoreAction(VT, InnerVT, Default); + setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Default); + setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Default); + setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Default); InnerVT = InnerVT.changeVectorElementType( MVT::getIntegerVT(2 * InnerVT.getScalarSizeInBits())); } @@ -1907,101 +1890,103 @@ void AArch64TargetLowering::addTypeForFixedLengthSVE(MVT VT, MVT InnerVT = VT.changeVectorElementType(MVT::f16); while (InnerVT != VT) { setTruncStoreAction(VT, InnerVT, Custom); - setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Custom); + setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Default); InnerVT = InnerVT.changeVectorElementType( MVT::getFloatingPointVT(2 * InnerVT.getScalarSizeInBits())); } } + bool PreferNEON = VT.is64BitVector() || VT.is128BitVector(); + bool PreferSVE = !PreferNEON && Subtarget->isSVEAvailable(); + // Lower fixed length vector operations to scalable equivalents. - setOperationAction(ISD::ABS, VT, Custom); - setOperationAction(ISD::ADD, VT, Custom); - setOperationAction(ISD::AND, VT, Custom); - setOperationAction(ISD::ANY_EXTEND, VT, Custom); - setOperationAction(ISD::BITCAST, VT, StreamingSVE ? Legal : Custom); - setOperationAction(ISD::BITREVERSE, VT, Custom); - setOperationAction(ISD::BSWAP, VT, Custom); - setOperationAction(ISD::BUILD_VECTOR, VT, Custom); - setOperationAction(ISD::CONCAT_VECTORS, VT, Custom); - setOperationAction(ISD::CTLZ, VT, Custom); - setOperationAction(ISD::CTPOP, VT, Custom); - setOperationAction(ISD::CTTZ, VT, Custom); - setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Custom); - setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); - setOperationAction(ISD::FABS, VT, Custom); - setOperationAction(ISD::FADD, VT, Custom); - setOperationAction(ISD::FCEIL, VT, Custom); - setOperationAction(ISD::FCOPYSIGN, VT, Custom); - setOperationAction(ISD::FDIV, VT, Custom); - setOperationAction(ISD::FFLOOR, VT, Custom); - setOperationAction(ISD::FMA, VT, Custom); - setOperationAction(ISD::FMAXIMUM, VT, Custom); - setOperationAction(ISD::FMAXNUM, VT, Custom); - setOperationAction(ISD::FMINIMUM, VT, Custom); - setOperationAction(ISD::FMINNUM, VT, Custom); - setOperationAction(ISD::FMUL, VT, Custom); - setOperationAction(ISD::FNEARBYINT, VT, Custom); - setOperationAction(ISD::FNEG, VT, Custom); - setOperationAction(ISD::FP_EXTEND, VT, Custom); - setOperationAction(ISD::FP_ROUND, VT, Custom); - setOperationAction(ISD::FP_TO_SINT, VT, Custom); - setOperationAction(ISD::FP_TO_UINT, VT, Custom); - setOperationAction(ISD::FRINT, VT, Custom); - setOperationAction(ISD::FROUND, VT, Custom); - setOperationAction(ISD::FROUNDEVEN, VT, Custom); - setOperationAction(ISD::FSQRT, VT, Custom); - setOperationAction(ISD::FSUB, VT, Custom); - setOperationAction(ISD::FTRUNC, VT, Custom); - setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); - setOperationAction(ISD::LOAD, VT, StreamingSVE ? Legal : Custom); - setOperationAction(ISD::MGATHER, VT, StreamingSVE ? Expand : Custom); - setOperationAction(ISD::MLOAD, VT, Custom); - setOperationAction(ISD::MSCATTER, VT, StreamingSVE ? Expand : Custom); - setOperationAction(ISD::MSTORE, VT, Custom); - setOperationAction(ISD::MUL, VT, Custom); - setOperationAction(ISD::MULHS, VT, Custom); - setOperationAction(ISD::MULHU, VT, Custom); - setOperationAction(ISD::OR, VT, Custom); - setOperationAction(ISD::SCALAR_TO_VECTOR, VT, StreamingSVE ? Legal : Expand); - setOperationAction(ISD::SDIV, VT, Custom); - setOperationAction(ISD::SELECT, VT, Custom); - setOperationAction(ISD::SETCC, VT, Custom); - setOperationAction(ISD::SHL, VT, Custom); - setOperationAction(ISD::SIGN_EXTEND, VT, Custom); - setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); - setOperationAction(ISD::SINT_TO_FP, VT, Custom); - setOperationAction(ISD::SMAX, VT, Custom); - setOperationAction(ISD::SMIN, VT, Custom); - setOperationAction(ISD::SPLAT_VECTOR, VT, Custom); - setOperationAction(ISD::SRA, VT, Custom); - setOperationAction(ISD::SRL, VT, Custom); - setOperationAction(ISD::STORE, VT, StreamingSVE ? Legal : Custom); - setOperationAction(ISD::SUB, VT, Custom); - setOperationAction(ISD::TRUNCATE, VT, Custom); - setOperationAction(ISD::UDIV, VT, Custom); - setOperationAction(ISD::UINT_TO_FP, VT, Custom); - setOperationAction(ISD::UMAX, VT, Custom); - setOperationAction(ISD::UMIN, VT, Custom); - setOperationAction(ISD::VECREDUCE_ADD, VT, Custom); - setOperationAction(ISD::VECREDUCE_AND, VT, Custom); - setOperationAction(ISD::VECREDUCE_FADD, VT, Custom); - setOperationAction(ISD::VECREDUCE_FMAX, VT, Custom); - setOperationAction(ISD::VECREDUCE_FMIN, VT, Custom); - setOperationAction(ISD::VECREDUCE_FMAXIMUM, VT, Custom); - setOperationAction(ISD::VECREDUCE_FMINIMUM, VT, Custom); - setOperationAction(ISD::VECREDUCE_OR, VT, Custom); - setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, - StreamingSVE ? Expand : Custom); - setOperationAction(ISD::VECREDUCE_SMAX, VT, Custom); - setOperationAction(ISD::VECREDUCE_SMIN, VT, Custom); - setOperationAction(ISD::VECREDUCE_UMAX, VT, Custom); - setOperationAction(ISD::VECREDUCE_UMIN, VT, Custom); - setOperationAction(ISD::VECREDUCE_XOR, VT, Custom); - setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom); - setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); - setOperationAction(ISD::VSELECT, VT, Custom); - setOperationAction(ISD::XOR, VT, Custom); - setOperationAction(ISD::ZERO_EXTEND, VT, Custom); + setOperationAction(ISD::ABS, VT, Default); + setOperationAction(ISD::ADD, VT, Default); + setOperationAction(ISD::AND, VT, Default); + setOperationAction(ISD::ANY_EXTEND, VT, Default); + setOperationAction(ISD::BITCAST, VT, PreferNEON ? Legal : Default); + setOperationAction(ISD::BITREVERSE, VT, Default); + setOperationAction(ISD::BSWAP, VT, Default); + setOperationAction(ISD::BUILD_VECTOR, VT, Default); + setOperationAction(ISD::CONCAT_VECTORS, VT, Default); + setOperationAction(ISD::CTLZ, VT, Default); + setOperationAction(ISD::CTPOP, VT, Default); + setOperationAction(ISD::CTTZ, VT, Default); + setOperationAction(ISD::EXTRACT_SUBVECTOR, VT, Default); + setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Default); + setOperationAction(ISD::FABS, VT, Default); + setOperationAction(ISD::FADD, VT, Default); + setOperationAction(ISD::FCEIL, VT, Default); + setOperationAction(ISD::FCOPYSIGN, VT, Default); + setOperationAction(ISD::FDIV, VT, Default); + setOperationAction(ISD::FFLOOR, VT, Default); + setOperationAction(ISD::FMA, VT, Default); + setOperationAction(ISD::FMAXIMUM, VT, Default); + setOperationAction(ISD::FMAXNUM, VT, Default); + setOperationAction(ISD::FMINIMUM, VT, Default); + setOperationAction(ISD::FMINNUM, VT, Default); + setOperationAction(ISD::FMUL, VT, Default); + setOperationAction(ISD::FNEARBYINT, VT, Default); + setOperationAction(ISD::FNEG, VT, Default); + setOperationAction(ISD::FP_EXTEND, VT, Default); + setOperationAction(ISD::FP_ROUND, VT, Default); + setOperationAction(ISD::FP_TO_SINT, VT, Default); + setOperationAction(ISD::FP_TO_UINT, VT, Default); + setOperationAction(ISD::FRINT, VT, Default); + setOperationAction(ISD::FROUND, VT, Default); + setOperationAction(ISD::FROUNDEVEN, VT, Default); + setOperationAction(ISD::FSQRT, VT, Default); + setOperationAction(ISD::FSUB, VT, Default); + setOperationAction(ISD::FTRUNC, VT, Default); + setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Default); + setOperationAction(ISD::LOAD, VT, PreferNEON ? Legal : Default); + setOperationAction(ISD::MGATHER, VT, PreferSVE ? Default : Expand); + setOperationAction(ISD::MLOAD, VT, Default); + setOperationAction(ISD::MSCATTER, VT, PreferSVE ? Default : Expand); + setOperationAction(ISD::MSTORE, VT, Default); + setOperationAction(ISD::MUL, VT, Default); + setOperationAction(ISD::MULHS, VT, Default); + setOperationAction(ISD::MULHU, VT, Default); + setOperationAction(ISD::OR, VT, Default); + setOperationAction(ISD::SCALAR_TO_VECTOR, VT, PreferNEON ? Legal : Expand); + setOperationAction(ISD::SDIV, VT, Default); + setOperationAction(ISD::SELECT, VT, Default); + setOperationAction(ISD::SETCC, VT, Default); + setOperationAction(ISD::SHL, VT, Default); + setOperationAction(ISD::SIGN_EXTEND, VT, Default); + setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Default); + setOperationAction(ISD::SINT_TO_FP, VT, Default); + setOperationAction(ISD::SMAX, VT, Default); + setOperationAction(ISD::SMIN, VT, Default); + setOperationAction(ISD::SPLAT_VECTOR, VT, Default); + setOperationAction(ISD::SRA, VT, Default); + setOperationAction(ISD::SRL, VT, Default); + setOperationAction(ISD::STORE, VT, PreferNEON ? Legal : Default); + setOperationAction(ISD::SUB, VT, Default); + setOperationAction(ISD::TRUNCATE, VT, Default); + setOperationAction(ISD::UDIV, VT, Default); + setOperationAction(ISD::UINT_TO_FP, VT, Default); + setOperationAction(ISD::UMAX, VT, Default); + setOperationAction(ISD::UMIN, VT, Default); + setOperationAction(ISD::VECREDUCE_ADD, VT, Default); + setOperationAction(ISD::VECREDUCE_AND, VT, Default); + setOperationAction(ISD::VECREDUCE_FADD, VT, Default); + setOperationAction(ISD::VECREDUCE_FMAX, VT, Default); + setOperationAction(ISD::VECREDUCE_FMIN, VT, Default); + setOperationAction(ISD::VECREDUCE_FMAXIMUM, VT, Default); + setOperationAction(ISD::VECREDUCE_FMINIMUM, VT, Default); + setOperationAction(ISD::VECREDUCE_OR, VT, Default); + setOperationAction(ISD::VECREDUCE_SEQ_FADD, VT, PreferSVE ? Default : Expand); + setOperationAction(ISD::VECREDUCE_SMAX, VT, Default); + setOperationAction(ISD::VECREDUCE_SMIN, VT, Default); + setOperationAction(ISD::VECREDUCE_UMAX, VT, Default); + setOperationAction(ISD::VECREDUCE_UMIN, VT, Default); + setOperationAction(ISD::VECREDUCE_XOR, VT, Default); + setOperationAction(ISD::VECTOR_SHUFFLE, VT, Default); + setOperationAction(ISD::VECTOR_SPLICE, VT, Default); + setOperationAction(ISD::VSELECT, VT, Default); + setOperationAction(ISD::XOR, VT, Default); + setOperationAction(ISD::ZERO_EXTEND, VT, Default); } void AArch64TargetLowering::addDRTypeForNEON(MVT VT) { diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index db6e8a00d2fb5e960f388ff191337ed46d4d1d4a..400368a5e1303d4e85cfa8a58b4b9a79b538eedb 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -1013,7 +1013,7 @@ private: bool isExtFreeImpl(const Instruction *Ext) const override; void addTypeForNEON(MVT VT); - void addTypeForFixedLengthSVE(MVT VT, bool StreamingSVE); + void addTypeForFixedLengthSVE(MVT VT); void addDRTypeForNEON(MVT VT); void addQRTypeForNEON(MVT VT); diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 9518d573bccdd17f12e97d10e1632a9ff73e433c..7bf06e71a03059cd6c35e20f0c54059a8ca68ae0 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -643,7 +643,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, case AArch64::ADDSXri: case AArch64::ADDSWri: // if NZCV is used, do not fold. - if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) + if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, + true) == -1) return 0; // fall-through to ADDXri and ADDWri. [[fallthrough]]; @@ -671,7 +672,8 @@ static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, case AArch64::SUBSXrr: case AArch64::SUBSWrr: // if NZCV is used, do not fold. - if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) + if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, + true) == -1) return 0; // fall-through to SUBXrr and SUBWrr. [[fallthrough]]; @@ -1275,7 +1277,8 @@ static unsigned convertToNonFlagSettingOpc(const MachineInstr &MI) { // Don't convert all compare instructions, because for some the zero register // encoding becomes the sp register. bool MIDefinesZeroReg = false; - if (MI.definesRegister(AArch64::WZR) || MI.definesRegister(AArch64::XZR)) + if (MI.definesRegister(AArch64::WZR, /*TRI=*/nullptr) || + MI.definesRegister(AArch64::XZR, /*TRI=*/nullptr)) MIDefinesZeroReg = true; switch (MI.getOpcode()) { @@ -1519,10 +1522,11 @@ bool AArch64InstrInfo::optimizeCompareInstr( assert(MRI); // Replace SUBSWrr with SUBWrr if NZCV is not used. - int DeadNZCVIdx = CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, true); + int DeadNZCVIdx = + CmpInstr.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true); if (DeadNZCVIdx != -1) { - if (CmpInstr.definesRegister(AArch64::WZR) || - CmpInstr.definesRegister(AArch64::XZR)) { + if (CmpInstr.definesRegister(AArch64::WZR, /*TRI=*/nullptr) || + CmpInstr.definesRegister(AArch64::XZR, /*TRI=*/nullptr)) { CmpInstr.eraseFromParent(); return true; } @@ -1623,7 +1627,7 @@ findCondCodeUseOperandIdxForBranchOrSelect(const MachineInstr &Instr) { return -1; case AArch64::Bcc: { - int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); + int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV, /*TRI=*/nullptr); assert(Idx >= 2); return Idx - 2; } @@ -1638,7 +1642,7 @@ findCondCodeUseOperandIdxForBranchOrSelect(const MachineInstr &Instr) { case AArch64::CSNEGXr: case AArch64::FCSELSrrr: case AArch64::FCSELDrrr: { - int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV); + int Idx = Instr.findRegisterUseOperandIdx(AArch64::NZCV, /*TRI=*/nullptr); assert(Idx >= 1); return Idx - 1; } @@ -1846,7 +1850,7 @@ static bool canCmpInstrBeRemoved(MachineInstr &MI, MachineInstr &CmpInstr, return false; // NZCV needs to be defined - if (MI.findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) + if (MI.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true) != -1) return false; // CmpInstr is 'ADDS %vreg, 0' or 'SUBS %vreg, 0' or 'SUBS %vreg, 1' @@ -5913,7 +5917,7 @@ static bool canCombine(MachineBasicBlock &MBB, MachineOperand &MO, } if (isCombineInstrSettingFlag(CombineOpc) && - MI->findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) + MI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true) == -1) return false; return true; @@ -6051,7 +6055,8 @@ static bool getMaddPatterns(MachineInstr &Root, if (!isCombineInstrCandidate(Opc)) return false; if (isCombineInstrSettingFlag(Opc)) { - int Cmp_NZCV = Root.findRegisterDefOperandIdx(AArch64::NZCV, true); + int Cmp_NZCV = + Root.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true); // When NZCV is live bail out. if (Cmp_NZCV == -1) return false; @@ -6546,7 +6551,8 @@ static bool getMiscPatterns(MachineInstr &Root, } if (isCombineInstrSettingFlag(Opc) && - Root.findRegisterDefOperandIdx(AArch64::NZCV, true) == -1) + Root.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, true) == + -1) return false; if (canCombine(MBB, Root.getOperand(2), AArch64::ADDWrr) || @@ -8031,7 +8037,8 @@ bool AArch64InstrInfo::optimizeCondBranch(MachineInstr &MI) const { DefMI->getOperand(2).getReg() == AArch64::XZR)) return false; - if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, true) != -1) + if (DefMI->findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr, + true) != -1) return false; AArch64CC::CondCode CC = (AArch64CC::CondCode)DefMI->getOperand(3).getImm(); @@ -9238,7 +9245,8 @@ AArch64InstrInfo::isCopyInstrImpl(const MachineInstr &MI) const { MI.getOperand(0).getSubReg() == 0) && (!MI.getOperand(0).getReg().isPhysical() || MI.findRegisterDefOperandIdx(MI.getOperand(0).getReg() - AArch64::W0 + - AArch64::X0) == -1)) + AArch64::X0, + /*TRI=*/nullptr) == -1)) return DestSourcePair{MI.getOperand(0), MI.getOperand(2)}; if (MI.getOpcode() == AArch64::ORRXrs && diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.h b/llvm/lib/Target/AArch64/AArch64InstrInfo.h index 9a2914891675c543cc34f599096598100051c1ef..f434799c3982b4b0a4a95a6b89b9c86190544ef4 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.h +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.h @@ -725,6 +725,7 @@ static inline unsigned getAUTOpcodeForKey(AArch64PACKey::ID K, bool Zero) { case DA: return Zero ? AArch64::AUTDZA : AArch64::AUTDA; case DB: return Zero ? AArch64::AUTDZB : AArch64::AUTDB; } + llvm_unreachable("Unhandled AArch64PACKey::ID enum"); } /// Return PAC opcode to be used for a ptrauth sign using the given key, or its @@ -737,6 +738,7 @@ static inline unsigned getPACOpcodeForKey(AArch64PACKey::ID K, bool Zero) { case DA: return Zero ? AArch64::PACDZA : AArch64::PACDA; case DB: return Zero ? AArch64::PACDZB : AArch64::PACDB; } + llvm_unreachable("Unhandled AArch64PACKey::ID enum"); } // struct TSFlags { diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index fb18d1c63ae80dd3a100166a7d9e77d12327a08e..a7abb58064a5351d5a110354cffa440300cdb4b3 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -315,6 +315,8 @@ def UseNegativeImmediates def UseScalarIncVL : Predicate<"Subtarget->useScalarIncVL()">; +def NoUseScalarIncVL : Predicate<"!Subtarget->useScalarIncVL()">; + def UseSVEFPLD1R : Predicate<"!Subtarget->noSVEFPLD1R()">; def IsNeonAvailable : Predicate<"Subtarget->isNeonAvailable()">; diff --git a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp index 05d60872bf51acac4b80e61e640f7805660d1df9..ff7a0d1faedf7ce6afc59282df24c8d9f51489ad 100644 --- a/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp +++ b/llvm/lib/Target/AArch64/AArch64MacroFusion.cpp @@ -245,7 +245,7 @@ static bool isCCSelectPair(const MachineInstr *FirstMI, if (FirstMI == nullptr) return true; - if (FirstMI->definesRegister(AArch64::WZR)) + if (FirstMI->definesRegister(AArch64::WZR, /*TRI=*/nullptr)) switch (FirstMI->getOpcode()) { case AArch64::SUBSWrs: return !AArch64InstrInfo::hasShiftedReg(*FirstMI); @@ -263,7 +263,7 @@ static bool isCCSelectPair(const MachineInstr *FirstMI, if (FirstMI == nullptr) return true; - if (FirstMI->definesRegister(AArch64::XZR)) + if (FirstMI->definesRegister(AArch64::XZR, /*TRI=*/nullptr)) switch (FirstMI->getOpcode()) { case AArch64::SUBSXrs: return !AArch64InstrInfo::hasShiftedReg(*FirstMI); diff --git a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp index 1494312886a40de8e35f0a77cb1213dced49e5c7..69fc13883f6b834a6c8239e1ef0c589ec1d1ca76 100644 --- a/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp +++ b/llvm/lib/Target/AArch64/AArch64RedundantCopyElimination.cpp @@ -265,7 +265,7 @@ bool AArch64RedundantCopyElimination::knownRegValInBlock( } // Bail if we see an instruction that defines NZCV that we don't handle. - if (PredI.definesRegister(AArch64::NZCV)) + if (PredI.definesRegister(AArch64::NZCV, /*TRI=*/nullptr)) return false; // Track clobbered and used registers. diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 705fa523a8b8f235a6e33c976e38c069e6081aae..525ae79da9962439c788dc106367c9f5aaeca5d6 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -2517,6 +2517,23 @@ let Predicates = [HasSVEorSME] in { def : Pat<(vscale (sve_cntd_imm_neg i32:$imm)), (SUBXrs XZR, (CNTD_XPiI 31, $imm), 0)>; } + // Add NoUseScalarIncVL to avoid affecting for patterns with UseScalarIncVL + let Predicates = [HasSVEorSME, NoUseScalarIncVL] in { + def : Pat<(add GPR64:$op, (vscale (sve_cnth_imm_neg i32:$imm))), + (SUBXrs GPR64:$op, (CNTH_XPiI 31, $imm), 0)>; + def : Pat<(add GPR64:$op, (vscale (sve_cntw_imm_neg i32:$imm))), + (SUBXrs GPR64:$op, (CNTW_XPiI 31, $imm), 0)>; + def : Pat<(add GPR64:$op, (vscale (sve_cntd_imm_neg i32:$imm))), + (SUBXrs GPR64:$op, (CNTD_XPiI 31, $imm), 0)>; + + def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cnth_imm_neg i32:$imm))))), + (SUBSWrr GPR32:$op, (EXTRACT_SUBREG (CNTH_XPiI 31, $imm), sub_32))>; + def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntw_imm_neg i32:$imm))))), + (SUBSWrr GPR32:$op, (EXTRACT_SUBREG (CNTW_XPiI 31, $imm), sub_32))>; + def : Pat<(add GPR32:$op, (i32 (trunc (vscale (sve_cntd_imm_neg i32:$imm))))), + (SUBSWrr GPR32:$op, (EXTRACT_SUBREG (CNTD_XPiI 31, $imm), sub_32))>; + } + let AddedComplexity = 5 in { def : Pat<(nxv8i16 (add ZPR:$op, (nxv8i16 (splat_vector (i32 (trunc (vscale (sve_cnth_imm i32:$imm)))))))), (INCH_ZPiI ZPR:$op, 31, $imm)>; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index 9eb1ecbb031580343700647606cafd1981f8257e..ef09a3cde495450c0271574fbbf3fb947da44144 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -144,7 +144,6 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { case CortexA78C: case CortexR82: case CortexX1: - case CortexX1C: PrefFunctionAlignment = Align(16); PrefLoopAlignment = Align(32); MaxBytesForLoopAlignment = 16; diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.h b/llvm/lib/Target/AArch64/AArch64Subtarget.h index c5ebd4c6cc615ae02dc073da7caff2fbe3f84b5c..3f3eefc4f68077cbbb3856c3c15c1f2ee153f18f 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.h +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.h @@ -39,61 +39,9 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo { public: enum ARMProcFamilyEnum : uint8_t { Others, - A64FX, - Ampere1, - Ampere1A, - Ampere1B, - AppleA7, - AppleA10, - AppleA11, - AppleA12, - AppleA13, - AppleA14, - AppleA15, - AppleA16, - AppleA17, - Carmel, - CortexA35, - CortexA53, - CortexA55, - CortexA510, - CortexA520, - CortexA57, - CortexA65, - CortexA72, - CortexA73, - CortexA75, - CortexA76, - CortexA77, - CortexA78, - CortexA78AE, - CortexA78C, - CortexA710, - CortexA715, - CortexA720, - CortexR82, - CortexX1, - CortexX1C, - CortexX2, - CortexX3, - CortexX4, - ExynosM3, - Falkor, - Kryo, - NeoverseE1, - NeoverseN1, - NeoverseN2, - Neoverse512TVB, - NeoverseV1, - NeoverseV2, - Saphira, - ThunderX2T99, - ThunderX, - ThunderXT81, - ThunderXT83, - ThunderXT88, - ThunderX3T110, - TSV110 +#define ARM_PROCESSOR_FAMILY(ENUM) ENUM, +#include "llvm/TargetParser/AArch64TargetParserDef.inc" +#undef ARM_PROCESSOR_FAMILY }; protected: diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 700242b88346cbcba1e1b304cf8741a7f999eb7d..af3a94a0faece8a141f7f1f865a324841b1a5702 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -790,6 +790,27 @@ AArch64TTIImpl::getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, break; return TyL.first + ExtraCost; } + case Intrinsic::get_active_lane_mask: { + auto *RetTy = dyn_cast(ICA.getReturnType()); + if (RetTy) { + EVT RetVT = getTLI()->getValueType(DL, RetTy); + EVT OpVT = getTLI()->getValueType(DL, ICA.getArgTypes()[0]); + if (!getTLI()->shouldExpandGetActiveLaneMask(RetVT, OpVT) && + !getTLI()->isTypeLegal(RetVT)) { + // We don't have enough context at this point to determine if the mask + // is going to be kept live after the block, which will force the vXi1 + // type to be expanded to legal vectors of integers, e.g. v4i1->v4i32. + // For now, we just assume the vectorizer created this intrinsic and + // the result will be the input for a PHI. In this case the cost will + // be extremely high for fixed-width vectors. + // NOTE: getScalarizationOverhead returns a cost that's far too + // pessimistic for the actual generated codegen. In reality there are + // two instructions generated per lane. + return RetTy->getNumElements() * 2; + } + } + break; + } default: break; } diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index dba384481f6a349274dbf9b307463869f0236bda..678c132e6a80a1bee5144dc13fd4a16789a578a2 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -203,7 +203,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost getAddressComputationCost(Type *Ty, ScalarEvolution *SE, diff --git a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp index 94584e20f5ab3fb2e45631db22faaca43c16a33e..11866f2dd18649003cef2840188a4c05b28d3c45 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64PostSelectOptimize.cpp @@ -199,10 +199,11 @@ bool AArch64PostSelectOptimize::optimizeNZCVDefs(MachineBasicBlock &MBB) { for (auto &II : instructionsWithoutDebug(MBB.rbegin(), MBB.rend())) { bool NZCVDead = LRU.available(AArch64::NZCV); - if (NZCVDead && II.definesRegister(AArch64::NZCV)) { + if (NZCVDead && II.definesRegister(AArch64::NZCV, /*TRI=*/nullptr)) { // The instruction defines NZCV, but NZCV is dead. unsigned NewOpc = getNonFlagSettingVariant(II.getOpcode()); - int DeadNZCVIdx = II.findRegisterDefOperandIdx(AArch64::NZCV); + int DeadNZCVIdx = + II.findRegisterDefOperandIdx(AArch64::NZCV, /*TRI=*/nullptr); if (DeadNZCVIdx != -1) { if (NewOpc) { // If there is an equivalent non-flag-setting op, we convert. diff --git a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp index abbf20257edcc039dc4c511c57043432cdb1c4e4..b4c5cde5fd888d10c8c38dfe27e9120f8b5187df 100644 --- a/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp +++ b/llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp @@ -146,8 +146,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, "ILP32 8 byte PC relative data " "relocation not supported (LP64 eqv: PREL64)"); return ELF::R_AARCH64_NONE; - } else - return ELF::R_AARCH64_PREL64; + } + return ELF::R_AARCH64_PREL64; case AArch64::fixup_aarch64_pcrel_adr_imm21: if (SymLoc != AArch64MCExpr::VK_ABS) Ctx.reportError(Fixup.getLoc(), @@ -162,9 +162,8 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, "invalid fixup for 32-bit pcrel ADRP instruction " "VK_ABS VK_NC"); return ELF::R_AARCH64_NONE; - } else { - return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC; } + return ELF::R_AARCH64_ADR_PREL_PG_HI21_NC; } if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) return R_CLS(ADR_GOT_PAGE); @@ -286,14 +285,12 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) return R_CLS(TLSLE_LDST32_TPREL_LO12_NC); if (SymLoc == AArch64MCExpr::VK_GOT && IsNC) { - if (IsILP32) { + if (IsILP32) return ELF::R_AARCH64_P32_LD32_GOT_LO12_NC; - } else { - Ctx.reportError(Fixup.getLoc(), - "LP64 4 byte unchecked GOT load/store relocation " - "not supported (ILP32 eqv: LD32_GOT_LO12_NC"); - return ELF::R_AARCH64_NONE; - } + Ctx.reportError(Fixup.getLoc(), + "LP64 4 byte unchecked GOT load/store relocation " + "not supported (ILP32 eqv: LD32_GOT_LO12_NC"); + return ELF::R_AARCH64_NONE; } if (SymLoc == AArch64MCExpr::VK_GOT && !IsNC) { if (IsILP32) { @@ -309,25 +306,20 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, return ELF::R_AARCH64_NONE; } if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { - if (IsILP32) { + if (IsILP32) return ELF::R_AARCH64_P32_TLSIE_LD32_GOTTPREL_LO12_NC; - } else { - Ctx.reportError(Fixup.getLoc(), - "LP64 32-bit load/store " - "relocation not supported (ILP32 eqv: " - "TLSIE_LD32_GOTTPREL_LO12_NC)"); - return ELF::R_AARCH64_NONE; - } + Ctx.reportError(Fixup.getLoc(), "LP64 32-bit load/store " + "relocation not supported (ILP32 eqv: " + "TLSIE_LD32_GOTTPREL_LO12_NC)"); + return ELF::R_AARCH64_NONE; } if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC) { - if (IsILP32) { + if (IsILP32) return ELF::R_AARCH64_P32_TLSDESC_LD32_LO12; - } else { - Ctx.reportError(Fixup.getLoc(), - "LP64 4 byte TLSDESC load/store relocation " - "not supported (ILP32 eqv: TLSDESC_LD64_LO12)"); - return ELF::R_AARCH64_NONE; - } + Ctx.reportError(Fixup.getLoc(), + "LP64 4 byte TLSDESC load/store relocation " + "not supported (ILP32 eqv: TLSDESC_LD64_LO12)"); + return ELF::R_AARCH64_NONE; } Ctx.reportError(Fixup.getLoc(), @@ -344,12 +336,11 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, if (AddressLoc == AArch64MCExpr::VK_LO15) return ELF::R_AARCH64_LD64_GOTPAGE_LO15; return ELF::R_AARCH64_LD64_GOT_LO12_NC; - } else { - Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " - "relocation not supported (LP64 eqv: " - "LD64_GOT_LO12_NC)"); - return ELF::R_AARCH64_NONE; } + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " + "relocation not supported (LP64 eqv: " + "LD64_GOT_LO12_NC)"); + return ELF::R_AARCH64_NONE; } if (SymLoc == AArch64MCExpr::VK_DTPREL && !IsNC) return R_CLS(TLSLD_LDST64_DTPREL_LO12); @@ -360,24 +351,20 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx, if (SymLoc == AArch64MCExpr::VK_TPREL && IsNC) return R_CLS(TLSLE_LDST64_TPREL_LO12_NC); if (SymLoc == AArch64MCExpr::VK_GOTTPREL && IsNC) { - if (!IsILP32) { + if (!IsILP32) return ELF::R_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC; - } else { - Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " - "relocation not supported (LP64 eqv: " - "TLSIE_LD64_GOTTPREL_LO12_NC)"); - return ELF::R_AARCH64_NONE; - } + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " + "relocation not supported (LP64 eqv: " + "TLSIE_LD64_GOTTPREL_LO12_NC)"); + return ELF::R_AARCH64_NONE; } if (SymLoc == AArch64MCExpr::VK_TLSDESC) { - if (!IsILP32) { + if (!IsILP32) return ELF::R_AARCH64_TLSDESC_LD64_LO12; - } else { - Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " - "relocation not supported (LP64 eqv: " - "TLSDESC_LD64_LO12)"); - return ELF::R_AARCH64_NONE; - } + Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store " + "relocation not supported (LP64 eqv: " + "TLSDESC_LD64_LO12)"); + return ELF::R_AARCH64_NONE; } Ctx.reportError(Fixup.getLoc(), "invalid fixup for 64-bit load/store instruction"); diff --git a/llvm/lib/Target/AMDGPU/AMDGPU.td b/llvm/lib/Target/AMDGPU/AMDGPU.td index 5c2c6d4b13c66975ad0b05af485fc44f01c1c48b..2b81f5d51032dd5ddb719bd19cc410e46b8d8663 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPU.td +++ b/llvm/lib/Target/AMDGPU/AMDGPU.td @@ -307,6 +307,12 @@ def FeatureMSAALoadDstSelBug : SubtargetFeature<"msaa-load-dst-sel-bug", "MSAA loads not honoring dst_sel bug" >; +def FeaturePrivEnabledTrap2NopBug : SubtargetFeature<"priv-enabled-trap2-nop-bug", + "HasPrivEnabledTrap2NopBug", + "true", + "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug" +>; + class SubtargetFeatureLDSBankCount : SubtargetFeature < "ldsbankcount"#Value, "LDSBankCount", @@ -1487,13 +1493,15 @@ def FeatureISAVersion11_Generic: FeatureSet< [FeatureMSAALoadDstSelBug, FeatureVALUTransUseHazard, FeatureUserSGPRInit16Bug, + FeaturePrivEnabledTrap2NopBug, FeatureRequiresCOV6])>; def FeatureISAVersion11_0_Common : FeatureSet< !listconcat(FeatureISAVersion11_Common.Features, [FeatureMSAALoadDstSelBug, FeatureVALUTransUseHazard, - FeatureMADIntraFwdBug])>; + FeatureMADIntraFwdBug, + FeaturePrivEnabledTrap2NopBug])>; def FeatureISAVersion11_0_0 : FeatureSet< !listconcat(FeatureISAVersion11_0_Common.Features, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index db69d50799e70b92932cfb1645d6aa20bb949167..f4a747784d1fd2ef1f34d72ad94e6c311916277d 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -5377,6 +5377,7 @@ const char* AMDGPUTargetLowering::getTargetNodeName(unsigned Opcode) const { NODE_NAME_CASE(RETURN_TO_EPILOG) NODE_NAME_CASE(ENDPGM) NODE_NAME_CASE(ENDPGM_TRAP) + NODE_NAME_CASE(SIMULATED_TRAP) NODE_NAME_CASE(DWORDADDR) NODE_NAME_CASE(FRACT) NODE_NAME_CASE(SETCC) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index f10a357125e56229379971fd88f20acea69a71d9..72661a8d29f8161e0bf683c9a751865cb6eab1be 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -407,6 +407,9 @@ enum NodeType : unsigned { // s_endpgm, but we may want to insert it in the middle of the block. ENDPGM_TRAP, + // "s_trap 2" equivalent on hardware that does not support it. + SIMULATED_TRAP, + // Return to a shader part's epilog code. RETURN_TO_EPILOG, diff --git a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td index 82f58ea38fd0a7221815b003795f6ed1af25b32b..702f6e67c552718e48705770d585c634a5846822 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/AMDGPUInstrInfo.td @@ -377,6 +377,8 @@ def AMDGPUendpgm : SDNode<"AMDGPUISD::ENDPGM", SDTNone, [SDNPHasChain, SDNPOptInGlue]>; def AMDGPUendpgm_trap : SDNode<"AMDGPUISD::ENDPGM_TRAP", SDTNone, [SDNPHasChain]>; +def AMDGPUsimulated_trap : SDNode<"AMDGPUISD::SIMULATED_TRAP", SDTNone, + [SDNPHasChain]>; def AMDGPUreturn_to_epilog : SDNode<"AMDGPUISD::RETURN_TO_EPILOG", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 780dfaae11ef3ed81a4f14ea61404dfb62ddeddc..6cd93abff1a42908af33ff80716669d0c463621f 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -4248,7 +4248,8 @@ bool AMDGPULegalizerInfo::loadInputValue( AMDGPU::isEntryFunctionCC(CC) && !MFI->hasWorkGroupIDZ() ? ~0u : 0xFFFFu); const ArgDescriptor WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); - if (ST.hasArchitectedSGPRs() && AMDGPU::isCompute(CC)) { + if (ST.hasArchitectedSGPRs() && + (AMDGPU::isCompute(CC) || CC == CallingConv::AMDGPU_Gfx)) { switch (ArgType) { case AMDGPUFunctionArgInfo::WORKGROUP_ID_X: Arg = &WorkGroupIDX; @@ -6724,8 +6725,18 @@ bool AMDGPULegalizerInfo::legalizeTrapHsaQueuePtr( return true; } -bool AMDGPULegalizerInfo::legalizeTrapHsa( - MachineInstr &MI, MachineRegisterInfo &MRI, MachineIRBuilder &B) const { +bool AMDGPULegalizerInfo::legalizeTrapHsa(MachineInstr &MI, + MachineRegisterInfo &MRI, + MachineIRBuilder &B) const { + // We need to simulate the 's_trap 2' instruction on targets that run in + // PRIV=1 (where it is treated as a nop). + if (ST.hasPrivEnabledTrap2NopBug()) { + ST.getInstrInfo()->insertSimulatedTrap(MRI, B.getMBB(), MI, + MI.getDebugLoc()); + MI.eraseFromParent(); + return true; + } + B.buildInstr(AMDGPU::S_TRAP) .addImm(static_cast(GCNSubtarget::TrapID::LLVMAMDHSATrap)); MI.eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h index 0dab3a982779435225ab02d5b6dc84727789fbe5..b423df17302ca20e2c87ac1b74b05ee609ce1358 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetTransformInfo.h @@ -155,7 +155,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind, diff --git a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp index 75766b11ca82299827dbd5ef36c93b9898c86af4..f0c111eaf0600cd816bf3a3036724c15e14f7e77 100644 --- a/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp +++ b/llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp @@ -241,7 +241,7 @@ GCNHazardRecognizer::getHazardType(SUnit *SU, int Stalls) { (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) || (ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) || (ST.hasReadM0LdsDirectHazard() && - MI->readsRegister(AMDGPU::LDS_DIRECT))) && + MI->readsRegister(AMDGPU::LDS_DIRECT, /*TRI=*/nullptr))) && checkReadM0Hazards(MI) > 0) return HazardType; @@ -381,7 +381,8 @@ unsigned GCNHazardRecognizer::PreEmitNoopsCommon(MachineInstr *MI) { MI->getOpcode() == AMDGPU::DS_READ_ADDTID_B32)) || (ST.hasReadM0SendMsgHazard() && isSendMsgTraceDataOrGDS(TII, *MI)) || (ST.hasReadM0LdsDmaHazard() && isLdsDma(*MI)) || - (ST.hasReadM0LdsDirectHazard() && MI->readsRegister(AMDGPU::LDS_DIRECT))) + (ST.hasReadM0LdsDirectHazard() && + MI->readsRegister(AMDGPU::LDS_DIRECT, /*TRI=*/nullptr))) return std::max(WaitStates, checkReadM0Hazards(MI)); if (SIInstrInfo::isMAI(*MI)) @@ -1161,7 +1162,7 @@ bool GCNHazardRecognizer::fixVMEMtoScalarWriteHazards(MachineInstr *MI) { for (const MachineOperand &Def : MI->defs()) { const MachineOperand *Op = - I.findRegisterUseOperand(Def.getReg(), false, TRI); + I.findRegisterUseOperand(Def.getReg(), TRI, false); if (!Op) continue; return true; diff --git a/llvm/lib/Target/AMDGPU/GCNSubtarget.h b/llvm/lib/Target/AMDGPU/GCNSubtarget.h index 2ca5ae306b11bedff5b81ac78952e7b9d6522409..be337e0b2192f297064d565c96d9bb25c63858e3 100644 --- a/llvm/lib/Target/AMDGPU/GCNSubtarget.h +++ b/llvm/lib/Target/AMDGPU/GCNSubtarget.h @@ -224,6 +224,7 @@ protected: bool HasImageStoreD16Bug = false; bool HasImageGather4D16Bug = false; bool HasMSAALoadDstSelBug = false; + bool HasPrivEnabledTrap2NopBug = false; bool Has1_5xVGPRs = false; bool HasMADIntraFwdBug = false; bool HasVOPDInsts = false; @@ -1032,6 +1033,8 @@ public: bool hasMSAALoadDstSelBug() const { return HasMSAALoadDstSelBug; } + bool hasPrivEnabledTrap2NopBug() const { return HasPrivEnabledTrap2NopBug; } + bool hasNSAEncoding() const { return HasNSAEncoding; } bool hasNonNSAEncoding() const { return getGeneration() < GFX12; } diff --git a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp index 7f874b245b8f4f4836e2f8c7668633fd061230b7..98e7359357891aaa8d56e27167679e7f95f66231 100644 --- a/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/R600InstrInfo.cpp @@ -207,11 +207,11 @@ bool R600InstrInfo::mustBeLastInClause(unsigned Opcode) const { } bool R600InstrInfo::usesAddressRegister(MachineInstr &MI) const { - return MI.findRegisterUseOperandIdx(R600::AR_X, false, &RI) != -1; + return MI.findRegisterUseOperandIdx(R600::AR_X, &RI, false) != -1; } bool R600InstrInfo::definesAddressRegister(MachineInstr &MI) const { - return MI.findRegisterDefOperandIdx(R600::AR_X, false, false, &RI) != -1; + return MI.findRegisterDefOperandIdx(R600::AR_X, &RI, false, false) != -1; } bool R600InstrInfo::readsLDSSrcReg(const MachineInstr &MI) const { diff --git a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp index 8b21c22b44971066d093a06c4c07df2633be4c66..a00ca625fc7390f7720fb66abc780b63a95024a2 100644 --- a/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp +++ b/llvm/lib/Target/AMDGPU/SIFixSGPRCopies.cpp @@ -947,8 +947,9 @@ void SIFixSGPRCopies::analyzeVGPRToSGPRCopy(MachineInstr* MI) { (Inst->isCopy() && Inst->getOperand(0).getReg() == AMDGPU::SCC)) { auto I = Inst->getIterator(); auto E = Inst->getParent()->end(); - while (++I != E && !I->findRegisterDefOperand(AMDGPU::SCC)) { - if (I->readsRegister(AMDGPU::SCC)) + while (++I != E && + !I->findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr)) { + if (I->readsRegister(AMDGPU::SCC, /*TRI=*/nullptr)) Users.push_back(&*I); } } else if (Inst->getNumExplicitDefs() != 0) { diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp index 17b6e0cb9c3b4547831855a48b017de4c1caa5a5..cb4efdc7cf657c6908110be7da7de2ecc21621fc 100644 --- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp @@ -2124,7 +2124,8 @@ SDValue SITargetLowering::getPreloadedValue(SelectionDAG &DAG, AMDGPU::isEntryFunctionCC(CC) && !MFI.hasWorkGroupIDZ() ? ~0u : 0xFFFFu); const ArgDescriptor WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::TTMP7, 0xFFFF0000u); - if (Subtarget->hasArchitectedSGPRs() && AMDGPU::isCompute(CC)) { + if (Subtarget->hasArchitectedSGPRs() && + (AMDGPU::isCompute(CC) || CC == CallingConv::AMDGPU_Gfx)) { switch (PVID) { case AMDGPUFunctionArgInfo::WORKGROUP_ID_X: Reg = &WorkGroupIDX; @@ -2798,7 +2799,9 @@ SDValue SITargetLowering::LowerFormalArguments( (void)UserSGPRInfo; if (!Subtarget->enableFlatScratch()) assert(!UserSGPRInfo.hasFlatScratchInit()); - if (CallConv != CallingConv::AMDGPU_CS || !Subtarget->hasArchitectedSGPRs()) + if ((CallConv != CallingConv::AMDGPU_CS && + CallConv != CallingConv::AMDGPU_Gfx) || + !Subtarget->hasArchitectedSGPRs()) assert(!Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() && !Info->hasWorkGroupIDZ()); } @@ -5402,6 +5405,14 @@ MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter( MI.eraseFromParent(); return SplitBB; } + case AMDGPU::SIMULATED_TRAP: { + assert(Subtarget->hasPrivEnabledTrap2NopBug()); + MachineRegisterInfo &MRI = BB->getParent()->getRegInfo(); + MachineBasicBlock *SplitBB = + TII->insertSimulatedTrap(MRI, *BB, MI, MI.getDebugLoc()); + MI.eraseFromParent(); + return SplitBB; + } default: if (TII->isImage(MI) || TII->isMUBUF(MI)) { if (!MI.mayStore()) @@ -6620,6 +6631,11 @@ SDValue SITargetLowering::lowerTrapHsa( SDLoc SL(Op); SDValue Chain = Op.getOperand(0); + // We need to simulate the 's_trap 2' instruction on targets that run in + // PRIV=1 (where it is treated as a nop). + if (Subtarget->hasPrivEnabledTrap2NopBug()) + return DAG.getNode(AMDGPUISD::SIMULATED_TRAP, SL, MVT::Other, Chain); + uint64_t TrapID = static_cast(GCNSubtarget::TrapID::LLVMAMDHSATrap); SDValue Ops[] = { Chain, diff --git a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp index 36de5b89af02809433c48945e0a960cdec4b1cd8..91a1c40dd8247dfc87ea0a061939b80fbe3a0afa 100644 --- a/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp +++ b/llvm/lib/Target/AMDGPU/SIInsertWaitcnts.cpp @@ -2252,12 +2252,12 @@ bool SIInsertWaitcnts::insertWaitcntInBlock(MachineFunction &MF, // Don't examine operands unless we need to track vccz correctness. if (ST->hasReadVCCZBug() || !ST->partialVCCWritesUpdateVCCZ()) { - if (Inst.definesRegister(AMDGPU::VCC_LO) || - Inst.definesRegister(AMDGPU::VCC_HI)) { + if (Inst.definesRegister(AMDGPU::VCC_LO, /*TRI=*/nullptr) || + Inst.definesRegister(AMDGPU::VCC_HI, /*TRI=*/nullptr)) { // Up to gfx9, writes to vcc_lo and vcc_hi don't update vccz. if (!ST->partialVCCWritesUpdateVCCZ()) VCCZCorrect = false; - } else if (Inst.definesRegister(AMDGPU::VCC)) { + } else if (Inst.definesRegister(AMDGPU::VCC, /*TRI=*/nullptr)) { // There is a hardware bug on CI/SI where SMRD instruction may corrupt // vccz bit, so when we detect that an instruction may read from a // corrupt vccz bit, we need to: diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index f4b21b7dfac391b6716e9f5e059393d0b3b8b680..e20fe1b716b6474cf464267e96bd79f171ce4f66 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -164,7 +164,7 @@ static bool resultDependsOnExec(const MachineInstr &MI) { break; case AMDGPU::S_AND_B32: case AMDGPU::S_AND_B64: - if (!Use.readsRegister(AMDGPU::EXEC)) + if (!Use.readsRegister(AMDGPU::EXEC, /*TRI=*/nullptr)) return true; break; default: @@ -2026,6 +2026,57 @@ void SIInstrInfo::insertReturn(MachineBasicBlock &MBB) const { } } +MachineBasicBlock *SIInstrInfo::insertSimulatedTrap(MachineRegisterInfo &MRI, + MachineBasicBlock &MBB, + MachineInstr &MI, + const DebugLoc &DL) const { + MachineFunction *MF = MBB.getParent(); + MachineBasicBlock *SplitBB = MBB.splitAt(MI, /*UpdateLiveIns=*/false); + MachineBasicBlock *HaltLoop = MF->CreateMachineBasicBlock(); + MF->push_back(HaltLoop); + + constexpr unsigned DoorbellIDMask = 0x3ff; + constexpr unsigned ECQueueWaveAbort = 0x400; + + // Start with a `s_trap 2`, if we're in PRIV=1 and we need the workaround this + // will be a nop. + BuildMI(MBB, MI, DL, get(AMDGPU::S_TRAP)) + .addImm(static_cast(GCNSubtarget::TrapID::LLVMAMDHSATrap)); + Register DoorbellReg = MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); + BuildMI(MBB, MI, DL, get(AMDGPU::S_SENDMSG_RTN_B32), DoorbellReg) + .addImm(AMDGPU::SendMsg::ID_RTN_GET_DOORBELL); + BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::TTMP2) + .addUse(AMDGPU::M0); + Register DoorbellRegMasked = + MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); + BuildMI(MBB, MI, DL, get(AMDGPU::S_AND_B32), DoorbellRegMasked) + .addUse(DoorbellReg) + .addImm(DoorbellIDMask); + Register SetWaveAbortBit = + MRI.createVirtualRegister(&AMDGPU::SReg_32RegClass); + BuildMI(MBB, MI, DL, get(AMDGPU::S_OR_B32), SetWaveAbortBit) + .addUse(DoorbellRegMasked) + .addImm(ECQueueWaveAbort); + BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::M0) + .addUse(SetWaveAbortBit); + BuildMI(MBB, MI, DL, get(AMDGPU::S_SENDMSG)) + .addImm(AMDGPU::SendMsg::ID_INTERRUPT); + BuildMI(MBB, MI, DL, get(AMDGPU::S_MOV_B32), AMDGPU::M0) + .addUse(AMDGPU::TTMP2); + BuildMI(MBB, MI, DL, get(AMDGPU::S_BRANCH)).addMBB(HaltLoop); + + BuildMI(*HaltLoop, HaltLoop->end(), DL, get(AMDGPU::S_SETHALT)).addImm(5); + BuildMI(*HaltLoop, HaltLoop->end(), DL, get(AMDGPU::S_BRANCH)) + .addMBB(HaltLoop); + + if (SplitBB != &MBB) + MBB.removeSuccessor(SplitBB); + MBB.addSuccessor(HaltLoop); + HaltLoop->addSuccessor(HaltLoop); + + return SplitBB; +} + unsigned SIInstrInfo::getNumWaitStates(const MachineInstr &MI) { switch (MI.getOpcode()) { default: @@ -6689,7 +6740,7 @@ SIInstrInfo::legalizeOperands(MachineInstr &MI, // Also include following copies of the return value ++End; while (End != MBB.end() && End->isCopy() && End->getOperand(1).isReg() && - MI.definesRegister(End->getOperand(1).getReg())) + MI.definesRegister(End->getOperand(1).getReg(), /*TRI=*/nullptr)) ++End; CreatedBB = loadMBUFScalarOperandsFromVGPR(*this, MI, {Dest}, MDT, Start, End); @@ -7257,7 +7308,7 @@ void SIInstrInfo::moveToVALUImpl(SIInstrWorklist &Worklist, .add(Inst.getOperand(1)); } legalizeOperands(*NewInstr, MDT); - int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC); + int SCCIdx = Inst.findRegisterDefOperandIdx(AMDGPU::SCC, /*TRI=*/nullptr); MachineOperand SCCOp = Inst.getOperand(SCCIdx); addSCCDefUsersToVALUWorklist(SCCOp, Inst, Worklist, CondReg); Inst.eraseFromParent(); @@ -7523,7 +7574,7 @@ void SIInstrInfo::lowerSelect(SIInstrWorklist &Worklist, MachineInstr &Inst, for (MachineInstr &CandI : make_range(std::next(MachineBasicBlock::reverse_iterator(Inst)), Inst.getParent()->rend())) { - if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != + if (CandI.findRegisterDefOperandIdx(AMDGPU::SCC, &RI, false, false) != -1) { if (CandI.isCopy() && CandI.getOperand(0).getReg() == AMDGPU::SCC) { BuildMI(MBB, MII, DL, get(AMDGPU::COPY), NewCondReg) @@ -8338,7 +8389,7 @@ void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op, make_range(std::next(MachineBasicBlock::iterator(SCCDefInst)), SCCDefInst.getParent()->end())) { // Check if SCC is used first. - int SCCIdx = MI.findRegisterUseOperandIdx(AMDGPU::SCC, false, &RI); + int SCCIdx = MI.findRegisterUseOperandIdx(AMDGPU::SCC, &RI, false); if (SCCIdx != -1) { if (MI.isCopy()) { MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo(); @@ -8355,7 +8406,7 @@ void SIInstrInfo::addSCCDefUsersToVALUWorklist(MachineOperand &Op, } } // Exit if we find another SCC def. - if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, false, false, &RI) != -1) + if (MI.findRegisterDefOperandIdx(AMDGPU::SCC, &RI, false, false) != -1) break; } for (auto &Copy : CopyToDelete) @@ -9408,7 +9459,7 @@ MachineInstr *SIInstrInfo::createPHIDestinationCopy( auto Cur = MBB.begin(); if (Cur != MBB.end()) do { - if (!Cur->isPHI() && Cur->readsRegister(Dst)) + if (!Cur->isPHI() && Cur->readsRegister(Dst, /*TRI=*/nullptr)) return BuildMI(MBB, Cur, DL, get(TargetOpcode::COPY), Dst).addReg(Src); ++Cur; } while (Cur != MBB.end() && Cur != LastPHIIt); @@ -9424,7 +9475,7 @@ MachineInstr *SIInstrInfo::createPHISourceCopy( (InsPt->getOpcode() == AMDGPU::SI_IF || InsPt->getOpcode() == AMDGPU::SI_ELSE || InsPt->getOpcode() == AMDGPU::SI_IF_BREAK) && - InsPt->definesRegister(Src)) { + InsPt->definesRegister(Src, /*TRI=*/nullptr)) { InsPt++; return BuildMI(MBB, InsPt, DL, get(ST.isWave32() ? AMDGPU::S_MOV_B32_term @@ -9796,7 +9847,8 @@ bool SIInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, return false; } - MachineOperand *SccDef = Def->findRegisterDefOperand(AMDGPU::SCC); + MachineOperand *SccDef = + Def->findRegisterDefOperand(AMDGPU::SCC, /*TRI=*/nullptr); SccDef->setIsDead(false); CmpInstr.eraseFromParent(); diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.h b/llvm/lib/Target/AMDGPU/SIInstrInfo.h index 4c5978cdc6665c68c912589878bf2b4fbed320a5..b314b9b2fb5135580db385a8abf638aec2aecd38 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.h +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.h @@ -1194,6 +1194,15 @@ public: unsigned Quantity) const override; void insertReturn(MachineBasicBlock &MBB) const; + + /// Build instructions that simulate the behavior of a `s_trap 2` instructions + /// for hardware (namely, gfx11) that runs in PRIV=1 mode. There, s_trap is + /// interpreted as a nop. + MachineBasicBlock *insertSimulatedTrap(MachineRegisterInfo &MRI, + MachineBasicBlock &MBB, + MachineInstr &MI, + const DebugLoc &DL) const; + /// Return the number of wait states that result from executing this /// instruction. static unsigned getNumWaitStates(const MachineInstr &MI); diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td index d6d49889656bbc45a7658907785953a640041094..cca8d96f29c0fc96d90b7781a20eb321f2debc33 100644 --- a/llvm/lib/Target/AMDGPU/SIInstructions.td +++ b/llvm/lib/Target/AMDGPU/SIInstructions.td @@ -106,6 +106,12 @@ def ENDPGM_TRAP : SPseudoInstSI< let usesCustomInserter = 1; } +def SIMULATED_TRAP : SPseudoInstSI<(outs), (ins), [(AMDGPUsimulated_trap)], + "SIMULATED_TRAP"> { + let hasSideEffects = 1; + let usesCustomInserter = 1; +} + def ATOMIC_FENCE : SPseudoInstSI< (outs), (ins i32imm:$ordering, i32imm:$scope), [(atomic_fence (i32 timm:$ordering), (i32 timm:$scope))], diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index 12433dc83c4892e89c29eb9f90b25fbe03302ac2..bf4a501cc3159d34cbf25e89a692d22b1ba7d04e 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -110,7 +110,8 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, } if (!AMDGPU::isGraphics(CC) || - (CC == CallingConv::AMDGPU_CS && ST.hasArchitectedSGPRs())) { + ((CC == CallingConv::AMDGPU_CS || CC == CallingConv::AMDGPU_CS) && + ST.hasArchitectedSGPRs())) { if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x")) WorkGroupIDX = true; diff --git a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp index d2a5eb89da129cbc90885c324ea2bbfa6157b089..c91d241f81abcc795c9d3ce1792067c75ce99734 100644 --- a/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp +++ b/llvm/lib/Target/AMDGPU/SIOptimizeExecMaskingPreRA.cpp @@ -456,7 +456,8 @@ bool SIOptimizeExecMaskingPreRA::runOnMachineFunction(MachineFunction &MF) { Register SavedExec = I->getOperand(0).getReg(); if (SavedExec.isVirtual() && MRI->hasOneNonDBGUse(SavedExec)) { MachineInstr *SingleExecUser = &*MRI->use_instr_nodbg_begin(SavedExec); - int Idx = SingleExecUser->findRegisterUseOperandIdx(SavedExec); + int Idx = SingleExecUser->findRegisterUseOperandIdx(SavedExec, + /*TRI=*/nullptr); assert(Idx != -1); if (SingleExecUser->getParent() == I->getParent() && !SingleExecUser->getOperand(Idx).isImplicit() && diff --git a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp index 82da53d0c0ebdd4b07a6f63df382d4bd556dd5b2..875bccb208c846166f27636c0fe9feb1c109b42a 100644 --- a/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp +++ b/llvm/lib/Target/AMDGPU/SIPreEmitPeephole.cpp @@ -171,7 +171,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const { if (A->getOpcode() == AndN2) MaskValue = ~MaskValue; - if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC)) { + if (!ReadsCond && A->registerDefIsDead(AMDGPU::SCC, /*TRI=*/nullptr)) { if (!MI.killsRegister(CondReg, TRI)) { // Replace AND with MOV if (MaskValue == 0) { @@ -235,7 +235,7 @@ bool SIPreEmitPeephole::optimizeVccBranch(MachineInstr &MI) const { TII->get(IsVCCZ ? AMDGPU::S_CBRANCH_EXECZ : AMDGPU::S_CBRANCH_EXECNZ)); } - MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, false /*Kill*/, TRI)); + MI.removeOperand(MI.findRegisterUseOperandIdx(CondReg, TRI, false /*Kill*/)); MI.addImplicitDefUseOperands(*MBB.getParent()); return true; diff --git a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp index acb54fd10b90dc9b29f0a0f14621e2eb7741126b..ddb5f719356855d42403e8f4a658ec05634b4eba 100644 --- a/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp @@ -2366,8 +2366,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, return false; } - bool NeedSaveSCC = - RS->isRegUsed(AMDGPU::SCC) && !MI->definesRegister(AMDGPU::SCC); + bool NeedSaveSCC = RS->isRegUsed(AMDGPU::SCC) && + !MI->definesRegister(AMDGPU::SCC, /*TRI=*/nullptr); Register TmpSReg = UseSGPR ? TmpReg @@ -2409,7 +2409,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, if (TmpSReg == FrameReg) { // Undo frame register modification. - if (NeedSaveSCC && !MI->registerDefIsDead(AMDGPU::SCC)) { + if (NeedSaveSCC && + !MI->registerDefIsDead(AMDGPU::SCC, /*TRI=*/nullptr)) { MachineBasicBlock::iterator I = BuildMI(*MBB, std::next(MI), DL, TII->get(AMDGPU::S_ADDC_U32), TmpSReg) @@ -2439,8 +2440,8 @@ bool SIRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator MI, // Convert to a swizzled stack address by scaling by the wave size. // In an entry function/kernel the offset is already swizzled. bool IsSALU = isSGPRClass(TII->getOpRegClass(*MI, FIOperandNum)); - bool LiveSCC = - RS->isRegUsed(AMDGPU::SCC) && !MI->definesRegister(AMDGPU::SCC); + bool LiveSCC = RS->isRegUsed(AMDGPU::SCC) && + !MI->definesRegister(AMDGPU::SCC, /*TRI=*/nullptr); const TargetRegisterClass *RC = IsSALU && !LiveSCC ? &AMDGPU::SReg_32RegClass : &AMDGPU::VGPR_32RegClass; diff --git a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp index 3c6f6ddfd89d0d16ff222c4ce2919582ff6004b6..647fae904d393dabbb0f0b4a70d1ef86df531f57 100644 --- a/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp +++ b/llvm/lib/Target/AMDGPU/SIShrinkInstructions.cpp @@ -1014,7 +1014,7 @@ bool SIShrinkInstructions::runOnMachineFunction(MachineFunction &MF) { // Copy deadness from the old explicit vcc def to the new implicit def. if (SDst && SDst->isDead()) - Inst32->findRegisterDefOperand(VCCReg)->setIsDead(); + Inst32->findRegisterDefOperand(VCCReg, /*TRI=*/nullptr)->setIsDead(); MI.eraseFromParent(); foldImmediates(*Inst32); diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp index 5e6c34992930be8b22cfcabcc746c10e6bc72706..ea8109bbee9aed22d3ffc561b6d6afd4397840a9 100644 --- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp +++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp @@ -1525,10 +1525,10 @@ void SIWholeQuadMode::lowerCopyInstrs() { MI->getOperand(0).setIsEarlyClobber(false); LIS->createAndComputeVirtRegInterval(Reg); } - int Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC); + int Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC, /*TRI=*/nullptr); while (Index >= 0) { MI->removeOperand(Index); - Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC); + Index = MI->findRegisterUseOperandIdx(AMDGPU::EXEC, /*TRI=*/nullptr); } MI->setDesc(TII->get(AMDGPU::COPY)); LLVM_DEBUG(dbgs() << " -> " << *MI); diff --git a/llvm/lib/Target/ARM/A15SDOptimizer.cpp b/llvm/lib/Target/ARM/A15SDOptimizer.cpp index 3543cefeb399de26728f91eaf433171ff5446176..be87707a297d25341665e279db94f38122494081 100644 --- a/llvm/lib/Target/ARM/A15SDOptimizer.cpp +++ b/llvm/lib/Target/ARM/A15SDOptimizer.cpp @@ -156,7 +156,7 @@ unsigned A15SDOptimizer::getPrefSPRLane(unsigned SReg) { MachineInstr *MI = MRI->getVRegDef(SReg); if (!MI) return ARM::ssub_0; - MachineOperand *MO = MI->findRegisterDefOperand(SReg); + MachineOperand *MO = MI->findRegisterDefOperand(SReg, /*TRI=*/nullptr); if (!MO) return ARM::ssub_0; assert(MO->isReg() && "Non-register operand found!"); @@ -192,7 +192,7 @@ void A15SDOptimizer::eraseInstrWithNoUses(MachineInstr *MI) { Register Reg = MO.getReg(); if (!Reg.isVirtual()) continue; - MachineOperand *Op = MI->findRegisterDefOperand(Reg); + MachineOperand *Op = MI->findRegisterDefOperand(Reg, /*TRI=*/nullptr); if (!Op) continue; diff --git a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp index 5d0468948dfb6172afed64fd3626d9f6eb3795f5..8f873bee484acc7679304f365cc4e836c27753dd 100644 --- a/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp +++ b/llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp @@ -326,7 +326,7 @@ ARMBaseInstrInfo::convertToThreeAddress(MachineInstr &MI, LiveVariables *LV, for (unsigned j = 0; j < 2; ++j) { // Look at the two new MI's in reverse order. MachineInstr *NewMI = NewMIs[j]; - if (!NewMI->readsRegister(Reg)) + if (!NewMI->readsRegister(Reg, /*TRI=*/nullptr)) continue; LV->addVirtualRegisterKilled(Reg, *NewMI); if (VI.removeKill(MI)) @@ -1732,7 +1732,7 @@ bool ARMBaseInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { // Get rid of the old implicit-def of DstRegD. Leave it if it defines a Q-reg // or some other super-register. - int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD); + int ImpDefIdx = MI.findRegisterDefOperandIdx(DstRegD, /*TRI=*/nullptr); if (ImpDefIdx != -1) MI.removeOperand(ImpDefIdx); @@ -2085,7 +2085,7 @@ bool ARMBaseInstrInfo::isSchedulingBoundary(const MachineInstr &MI, // Calls don't actually change the stack pointer, even if they have imp-defs. // No ARM calling conventions change the stack pointer. (X86 calling // conventions sometimes do). - if (!MI.isCall() && MI.definesRegister(ARM::SP)) + if (!MI.isCall() && MI.definesRegister(ARM::SP, /*TRI=*/nullptr)) return true; return false; @@ -4137,7 +4137,7 @@ static const MachineInstr *getBundledDefMI(const TargetRegisterInfo *TRI, int Idx = -1; while (II->isInsideBundle()) { - Idx = II->findRegisterDefOperandIdx(Reg, false, true, TRI); + Idx = II->findRegisterDefOperandIdx(Reg, TRI, false, true); if (Idx != -1) break; --II; @@ -4161,7 +4161,7 @@ static const MachineInstr *getBundledUseMI(const TargetRegisterInfo *TRI, // FIXME: This doesn't properly handle multiple uses. int Idx = -1; while (II != E && II->isInsideBundle()) { - Idx = II->findRegisterUseOperandIdx(Reg, false, TRI); + Idx = II->findRegisterUseOperandIdx(Reg, TRI, false); if (Idx != -1) break; if (II->getOpcode() != ARM::t2IT) @@ -5361,7 +5361,7 @@ unsigned ARMBaseInstrInfo::getPartialRegUpdateClearance( case ARM::VMOVv2i32: case ARM::VMOVv2f32: case ARM::VMOVv1i64: - UseOp = MI.findRegisterUseOperandIdx(Reg, false, TRI); + UseOp = MI.findRegisterUseOperandIdx(Reg, TRI, false); break; // Explicitly reads the dependency. @@ -6092,7 +6092,7 @@ ARMBaseInstrInfo::getOutliningCandidateInfo( bool ARMBaseInstrInfo::checkAndUpdateStackOffset(MachineInstr *MI, int64_t Fixup, bool Updt) const { - int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP); + int SPIdx = MI->findRegisterUseOperandIdx(ARM::SP, /*TRI=*/nullptr); unsigned AddrMode = (MI->getDesc().TSFlags & ARMII::AddrModeMask); if (SPIdx < 0) // No SP operand diff --git a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp index 7a3ba5870bc6dfd89b807220e39c956f2a08b142..9579053943f9f004d401e9137ddd0272ef8d4a92 100644 --- a/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp +++ b/llvm/lib/Target/ARM/ARMConstantIslandPass.cpp @@ -1937,7 +1937,7 @@ bool ARMConstantIslands::optimizeThumb2Branches() { // If the conditional branch doesn't kill CPSR, then CPSR can be liveout // so this transformation is not safe. - if (!Br.MI->killsRegister(ARM::CPSR)) + if (!Br.MI->killsRegister(ARM::CPSR, /*TRI=*/nullptr)) return false; Register PredReg; diff --git a/llvm/lib/Target/ARM/ARMFrameLowering.cpp b/llvm/lib/Target/ARM/ARMFrameLowering.cpp index 9b54dd4e4e618d75255bf91d0429f0cf18d620da..a332f743f495b8a3357a630f6d06003ac9c59b43 100644 --- a/llvm/lib/Target/ARM/ARMFrameLowering.cpp +++ b/llvm/lib/Target/ARM/ARMFrameLowering.cpp @@ -1873,7 +1873,7 @@ skipAlignedDPRCS2Spills(MachineBasicBlock::iterator MI, case 1: case 2: case 4: - assert(MI->killsRegister(ARM::R4) && "Missed kill flag"); + assert(MI->killsRegister(ARM::R4, /*TRI=*/nullptr) && "Missed kill flag"); ++MI; } return MI; diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index 3907131be6d13128b30c926f09a767c4a247efb4..d0e9f61c0bd1228ee717cdd9fab23403e021e89f 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -11796,9 +11796,9 @@ static bool checkAndUpdateCPSRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock::iterator miI(std::next(SelectItr)); for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { const MachineInstr& mi = *miI; - if (mi.readsRegister(ARM::CPSR)) + if (mi.readsRegister(ARM::CPSR, /*TRI=*/nullptr)) return false; - if (mi.definesRegister(ARM::CPSR)) + if (mi.definesRegister(ARM::CPSR, /*TRI=*/nullptr)) break; // Should have kill-flag - update below. } @@ -12157,7 +12157,7 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, // Check whether CPSR is live past the tMOVCCr_pseudo. const TargetRegisterInfo *TRI = Subtarget->getRegisterInfo(); - if (!MI.killsRegister(ARM::CPSR) && + if (!MI.killsRegister(ARM::CPSR, /*TRI=*/nullptr) && !checkAndUpdateCPSRKill(MI, thisMBB, TRI)) { copy0MBB->addLiveIn(ARM::CPSR); sinkMBB->addLiveIn(ARM::CPSR); diff --git a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp index 469340784284cb69e02dd5b1299a0633ce841b8c..4a5b672f862bec194f44dcc50a56f0e278f184c6 100644 --- a/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp +++ b/llvm/lib/Target/ARM/ARMLoadStoreOptimizer.cpp @@ -495,7 +495,7 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, bool InsertSub = false; unsigned Opc = MBBI->getOpcode(); - if (MBBI->readsRegister(Base)) { + if (MBBI->readsRegister(Base, /*TRI=*/nullptr)) { int Offset; bool IsLoad = Opc == ARM::tLDRi || Opc == ARM::tLDRHi || Opc == ARM::tLDRBi; @@ -560,7 +560,8 @@ void ARMLoadStoreOpt::UpdateBaseRegUses(MachineBasicBlock &MBB, return; } - if (MBBI->killsRegister(Base) || MBBI->definesRegister(Base)) + if (MBBI->killsRegister(Base, /*TRI=*/nullptr) || + MBBI->definesRegister(Base, /*TRI=*/nullptr)) // Register got killed. Stop updating. return; } @@ -888,7 +889,7 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) { if (is_contained(ImpDefs, DefReg)) continue; // We can ignore cases where the super-reg is read and written. - if (MI->readsRegister(DefReg)) + if (MI->readsRegister(DefReg, /*TRI=*/nullptr)) continue; ImpDefs.push_back(DefReg); } @@ -903,7 +904,7 @@ MachineInstr *ARMLoadStoreOpt::MergeOpsUpdate(const MergeCandidate &Cand) { MachineBasicBlock &MBB = *LatestMI->getParent(); unsigned Offset = getMemoryOpOffset(*First); Register Base = getLoadStoreBaseOp(*First).getReg(); - bool BaseKill = LatestMI->killsRegister(Base); + bool BaseKill = LatestMI->killsRegister(Base, /*TRI=*/nullptr); Register PredReg; ARMCC::CondCodes Pred = getInstrPredicate(*First, PredReg); DebugLoc DL = First->getDebugLoc(); @@ -2076,7 +2077,8 @@ bool ARMLoadStoreOpt::CombineMovBx(MachineBasicBlock &MBB) { MachineBasicBlock::iterator Prev = MBBI; --Prev; - if (Prev->getOpcode() != ARM::tMOVr || !Prev->definesRegister(ARM::LR)) + if (Prev->getOpcode() != ARM::tMOVr || + !Prev->definesRegister(ARM::LR, /*TRI=*/nullptr)) return false; for (auto Use : Prev->uses()) @@ -3176,7 +3178,7 @@ bool ARMPreAllocLoadStoreOpt::DistributeIncrements(Register Base) { if (PrePostInc || BaseAccess->getParent() != Increment->getParent()) return false; Register PredReg; - if (Increment->definesRegister(ARM::CPSR) || + if (Increment->definesRegister(ARM::CPSR, /*TRI=*/nullptr) || getInstrPredicate(*Increment, PredReg) != ARMCC::AL) return false; diff --git a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp index ea5dd5427ce72015fa7bcc338eb8e528fa729264..91a36898aecba13a81133725b7297331d1bd5fbd 100644 --- a/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp +++ b/llvm/lib/Target/ARM/ARMLowOverheadLoops.cpp @@ -91,11 +91,11 @@ static bool isVectorPredicated(MachineInstr *MI) { } static bool isVectorPredicate(MachineInstr *MI) { - return MI->findRegisterDefOperandIdx(ARM::VPR) != -1; + return MI->findRegisterDefOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; } static bool hasVPRUse(MachineInstr &MI) { - return MI.findRegisterUseOperandIdx(ARM::VPR) != -1; + return MI.findRegisterUseOperandIdx(ARM::VPR, /*TRI=*/nullptr) != -1; } static bool isDomainMVE(MachineInstr *MI) { @@ -564,7 +564,8 @@ static bool TryRemove(MachineInstr *MI, ReachingDefAnalysis &RDA, SmallPtrSet ModifiedITs; SmallPtrSet RemoveITs; for (auto *Dead : Killed) { - if (MachineOperand *MO = Dead->findRegisterUseOperand(ARM::ITSTATE)) { + if (MachineOperand *MO = + Dead->findRegisterUseOperand(ARM::ITSTATE, /*TRI=*/nullptr)) { MachineInstr *IT = RDA.getMIOperand(Dead, *MO); RemoveITs.insert(IT); auto &CurrentBlock = ITBlocks[IT]; diff --git a/llvm/lib/Target/ARM/ARMSubtarget.cpp b/llvm/lib/Target/ARM/ARMSubtarget.cpp index 04ba20a17187b44967ea2472e4f1c12941eadbc8..5e13d8fabe0485dbb7af8ebc9a5038f629ac9c70 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.cpp +++ b/llvm/lib/Target/ARM/ARMSubtarget.cpp @@ -293,13 +293,11 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case CortexA78C: case CortexA710: case CortexR4: - case CortexR4F: case CortexR5: case CortexR7: case CortexM3: case CortexM7: case CortexR52: - case CortexM52: case CortexX1: case CortexX1C: break; @@ -314,8 +312,6 @@ void ARMSubtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { case Krait: PreISelOperandLatencyAdjustment = 1; break; - case NeoverseN1: - case NeoverseN2: case NeoverseV1: break; case Swift: diff --git a/llvm/lib/Target/ARM/ARMSubtarget.h b/llvm/lib/Target/ARM/ARMSubtarget.h index 497ae160fde281e6e1cc5f9d0a755c5e9e37b03a..00239ff94b7ba5501f462b1dd410c2687087bba4 100644 --- a/llvm/lib/Target/ARM/ARMSubtarget.h +++ b/llvm/lib/Target/ARM/ARMSubtarget.h @@ -49,45 +49,9 @@ class ARMSubtarget : public ARMGenSubtargetInfo { protected: enum ARMProcFamilyEnum { Others, - - CortexA12, - CortexA15, - CortexA17, - CortexA32, - CortexA35, - CortexA5, - CortexA53, - CortexA55, - CortexA57, - CortexA7, - CortexA72, - CortexA73, - CortexA75, - CortexA76, - CortexA77, - CortexA78, - CortexA78AE, - CortexA78C, - CortexA710, - CortexA8, - CortexA9, - CortexM3, - CortexM7, - CortexM52, - CortexR4, - CortexR4F, - CortexR5, - CortexR52, - CortexR7, - CortexX1, - CortexX1C, - Exynos, - Krait, - Kryo, - NeoverseN1, - NeoverseN2, - NeoverseV1, - Swift +#define ARM_PROCESSOR_FAMILY(ENUM) ENUM, +#include "llvm/TargetParser/ARMTargetParserDef.inc" +#undef ARM_PROCESSOR_FAMILY }; enum ARMProcClassEnum { None, @@ -97,43 +61,9 @@ protected: RClass }; enum ARMArchEnum { - ARMv4, - ARMv4t, - ARMv5, - ARMv5t, - ARMv5te, - ARMv5tej, - ARMv6, - ARMv6k, - ARMv6kz, - ARMv6m, - ARMv6sm, - ARMv6t2, - ARMv7a, - ARMv7em, - ARMv7m, - ARMv7r, - ARMv7ve, - ARMv81a, - ARMv82a, - ARMv83a, - ARMv84a, - ARMv85a, - ARMv86a, - ARMv87a, - ARMv88a, - ARMv89a, - ARMv8a, - ARMv8mBaseline, - ARMv8mMainline, - ARMv8r, - ARMv81mMainline, - ARMv9a, - ARMv91a, - ARMv92a, - ARMv93a, - ARMv94a, - ARMv95a, +#define ARM_ARCHITECTURE(ENUM) ENUM, +#include "llvm/TargetParser/ARMTargetParserDef.inc" +#undef ARM_ARCHITECTURE }; public: diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index 04b32194f806f651577b4283a6ff7771f0ec74a8..58eab45b9641f57e1af2423bb0c60c5bcbdbd895 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -256,7 +256,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost diff --git a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp index e8d2cba7ee556fc1087e683bbfa00b8187a3e5f7..c9bbc41ac13bacbb098e2c32c94eef664e5455fa 100644 --- a/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp +++ b/llvm/lib/Target/ARM/MVETPAndVPTOptimisationsPass.cpp @@ -667,17 +667,18 @@ static bool MoveVPNOTBeforeFirstUser(MachineBasicBlock &MBB, MachineOperand *VPNOTOperandKiller = nullptr; for (; Iter != MBB.end(); ++Iter) { if (MachineOperand *MO = - Iter->findRegisterUseOperand(VPNOTOperand, /*isKill*/ true)) { + Iter->findRegisterUseOperand(VPNOTOperand, /*TRI=*/nullptr, + /*isKill*/ true)) { // If we find the operand that kills the VPNOTOperand's result, save it. VPNOTOperandKiller = MO; } - if (Iter->findRegisterUseOperandIdx(Reg) != -1) { + if (Iter->findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != -1) { MustMove = true; continue; } - if (Iter->findRegisterUseOperandIdx(VPNOTResult) == -1) + if (Iter->findRegisterUseOperandIdx(VPNOTResult, /*TRI=*/nullptr) == -1) continue; HasUser = true; @@ -731,7 +732,7 @@ bool MVETPAndVPTOptimisations::ReduceOldVCCRValueUses(MachineBasicBlock &MBB) { // If we already have a VCCRValue, and this is a VPNOT on VCCRValue, we've // found what we were looking for. if (VCCRValue && Iter->getOpcode() == ARM::MVE_VPNOT && - Iter->findRegisterUseOperandIdx(VCCRValue) != -1) { + Iter->findRegisterUseOperandIdx(VCCRValue, /*TRI=*/nullptr) != -1) { // Move the VPNOT closer to its first user if needed, and ignore if it // has no users. if (!MoveVPNOTBeforeFirstUser(MBB, Iter, VCCRValue)) @@ -763,7 +764,8 @@ bool MVETPAndVPTOptimisations::ReduceOldVCCRValueUses(MachineBasicBlock &MBB) { for (; Iter != End; ++Iter) { bool IsInteresting = false; - if (MachineOperand *MO = Iter->findRegisterUseOperand(VCCRValue)) { + if (MachineOperand *MO = + Iter->findRegisterUseOperand(VCCRValue, /*TRI=*/nullptr)) { IsInteresting = true; // - If the instruction is a VPNOT, it can be removed, and we can just @@ -794,8 +796,8 @@ bool MVETPAndVPTOptimisations::ReduceOldVCCRValueUses(MachineBasicBlock &MBB) { } else { // If the instr uses OppositeVCCRValue, make it use LastVPNOTResult // instead as they contain the same value. - if (MachineOperand *MO = - Iter->findRegisterUseOperand(OppositeVCCRValue)) { + if (MachineOperand *MO = Iter->findRegisterUseOperand( + OppositeVCCRValue, /*TRI=*/nullptr)) { IsInteresting = true; // This is pointless if LastVPNOTResult == OppositeVCCRValue. @@ -855,8 +857,9 @@ bool MVETPAndVPTOptimisations::ReplaceVCMPsByVPNOTs(MachineBasicBlock &MBB) { for (MachineInstr &Instr : MBB.instrs()) { if (PrevVCMP) { - if (MachineOperand *MO = Instr.findRegisterUseOperand( - PrevVCMP->getOperand(0).getReg(), /*isKill*/ true)) { + if (MachineOperand *MO = + Instr.findRegisterUseOperand(PrevVCMP->getOperand(0).getReg(), + /*TRI=*/nullptr, /*isKill*/ true)) { // If we come accross the instr that kills PrevVCMP's result, record it // so we can remove the kill flag later if we need to. PrevVCMPResultKiller = MO; diff --git a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp index d2b0bcf1250fe78b3b7aacc5c94f7939f370ee5b..197eca421e21d32336e0986ebdd35b53a030c161 100644 --- a/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp +++ b/llvm/lib/Target/ARM/MVEVPTBlockPass.cpp @@ -131,7 +131,8 @@ static bool StepOverPredicatedInstrs(MachineBasicBlock::instr_iterator &Iter, static bool IsVPRDefinedOrKilledByBlock(MachineBasicBlock::iterator Iter, MachineBasicBlock::iterator End) { for (; Iter != End; ++Iter) - if (Iter->definesRegister(ARM::VPR) || Iter->killsRegister(ARM::VPR)) + if (Iter->definesRegister(ARM::VPR, /*TRI=*/nullptr) || + Iter->killsRegister(ARM::VPR, /*TRI=*/nullptr)) return true; return false; } diff --git a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp index 2945b5eaae3e3fd1675d57b2a4a93376204a1141..147bf751945db1cecff1830d4b6f324ef0761154 100644 --- a/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp +++ b/llvm/lib/Target/ARM/Thumb2ITBlockPass.cpp @@ -269,7 +269,8 @@ bool Thumb2ITBlock::InsertITInstructions(MachineBasicBlock &MBB) { MIB.addImm(Mask); // Last instruction in IT block kills ITSTATE. - LastITMI->findRegisterUseOperand(ARM::ITSTATE)->setIsKill(); + LastITMI->findRegisterUseOperand(ARM::ITSTATE, /*TRI=*/nullptr) + ->setIsKill(); // Finalize the bundle. finalizeBundle(MBB, InsertPos.getInstrIterator(), diff --git a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp index fc2834cb0b45c7d6812f7a3b9da2af9839f3ae3f..8ef5c3d9d6bad359d2ecb876557317fb09a6029e 100644 --- a/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp +++ b/llvm/lib/Target/ARM/Thumb2InstrInfo.cpp @@ -571,7 +571,7 @@ bool llvm::rewriteT2FrameIndex(MachineInstr &MI, unsigned FrameRegIdx, Register PredReg; if (Offset == 0 && getInstrPredicate(MI, PredReg) == ARMCC::AL && - !MI.definesRegister(ARM::CPSR)) { + !MI.definesRegister(ARM::CPSR, /*TRI=*/nullptr)) { // Turn it into a move. MI.setDesc(TII.get(ARM::tMOVr)); MI.getOperand(FrameRegIdx).ChangeToRegister(FrameReg, false); diff --git a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp index 286010e2ba232740be3f1e93da72e8da9ec53064..f572af98600738562bf8d028d9e3e78185fb17fd 100644 --- a/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp +++ b/llvm/lib/Target/ARM/Thumb2SizeReduction.cpp @@ -1097,12 +1097,13 @@ bool Thumb2SizeReduce::ReduceMBB(MachineBasicBlock &MBB, // marker is only on the BUNDLE instruction. Process the BUNDLE // instruction as we finish with the bundled instruction to work around // the inconsistency. - if (BundleMI->killsRegister(ARM::CPSR)) + if (BundleMI->killsRegister(ARM::CPSR, /*TRI=*/nullptr)) LiveCPSR = false; - MachineOperand *MO = BundleMI->findRegisterDefOperand(ARM::CPSR); + MachineOperand *MO = + BundleMI->findRegisterDefOperand(ARM::CPSR, /*TRI=*/nullptr); if (MO && !MO->isDead()) LiveCPSR = true; - MO = BundleMI->findRegisterUseOperand(ARM::CPSR); + MO = BundleMI->findRegisterUseOperand(ARM::CPSR, /*TRI=*/nullptr); if (MO && !MO->isKill()) LiveCPSR = true; } diff --git a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h index 5aa9ec283406c218d282b70e87ef2aeaf41cf64c..0ecff32a7525f8be65a92cf61ba5b1ba4fd9d6b1 100644 --- a/llvm/lib/Target/BPF/BPFTargetTransformInfo.h +++ b/llvm/lib/Target/BPF/BPFTargetTransformInfo.h @@ -59,14 +59,14 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), - const Instruction *CxtI = nullptr) { - int ISD = TLI->InstructionOpcodeToISD(Opcode); - if (ISD == ISD::ADD && CostKind == TTI::TCK_RecipThroughput) - return SCEVCheapExpansionBudget.getValue() + 1; - - return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, - Op2Info); + ArrayRef Args = std::nullopt, + const Instruction *CxtI = nullptr) { + int ISD = TLI->InstructionOpcodeToISD(Opcode); + if (ISD == ISD::ADD && CostKind == TTI::TCK_RecipThroughput) + return SCEVCheapExpansionBudget.getValue() + 1; + + return BaseT::getArithmeticInstrCost(Opcode, Ty, CostKind, Op1Info, + Op2Info); } TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp index 310993662b672fe0844a67ebc8edf09324fcb74d..99ac0c346d0c0d3f09dbf2e0e72303fe9021a502 100644 --- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp @@ -283,7 +283,7 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, // uses I2's use reg we need to modify that (first) instruction to now kill // this reg. unsigned KilledOperand = 0; - if (I2.killsRegister(I2UseReg)) + if (I2.killsRegister(I2UseReg, /*TRI=*/nullptr)) KilledOperand = I2UseReg; MachineInstr *KillingInstr = nullptr; @@ -360,11 +360,12 @@ bool HexagonCopyToCombine::isSafeToMoveTogether(MachineInstr &I1, if (isUnsafeToMoveAcross(MI, I1UseReg, I1DestReg, TRI) || // Check for an aliased register kill. Bail out if we see one. - (!MI.killsRegister(I1UseReg) && MI.killsRegister(I1UseReg, TRI))) + (!MI.killsRegister(I1UseReg, /*TRI=*/nullptr) && + MI.killsRegister(I1UseReg, TRI))) return false; // Check for an exact kill (registers match). - if (I1UseReg && MI.killsRegister(I1UseReg)) { + if (I1UseReg && MI.killsRegister(I1UseReg, /*TRI=*/nullptr)) { assert(!KillingInstr && "Should only see one killing instruction"); KilledOperand = I1UseReg; KillingInstr = &MI; diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp index e1005296d637520777bae238196708e29c6f56f5..204f3b6b20c751348610e2374267f0bf811f9236 100644 --- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp +++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp @@ -779,7 +779,8 @@ MachineInstr *HexagonExpandCondsets::getReachingDefForPred(RegisterRef RD, // Check if this instruction can be ignored, i.e. if it is predicated // on the complementary condition. if (PredValid && HII->isPredicated(*MI)) { - if (MI->readsRegister(PredR) && (Cond != HII->isPredicatedTrue(*MI))) + if (MI->readsRegister(PredR, /*TRI=*/nullptr) && + (Cond != HII->isPredicatedTrue(*MI))) continue; } @@ -937,7 +938,8 @@ void HexagonExpandCondsets::renameInRange(RegisterRef RO, RegisterRef RN, // on the opposite condition. if (!HII->isPredicated(MI)) continue; - if (!MI.readsRegister(PredR) || (Cond != HII->isPredicatedTrue(MI))) + if (!MI.readsRegister(PredR, /*TRI=*/nullptr) || + (Cond != HII->isPredicatedTrue(MI))) continue; for (auto &Op : MI.operands()) { @@ -1007,7 +1009,8 @@ bool HexagonExpandCondsets::predicate(MachineInstr &TfrI, bool Cond, // By default assume that the instruction executes on the same condition // as TfrI (Exec_Then), and also on the opposite one (Exec_Else). unsigned Exec = Exec_Then | Exec_Else; - if (PredValid && HII->isPredicated(MI) && MI.readsRegister(PredR)) + if (PredValid && HII->isPredicated(MI) && + MI.readsRegister(PredR, /*TRI=*/nullptr)) Exec = (Cond == HII->isPredicatedTrue(MI)) ? Exec_Then : Exec_Else; for (auto &Op : MI.operands()) { diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp index b9bf26ba7cca1ec3447cd9d0ac4dfdadf288754d..e04f9c6faacd3e0f3a9a6b14a0ffa1b745b36089 100644 --- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp +++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp @@ -3517,7 +3517,7 @@ unsigned HexagonInstrInfo::getCompoundOpcode(const MachineInstr &GA, (GB.getOpcode() != Hexagon::J2_jumptnew)) return -1u; Register DestReg = GA.getOperand(0).getReg(); - if (!GB.readsRegister(DestReg)) + if (!GB.readsRegister(DestReg, /*TRI=*/nullptr)) return -1u; if (DestReg != Hexagon::P0 && DestReg != Hexagon::P1) return -1u; @@ -4334,7 +4334,7 @@ std::optional HexagonInstrInfo::getOperandLatency( if (DefMO.isReg() && DefMO.getReg().isPhysical()) { if (DefMO.isImplicit()) { for (MCPhysReg SR : HRI.superregs(DefMO.getReg())) { - int Idx = DefMI.findRegisterDefOperandIdx(SR, false, false, &HRI); + int Idx = DefMI.findRegisterDefOperandIdx(SR, &HRI, false, false); if (Idx != -1) { DefIdx = Idx; break; @@ -4345,7 +4345,7 @@ std::optional HexagonInstrInfo::getOperandLatency( const MachineOperand &UseMO = UseMI.getOperand(UseIdx); if (UseMO.isImplicit()) { for (MCPhysReg SR : HRI.superregs(UseMO.getReg())) { - int Idx = UseMI.findRegisterUseOperandIdx(SR, false, &HRI); + int Idx = UseMI.findRegisterUseOperandIdx(SR, &HRI, false); if (Idx != -1) { UseIdx = Idx; break; diff --git a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h index 9689f2f5bb865c21ba85a8245e4bfb884052e4c0..90c402876a57cde372270abbd72a5a5a4988517f 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h +++ b/llvm/lib/Target/Hexagon/HexagonTargetTransformInfo.h @@ -141,7 +141,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, TTI::CastContextHint CCH, diff --git a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h index bc612963b0ada26aacdee1d382b966ade8cb3abc..b064f4d5b1edf32ce8f641826166b7dfac9de3e0 100644 --- a/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h +++ b/llvm/lib/Target/Lanai/LanaiTargetTransformInfo.h @@ -94,7 +94,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr) { int ISD = TLI->InstructionOpcodeToISD(Opcode); diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp index 786aa7bcb64ea0d4440ba425e277a3f54a8bfb1a..62e4b36b5c9a80291454971133f249fbfda30937 100644 --- a/llvm/lib/Target/M68k/M68kISelLowering.cpp +++ b/llvm/lib/Target/M68k/M68kISelLowering.cpp @@ -3075,9 +3075,9 @@ static bool checkAndUpdateCCRKill(MachineBasicBlock::iterator SelectItr, MachineBasicBlock::iterator miI(std::next(SelectItr)); for (MachineBasicBlock::iterator miE = BB->end(); miI != miE; ++miI) { const MachineInstr &mi = *miI; - if (mi.readsRegister(M68k::CCR)) + if (mi.readsRegister(M68k::CCR, /*TRI=*/nullptr)) return false; - if (mi.definesRegister(M68k::CCR)) + if (mi.definesRegister(M68k::CCR, /*TRI=*/nullptr)) break; // Should have kill-flag - update below. } @@ -3208,7 +3208,7 @@ M68kTargetLowering::EmitLoweredSelect(MachineInstr &MI, const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); MachineInstr *LastCCRSUser = CascadedCMOV ? CascadedCMOV : LastCMOV; - if (!LastCCRSUser->killsRegister(M68k::CCR) && + if (!LastCCRSUser->killsRegister(M68k::CCR, /*TRI=*/nullptr) && !checkAndUpdateCCRKill(LastCCRSUser, MBB, TRI)) { Copy0MBB->addLiveIn(M68k::CCR); SinkMBB->addLiveIn(M68k::CCR); diff --git a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp index cb98c04ff4e501c52936901cfd4413479426ae9e..b525606b1f8fd763202d1f31f5291d6d0de21fc8 100644 --- a/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/llvm/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -365,7 +365,8 @@ void RegDefsUses::setCallerSaved(const MachineInstr &MI) { // Add RA/RA_64 to Defs to prevent users of RA/RA_64 from going into // the delay slot. The reason is that RA/RA_64 must not be changed // in the delay slot so that the callee can return to the caller. - if (MI.definesRegister(Mips::RA) || MI.definesRegister(Mips::RA_64)) { + if (MI.definesRegister(Mips::RA, /*TRI=*/nullptr) || + MI.definesRegister(Mips::RA_64, /*TRI=*/nullptr)) { Defs.set(Mips::RA); Defs.set(Mips::RA_64); } diff --git a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp index d33852a04baf0d3e7c556fd2e8415e061b9598e6..199474fbd82d753d44500353057e13c42d0afb83 100644 --- a/llvm/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/llvm/lib/Target/Mips/MipsExpandPseudo.cpp @@ -479,13 +479,13 @@ bool MipsExpandPseudo::expandAtomicBinOpSubword( BuildMI(loopMBB, DL, TII->get(Mips::SRAV), StoreVal) .addReg(OldVal) .addReg(ShiftAmnt); - if (STI->hasMips32r2() && !IsUnsigned) { - BuildMI(loopMBB, DL, TII->get(SEOp), StoreVal).addReg(StoreVal); - } else if (STI->hasMips32r2() && IsUnsigned) { + if (IsUnsigned) { const unsigned OpMask = SEOp == Mips::SEH ? 0xffff : 0xff; BuildMI(loopMBB, DL, TII->get(Mips::ANDi), StoreVal) .addReg(StoreVal) .addImm(OpMask); + } else if (STI->hasMips32r2()) { + BuildMI(loopMBB, DL, TII->get(SEOp), StoreVal).addReg(StoreVal); } else { const unsigned ShiftImm = SEOp == Mips::SEH ? 16 : 24; const unsigned SROp = IsUnsigned ? Mips::SRL : Mips::SRA; diff --git a/llvm/lib/Target/Mips/MipsInstrInfo.cpp b/llvm/lib/Target/Mips/MipsInstrInfo.cpp index 392cc15d7943afa66b870b484bb5f82340de6caf..f4fba5e53132df9f33bfd707d3742a260f6eb5bd 100644 --- a/llvm/lib/Target/Mips/MipsInstrInfo.cpp +++ b/llvm/lib/Target/Mips/MipsInstrInfo.cpp @@ -619,7 +619,7 @@ bool MipsInstrInfo::SafeInLoadDelaySlot(const MachineInstr &MIInSlot, return false; return !llvm::any_of(LoadMI.defs(), [&](const MachineOperand &Op) { - return Op.isReg() && MIInSlot.readsRegister(Op.getReg()); + return Op.isReg() && MIInSlot.readsRegister(Op.getReg(), /*TRI=*/nullptr); }); } @@ -699,7 +699,7 @@ MipsInstrInfo::genInstrWithNewOpc(unsigned NewOpc, bool BranchWithZeroOperand = false; if (I->isBranch() && !I->isPseudo()) { auto TRI = I->getParent()->getParent()->getSubtarget().getRegisterInfo(); - ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, false, TRI); + ZeroOperandPosition = I->findRegisterUseOperandIdx(Mips::ZERO, TRI, false); BranchWithZeroOperand = ZeroOperandPosition != -1; } diff --git a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h index 3ce2675560c4df0c5d865ebe8245492b2ba0ef21..5a4fbab97f952e021f26f5f9a52cf4497b5696df 100644 --- a/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h +++ b/llvm/lib/Target/NVPTX/NVPTXTargetTransformInfo.h @@ -98,7 +98,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); void getUnrollingPreferences(Loop *L, ScalarEvolution &SE, diff --git a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp index 5299c0c924b3c53f7eaec793bc25f0d6c3b924e1..491779124e8a77267b722a2d65f863defc252d15 100644 --- a/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp +++ b/llvm/lib/Target/PowerPC/PPCCTRLoops.cpp @@ -123,10 +123,12 @@ bool PPCCTRLoops::isCTRClobber(MachineInstr *MI, bool CheckReads) const { // CTR defination inside the callee of a call instruction will not impact // the defination of MTCTRloop, so we can use definesRegister() for the // check, no need to check the regmask. - return MI->definesRegister(PPC::CTR) || MI->definesRegister(PPC::CTR8); + return MI->definesRegister(PPC::CTR, /*TRI=*/nullptr) || + MI->definesRegister(PPC::CTR8, /*TRI=*/nullptr); } - if (MI->modifiesRegister(PPC::CTR) || MI->modifiesRegister(PPC::CTR8)) + if (MI->modifiesRegister(PPC::CTR, /*TRI=*/nullptr) || + MI->modifiesRegister(PPC::CTR8, /*TRI=*/nullptr)) return true; if (MI->getDesc().isCall()) @@ -134,7 +136,8 @@ bool PPCCTRLoops::isCTRClobber(MachineInstr *MI, bool CheckReads) const { // We define the CTR in the loop preheader, so if there is any CTR reader in // the loop, we also can not use CTR loop form. - if (MI->readsRegister(PPC::CTR) || MI->readsRegister(PPC::CTR8)) + if (MI->readsRegister(PPC::CTR, /*TRI=*/nullptr) || + MI->readsRegister(PPC::CTR8, /*TRI=*/nullptr)) return true; return false; diff --git a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td index a9359794a641c95ec99ad98038eb69f2e6825360..9af8ada7837614c1d311bc555ab5460a3f53e609 100644 --- a/llvm/lib/Target/PowerPC/PPCInstr64Bit.td +++ b/llvm/lib/Target/PowerPC/PPCInstr64Bit.td @@ -76,7 +76,7 @@ let Interpretation64Bit = 1, isCodeGenOnly = 1 in { let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let isReturn = 1, isPredicable = 1, Uses = [LR8, RM] in def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, - [(retglue)]>, Requires<[In64BitMode]>; + [(PPCretglue)]>, Requires<[In64BitMode]>; let isBranch = 1, isIndirectBranch = 1, Uses = [CTR8] in { let isPredicable = 1 in def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp index b32f178ca38e65f5a32df2f67be91f7beea94f28..9e56de732c587e8a568e533ac18702b6eb61b5a4 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.cpp @@ -2125,7 +2125,8 @@ bool PPCInstrInfo::foldImmediate(MachineInstr &UseMI, MachineInstr &DefMI, static bool MBBDefinesCTR(MachineBasicBlock &MBB) { for (MachineInstr &MI : MBB) - if (MI.definesRegister(PPC::CTR) || MI.definesRegister(PPC::CTR8)) + if (MI.definesRegister(PPC::CTR, /*TRI=*/nullptr) || + MI.definesRegister(PPC::CTR8, /*TRI=*/nullptr)) return true; return false; } @@ -2731,19 +2732,19 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, MI->setDesc(NewDesc); for (MCPhysReg ImpDef : NewDesc.implicit_defs()) { - if (!MI->definesRegister(ImpDef)) { + if (!MI->definesRegister(ImpDef, /*TRI=*/nullptr)) { MI->addOperand(*MI->getParent()->getParent(), MachineOperand::CreateReg(ImpDef, true, true)); } } for (MCPhysReg ImpUse : NewDesc.implicit_uses()) { - if (!MI->readsRegister(ImpUse)) { + if (!MI->readsRegister(ImpUse, /*TRI=*/nullptr)) { MI->addOperand(*MI->getParent()->getParent(), MachineOperand::CreateReg(ImpUse, false, true)); } } } - assert(MI->definesRegister(PPC::CR0) && + assert(MI->definesRegister(PPC::CR0, /*TRI=*/nullptr) && "Record-form instruction does not define cr0?"); // Modify the condition code of operands in OperandsToUpdate. @@ -2793,7 +2794,7 @@ bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const { bool SrcRegHasOtherUse = false; MachineInstr *SrcMI = getDefMIPostRA(SrcReg, CmpMI, SrcRegHasOtherUse); - if (!SrcMI || !SrcMI->definesRegister(SrcReg)) + if (!SrcMI || !SrcMI->definesRegister(SrcReg, /*TRI=*/nullptr)) return false; MachineOperand RegMO = CmpMI.getOperand(0); @@ -2806,7 +2807,7 @@ bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const { bool IsCRRegKilled = false; if (!isRegElgibleForForwarding(RegMO, *SrcMI, CmpMI, false, IsCRRegKilled, SeenUseOfCRReg) || - SrcMI->definesRegister(CRReg) || SeenUseOfCRReg) + SrcMI->definesRegister(CRReg, /*TRI=*/nullptr) || SeenUseOfCRReg) return false; int SrcMIOpc = SrcMI->getOpcode(); @@ -2823,7 +2824,7 @@ bool PPCInstrInfo::optimizeCmpPostRA(MachineInstr &CmpMI) const { .addReg(CRReg, RegState::ImplicitDefine); SrcMI->clearRegisterDeads(CRReg); - assert(SrcMI->definesRegister(PPC::CR0) && + assert(SrcMI->definesRegister(PPC::CR0, /*TRI=*/nullptr) && "Record-form instruction does not define cr0?"); LLVM_DEBUG(dbgs() << "with: "); @@ -3293,7 +3294,7 @@ void PPCInstrInfo::replaceInstrOperandWithImm(MachineInstr &MI, // result its number of explicit operands may be changed, thus the begin of // implicit operand is changed. const TargetRegisterInfo *TRI = &getRegisterInfo(); - int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, false, TRI); + int UseOpIdx = MI.findRegisterUseOperandIdx(InUseReg, TRI, false); if (UseOpIdx >= 0) { MachineOperand &MO = MI.getOperand(UseOpIdx); if (MO.isImplicit()) diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td index 261b9a3d1dffe9a17a21eb5d1821005c7b167617..7929a781dbda84bc09828b679a46d7477e8809aa 100644 --- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td +++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td @@ -336,7 +336,7 @@ def PPCbctrl_load_toc_rm : SDNode<"PPCISD::BCTRL_LOAD_TOC_RM", [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue, SDNPVariadic]>; -def retglue : SDNode<"PPCISD::RET_GLUE", SDTNone, +def PPCretglue : SDNode<"PPCISD::RET_GLUE", SDTNone, [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; def PPCtc_return : SDNode<"PPCISD::TC_RETURN", SDT_PPCTC_ret, @@ -1299,7 +1299,7 @@ def RESTORE_CRBIT : PPCEmitTimePseudo<(outs crbitrc:$cond), (ins memri:$F), let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7, hasSideEffects = 0 in { let isPredicable = 1, isReturn = 1, Uses = [LR, RM] in def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB, - [(retglue)]>, Requires<[In32BitMode]>; + [(PPCretglue)]>, Requires<[In32BitMode]>; let isBranch = 1, isIndirectBranch = 1, Uses = [CTR] in { let isPredicable = 1 in def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB, diff --git a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp index 6e3bf26a598a9a6d121f828abe4e95602d1c7ad3..a182be3ea712b4d823cedb276b40ecd070cdfbfa 100644 --- a/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp @@ -158,7 +158,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) { ++AfterBBI) { // Track the operand that kill Reg. We would unset the kill flag of // the operand if there is a following redundant load immediate. - int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, true, TRI); + int KillIdx = AfterBBI->findRegisterUseOperandIdx(Reg, TRI, true); // We can't just clear implicit kills, so if we encounter one, stop // looking further. @@ -204,7 +204,7 @@ static bool hasPCRelativeForm(MachineInstr &Use) { DeadOrKillToUnset->setIsKill(false); } DeadOrKillToUnset = - AfterBBI->findRegisterDefOperand(Reg, true, true, TRI); + AfterBBI->findRegisterDefOperand(Reg, TRI, true, true); if (DeadOrKillToUnset) LLVM_DEBUG(dbgs() << " Dead flag of " << *DeadOrKillToUnset << " from " diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp index 0f450a4bf9692bce736a91e00e651dacbae2b89d..7e4cd6c72aa87a45b72926c24330a56c499a6960 100644 --- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1013,8 +1013,8 @@ void PPCRegisterInfo::lowerCRRestore(MachineBasicBlock::iterator II, Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); Register DestReg = MI.getOperand(0).getReg(); - assert(MI.definesRegister(DestReg) && - "RESTORE_CR does not define its destination"); + assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && + "RESTORE_CR does not define its destination"); addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), Reg), FrameIndex); @@ -1175,8 +1175,8 @@ void PPCRegisterInfo::lowerCRBitRestore(MachineBasicBlock::iterator II, Register Reg = MF.getRegInfo().createVirtualRegister(LP64 ? G8RC : GPRC); Register DestReg = MI.getOperand(0).getReg(); - assert(MI.definesRegister(DestReg) && - "RESTORE_CRBIT does not define its destination"); + assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && + "RESTORE_CRBIT does not define its destination"); addFrameReference(BuildMI(MBB, II, dl, TII.get(LP64 ? PPC::LWZ8 : PPC::LWZ), Reg), FrameIndex); @@ -1363,7 +1363,7 @@ void PPCRegisterInfo::lowerACCRestore(MachineBasicBlock::iterator II, DebugLoc DL = MI.getDebugLoc(); Register DestReg = MI.getOperand(0).getReg(); - assert(MI.definesRegister(DestReg) && + assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && "RESTORE_ACC does not define its destination"); bool IsPrimed = PPC::ACCRCRegClass.contains(DestReg); @@ -1491,7 +1491,7 @@ void PPCRegisterInfo::lowerQuadwordRestore(MachineBasicBlock::iterator II, DebugLoc DL = MI.getDebugLoc(); Register DestReg = MI.getOperand(0).getReg(); - assert(MI.definesRegister(DestReg) && + assert(MI.definesRegister(DestReg, /*TRI=*/nullptr) && "RESTORE_QUADWORD does not define its destination"); Register Reg = PPC::X0 + (DestReg - PPC::G8p0) * 2; diff --git a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h index 36006dd7df7396affc0d1b2c3cdc7154d4563b58..061f5da5daf53b86525f500e028b88142b5e7e6f 100644 --- a/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h +++ b/llvm/lib/Target/PowerPC/PPCTargetTransformInfo.h @@ -106,7 +106,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost getShuffleCost(TTI::ShuffleKind Kind, Type *Tp, ArrayRef Mask, diff --git a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp index 3f4a73ad89bf8ace318b15c4db01a2892fc565d2..8ac79ddce595e0d36a41ba5fdf8ca455c8f2b47d 100644 --- a/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp +++ b/llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp @@ -38,7 +38,7 @@ #include "llvm/Support/CommandLine.h" #include "llvm/Support/MathExtras.h" #include "llvm/Support/RISCVAttributes.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include diff --git a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp index 8d97c5ffd20a05ab543bddbbe19c8e52ffd27cc5..fb0dc482e6081302b8fceb22f8a475719e8f1182 100644 --- a/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp +++ b/llvm/lib/Target/RISCV/MCA/RISCVCustomBehaviour.cpp @@ -20,26 +20,6 @@ #define DEBUG_TYPE "llvm-mca-riscv-custombehaviour" -// This brings in a table with primary key of -// base instruction opcode and lmul and maps -// to the opcode of the pseudo instruction. -namespace RISCVVInversePseudosTable { -using namespace llvm; -using namespace llvm::RISCV; - -struct PseudoInfo { - uint16_t Pseudo; - uint16_t BaseInstr; - uint8_t VLMul; - uint8_t SEW; -}; - -#define GET_RISCVVInversePseudosTable_IMPL -#define GET_RISCVVInversePseudosTable_DECL -#include "RISCVGenSearchableTables.inc" - -} // end namespace RISCVVInversePseudosTable - namespace llvm { namespace mca { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp index 67c9060b515772bfe6e8b357ece2d855a0f549f4..4c59474df883585506bb3a252a36fa5e353a8cfb 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp @@ -16,7 +16,6 @@ #include "llvm/MC/MCInst.h" #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCSubtargetInfo.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/raw_ostream.h" #include "llvm/TargetParser/TargetParser.h" #include "llvm/TargetParser/Triple.h" diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h index aa641bc866aa5e91b9a7acf45913968c94c7309d..08f056f78979af4cd7afe5ea3c848fef50d7fd6b 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.h @@ -19,7 +19,7 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringSwitch.h" #include "llvm/MC/MCInstrDesc.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/TargetParser/SubtargetFeature.h" diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp index 79e56a7a6d03d7738ee501d1866cefb15924ede6..12a69842ab4c37ebef7a9e473a50b67388051b27 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.cpp @@ -43,6 +43,15 @@ #define GET_SUBTARGETINFO_MC_DESC #include "RISCVGenSubtargetInfo.inc" +namespace llvm::RISCVVInversePseudosTable { + +using namespace RISCV; + +#define GET_RISCVVInversePseudosTable_IMPL +#include "RISCVGenSearchableTables.inc" + +} // namespace llvm::RISCVVInversePseudosTable + using namespace llvm; static MCInstrInfo *createRISCVMCInstrInfo() { diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h index 3cfddb530cdf63035a8bd61cd28b9932d896850a..d4aa0fe99078e15ffd729b2c881ca277f6535a96 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCTargetDesc.h @@ -37,7 +37,21 @@ MCAsmBackend *createRISCVAsmBackend(const Target &T, const MCSubtargetInfo &STI, std::unique_ptr createRISCVELFObjectWriter(uint8_t OSABI, bool Is64Bit); -} + +namespace RISCVVInversePseudosTable { + +struct PseudoInfo { + uint16_t Pseudo; + uint16_t BaseInstr; + uint8_t VLMul; + uint8_t SEW; +}; + +#define GET_RISCVVInversePseudosTable_DECL +#include "RISCVGenSearchableTables.inc" + +} // namespace RISCVVInversePseudosTable +} // namespace llvm // Defines symbolic names for RISC-V registers. #define GET_REGINFO_ENUM diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 4a4b1e13c2b9ec35a5dc81de24fc6e9c3cc425b5..0f92e9ed6a64d39f3d6920c81355da64c3305db4 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -16,7 +16,7 @@ #include "llvm/MC/MCSymbol.h" #include "llvm/Support/FormattedStream.h" #include "llvm/Support/RISCVAttributes.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" using namespace llvm; diff --git a/llvm/lib/Target/RISCV/RISCV.h b/llvm/lib/Target/RISCV/RISCV.h index 7af543f018ccbd5ed10e9b19aa2c80cc58656bba..d405395dcf9ec4146db78ee6fc6bb19fd9ff0ae7 100644 --- a/llvm/lib/Target/RISCV/RISCV.h +++ b/llvm/lib/Target/RISCV/RISCV.h @@ -61,6 +61,9 @@ void initializeRISCVExpandAtomicPseudoPass(PassRegistry &); FunctionPass *createRISCVInsertVSETVLIPass(); void initializeRISCVInsertVSETVLIPass(PassRegistry &); +FunctionPass *createRISCVCoalesceVSETVLIPass(); +void initializeRISCVCoalesceVSETVLIPass(PassRegistry &); + FunctionPass *createRISCVPostRAExpandPseudoPass(); void initializeRISCVPostRAExpandPseudoPass(PassRegistry &); FunctionPass *createRISCVInsertReadWriteCSRPass(); diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp index 779f179dff619ff81aa3f54e8013da4b76a01241..6eceaddc747d15ed9f116b095bf7c2ac955124a8 100644 --- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp +++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp @@ -37,8 +37,8 @@ #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/Transforms/Instrumentation/HWAddressSanitizer.h" using namespace llvm; diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index b064191b838e5b5de9e53e82363d08a7aa1bb07d..c3dc4ea53697c041bb8d344cb677976a1c16e2f7 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -391,7 +391,7 @@ def HasStdExtZcb : Predicate<"Subtarget->hasStdExtZcb()">, def FeatureStdExtZcd : RISCVExtension<"zcd", 1, 0, "'Zcd' (Compressed Double-Precision Floating-Point Instructions)", - [FeatureStdExtZca]>; + [FeatureStdExtD, FeatureStdExtZca]>; def HasStdExtCOrZcd : Predicate<"Subtarget->hasStdExtCOrZcd()">, @@ -402,7 +402,7 @@ def HasStdExtCOrZcd def FeatureStdExtZcf : RISCVExtension<"zcf", 1, 0, "'Zcf' (Compressed Single-Precision Floating-Point Instructions)", - [FeatureStdExtZca]>; + [FeatureStdExtF, FeatureStdExtZca]>; def FeatureStdExtZcmp : RISCVExtension<"zcmp", 1, 0, @@ -423,8 +423,7 @@ def HasStdExtZcmt : Predicate<"Subtarget->hasStdExtZcmt()">, def FeatureStdExtZce : RISCVExtension<"zce", 1, 0, "'Zce' (Compressed extensions for microcontrollers)", - [FeatureStdExtZca, FeatureStdExtZcb, FeatureStdExtZcmp, - FeatureStdExtZcmt]>; + [FeatureStdExtZcb, FeatureStdExtZcmp, FeatureStdExtZcmt]>; def HasStdExtCOrZcfOrZce : Predicate<"Subtarget->hasStdExtC() || Subtarget->hasStdExtZcf() " @@ -1016,8 +1015,7 @@ def HasVendorXTHeadCmo : Predicate<"Subtarget->hasVendorXTHeadCmo()">, def FeatureVendorXTHeadFMemIdx : RISCVExtension<"xtheadfmemidx", 1, 0, - "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)", - [FeatureStdExtF]>; + "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">; def HasVendorXTHeadFMemIdx : Predicate<"Subtarget->hasVendorXTHeadFMemIdx()">, AssemblerPredicate<(all_of FeatureVendorXTHeadFMemIdx), "'xtheadfmemidx' (T-Head FP Indexed Memory Operations)">; @@ -1089,7 +1087,7 @@ def HasVendorXSfvqmaccqoq def FeatureVendorXSfvfwmaccqqq : RISCVExtension<"xsfvfwmaccqqq", 1, 0, "'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4))", - [FeatureStdExtZve32f, FeatureStdExtZvfbfmin]>; + [FeatureStdExtZvfbfmin]>; def HasVendorXSfvfwmaccqqq : Predicate<"Subtarget->hasVendorXSfvfwmaccqqq()">, AssemblerPredicate<(all_of FeatureVendorXSfvfwmaccqqq), diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp index f99dc0b857636884d5b909231ce3aadfe1a10a15..b0568297a470a751e999028fc7467fa9eb944ef0 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp @@ -43,7 +43,6 @@ namespace llvm::RISCV { #define GET_RISCVVSETable_IMPL #define GET_RISCVVLXTable_IMPL #define GET_RISCVVSXTable_IMPL -#define GET_RISCVMaskedPseudosTable_IMPL #include "RISCVGenSearchableTables.inc" } // namespace llvm::RISCV diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h index 92f818b0dc48910acf14c63b4cbfdb69cfb56222..7d4aec2dfdc9841efd74857d179c8d51d5c116f2 100644 --- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h +++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.h @@ -261,13 +261,6 @@ struct VLX_VSXPseudo { uint16_t Pseudo; }; -struct RISCVMaskedPseudoInfo { - uint16_t MaskedPseudo; - uint16_t UnmaskedPseudo; - uint8_t MaskOpIdx; - uint8_t MaskAffectsResult : 1; -}; - #define GET_RISCVVSSEGTable_DECL #define GET_RISCVVLSEGTable_DECL #define GET_RISCVVLXSEGTable_DECL @@ -276,8 +269,6 @@ struct RISCVMaskedPseudoInfo { #define GET_RISCVVSETable_DECL #define GET_RISCVVLXTable_DECL #define GET_RISCVVSXTable_DECL -#define GET_RISCVMaskedPseudosTable_DECL -#include "RISCVGenSearchableTables.inc" } // namespace RISCV } // namespace llvm diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 605b4a66d6221b8a3c61ff903679118971463575..6529ab7a84a133672234c5e1793a09aa07fc6827 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -13449,9 +13449,8 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, SDValue X = DAG.getFreeze(N->getOperand(0)); SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ShiftAmt, DL, VT)); - SDValue Shift2 = - DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ScaleShift, DL, VT)); - return DAG.getNode(ISD::ADD, DL, VT, Shift1, Shift2); + return DAG.getNode(RISCVISD::SHL_ADD, DL, VT, X, + DAG.getConstant(ScaleShift, DL, VT), Shift1); } } @@ -13485,10 +13484,23 @@ static SDValue expandMul(SDNode *N, SelectionDAG &DAG, SDValue X = DAG.getFreeze(N->getOperand(0)); SDValue Shift1 = DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ShiftAmt, DL, VT)); - SDValue Shift2 = - DAG.getNode(ISD::SHL, DL, VT, X, DAG.getConstant(ScaleShift, DL, VT)); return DAG.getNode(ISD::ADD, DL, VT, Shift1, - DAG.getNode(ISD::ADD, DL, VT, Shift2, X)); + DAG.getNode(RISCVISD::SHL_ADD, DL, VT, X, + DAG.getConstant(ScaleShift, DL, VT), X)); + } + } + + // 2^N - 3/5/9 --> (sub (shl X, C1), (shXadd X, x)) + for (uint64_t Offset : {3, 5, 9}) { + if (isPowerOf2_64(MulAmt + Offset)) { + SDLoc DL(N); + SDValue Shift1 = + DAG.getNode(ISD::SHL, DL, VT, N->getOperand(0), + DAG.getConstant(Log2_64(MulAmt + Offset), DL, VT)); + SDValue Mul359 = DAG.getNode(RISCVISD::SHL_ADD, DL, VT, N->getOperand(0), + DAG.getConstant(Log2_64(Offset - 1), DL, VT), + N->getOperand(0)); + return DAG.getNode(ISD::SUB, DL, VT, Shift1, Mul359); } } @@ -16834,7 +16846,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, StrideC && StrideC->getZExtValue() == ElementSize) return DAG.getMaskedStore(Store->getChain(), DL, Value, Base, DAG.getUNDEF(XLenVT), Mask, - Store->getMemoryVT(), Store->getMemOperand(), + Value.getValueType(), Store->getMemOperand(), ISD::UNINDEXED, false); return SDValue(); } @@ -17775,6 +17787,18 @@ static MachineBasicBlock *emitSelectPseudo(MachineInstr &MI, return TailMBB; } +// Helper to find Masked Pseudo instruction from MC instruction, LMUL and SEW. +static const RISCV::RISCVMaskedPseudoInfo * +lookupMaskedIntrinsic(uint16_t MCOpcode, RISCVII::VLMUL LMul, unsigned SEW) { + const RISCVVInversePseudosTable::PseudoInfo *Inverse = + RISCVVInversePseudosTable::getBaseInfo(MCOpcode, LMul, SEW); + assert(Inverse && "Unexpected LMUL and SEW pair for instruction"); + const RISCV::RISCVMaskedPseudoInfo *Masked = + RISCV::lookupMaskedIntrinsicByUnmasked(Inverse->Pseudo); + assert(Masked && "Could not find masked instruction for LMUL and SEW pair"); + return Masked; +} + static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI, MachineBasicBlock *BB, unsigned CVTXOpc) { @@ -17812,80 +17836,9 @@ static MachineBasicBlock *emitVFROUND_NOEXCEPT_MASK(MachineInstr &MI, unsigned Log2SEW = MI.getOperand(RISCVII::getSEWOpNum(MI.getDesc())).getImm(); // There is no E8 variant for VFCVT_F_X. assert(Log2SEW >= 4); - // Since MI (VFROUND) isn't SEW specific, we cannot use a macro to make - // handling of different (LMUL, SEW) pairs easier because we need to pull the - // SEW immediate from MI, and that information is not avaliable during macro - // expansion. - unsigned CVTFOpc; - if (Log2SEW == 4) { - switch (LMul) { - case RISCVII::LMUL_1: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E16_MASK; - break; - case RISCVII::LMUL_2: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E16_MASK; - break; - case RISCVII::LMUL_4: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E16_MASK; - break; - case RISCVII::LMUL_8: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E16_MASK; - break; - case RISCVII::LMUL_F2: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E16_MASK; - break; - case RISCVII::LMUL_F4: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF4_E16_MASK; - break; - case RISCVII::LMUL_F8: - case RISCVII::LMUL_RESERVED: - llvm_unreachable("Unexpected LMUL and SEW combination value for MI."); - } - } else if (Log2SEW == 5) { - switch (LMul) { - case RISCVII::LMUL_1: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E32_MASK; - break; - case RISCVII::LMUL_2: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E32_MASK; - break; - case RISCVII::LMUL_4: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E32_MASK; - break; - case RISCVII::LMUL_8: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E32_MASK; - break; - case RISCVII::LMUL_F2: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_MF2_E32_MASK; - break; - case RISCVII::LMUL_F4: - case RISCVII::LMUL_F8: - case RISCVII::LMUL_RESERVED: - llvm_unreachable("Unexpected LMUL and SEW combination value for MI."); - } - } else if (Log2SEW == 6) { - switch (LMul) { - case RISCVII::LMUL_1: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M1_E64_MASK; - break; - case RISCVII::LMUL_2: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M2_E64_MASK; - break; - case RISCVII::LMUL_4: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M4_E64_MASK; - break; - case RISCVII::LMUL_8: - CVTFOpc = RISCV::PseudoVFCVT_F_X_V_M8_E64_MASK; - break; - case RISCVII::LMUL_F2: - case RISCVII::LMUL_F4: - case RISCVII::LMUL_F8: - case RISCVII::LMUL_RESERVED: - llvm_unreachable("Unexpected LMUL and SEW combination value for MI."); - } - } else { - llvm_unreachable("Unexpected LMUL and SEW combination value for MI."); - } + unsigned CVTFOpc = + lookupMaskedIntrinsic(RISCV::VFCVT_F_X_V, LMul, 1 << Log2SEW) + ->MaskedPseudo; BuildMI(*BB, MI, DL, TII.get(CVTFOpc)) .add(MI.getOperand(0)) @@ -18149,7 +18102,7 @@ void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, if (MI.getOperand(Idx).getImm() != RISCVFPRndMode::DYN) return; // If the instruction already reads FRM, don't add another read. - if (MI.readsRegister(RISCV::FRM)) + if (MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) return; MI.addOperand( MachineOperand::CreateReg(RISCV::FRM, /*isDef*/ false, /*isImp*/ true)); diff --git a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp index aac0ecc1cfc9b8ebe89660cec52fdf680323b9d0..7b9e9fb988bc68e25cf6256e247c718adfcc0236 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertReadWriteCSR.cpp @@ -82,7 +82,8 @@ bool RISCVInsertReadWriteCSR::emitWriteRoundingModeOpt(MachineBasicBlock &MBB) { continue; } - if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::FRM)) { + if (MI.isCall() || MI.isInlineAsm() || + MI.readsRegister(RISCV::FRM, /*TRI=*/nullptr)) { // Restore FRM before unknown operations. if (SavedFRM.isValid()) BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteFRM)) @@ -92,7 +93,7 @@ bool RISCVInsertReadWriteCSR::emitWriteRoundingModeOpt(MachineBasicBlock &MBB) { continue; } - assert(!MI.modifiesRegister(RISCV::FRM) && + assert(!MI.modifiesRegister(RISCV::FRM, /*TRI=*/nullptr) && "Expected that MI could not modify FRM."); int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc()); diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 331253e39c0acb8a39042a62c6a0c896d21be6dd..ec1a9f4c135ccb33eb9844a714338201e476308e 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -27,16 +27,19 @@ #include "RISCV.h" #include "RISCVSubtarget.h" #include "llvm/ADT/Statistic.h" +#include "llvm/CodeGen/LiveDebugVariables.h" #include "llvm/CodeGen/LiveIntervals.h" +#include "llvm/CodeGen/LiveStacks.h" #include "llvm/CodeGen/MachineFunctionPass.h" #include using namespace llvm; #define DEBUG_TYPE "riscv-insert-vsetvli" #define RISCV_INSERT_VSETVLI_NAME "RISC-V Insert VSETVLI pass" +#define RISCV_COALESCE_VSETVLI_NAME "RISC-V Coalesce VSETVLI pass" STATISTIC(NumInsertedVSETVL, "Number of VSETVL inst inserted"); -STATISTIC(NumRemovedVSETVL, "Number of VSETVL inst removed"); +STATISTIC(NumCoalescedVSETVL, "Number of VSETVL inst coalesced"); static cl::opt DisableInsertVSETVLPHIOpt( "riscv-disable-insert-vsetvl-phi-opt", cl::init(false), cl::Hidden, @@ -190,6 +193,11 @@ static bool hasUndefinedMergeOp(const MachineInstr &MI, if (UseMO.getReg() == RISCV::NoRegister) return true; + if (UseMO.isUndef()) + return true; + if (UseMO.getReg().isPhysical()) + return false; + if (MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg())) { if (UseMI->isImplicitDef()) return true; @@ -356,9 +364,11 @@ DemandedFields getDemanded(const MachineInstr &MI, // Most instructions don't use any of these subfeilds. DemandedFields Res; // Start conservative if registers are used - if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VL)) + if (MI.isCall() || MI.isInlineAsm() || + MI.readsRegister(RISCV::VL, /*TRI=*/nullptr)) Res.demandVL(); - if (MI.isCall() || MI.isInlineAsm() || MI.readsRegister(RISCV::VTYPE)) + if (MI.isCall() || MI.isInlineAsm() || + MI.readsRegister(RISCV::VTYPE, /*TRI=*/nullptr)) Res.demandVTYPE(); // Start conservative on the unlowered form too uint64_t TSFlags = MI.getDesc().TSFlags; @@ -778,11 +788,40 @@ private: VSETVLIInfo &Info) const; void computeIncomingVLVTYPE(const MachineBasicBlock &MBB); void emitVSETVLIs(MachineBasicBlock &MBB); - void doLocalPostpass(MachineBasicBlock &MBB); void doPRE(MachineBasicBlock &MBB); void insertReadVL(MachineBasicBlock &MBB); }; +class RISCVCoalesceVSETVLI : public MachineFunctionPass { +public: + static char ID; + const RISCVSubtarget *ST; + const TargetInstrInfo *TII; + MachineRegisterInfo *MRI; + LiveIntervals *LIS; + + RISCVCoalesceVSETVLI() : MachineFunctionPass(ID) {} + bool runOnMachineFunction(MachineFunction &MF) override; + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.setPreservesCFG(); + + AU.addRequired(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + AU.addPreserved(); + AU.addPreserved(); + + MachineFunctionPass::getAnalysisUsage(AU); + } + + StringRef getPassName() const override { return RISCV_COALESCE_VSETVLI_NAME; } + +private: + bool coalesceVSETVLIs(MachineBasicBlock &MBB); +}; + } // end anonymous namespace char RISCVInsertVSETVLI::ID = 0; @@ -790,6 +829,11 @@ char RISCVInsertVSETVLI::ID = 0; INITIALIZE_PASS(RISCVInsertVSETVLI, DEBUG_TYPE, RISCV_INSERT_VSETVLI_NAME, false, false) +char RISCVCoalesceVSETVLI::ID = 0; + +INITIALIZE_PASS(RISCVCoalesceVSETVLI, "riscv-coalesce-vsetvli", + RISCV_COALESCE_VSETVLI_NAME, false, false) + // Return a VSETVLIInfo representing the changes made by this VSETVLI or // VSETIVLI instruction. static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) { @@ -1157,8 +1201,9 @@ void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info, // If this is something that updates VL/VTYPE that we don't know about, set // the state to unknown. - if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) || - MI.modifiesRegister(RISCV::VTYPE)) + if (MI.isCall() || MI.isInlineAsm() || + MI.modifiesRegister(RISCV::VL, /*TRI=*/nullptr) || + MI.modifiesRegister(RISCV::VTYPE, /*TRI=*/nullptr)) Info = VSETVLIInfo::getUnknown(); } @@ -1341,8 +1386,9 @@ void RISCVInsertVSETVLI::emitVSETVLIs(MachineBasicBlock &MBB) { /*isImp*/ true)); } - if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) || - MI.modifiesRegister(RISCV::VTYPE)) + if (MI.isCall() || MI.isInlineAsm() || + MI.modifiesRegister(RISCV::VL, /*TRI=*/nullptr) || + MI.modifiesRegister(RISCV::VTYPE, /*TRI=*/nullptr)) PrefixTransparent = false; transferAfter(CurInfo, MI); @@ -1511,12 +1557,12 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI, auto &AVL = MI.getOperand(1); auto &PrevAVL = PrevMI.getOperand(1); - assert(MRI.isSSA()); // If the AVL is a register, we need to make sure MI's AVL dominates PrevMI. // For now just check that PrevMI uses the same virtual register. if (AVL.isReg() && AVL.getReg() != RISCV::X0 && - (!PrevAVL.isReg() || PrevAVL.getReg() != AVL.getReg())) + (!MRI.hasOneDef(AVL.getReg()) || !PrevAVL.isReg() || + PrevAVL.getReg() != AVL.getReg())) return false; } @@ -1526,7 +1572,7 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI, return areCompatibleVTYPEs(PriorVType, VType, Used); } -void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) { +bool RISCVCoalesceVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) { MachineInstr *NextMI = nullptr; // We can have arbitrary code in successors, so VL and VTYPE // must be considered demanded. @@ -1538,8 +1584,9 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) { if (!isVectorConfigInstr(MI)) { doUnion(Used, getDemanded(MI, MRI, ST)); - if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VL) || - MI.modifiesRegister(RISCV::VTYPE)) + if (MI.isCall() || MI.isInlineAsm() || + MI.modifiesRegister(RISCV::VL, /*TRI=*/nullptr) || + MI.modifiesRegister(RISCV::VTYPE, /*TRI=*/nullptr)) NextMI = nullptr; continue; } @@ -1558,8 +1605,28 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) { if (canMutatePriorConfig(MI, *NextMI, Used, *MRI)) { if (!isVLPreservingConfig(*NextMI)) { - MI.getOperand(0).setReg(NextMI->getOperand(0).getReg()); + Register DefReg = NextMI->getOperand(0).getReg(); + + MI.getOperand(0).setReg(DefReg); MI.getOperand(0).setIsDead(false); + + // The def of DefReg moved to MI, so extend the LiveInterval up to + // it. + if (DefReg.isVirtual()) { + LiveInterval &DefLI = LIS->getInterval(DefReg); + SlotIndex MISlot = LIS->getInstructionIndex(MI).getRegSlot(); + VNInfo *DefVNI = DefLI.getVNInfoAt(DefLI.beginIndex()); + LiveInterval::Segment S(MISlot, DefLI.beginIndex(), DefVNI); + DefLI.addSegment(S); + DefVNI->def = MISlot; + // Mark DefLI as spillable if it was previously unspillable + DefLI.setWeight(0); + + // DefReg may have had no uses, in which case we need to shrink + // the LiveInterval up to MI. + LIS->shrinkToUses(&DefLI); + } + Register OldVLReg; if (MI.getOperand(1).isReg()) OldVLReg = MI.getOperand(1).getReg(); @@ -1567,11 +1634,21 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) { MI.getOperand(1).ChangeToImmediate(NextMI->getOperand(1).getImm()); else MI.getOperand(1).ChangeToRegister(NextMI->getOperand(1).getReg(), false); - if (OldVLReg) { + + // Clear NextMI's AVL early so we're not counting it as a use. + if (NextMI->getOperand(1).isReg()) + NextMI->getOperand(1).setReg(RISCV::NoRegister); + + if (OldVLReg && OldVLReg.isVirtual()) { + // NextMI no longer uses OldVLReg so shrink its LiveInterval. + LIS->shrinkToUses(&LIS->getInterval(OldVLReg)); + MachineInstr *VLOpDef = MRI->getUniqueVRegDef(OldVLReg); if (VLOpDef && TII->isAddImmediate(*VLOpDef, OldVLReg) && - MRI->use_nodbg_empty(OldVLReg)) + MRI->use_nodbg_empty(OldVLReg)) { VLOpDef->eraseFromParent(); + LIS->removeInterval(OldVLReg); + } } MI.setDesc(NextMI->getDesc()); } @@ -1584,9 +1661,13 @@ void RISCVInsertVSETVLI::doLocalPostpass(MachineBasicBlock &MBB) { Used = getDemanded(MI, MRI, ST); } - NumRemovedVSETVL += ToDelete.size(); - for (auto *MI : ToDelete) + NumCoalescedVSETVL += ToDelete.size(); + for (auto *MI : ToDelete) { + LIS->RemoveMachineInstrFromMaps(*MI); MI->eraseFromParent(); + } + + return !ToDelete.empty(); } void RISCVInsertVSETVLI::insertReadVL(MachineBasicBlock &MBB) { @@ -1661,15 +1742,6 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) { for (MachineBasicBlock &MBB : MF) emitVSETVLIs(MBB); - // Now that all vsetvlis are explicit, go through and do block local - // DSE and peephole based demanded fields based transforms. Note that - // this *must* be done outside the main dataflow so long as we allow - // any cross block analysis within the dataflow. We can't have both - // demanded fields based mutation and non-local analysis in the - // dataflow at the same time without introducing inconsistencies. - for (MachineBasicBlock &MBB : MF) - doLocalPostpass(MBB); - // Insert PseudoReadVL after VLEFF/VLSEGFF and replace it with the vl output // of VLEFF/VLSEGFF. for (MachineBasicBlock &MBB : MF) @@ -1683,3 +1755,29 @@ bool RISCVInsertVSETVLI::runOnMachineFunction(MachineFunction &MF) { FunctionPass *llvm::createRISCVInsertVSETVLIPass() { return new RISCVInsertVSETVLI(); } + +// Now that all vsetvlis are explicit, go through and do block local +// DSE and peephole based demanded fields based transforms. Note that +// this *must* be done outside the main dataflow so long as we allow +// any cross block analysis within the dataflow. We can't have both +// demanded fields based mutation and non-local analysis in the +// dataflow at the same time without introducing inconsistencies. +bool RISCVCoalesceVSETVLI::runOnMachineFunction(MachineFunction &MF) { + // Skip if the vector extension is not enabled. + ST = &MF.getSubtarget(); + if (!ST->hasVInstructions()) + return false; + TII = ST->getInstrInfo(); + MRI = &MF.getRegInfo(); + LIS = &getAnalysis(); + + bool Changed = false; + for (MachineBasicBlock &MBB : MF) + Changed |= coalesceVSETVLIs(MBB); + + return Changed; +} + +FunctionPass *llvm::createRISCVCoalesceVSETVLIPass() { + return new RISCVCoalesceVSETVLI(); +} diff --git a/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp b/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp index e487cc8b2e20c90fca5c945339171a99a06e6d0d..f72ba2d5c667b880f14e5f522c18b594943c35f7 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertWriteVXRM.cpp @@ -225,7 +225,8 @@ bool RISCVInsertWriteVXRM::computeVXRMChanges(const MachineBasicBlock &MBB) { continue; } - if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VXRM)) { + if (MI.isCall() || MI.isInlineAsm() || + MI.modifiesRegister(RISCV::VXRM, /*TRI=*/nullptr)) { if (!BBInfo.VXRMUse.isValid()) BBInfo.VXRMUse.setUnknown(); @@ -386,7 +387,8 @@ void RISCVInsertWriteVXRM::emitWriteVXRM(MachineBasicBlock &MBB) { continue; } - if (MI.isCall() || MI.isInlineAsm() || MI.modifiesRegister(RISCV::VXRM)) + if (MI.isCall() || MI.isInlineAsm() || + MI.modifiesRegister(RISCV::VXRM, /*TRI=*/nullptr)) Info.setUnknown(); } diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 70ac1f8a592e02d075f2ee24857ff56dba25eead..dac47d6f4154f3f4c7fbd24c32cc50b56dcdabf9 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -66,6 +66,13 @@ using namespace RISCV; } // namespace llvm::RISCVVPseudosTable +namespace llvm::RISCV { + +#define GET_RISCVMaskedPseudosTable_IMPL +#include "RISCVGenSearchableTables.inc" + +} // end namespace llvm::RISCV + RISCVInstrInfo::RISCVInstrInfo(RISCVSubtarget &STI) : RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP), STI(STI) {} @@ -239,7 +246,7 @@ static bool isConvertibleToVMV_V_V(const RISCVSubtarget &STI, } else if (MBBI->getNumDefs()) { // Check all the instructions which will change VL. // For example, vleff has implicit def VL. - if (MBBI->modifiesRegister(RISCV::VL)) + if (MBBI->modifiesRegister(RISCV::VL, /*TRI=*/nullptr)) return false; // Only converting whole register copies to vmv.v.v when the defining @@ -3546,8 +3553,8 @@ RISCV::isRVVSpillForZvlsseg(unsigned Opcode) { } bool RISCV::isFaultFirstLoad(const MachineInstr &MI) { - return MI.getNumExplicitDefs() == 2 && MI.modifiesRegister(RISCV::VL) && - !MI.isInlineAsm(); + return MI.getNumExplicitDefs() == 2 && + MI.modifiesRegister(RISCV::VL, /*TRI=*/nullptr) && !MI.isInlineAsm(); } bool RISCV::hasEqualFRM(const MachineInstr &MI1, const MachineInstr &MI2) { diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.h b/llvm/lib/Target/RISCV/RISCVInstrInfo.h index 70fe7da85be0e7495019fd7ca2532c2880080e4c..3b03d5efde6ef5e8f90ac6e764695ef01c1a9d93 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.h +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.h @@ -359,5 +359,17 @@ struct PseudoInfo { } // end namespace RISCVVPseudosTable +namespace RISCV { + +struct RISCVMaskedPseudoInfo { + uint16_t MaskedPseudo; + uint16_t UnmaskedPseudo; + uint8_t MaskOpIdx; + uint8_t MaskAffectsResult : 1; +}; +#define GET_RISCVMaskedPseudosTable_DECL +#include "RISCVGenSearchableTables.inc" +} // end namespace RISCV + } // end namespace llvm #endif diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index 435cd7f84c61228095d9c4558ad6c35b2d248756..e9715b40adc079a6968f02e5bb2d8f247168652d 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -3593,7 +3593,7 @@ multiclass VPseudoConversion { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); - let VLMul = MInfo.value in { + let VLMul = MInfo.value, SEW=sew in { def suffix : VPseudoUnaryNoMask; def suffix # "_MASK" : VPseudoUnaryMask, @@ -3607,7 +3607,7 @@ multiclass VPseudoConversionRoundingMode { - let VLMul = MInfo.value in { + let VLMul = MInfo.value, SEW=sew in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); def suffix : VPseudoUnaryNoMaskRoundingMode; def suffix # "_MASK" : VPseudoUnaryMaskRoundingMode { - let VLMul = MInfo.value in { + let VLMul = MInfo.value, SEW=sew in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); def suffix : VPseudoUnaryNoMask_FRM; diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td index 986148bca849502b033d9803af638e887c53270e..ffe2b7e27120847ee40c626984fd7a5eda46267b 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td @@ -747,6 +747,8 @@ foreach i = {1,2,3} in { defvar shxadd_uw = !cast("SH"#i#"ADD_UW"); def : Pat<(i64 (add_like_non_imm12 (shl (and GPR:$rs1, 0xFFFFFFFF), (i64 i)), (XLenVT GPR:$rs2))), (shxadd_uw GPR:$rs1, GPR:$rs2)>; + def : Pat<(i64 (riscv_shl_add (and GPR:$rs1, 0xFFFFFFFF), (i64 i), GPR:$rs2)), + (shxadd_uw GPR:$rs1, GPR:$rs2)>; } def : Pat<(i64 (add_like_non_imm12 (and (shl GPR:$rs1, (i64 1)), 0x1FFFFFFFF), (XLenVT GPR:$rs2))), diff --git a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp index ead91c5656be8b86898b16bf327908d54b8a14e0..788d8f9cfc853a0bac0ead9831641aeefefb1742 100644 --- a/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp +++ b/llvm/lib/Target/RISCV/RISCVOptWInstrs.cpp @@ -420,7 +420,7 @@ static bool isSignExtendedW(Register SrcReg, const RISCVSubtarget &ST, if (!MI) continue; - int OpNo = MI->findRegisterDefOperandIdx(Reg); + int OpNo = MI->findRegisterDefOperandIdx(Reg, /*TRI=*/nullptr); assert(OpNo != -1 && "Couldn't find register"); // If this is a sign extending operation we don't need to look any further. diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index ae1a6f179a49e31530f59ef567fe7f25e90743d2..0876f46728a10c836611f787d848301ac30603a8 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -91,11 +91,6 @@ static cl::opt cl::desc("Enable the loop data prefetch pass"), cl::init(true)); -static cl::opt - EnableSplitRegAlloc("riscv-split-regalloc", cl::Hidden, - cl::desc("Enable Split RegisterAlloc for RVV"), - cl::init(true)); - static cl::opt EnableMISchedLoadClustering( "riscv-misched-load-clustering", cl::Hidden, cl::desc("Enable load clustering in the machine scheduler"), @@ -121,6 +116,7 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVTarget() { initializeRISCVExpandPseudoPass(*PR); initializeRISCVFoldMasksPass(*PR); initializeRISCVInsertVSETVLIPass(*PR); + initializeRISCVCoalesceVSETVLIPass(*PR); initializeRISCVInsertReadWriteCSRPass(*PR); initializeRISCVInsertWriteVXRMPass(*PR); initializeRISCVDAGToDAGISelPass(*PR); @@ -392,16 +388,15 @@ FunctionPass *RISCVPassConfig::createRVVRegAllocPass(bool Optimized) { } bool RISCVPassConfig::addRegAssignAndRewriteFast() { - if (EnableSplitRegAlloc) - addPass(createRVVRegAllocPass(false)); + addPass(createRVVRegAllocPass(false)); + addPass(createRISCVCoalesceVSETVLIPass()); return TargetPassConfig::addRegAssignAndRewriteFast(); } bool RISCVPassConfig::addRegAssignAndRewriteOptimized() { - if (EnableSplitRegAlloc) { - addPass(createRVVRegAllocPass(true)); - addPass(createVirtRegRewriter(false)); - } + addPass(createRVVRegAllocPass(true)); + addPass(createVirtRegRewriter(false)); + addPass(createRISCVCoalesceVSETVLIPass()); return TargetPassConfig::addRegAssignAndRewriteOptimized(); } diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h index 2f9281ab89244729a9b91f3778082f7e4eaad84c..a4d1390875095855d427ef71b9b3bbbfa0062b01 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h +++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h @@ -210,7 +210,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); bool isElementTypeLegalForScalableVector(Type *Ty) const { diff --git a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp index 21a69fc3ad9b447751c9bf716727e03ea17f849c..9994a966c82c31d59fbd12dfe3a0f1a61e0517f4 100644 --- a/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVInstructionSelector.cpp @@ -646,6 +646,37 @@ bool SPIRVInstructionSelector::selectUnOp(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, unsigned Opcode) const { + if (STI.isOpenCLEnv() && I.getOperand(1).isReg()) { + Register SrcReg = I.getOperand(1).getReg(); + bool IsGV = false; + for (MachineRegisterInfo::def_instr_iterator DefIt = + MRI->def_instr_begin(SrcReg); + DefIt != MRI->def_instr_end(); DefIt = std::next(DefIt)) { + if ((*DefIt).getOpcode() == TargetOpcode::G_GLOBAL_VALUE) { + IsGV = true; + break; + } + } + if (IsGV) { + uint32_t SpecOpcode = 0; + switch (Opcode) { + case SPIRV::OpConvertPtrToU: + SpecOpcode = static_cast(SPIRV::Opcode::ConvertPtrToU); + break; + case SPIRV::OpConvertUToPtr: + SpecOpcode = static_cast(SPIRV::Opcode::ConvertUToPtr); + break; + } + if (SpecOpcode) + return BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(SPIRV::OpSpecConstantOp)) + .addDef(ResVReg) + .addUse(GR.getSPIRVTypeID(ResType)) + .addImm(SpecOpcode) + .addUse(SrcReg) + .constrainAllUses(TII, TRI, RBI); + } + } return selectUnOpWithSrc(ResVReg, ResType, I, I.getOperand(1).getReg(), Opcode); } @@ -1587,8 +1618,18 @@ bool SPIRVInstructionSelector::selectIToF(Register ResVReg, bool SPIRVInstructionSelector::selectExt(Register ResVReg, const SPIRVType *ResType, MachineInstr &I, bool IsSigned) const { - if (GR.isScalarOrVectorOfType(I.getOperand(1).getReg(), SPIRV::OpTypeBool)) + Register SrcReg = I.getOperand(1).getReg(); + if (GR.isScalarOrVectorOfType(SrcReg, SPIRV::OpTypeBool)) return selectSelect(ResVReg, ResType, I, IsSigned); + + SPIRVType *SrcType = GR.getSPIRVTypeForVReg(SrcReg); + if (SrcType == ResType) + return BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(TargetOpcode::COPY)) + .addDef(ResVReg) + .addUse(SrcReg) + .constrainAllUses(TII, TRI, RBI); + unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; return selectUnOp(ResVReg, ResType, I, Opcode); } @@ -1622,11 +1663,16 @@ bool SPIRVInstructionSelector::selectIntToBool(Register IntReg, bool SPIRVInstructionSelector::selectTrunc(Register ResVReg, const SPIRVType *ResType, MachineInstr &I) const { - if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool)) { - Register IntReg = I.getOperand(1).getReg(); - const SPIRVType *ArgType = GR.getSPIRVTypeForVReg(IntReg); + Register IntReg = I.getOperand(1).getReg(); + const SPIRVType *ArgType = GR.getSPIRVTypeForVReg(IntReg); + if (GR.isScalarOrVectorOfType(ResVReg, SPIRV::OpTypeBool)) return selectIntToBool(IntReg, ResVReg, I, ArgType, ResType); - } + if (ArgType == ResType) + return BuildMI(*I.getParent(), I, I.getDebugLoc(), + TII.get(TargetOpcode::COPY)) + .addDef(ResVReg) + .addUse(IntReg) + .constrainAllUses(TII, TRI, RBI); bool IsSigned = GR.isScalarOrVectorSigned(ResType); unsigned Opcode = IsSigned ? SPIRV::OpSConvert : SPIRV::OpUConvert; return selectUnOp(ResVReg, ResType, I, Opcode); diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index d16f6d5bf67ef420ea50d95957be5e0567525ae7..9ee0b38d22332a1ed6b6cfe233326ff87e112b9a 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -224,6 +224,10 @@ static SPIRVType *propagateSPIRVType(MachineInstr *MI, SPIRVGlobalRegistry *GR, } break; } + case TargetOpcode::G_PTRTOINT: + SpirvTy = GR->getOrCreateSPIRVIntegerType( + MRI.getType(Reg).getScalarSizeInBits(), MIB); + break; case TargetOpcode::G_TRUNC: case TargetOpcode::G_ADDRSPACE_CAST: case TargetOpcode::G_PTR_ADD: @@ -252,6 +256,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI, if (!SpvType) SpvType = GR.getSPIRVTypeForVReg(SrcReg); assert(SpvType && "VReg is expected to have SPIRV type"); + LLT SrcLLT = MRI.getType(SrcReg); LLT NewT = LLT::scalar(32); bool IsFloat = SpvType->getOpcode() == SPIRV::OpTypeFloat; bool IsVectorFloat = @@ -261,10 +266,10 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI, IsFloat |= IsVectorFloat; auto GetIdOp = IsFloat ? SPIRV::GET_fID : SPIRV::GET_ID; auto DstClass = IsFloat ? &SPIRV::fIDRegClass : &SPIRV::IDRegClass; - if (MRI.getType(SrcReg).isPointer()) { + if (SrcLLT.isPointer()) { unsigned PtrSz = GR.getPointerSize(); NewT = LLT::pointer(0, PtrSz); - bool IsVec = MRI.getType(SrcReg).isVector(); + bool IsVec = SrcLLT.isVector(); if (IsVec) NewT = LLT::fixed_vector(2, NewT); if (PtrSz == 64) { @@ -284,7 +289,7 @@ createNewIdReg(SPIRVType *SpvType, Register SrcReg, MachineRegisterInfo &MRI, DstClass = &SPIRV::pID32RegClass; } } - } else if (MRI.getType(SrcReg).isVector()) { + } else if (SrcLLT.isVector()) { NewT = LLT::fixed_vector(2, NewT); if (IsFloat) { GetIdOp = SPIRV::GET_vfID; @@ -440,6 +445,7 @@ static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, insertAssignInstr(Reg, Ty, nullptr, GR, MIB, MRI); } else if (MI.getOpcode() == TargetOpcode::G_TRUNC || MI.getOpcode() == TargetOpcode::G_ZEXT || + MI.getOpcode() == TargetOpcode::G_PTRTOINT || MI.getOpcode() == TargetOpcode::G_GLOBAL_VALUE || MI.getOpcode() == TargetOpcode::COPY || MI.getOpcode() == TargetOpcode::G_ADDRSPACE_CAST) { @@ -483,7 +489,8 @@ static void processInstrsWithTypeFolding(MachineFunction &MF, continue; Register DstReg = MI.getOperand(0).getReg(); bool IsDstPtr = MRI.getType(DstReg).isPointer(); - if (IsDstPtr || MRI.getType(DstReg).isVector()) + bool isDstVec = MRI.getType(DstReg).isVector(); + if (IsDstPtr || isDstVec) MRI.setRegClass(DstReg, &SPIRV::IDRegClass); // Don't need to reset type of register holding constant and used in // G_ADDRSPACE_CAST, since it breaks legalizer. diff --git a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td index ff102e318469f4e5cb1b52e1e90330e6980dce4f..31e19ad8630cdd6658a441d54881354d294ba520 100644 --- a/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td +++ b/llvm/lib/Target/SPIRV/SPIRVSymbolicOperands.td @@ -1612,3 +1612,5 @@ multiclass OpcodeOperand value> { defm InBoundsPtrAccessChain : OpcodeOperand<70>; defm PtrCastToGeneric : OpcodeOperand<121>; defm Bitcast : OpcodeOperand<124>; +defm ConvertPtrToU : OpcodeOperand<117>; +defm ConvertUToPtr : OpcodeOperand<120>; diff --git a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp index e58f50e471fc0ece73007f873d37a118e0f2624b..99067e3ef18732fcffb615481966147c7c5023d5 100644 --- a/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp +++ b/llvm/lib/Target/SystemZ/SystemZElimCompare.cpp @@ -633,7 +633,7 @@ bool SystemZElimCompare::fuseCompareOperations( RegMask = MBBI->getOperand(3).getRegMask(); // Clear out all current operands. - int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI); + int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, TRI, false); assert(CCUse >= 0 && "BRC/BCR must use CC"); Branch->removeOperand(CCUse); // Remove regmask (sibcall). @@ -707,11 +707,11 @@ bool SystemZElimCompare::processBlock(MachineBasicBlock &MBB) { continue; } - if (MI.definesRegister(SystemZ::CC)) { + if (MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr)) { CCUsers.clear(); CompleteCCUsers = true; } - if (MI.readsRegister(SystemZ::CC) && CompleteCCUsers) + if (MI.readsRegister(SystemZ::CC, /*TRI=*/nullptr) && CompleteCCUsers) CCUsers.push_back(&MI); } return Changed; diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp index 48956b571dc3b39f50dfd81b48967ae75ea42c48..115f34fa7751da539d1b6c753936a8681b06d9bd 100644 --- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp +++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp @@ -8092,9 +8092,9 @@ static bool checkCCKill(MachineInstr &MI, MachineBasicBlock *MBB) { MachineBasicBlock::iterator miI(std::next(MachineBasicBlock::iterator(MI))); for (MachineBasicBlock::iterator miE = MBB->end(); miI != miE; ++miI) { const MachineInstr& mi = *miI; - if (mi.readsRegister(SystemZ::CC)) + if (mi.readsRegister(SystemZ::CC, /*TRI=*/nullptr)) return false; - if (mi.definesRegister(SystemZ::CC)) + if (mi.definesRegister(SystemZ::CC, /*TRI=*/nullptr)) break; // Should have kill-flag - update below. } @@ -8233,7 +8233,8 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI, } break; } - if (NextMI.definesRegister(SystemZ::CC) || NextMI.usesCustomInsertionHook()) + if (NextMI.definesRegister(SystemZ::CC, /*TRI=*/nullptr) || + NextMI.usesCustomInsertionHook()) break; bool User = false; for (auto *SelMI : Selects) @@ -8251,8 +8252,8 @@ SystemZTargetLowering::emitSelect(MachineInstr &MI, } MachineInstr *LastMI = Selects.back(); - bool CCKilled = - (LastMI->killsRegister(SystemZ::CC) || checkCCKill(*LastMI, MBB)); + bool CCKilled = (LastMI->killsRegister(SystemZ::CC, /*TRI=*/nullptr) || + checkCCKill(*LastMI, MBB)); MachineBasicBlock *StartMBB = MBB; MachineBasicBlock *JoinMBB = SystemZ::splitBlockAfter(LastMI, MBB); MachineBasicBlock *FalseMBB = SystemZ::emitBlockAfter(StartMBB); @@ -8352,7 +8353,8 @@ MachineBasicBlock *SystemZTargetLowering::emitCondStore(MachineInstr &MI, // Unless CC was killed in the CondStore instruction, mark it as // live-in to both FalseMBB and JoinMBB. - if (!MI.killsRegister(SystemZ::CC) && !checkCCKill(MI, JoinMBB)) { + if (!MI.killsRegister(SystemZ::CC, /*TRI=*/nullptr) && + !checkCCKill(MI, JoinMBB)) { FalseMBB->addLiveIn(SystemZ::CC); JoinMBB->addLiveIn(SystemZ::CC); } @@ -8755,7 +8757,7 @@ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI, // If the CC def wasn't dead in the ATOMIC_CMP_SWAPW, mark CC as live-in // to the block after the loop. At this point, CC may have been defined // either by the CR in LoopMBB or by the CS in SetMBB. - if (!MI.registerDefIsDead(SystemZ::CC)) + if (!MI.registerDefIsDead(SystemZ::CC, /*TRI=*/nullptr)) DoneMBB->addLiveIn(SystemZ::CC); MI.eraseFromParent(); diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp index 950548abcfa92c62200adbcb7dce2134453a8f97..6b75c30943b40ae24e949d7cf61ee1c284de48d5 100644 --- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp +++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp @@ -938,8 +938,9 @@ static LogicOp interpretAndImmediate(unsigned Opcode) { } static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) { - if (OldMI->registerDefIsDead(SystemZ::CC)) { - MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC); + if (OldMI->registerDefIsDead(SystemZ::CC, /*TRI=*/nullptr)) { + MachineOperand *CCDef = + NewMI->findRegisterDefOperand(SystemZ::CC, /*TRI=*/nullptr); if (CCDef != nullptr) CCDef->setIsDead(true); } @@ -1034,7 +1035,8 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl( .addFrameIndex(FrameIndex) .addImm(0) .addImm(MI.getOperand(2).getImm()); - BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true); + BuiltMI->findRegisterDefOperand(SystemZ::CC, /*TRI=*/nullptr) + ->setIsDead(true); CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator()); return BuiltMI; } @@ -1195,7 +1197,7 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl( unsigned NumOps = MI.getNumExplicitOperands(); int MemOpcode = SystemZ::getMemOpcode(Opcode); if (MemOpcode == -1 || - (CCLiveAtMI && !MI.definesRegister(SystemZ::CC) && + (CCLiveAtMI && !MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr) && get(MemOpcode).hasImplicitDefOfPhysReg(SystemZ::CC))) return nullptr; @@ -1303,9 +1305,9 @@ MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl( MIB.addImm(CCValid); MIB.addImm(NeedsCommute ? CCMask ^ CCValid : CCMask); } - if (MIB->definesRegister(SystemZ::CC) && - (!MI.definesRegister(SystemZ::CC) || - MI.registerDefIsDead(SystemZ::CC))) { + if (MIB->definesRegister(SystemZ::CC, /*TRI=*/nullptr) && + (!MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr) || + MI.registerDefIsDead(SystemZ::CC, /*TRI=*/nullptr))) { MIB->addRegisterDead(SystemZ::CC, TRI); if (CCLiveRange) CCLiveRange->createDeadDef(MISlot, LIS->getVNInfoAllocator()); @@ -1861,14 +1863,14 @@ prepareCompareSwapOperands(MachineBasicBlock::iterator const MBBI) const { bool CCLive = true; SmallVector CCUsers; for (MachineInstr &MI : llvm::make_range(std::next(MBBI), MBB->end())) { - if (MI.readsRegister(SystemZ::CC)) { + if (MI.readsRegister(SystemZ::CC, /*TRI=*/nullptr)) { unsigned Flags = MI.getDesc().TSFlags; if ((Flags & SystemZII::CCMaskFirst) || (Flags & SystemZII::CCMaskLast)) CCUsers.push_back(&MI); else return false; } - if (MI.definesRegister(SystemZ::CC)) { + if (MI.definesRegister(SystemZ::CC, /*TRI=*/nullptr)) { CCLive = false; break; } diff --git a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h index 696d887c1d5db8001cca83e22a685db619220129..3cf4a69ac2818643936cd90fad902bdb23fd9a5a 100644 --- a/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h +++ b/llvm/lib/Target/SystemZ/SystemZTargetTransformInfo.h @@ -89,7 +89,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, ArrayRef Mask, diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp index a2a054127d5f65a139bee50d065c0a458a44fb2d..da3717499689da9452a56486829e67a760d8f534 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyDebugValueManager.cpp @@ -37,7 +37,7 @@ WebAssemblyDebugValueManager::WebAssemblyDebugValueManager(MachineInstr *Def) ME = Def->getParent()->end(); MI != ME; ++MI) { // If another definition appears, stop - if (MI->definesRegister(CurrentReg)) + if (MI->definesRegister(CurrentReg, /*TRI=*/nullptr)) break; if (MI->isDebugValue() && MI->hasDebugOperandForReg(CurrentReg)) DbgValues.push_back(&*MI); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp index 3046f9476f91c34acf81a5ef57e08eb9e249d01b..ef174e1716ef1e1e149fc4bca601fe21eaec115e 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyRegStackify.cpp @@ -80,13 +80,13 @@ FunctionPass *llvm::createWebAssemblyRegStackify() { // the expression stack. static void imposeStackOrdering(MachineInstr *MI) { // Write the opaque VALUE_STACK register. - if (!MI->definesRegister(WebAssembly::VALUE_STACK)) + if (!MI->definesRegister(WebAssembly::VALUE_STACK, /*TRI=*/nullptr)) MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, /*isDef=*/true, /*isImp=*/true)); // Also read the opaque VALUE_STACK register. - if (!MI->readsRegister(WebAssembly::VALUE_STACK)) + if (!MI->readsRegister(WebAssembly::VALUE_STACK, /*TRI=*/nullptr)) MI->addOperand(MachineOperand::CreateReg(WebAssembly::VALUE_STACK, /*isDef=*/false, /*isImp=*/true)); @@ -371,8 +371,8 @@ static bool isSafeToMove(const MachineOperand *Def, const MachineOperand *Use, Register Reg = MO.getReg(); // If the register is dead here and at Insert, ignore it. - if (MO.isDead() && Insert->definesRegister(Reg) && - !Insert->readsRegister(Reg)) + if (MO.isDead() && Insert->definesRegister(Reg, /*TRI=*/nullptr) && + !Insert->readsRegister(Reg, /*TRI=*/nullptr)) continue; if (Reg.isPhysical()) { @@ -864,7 +864,8 @@ bool WebAssemblyRegStackify::runOnMachineFunction(MachineFunction &MF) { if (WebAssembly::isArgument(DefI->getOpcode())) continue; - MachineOperand *Def = DefI->findRegisterDefOperand(Reg); + MachineOperand *Def = + DefI->findRegisterDefOperand(Reg, /*TRI=*/nullptr); assert(Def != nullptr); // Decide which strategy to take. Prefer to move a single-use value diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h index a803fe5c1bbecc153a442e2388d1b477ed54f775..801f905d377ed921b8bd0a8ed4e89b3ea8f3d363 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetTransformInfo.h @@ -63,7 +63,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); using BaseT::getVectorInstrCost; InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val, diff --git a/llvm/lib/Target/X86/X86CmovConversion.cpp b/llvm/lib/Target/X86/X86CmovConversion.cpp index 8dc3b91f08e2920858c412419e5ea418e79f7866..297acf07115a9bf11313c68b07cc7102289be655 100644 --- a/llvm/lib/Target/X86/X86CmovConversion.cpp +++ b/llvm/lib/Target/X86/X86CmovConversion.cpp @@ -355,7 +355,7 @@ bool X86CmovConverterPass::collectCmovCandidates( FoundNonCMOVInst = true; // Check if this instruction define EFLAGS, to determine end of processed // range, as there would be no more instructions using current EFLAGS def. - if (I.definesRegister(X86::EFLAGS)) { + if (I.definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) { // Check if current processed CMOV-group should not be skipped and add // it as a CMOV-group-candidate. if (!SkipGroup) @@ -582,7 +582,7 @@ bool X86CmovConverterPass::checkForProfitableCmovCandidates( } static bool checkEFLAGSLive(MachineInstr *MI) { - if (MI->killsRegister(X86::EFLAGS)) + if (MI->killsRegister(X86::EFLAGS, /*TRI=*/nullptr)) return false; // The EFLAGS operand of MI might be missing a kill marker. @@ -592,9 +592,9 @@ static bool checkEFLAGSLive(MachineInstr *MI) { // Scan forward through BB for a use/def of EFLAGS. for (auto I = std::next(ItrMI), E = BB->end(); I != E; ++I) { - if (I->readsRegister(X86::EFLAGS)) + if (I->readsRegister(X86::EFLAGS, /*TRI=*/nullptr)) return true; - if (I->definesRegister(X86::EFLAGS)) + if (I->definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) return false; } diff --git a/llvm/lib/Target/X86/X86FixupSetCC.cpp b/llvm/lib/Target/X86/X86FixupSetCC.cpp index 269f8ce6bd7a421302530eea33a9241624bd456a..5c7105988070c37fa237f36dea1a1a4bade79837 100644 --- a/llvm/lib/Target/X86/X86FixupSetCC.cpp +++ b/llvm/lib/Target/X86/X86FixupSetCC.cpp @@ -69,7 +69,7 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) { MachineInstr *FlagsDefMI = nullptr; for (auto &MI : MBB) { // Remember the most recent preceding eflags defining instruction. - if (MI.definesRegister(X86::EFLAGS)) + if (MI.definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) FlagsDefMI = &MI; // Find a setcc that is used by a zext. @@ -94,7 +94,7 @@ bool X86FixupSetCCPass::runOnMachineFunction(MachineFunction &MF) { // it, itself, by definition, clobbers eflags. But it may happen that // FlagsDefMI also *uses* eflags, in which case the transformation is // invalid. - if (FlagsDefMI->readsRegister(X86::EFLAGS)) + if (FlagsDefMI->readsRegister(X86::EFLAGS, /*TRI=*/nullptr)) continue; // On 32-bit, we need to be careful to force an ABCD register. diff --git a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp index d96613d7bb7efcfb599859ea65f199588cb7d5e5..78355d3550833ef1ed23733eb3ff15e66521c1ae 100644 --- a/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp +++ b/llvm/lib/Target/X86/X86FlagsCopyLowering.cpp @@ -442,7 +442,8 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { llvm::reverse(llvm::make_range(Begin, End)), [&](MachineInstr &MI) { // Flag any instruction (other than the copy we are // currently rewriting) that defs EFLAGS. - return &MI != CopyI && MI.findRegisterDefOperand(X86::EFLAGS); + return &MI != CopyI && + MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); }); }; auto HasEFLAGSClobberPath = [&](MachineBasicBlock *BeginMBB, @@ -500,7 +501,7 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { auto DefIt = llvm::find_if( llvm::reverse(llvm::make_range(TestMBB->instr_begin(), TestPos)), [&](MachineInstr &MI) { - return MI.findRegisterDefOperand(X86::EFLAGS); + return MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); }); if (DefIt.base() != TestMBB->instr_begin()) { dbgs() << " Using EFLAGS defined by: "; @@ -562,9 +563,10 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { break; } - MachineOperand *FlagUse = MI.findRegisterUseOperand(X86::EFLAGS); + MachineOperand *FlagUse = + MI.findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr); if (!FlagUse) { - if (MI.findRegisterDefOperand(X86::EFLAGS)) { + if (MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)) { // If EFLAGS are defined, it's as-if they were killed. We can stop // scanning here. // @@ -615,7 +617,7 @@ bool X86FlagsCopyLoweringPass::runOnMachineFunction(MachineFunction &MF) { rewriteCopy(MI, *FlagUse, CopyDefI); } else { // We assume all other instructions that use flags also def them. - assert(MI.findRegisterDefOperand(X86::EFLAGS) && + assert(MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr) && "Expected a def of EFLAGS for this instruction!"); // NB!!! Several arithmetic instructions only *partially* update @@ -734,7 +736,7 @@ CondRegArray X86FlagsCopyLoweringPass::collectCondsInRegs( // Stop scanning when we see the first definition of the EFLAGS as prior to // this we would potentially capture the wrong flag state. - if (MI.findRegisterDefOperand(X86::EFLAGS)) + if (MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)) break; } return CondRegs; @@ -914,7 +916,7 @@ void X86FlagsCopyLoweringPass::rewriteCondJmp( // Rewrite the jump to use the !ZF flag from the test, and kill its use of // flags afterward. JmpI.getOperand(1).setImm(Inverted ? X86::COND_E : X86::COND_NE); - JmpI.findRegisterUseOperand(X86::EFLAGS)->setIsKill(true); + JmpI.findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->setIsKill(true); LLVM_DEBUG(dbgs() << " fixed jCC: "; JmpI.dump()); } diff --git a/llvm/lib/Target/X86/X86FloatingPoint.cpp b/llvm/lib/Target/X86/X86FloatingPoint.cpp index 260879ffaa4f120aac8824e88cb77542163618f9..02c3ca9839fc2d81aacbebe4d7e5fda51fd5a896 100644 --- a/llvm/lib/Target/X86/X86FloatingPoint.cpp +++ b/llvm/lib/Target/X86/X86FloatingPoint.cpp @@ -829,7 +829,8 @@ static const TableEntry PopTable[] = { }; static bool doesInstructionSetFPSW(MachineInstr &MI) { - if (const MachineOperand *MO = MI.findRegisterDefOperand(X86::FPSW)) + if (const MachineOperand *MO = + MI.findRegisterDefOperand(X86::FPSW, /*TRI=*/nullptr)) if (!MO->isDead()) return true; return false; @@ -872,7 +873,7 @@ void FPS::popStackAfter(MachineBasicBlock::iterator &I) { if (doesInstructionSetFPSW(MI)) { MachineBasicBlock &MBB = *MI.getParent(); MachineBasicBlock::iterator Next = getNextFPInstruction(I); - if (Next != MBB.end() && Next->readsRegister(X86::FPSW)) + if (Next != MBB.end() && Next->readsRegister(X86::FPSW, /*TRI=*/nullptr)) I = Next; } I = BuildMI(*MBB, ++I, dl, TII->get(X86::ST_FPrr)).addReg(X86::ST0); @@ -1082,9 +1083,10 @@ void FPS::handleReturn(MachineBasicBlock::iterator &I) { // FP Register uses must be kills unless there are two uses of the same // register, in which case only one will be a kill. assert(Op.isUse() && - (Op.isKill() || // Marked kill. - getFPReg(Op) == FirstFPRegOp || // Second instance. - MI.killsRegister(Op.getReg())) && // Later use is marked kill. + (Op.isKill() || // Marked kill. + getFPReg(Op) == FirstFPRegOp || // Second instance. + MI.killsRegister(Op.getReg(), + /*TRI=*/nullptr)) && // Later use is marked kill. "Ret only defs operands, and values aren't live beyond it"); if (FirstFPRegOp == ~0U) @@ -1181,7 +1183,7 @@ void FPS::handleOneArgFP(MachineBasicBlock::iterator &I) { // Is this the last use of the source register? unsigned Reg = getFPReg(MI.getOperand(NumOps - 1)); - bool KillsSrc = MI.killsRegister(X86::FP0 + Reg); + bool KillsSrc = MI.killsRegister(X86::FP0 + Reg, /*TRI=*/nullptr); // FISTP64m is strange because there isn't a non-popping versions. // If we have one _and_ we don't want to pop the operand, duplicate the value @@ -1244,7 +1246,7 @@ void FPS::handleOneArgFPRW(MachineBasicBlock::iterator &I) { // Is this the last use of the source register? unsigned Reg = getFPReg(MI.getOperand(1)); - bool KillsSrc = MI.killsRegister(X86::FP0 + Reg); + bool KillsSrc = MI.killsRegister(X86::FP0 + Reg, /*TRI=*/nullptr); if (KillsSrc) { // If this is the last use of the source register, just make sure it's on @@ -1355,8 +1357,8 @@ void FPS::handleTwoArgFP(MachineBasicBlock::iterator &I) { unsigned Dest = getFPReg(MI.getOperand(0)); unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1)); - bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); - bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); + bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0, /*TRI=*/nullptr); + bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1, /*TRI=*/nullptr); const DebugLoc &dl = MI.getDebugLoc(); unsigned TOS = getStackEntry(0); @@ -1453,8 +1455,8 @@ void FPS::handleCompareFP(MachineBasicBlock::iterator &I) { assert(NumOperands == 2 && "Illegal FUCOM* instruction!"); unsigned Op0 = getFPReg(MI.getOperand(NumOperands - 2)); unsigned Op1 = getFPReg(MI.getOperand(NumOperands - 1)); - bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0); - bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); + bool KillsOp0 = MI.killsRegister(X86::FP0 + Op0, /*TRI=*/nullptr); + bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1, /*TRI=*/nullptr); // Make sure the first operand is on the top of stack, the other one can be // anywhere. @@ -1480,7 +1482,7 @@ void FPS::handleCondMovFP(MachineBasicBlock::iterator &I) { unsigned Op0 = getFPReg(MI.getOperand(0)); unsigned Op1 = getFPReg(MI.getOperand(2)); - bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1); + bool KillsOp1 = MI.killsRegister(X86::FP0 + Op1, /*TRI=*/nullptr); // The first operand *must* be on the top of the stack. moveToTop(Op0, I); @@ -1524,7 +1526,7 @@ void FPS::handleSpecialFP(MachineBasicBlock::iterator &Inst) { // We handle three kinds of copies: FP <- FP, FP <- ST, and ST <- FP. const MachineOperand &MO1 = MI.getOperand(1); const MachineOperand &MO0 = MI.getOperand(0); - bool KillsSrc = MI.killsRegister(MO1.getReg()); + bool KillsSrc = MI.killsRegister(MO1.getReg(), /*TRI=*/nullptr); // FP <- FP copy. unsigned DstFP = getFPReg(MO0); diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index a4df05e1bd03ca1a331d17491393d02768842fa4..bb43cbe15f52258e18829a9f0460e5a24c1a807e 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -20459,8 +20459,7 @@ static SDValue matchTruncateWithPACK(unsigned &PackOpcode, EVT DstVT, // the truncation then we can use PACKSS by converting the srl to a sra. // SimplifyDemandedBits often relaxes sra to srl so we need to reverse it. if (In.getOpcode() == ISD::SRL && In->hasOneUse()) - if (const APInt *ShAmt = DAG.getValidShiftAmountConstant( - In, APInt::getAllOnes(SrcVT.getVectorNumElements()))) { + if (const APInt *ShAmt = DAG.getValidShiftAmountConstant(In)) { if (*ShAmt == MinSignBits) { PackOpcode = X86ISD::PACKSS; return DAG.getNode(ISD::SRA, DL, SrcVT, In->ops()); @@ -34228,10 +34227,10 @@ static bool isEFLAGSLiveAfter(MachineBasicBlock::iterator Itr, MachineBasicBlock *BB) { // Scan forward through BB for a use/def of EFLAGS. for (const MachineInstr &mi : llvm::make_range(std::next(Itr), BB->end())) { - if (mi.readsRegister(X86::EFLAGS)) + if (mi.readsRegister(X86::EFLAGS, /*TRI=*/nullptr)) return true; // If we found a def, we can stop searching. - if (mi.definesRegister(X86::EFLAGS)) + if (mi.definesRegister(X86::EFLAGS, /*TRI=*/nullptr)) return false; } @@ -34817,7 +34816,7 @@ X86TargetLowering::EmitLoweredCascadedSelect(MachineInstr &FirstCMOV, // If the EFLAGS register isn't dead in the terminator, then claim that it's // live into the sink and copy blocks. const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); - if (!SecondCascadedCMOV.killsRegister(X86::EFLAGS) && + if (!SecondCascadedCMOV.killsRegister(X86::EFLAGS, /*TRI=*/nullptr) && !checkAndUpdateEFLAGSKill(SecondCascadedCMOV, ThisMBB, TRI)) { SecondInsertedMBB->addLiveIn(X86::EFLAGS); SinkMBB->addLiveIn(X86::EFLAGS); @@ -34973,7 +34972,7 @@ X86TargetLowering::EmitLoweredSelect(MachineInstr &MI, // If the EFLAGS register isn't dead in the terminator, then claim that it's // live into the sink and copy blocks. const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); - if (!LastCMOV->killsRegister(X86::EFLAGS) && + if (!LastCMOV->killsRegister(X86::EFLAGS, /*TRI=*/nullptr) && !checkAndUpdateEFLAGSKill(LastCMOV, ThisMBB, TRI)) { FalseMBB->addLiveIn(X86::EFLAGS); SinkMBB->addLiveIn(X86::EFLAGS); @@ -36552,10 +36551,11 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, // four operand definitions that are E[ABCD] registers. We skip them and // then insert the LEA. MachineBasicBlock::reverse_iterator RMBBI(MI.getReverseIterator()); - while (RMBBI != BB->rend() && (RMBBI->definesRegister(X86::EAX) || - RMBBI->definesRegister(X86::EBX) || - RMBBI->definesRegister(X86::ECX) || - RMBBI->definesRegister(X86::EDX))) { + while (RMBBI != BB->rend() && + (RMBBI->definesRegister(X86::EAX, /*TRI=*/nullptr) || + RMBBI->definesRegister(X86::EBX, /*TRI=*/nullptr) || + RMBBI->definesRegister(X86::ECX, /*TRI=*/nullptr) || + RMBBI->definesRegister(X86::EDX, /*TRI=*/nullptr))) { ++RMBBI; } MachineBasicBlock::iterator MBBI(RMBBI); diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp index 510b08f9901a22f623d7bcd9beda8f52c363c57d..3d80c43b571f9cc61c91edca26903fc06468c907 100644 --- a/llvm/lib/Target/X86/X86InstrInfo.cpp +++ b/llvm/lib/Target/X86/X86InstrInfo.cpp @@ -1168,7 +1168,7 @@ bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src, RC = Opc != X86::LEA32r ? &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass; } Register SrcReg = Src.getReg(); - isKill = MI.killsRegister(SrcReg); + isKill = MI.killsRegister(SrcReg, /*TRI=*/nullptr); // For both LEA64 and LEA32 the register already has essentially the right // type (32-bit or 64-bit) we may just need to forbid SP. @@ -3727,7 +3727,7 @@ bool X86InstrInfo::analyzeBranchImpl( // In practice we should never have an undef eflags operand, if we do // abort here as we are not prepared to preserve the flag. - if (I->findRegisterUseOperand(X86::EFLAGS)->isUndef()) + if (I->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->isUndef()) return true; // Working from the bottom, handle the first conditional branch. @@ -5472,7 +5472,8 @@ bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, Register SrcReg, } // Make sure Sub instruction defines EFLAGS and mark the def live. - MachineOperand *FlagDef = Sub->findRegisterDefOperand(X86::EFLAGS); + MachineOperand *FlagDef = + Sub->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); assert(FlagDef && "Unable to locate a def EFLAGS operand"); FlagDef->setIsDead(false); @@ -5629,7 +5630,7 @@ bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, return false; } - if (UseMI.findRegisterUseOperand(Reg)->getSubReg()) + if (UseMI.findRegisterUseOperand(Reg, /*TRI=*/nullptr)->getSubReg()) return false; // Immediate has larger code size than register. So avoid folding the // immediate if it has more than 1 use and we are optimizing for size. @@ -5676,7 +5677,8 @@ bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, if (!MakeChange) return true; UseMI.setDesc(get(X86::MOV32r0)); - UseMI.removeOperand(UseMI.findRegisterUseOperandIdx(Reg)); + UseMI.removeOperand( + UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr)); UseMI.addOperand(MachineOperand::CreateReg(X86::EFLAGS, /*isDef=*/true, /*isImp=*/true, /*isKill=*/false, @@ -5698,18 +5700,18 @@ bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, NewOpc == X86::SBB64ri32 || NewOpc == X86::SBB32ri || NewOpc == X86::SUB64ri32_ND || NewOpc == X86::SUB32ri_ND || NewOpc == X86::SBB64ri32_ND || NewOpc == X86::SBB32ri_ND) && - UseMI.findRegisterUseOperandIdx(Reg) != 2) + UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 2) return false; // For CMP instructions the immediate can only be at index 1. if (((NewOpc == X86::CMP64ri32 || NewOpc == X86::CMP32ri) || (NewOpc == X86::CCMP64ri32 || NewOpc == X86::CCMP32ri)) && - UseMI.findRegisterUseOperandIdx(Reg) != 1) + UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr) != 1) return false; using namespace X86; if (isSHL(Opc) || isSHR(Opc) || isSAR(Opc) || isROL(Opc) || isROR(Opc) || isRCL(Opc) || isRCR(Opc)) { - unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg); + unsigned RegIdx = UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr); if (RegIdx < 2) return false; if (!isInt<8>(ImmVal)) @@ -5733,13 +5735,15 @@ bool X86InstrInfo::foldImmediateImpl(MachineInstr &UseMI, MachineInstr *DefMI, if (!Modified) { // Modify the instruction. if (ImmVal == 0 && canConvert2Copy(NewOpc) && - UseMI.registerDefIsDead(X86::EFLAGS)) { + UseMI.registerDefIsDead(X86::EFLAGS, /*TRI=*/nullptr)) { // %100 = add %101, 0 // ==> // %100 = COPY %101 UseMI.setDesc(get(TargetOpcode::COPY)); - UseMI.removeOperand(UseMI.findRegisterUseOperandIdx(Reg)); - UseMI.removeOperand(UseMI.findRegisterDefOperandIdx(X86::EFLAGS)); + UseMI.removeOperand( + UseMI.findRegisterUseOperandIdx(Reg, /*TRI=*/nullptr)); + UseMI.removeOperand( + UseMI.findRegisterDefOperandIdx(X86::EFLAGS, /*TRI=*/nullptr)); UseMI.untieRegOperand(0); UseMI.clearFlag(MachineInstr::MIFlag::NoSWrap); UseMI.clearFlag(MachineInstr::MIFlag::NoUWrap); @@ -9538,7 +9542,8 @@ bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst, // not change anything because rearranging the operands could affect other // instructions that depend on the exact status flags (zero, sign, etc.) // that are set by using these particular operands with this operation. - const MachineOperand *FlagDef = Inst.findRegisterDefOperand(X86::EFLAGS); + const MachineOperand *FlagDef = + Inst.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); assert((Inst.getNumDefs() == 1 || FlagDef) && "Implicit def isn't flags?"); if (FlagDef && !FlagDef->isDead()) return false; @@ -10060,8 +10065,10 @@ void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &NewMI1, MachineInstr &NewMI2) const { // Integer instructions may define an implicit EFLAGS dest register operand. - MachineOperand *OldFlagDef1 = OldMI1.findRegisterDefOperand(X86::EFLAGS); - MachineOperand *OldFlagDef2 = OldMI2.findRegisterDefOperand(X86::EFLAGS); + MachineOperand *OldFlagDef1 = + OldMI1.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); + MachineOperand *OldFlagDef2 = + OldMI2.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); assert(!OldFlagDef1 == !OldFlagDef2 && "Unexpected instruction type for reassociation"); @@ -10072,8 +10079,10 @@ void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1, assert(OldFlagDef1->isDead() && OldFlagDef2->isDead() && "Must have dead EFLAGS operand in reassociable instruction"); - MachineOperand *NewFlagDef1 = NewMI1.findRegisterDefOperand(X86::EFLAGS); - MachineOperand *NewFlagDef2 = NewMI2.findRegisterDefOperand(X86::EFLAGS); + MachineOperand *NewFlagDef1 = + NewMI1.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); + MachineOperand *NewFlagDef2 = + NewMI2.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); assert(NewFlagDef1 && NewFlagDef2 && "Unexpected operand in reassociable instruction"); diff --git a/llvm/lib/Target/X86/X86MCInstLower.cpp b/llvm/lib/Target/X86/X86MCInstLower.cpp index e6510be6b9afd03c37b805529f3d5d76a68b9aed..1d699b42dc673676e9060c6d1e0072c82322e1b4 100644 --- a/llvm/lib/Target/X86/X86MCInstLower.cpp +++ b/llvm/lib/Target/X86/X86MCInstLower.cpp @@ -506,7 +506,8 @@ void X86MCInstLower::Lower(const MachineInstr *MI, MCInst &OutMI) const { // recognize as TZCNT, which has better performance than BSF. // BSF and TZCNT have different interpretations on ZF bit. So make sure // it won't be used later. - const MachineOperand *FlagDef = MI->findRegisterDefOperand(X86::EFLAGS); + const MachineOperand *FlagDef = + MI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); if (!MF.getFunction().hasOptSize() && FlagDef && FlagDef->isDead()) OutMI.setFlags(X86::IP_HAS_REPEAT); break; diff --git a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp index 69a54e7667b55377677d9e17e7f6aea32c044d42..489c8f4925243209215fe293f7eeb19b2965f2cf 100644 --- a/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp +++ b/llvm/lib/Target/X86/X86SpeculativeLoadHardening.cpp @@ -483,7 +483,7 @@ bool X86SpeculativeLoadHardeningPass::runOnMachineFunction( PredStateSubReg); ++NumInstsInserted; MachineOperand *ZeroEFLAGSDefOp = - ZeroI->findRegisterDefOperand(X86::EFLAGS); + ZeroI->findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr); assert(ZeroEFLAGSDefOp && ZeroEFLAGSDefOp->isImplicit() && "Must have an implicit def of EFLAGS!"); ZeroEFLAGSDefOp->setIsDead(true); @@ -762,7 +762,8 @@ X86SpeculativeLoadHardeningPass::tracePredStateThroughCFG( // If this is the last cmov and the EFLAGS weren't originally // live-in, mark them as killed. if (!LiveEFLAGS && Cond == Conds.back()) - CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true); + CMovI->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr) + ->setIsKill(true); ++NumInstsInserted; LLVM_DEBUG(dbgs() << " Inserting cmov: "; CMovI->dump(); @@ -1185,7 +1186,8 @@ X86SpeculativeLoadHardeningPass::tracePredStateThroughIndirectBranches( .addReg(PS->InitialReg) .addReg(PS->PoisonReg) .addImm(X86::COND_NE); - CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true); + CMovI->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr) + ->setIsKill(true); ++NumInstsInserted; LLVM_DEBUG(dbgs() << " Inserting cmov: "; CMovI->dump(); dbgs() << "\n"); CMovs.push_back(&*CMovI); @@ -1202,7 +1204,8 @@ X86SpeculativeLoadHardeningPass::tracePredStateThroughIndirectBranches( // Returns true if the MI has EFLAGS as a register def operand and it's live, // otherwise it returns false static bool isEFLAGSDefLive(const MachineInstr &MI) { - if (const MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { + if (const MachineOperand *DefOp = + MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)) { return !DefOp->isDead(); } return false; @@ -1213,7 +1216,8 @@ static bool isEFLAGSLive(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, // Check if EFLAGS are alive by seeing if there is a def of them or they // live-in, and then seeing if that def is in turn used. for (MachineInstr &MI : llvm::reverse(llvm::make_range(MBB.begin(), I))) { - if (MachineOperand *DefOp = MI.findRegisterDefOperand(X86::EFLAGS)) { + if (MachineOperand *DefOp = + MI.findRegisterDefOperand(X86::EFLAGS, /*TRI=*/nullptr)) { // If the def is dead, then EFLAGS is not live. if (DefOp->isDead()) return false; @@ -2182,7 +2186,7 @@ void X86SpeculativeLoadHardeningPass::tracePredStateThroughCall( .addReg(NewStateReg, RegState::Kill) .addReg(PS->PoisonReg) .addImm(X86::COND_NE); - CMovI->findRegisterUseOperand(X86::EFLAGS)->setIsKill(true); + CMovI->findRegisterUseOperand(X86::EFLAGS, /*TRI=*/nullptr)->setIsKill(true); ++NumInstsInserted; LLVM_DEBUG(dbgs() << " Inserting cmov: "; CMovI->dump(); dbgs() << "\n"); diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index 8ef9b4f86ffd7c25050536719527a2d7956ccb9b..b50193074573987478ffa16fc2d8abec13defc09 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -139,7 +139,7 @@ public: unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind, TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None}, TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None}, - ArrayRef Args = ArrayRef(), + ArrayRef Args = std::nullopt, const Instruction *CxtI = nullptr); InstructionCost getAltInstrCost(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1, diff --git a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp index 1fa00af2111e0c26901d1cacf924fafff67344e5..eaf0466302994ebc7f9e3424e734d2a73a5bb09a 100644 --- a/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp +++ b/llvm/lib/Target/Xtensa/AsmParser/XtensaAsmParser.cpp @@ -8,7 +8,9 @@ // //===----------------------------------------------------------------------===// +#include "MCTargetDesc/XtensaMCExpr.h" #include "MCTargetDesc/XtensaMCTargetDesc.h" +#include "MCTargetDesc/XtensaTargetStreamer.h" #include "TargetInfo/XtensaTargetInfo.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringSwitch.h" @@ -22,6 +24,7 @@ #include "llvm/MC/MCRegisterInfo.h" #include "llvm/MC/MCStreamer.h" #include "llvm/MC/MCSubtargetInfo.h" +#include "llvm/MC/MCSymbol.h" #include "llvm/MC/TargetRegistry.h" #include "llvm/Support/Casting.h" @@ -35,6 +38,12 @@ class XtensaAsmParser : public MCTargetAsmParser { SMLoc getLoc() const { return getParser().getTok().getLoc(); } + XtensaTargetStreamer &getTargetStreamer() { + MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer(); + return static_cast(TS); + } + + ParseStatus parseDirective(AsmToken DirectiveID) override; bool parseRegister(MCRegister &Reg, SMLoc &StartLoc, SMLoc &EndLoc) override; bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, OperandVector &Operands) override; @@ -45,6 +54,9 @@ class XtensaAsmParser : public MCTargetAsmParser { unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, unsigned Kind) override; + bool processInstruction(MCInst &Inst, SMLoc IDLoc, MCStreamer &Out, + const MCSubtargetInfo *STI); + // Auto-generated instruction matching functions #define GET_ASSEMBLER_HEADER #include "XtensaGenAsmMatcher.inc" @@ -62,6 +74,7 @@ class XtensaAsmParser : public MCTargetAsmParser { return ParseStatus::NoMatch; } ParseStatus parsePCRelTarget(OperandVector &Operands); + bool parseLiteralDirective(SMLoc L); public: enum XtensaMatchResultTy { @@ -148,7 +161,8 @@ public: bool isImm12() const { return isImm(-2048, 2047); } - bool isImm12m() const { return isImm(-2048, 2047); } + // Convert MOVI to literal load, when immediate is not in range (-2048, 2047) + bool isImm12m() const { return Kind == Immediate; } bool isOffset4m32() const { return isImm(0, 60) && @@ -348,6 +362,69 @@ static SMLoc RefineErrorLoc(const SMLoc Loc, const OperandVector &Operands, return Loc; } +bool XtensaAsmParser::processInstruction(MCInst &Inst, SMLoc IDLoc, + MCStreamer &Out, + const MCSubtargetInfo *STI) { + Inst.setLoc(IDLoc); + const unsigned Opcode = Inst.getOpcode(); + switch (Opcode) { + case Xtensa::L32R: { + const MCSymbolRefExpr *OpExpr = + static_cast(Inst.getOperand(1).getExpr()); + XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None; + const MCExpr *NewOpExpr = XtensaMCExpr::create(OpExpr, Kind, getContext()); + Inst.getOperand(1).setExpr(NewOpExpr); + break; + } + case Xtensa::MOVI: { + XtensaTargetStreamer &TS = this->getTargetStreamer(); + + // Expand MOVI operand + if (!Inst.getOperand(1).isExpr()) { + uint64_t ImmOp64 = Inst.getOperand(1).getImm(); + int32_t Imm = ImmOp64; + if (!isInt<12>(Imm)) { + XtensaTargetStreamer &TS = this->getTargetStreamer(); + MCInst TmpInst; + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(Xtensa::L32R); + const MCExpr *Value = MCConstantExpr::create(ImmOp64, getContext()); + MCSymbol *Sym = getContext().createTempSymbol(); + const MCExpr *Expr = MCSymbolRefExpr::create( + Sym, MCSymbolRefExpr::VK_None, getContext()); + const MCExpr *OpExpr = XtensaMCExpr::create( + Expr, XtensaMCExpr::VK_Xtensa_None, getContext()); + TmpInst.addOperand(Inst.getOperand(0)); + MCOperand Op1 = MCOperand::createExpr(OpExpr); + TmpInst.addOperand(Op1); + TS.emitLiteral(Sym, Value, true, IDLoc); + Inst = TmpInst; + } + } else { + MCInst TmpInst; + TmpInst.setLoc(IDLoc); + TmpInst.setOpcode(Xtensa::L32R); + const MCExpr *Value = Inst.getOperand(1).getExpr(); + MCSymbol *Sym = getContext().createTempSymbol(); + const MCExpr *Expr = + MCSymbolRefExpr::create(Sym, MCSymbolRefExpr::VK_None, getContext()); + const MCExpr *OpExpr = XtensaMCExpr::create( + Expr, XtensaMCExpr::VK_Xtensa_None, getContext()); + TmpInst.addOperand(Inst.getOperand(0)); + MCOperand Op1 = MCOperand::createExpr(OpExpr); + TmpInst.addOperand(Op1); + Inst = TmpInst; + TS.emitLiteral(Sym, Value, true, IDLoc); + } + break; + } + default: + break; + } + + return true; +} + bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, OperandVector &Operands, MCStreamer &Out, @@ -361,6 +438,7 @@ bool XtensaAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, default: break; case Match_Success: + processInstruction(Inst, IDLoc, Out, STI); Inst.setLoc(IDLoc); Out.emitInstruction(Inst, getSTI()); return false; @@ -686,6 +764,57 @@ bool XtensaAsmParser::ParseInstruction(ParseInstructionInfo &Info, return false; } +bool XtensaAsmParser::parseLiteralDirective(SMLoc L) { + MCAsmParser &Parser = getParser(); + const MCExpr *Value; + SMLoc LiteralLoc = getLexer().getLoc(); + XtensaTargetStreamer &TS = this->getTargetStreamer(); + + if (Parser.parseExpression(Value)) + return true; + + const MCSymbolRefExpr *SE = dyn_cast(Value); + + if (!SE) + return Error(LiteralLoc, "literal label must be a symbol"); + + if (Parser.parseComma()) + return true; + + SMLoc OpcodeLoc = getLexer().getLoc(); + if (parseOptionalToken(AsmToken::EndOfStatement)) + return Error(OpcodeLoc, "expected value"); + + if (Parser.parseExpression(Value)) + return true; + + if (parseEOL()) + return true; + + MCSymbol *Sym = getContext().getOrCreateSymbol(SE->getSymbol().getName()); + + TS.emitLiteral(Sym, Value, true, LiteralLoc); + + return false; +} + +ParseStatus XtensaAsmParser::parseDirective(AsmToken DirectiveID) { + StringRef IDVal = DirectiveID.getString(); + SMLoc Loc = getLexer().getLoc(); + + if (IDVal == ".literal_position") { + XtensaTargetStreamer &TS = this->getTargetStreamer(); + TS.emitLiteralPosition(); + return parseEOL(); + } + + if (IDVal == ".literal") { + return parseLiteralDirective(Loc); + } + + return ParseStatus::NoMatch; +} + // Force static initialization. extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaAsmParser() { RegisterMCAsmParser X(getTheXtensaTarget()); diff --git a/llvm/lib/Target/Xtensa/CMakeLists.txt b/llvm/lib/Target/Xtensa/CMakeLists.txt index 2064511e75b82e59eafbd8f67e7ee99c4662aeae..726efadc87c0b2555d5c3f2f1f54d66b7c185676 100644 --- a/llvm/lib/Target/Xtensa/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/CMakeLists.txt @@ -4,6 +4,7 @@ set(LLVM_TARGET_DEFINITIONS Xtensa.td) tablegen(LLVM XtensaGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM XtensaGenAsmWriter.inc -gen-asm-writer) +tablegen(LLVM XtensaGenCallingConv.inc -gen-callingconv) tablegen(LLVM XtensaGenDAGISel.inc -gen-dag-isel) tablegen(LLVM XtensaGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM XtensaGenInstrInfo.inc -gen-instr-info) @@ -15,6 +16,7 @@ add_public_tablegen_target(XtensaCommonTableGen) add_llvm_target(XtensaCodeGen XtensaAsmPrinter.cpp + XtensaConstantPoolValue.cpp XtensaFrameLowering.cpp XtensaInstrInfo.cpp XtensaISelDAGToDAG.cpp @@ -22,6 +24,7 @@ add_llvm_target(XtensaCodeGen XtensaRegisterInfo.cpp XtensaSubtarget.cpp XtensaTargetMachine.cpp + XtensaUtils.cpp LINK_COMPONENTS AsmPrinter diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt index 6841b44f9d569cdb10bc806b35dee22728920881..dc12863394c7ad0cf25437319d2d65c43d55ebae 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/CMakeLists.txt @@ -6,6 +6,7 @@ add_llvm_component_library(LLVMXtensaDesc XtensaMCCodeEmitter.cpp XtensaMCExpr.cpp XtensaMCTargetDesc.cpp + XtensaTargetStreamer.cpp LINK_COMPONENTS MC diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp index 48674d15bdfbe27b56c01625fe4ea3ee8bbe2258..87ef66ba742b6d5500df0dc70e651c7263ea96c4 100644 --- a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaMCTargetDesc.cpp @@ -8,9 +8,10 @@ // //===----------------------------------------------------------------------===// #include "XtensaMCTargetDesc.h" +#include "TargetInfo/XtensaTargetInfo.h" #include "XtensaInstPrinter.h" #include "XtensaMCAsmInfo.h" -#include "TargetInfo/XtensaTargetInfo.h" +#include "XtensaTargetStreamer.h" #include "llvm/ADT/STLExtras.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCInstrInfo.h" @@ -63,16 +64,29 @@ createXtensaMCSubtargetInfo(const Triple &TT, StringRef CPU, StringRef FS) { return createXtensaMCSubtargetInfoImpl(TT, CPU, CPU, FS); } +static MCTargetStreamer * +createXtensaAsmTargetStreamer(MCStreamer &S, formatted_raw_ostream &OS, + MCInstPrinter *InstPrint, bool isVerboseAsm) { + return new XtensaTargetAsmStreamer(S, OS); +} + +static MCTargetStreamer * +createXtensaObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) { + return new XtensaTargetELFStreamer(S); +} + extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() { // Register the MCAsmInfo. - TargetRegistry::RegisterMCAsmInfo(getTheXtensaTarget(), createXtensaMCAsmInfo); + TargetRegistry::RegisterMCAsmInfo(getTheXtensaTarget(), + createXtensaMCAsmInfo); // Register the MCCodeEmitter. TargetRegistry::RegisterMCCodeEmitter(getTheXtensaTarget(), createXtensaMCCodeEmitter); // Register the MCInstrInfo. - TargetRegistry::RegisterMCInstrInfo(getTheXtensaTarget(), createXtensaMCInstrInfo); + TargetRegistry::RegisterMCInstrInfo(getTheXtensaTarget(), + createXtensaMCInstrInfo); // Register the MCInstPrinter. TargetRegistry::RegisterMCInstPrinter(getTheXtensaTarget(), @@ -89,4 +103,12 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeXtensaTargetMC() { // Register the MCAsmBackend. TargetRegistry::RegisterMCAsmBackend(getTheXtensaTarget(), createXtensaMCAsmBackend); + + // Register the asm target streamer. + TargetRegistry::RegisterAsmTargetStreamer(getTheXtensaTarget(), + createXtensaAsmTargetStreamer); + + // Register the ELF target streamer. + TargetRegistry::RegisterObjectTargetStreamer( + getTheXtensaTarget(), createXtensaObjectTargetStreamer); } diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp new file mode 100644 index 0000000000000000000000000000000000000000..0ea70cff4d404495fc367b7b46d1796e9d96be1e --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.cpp @@ -0,0 +1,119 @@ +//===-- XtensaTargetStreamer.cpp - Xtensa Target Streamer Methods ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file provides Xtensa specific target streamer methods. +// +//===----------------------------------------------------------------------===// + +#include "XtensaTargetStreamer.h" +#include "XtensaInstPrinter.h" +#include "llvm/BinaryFormat/ELF.h" +#include "llvm/MC/MCAssembler.h" +#include "llvm/MC/MCContext.h" +#include "llvm/MC/MCObjectFileInfo.h" +#include "llvm/MC/MCSectionELF.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/FormattedStream.h" + +using namespace llvm; + +static std::string getLiteralSectionName(StringRef CSectionName) { + std::size_t Pos = CSectionName.find(".text"); + std::string SectionName; + if (Pos != std::string::npos) { + SectionName = CSectionName.substr(0, Pos); + + if (Pos > 0) + SectionName += ".text"; + + CSectionName = CSectionName.drop_front(Pos); + CSectionName.consume_front(".text"); + + SectionName += ".literal"; + SectionName += CSectionName; + } else { + SectionName = CSectionName; + SectionName += ".literal"; + } + return SectionName; +} + +XtensaTargetStreamer::XtensaTargetStreamer(MCStreamer &S) + : MCTargetStreamer(S) {} + +XtensaTargetAsmStreamer::XtensaTargetAsmStreamer(MCStreamer &S, + formatted_raw_ostream &OS) + : XtensaTargetStreamer(S), OS(OS) {} + +void XtensaTargetAsmStreamer::emitLiteral(MCSymbol *LblSym, const MCExpr *Value, + bool SwitchLiteralSection, SMLoc L) { + SmallString<60> Str; + raw_svector_ostream LiteralStr(Str); + + LiteralStr << "\t.literal " << LblSym->getName() << ", "; + + if (auto CE = dyn_cast(Value)) { + LiteralStr << CE->getValue() << "\n"; + } else if (auto SRE = dyn_cast(Value)) { + const MCSymbol &Sym = SRE->getSymbol(); + LiteralStr << Sym.getName() << "\n"; + } else { + llvm_unreachable("unexpected constant pool entry type"); + } + + OS << LiteralStr.str(); +} + +void XtensaTargetAsmStreamer::emitLiteralPosition() { + OS << "\t.literal_position\n"; +} + +void XtensaTargetAsmStreamer::startLiteralSection(MCSection *BaseSection) { + emitLiteralPosition(); +} + +XtensaTargetELFStreamer::XtensaTargetELFStreamer(MCStreamer &S) + : XtensaTargetStreamer(S) {} + +void XtensaTargetELFStreamer::emitLiteral(MCSymbol *LblSym, const MCExpr *Value, + bool SwitchLiteralSection, SMLoc L) { + MCStreamer &OutStreamer = getStreamer(); + if (SwitchLiteralSection) { + MCContext &Context = OutStreamer.getContext(); + auto *CS = static_cast(OutStreamer.getCurrentSectionOnly()); + std::string SectionName = getLiteralSectionName(CS->getName()); + + MCSection *ConstSection = Context.getELFSection( + SectionName, ELF::SHT_PROGBITS, ELF::SHF_EXECINSTR | ELF::SHF_ALLOC); + + OutStreamer.pushSection(); + OutStreamer.switchSection(ConstSection); + } + + OutStreamer.emitLabel(LblSym, L); + OutStreamer.emitValue(Value, 4, L); + + if (SwitchLiteralSection) { + OutStreamer.popSection(); + } +} + +void XtensaTargetELFStreamer::startLiteralSection(MCSection *BaseSection) { + MCContext &Context = getStreamer().getContext(); + + std::string SectionName = getLiteralSectionName(BaseSection->getName()); + + MCSection *ConstSection = Context.getELFSection( + SectionName, ELF::SHT_PROGBITS, ELF::SHF_EXECINSTR | ELF::SHF_ALLOC); + + ConstSection->setAlignment(Align(4)); +} + +MCELFStreamer &XtensaTargetELFStreamer::getStreamer() { + return static_cast(Streamer); +} diff --git a/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h new file mode 100644 index 0000000000000000000000000000000000000000..817940e880b3c42056f938bb3a8a6709e5568d24 --- /dev/null +++ b/llvm/lib/Target/Xtensa/MCTargetDesc/XtensaTargetStreamer.h @@ -0,0 +1,58 @@ +//===-- XtensaTargetStreamer.h - Xtensa Target Streamer --------*- C++ -*--===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H +#define LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H + +#include "llvm/MC/MCELFStreamer.h" +#include "llvm/MC/MCStreamer.h" +#include "llvm/Support/SMLoc.h" + +namespace llvm { +class formatted_raw_ostream; + +class XtensaTargetStreamer : public MCTargetStreamer { +public: + XtensaTargetStreamer(MCStreamer &S); + + // Emit literal label and literal Value to the literal section. If literal + // section is not switched yet (SwitchLiteralSection is true) then switch to + // literal section. + virtual void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, + bool SwitchLiteralSection, SMLoc L = SMLoc()) = 0; + + virtual void emitLiteralPosition() = 0; + + // Switch to the literal section. The BaseSection name is used to construct + // literal section name. + virtual void startLiteralSection(MCSection *BaseSection) = 0; +}; + +class XtensaTargetAsmStreamer : public XtensaTargetStreamer { + formatted_raw_ostream &OS; + +public: + XtensaTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS); + void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, + bool SwitchLiteralSection, SMLoc L) override; + void emitLiteralPosition() override; + void startLiteralSection(MCSection *Section) override; +}; + +class XtensaTargetELFStreamer : public XtensaTargetStreamer { +public: + XtensaTargetELFStreamer(MCStreamer &S); + MCELFStreamer &getStreamer(); + void emitLiteral(MCSymbol *LblSym, const MCExpr *Value, + bool SwitchLiteralSection, SMLoc L) override; + void emitLiteralPosition() override {} + void startLiteralSection(MCSection *Section) override; +}; +} // end namespace llvm + +#endif // LLVM_LIB_TARGET_XTENSA_XTENSATARGETSTREAMER_H diff --git a/llvm/lib/Target/Xtensa/Xtensa.td b/llvm/lib/Target/Xtensa/Xtensa.td index b953540be94de0b0089fa6c00a2e7a46e9056f5d..460a15e808b3a405d5dca9decbc2d4b5d14c23f3 100644 --- a/llvm/lib/Target/Xtensa/Xtensa.td +++ b/llvm/lib/Target/Xtensa/Xtensa.td @@ -35,6 +35,12 @@ def : Proc<"generic", []>; include "XtensaRegisterInfo.td" +//===----------------------------------------------------------------------===// +// Calling Convention Description +//===----------------------------------------------------------------------===// + +include "XtensaCallingConv.td" + //===----------------------------------------------------------------------===// // Instruction Descriptions //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp index 87dbf2eb5166cda831a2f7fd7a282b0a92a4718e..e222919b28dc986c27abb001d56c60a2345e0f4a 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.cpp @@ -12,8 +12,13 @@ //===----------------------------------------------------------------------===// #include "XtensaAsmPrinter.h" +#include "MCTargetDesc/XtensaMCExpr.h" +#include "MCTargetDesc/XtensaTargetStreamer.h" #include "TargetInfo/XtensaTargetInfo.h" +#include "XtensaConstantPoolValue.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/BinaryFormat/ELF.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/CodeGen/MachineModuleInfoImpls.h" #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/MC/MCExpr.h" @@ -25,12 +30,152 @@ using namespace llvm; +static MCSymbolRefExpr::VariantKind +getModifierVariantKind(XtensaCP::XtensaCPModifier Modifier) { + switch (Modifier) { + case XtensaCP::no_modifier: + return MCSymbolRefExpr::VK_None; + case XtensaCP::TPOFF: + return MCSymbolRefExpr::VK_TPOFF; + } + report_fatal_error("Invalid XtensaCPModifier!"); +} + void XtensaAsmPrinter::emitInstruction(const MachineInstr *MI) { MCInst LoweredMI; lowerToMCInst(MI, LoweredMI); EmitToStreamer(*OutStreamer, LoweredMI); } +void XtensaAsmPrinter::emitMachineConstantPoolValue( + MachineConstantPoolValue *MCPV) { + XtensaConstantPoolValue *ACPV = static_cast(MCPV); + MCSymbol *MCSym; + + assert(ACPV->isExtSymbol() && "unrecognized constant pool value"); + + XtensaConstantPoolSymbol *XtensaSym = cast(ACPV); + const char *Sym = XtensaSym->getSymbol(); + std::string SymName(Sym); + + if (XtensaSym->isPrivateLinkage()) + SymName = ".L" + SymName; + + MCSym = GetExternalSymbolSymbol(StringRef(SymName)); + MCSymbol *LblSym = GetCPISymbol(ACPV->getLabelId()); + auto *TS = + static_cast(OutStreamer->getTargetStreamer()); + MCSymbolRefExpr::VariantKind VK = getModifierVariantKind(ACPV->getModifier()); + + if (ACPV->getModifier() != XtensaCP::no_modifier) { + std::string SymName(MCSym->getName()); + StringRef Modifier = ACPV->getModifierText(); + SymName += Modifier; + MCSym = GetExternalSymbolSymbol(StringRef(SymName)); + } + + const MCExpr *Expr = MCSymbolRefExpr::create(MCSym, VK, OutContext); + TS->emitLiteral(LblSym, Expr, false); +} + +void XtensaAsmPrinter::emitMachineConstantPoolEntry( + const MachineConstantPoolEntry &CPE, int i) { + if (CPE.isMachineConstantPoolEntry()) { + XtensaConstantPoolValue *ACPV = + static_cast(CPE.Val.MachineCPVal); + ACPV->setLabelId(i); + emitMachineConstantPoolValue(CPE.Val.MachineCPVal); + } else { + MCSymbol *LblSym = GetCPISymbol(i); + auto *TS = + static_cast(OutStreamer->getTargetStreamer()); + const Constant *C = CPE.Val.ConstVal; + const MCExpr *Value = nullptr; + + Type *Ty = C->getType(); + if (const auto *CFP = dyn_cast(C)) { + Value = MCConstantExpr::create( + CFP->getValueAPF().bitcastToAPInt().getSExtValue(), OutContext); + } else if (const auto *CI = dyn_cast(C)) { + Value = MCConstantExpr::create(CI->getValue().getSExtValue(), OutContext); + } else if (isa(Ty)) { + Value = lowerConstant(C); + } else { + llvm_unreachable("unexpected constant pool entry type"); + } + + TS->emitLiteral(LblSym, Value, false); + } +} + +// EmitConstantPool - Print to the current output stream assembly +// representations of the constants in the constant pool MCP. This is +// used to print out constants which have been "spilled to memory" by +// the code generator. +void XtensaAsmPrinter::emitConstantPool() { + const Function &F = MF->getFunction(); + const MachineConstantPool *MCP = MF->getConstantPool(); + const std::vector &CP = MCP->getConstants(); + if (CP.empty()) + return; + + OutStreamer->pushSection(); + + auto *TS = + static_cast(OutStreamer->getTargetStreamer()); + MCSection *CS = getObjFileLowering().SectionForGlobal(&F, TM); + TS->startLiteralSection(CS); + + int CPIdx = 0; + for (const MachineConstantPoolEntry &CPE : CP) { + emitMachineConstantPoolEntry(CPE, CPIdx++); + } + + OutStreamer->popSection(); +} + +MCSymbol * +XtensaAsmPrinter::GetConstantPoolIndexSymbol(const MachineOperand &MO) const { + // Create a symbol for the name. + return GetCPISymbol(MO.getIndex()); +} + +MCOperand +XtensaAsmPrinter::LowerSymbolOperand(const MachineOperand &MO, + MachineOperand::MachineOperandType MOTy, + unsigned Offset) const { + const MCSymbol *Symbol; + XtensaMCExpr::VariantKind Kind = XtensaMCExpr::VK_Xtensa_None; + + switch (MOTy) { + case MachineOperand::MO_GlobalAddress: + Symbol = getSymbol(MO.getGlobal()); + Offset += MO.getOffset(); + break; + case MachineOperand::MO_ConstantPoolIndex: + Symbol = GetConstantPoolIndexSymbol(MO); + Offset += MO.getOffset(); + break; + default: + report_fatal_error(""); + } + + const MCExpr *ME = + MCSymbolRefExpr::create(Symbol, MCSymbolRefExpr::VK_None, OutContext); + ME = XtensaMCExpr::create(ME, Kind, OutContext); + + if (Offset) { + // Assume offset is never negative. + assert(Offset > 0); + + const MCConstantExpr *OffsetExpr = + MCConstantExpr::create(Offset, OutContext); + ME = MCBinaryExpr::createAdd(ME, OffsetExpr, OutContext); + } + + return MCOperand::createExpr(ME); +} + MCOperand XtensaAsmPrinter::lowerOperand(const MachineOperand &MO, unsigned Offset) const { MachineOperand::MachineOperandType MOTy = MO.getType(); @@ -45,6 +190,9 @@ MCOperand XtensaAsmPrinter::lowerOperand(const MachineOperand &MO, return MCOperand::createImm(MO.getImm() + Offset); case MachineOperand::MO_RegisterMask: break; + case MachineOperand::MO_GlobalAddress: + case MachineOperand::MO_ConstantPoolIndex: + return LowerSymbolOperand(MO, MOTy, Offset); default: report_fatal_error("unknown operand type"); } diff --git a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h index dec2a1ee4954f96297ebb33f3cbe3cba6cc31ffd..f3fec19724aab66a1ac11ea3e7f5ba2b98aadb88 100644 --- a/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h +++ b/llvm/lib/Target/Xtensa/XtensaAsmPrinter.h @@ -15,6 +15,7 @@ #include "XtensaTargetMachine.h" #include "llvm/CodeGen/AsmPrinter.h" +#include "llvm/CodeGen/MachineConstantPool.h" #include "llvm/Support/Compiler.h" namespace llvm { @@ -35,6 +36,18 @@ public: StringRef getPassName() const override { return "Xtensa Assembly Printer"; } void emitInstruction(const MachineInstr *MI) override; + void emitConstantPool() override; + + void emitMachineConstantPoolEntry(const MachineConstantPoolEntry &CPE, int i); + + void emitMachineConstantPoolValue(MachineConstantPoolValue *MCPV) override; + + MCSymbol *GetConstantPoolIndexSymbol(const MachineOperand &MO) const; + + MCOperand LowerSymbolOperand(const MachineOperand &MO, + MachineOperand::MachineOperandType MOTy, + unsigned Offset) const; + // Lower MachineInstr MI to MCInst OutMI. void lowerToMCInst(const MachineInstr *MI, MCInst &OutMI) const; diff --git a/llvm/lib/Target/Xtensa/XtensaCallingConv.td b/llvm/lib/Target/Xtensa/XtensaCallingConv.td new file mode 100644 index 0000000000000000000000000000000000000000..a348b4c890b22af40ae335ecb90e0a55ccbe3572 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaCallingConv.td @@ -0,0 +1,24 @@ +//===- XtensaCallingConv.td - Xtensa Calling Conventions -*- tablegen ---*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// This describes the calling conventions for the Xtensa ABI. +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Xtensa return value calling convention +//===----------------------------------------------------------------------===// +def RetCC_Xtensa : CallingConv<[ + // First two return values go in a2, a3, a4, a5 + CCIfType<[i32], CCAssignToReg<[A2, A3, A4, A5]>>, + CCIfType<[i64], CCAssignToRegWithShadow<[A2, A4], [A3, A5]>> +]>; + +//===----------------------------------------------------------------------===// +// Callee-saved register lists. +//===----------------------------------------------------------------------===// + +def CSR_Xtensa : CalleeSavedRegs<(add A0, A12, A13, A14, A15)>; diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp new file mode 100644 index 0000000000000000000000000000000000000000..4e53aa5736c72ce11724fc2f94f0e6652cdf5b10 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.cpp @@ -0,0 +1,207 @@ +//===- XtensaConstantPoolValue.cpp - Xtensa constantpool value ------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the Xtensa specific constantpool value class. +// +//===----------------------------------------------------------------------===// + +#include "XtensaConstantPoolValue.h" +#include "llvm/ADT/FoldingSet.h" +#include "llvm/CodeGen/MachineBasicBlock.h" +#include "llvm/IR/Constant.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/Type.h" +#include "llvm/Support/raw_ostream.h" +#include +using namespace llvm; + +XtensaConstantPoolValue::XtensaConstantPoolValue( + Type *Ty, unsigned ID, XtensaCP::XtensaCPKind Kind, + XtensaCP::XtensaCPModifier modifier) + : MachineConstantPoolValue(Ty), LabelId(ID), Kind(Kind), + Modifier(modifier) {} + +XtensaConstantPoolValue::XtensaConstantPoolValue( + LLVMContext &C, unsigned ID, XtensaCP::XtensaCPKind Kind, + XtensaCP::XtensaCPModifier Modifier) + : MachineConstantPoolValue((Type *)Type::getInt32Ty(C)), LabelId(ID), + Kind(Kind), Modifier(Modifier) {} + +XtensaConstantPoolValue::~XtensaConstantPoolValue() {} + +StringRef XtensaConstantPoolValue::getModifierText() const { + switch (Modifier) { + case XtensaCP::no_modifier: + return ""; + case XtensaCP::TPOFF: + return "@TPOFF"; + } + report_fatal_error("Unknown modifier!"); +} + +int XtensaConstantPoolValue::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + report_fatal_error("Shouldn't be calling this directly!"); +} + +void XtensaConstantPoolValue::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddInteger(LabelId); +} + +bool XtensaConstantPoolValue::hasSameValue(XtensaConstantPoolValue *ACPV) { + if (ACPV->Kind == Kind) { + if (ACPV->LabelId == LabelId) + return true; + } + return false; +} + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) +void XtensaConstantPoolValue::dump() const { errs() << " " << *this; } +#endif + +void XtensaConstantPoolValue::print(raw_ostream &O) const {} + +//===----------------------------------------------------------------------===// +// XtensaConstantPoolConstant +//===----------------------------------------------------------------------===// + +XtensaConstantPoolConstant::XtensaConstantPoolConstant( + const Constant *C, unsigned ID, XtensaCP::XtensaCPKind Kind) + : XtensaConstantPoolValue(C->getType(), ID, Kind), CVal(C) {} + +XtensaConstantPoolConstant * +XtensaConstantPoolConstant::Create(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind) { + return new XtensaConstantPoolConstant(C, ID, Kind); +} + +const BlockAddress *XtensaConstantPoolConstant::getBlockAddress() const { + return dyn_cast_or_null(CVal); +} + +int XtensaConstantPoolConstant::getExistingMachineCPValue( + MachineConstantPool *CP, Align Alignment) { + return getExistingMachineCPValueImpl(CP, + Alignment); +} + +bool XtensaConstantPoolConstant::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolConstant *ACPC = + dyn_cast(ACPV); + return ACPC && ACPC->CVal == CVal && + XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolConstant::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddPointer(CVal); + XtensaConstantPoolValue::addSelectionDAGCSEId(ID); +} + +void XtensaConstantPoolConstant::print(raw_ostream &O) const { + O << CVal->getName(); + XtensaConstantPoolValue::print(O); +} + +XtensaConstantPoolSymbol::XtensaConstantPoolSymbol( + LLVMContext &C, const char *Str, unsigned ID, bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier) + : XtensaConstantPoolValue(C, ID, XtensaCP::CPExtSymbol, Modifier), S(Str), + PrivateLinkage(PrivLinkage) {} + +XtensaConstantPoolSymbol * +XtensaConstantPoolSymbol::Create(LLVMContext &C, const char *Str, unsigned ID, + bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier) + +{ + return new XtensaConstantPoolSymbol(C, Str, ID, PrivLinkage, Modifier); +} + +int XtensaConstantPoolSymbol::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + return getExistingMachineCPValueImpl(CP, Alignment); +} + +bool XtensaConstantPoolSymbol::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolSymbol *ACPS = + dyn_cast(ACPV); + return ACPS && ACPS->S == S && XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolSymbol::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddString(S); + XtensaConstantPoolValue::addSelectionDAGCSEId(ID); +} + +void XtensaConstantPoolSymbol::print(raw_ostream &O) const { + O << S; + XtensaConstantPoolValue::print(O); +} + +XtensaConstantPoolMBB::XtensaConstantPoolMBB(LLVMContext &C, + const MachineBasicBlock *M, + unsigned Id) + : XtensaConstantPoolValue(C, 0, XtensaCP::CPMachineBasicBlock), MBB(M) {} + +XtensaConstantPoolMBB *XtensaConstantPoolMBB::Create(LLVMContext &C, + const MachineBasicBlock *M, + unsigned Idx) { + return new XtensaConstantPoolMBB(C, M, Idx); +} + +int XtensaConstantPoolMBB::getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) { + return getExistingMachineCPValueImpl(CP, Alignment); +} + +bool XtensaConstantPoolMBB::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolMBB *ACPMBB = dyn_cast(ACPV); + return ACPMBB && ACPMBB->MBB == MBB && + XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolMBB::addSelectionDAGCSEId(FoldingSetNodeID &ID) { + ID.AddPointer(MBB); + XtensaConstantPoolValue::addSelectionDAGCSEId(ID); +} + +void XtensaConstantPoolMBB::print(raw_ostream &O) const { + O << "BB#" << MBB->getNumber(); + XtensaConstantPoolValue::print(O); +} + +XtensaConstantPoolJumpTable::XtensaConstantPoolJumpTable(LLVMContext &C, + unsigned Index) + : XtensaConstantPoolValue(C, 0, XtensaCP::CPJumpTable), Idx(Index) {} + +XtensaConstantPoolJumpTable *XtensaConstantPoolJumpTable::Create(LLVMContext &C, + unsigned Idx) { + return new XtensaConstantPoolJumpTable(C, Idx); +} + +int XtensaConstantPoolJumpTable::getExistingMachineCPValue( + MachineConstantPool *CP, Align Alignment) { + return getExistingMachineCPValueImpl(CP, + Alignment); +} + +bool XtensaConstantPoolJumpTable::hasSameValue(XtensaConstantPoolValue *ACPV) { + const XtensaConstantPoolJumpTable *ACPJT = + dyn_cast(ACPV); + return ACPJT && ACPJT->Idx == Idx && + XtensaConstantPoolValue::hasSameValue(ACPV); +} + +void XtensaConstantPoolJumpTable::addSelectionDAGCSEId(FoldingSetNodeID &ID) {} + +void XtensaConstantPoolJumpTable::print(raw_ostream &O) const { + O << "JT" << Idx; + XtensaConstantPoolValue::print(O); +} diff --git a/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h new file mode 100644 index 0000000000000000000000000000000000000000..5580de48447468b511b0b6511639fda7cca0e021 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaConstantPoolValue.h @@ -0,0 +1,263 @@ +//===- XtensaConstantPoolValue.h - Xtensa constantpool value ----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file implements the Xtensa specific constantpool value class. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H +#define LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H + +#include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/Support/Casting.h" +#include "llvm/Support/ErrorHandling.h" +#include +#include +#include + +namespace llvm { + +class BlockAddress; +class Constant; +class GlobalValue; +class LLVMContext; +class MachineBasicBlock; + +namespace XtensaCP { +enum XtensaCPKind { + CPExtSymbol, + CPBlockAddress, + CPMachineBasicBlock, + CPJumpTable +}; + +enum XtensaCPModifier { + no_modifier, // None + TPOFF // Thread Pointer Offset +}; +} // namespace XtensaCP + +/// XtensaConstantPoolValue - Xtensa specific constantpool value. This is used +/// to represent PC-relative displacement between the address of the load +/// instruction and the constant being loaded. +class XtensaConstantPoolValue : public MachineConstantPoolValue { + unsigned LabelId; // Label id of the load. + XtensaCP::XtensaCPKind Kind; // Kind of constant. + XtensaCP::XtensaCPModifier Modifier; // Symbol name modifier + //(for example Global Variable name) + +protected: + XtensaConstantPoolValue( + Type *Ty, unsigned ID, XtensaCP::XtensaCPKind Kind, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + + XtensaConstantPoolValue( + LLVMContext &C, unsigned id, XtensaCP::XtensaCPKind Kind, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + + template + int getExistingMachineCPValueImpl(MachineConstantPool *CP, Align Alignment) { + const std::vector &Constants = CP->getConstants(); + for (unsigned i = 0, e = Constants.size(); i != e; ++i) { + if (Constants[i].isMachineConstantPoolEntry() && + (Constants[i].getAlign() >= Alignment)) { + auto *CPV = static_cast( + Constants[i].Val.MachineCPVal); + if (Derived *APC = dyn_cast(CPV)) + if (cast(this)->equals(APC)) + return i; + } + } + + return -1; + } + +public: + ~XtensaConstantPoolValue() override; + + XtensaCP::XtensaCPModifier getModifier() const { return Modifier; } + bool hasModifier() const { return Modifier != XtensaCP::no_modifier; } + StringRef getModifierText() const; + + unsigned getLabelId() const { return LabelId; } + void setLabelId(unsigned ID) { LabelId = ID; } + + bool isExtSymbol() const { return Kind == XtensaCP::CPExtSymbol; } + bool isBlockAddress() const { return Kind == XtensaCP::CPBlockAddress; } + bool isMachineBasicBlock() const { + return Kind == XtensaCP::CPMachineBasicBlock; + } + bool isJumpTable() const { return Kind == XtensaCP::CPJumpTable; } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + virtual bool hasSameValue(XtensaConstantPoolValue *ACPV); + + bool equals(const XtensaConstantPoolValue *A) const { + return this->LabelId == A->LabelId && this->Modifier == A->Modifier; + } + + void print(raw_ostream &O) const override; + +#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) + void dump() const; +#endif +}; + +inline raw_ostream &operator<<(raw_ostream &O, + const XtensaConstantPoolValue &V) { + V.print(O); + return O; +} + +/// XtensaConstantPoolConstant - Xtensa-specific constant pool values for +/// Constants (for example BlockAddresses). +class XtensaConstantPoolConstant : public XtensaConstantPoolValue { + const Constant *CVal; // Constant being loaded. + + XtensaConstantPoolConstant(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind); + +public: + static XtensaConstantPoolConstant *Create(const Constant *C, unsigned ID, + XtensaCP::XtensaCPKind Kind); + + const BlockAddress *getBlockAddress() const; + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + void print(raw_ostream &O) const override; + static bool classof(const XtensaConstantPoolValue *APV) { + return APV->isBlockAddress(); + } + + bool equals(const XtensaConstantPoolConstant *A) const { + return CVal == A->CVal && XtensaConstantPoolValue::equals(A); + } +}; + +/// XtensaConstantPoolSymbol - Xtensa-specific constantpool values for external +/// symbols. +class XtensaConstantPoolSymbol : public XtensaConstantPoolValue { + const std::string S; // ExtSymbol being loaded. + bool PrivateLinkage; + + XtensaConstantPoolSymbol( + LLVMContext &C, const char *S, unsigned Id, bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + +public: + static XtensaConstantPoolSymbol * + Create(LLVMContext &C, const char *S, unsigned ID, bool PrivLinkage, + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier); + + const char *getSymbol() const { return S.c_str(); } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + bool isPrivateLinkage() { return PrivateLinkage; } + + void print(raw_ostream &O) const override; + + static bool classof(const XtensaConstantPoolValue *ACPV) { + return ACPV->isExtSymbol(); + } + + bool equals(const XtensaConstantPoolSymbol *A) const { + return S == A->S && XtensaConstantPoolValue::equals(A); + } +}; + +/// XtensaConstantPoolMBB - Xtensa-specific constantpool value of a machine +/// basic block. +class XtensaConstantPoolMBB : public XtensaConstantPoolValue { + const MachineBasicBlock *MBB; // Machine basic block. + + XtensaConstantPoolMBB(LLVMContext &C, const MachineBasicBlock *M, + unsigned ID); + +public: + static XtensaConstantPoolMBB *Create(LLVMContext &C, + const MachineBasicBlock *M, unsigned ID); + + const MachineBasicBlock *getMBB() const { return MBB; } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + void print(raw_ostream &O) const override; + + static bool classof(const XtensaConstantPoolValue *ACPV) { + return ACPV->isMachineBasicBlock(); + } + + bool equals(const XtensaConstantPoolMBB *A) const { + return MBB == A->MBB && XtensaConstantPoolValue::equals(A); + } +}; + +/// XtensaConstantPoolJumpTable - Xtensa-specific constantpool values for Jump +/// Table symbols. +class XtensaConstantPoolJumpTable : public XtensaConstantPoolValue { + unsigned Idx; // Jump Table Index. + + XtensaConstantPoolJumpTable(LLVMContext &C, unsigned Idx); + +public: + static XtensaConstantPoolJumpTable *Create(LLVMContext &C, unsigned Idx); + + unsigned getIndex() const { return Idx; } + + int getExistingMachineCPValue(MachineConstantPool *CP, + Align Alignment) override; + + void addSelectionDAGCSEId(FoldingSetNodeID &ID) override; + + /// hasSameValue - Return true if this Xtensa constpool value can share the + /// same constantpool entry as another Xtensa constpool value. + bool hasSameValue(XtensaConstantPoolValue *ACPV) override; + + void print(raw_ostream &O) const override; + + static bool classof(const XtensaConstantPoolValue *ACPV) { + return ACPV->isJumpTable(); + } + + bool equals(const XtensaConstantPoolJumpTable *A) const { + return Idx == A->Idx && XtensaConstantPoolValue::equals(A); + } +}; + +} // namespace llvm + +#endif /* LLVM_LIB_TARGET_XTENSA_XTENSACONSTANTPOOLVALUE_H */ diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp index 2092a2d947f8665db5f2f9d5d04439edee83a4b3..ab37c09bf8bfe06051dc85a9fba50e4b889670dc 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.cpp @@ -37,3 +37,23 @@ void XtensaFrameLowering::emitPrologue(MachineFunction &MF, void XtensaFrameLowering::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const {} + +// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions +MachineBasicBlock::iterator XtensaFrameLowering::eliminateCallFramePseudoInstr( + MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + const XtensaInstrInfo &TII = + *static_cast(MF.getSubtarget().getInstrInfo()); + + if (!hasReservedCallFrame(MF)) { + int64_t Amount = I->getOperand(0).getImm(); + + if (I->getOpcode() == Xtensa::ADJCALLSTACKDOWN) + Amount = -Amount; + + unsigned SP = Xtensa::SP; + TII.adjustStackPtr(SP, Amount, MBB, I); + } + + return MBB.erase(I); +} diff --git a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h index 19e52310a99d9126a31270f49aa10791b5c64458..2da88ab14073ab85cf97fa1e30937274ee78c015 100644 --- a/llvm/lib/Target/Xtensa/XtensaFrameLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaFrameLowering.h @@ -25,6 +25,10 @@ public: /// the function. void emitPrologue(MachineFunction &, MachineBasicBlock &) const override; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override; + + MachineBasicBlock::iterator + eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const override; }; } // namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp index 30073727545228be6ab52916e3ea238ad174b43f..5ebedefafc165e38d5a86cb47330d5c34d7a7fbc 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelDAGToDAG.cpp @@ -12,9 +12,11 @@ #include "Xtensa.h" #include "XtensaTargetMachine.h" +#include "XtensaUtils.h" #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/CodeGen/SelectionDAGISel.h" +#include "llvm/IR/DiagnosticInfo.h" #include "llvm/Support/Debug.h" #include "llvm/Support/raw_ostream.h" @@ -37,9 +39,57 @@ public: void Select(SDNode *Node) override; + // For load/store instructions generate (base+offset) pair from + // memory address. The offset must be a multiple of scale argument. bool selectMemRegAddr(SDValue Addr, SDValue &Base, SDValue &Offset, int Scale) { - report_fatal_error("MemReg address is not implemented yet"); + EVT ValTy = Addr.getValueType(); + + // if Address is FI, get the TargetFrameIndex. + if (FrameIndexSDNode *FIN = dyn_cast(Addr)) { + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), ValTy); + + return true; + } + + if (TM.isPositionIndependent()) { + DiagnosticInfoUnsupported Diag(CurDAG->getMachineFunction().getFunction(), + "PIC relocations are not supported ", + Addr.getDebugLoc()); + CurDAG->getContext()->diagnose(Diag); + } + + if ((Addr.getOpcode() == ISD::TargetExternalSymbol || + Addr.getOpcode() == ISD::TargetGlobalAddress)) + return false; + + // Addresses of the form FI+const + bool Valid = false; + if (CurDAG->isBaseWithConstantOffset(Addr)) { + ConstantSDNode *CN = dyn_cast(Addr.getOperand(1)); + int64_t OffsetVal = CN->getSExtValue(); + + Valid = isValidAddrOffset(Scale, OffsetVal); + + if (Valid) { + // If the first operand is a FI, get the TargetFI Node + if (FrameIndexSDNode *FIN = + dyn_cast(Addr.getOperand(0))) + Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy); + else + Base = Addr.getOperand(0); + + Offset = + CurDAG->getTargetConstant(CN->getZExtValue(), SDLoc(Addr), ValTy); + return true; + } + } + + // Last case + Base = Addr; + Offset = CurDAG->getTargetConstant(0, SDLoc(Addr), Addr.getValueType()); + return true; } bool selectMemRegAddrISH1(SDValue Addr, SDValue &Base, SDValue &Offset) { diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp index 276fab838d17c0d982b89226d3eb74f2dfe82873..64b996b6a42e559e0bbb7319f7399267baf966e7 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.cpp @@ -12,6 +12,7 @@ //===----------------------------------------------------------------------===// #include "XtensaISelLowering.h" +#include "XtensaConstantPoolValue.h" #include "XtensaSubtarget.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/CallingConvLower.h" @@ -22,15 +23,26 @@ #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/Support/MathExtras.h" #include "llvm/Support/raw_ostream.h" +#include using namespace llvm; #define DEBUG_TYPE "xtensa-lower" +// Return true if we must use long (in fact, indirect) function call. +// It's simplified version, production implimentation must +// resolve a functions in ROM (usually glibc functions) +static bool isLongCall(const char *str) { + // Currently always use long calls + return true; +} + XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM, const XtensaSubtarget &STI) : TargetLowering(TM), Subtarget(STI) { + MVT PtrVT = MVT::i32; // Set up the register classes. addRegisterClass(MVT::i32, &Xtensa::ARRegClass); @@ -41,18 +53,507 @@ XtensaTargetLowering::XtensaTargetLowering(const TargetMachine &TM, setMinFunctionAlignment(Align(4)); + setOperationAction(ISD::Constant, MVT::i32, Custom); + setOperationAction(ISD::Constant, MVT::i64, Expand); + + setBooleanContents(ZeroOrOneBooleanContent); + + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8, Expand); + setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Expand); + + setOperationAction(ISD::BITCAST, MVT::i32, Expand); + setOperationAction(ISD::BITCAST, MVT::f32, Expand); + setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::SINT_TO_FP, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand); + setOperationAction(ISD::FP_TO_SINT, MVT::i32, Expand); + + // No sign extend instructions for i1 + for (MVT VT : MVT::integer_valuetypes()) { + setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote); + setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote); + } + + setOperationAction(ISD::ConstantPool, PtrVT, Custom); + // Compute derived properties from the register classes computeRegisterProperties(STI.getRegisterInfo()); } +//===----------------------------------------------------------------------===// +// Calling conventions +//===----------------------------------------------------------------------===// + +#include "XtensaGenCallingConv.inc" + +static bool CC_Xtensa_Custom(unsigned ValNo, MVT ValVT, MVT LocVT, + CCValAssign::LocInfo LocInfo, + ISD::ArgFlagsTy ArgFlags, CCState &State) { + static const MCPhysReg IntRegs[] = {Xtensa::A2, Xtensa::A3, Xtensa::A4, + Xtensa::A5, Xtensa::A6, Xtensa::A7}; + + if (ArgFlags.isByVal()) { + Align ByValAlign = ArgFlags.getNonZeroByValAlign(); + unsigned ByValSize = ArgFlags.getByValSize(); + if (ByValSize < 4) { + ByValSize = 4; + } + if (ByValAlign < Align(4)) { + ByValAlign = Align(4); + } + unsigned Offset = State.AllocateStack(ByValSize, ByValAlign); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); + // Mark all unused registers as allocated to avoid misuse + // of such registers. + while (State.AllocateReg(IntRegs)) + ; + return false; + } + + // Promote i8 and i16 + if (LocVT == MVT::i8 || LocVT == MVT::i16) { + LocVT = MVT::i32; + if (ArgFlags.isSExt()) + LocInfo = CCValAssign::SExt; + else if (ArgFlags.isZExt()) + LocInfo = CCValAssign::ZExt; + else + LocInfo = CCValAssign::AExt; + } + + unsigned Register; + + Align OrigAlign = ArgFlags.getNonZeroOrigAlign(); + bool needs64BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(8)); + bool needs128BitAlign = (ValVT == MVT::i32 && OrigAlign == Align(16)); + + if (ValVT == MVT::i32) { + Register = State.AllocateReg(IntRegs); + // If this is the first part of an i64 arg, + // the allocated register must be either A2, A4 or A6. + if (needs64BitAlign && (Register == Xtensa::A3 || Register == Xtensa::A5 || + Register == Xtensa::A7)) + Register = State.AllocateReg(IntRegs); + // arguments with 16byte alignment must be passed in the first register or + // passed via stack + if (needs128BitAlign && (Register != Xtensa::A2)) + while ((Register = State.AllocateReg(IntRegs))) + ; + LocVT = MVT::i32; + } else if (ValVT == MVT::f64) { + // Allocate int register and shadow next int register. + Register = State.AllocateReg(IntRegs); + if (Register == Xtensa::A3 || Register == Xtensa::A5 || + Register == Xtensa::A7) + Register = State.AllocateReg(IntRegs); + State.AllocateReg(IntRegs); + LocVT = MVT::i32; + } else { + report_fatal_error("Cannot handle this ValVT."); + } + + if (!Register) { + unsigned Offset = State.AllocateStack(ValVT.getStoreSize(), OrigAlign); + State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo)); + } else { + State.addLoc(CCValAssign::getReg(ValNo, ValVT, Register, LocVT, LocInfo)); + } + + return false; +} + +CCAssignFn *XtensaTargetLowering::CCAssignFnForCall(CallingConv::ID CC, + bool IsVarArg) const { + return CC_Xtensa_Custom; +} + +SDValue XtensaTargetLowering::LowerFormalArguments( + SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, + const SmallVectorImpl &Ins, const SDLoc &DL, + SelectionDAG &DAG, SmallVectorImpl &InVals) const { + MachineFunction &MF = DAG.getMachineFunction(); + MachineFrameInfo &MFI = MF.getFrameInfo(); + + // Used with vargs to acumulate store chains. + std::vector OutChains; + + if (IsVarArg) + report_fatal_error("Var arg not supported by FormalArguments Lowering"); + + // Assign locations to all of the incoming arguments. + SmallVector ArgLocs; + CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), ArgLocs, + *DAG.getContext()); + + CCInfo.AnalyzeFormalArguments(Ins, CCAssignFnForCall(CallConv, IsVarArg)); + + for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) { + CCValAssign &VA = ArgLocs[i]; + // Arguments stored on registers + if (VA.isRegLoc()) { + EVT RegVT = VA.getLocVT(); + const TargetRegisterClass *RC; + + if (RegVT == MVT::i32) + RC = &Xtensa::ARRegClass; + else + report_fatal_error("RegVT not supported by FormalArguments Lowering"); + + // Transform the arguments stored on + // physical registers into virtual ones + unsigned Register = MF.addLiveIn(VA.getLocReg(), RC); + SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, Register, RegVT); + + // If this is an 8 or 16-bit value, it has been passed promoted + // to 32 bits. Insert an assert[sz]ext to capture this, then + // truncate to the right size. + if (VA.getLocInfo() != CCValAssign::Full) { + unsigned Opcode = 0; + if (VA.getLocInfo() == CCValAssign::SExt) + Opcode = ISD::AssertSext; + else if (VA.getLocInfo() == CCValAssign::ZExt) + Opcode = ISD::AssertZext; + if (Opcode) + ArgValue = DAG.getNode(Opcode, DL, RegVT, ArgValue, + DAG.getValueType(VA.getValVT())); + ArgValue = DAG.getNode((VA.getValVT() == MVT::f32) ? ISD::BITCAST + : ISD::TRUNCATE, + DL, VA.getValVT(), ArgValue); + } + + InVals.push_back(ArgValue); + + } else { + assert(VA.isMemLoc()); + + EVT ValVT = VA.getValVT(); + + // The stack pointer offset is relative to the caller stack frame. + int FI = MFI.CreateFixedObject(ValVT.getStoreSize(), VA.getLocMemOffset(), + true); + + if (Ins[VA.getValNo()].Flags.isByVal()) { + // Assume that in this case load operation is created + SDValue FIN = DAG.getFrameIndex(FI, MVT::i32); + InVals.push_back(FIN); + } else { + // Create load nodes to retrieve arguments from the stack + SDValue FIN = + DAG.getFrameIndex(FI, getFrameIndexTy(DAG.getDataLayout())); + InVals.push_back(DAG.getLoad( + ValVT, DL, Chain, FIN, + MachinePointerInfo::getFixedStack(DAG.getMachineFunction(), FI))); + } + } + } + + // All stores are grouped in one node to allow the matching between + // the size of Ins and InVals. This only happens when on varg functions + if (!OutChains.empty()) { + OutChains.push_back(Chain); + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, OutChains); + } + + return Chain; +} + +SDValue +XtensaTargetLowering::LowerCall(CallLoweringInfo &CLI, + SmallVectorImpl &InVals) const { + SelectionDAG &DAG = CLI.DAG; + SDLoc &DL = CLI.DL; + SmallVector &Outs = CLI.Outs; + SmallVector &OutVals = CLI.OutVals; + SmallVector &Ins = CLI.Ins; + SDValue Chain = CLI.Chain; + SDValue Callee = CLI.Callee; + bool &IsTailCall = CLI.IsTailCall; + CallingConv::ID CallConv = CLI.CallConv; + bool IsVarArg = CLI.IsVarArg; + + MachineFunction &MF = DAG.getMachineFunction(); + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + const TargetFrameLowering *TFL = Subtarget.getFrameLowering(); + + // TODO: Support tail call optimization. + IsTailCall = false; + + // Analyze the operands of the call, assigning locations to each operand. + SmallVector ArgLocs; + CCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext()); + + CCAssignFn *CC = CCAssignFnForCall(CallConv, IsVarArg); + + CCInfo.AnalyzeCallOperands(Outs, CC); + + // Get a count of how many bytes are to be pushed on the stack. + unsigned NumBytes = CCInfo.getStackSize(); + + Align StackAlignment = TFL->getStackAlign(); + unsigned NextStackOffset = alignTo(NumBytes, StackAlignment); + + Chain = DAG.getCALLSEQ_START(Chain, NextStackOffset, 0, DL); + + // Copy argument values to their designated locations. + std::deque> RegsToPass; + SmallVector MemOpChains; + SDValue StackPtr; + for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) { + CCValAssign &VA = ArgLocs[I]; + SDValue ArgValue = OutVals[I]; + ISD::ArgFlagsTy Flags = Outs[I].Flags; + + if (VA.isRegLoc()) + // Queue up the argument copies and emit them at the end. + RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue)); + else if (Flags.isByVal()) { + assert(VA.isMemLoc()); + assert(Flags.getByValSize() && + "ByVal args of size 0 should have been ignored by front-end."); + assert(!IsTailCall && + "Do not tail-call optimize if there is a byval argument."); + + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT); + unsigned Offset = VA.getLocMemOffset(); + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, + DAG.getIntPtrConstant(Offset, DL)); + SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), DL, MVT::i32); + SDValue Memcpy = DAG.getMemcpy( + Chain, DL, Address, ArgValue, SizeNode, Flags.getNonZeroByValAlign(), + /*isVolatile=*/false, /*AlwaysInline=*/false, + /*isTailCall=*/false, MachinePointerInfo(), MachinePointerInfo()); + MemOpChains.push_back(Memcpy); + } else { + assert(VA.isMemLoc() && "Argument not register or memory"); + + // Work out the address of the stack slot. Unpromoted ints and + // floats are passed as right-justified 8-byte values. + if (!StackPtr.getNode()) + StackPtr = DAG.getCopyFromReg(Chain, DL, Xtensa::SP, PtrVT); + unsigned Offset = VA.getLocMemOffset(); + SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr, + DAG.getIntPtrConstant(Offset, DL)); + + // Emit the store. + MemOpChains.push_back( + DAG.getStore(Chain, DL, ArgValue, Address, MachinePointerInfo())); + } + } + + // Join the stores, which are independent of one another. + if (!MemOpChains.empty()) + Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains); + + // Build a sequence of copy-to-reg nodes, chained and glued together. + SDValue Glue; + for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) { + unsigned Reg = RegsToPass[I].first; + Chain = DAG.getCopyToReg(Chain, DL, Reg, RegsToPass[I].second, Glue); + Glue = Chain.getValue(1); + } + std::string name; + unsigned char TF = 0; + + // Accept direct calls by converting symbolic call addresses to the + // associated Target* opcodes. + if (ExternalSymbolSDNode *E = dyn_cast(Callee)) { + name = E->getSymbol(); + TF = E->getTargetFlags(); + if (isPositionIndependent()) { + report_fatal_error("PIC relocations is not supported"); + } else + Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT, TF); + } else if (GlobalAddressSDNode *G = dyn_cast(Callee)) { + const GlobalValue *GV = G->getGlobal(); + name = GV->getName().str(); + } + + if ((!name.empty()) && isLongCall(name.c_str())) { + // Create a constant pool entry for the callee address + XtensaCP::XtensaCPModifier Modifier = XtensaCP::no_modifier; + + XtensaConstantPoolValue *CPV = XtensaConstantPoolSymbol::Create( + *DAG.getContext(), name.c_str(), 0 /* XtensaCLabelIndex */, false, + Modifier); + + // Get the address of the callee into a register + SDValue CPAddr = DAG.getTargetConstantPool(CPV, PtrVT, Align(4), 0, TF); + SDValue CPWrap = getAddrPCRel(CPAddr, DAG); + Callee = CPWrap; + } + + // The first call operand is the chain and the second is the target address. + SmallVector Ops; + Ops.push_back(Chain); + Ops.push_back(Callee); + + // Add a register mask operand representing the call-preserved registers. + const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo(); + const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv); + assert(Mask && "Missing call preserved mask for calling convention"); + Ops.push_back(DAG.getRegisterMask(Mask)); + + // Add argument registers to the end of the list so that they are + // known live into the call. + for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) { + unsigned Reg = RegsToPass[I].first; + Ops.push_back(DAG.getRegister(Reg, RegsToPass[I].second.getValueType())); + } + + // Glue the call to the argument copies, if any. + if (Glue.getNode()) + Ops.push_back(Glue); + + SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); + Chain = DAG.getNode(XtensaISD::CALL, DL, NodeTys, Ops); + Glue = Chain.getValue(1); + + // Mark the end of the call, which is glued to the call itself. + Chain = DAG.getCALLSEQ_END(Chain, DAG.getConstant(NumBytes, DL, PtrVT, true), + DAG.getConstant(0, DL, PtrVT, true), Glue, DL); + Glue = Chain.getValue(1); + + // Assign locations to each value returned by this call. + SmallVector RetLocs; + CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); + RetCCInfo.AnalyzeCallResult(Ins, RetCC_Xtensa); + + // Copy all of the result registers out of their specified physreg. + for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) { + CCValAssign &VA = RetLocs[I]; + + // Copy the value out, gluing the copy to the end of the call sequence. + unsigned Reg = VA.getLocReg(); + SDValue RetValue = DAG.getCopyFromReg(Chain, DL, Reg, VA.getLocVT(), Glue); + Chain = RetValue.getValue(1); + Glue = RetValue.getValue(2); + + InVals.push_back(RetValue); + } + return Chain; +} + +bool XtensaTargetLowering::CanLowerReturn( + CallingConv::ID CallConv, MachineFunction &MF, bool IsVarArg, + const SmallVectorImpl &Outs, LLVMContext &Context) const { + SmallVector RVLocs; + CCState CCInfo(CallConv, IsVarArg, MF, RVLocs, Context); + return CCInfo.CheckReturn(Outs, RetCC_Xtensa); +} + +SDValue +XtensaTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv, + bool IsVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, + const SDLoc &DL, SelectionDAG &DAG) const { + if (IsVarArg) + report_fatal_error("VarArg not supported"); + + MachineFunction &MF = DAG.getMachineFunction(); + + // Assign locations to each returned value. + SmallVector RetLocs; + CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext()); + RetCCInfo.AnalyzeReturn(Outs, RetCC_Xtensa); + + SDValue Glue; + // Quick exit for void returns + if (RetLocs.empty()) + return DAG.getNode(XtensaISD::RET, DL, MVT::Other, Chain); + + // Copy the result values into the output registers. + SmallVector RetOps; + RetOps.push_back(Chain); + for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) { + CCValAssign &VA = RetLocs[I]; + SDValue RetValue = OutVals[I]; + + // Make the return register live on exit. + assert(VA.isRegLoc() && "Can only return in registers!"); + + // Chain and glue the copies together. + unsigned Register = VA.getLocReg(); + Chain = DAG.getCopyToReg(Chain, DL, Register, RetValue, Glue); + Glue = Chain.getValue(1); + RetOps.push_back(DAG.getRegister(Register, VA.getLocVT())); + } + + // Update chain and glue. + RetOps[0] = Chain; + if (Glue.getNode()) + RetOps.push_back(Glue); + + return DAG.getNode(XtensaISD::RET, DL, MVT::Other, RetOps); +} + +SDValue XtensaTargetLowering::LowerImmediate(SDValue Op, + SelectionDAG &DAG) const { + const ConstantSDNode *CN = cast(Op); + SDLoc DL(CN); + APInt APVal = CN->getAPIntValue(); + int64_t Value = APVal.getSExtValue(); + if (Op.getValueType() == MVT::i32) { + // Check if use node maybe lowered to the MOVI instruction + if (Value > -2048 && Value <= 2047) + return Op; + // Check if use node maybe lowered to the ADDMI instruction + SDNode &OpNode = *Op.getNode(); + if ((OpNode.hasOneUse() && OpNode.use_begin()->getOpcode() == ISD::ADD) && + isShiftedInt<16, 8>(Value)) + return Op; + Type *Ty = Type::getInt32Ty(*DAG.getContext()); + Constant *CV = ConstantInt::get(Ty, Value); + SDValue CP = DAG.getConstantPool(CV, MVT::i32); + return CP; + } + return Op; +} + +SDValue XtensaTargetLowering::getAddrPCRel(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + EVT Ty = Op.getValueType(); + return DAG.getNode(XtensaISD::PCREL_WRAPPER, DL, Ty, Op); +} + +SDValue XtensaTargetLowering::LowerConstantPool(ConstantPoolSDNode *CP, + SelectionDAG &DAG) const { + EVT PtrVT = getPointerTy(DAG.getDataLayout()); + SDValue Result; + if (!CP->isMachineConstantPoolEntry()) { + Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT, CP->getAlign(), + CP->getOffset()); + } else { + report_fatal_error("This constantpool type is not supported yet"); + } + + return getAddrPCRel(Result, DAG); +} + SDValue XtensaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const { switch (Op.getOpcode()) { + case ISD::Constant: + return LowerImmediate(Op, DAG); + case ISD::ConstantPool: + return LowerConstantPool(cast(Op), DAG); default: report_fatal_error("Unexpected node to lower"); } } const char *XtensaTargetLowering::getTargetNodeName(unsigned Opcode) const { + switch (Opcode) { + case XtensaISD::CALL: + return "XtensaISD::CALL"; + case XtensaISD::PCREL_WRAPPER: + return "XtensaISD::PCREL_WRAPPER"; + case XtensaISD::RET: + return "XtensaISD::RET"; + } return nullptr; } diff --git a/llvm/lib/Target/Xtensa/XtensaISelLowering.h b/llvm/lib/Target/Xtensa/XtensaISelLowering.h index 8b03712efc9bb5a6c5ab37544dab5e98bf520858..077559e2d6129864f75c3e2db1e28a6e086d76fd 100644 --- a/llvm/lib/Target/Xtensa/XtensaISelLowering.h +++ b/llvm/lib/Target/Xtensa/XtensaISelLowering.h @@ -19,6 +19,23 @@ #include "llvm/CodeGen/TargetLowering.h" namespace llvm { + +namespace XtensaISD { +enum { + FIRST_NUMBER = ISD::BUILTIN_OP_END, + + // Calls a function. Operand 0 is the chain operand and operand 1 + // is the target address. The arguments start at operand 2. + // There is an optional glue operand at the end. + CALL, + + // Wraps a TargetGlobalAddress that should be loaded using PC-relative + // accesses. Operand 0 is the address. + PCREL_WRAPPER, + RET +}; +} + class XtensaSubtarget; class XtensaTargetLowering : public TargetLowering { @@ -30,10 +47,37 @@ public: SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override; + SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, + bool isVarArg, + const SmallVectorImpl &Ins, + const SDLoc &DL, SelectionDAG &DAG, + SmallVectorImpl &InVals) const override; + + SDValue LowerCall(CallLoweringInfo &CLI, + SmallVectorImpl &InVals) const override; + + bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF, + bool isVarArg, + const SmallVectorImpl &Outs, + LLVMContext &Context) const override; + + SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg, + const SmallVectorImpl &Outs, + const SmallVectorImpl &OutVals, const SDLoc &DL, + SelectionDAG &DAG) const override; + const XtensaSubtarget &getSubtarget() const { return Subtarget; } private: const XtensaSubtarget &Subtarget; + + SDValue LowerImmediate(SDValue Op, SelectionDAG &DAG) const; + + SDValue LowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const; + + SDValue getAddrPCRel(SDValue Op, SelectionDAG &DAG) const; + + CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg) const; }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp index 41b794d64fdb1f157ae9fb02efd70bc5a595f4f7..26d8727ce1d3bce4523e772f88ee3bebcd0f1d38 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.cpp @@ -15,6 +15,7 @@ #include "XtensaInstrInfo.h" #include "XtensaTargetMachine.h" #include "llvm/CodeGen/MachineConstantPool.h" +#include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" @@ -23,5 +24,139 @@ using namespace llvm; +static const MachineInstrBuilder & +addFrameReference(const MachineInstrBuilder &MIB, int FI) { + MachineInstr *MI = MIB; + MachineFunction &MF = *MI->getParent()->getParent(); + MachineFrameInfo &MFFrame = MF.getFrameInfo(); + const MCInstrDesc &MCID = MI->getDesc(); + MachineMemOperand::Flags Flags = MachineMemOperand::MONone; + if (MCID.mayLoad()) + Flags |= MachineMemOperand::MOLoad; + if (MCID.mayStore()) + Flags |= MachineMemOperand::MOStore; + int64_t Offset = 0; + Align Alignment = MFFrame.getObjectAlign(FI); + + MachineMemOperand *MMO = + MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(MF, FI, Offset), + Flags, MFFrame.getObjectSize(FI), Alignment); + return MIB.addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); +} + XtensaInstrInfo::XtensaInstrInfo(const XtensaSubtarget &STI) - : XtensaGenInstrInfo(), RI(STI), STI(STI) {} + : XtensaGenInstrInfo(Xtensa::ADJCALLSTACKDOWN, Xtensa::ADJCALLSTACKUP), + RI(STI), STI(STI) {} + +/// Adjust SP by Amount bytes. +void XtensaInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, + MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const { + DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc(); + + if (Amount == 0) + return; + + MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Xtensa::ARRegClass; + + // create virtual reg to store immediate + unsigned Reg = RegInfo.createVirtualRegister(RC); + + if (isInt<8>(Amount)) { // addi sp, sp, amount + BuildMI(MBB, I, DL, get(Xtensa::ADDI), Reg).addReg(SP).addImm(Amount); + } else { // Expand immediate that doesn't fit in 8-bit. + unsigned Reg1; + loadImmediate(MBB, I, &Reg1, Amount); + BuildMI(MBB, I, DL, get(Xtensa::ADD), Reg) + .addReg(SP) + .addReg(Reg1, RegState::Kill); + } + + BuildMI(MBB, I, DL, get(Xtensa::OR), SP) + .addReg(Reg, RegState::Kill) + .addReg(Reg, RegState::Kill); +} + +void XtensaInstrInfo::copyPhysReg(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, MCRegister DestReg, + MCRegister SrcReg, bool KillSrc) const { + // The MOV instruction is not present in core ISA, + // so use OR instruction. + if (Xtensa::ARRegClass.contains(DestReg, SrcReg)) + BuildMI(MBB, MBBI, DL, get(Xtensa::OR), DestReg) + .addReg(SrcReg, getKillRegState(KillSrc)) + .addReg(SrcReg, getKillRegState(KillSrc)); + else + report_fatal_error("Impossible reg-to-reg copy"); +} + +void XtensaInstrInfo::storeRegToStackSlot( + MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, Register VReg) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + unsigned LoadOpcode, StoreOpcode; + getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx); + MachineInstrBuilder MIB = BuildMI(MBB, MBBI, DL, get(StoreOpcode)) + .addReg(SrcReg, getKillRegState(isKill)); + addFrameReference(MIB, FrameIdx); +} + +void XtensaInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + Register DestReg, int FrameIdx, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + unsigned LoadOpcode, StoreOpcode; + getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode, FrameIdx); + addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg), FrameIdx); +} + +void XtensaInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC, + unsigned &LoadOpcode, + unsigned &StoreOpcode, + int64_t offset) const { + assert((RC == &Xtensa::ARRegClass) && + "Unsupported regclass to load or store"); + + LoadOpcode = Xtensa::L32I; + StoreOpcode = Xtensa::S32I; +} + +void XtensaInstrInfo::loadImmediate(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, + unsigned *Reg, int64_t Value) const { + DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc(); + MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); + const TargetRegisterClass *RC = &Xtensa::ARRegClass; + + // create virtual reg to store immediate + *Reg = RegInfo.createVirtualRegister(RC); + if (Value >= -2048 && Value <= 2047) { + BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), *Reg).addImm(Value); + } else if (Value >= -32768 && Value <= 32767) { + int Low = Value & 0xFF; + int High = Value & ~0xFF; + + BuildMI(MBB, MBBI, DL, get(Xtensa::MOVI), *Reg).addImm(Low); + BuildMI(MBB, MBBI, DL, get(Xtensa::ADDMI), *Reg).addReg(*Reg).addImm(High); + } else if (Value >= -4294967296LL && Value <= 4294967295LL) { + // 32 bit arbirary constant + MachineConstantPool *MCP = MBB.getParent()->getConstantPool(); + uint64_t UVal = ((uint64_t)Value) & 0xFFFFFFFFLL; + const Constant *CVal = ConstantInt::get( + Type::getInt32Ty(MBB.getParent()->getFunction().getContext()), UVal, + false); + unsigned Idx = MCP->getConstantPoolIndex(CVal, Align(2U)); + // MCSymbol MSym + BuildMI(MBB, MBBI, DL, get(Xtensa::L32R), *Reg).addConstantPoolIndex(Idx); + } else { + // use L32R to let assembler load immediate best + // TODO replace to L32R + report_fatal_error("Unsupported load immediate value"); + } +} diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h index 8c73c9bd794081460aa9b862c5f8f2d3bfb11a6f..1acd314e2720a348b19f054003596a09718e24cf 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.h +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.h @@ -35,9 +35,38 @@ class XtensaInstrInfo : public XtensaGenInstrInfo { public: XtensaInstrInfo(const XtensaSubtarget &STI); + void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, + MachineBasicBlock::iterator I) const; + // Return the XtensaRegisterInfo, which this class owns. const XtensaRegisterInfo &getRegisterInfo() const { return RI; } + void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, + bool KillSrc) const override; + + void storeRegToStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, Register SrcReg, + bool isKill, int FrameIndex, + const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const override; + + void loadRegFromStackSlot(MachineBasicBlock &MBB, + MachineBasicBlock::iterator MBBI, Register DestReg, + int FrameIdx, const TargetRegisterClass *RC, + const TargetRegisterInfo *TRI, + Register VReg) const override; + + // Get the load and store opcodes for a given register class and offset. + void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, + unsigned &StoreOpcode, int64_t offset) const; + + // Emit code before MBBI in MI to move immediate value Value into + // physical register Reg. + void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, + unsigned *Reg, int64_t Value) const; + const XtensaSubtarget &getSubtarget() const { return STI; } }; } // end namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td index 268a9943d8c1604a930d3c9417a4f27000d3bd67..6e9e75257ccf4cb96aeb03038ca2bcc95469e988 100644 --- a/llvm/lib/Target/Xtensa/XtensaInstrInfo.td +++ b/llvm/lib/Target/Xtensa/XtensaInstrInfo.td @@ -14,6 +14,7 @@ include "XtensaInstrFormats.td" include "XtensaOperands.td" +include "XtensaOperators.td" //===----------------------------------------------------------------------===// // Arithmetic & Logical instructions @@ -238,6 +239,34 @@ def L32R : RI16_Inst<0x01, (outs AR:$t), (ins L32Rtarget:$label), let imm16 = label; } +// pcrel addr loading using L32R +def : Pat<(Xtensa_pcrel_wrapper tconstpool : $in), (L32R tconstpool : $in)>; + +// FrameIndexes are legalized when they are operands from load/store +// instructions. The same not happens for stack address copies, so an +// add op with mem ComplexPattern is used and the stack address copy +// can be matched. +// Setting of attribute mayLoad is trick to process instruction operands +// in function XtensaRegisterInfo::eliminateFI + +let isCodeGenOnly = 1, mayLoad = 1 in { + + def LEA_ADD : RRI8_Inst<0x02, (outs AR:$t), (ins mem32:$addr), + "addi\t$t, $addr", + [(set AR:$t, addr_ish4:$addr)]> { + bits<12> addr; + + let r = 0x0C; + let imm8{7-0} = addr{11-4}; + let s{3-0} = addr{3-0}; + } +} + +//extending loads +def : Pat<(i32 (extloadi1 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; +def : Pat<(i32 (extloadi8 addr_ish1:$addr)), (L8UI addr_ish1:$addr)>; +def : Pat<(i32 (extloadi16 addr_ish2:$addr)), (L16UI addr_ish2:$addr)>; + //===----------------------------------------------------------------------===// // Conditional branch instructions //===----------------------------------------------------------------------===// @@ -426,7 +455,7 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, Uses = [A0] in { def RET : CALLX_Inst<0x00, 0x00, 0x00, (outs), (ins), - "ret", []> { + "ret", [(Xtensa_ret)]> { let m = 0x2; let n = 0x0; let s = 0; @@ -434,6 +463,14 @@ let isReturn = 1, isTerminator = 1, } } +// Call patterns +def : Pat<(Xtensa_call (i32 tglobaladdr:$dst)), + (CALL0 tglobaladdr:$dst)>; +def : Pat<(Xtensa_call (i32 texternalsym:$dst)), + (CALL0 texternalsym:$dst)>; +def : Pat<(Xtensa_call AR:$dst), + (CALLX0 AR:$dst)>; + //===----------------------------------------------------------------------===// // Mem barrier instructions //===----------------------------------------------------------------------===// @@ -506,3 +543,19 @@ def XSR : RSR_Inst<0x00, 0x01, 0x06, (outs AR:$ard, SR:$srd), (ins AR:$t, SR:$sr "xsr\t$t, $sr", []> { let Constraints = "$ard = $t, $srd = $sr"; } + +//===----------------------------------------------------------------------===// +// Stack allocation +//===----------------------------------------------------------------------===// + +// ADJCALLSTACKDOWN/UP implicitly use/def SP because they may be expanded into +// a stack adjustment and the codegen must know that they may modify the stack +// pointer before prolog-epilog rewriting occurs. +let Defs = [SP], Uses = [SP] in { + def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKDOWN", + [(Xtensa_callseq_start timm:$amt1, timm:$amt2)]>; + def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2), + "#ADJCALLSTACKUP", + [(Xtensa_callseq_end timm:$amt1, timm:$amt2)]>; +} diff --git a/llvm/lib/Target/Xtensa/XtensaOperands.td b/llvm/lib/Target/Xtensa/XtensaOperands.td index 7a1a2e86e8c20fae34d1c80918fe88696576c728..f41081f9bf2f9686f5e56870da2a6db4f847959d 100644 --- a/llvm/lib/Target/Xtensa/XtensaOperands.td +++ b/llvm/lib/Target/Xtensa/XtensaOperands.td @@ -195,7 +195,7 @@ def jumptarget : Operand { let ParserMatchClass = XtensaPCRelTargetAsmOperand; } -def L32Rtarget : Operand { +def L32Rtarget : Operand { let PrintMethod = "printL32RTarget"; let EncoderMethod = "getL32RTargetEncoding"; let DecoderMethod = "decodeL32ROperand"; diff --git a/llvm/lib/Target/Xtensa/XtensaOperators.td b/llvm/lib/Target/Xtensa/XtensaOperators.td new file mode 100644 index 0000000000000000000000000000000000000000..cd4d831c85b581d15834b09a75b594205dd37078 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaOperators.td @@ -0,0 +1,36 @@ +//===- XtensaOperators.td - Xtensa-specific operators ---------*- tblgen-*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +//===----------------------------------------------------------------------===// +// Type profiles +//===----------------------------------------------------------------------===// +def SDT_XtensaCallSeqStart : SDCallSeqStart<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaCallSeqEnd : SDCallSeqEnd<[SDTCisVT<0, i32>, SDTCisVT<1, i32>]>; +def SDT_XtensaCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>; + +def SDT_XtensaWrapPtr : SDTypeProfile<1, 1, + [SDTCisSameAs<0, 1>, + SDTCisPtrTy<0>]>; + +//===----------------------------------------------------------------------===// +// Node definitions +//===----------------------------------------------------------------------===// +def Xtensa_call: SDNode<"XtensaISD::CALL", SDT_XtensaCall, + [SDNPHasChain, SDNPOutGlue, SDNPOptInGlue, SDNPVariadic]>; + +def Xtensa_ret: SDNode<"XtensaISD::RET", SDTNone, + [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>; + +def Xtensa_pcrel_wrapper: SDNode<"XtensaISD::PCREL_WRAPPER", SDT_XtensaWrapPtr, []>; + +def Xtensa_callseq_start: SDNode<"ISD::CALLSEQ_START", SDT_XtensaCallSeqStart, + [SDNPHasChain, SDNPSideEffect, SDNPOutGlue]>; + +def Xtensa_callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_XtensaCallSeqEnd, + [SDNPHasChain, SDNPSideEffect, SDNPOptInGlue, + SDNPOutGlue]>; diff --git a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp index f749cc51f96a04ebe222924ce697e73bcf1de601..bced2d4ad0095b43a61daa9302154014cb77f287 100644 --- a/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp +++ b/llvm/lib/Target/Xtensa/XtensaRegisterInfo.cpp @@ -13,6 +13,9 @@ #include "XtensaRegisterInfo.h" #include "XtensaInstrInfo.h" #include "XtensaSubtarget.h" +#include "XtensaUtils.h" +#include "llvm/CodeGen/MachineFrameInfo.h" +#include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/Support/Debug.h" @@ -31,15 +34,13 @@ XtensaRegisterInfo::XtensaRegisterInfo(const XtensaSubtarget &STI) const uint16_t * XtensaRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { - // Calling convention is not implemented yet - return nullptr; + return CSR_Xtensa_SaveList; } const uint32_t * XtensaRegisterInfo::getCallPreservedMask(const MachineFunction &MF, CallingConv::ID) const { - // Calling convention is not implemented yet - return nullptr; + return CSR_Xtensa_RegMask; } BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { @@ -60,7 +61,70 @@ BitVector XtensaRegisterInfo::getReservedRegs(const MachineFunction &MF) const { bool XtensaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj, unsigned FIOperandNum, RegScavenger *RS) const { - report_fatal_error("Eliminate frame index not supported yet"); + MachineInstr &MI = *II; + MachineFunction &MF = *MI.getParent()->getParent(); + int FrameIndex = MI.getOperand(FIOperandNum).getIndex(); + uint64_t StackSize = MF.getFrameInfo().getStackSize(); + int64_t SPOffset = MF.getFrameInfo().getObjectOffset(FrameIndex); + MachineFrameInfo &MFI = MF.getFrameInfo(); + const std::vector &CSI = MFI.getCalleeSavedInfo(); + int MinCSFI = 0; + int MaxCSFI = -1; + + if (CSI.size()) { + MinCSFI = CSI[0].getFrameIdx(); + MaxCSFI = CSI[CSI.size() - 1].getFrameIdx(); + } + // The following stack frame objects are always referenced relative to $sp: + // 1. Outgoing arguments. + // 2. Pointer to dynamically allocated stack space. + // 3. Locations for callee-saved registers. + // 4. Locations for eh data registers. + // Everything else is referenced relative to whatever register + // getFrameRegister() returns. + unsigned FrameReg; + if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI)) + FrameReg = Xtensa::SP; + else + FrameReg = getFrameRegister(MF); + + // Calculate final offset. + // - There is no need to change the offset if the frame object is one of the + // following: an outgoing argument, pointer to a dynamically allocated + // stack space or a $gp restore location, + // - If the frame object is any of the following, its offset must be adjusted + // by adding the size of the stack: + // incoming argument, callee-saved register location or local variable. + bool IsKill = false; + int64_t Offset = + SPOffset + (int64_t)StackSize + MI.getOperand(FIOperandNum + 1).getImm(); + + bool Valid = isValidAddrOffset(MI, Offset); + + // If MI is not a debug value, make sure Offset fits in the 16-bit immediate + // field. + if (!MI.isDebugValue() && !Valid) { + MachineBasicBlock &MBB = *MI.getParent(); + DebugLoc DL = II->getDebugLoc(); + unsigned ADD = Xtensa::ADD; + unsigned Reg; + const XtensaInstrInfo &TII = *static_cast( + MBB.getParent()->getSubtarget().getInstrInfo()); + + TII.loadImmediate(MBB, II, &Reg, Offset); + BuildMI(MBB, II, DL, TII.get(ADD), Reg) + .addReg(FrameReg) + .addReg(Reg, RegState::Kill); + + FrameReg = Reg; + Offset = 0; + IsKill = true; + } + + MI.getOperand(FIOperandNum).ChangeToRegister(FrameReg, false, false, IsKill); + MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset); + + return false; } Register XtensaRegisterInfo::getFrameRegister(const MachineFunction &MF) const { diff --git a/llvm/lib/Target/Xtensa/XtensaUtils.cpp b/llvm/lib/Target/Xtensa/XtensaUtils.cpp new file mode 100644 index 0000000000000000000000000000000000000000..98e424f6ea4406e3c8340a3bf7aa27e396244e76 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaUtils.cpp @@ -0,0 +1,59 @@ +//===--- XtensaUtils.cpp ---- Xtensa Utility Functions ----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains miscellaneous utility functions. +// +//===----------------------------------------------------------------------===// + +#include "XtensaUtils.h" + +namespace llvm { + +bool isValidAddrOffset(int Scale, int64_t OffsetVal) { + bool Valid = false; + + switch (Scale) { + case 1: + Valid = (OffsetVal >= 0 && OffsetVal <= 255); + break; + case 2: + Valid = (OffsetVal >= 0 && OffsetVal <= 510) && ((OffsetVal & 0x1) == 0); + break; + case 4: + Valid = (OffsetVal >= 0 && OffsetVal <= 1020) && ((OffsetVal & 0x3) == 0); + break; + default: + break; + } + return Valid; +} + +bool isValidAddrOffset(MachineInstr &MI, int64_t Offset) { + int Scale = 0; + + switch (MI.getOpcode()) { + case Xtensa::L8UI: + case Xtensa::S8I: + Scale = 1; + break; + case Xtensa::L16SI: + case Xtensa::L16UI: + case Xtensa::S16I: + Scale = 2; + break; + case Xtensa::LEA_ADD: + return (Offset >= -128 && Offset <= 127); + default: + // assume that MI is 32-bit load/store operation + Scale = 4; + break; + } + return isValidAddrOffset(Scale, Offset); +} + +} // namespace llvm diff --git a/llvm/lib/Target/Xtensa/XtensaUtils.h b/llvm/lib/Target/Xtensa/XtensaUtils.h new file mode 100644 index 0000000000000000000000000000000000000000..2b0ac37a6971a1fe77ad9dc9026ab45843a0b508 --- /dev/null +++ b/llvm/lib/Target/Xtensa/XtensaUtils.h @@ -0,0 +1,27 @@ +//===--- XtensaUtils.h ---- Xtensa Utility Functions ------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file contains miscellaneous utility functions. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_LIB_TARGET_XTENSA_XTENSAUTILS_H +#define LLVM_LIB_TARGET_XTENSA_XTENSAUTILS_H + +#include "XtensaInstrInfo.h" +#include "llvm/CodeGen/MachineInstr.h" + +namespace llvm { +// Check address offset for load/store instructions. +// The offset should be multiple of scale. +bool isValidAddrOffset(int Scale, int64_t OffsetVal); + +// Check address offset for load/store instructions. +bool isValidAddrOffset(MachineInstr &MI, int64_t Offset); +} // namespace llvm +#endif // LLVM_LIB_TARGET_XTENSA_XTENSAUTILS_H diff --git a/llvm/lib/TargetParser/CMakeLists.txt b/llvm/lib/TargetParser/CMakeLists.txt index da1e352b0373387ab738f5b300d66eab088cd402..4b5d582d57a42a566dc6ec89419efc1460e8cb05 100644 --- a/llvm/lib/TargetParser/CMakeLists.txt +++ b/llvm/lib/TargetParser/CMakeLists.txt @@ -20,6 +20,7 @@ add_llvm_component_library(LLVMTargetParser CSKYTargetParser.cpp Host.cpp LoongArchTargetParser.cpp + RISCVISAInfo.cpp RISCVTargetParser.cpp SubtargetFeature.cpp TargetParser.cpp @@ -37,5 +38,7 @@ add_llvm_component_library(LLVMTargetParser Support DEPENDS + ARMTargetParserTableGen + AArch64TargetParserTableGen RISCVTargetParserTableGen ) diff --git a/llvm/lib/Support/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp similarity index 93% rename from llvm/lib/Support/RISCVISAInfo.cpp rename to llvm/lib/TargetParser/RISCVISAInfo.cpp index fa967403ea449c9cba9bc4ca4a26460d9f9f8a74..39cb3f2c2fe17871a889f27609bcafc3dc0b5879 100644 --- a/llvm/lib/Support/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -1,4 +1,4 @@ -//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ------------*- C++ -*-===// +//===-- RISCVISAInfo.cpp - RISC-V Arch String Parser ----------------------===// // // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // See https://llvm.org/LICENSE.txt for license information. @@ -6,7 +6,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/ADT/MapVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/SetVector.h" @@ -29,7 +29,7 @@ namespace { struct RISCVSupportedExtension { const char *Name; /// Supported version. - RISCVISAInfo::ExtensionVersion Version; + RISCVISAUtils::ExtensionVersion Version; bool operator<(const RISCVSupportedExtension &RHS) const { return StringRef(Name) < StringRef(RHS.Name); @@ -43,8 +43,6 @@ struct RISCVProfile { } // end anonymous namespace -static constexpr StringLiteral AllStdExts = "mafdqlcbkjtpvnh"; - static const char *RISCVGImplications[] = { "i", "m", "a", "f", "d", "zicsr", "zifencei" }; @@ -370,7 +368,7 @@ struct LessExtName { }; } // namespace -static std::optional +static std::optional findDefaultVersion(StringRef ExtName) { // Find default version of an extension. // TODO: We might set default version based on profile or ISA spec. @@ -387,7 +385,7 @@ findDefaultVersion(StringRef ExtName) { } void RISCVISAInfo::addExtension(StringRef ExtName, - RISCVISAInfo::ExtensionVersion Version) { + RISCVISAUtils::ExtensionVersion Version) { Exts[ExtName.str()] = Version; } @@ -411,7 +409,7 @@ static StringRef getExtensionType(StringRef Ext) { return StringRef(); } -static std::optional +static std::optional isExperimentalExtension(StringRef Ext) { auto I = llvm::lower_bound(SupportedExperimentalExtensions, Ext, LessExtName()); @@ -468,78 +466,6 @@ bool RISCVISAInfo::hasExtension(StringRef Ext) const { return Exts.count(Ext.str()) != 0; } -// We rank extensions in the following order: -// -Single letter extensions in canonical order. -// -Unknown single letter extensions in alphabetical order. -// -Multi-letter extensions starting with 'z' sorted by canonical order of -// the second letter then sorted alphabetically. -// -Multi-letter extensions starting with 's' in alphabetical order. -// -(TODO) Multi-letter extensions starting with 'zxm' in alphabetical order. -// -X extensions in alphabetical order. -// These flags are used to indicate the category. The first 6 bits store the -// single letter extension rank for single letter and multi-letter extensions -// starting with 'z'. -enum RankFlags { - RF_Z_EXTENSION = 1 << 6, - RF_S_EXTENSION = 1 << 7, - RF_X_EXTENSION = 1 << 8, -}; - -// Get the rank for single-letter extension, lower value meaning higher -// priority. -static unsigned singleLetterExtensionRank(char Ext) { - assert(Ext >= 'a' && Ext <= 'z'); - switch (Ext) { - case 'i': - return 0; - case 'e': - return 1; - } - - size_t Pos = AllStdExts.find(Ext); - if (Pos != StringRef::npos) - return Pos + 2; // Skip 'e' and 'i' from above. - - // If we got an unknown extension letter, then give it an alphabetical - // order, but after all known standard extensions. - return 2 + AllStdExts.size() + (Ext - 'a'); -} - -// Get the rank for multi-letter extension, lower value meaning higher -// priority/order in canonical order. -static unsigned getExtensionRank(const std::string &ExtName) { - assert(ExtName.size() >= 1); - switch (ExtName[0]) { - case 's': - return RF_S_EXTENSION; - case 'z': - assert(ExtName.size() >= 2); - // `z` extension must be sorted by canonical order of second letter. - // e.g. zmx has higher rank than zax. - return RF_Z_EXTENSION | singleLetterExtensionRank(ExtName[1]); - case 'x': - return RF_X_EXTENSION; - default: - assert(ExtName.size() == 1); - return singleLetterExtensionRank(ExtName[0]); - } -} - -// Compare function for extension. -// Only compare the extension name, ignore version comparison. -bool RISCVISAInfo::compareExtension(const std::string &LHS, - const std::string &RHS) { - unsigned LHSRank = getExtensionRank(LHS); - unsigned RHSRank = getExtensionRank(RHS); - - // If the ranks differ, pick the lower rank. - if (LHSRank != RHSRank) - return LHSRank < RHSRank; - - // If the rank is same, it must be sorted by lexicographic order. - return LHS < RHS; -} - std::vector RISCVISAInfo::toFeatures(bool AddAllExtensions, bool IgnoreUnknown) const { std::vector Features; @@ -808,7 +734,7 @@ static Error splitExtsByUnderscore(StringRef Exts, static Error processMultiLetterExtension( StringRef RawExt, - MapVector> &SeenExtMap, bool IgnoreUnknown, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck) { @@ -854,7 +780,7 @@ static Error processMultiLetterExtension( static Error processSingleLetterExtension( StringRef &RawExt, - MapVector> &SeenExtMap, bool IgnoreUnknown, bool EnableExperimentalExtension, bool ExperimentalExtensionVersionCheck) { @@ -930,7 +856,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, unsigned XLen = HasRV64 ? 64 : 32; std::unique_ptr ISAInfo(new RISCVISAInfo(XLen)); - MapVector> SeenExtMap; @@ -1007,7 +933,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, for (auto &Ext : SplitExts) { StringRef CurrExt = Ext; while (!CurrExt.empty()) { - if (AllStdExts.contains(CurrExt.front())) { + if (RISCVISAUtils::AllStdExts.contains(CurrExt.front())) { if (auto E = processSingleLetterExtension( CurrExt, SeenExtMap, IgnoreUnknown, EnableExperimentalExtension, ExperimentalExtensionVersionCheck)) @@ -1041,7 +967,7 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, // Check all Extensions are supported. for (auto &SeenExtAndVers : SeenExtMap) { const std::string &ExtName = SeenExtAndVers.first; - RISCVISAInfo::ExtensionVersion ExtVers = SeenExtAndVers.second; + RISCVISAUtils::ExtensionVersion ExtVers = SeenExtAndVers.second; if (!RISCVISAInfo::isSupportedExtension(ExtName)) return getStringErrorForInvalidExt(ExtName); @@ -1102,20 +1028,28 @@ Error RISCVISAInfo::checkDependency() { return createStringError(errc::invalid_argument, "'zcf' is only supported for 'rv32'"); + if (Exts.count("zacas") && !(Exts.count("a") || Exts.count("zamo"))) + return createStringError( + errc::invalid_argument, + "'zacas' requires 'a' or 'zaamo' extension to also be specified"); + + if (Exts.count("zabha") && !(Exts.count("a") || Exts.count("zamo"))) + return createStringError( + errc::invalid_argument, + "'zabha' requires 'a' or 'zaamo' extension to also be specified"); + return Error::success(); } static const char *ImpliedExtsD[] = {"f"}; static const char *ImpliedExtsF[] = {"zicsr"}; static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"}; -static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsXSfvcp[] = {"zve32x"}; static const char *ImpliedExtsXSfvfnrclipxfqf[] = {"zve32f"}; static const char *ImpliedExtsXSfvfwmaccqqq[] = {"zvfbfmin"}; static const char *ImpliedExtsXSfvqmaccdod[] = {"zve32x"}; static const char *ImpliedExtsXSfvqmaccqoq[] = {"zve32x"}; -static const char *ImpliedExtsZabha[] = {"a"}; -static const char *ImpliedExtsZacas[] = {"a"}; +static const char *ImpliedExtsXTHeadVdot[] = {"v"}; static const char *ImpliedExtsZcb[] = {"zca"}; static const char *ImpliedExtsZcd[] = {"d", "zca"}; static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"}; @@ -1131,8 +1065,8 @@ static const char *ImpliedExtsZfhmin[] = {"f"}; static const char *ImpliedExtsZfinx[] = {"zicsr"}; static const char *ImpliedExtsZhinx[] = {"zhinxmin"}; static const char *ImpliedExtsZhinxmin[] = {"zfinx"}; -static const char *ImpliedExtsZicntr[] = {"zicsr"}; static const char *ImpliedExtsZicfiss[] = {"zicsr", "zimop"}; +static const char *ImpliedExtsZicntr[] = {"zicsr"}; static const char *ImpliedExtsZihpm[] = {"zicsr"}; static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"}; static const char *ImpliedExtsZkn[] = {"zbkb", "zbkc", "zbkx", @@ -1189,8 +1123,6 @@ static constexpr ImpliedExtsEntry ImpliedExts[] = { {{"xsfvqmaccdod"}, {ImpliedExtsXSfvqmaccdod}}, {{"xsfvqmaccqoq"}, {ImpliedExtsXSfvqmaccqoq}}, {{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}}, - {{"zabha"}, {ImpliedExtsZabha}}, - {{"zacas"}, {ImpliedExtsZacas}}, {{"zcb"}, {ImpliedExtsZcb}}, {{"zcd"}, {ImpliedExtsZcd}}, {{"zce"}, {ImpliedExtsZce}}, diff --git a/llvm/lib/TargetParser/RISCVTargetParser.cpp b/llvm/lib/TargetParser/RISCVTargetParser.cpp index 0d95e3a9b8196293df4cd64b46c9f18c62d3bb22..9003f9beffa7e7a19fb690f2367573d180efd051 100644 --- a/llvm/lib/TargetParser/RISCVTargetParser.cpp +++ b/llvm/lib/TargetParser/RISCVTargetParser.cpp @@ -14,7 +14,7 @@ #include "llvm/TargetParser/RISCVTargetParser.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringSwitch.h" -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/TargetParser/Triple.h" namespace llvm { diff --git a/llvm/lib/Transforms/Coroutines/CoroInstr.h b/llvm/lib/Transforms/Coroutines/CoroInstr.h index 79e745bb162cdb23c4fa9db751b2fb7802a138ae..a31703fe01304c9311383d0f1bb4b4247f595892 100644 --- a/llvm/lib/Transforms/Coroutines/CoroInstr.h +++ b/llvm/lib/Transforms/Coroutines/CoroInstr.h @@ -78,10 +78,10 @@ public: } }; -/// This represents the llvm.coro.await.suspend instruction. +/// This represents the llvm.coro.await.suspend.{void,bool,handle} instructions. // FIXME: add callback metadata // FIXME: make a proper IntrinisicInst. Currently this is not possible, -// because llvm.coro.await.suspend can be invoked. +// because llvm.coro.await.suspend.* can be invoked. class LLVM_LIBRARY_VISIBILITY CoroAwaitSuspendInst : public CallBase { enum { AwaiterArg, FrameArg, WrapperArg }; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index fc284bc61cce97c3a5f5eebb1bffb072fb95dadc..88b7e496897e1f1aa93dd078ccab153b24f83df7 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -1134,6 +1134,8 @@ static bool MulWillOverflow(APInt &C0, APInt &C1, bool IsSigned) { // Simplifies X % C0 + (( X / C0 ) % C1) * C0 to X % (C0 * C1), where (C0 * C1) // does not overflow. +// Simplifies (X / C0) * C1 + (X % C0) * C2 to +// (X / C0) * (C1 - C2 * C0) + X * C2 Value *InstCombinerImpl::SimplifyAddWithRemainder(BinaryOperator &I) { Value *LHS = I.getOperand(0), *RHS = I.getOperand(1); Value *X, *MulOpV; @@ -1161,6 +1163,33 @@ Value *InstCombinerImpl::SimplifyAddWithRemainder(BinaryOperator &I) { } } + // Match I = (X / C0) * C1 + (X % C0) * C2 + Value *Div, *Rem; + APInt C1, C2; + if (!LHS->hasOneUse() || !MatchMul(LHS, Div, C1)) + Div = LHS, C1 = APInt(I.getType()->getScalarSizeInBits(), 1); + if (!RHS->hasOneUse() || !MatchMul(RHS, Rem, C2)) + Rem = RHS, C2 = APInt(I.getType()->getScalarSizeInBits(), 1); + if (match(Div, m_IRem(m_Value(), m_Value()))) { + std::swap(Div, Rem); + std::swap(C1, C2); + } + Value *DivOpV; + APInt DivOpC; + if (MatchRem(Rem, X, C0, IsSigned) && + MatchDiv(Div, DivOpV, DivOpC, IsSigned) && X == DivOpV && C0 == DivOpC) { + APInt NewC = C1 - C2 * C0; + if (!NewC.isZero() && !Rem->hasOneUse()) + return nullptr; + if (!isGuaranteedNotToBeUndef(X, &AC, &I, &DT)) + return nullptr; + Value *MulXC2 = Builder.CreateMul(X, ConstantInt::get(X->getType(), C2)); + if (NewC.isZero()) + return MulXC2; + return Builder.CreateAdd( + Builder.CreateMul(Div, ConstantInt::get(X->getType(), NewC)), MulXC2); + } + return nullptr; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index e1923a3441790a349a371321f0200f0e5e4e2f3f..8ec1ed7529c1cbe81154c9e3b0c0595b8a2e0dc1 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -3958,6 +3958,10 @@ Instruction *InstCombinerImpl::visitOr(BinaryOperator &I) { /*SimplifyOnly*/ false, *this)) return BinaryOperator::CreateOr(Op0, V); + if (cast(I).isDisjoint()) + if (Value *V = SimplifyAddWithRemainder(I)) + return replaceInstUsesWith(I, V); + return nullptr; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index a37a4cde96f899f9ac8c43e491ae80bfad5dc754..e5652458f150b56cc59b11c542f9aaf8b66e7c39 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -606,14 +606,13 @@ static Instruction *foldCttzCtlz(IntrinsicInst &II, InstCombinerImpl &IC) { return IC.replaceOperand(II, 1, IC.Builder.getTrue()); } - // Add range metadata since known bits can't completely reflect what we know. - auto *IT = cast(Op0->getType()->getScalarType()); - if (IT && IT->getBitWidth() != 1 && !II.getMetadata(LLVMContext::MD_range)) { - Metadata *LowAndHigh[] = { - ConstantAsMetadata::get(ConstantInt::get(IT, DefiniteZeros)), - ConstantAsMetadata::get(ConstantInt::get(IT, PossibleZeros + 1))}; - II.setMetadata(LLVMContext::MD_range, - MDNode::get(II.getContext(), LowAndHigh)); + // Add range attribute since known bits can't completely reflect what we know. + unsigned BitWidth = Op0->getType()->getScalarSizeInBits(); + if (BitWidth != 1 && !II.hasRetAttr(Attribute::Range) && + !II.getMetadata(LLVMContext::MD_range)) { + ConstantRange Range(APInt(BitWidth, DefiniteZeros), + APInt(BitWidth, PossibleZeros + 1)); + II.addRangeRetAttr(Range); return &II; } @@ -685,16 +684,12 @@ static Instruction *foldCtpop(IntrinsicInst &II, InstCombinerImpl &IC) { Constant::getNullValue(Ty)), Ty); - // Add range metadata since known bits can't completely reflect what we know. - auto *IT = cast(Ty->getScalarType()); - unsigned MinCount = Known.countMinPopulation(); - unsigned MaxCount = Known.countMaxPopulation(); - if (IT->getBitWidth() != 1 && !II.getMetadata(LLVMContext::MD_range)) { - Metadata *LowAndHigh[] = { - ConstantAsMetadata::get(ConstantInt::get(IT, MinCount)), - ConstantAsMetadata::get(ConstantInt::get(IT, MaxCount + 1))}; - II.setMetadata(LLVMContext::MD_range, - MDNode::get(II.getContext(), LowAndHigh)); + // Add range attribute since known bits can't completely reflect what we know. + if (BitWidth != 1 && !II.hasRetAttr(Attribute::Range) && + !II.getMetadata(LLVMContext::MD_range)) { + ConstantRange Range(APInt(BitWidth, Known.countMinPopulation()), + APInt(BitWidth, Known.countMaxPopulation() + 1)); + II.addRangeRetAttr(Range); return &II; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp index d697f361dec023392347c7bdda0d1228ca54a702..ed2a98ba4ae40ede47264d0c0fc9776d43a7ff1a 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineNegator.cpp @@ -320,7 +320,8 @@ std::array Negator::getSortedOperandsOfBinOp(Instruction *I) { return NegatedPHI; } case Instruction::Select: { - if (isKnownNegation(I->getOperand(1), I->getOperand(2))) { + if (isKnownNegation(I->getOperand(1), I->getOperand(2), /*NeedNSW=*/false, + /*AllowPoison=*/false)) { // Of one hand of select is known to be negation of another hand, // just swap the hands around. auto *NewSelect = cast(I->clone()); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 73600206a55c145fea16ff180fe8d62f67941173..117eb7a1dcc933d088e2634a718f0bd65274dd39 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -1722,11 +1722,11 @@ static Instruction *foldSelectICmpEq(SelectInst &SI, ICmpInst *ICI, return match(CmpRHS, m_Zero()) && match(FalseVal, matchInner); if (NotMask == NotInner) { - return match(FalseVal, - m_c_BinOp(OuterOpc, m_Not(matchInner), m_Specific(CmpRHS))); + return match(FalseVal, m_c_BinOp(OuterOpc, m_NotForbidPoison(matchInner), + m_Specific(CmpRHS))); } else if (NotMask == NotRHS) { - return match(FalseVal, - m_c_BinOp(OuterOpc, matchInner, m_Not(m_Specific(CmpRHS)))); + return match(FalseVal, m_c_BinOp(OuterOpc, matchInner, + m_NotForbidPoison(m_Specific(CmpRHS)))); } else { return match(FalseVal, m_c_BinOp(OuterOpc, matchInner, m_Specific(CmpRHS))); diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp index a35f24447cc39b7f65f3b0d06b7919a23319ff6e..88b85234034038517fc5f1e55c02c2c3c834e60b 100644 --- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp @@ -930,11 +930,33 @@ void HWAddressSanitizer::instrumentMemAccessOutline(Value *Ptr, bool IsWrite, IRBuilder<> IRB(InsertBefore); Module *M = IRB.GetInsertBlock()->getParent()->getParent(); - IRB.CreateCall(Intrinsic::getDeclaration( - M, UseShortGranules - ? Intrinsic::hwasan_check_memaccess_shortgranules - : Intrinsic::hwasan_check_memaccess), - {ShadowBase, Ptr, ConstantInt::get(Int32Ty, AccessInfo)}); + bool useFixedShadowIntrinsic = false; + // The memaccess fixed shadow intrinsic is only supported on AArch64, + // which allows a 16-bit immediate to be left-shifted by 32. + // Since kShadowBaseAlignment == 32, and Linux by default will not + // mmap above 48-bits, practically any valid shadow offset is + // representable. + // In particular, an offset of 4TB (1024 << 32) is representable, and + // ought to be good enough for anybody. + if (TargetTriple.isAArch64() && Mapping.Offset != kDynamicShadowSentinel) { + uint16_t offset_shifted = Mapping.Offset >> 32; + useFixedShadowIntrinsic = (uint64_t)offset_shifted << 32 == Mapping.Offset; + } + + if (useFixedShadowIntrinsic) + IRB.CreateCall( + Intrinsic::getDeclaration( + M, UseShortGranules + ? Intrinsic::hwasan_check_memaccess_shortgranules_fixedshadow + : Intrinsic::hwasan_check_memaccess_fixedshadow), + {Ptr, ConstantInt::get(Int32Ty, AccessInfo), + ConstantInt::get(Int64Ty, Mapping.Offset)}); + else + IRB.CreateCall(Intrinsic::getDeclaration( + M, UseShortGranules + ? Intrinsic::hwasan_check_memaccess_shortgranules + : Intrinsic::hwasan_check_memaccess), + {ShadowBase, Ptr, ConstantInt::get(Int32Ty, AccessInfo)}); } void HWAddressSanitizer::instrumentMemAccessInline(Value *Ptr, bool IsWrite, diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 824cbee4eca5783bc63e0c1b317c2e0748b62a56..e5ef0333696d0f68e55c7a4ff23e0b3c6779e670 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -152,6 +152,7 @@ #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/DepthFirstIterator.h" #include "llvm/ADT/SetVector.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" @@ -1464,19 +1465,21 @@ struct MemorySanitizerVisitor : public InstVisitor { } void materializeChecks() { - llvm::stable_sort(InstrumentationList, - [](const ShadowOriginAndInsertPoint &L, - const ShadowOriginAndInsertPoint &R) { - return L.OrigIns < R.OrigIns; - }); +#ifndef NDEBUG + // For assert below. + SmallPtrSet Done; +#endif for (auto I = InstrumentationList.begin(); I != InstrumentationList.end();) { - auto J = - std::find_if(I + 1, InstrumentationList.end(), - [L = I->OrigIns](const ShadowOriginAndInsertPoint &R) { - return L != R.OrigIns; - }); + auto OrigIns = I->OrigIns; + // Checks are grouped by the original instruction. We call all + // `insertShadowCheck` for an instruction at once. + assert(Done.insert(OrigIns).second); + auto J = std::find_if(I + 1, InstrumentationList.end(), + [OrigIns](const ShadowOriginAndInsertPoint &R) { + return OrigIns != R.OrigIns; + }); // Process all checks of instruction at once. materializeInstructionChecks(ArrayRef(I, J)); I = J; diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp index 86d5c9909f3dc5a200d1ddd5c1450eab0593de85..d829e92b24440a194013236d3fb48fcda8e2468b 100644 --- a/llvm/lib/Transforms/Scalar/GVN.cpp +++ b/llvm/lib/Transforms/Scalar/GVN.cpp @@ -33,6 +33,7 @@ #include "llvm/Analysis/GlobalsModRef.h" #include "llvm/Analysis/InstructionPrecedenceTracking.h" #include "llvm/Analysis/InstructionSimplify.h" +#include "llvm/Analysis/Loads.h" #include "llvm/Analysis/LoopInfo.h" #include "llvm/Analysis/MemoryBuiltins.h" #include "llvm/Analysis/MemoryDependenceAnalysis.h" @@ -2419,6 +2420,10 @@ bool GVNPass::propagateEquality(Value *LHS, Value *RHS, if (isa(LHS) || (isa(LHS) && !isa(RHS))) std::swap(LHS, RHS); assert((isa(LHS) || isa(LHS)) && "Unexpected value!"); + const DataLayout &DL = + isa(LHS) + ? cast(LHS)->getParent()->getParent()->getDataLayout() + : cast(LHS)->getModule()->getDataLayout(); // If there is no obvious reason to prefer the left-hand side over the // right-hand side, ensure the longest lived term is on the right-hand side, @@ -2445,23 +2450,32 @@ bool GVNPass::propagateEquality(Value *LHS, Value *RHS, // using the leader table is about compiling faster, not optimizing better). // The leader table only tracks basic blocks, not edges. Only add to if we // have the simple case where the edge dominates the end. - if (RootDominatesEnd && !isa(RHS)) + if (RootDominatesEnd && !isa(RHS) && + canReplacePointersIfEqual(LHS, RHS, DL)) addToLeaderTable(LVN, RHS, Root.getEnd()); // Replace all occurrences of 'LHS' with 'RHS' everywhere in the scope. As // LHS always has at least one use that is not dominated by Root, this will // never do anything if LHS has only one use. if (!LHS->hasOneUse()) { + // Create a callback that captures the DL. + auto canReplacePointersCallBack = [&DL](const Use &U, const Value *To) { + return canReplacePointersInUseIfEqual(U, To, DL); + }; unsigned NumReplacements = DominatesByEdge - ? replaceDominatedUsesWith(LHS, RHS, *DT, Root) - : replaceDominatedUsesWith(LHS, RHS, *DT, Root.getStart()); - - Changed |= NumReplacements > 0; - NumGVNEqProp += NumReplacements; - // Cached information for anything that uses LHS will be invalid. - if (MD) - MD->invalidateCachedPointerInfo(LHS); + ? replaceDominatedUsesWithIf(LHS, RHS, *DT, Root, + canReplacePointersCallBack) + : replaceDominatedUsesWithIf(LHS, RHS, *DT, Root.getStart(), + canReplacePointersCallBack); + + if (NumReplacements > 0) { + Changed = true; + NumGVNEqProp += NumReplacements; + // Cached information for anything that uses LHS will be invalid. + if (MD) + MD->invalidateCachedPointerInfo(LHS); + } } // Now try to deduce additional equalities from this one. For example, if diff --git a/llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp b/llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp index f4207474e9a68a716ffa25e076393d6afd39ff0d..59a7dd1a00ed48a0186846faf6c23598fb95badd 100644 --- a/llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp +++ b/llvm/lib/Transforms/Utils/EntryExitInstrumenter.cpp @@ -137,7 +137,8 @@ static bool runOnFunction(Function &F, bool PostInlining) { PreservedAnalyses llvm::EntryExitInstrumenterPass::run(Function &F, FunctionAnalysisManager &AM) { - runOnFunction(F, PostInlining); + if (!runOnFunction(F, PostInlining)) + return PreservedAnalyses::all(); PreservedAnalyses PA; PA.preserveSet(); return PA; diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index a42ef0c4e6ae9ed03f2b6f93add92c2ba5b06013..5f456092bf4e9a8b6b9a43033343545c60247c10 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -59,6 +59,7 @@ #include "llvm/IR/IntrinsicsWebAssembly.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/MDBuilder.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" #include "llvm/IR/PatternMatch.h" @@ -3284,6 +3285,9 @@ void llvm::combineMetadata(Instruction *K, const Instruction *J, case LLVMContext::MD_invariant_group: // Preserve !invariant.group in K. break; + case LLVMContext::MD_mmra: + // Combine MMRAs + break; case LLVMContext::MD_align: if (DoesKMove || !K->hasMetadata(LLVMContext::MD_noundef)) K->setMetadata( @@ -3322,6 +3326,16 @@ void llvm::combineMetadata(Instruction *K, const Instruction *J, if (auto *JMD = J->getMetadata(LLVMContext::MD_invariant_group)) if (isa(K) || isa(K)) K->setMetadata(LLVMContext::MD_invariant_group, JMD); + + // Merge MMRAs. + // This is handled separately because we also want to handle cases where K + // doesn't have tags but J does. + auto JMMRA = J->getMetadata(LLVMContext::MD_mmra); + auto KMMRA = K->getMetadata(LLVMContext::MD_mmra); + if (JMMRA || KMMRA) { + K->setMetadata(LLVMContext::MD_mmra, + MMRAMetadata::combine(K->getContext(), JMMRA, KMMRA)); + } } void llvm::combineMetadataForCSE(Instruction *K, const Instruction *J, @@ -3341,7 +3355,8 @@ void llvm::combineMetadataForCSE(Instruction *K, const Instruction *J, LLVMContext::MD_preserve_access_index, LLVMContext::MD_prof, LLVMContext::MD_nontemporal, - LLVMContext::MD_noundef}; + LLVMContext::MD_noundef, + LLVMContext::MD_mmra}; combineMetadata(K, J, KnownIDs, KDominatesJ); } @@ -3429,15 +3444,15 @@ void llvm::patchReplacementInstruction(Instruction *I, Value *Repl) { combineMetadataForCSE(ReplInst, I, false); } -template +template static unsigned replaceDominatedUsesWith(Value *From, Value *To, const RootType &Root, - const DominatesFn &Dominates) { + const ShouldReplaceFn &ShouldReplace) { assert(From->getType() == To->getType()); unsigned Count = 0; for (Use &U : llvm::make_early_inc_range(From->uses())) { - if (!Dominates(Root, U)) + if (!ShouldReplace(Root, U)) continue; LLVM_DEBUG(dbgs() << "Replace dominated use of '"; From->printAsOperand(dbgs()); @@ -3481,6 +3496,26 @@ unsigned llvm::replaceDominatedUsesWith(Value *From, Value *To, return ::replaceDominatedUsesWith(From, To, BB, Dominates); } +unsigned llvm::replaceDominatedUsesWithIf( + Value *From, Value *To, DominatorTree &DT, const BasicBlockEdge &Root, + function_ref ShouldReplace) { + auto DominatesAndShouldReplace = + [&DT, &ShouldReplace, To](const BasicBlockEdge &Root, const Use &U) { + return DT.dominates(Root, U) && ShouldReplace(U, To); + }; + return ::replaceDominatedUsesWith(From, To, Root, DominatesAndShouldReplace); +} + +unsigned llvm::replaceDominatedUsesWithIf( + Value *From, Value *To, DominatorTree &DT, const BasicBlock *BB, + function_ref ShouldReplace) { + auto DominatesAndShouldReplace = [&DT, &ShouldReplace, + To](const BasicBlock *BB, const Use &U) { + return DT.dominates(BB, U) && ShouldReplace(U, To); + }; + return ::replaceDominatedUsesWith(From, To, BB, DominatesAndShouldReplace); +} + bool llvm::callsGCLeafFunction(const CallBase *Call, const TargetLibraryInfo &TLI) { // Check if the function is specifically marked as a gc leaf function. diff --git a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp index 0826d748ba0d2a8d85f30c94977c113a3a840928..3eda669eb8a7263c9b17d25415c1b860f07ba55d 100644 --- a/llvm/lib/Transforms/Utils/SimplifyCFG.cpp +++ b/llvm/lib/Transforms/Utils/SimplifyCFG.cpp @@ -51,6 +51,7 @@ #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/LLVMContext.h" #include "llvm/IR/MDBuilder.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/Metadata.h" #include "llvm/IR/Module.h" #include "llvm/IR/NoFolder.h" @@ -1677,7 +1678,8 @@ bool SimplifyCFGOpt::hoistCommonCodeFromSuccessors(BasicBlock *BB, for (auto &SuccIter : OtherSuccIterRange) { Instruction *I2 = &*SuccIter; HasTerminator |= I2->isTerminator(); - if (AllInstsAreIdentical && !I1->isIdenticalToWhenDefined(I2)) + if (AllInstsAreIdentical && (!I1->isIdenticalToWhenDefined(I2) || + MMRAMetadata(*I1) != MMRAMetadata(*I2))) AllInstsAreIdentical = false; } @@ -1964,6 +1966,7 @@ static bool canSinkInstructions( } const Instruction *I0 = Insts.front(); + const auto I0MMRA = MMRAMetadata(*I0); for (auto *I : Insts) { if (!I->isSameOperationAs(I0)) return false; @@ -1975,6 +1978,11 @@ static bool canSinkInstructions( return false; if (isa(I) && I->getOperand(0)->isSwiftError()) return false; + + // Treat MMRAs conservatively. This pass can be quite aggressive and + // could drop a lot of MMRAs otherwise. + if (MMRAMetadata(*I) != I0MMRA) + return false; } // All instructions in Insts are known to be the same opcode. If they have a diff --git a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp index da03a69708ddfc7e95a4fbc0be4c05215f55d5d4..da3c780550a083ce7470b3dfa3e2cee12d5d214c 100644 --- a/llvm/lib/Transforms/Vectorize/VectorCombine.cpp +++ b/llvm/lib/Transforms/Vectorize/VectorCombine.cpp @@ -1395,60 +1395,91 @@ bool VectorCombine::scalarizeLoadExtract(Instruction &I) { return true; } -/// Try to convert "shuffle (binop), (binop)" with a shared binop operand into -/// "binop (shuffle), (shuffle)". +/// Try to convert "shuffle (binop), (binop)" into "binop (shuffle), (shuffle)". bool VectorCombine::foldShuffleOfBinops(Instruction &I) { - auto *VecTy = cast(I.getType()); BinaryOperator *B0, *B1; - ArrayRef Mask; + ArrayRef OldMask; if (!match(&I, m_Shuffle(m_OneUse(m_BinOp(B0)), m_OneUse(m_BinOp(B1)), - m_Mask(Mask))) || - B0->getOpcode() != B1->getOpcode() || B0->getType() != VecTy) + m_Mask(OldMask)))) return false; // Don't introduce poison into div/rem. - if (any_of(Mask, [](int M) { return M == PoisonMaskElem; }) && + if (any_of(OldMask, [](int M) { return M == PoisonMaskElem; }) && B0->isIntDivRem()) return false; - // Try to replace a binop with a shuffle if the shuffle is not costly. - // The new shuffle will choose from a single, common operand, so it may be - // cheaper than the existing two-operand shuffle. - SmallVector UnaryMask = createUnaryMask(Mask, Mask.size()); + // TODO: Add support for addlike etc. Instruction::BinaryOps Opcode = B0->getOpcode(); - InstructionCost BinopCost = TTI.getArithmeticInstrCost(Opcode, VecTy); - InstructionCost ShufCost = TTI.getShuffleCost( - TargetTransformInfo::SK_PermuteSingleSrc, VecTy, UnaryMask); - if (ShufCost > BinopCost) + if (Opcode != B1->getOpcode()) + return false; + + auto *ShuffleDstTy = dyn_cast(I.getType()); + auto *BinOpTy = dyn_cast(B0->getType()); + if (!ShuffleDstTy || !BinOpTy) return false; + unsigned NumSrcElts = BinOpTy->getNumElements(); + // If we have something like "add X, Y" and "add Z, X", swap ops to match. Value *X = B0->getOperand(0), *Y = B0->getOperand(1); Value *Z = B1->getOperand(0), *W = B1->getOperand(1); - if (BinaryOperator::isCommutative(Opcode) && X != Z && Y != W) + if (BinaryOperator::isCommutative(Opcode) && X != Z && Y != W && + (X == W || Y == Z)) std::swap(X, Y); - Value *Shuf0, *Shuf1; + auto ConvertToUnary = [NumSrcElts](int &M) { + if (M >= (int)NumSrcElts) + M -= NumSrcElts; + }; + + SmallVector NewMask0(OldMask.begin(), OldMask.end()); + TargetTransformInfo::ShuffleKind SK0 = TargetTransformInfo::SK_PermuteTwoSrc; if (X == Z) { - // shuf (bo X, Y), (bo X, W) --> bo (shuf X), (shuf Y, W) - Shuf0 = Builder.CreateShuffleVector(X, UnaryMask); - Shuf1 = Builder.CreateShuffleVector(Y, W, Mask); - } else if (Y == W) { - // shuf (bo X, Y), (bo Z, Y) --> bo (shuf X, Z), (shuf Y) - Shuf0 = Builder.CreateShuffleVector(X, Z, Mask); - Shuf1 = Builder.CreateShuffleVector(Y, UnaryMask); - } else { - return false; + llvm::for_each(NewMask0, ConvertToUnary); + SK0 = TargetTransformInfo::SK_PermuteSingleSrc; + Z = PoisonValue::get(BinOpTy); } + SmallVector NewMask1(OldMask.begin(), OldMask.end()); + TargetTransformInfo::ShuffleKind SK1 = TargetTransformInfo::SK_PermuteTwoSrc; + if (Y == W) { + llvm::for_each(NewMask1, ConvertToUnary); + SK1 = TargetTransformInfo::SK_PermuteSingleSrc; + W = PoisonValue::get(BinOpTy); + } + + // Try to replace a binop with a shuffle if the shuffle is not costly. + TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; + + InstructionCost OldCost = + TTI.getArithmeticInstrCost(B0->getOpcode(), BinOpTy, CostKind) + + TTI.getArithmeticInstrCost(B1->getOpcode(), BinOpTy, CostKind) + + TTI.getShuffleCost(TargetTransformInfo::SK_PermuteTwoSrc, BinOpTy, + OldMask, CostKind, 0, nullptr, {B0, B1}, &I); + + InstructionCost NewCost = + TTI.getShuffleCost(SK0, BinOpTy, NewMask0, CostKind, 0, nullptr, {X, Z}) + + TTI.getShuffleCost(SK1, BinOpTy, NewMask1, CostKind, 0, nullptr, {Y, W}) + + TTI.getArithmeticInstrCost(Opcode, ShuffleDstTy, CostKind); + + LLVM_DEBUG(dbgs() << "Found a shuffle feeding two binops: " << I + << "\n OldCost: " << OldCost << " vs NewCost: " << NewCost + << "\n"); + if (NewCost >= OldCost) + return false; + + Value *Shuf0 = Builder.CreateShuffleVector(X, Z, NewMask0); + Value *Shuf1 = Builder.CreateShuffleVector(Y, W, NewMask1); Value *NewBO = Builder.CreateBinOp(Opcode, Shuf0, Shuf1); + // Intersect flags from the old binops. if (auto *NewInst = dyn_cast(NewBO)) { NewInst->copyIRFlags(B0); NewInst->andIRFlags(B1); } - // TODO: Add Shuf0/Shuf1 to WorkList? + Worklist.pushValue(Shuf0); + Worklist.pushValue(Shuf1); replaceValue(I, *NewBO); return true; } diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll index 8d5535e2a82f7d56a6b42828e5def1e6a9249df2..7ce3021b00935e38a06cf6037b8950c4eac89e3c 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll @@ -693,14 +693,14 @@ define void @get_lane_mask() #0 { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_nxv2i1_i32 = call @llvm.get.active.lane.mask.nxv2i1.i32(i32 undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %mask_nxv32i1_i64 = call @llvm.get.active.lane.mask.nxv32i1.i64(i64 undef, i64 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_nxv16i1_i16 = call @llvm.get.active.lane.mask.nxv16i1.i16(i16 undef, i16 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 144 for instruction: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 22 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void @@ -716,14 +716,14 @@ define void @get_lane_mask() #0 { ; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %mask_nxv2i1_i32 = call @llvm.get.active.lane.mask.nxv2i1.i32(i32 undef, i32 undef) ; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %mask_nxv32i1_i64 = call @llvm.get.active.lane.mask.nxv32i1.i64(i64 undef, i64 undef) ; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %mask_nxv16i1_i16 = call @llvm.get.active.lane.mask.nxv16i1.i16(i16 undef, i16 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %mask_v16i1_i64 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i64(i64 undef, i64 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_v8i1_i64 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 undef, i64 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_v4i1_i64 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 undef, i64 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i64 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 undef, i64 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %mask_v16i1_i32 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 undef, i32 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %mask_v8i1_i32 = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i32(i32 undef, i32 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %mask_v4i1_i32 = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i32(i32 undef, i32 undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %mask_v2i1_i32 = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i32(i32 undef, i32 undef) ; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %mask_v32i1_i64 = call <32 x i1> @llvm.get.active.lane.mask.v32i1.i64(i64 undef, i64 undef) ; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %mask_v16i1_i16 = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i16(i16 undef, i16 undef) ; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void diff --git a/llvm/test/Analysis/ValueTracking/known-non-zero.ll b/llvm/test/Analysis/ValueTracking/known-non-zero.ll index 0159050d925c3eec0d8fa803d9d84b7f4bfe04ca..c00e47fba8c72738c2631ce20bc1c994a9a987c2 100644 --- a/llvm/test/Analysis/ValueTracking/known-non-zero.ll +++ b/llvm/test/Analysis/ValueTracking/known-non-zero.ll @@ -1202,7 +1202,6 @@ define <2 x i1> @cmp_excludes_zero_with_nonsplat_vec_wpoison(<2 x i8> %a, <2 x i ret <2 x i1> %r } - define <2 x i1> @cmp_excludes_zero_with_nonsplat_vec_fail(<2 x i8> %a, <2 x i8> %b) { ; CHECK-LABEL: @cmp_excludes_zero_with_nonsplat_vec_fail( ; CHECK-NEXT: [[C:%.*]] = icmp sge <2 x i8> [[A:%.*]], @@ -1314,8 +1313,8 @@ define i1 @range_attr(i8 range(i8 1, 0) %x, i8 %y) { define i1 @neg_range_attr(i8 range(i8 -1, 1) %x, i8 %y) { ; CHECK-LABEL: @neg_range_attr( -; CHECK-NEXT: [[I:%.*]] = or i8 [[Y:%.*]], [[X:%.*]] -; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[I]], 0 +; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], [[X:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; %or = or i8 %y, %x @@ -1328,7 +1327,7 @@ declare range(i8 -1, 1) i8 @returns_contain_zero_range_helper() define i1 @range_return(i8 %y) { ; CHECK-LABEL: @range_return( -; CHECK-NEXT: [[I:%.*]] = call i8 @returns_non_zero_range_helper() +; CHECK-NEXT: [[X:%.*]] = call i8 @returns_non_zero_range_helper() ; CHECK-NEXT: ret i1 false ; %x = call i8 @returns_non_zero_range_helper() @@ -1339,8 +1338,8 @@ define i1 @range_return(i8 %y) { define i1 @neg_range_return(i8 %y) { ; CHECK-LABEL: @neg_range_return( -; CHECK-NEXT: [[I:%.*]] = call i8 @returns_contain_zero_range_helper() -; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], [[I]] +; CHECK-NEXT: [[X:%.*]] = call i8 @returns_contain_zero_range_helper() +; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], [[X]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1354,7 +1353,7 @@ declare i8 @returns_i8_helper() define i1 @range_call(i8 %y) { ; CHECK-LABEL: @range_call( -; CHECK-NEXT: [[I:%.*]] = call range(i8 1, 0) i8 @returns_i8_helper() +; CHECK-NEXT: [[X:%.*]] = call range(i8 1, 0) i8 @returns_i8_helper() ; CHECK-NEXT: ret i1 false ; %x = call range(i8 1, 0) i8 @returns_i8_helper() @@ -1365,8 +1364,8 @@ define i1 @range_call(i8 %y) { define i1 @neg_range_call(i8 %y) { ; CHECK-LABEL: @neg_range_call( -; CHECK-NEXT: [[I:%.*]] = call range(i8 -1, 1) i8 @returns_i8_helper() -; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], [[I]] +; CHECK-NEXT: [[X:%.*]] = call range(i8 -1, 1) i8 @returns_i8_helper() +; CHECK-NEXT: [[OR:%.*]] = or i8 [[Y:%.*]], [[X]] ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[OR]], 0 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1401,7 +1400,7 @@ declare range(i8 -1, 1) <2 x i8> @returns_contain_zero_range_helper_vec() define <2 x i1> @range_return_vec(<2 x i8> %y) { ; CHECK-LABEL: @range_return_vec( -; CHECK-NEXT: [[I:%.*]] = call <2 x i8> @returns_non_zero_range_helper_vec() +; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @returns_non_zero_range_helper_vec() ; CHECK-NEXT: ret <2 x i1> ; %x = call <2 x i8> @returns_non_zero_range_helper_vec() @@ -1412,8 +1411,8 @@ define <2 x i1> @range_return_vec(<2 x i8> %y) { define <2 x i1> @neg_range_return_vec(<2 x i8> %y) { ; CHECK-LABEL: @neg_range_return_vec( -; CHECK-NEXT: [[I:%.*]] = call <2 x i8> @returns_contain_zero_range_helper_vec() -; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[Y:%.*]], [[I]] +; CHECK-NEXT: [[X:%.*]] = call <2 x i8> @returns_contain_zero_range_helper_vec() +; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[Y:%.*]], [[X]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i8> [[OR]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1427,7 +1426,7 @@ declare <2 x i8> @returns_i8_helper_vec() define <2 x i1> @range_call_vec(<2 x i8> %y) { ; CHECK-LABEL: @range_call_vec( -; CHECK-NEXT: [[I:%.*]] = call range(i8 1, 0) <2 x i8> @returns_i8_helper_vec() +; CHECK-NEXT: [[X:%.*]] = call range(i8 1, 0) <2 x i8> @returns_i8_helper_vec() ; CHECK-NEXT: ret <2 x i1> ; %x = call range(i8 1, 0) <2 x i8> @returns_i8_helper_vec() @@ -1438,8 +1437,8 @@ define <2 x i1> @range_call_vec(<2 x i8> %y) { define <2 x i1> @neg_range_call_vec(<2 x i8> %y) { ; CHECK-LABEL: @neg_range_call_vec( -; CHECK-NEXT: [[I:%.*]] = call range(i8 -1, 1) <2 x i8> @returns_i8_helper_vec() -; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[Y:%.*]], [[I]] +; CHECK-NEXT: [[X:%.*]] = call range(i8 -1, 1) <2 x i8> @returns_i8_helper_vec() +; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[Y:%.*]], [[X]] ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i8> [[OR]], zeroinitializer ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -1449,5 +1448,53 @@ define <2 x i1> @neg_range_call_vec(<2 x i8> %y) { ret <2 x i1> %cmp } +define i1 @trunc_nsw_non_zero(i8 %x) { +; CHECK-LABEL: @trunc_nsw_non_zero( +; CHECK-NEXT: [[X_NE_Z:%.*]] = icmp ne i8 [[X:%.*]], 0 +; CHECK-NEXT: call void @llvm.assume(i1 [[X_NE_Z]]) +; CHECK-NEXT: ret i1 true +; + %x_ne_z = icmp ne i8 %x, 0 + call void @llvm.assume(i1 %x_ne_z) + %v = trunc nsw i8 %x to i4 + %r = icmp ne i4 %v, 0 + ret i1 %r +} + +define i1 @trunc_nuw_non_zero(i8 %xx) { +; CHECK-LABEL: @trunc_nuw_non_zero( +; CHECK-NEXT: ret i1 false +; + %x = add nuw i8 %xx, 1 + %v = trunc nuw i8 %x to i4 + %r = icmp eq i4 %v, 0 + ret i1 %r +} + +define i1 @trunc_non_zero_fail(i8 %x) { +; CHECK-LABEL: @trunc_non_zero_fail( +; CHECK-NEXT: [[X_NE_Z:%.*]] = icmp ne i8 [[X:%.*]], 0 +; CHECK-NEXT: call void @llvm.assume(i1 [[X_NE_Z]]) +; CHECK-NEXT: [[R:%.*]] = trunc i8 [[X]] to i1 +; CHECK-NEXT: ret i1 [[R]] +; + %x_ne_z = icmp ne i8 %x, 0 + call void @llvm.assume(i1 %x_ne_z) + %r = trunc i8 %x to i1 + ret i1 %r +} + +define i1 @trunc_nsw_nuw_non_zero_fail(i8 %xx) { +; CHECK-LABEL: @trunc_nsw_nuw_non_zero_fail( +; CHECK-NEXT: [[X:%.*]] = add nsw i8 [[XX:%.*]], 1 +; CHECK-NEXT: [[V:%.*]] = trunc nuw nsw i8 [[X]] to i4 +; CHECK-NEXT: [[R:%.*]] = icmp eq i4 [[V]], 0 +; CHECK-NEXT: ret i1 [[R]] +; + %x = add nsw i8 %xx, 1 + %v = trunc nsw nuw i8 %x to i4 + %r = icmp eq i4 %v, 0 + ret i1 %r +} declare i32 @llvm.experimental.get.vector.length.i32(i32, i32, i1) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll index 9a525151ca328b61815a32a5e0458be8248834b6..c97a00ccdd455719462ced3dfb0bd3d1a98d8133 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-udiv.ll @@ -243,3 +243,29 @@ define <8 x i16> @pr38477(<8 x i16> %a0) { %1 = udiv <8 x i16> %a0, ret <8 x i16> %1 } + +define i32 @udiv_div_by_180(i32 %x) +; SDAG-LABEL: udiv_div_by_180: +; SDAG: // %bb.0: +; SDAG-NEXT: mov w8, #5826 // =0x16c2 +; SDAG-NEXT: and w9, w0, #0xff +; SDAG-NEXT: movk w8, #364, lsl #16 +; SDAG-NEXT: umull x8, w9, w8 +; SDAG-NEXT: lsr x0, x8, #32 +; SDAG-NEXT: // kill: def $w0 killed $w0 killed $x0 +; SDAG-NEXT: ret +; +; GISEL-LABEL: udiv_div_by_180: +; GISEL: // %bb.0: +; GISEL-NEXT: uxtb w8, w0 +; GISEL-NEXT: mov w9, #5826 // =0x16c2 +; GISEL-NEXT: movk w9, #364, lsl #16 +; GISEL-NEXT: umull x8, w8, w9 +; GISEL-NEXT: lsr x0, x8, #32 +; GISEL-NEXT: // kill: def $w0 killed $w0 killed $x0 +; GISEL-NEXT: ret +{ + %truncate = and i32 %x, 255 + %udiv = udiv i32 %truncate, 180 + ret i32 %udiv +} diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll index 664d99a3627b58f41b43b796c648b17b36c6c551..5bef95910d9060b31a75180a7cfecec0cf5a452b 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll @@ -17,11 +17,11 @@ define %"class.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: mov z1.d, #0 // =0x0 ; CHECK-NEXT: cntd x9 ; CHECK-NEXT: ptrue p1.b -; CHECK-NEXT: neg x9, x9 -; CHECK-NEXT: mov w10, #100 // =0x64 +; CHECK-NEXT: neg x10, x9 +; CHECK-NEXT: mov w11, #100 // =0x64 ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: mov x8, xzr -; CHECK-NEXT: and x10, x9, x10 +; CHECK-NEXT: and x10, x10, x11 ; CHECK-NEXT: rdvl x11, #2 ; CHECK-NEXT: zip2 z0.d, z1.d, z1.d ; CHECK-NEXT: zip1 z1.d, z1.d, z1.d @@ -33,7 +33,7 @@ define %"class.std::complex" @complex_mul_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: ld1d { z3.d }, p0/z, [x12, #1, mul vl] ; CHECK-NEXT: ld1b { z4.b }, p1/z, [x1, x8] ; CHECK-NEXT: ld1d { z5.d }, p0/z, [x13, #1, mul vl] -; CHECK-NEXT: adds x10, x10, x9 +; CHECK-NEXT: subs x10, x10, x9 ; CHECK-NEXT: add x8, x8, x11 ; CHECK-NEXT: fcmla z1.d, p0/m, z4.d, z2.d, #0 ; CHECK-NEXT: fcmla z0.d, p0/m, z5.d, z3.d, #0 @@ -106,12 +106,12 @@ define %"class.std::complex" @complex_mul_nonzero_init_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: cntd x9 ; CHECK-NEXT: fmov d2, #2.00000000 ; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: neg x9, x9 +; CHECK-NEXT: neg x10, x9 ; CHECK-NEXT: ptrue p1.b -; CHECK-NEXT: mov w10, #100 // =0x64 +; CHECK-NEXT: mov w11, #100 // =0x64 ; CHECK-NEXT: mov x8, xzr ; CHECK-NEXT: sel z3.d, p0, z0.d, z1.d -; CHECK-NEXT: and x10, x9, x10 +; CHECK-NEXT: and x10, x10, x11 ; CHECK-NEXT: rdvl x11, #2 ; CHECK-NEXT: mov z1.d, p0/m, z2.d ; CHECK-NEXT: ptrue p0.d @@ -125,7 +125,7 @@ define %"class.std::complex" @complex_mul_nonzero_init_v2f64(ptr %a, ptr %b) { ; CHECK-NEXT: ld1d { z3.d }, p0/z, [x12, #1, mul vl] ; CHECK-NEXT: ld1b { z4.b }, p1/z, [x1, x8] ; CHECK-NEXT: ld1d { z5.d }, p0/z, [x13, #1, mul vl] -; CHECK-NEXT: adds x10, x10, x9 +; CHECK-NEXT: subs x10, x10, x9 ; CHECK-NEXT: add x8, x8, x11 ; CHECK-NEXT: fcmla z1.d, p0/m, z4.d, z2.d, #0 ; CHECK-NEXT: fcmla z0.d, p0/m, z5.d, z3.d, #0 @@ -191,13 +191,13 @@ define %"class.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) { ; CHECK: // %bb.0: // %entry ; CHECK-NEXT: mov z1.d, #0 // =0x0 ; CHECK-NEXT: cntw x9 -; CHECK-NEXT: mov w10, #1000 // =0x3e8 -; CHECK-NEXT: neg x9, x9 +; CHECK-NEXT: mov w11, #1000 // =0x3e8 +; CHECK-NEXT: neg x10, x9 ; CHECK-NEXT: rdvl x12, #2 ; CHECK-NEXT: ptrue p1.b ; CHECK-NEXT: ptrue p0.d ; CHECK-NEXT: mov x8, xzr -; CHECK-NEXT: and x10, x9, x10 +; CHECK-NEXT: and x10, x10, x11 ; CHECK-NEXT: zip2 z0.d, z1.d, z1.d ; CHECK-NEXT: zip1 z1.d, z1.d, z1.d ; CHECK-NEXT: add x11, x1, x12 @@ -219,7 +219,7 @@ define %"class.std::complex" @complex_mul_v2f64_unrolled(ptr %a, ptr %b) { ; CHECK-NEXT: ld1d { z17.d }, p0/z, [x15, #1, mul vl] ; CHECK-NEXT: ld1b { z18.b }, p1/z, [x11, x8] ; CHECK-NEXT: ld1d { z19.d }, p0/z, [x17, #1, mul vl] -; CHECK-NEXT: adds x10, x10, x9 +; CHECK-NEXT: subs x10, x10, x9 ; CHECK-NEXT: add x8, x8, x13 ; CHECK-NEXT: fcmla z1.d, p0/m, z7.d, z4.d, #0 ; CHECK-NEXT: fcmla z0.d, p0/m, z16.d, z5.d, #0 diff --git a/llvm/test/CodeGen/AArch64/concatbinop.ll b/llvm/test/CodeGen/AArch64/concatbinop.ll new file mode 100644 index 0000000000000000000000000000000000000000..a13e62e0612cc08a84e9a1de193f3e0a4ce1bb9f --- /dev/null +++ b/llvm/test/CodeGen/AArch64/concatbinop.ll @@ -0,0 +1,182 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=aarch64 -mattr=+fullfp16 -verify-machineinstrs -o - %s | FileCheck %s + + +define <8 x i16> @concat_add(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { +; CHECK-LABEL: concat_add: +; CHECK: // %bb.0: +; CHECK-NEXT: add v2.4h, v2.4h, v3.4h +; CHECK-NEXT: add v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = add <4 x i16> %a, %b + %y = add <4 x i16> %c, %d + %z = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> + ret <8 x i16> %z +} + +define <8 x i16> @concat_addtunc(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { +; CHECK-LABEL: concat_addtunc: +; CHECK: // %bb.0: +; CHECK-NEXT: add v2.4s, v2.4s, v3.4s +; CHECK-NEXT: add v0.4s, v0.4s, v1.4s +; CHECK-NEXT: uzp1 v0.8h, v0.8h, v2.8h +; CHECK-NEXT: ret + %x = add <4 x i32> %a, %b + %y = add <4 x i32> %c, %d + %xt = trunc <4 x i32> %x to <4 x i16> + %yt = trunc <4 x i32> %y to <4 x i16> + %z = shufflevector <4 x i16> %xt, <4 x i16> %yt, <8 x i32> + ret <8 x i16> %z +} + +define <8 x i16> @concat_addtunc2(<4 x i32> %a, <4 x i32> %b, <4 x i32> %c, <4 x i32> %d) { +; CHECK-LABEL: concat_addtunc2: +; CHECK: // %bb.0: +; CHECK-NEXT: xtn v1.4h, v1.4s +; CHECK-NEXT: xtn v0.4h, v0.4s +; CHECK-NEXT: xtn v2.4h, v2.4s +; CHECK-NEXT: xtn v3.4h, v3.4s +; CHECK-NEXT: add v0.4h, v0.4h, v1.4h +; CHECK-NEXT: add v1.4h, v2.4h, v3.4h +; CHECK-NEXT: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret + %at = trunc <4 x i32> %a to <4 x i16> + %bt = trunc <4 x i32> %b to <4 x i16> + %ct = trunc <4 x i32> %c to <4 x i16> + %dt = trunc <4 x i32> %d to <4 x i16> + %x = add <4 x i16> %at, %bt + %y = add <4 x i16> %ct, %dt + %z = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> + ret <8 x i16> %z +} + +define <8 x i16> @concat_sub(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { +; CHECK-LABEL: concat_sub: +; CHECK: // %bb.0: +; CHECK-NEXT: sub v2.4h, v2.4h, v3.4h +; CHECK-NEXT: sub v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = sub <4 x i16> %a, %b + %y = sub <4 x i16> %c, %d + %z = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> + ret <8 x i16> %z +} + +define <8 x i16> @concat_mul(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { +; CHECK-LABEL: concat_mul: +; CHECK: // %bb.0: +; CHECK-NEXT: mul v2.4h, v2.4h, v3.4h +; CHECK-NEXT: mul v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = mul <4 x i16> %a, %b + %y = mul <4 x i16> %c, %d + %z = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> + ret <8 x i16> %z +} + +define <8 x i16> @concat_xor(<4 x i16> %a, <4 x i16> %b, <4 x i16> %c, <4 x i16> %d) { +; CHECK-LABEL: concat_xor: +; CHECK: // %bb.0: +; CHECK-NEXT: eor v2.8b, v2.8b, v3.8b +; CHECK-NEXT: eor v0.8b, v0.8b, v1.8b +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = xor <4 x i16> %a, %b + %y = xor <4 x i16> %c, %d + %z = shufflevector <4 x i16> %x, <4 x i16> %y, <8 x i32> + ret <8 x i16> %z +} + +define <8 x half> @concat_fadd(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) { +; CHECK-LABEL: concat_fadd: +; CHECK: // %bb.0: +; CHECK-NEXT: fadd v2.4h, v2.4h, v3.4h +; CHECK-NEXT: fadd v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = fadd <4 x half> %a, %b + %y = fadd <4 x half> %c, %d + %z = shufflevector <4 x half> %x, <4 x half> %y, <8 x i32> + ret <8 x half> %z +} + +define <8 x half> @concat_fmul(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) { +; CHECK-LABEL: concat_fmul: +; CHECK: // %bb.0: +; CHECK-NEXT: fmul v2.4h, v2.4h, v3.4h +; CHECK-NEXT: fmul v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = fmul <4 x half> %a, %b + %y = fmul <4 x half> %c, %d + %z = shufflevector <4 x half> %x, <4 x half> %y, <8 x i32> + ret <8 x half> %z +} + +define <8 x half> @concat_min(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) { +; CHECK-LABEL: concat_min: +; CHECK: // %bb.0: +; CHECK-NEXT: fminnm v2.4h, v2.4h, v3.4h +; CHECK-NEXT: fminnm v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = call <4 x half> @llvm.minnum.v4f16(<4 x half> %a, <4 x half> %b) + %y = call <4 x half> @llvm.minnum.v4f16(<4 x half> %c, <4 x half> %d) + %z = shufflevector <4 x half> %x, <4 x half> %y, <8 x i32> + ret <8 x half> %z +} + +define <8 x half> @concat_minmax(<4 x half> %a, <4 x half> %b, <4 x half> %c, <4 x half> %d) { +; CHECK-LABEL: concat_minmax: +; CHECK: // %bb.0: +; CHECK-NEXT: fmaxnm v2.4h, v2.4h, v3.4h +; CHECK-NEXT: fminnm v0.4h, v0.4h, v1.4h +; CHECK-NEXT: mov v0.d[1], v2.d[0] +; CHECK-NEXT: ret + %x = call <4 x half> @llvm.minnum.v4f16(<4 x half> %a, <4 x half> %b) + %y = call <4 x half> @llvm.maxnum.v4f16(<4 x half> %c, <4 x half> %d) + %z = shufflevector <4 x half> %x, <4 x half> %y, <8 x i32> + ret <8 x half> %z +} + +define <16 x i8> @signOf_neon(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b) { +; CHECK-LABEL: signOf_neon: +; CHECK: // %bb.0: // %entry +; CHECK-NEXT: ldp q1, q2, [x0] +; CHECK-NEXT: movi v0.8b, #1 +; CHECK-NEXT: ldp q3, q4, [x1] +; CHECK-NEXT: cmhi v5.8h, v1.8h, v3.8h +; CHECK-NEXT: cmhi v6.8h, v2.8h, v4.8h +; CHECK-NEXT: cmhi v1.8h, v3.8h, v1.8h +; CHECK-NEXT: cmhi v2.8h, v4.8h, v2.8h +; CHECK-NEXT: xtn v3.8b, v5.8h +; CHECK-NEXT: xtn v4.8b, v6.8h +; CHECK-NEXT: xtn v1.8b, v1.8h +; CHECK-NEXT: xtn v2.8b, v2.8h +; CHECK-NEXT: and v3.8b, v3.8b, v0.8b +; CHECK-NEXT: and v4.8b, v4.8b, v0.8b +; CHECK-NEXT: orr v0.8b, v3.8b, v1.8b +; CHECK-NEXT: orr v1.8b, v4.8b, v2.8b +; CHECK-NEXT: mov v0.d[1], v1.d[0] +; CHECK-NEXT: ret +entry: + %0 = load <8 x i16>, ptr %a, align 2 + %add.ptr = getelementptr inbounds i8, ptr %a, i64 16 + %1 = load <8 x i16>, ptr %add.ptr, align 2 + %2 = load <8 x i16>, ptr %b, align 2 + %add.ptr6 = getelementptr inbounds i8, ptr %b, i64 16 + %3 = load <8 x i16>, ptr %add.ptr6, align 2 + %cmp.i33 = icmp ugt <8 x i16> %0, %2 + %cmp.i31 = icmp ugt <8 x i16> %1, %3 + %cmp.i29 = icmp ugt <8 x i16> %2, %0 + %cmp.i = icmp ugt <8 x i16> %3, %1 + %vmovn.i38.neg = zext <8 x i1> %cmp.i33 to <8 x i8> + %vmovn.i37.neg = zext <8 x i1> %cmp.i31 to <8 x i8> + %4 = select <8 x i1> %cmp.i29, <8 x i8> , <8 x i8> %vmovn.i38.neg + %5 = select <8 x i1> %cmp.i, <8 x i8> , <8 x i8> %vmovn.i37.neg + %or.i = shufflevector <8 x i8> %4, <8 x i8> %5, <16 x i32> + ret <16 x i8> %or.i +} diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll index dd72c2b2bd01094bc1e234093e7b37049563b73a..e3cc74f766ee0ecc763da69b1d97d5e0041c67fc 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-bitcast.ll @@ -60,11 +60,8 @@ define void @bitcast_v2i16(ptr %a, ptr %b) { ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #16 ; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: ldrh w8, [x0, #2] -; CHECK-NEXT: str w8, [sp, #4] -; CHECK-NEXT: ldrh w8, [x0] -; CHECK-NEXT: str w8, [sp] -; CHECK-NEXT: ldr d0, [sp] +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: mov z1.s, z0.s[1] ; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: strh w8, [sp, #8] diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll index 1b9bb42c8582e1d1e8a43c62e910533a4ac7b7d7..a752e119b2fb2ace8f20cef7cd9637dfd01a639b 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-extract-vector-elt.ll @@ -90,8 +90,6 @@ define float @extractelement_v8f32(ptr %a) { define double @extractelement_v1f64(<1 x double> %op1) { ; CHECK-LABEL: extractelement_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %r = extractelement <1 x double> %op1, i64 0 ret double %r diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll index e92694d1fc80d2eb759032eb0196a703c945b6d5..465cc179a3b989a80ddd783a47bb346fd6869bb4 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-compares.ll @@ -127,11 +127,9 @@ define void @fcmp_oeq_v8f32(ptr %a, ptr %b, ptr %c) { define <1 x i64> @fcmp_oeq_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: fcmp_oeq_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: ptrue p0.d, vl1 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: fcmeq p0.d, p0/z, z0.d, z1.d -; CHECK-NEXT: mov z0.d, p0/z, #-1 // =0xffffffffffffffff +; CHECK-NEXT: fcmp d0, d1 +; CHECK-NEXT: csetm x8, eq +; CHECK-NEXT: mov z0.d, x8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %cmp = fcmp oeq <1 x double> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll index 478be9ab76dd9fb32b8f8c03eae6de4f15ea3693..cbe71d715a8fb96e2a2093fd08367a7dd025b655 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-fma.ll @@ -112,9 +112,6 @@ define void @fma_v8f32(ptr %a, ptr %b, ptr %c) { define <1 x double> @fma_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x double> %op3) { ; CHECK-LABEL: fma_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d2 killed $d2 def $z2 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fmadd d0, d0, d1, d2 ; CHECK-NEXT: ret %mul = fmul contract <1 x double> %op1, %op2 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll index 4dc034adf459ae2b191bde3885dc5b8fcf348de9..94a74763aa0e9ff3710b0c0366ed87cef453f51e 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-minmax.ll @@ -99,8 +99,6 @@ define void @fmaxnm_v8f32(ptr %a, ptr %b) { define <1 x double> @fmaxnm_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: fmaxnm_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fmaxnm d0, d0, d1 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.maxnum.v1f64(<1 x double> %op1, <1 x double> %op2) @@ -233,8 +231,6 @@ define void @fminnm_v8f32(ptr %a, ptr %b) { define <1 x double> @fminnm_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: fminnm_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fminnm d0, d0, d1 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.minnum.v1f64(<1 x double> %op1, <1 x double> %op2) @@ -367,8 +363,6 @@ define void @fmax_v8f32(ptr %a, ptr %b) { define <1 x double> @fmax_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: fmax_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fmax d0, d0, d1 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.maximum.v1f64(<1 x double> %op1, <1 x double> %op2) @@ -501,8 +495,6 @@ define void @fmin_v8f32(ptr %a, ptr %b) { define <1 x double> @fmin_v1f64(<1 x double> %op1, <1 x double> %op2) { ; CHECK-LABEL: fmin_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fmin d0, d0, d1 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.minimum.v1f64(<1 x double> %op1, <1 x double> %op2) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll index bd10a0e091c0d4008be637b791095c9f99fddb88..df9613a30e40b0dacc9e3b66eddfb01165198e15 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-reduce.ll @@ -144,7 +144,6 @@ define float @fadda_v8f32(float %start, ptr %a) { define double @fadda_v1f64(double %start, <1 x double> %a) { ; CHECK-LABEL: fadda_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret %res = call double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a) @@ -263,7 +262,6 @@ define float @faddv_v8f32(float %start, ptr %a) { define double @faddv_v1f64(double %start, <1 x double> %a) { ; CHECK-LABEL: faddv_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 ; CHECK-NEXT: fadd d0, d0, d1 ; CHECK-NEXT: ret %res = call fast double @llvm.vector.reduce.fadd.v1f64(double %start, <1 x double> %a) @@ -379,8 +377,6 @@ define float @fmaxv_v8f32(ptr %a) { define double @fmaxv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fmaxv_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %res = call double @llvm.vector.reduce.fmax.v1f64(<1 x double> %a) ret double %res @@ -495,8 +491,6 @@ define float @fminv_v8f32(ptr %a) { define double @fminv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fminv_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %res = call double @llvm.vector.reduce.fmin.v1f64(<1 x double> %a) ret double %res @@ -611,8 +605,6 @@ define float @fmaximumv_v8f32(ptr %a) { define double @fmaximumv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fmaximumv_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %res = call double @llvm.vector.reduce.fmaximum.v1f64(<1 x double> %a) ret double %res @@ -727,8 +719,6 @@ define float @fminimumv_v8f32(ptr %a) { define double @fminimumv_v1f64(<1 x double> %a) { ; CHECK-LABEL: fminimumv_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %res = call double @llvm.vector.reduce.fminimum.v1f64(<1 x double> %a) ret double %res diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll index 24832d807c649c00fe301f72b5b4e19aeacd1381..7ddc641f366caaf3905ae6774dd606a6b9c8ce52 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-rounding.ll @@ -101,7 +101,6 @@ define void @frintp_v8f32(ptr %a) { define <1 x double> @frintp_v1f64(<1 x double> %op) { ; CHECK-LABEL: frintp_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frintp d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.ceil.v1f64(<1 x double> %op) @@ -232,7 +231,6 @@ define void @frintm_v8f32(ptr %a) { define <1 x double> @frintm_v1f64(<1 x double> %op) { ; CHECK-LABEL: frintm_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frintm d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.floor.v1f64(<1 x double> %op) @@ -363,7 +361,6 @@ define void @frinti_v8f32(ptr %a) { define <1 x double> @frinti_v1f64(<1 x double> %op) { ; CHECK-LABEL: frinti_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frinti d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.nearbyint.v1f64(<1 x double> %op) @@ -494,7 +491,6 @@ define void @frintx_v8f32(ptr %a) { define <1 x double> @frintx_v1f64(<1 x double> %op) { ; CHECK-LABEL: frintx_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frintx d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.rint.v1f64(<1 x double> %op) @@ -625,7 +621,6 @@ define void @frinta_v8f32(ptr %a) { define <1 x double> @frinta_v1f64(<1 x double> %op) { ; CHECK-LABEL: frinta_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frinta d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.round.v1f64(<1 x double> %op) @@ -756,7 +751,6 @@ define void @frintn_v8f32(ptr %a) { define <1 x double> @frintn_v1f64(<1 x double> %op) { ; CHECK-LABEL: frintn_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frintn d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.roundeven.v1f64(<1 x double> %op) @@ -887,7 +881,6 @@ define void @frintz_v8f32(ptr %a) { define <1 x double> @frintz_v1f64(<1 x double> %op) { ; CHECK-LABEL: frintz_v1f64: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: frintz d0, d0 ; CHECK-NEXT: ret %res = call <1 x double> @llvm.trunc.v1f64(<1 x double> %op) diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll index 132225546fc4fea3ad248971340a6bda99e15672..7d36925fdc57f3ef71b3eee1af2ad2dca01aed9c 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-select.ll @@ -132,16 +132,7 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, i1 %mask ; CHECK-LABEL: select_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: tst w0, #0x1 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: csetm x8, ne -; CHECK-NEXT: mvn x9, x8 -; CHECK-NEXT: mov z2.d, x8 -; CHECK-NEXT: mov z3.d, x9 -; CHECK-NEXT: and z0.d, z0.d, z2.d -; CHECK-NEXT: and z1.d, z1.d, z3.d -; CHECK-NEXT: orr z0.d, z0.d, z1.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: fcsel d0, d0, d1, ne ; CHECK-NEXT: ret %sel = select i1 %mask, <1 x double> %op1, <1 x double> %op2 ret <1 x double> %sel diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll index 58eae212d7999b78dd5c22fe650fe575da360ca0..bf8a335a8503794455530f56dbb2441feb801cf7 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-to-int.ll @@ -464,7 +464,6 @@ define void @fcvtzu_v8f32_v8i64(ptr %a, ptr %b) { define <1 x i16> @fcvtzu_v1f64_v1i16(<1 x double> %op1) { ; CHECK-LABEL: fcvtzu_v1f64_v1i16: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: fcvtzs w8, d0 ; CHECK-NEXT: mov z0.h, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 @@ -1215,7 +1214,6 @@ define void @fcvtzs_v8f32_v8i64(ptr %a, ptr %b) { define <1 x i16> @fcvtzs_v1f64_v1i16(<1 x double> %op1) { ; CHECK-LABEL: fcvtzs_v1f64_v1i16: ; CHECK: // %bb.0: -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 ; CHECK-NEXT: fcvtzs w8, d0 ; CHECK-NEXT: mov z0.h, w8 ; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll index 4c5a6fe2fd23158f4b9c97366ab0df161c60e211..30a4f04a3d2bd62378a7dba57e6c940dfbfb9529 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-fp-vselect.ll @@ -149,16 +149,7 @@ define <1 x double> @select_v1f64(<1 x double> %op1, <1 x double> %op2, <1 x i1> ; CHECK-LABEL: select_v1f64: ; CHECK: // %bb.0: ; CHECK-NEXT: tst w0, #0x1 -; CHECK-NEXT: // kill: def $d1 killed $d1 def $z1 -; CHECK-NEXT: // kill: def $d0 killed $d0 def $z0 -; CHECK-NEXT: csetm x8, ne -; CHECK-NEXT: mvn x9, x8 -; CHECK-NEXT: mov z2.d, x8 -; CHECK-NEXT: mov z3.d, x9 -; CHECK-NEXT: and z0.d, z0.d, z2.d -; CHECK-NEXT: and z1.d, z1.d, z3.d -; CHECK-NEXT: orr z0.d, z0.d, z1.d -; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 +; CHECK-NEXT: fcsel d0, d0, d1, ne ; CHECK-NEXT: ret %sel = select <1 x i1> %mask, <1 x double> %op1, <1 x double> %op2 ret <1 x double> %sel diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll index 1fc51d50b50ae0c02641ace331d14095d8b3e916..efe9066f2c835fec28d4fd768229858d079d7253 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-ld2-alloca.ll @@ -47,6 +47,7 @@ define void @alloc_v6i8(ptr %st_ptr) nounwind { ; CHECK-NEXT: add x20, sp, #24 ; CHECK-NEXT: bl def ; CHECK-NEXT: ptrue p0.b, vl3 +; CHECK-NEXT: ptrue p1.s, vl2 ; CHECK-NEXT: ld2b { z0.b, z1.b }, p0/z, [x20] ; CHECK-NEXT: ptrue p0.h, vl4 ; CHECK-NEXT: mov z2.b, z1.b[3] @@ -63,9 +64,10 @@ define void @alloc_v6i8(ptr %st_ptr) nounwind { ; CHECK-NEXT: add x8, sp, #12 ; CHECK-NEXT: ldr d0, [sp] ; CHECK-NEXT: st1b { z0.h }, p0, [x8] -; CHECK-NEXT: ldrh w8, [sp, #12] +; CHECK-NEXT: ld1h { z0.s }, p1/z, [x8] ; CHECK-NEXT: strb w9, [x19, #2] ; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Folded Reload +; CHECK-NEXT: fmov w8, s0 ; CHECK-NEXT: strh w8, [x19] ; CHECK-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload ; CHECK-NEXT: add sp, sp, #48 diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll index 688c39b89c0df0ebf09d9a1a985a5025d58a06a9..8ca8e6980913590c12a2a449fa2002dece21dd33 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-loads.ll @@ -45,14 +45,9 @@ define <32 x i8> @load_v32i8(ptr %a) { define <2 x i16> @load_v2i16(ptr %a) { ; CHECK-LABEL: load_v2i16: ; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: ldrh w8, [x0, #2] -; CHECK-NEXT: str w8, [sp, #12] -; CHECK-NEXT: ldrh w8, [x0] -; CHECK-NEXT: str w8, [sp, #8] -; CHECK-NEXT: ldr d0, [sp, #8] -; CHECK-NEXT: add sp, sp, #16 +; CHECK-NEXT: ptrue p0.s, vl2 +; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] +; CHECK-NEXT: // kill: def $d0 killed $d0 killed $z0 ; CHECK-NEXT: ret %load = load <2 x i16>, ptr %a ret <2 x i16> %load diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll index 6fcb95f2833388babe907ccc0326c3655afc46ab..b5adea594242981f948d1cf14d0accd39bf4df95 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-optimize-ptrue.ll @@ -70,21 +70,11 @@ define void @add_v32i8(ptr %a, ptr %b) { define void @add_v2i16(ptr %a, ptr %b, ptr %c) { ; CHECK-LABEL: add_v2i16: ; CHECK: // %bb.0: -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: ldrh w8, [x0, #2] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: str w8, [sp, #4] -; CHECK-NEXT: ldrh w8, [x0] -; CHECK-NEXT: str w8, [sp] -; CHECK-NEXT: ldrh w8, [x1, #2] -; CHECK-NEXT: str w8, [sp, #12] -; CHECK-NEXT: ldrh w8, [x1] -; CHECK-NEXT: str w8, [sp, #8] -; CHECK-NEXT: ldp d0, d1, [sp] +; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] +; CHECK-NEXT: ld1h { z1.s }, p0/z, [x1] ; CHECK-NEXT: add z0.s, z0.s, z1.s ; CHECK-NEXT: st1h { z0.s }, p0, [x0] -; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret %op1 = load <2 x i16>, ptr %a %op2 = load <2 x i16>, ptr %b diff --git a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll index 75bae88fc4798ea78a84fdcbbaec17db72783db6..838db0ce8185cfeb324fd49cf99c17aba38a64f9 100644 --- a/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll +++ b/llvm/test/CodeGen/AArch64/sve-streaming-mode-fixed-length-subvector.ll @@ -77,16 +77,9 @@ bb1: define void @subvector_v2i16(ptr %in, ptr %out) { ; CHECK-LABEL: subvector_v2i16: ; CHECK: // %bb.0: // %bb1 -; CHECK-NEXT: sub sp, sp, #16 -; CHECK-NEXT: .cfi_def_cfa_offset 16 -; CHECK-NEXT: ldrh w8, [x0, #2] ; CHECK-NEXT: ptrue p0.s, vl2 -; CHECK-NEXT: str w8, [sp, #12] -; CHECK-NEXT: ldrh w8, [x0] -; CHECK-NEXT: str w8, [sp, #8] -; CHECK-NEXT: ldr d0, [sp, #8] +; CHECK-NEXT: ld1h { z0.s }, p0/z, [x0] ; CHECK-NEXT: st1h { z0.s }, p0, [x1] -; CHECK-NEXT: add sp, sp, #16 ; CHECK-NEXT: ret %a = load <2 x i16>, ptr %in br label %bb1 diff --git a/llvm/test/CodeGen/AArch64/sve-vl-arith.ll b/llvm/test/CodeGen/AArch64/sve-vl-arith.ll index dd4294c8d3bdcc2dd69d685426316d0c8b79e732..de2af590acd1e26ca21ec58b67b7e9969f24efd9 100644 --- a/llvm/test/CodeGen/AArch64/sve-vl-arith.ll +++ b/llvm/test/CodeGen/AArch64/sve-vl-arith.ll @@ -186,8 +186,8 @@ define i64 @incd_scalar_i64(i64 %a) { define i64 @decb_scalar_i64(i64 %a) { ; NO_SCALAR_INC-LABEL: decb_scalar_i64: ; NO_SCALAR_INC: // %bb.0: -; NO_SCALAR_INC-NEXT: rdvl x8, #-2 -; NO_SCALAR_INC-NEXT: add x0, x0, x8 +; NO_SCALAR_INC-NEXT: cnth x8, all, mul #4 +; NO_SCALAR_INC-NEXT: sub x0, x0, x8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: decb_scalar_i64: @@ -204,8 +204,7 @@ define i64 @dech_scalar_i64(i64 %a) { ; NO_SCALAR_INC-LABEL: dech_scalar_i64: ; NO_SCALAR_INC: // %bb.0: ; NO_SCALAR_INC-NEXT: cnth x8, all, mul #3 -; NO_SCALAR_INC-NEXT: neg x8, x8 -; NO_SCALAR_INC-NEXT: add x0, x0, x8 +; NO_SCALAR_INC-NEXT: sub x0, x0, x8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: dech_scalar_i64: @@ -222,8 +221,7 @@ define i64 @decw_scalar_i64(i64 %a) { ; NO_SCALAR_INC-LABEL: decw_scalar_i64: ; NO_SCALAR_INC: // %bb.0: ; NO_SCALAR_INC-NEXT: cntw x8, all, mul #3 -; NO_SCALAR_INC-NEXT: neg x8, x8 -; NO_SCALAR_INC-NEXT: add x0, x0, x8 +; NO_SCALAR_INC-NEXT: sub x0, x0, x8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: decw_scalar_i64: @@ -240,8 +238,7 @@ define i64 @decd_scalar_i64(i64 %a) { ; NO_SCALAR_INC-LABEL: decd_scalar_i64: ; NO_SCALAR_INC: // %bb.0: ; NO_SCALAR_INC-NEXT: cntd x8, all, mul #3 -; NO_SCALAR_INC-NEXT: neg x8, x8 -; NO_SCALAR_INC-NEXT: add x0, x0, x8 +; NO_SCALAR_INC-NEXT: sub x0, x0, x8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: decd_scalar_i64: @@ -345,8 +342,8 @@ define i32 @incd_scalar_i32(i32 %a) { define i32 @decb_scalar_i32(i32 %a) { ; NO_SCALAR_INC-LABEL: decb_scalar_i32: ; NO_SCALAR_INC: // %bb.0: -; NO_SCALAR_INC-NEXT: rdvl x8, #-4 -; NO_SCALAR_INC-NEXT: add w0, w0, w8 +; NO_SCALAR_INC-NEXT: cnth x8, all, mul #8 +; NO_SCALAR_INC-NEXT: sub w0, w0, w8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: decb_scalar_i32: @@ -367,8 +364,7 @@ define i32 @dech_scalar_i32(i32 %a) { ; NO_SCALAR_INC-LABEL: dech_scalar_i32: ; NO_SCALAR_INC: // %bb.0: ; NO_SCALAR_INC-NEXT: cnth x8 -; NO_SCALAR_INC-NEXT: neg x8, x8 -; NO_SCALAR_INC-NEXT: add w0, w0, w8 +; NO_SCALAR_INC-NEXT: sub w0, w0, w8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: dech_scalar_i32: @@ -389,8 +385,7 @@ define i32 @decw_scalar_i32(i32 %a) { ; NO_SCALAR_INC-LABEL: decw_scalar_i32: ; NO_SCALAR_INC: // %bb.0: ; NO_SCALAR_INC-NEXT: cntw x8 -; NO_SCALAR_INC-NEXT: neg x8, x8 -; NO_SCALAR_INC-NEXT: add w0, w0, w8 +; NO_SCALAR_INC-NEXT: sub w0, w0, w8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: decw_scalar_i32: @@ -411,8 +406,7 @@ define i32 @decd_scalar_i32(i32 %a) { ; NO_SCALAR_INC-LABEL: decd_scalar_i32: ; NO_SCALAR_INC: // %bb.0: ; NO_SCALAR_INC-NEXT: cntd x8 -; NO_SCALAR_INC-NEXT: neg x8, x8 -; NO_SCALAR_INC-NEXT: add w0, w0, w8 +; NO_SCALAR_INC-NEXT: sub w0, w0, w8 ; NO_SCALAR_INC-NEXT: ret ; ; CHECK-LABEL: decd_scalar_i32: diff --git a/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll b/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll index dbdab799c83522fb39d41b31dd7e27f8e756b172..9572778484f8d388f222716b04fc097d54362042 100644 --- a/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll +++ b/llvm/test/CodeGen/AArch64/vscale-and-sve-cnt-demandedbits.ll @@ -194,7 +194,7 @@ define i32 @vscale_with_multiplier() vscale_range(1,16) { ; CHECK-LABEL: vscale_with_multiplier: ; CHECK: // %bb.0: ; CHECK-NEXT: rdvl x8, #1 -; CHECK-NEXT: mov w9, #5 +; CHECK-NEXT: mov w9, #5 // =0x5 ; CHECK-NEXT: lsr x8, x8, #4 ; CHECK-NEXT: mul x8, x8, x9 ; CHECK-NEXT: and w9, w8, #0x3f @@ -212,7 +212,7 @@ define i32 @vscale_with_negative_multiplier() vscale_range(1,16) { ; CHECK-LABEL: vscale_with_negative_multiplier: ; CHECK: // %bb.0: ; CHECK-NEXT: rdvl x8, #1 -; CHECK-NEXT: mov x9, #-5 +; CHECK-NEXT: mov x9, #-5 // =0xfffffffffffffffb ; CHECK-NEXT: lsr x8, x8, #4 ; CHECK-NEXT: mul x8, x8, x9 ; CHECK-NEXT: and w9, w8, #0xffffffc0 @@ -230,9 +230,9 @@ define i32 @pow2_vscale_with_negative_multiplier() vscale_range(1,16) { ; CHECK-LABEL: pow2_vscale_with_negative_multiplier: ; CHECK: // %bb.0: ; CHECK-NEXT: cntd x8 -; CHECK-NEXT: neg x8, x8 -; CHECK-NEXT: orr w9, w8, #0xfffffff0 -; CHECK-NEXT: add w0, w8, w9 +; CHECK-NEXT: neg x9, x8 +; CHECK-NEXT: orr w9, w9, #0xfffffff0 +; CHECK-NEXT: sub w0, w9, w8 ; CHECK-NEXT: ret %vscale = call i32 @llvm.vscale.i32() %mul = mul i32 %vscale, -2 diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir new file mode 100644 index 0000000000000000000000000000000000000000..ac98dca00be3df7154e1e4d49261f1d475313d45 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-trap-gfx11.mir @@ -0,0 +1,49 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -o - -run-pass=legalizer %s | FileCheck -check-prefix=GFX1100 %s +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx11-generic --amdhsa-code-object-version=6 -o - -run-pass=legalizer %s | FileCheck -check-prefix=GFX1100 %s +# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1150 -o - -run-pass=legalizer %s | FileCheck -check-prefix=GFX1150 %s + +--- +name: test_trap +body: | + bb.0: + ; GFX1100-LABEL: name: test_trap + ; GFX1100: successors: %bb.2(0x80000000) + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX1100-NEXT: [[C1:%[0-9]+]]:_(p1) = G_CONSTANT i64 0 + ; GFX1100-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1) + ; GFX1100-NEXT: S_TRAP 2 + ; GFX1100-NEXT: [[S_SENDMSG_RTN_B32_:%[0-9]+]]:sreg_32 = S_SENDMSG_RTN_B32 128 + ; GFX1100-NEXT: $ttmp2 = S_MOV_B32 $m0 + ; GFX1100-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_SENDMSG_RTN_B32_]], 1023, implicit-def $scc + ; GFX1100-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_AND_B32_]], 1024, implicit-def $scc + ; GFX1100-NEXT: $m0 = S_MOV_B32 [[S_OR_B32_]] + ; GFX1100-NEXT: S_SENDMSG 1, implicit $exec, implicit $m0 + ; GFX1100-NEXT: $m0 = S_MOV_B32 $ttmp2 + ; GFX1100-NEXT: S_BRANCH %bb.2 + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: .1: + ; GFX1100-NEXT: successors: + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1) + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: .2: + ; GFX1100-NEXT: successors: %bb.2(0x80000000) + ; GFX1100-NEXT: {{ $}} + ; GFX1100-NEXT: S_SETHALT 5 + ; GFX1100-NEXT: S_BRANCH %bb.2 + ; + ; GFX1150-LABEL: name: test_trap + ; GFX1150: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 + ; GFX1150-NEXT: [[C1:%[0-9]+]]:_(p1) = G_CONSTANT i64 0 + ; GFX1150-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1) + ; GFX1150-NEXT: S_TRAP 2 + ; GFX1150-NEXT: G_STORE [[C]](s32), [[C1]](p1) :: (store (s8), addrspace 1) + %0:_(s8) = G_CONSTANT i8 0 + %1:_(p1) = G_CONSTANT i64 0 + G_STORE %0, %1 :: (store 1, addrspace 1) + G_TRAP + G_STORE %0, %1 :: (store 1, addrspace 1) + +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll new file mode 100644 index 0000000000000000000000000000000000000000..71a2d3e8a5304f70c7b3d0c2bd41fa2490b954a6 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/mmra.ll @@ -0,0 +1,34 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -global-isel -march=amdgcn -mcpu=gfx900 -stop-after=finalize-isel < %s | FileCheck %s + +declare void @readsMem(ptr) #0 +declare void @writesMem(ptr) #1 + +define void @fence_loads(ptr %ptr) { + ; CHECK-LABEL: name: fence_loads + ; CHECK: bb.1 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1 + ; CHECK-NEXT: ATOMIC_FENCE 5, 1, mmra !0 + ; CHECK-NEXT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[REG_SEQUENCE]], 0, 0, implicit $exec, implicit $flat_scr, mmra !1 :: (load acquire (s8) from %ir.ptr, align 4) + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]] + ; CHECK-NEXT: FLAT_STORE_BYTE [[REG_SEQUENCE]], [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr, mmra !2 :: (store release (s8) into %ir.ptr, align 4) + ; CHECK-NEXT: SI_RETURN + fence release, !mmra !0 + %ld = load atomic i8, ptr %ptr acquire, align 4, !mmra !2 + store atomic i8 1, ptr %ptr release, align 4, !mmra !1 + ret void +} + +; TODO: test atomicrmw, cmpxchg - current lowering doesn't work and blows up on i1 PHIs. + +attributes #0 = { memory(read) } +attributes #1 = { memory(write) } + +!0 = !{!"foo", !"bar"} +!1 = !{!"bux", !"baz"} +!2 = !{!0, !1} diff --git a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll index 4d36fb3143510b6f5d251c5ea8fe089fa9850040..b8c8d993d389bdc9747348595f666ba4e21e8c4f 100644 --- a/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll +++ b/llvm/test/CodeGen/AMDGPU/flat_atomics_i64.ll @@ -3641,7 +3641,7 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr %out, double %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_wait_storecnt_dscnt 0x0 -; GFX12-NEXT: global_inv scope:SCOPE_SYS +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr double, ptr %out, i64 4 @@ -3688,7 +3688,7 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr %out, ptr %in) { ; GFX12-NEXT: v_dual_mov_b32 v2, s2 :: v_dual_mov_b32 v3, s3 ; GFX12-NEXT: flat_atomic_swap_b64 v[0:1], v[2:3] offset:32 ; GFX12-NEXT: s_wait_storecnt_dscnt 0x0 -; GFX12-NEXT: global_inv scope:SCOPE_SYS +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr ptr, ptr %out, i32 4 diff --git a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll index 08b068f3588c38b63f4b255a4ecc677d5ab58ecf..f5dbaaff9cf882daa18a79d0cb545498da242e34 100644 --- a/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll +++ b/llvm/test/CodeGen/AMDGPU/global_atomics_i64.ll @@ -4570,7 +4570,7 @@ define amdgpu_kernel void @atomic_xchg_f64_offset(ptr addrspace(1) %out, double ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_inv scope:SCOPE_SYS +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr double, ptr addrspace(1) %out, i64 4 @@ -4625,7 +4625,7 @@ define amdgpu_kernel void @atomic_xchg_pointer_offset(ptr addrspace(1) %out, ptr ; GFX12-NEXT: v_mov_b32_e32 v0, s2 ; GFX12-NEXT: global_atomic_swap_b64 v2, v[0:1], s[0:1] offset:32 ; GFX12-NEXT: s_wait_storecnt 0x0 -; GFX12-NEXT: global_inv scope:SCOPE_SYS +; GFX12-NEXT: global_inv scope:SCOPE_DEV ; GFX12-NEXT: s_endpgm entry: %gep = getelementptr ptr, ptr addrspace(1) %out, i64 4 diff --git a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll index a113c07b3e2bea508e4aa7d6d1cf4e7b9f5c2349..b8c16d2ed3b2f1ffa86186464aae5f05b070fd31 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.fptrunc.round.ll @@ -1,52 +1,453 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=CHECK,SDAG %s +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=CHECK,SDAG %s +; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck -check-prefixes=CHECK,GISEL %s -define amdgpu_gs void @test_fptrunc_round_upward(float %a, i32 %data0, <4 x i32> %data1, ptr addrspace(1) %out) { -; CHECK-LABEL: test_fptrunc_round_upward: +define amdgpu_gs half @v_fptrunc_round_f32_to_f16_upward(float %a) { +; CHECK-LABEL: v_fptrunc_round_f32_to_f16_upward: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 ; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 -; CHECK-NEXT: global_store_short v[6:7], v0, off -; CHECK-NEXT: s_endpgm - %res = call half @llvm.fptrunc.round(float %a, metadata !"round.upward") - store half %res, ptr addrspace(1) %out, align 4 - ret void +; CHECK-NEXT: ; return to shader part epilog + %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward") + ret half %res } -define amdgpu_gs void @test_fptrunc_round_downward(float %a, i32 %data0, <4 x i32> %data1, ptr addrspace(1) %out) { -; CHECK-LABEL: test_fptrunc_round_downward: +define amdgpu_gs half @v_fptrunc_round_f32_to_f16_downward(float %a) { +; CHECK-LABEL: v_fptrunc_round_f32_to_f16_downward: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 ; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 -; CHECK-NEXT: global_store_short v[6:7], v0, off -; CHECK-NEXT: s_endpgm - %res = call half @llvm.fptrunc.round(float %a, metadata !"round.downward") - store half %res, ptr addrspace(1) %out, align 4 - ret void +; CHECK-NEXT: ; return to shader part epilog + %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.downward") + ret half %res } -define amdgpu_gs void @test_fptrunc_round_upward_multiple_calls(float %a, float %b, i32 %data0, <4 x i32> %data1, ptr addrspace(1) %out) { -; CHECK-LABEL: test_fptrunc_round_upward_multiple_calls: +define amdgpu_gs void @v_fptrunc_round_f32_to_f16_upward_multiple_calls(float %a, float %b, ptr addrspace(1) %out) { +; CHECK-LABEL: v_fptrunc_round_f32_to_f16_upward_multiple_calls: ; CHECK: ; %bb.0: ; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 ; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 -; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v1 ; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2 ; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1 ; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0 -; CHECK-NEXT: v_add_f16_e32 v0, v0, v2 +; CHECK-NEXT: v_add_f16_e32 v0, v0, v4 ; CHECK-NEXT: v_add_f16_e32 v0, v1, v0 -; CHECK-NEXT: global_store_short v[7:8], v0, off +; CHECK-NEXT: global_store_short v[2:3], v0, off +; CHECK-NEXT: s_endpgm + %res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward") + %res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward") + %res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward") + %res4 = fadd half %res1, %res2 + %res5 = fadd half %res3, %res4 + store half %res5, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_upward(float inreg %a, ptr addrspace(1) %out) { +; CHECK-LABEL: s_fptrunc_round_f32_to_f16_upward: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v0, s0 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward") + %bitcast = bitcast half %res to i16 + %ret = zext i16 %bitcast to i32 + ret i32 %ret +} + +define amdgpu_gs i32 @s_fptrunc_round_f32_to_f16_downward(float inreg %a, ptr addrspace(1) %out) { +; CHECK-LABEL: s_fptrunc_round_f32_to_f16_downward: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v0, s0 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: ; return to shader part epilog + %res = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.downward") + %bitcast = bitcast half %res to i16 + %ret = zext i16 %bitcast to i32 + ret i32 %ret +} + +define amdgpu_gs void @s_fptrunc_round_f32_to_f16_upward_multiple_calls(float inreg %a, float inreg %b, ptr addrspace(1) %out) { +; CHECK-LABEL: s_fptrunc_round_f32_to_f16_upward_multiple_calls: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: v_mov_b32_e32 v3, s1 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v2 +; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v3 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2 +; CHECK-NEXT: v_cvt_f16_f32_e32 v3, v3 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0 +; CHECK-NEXT: v_add_f16_e32 v2, v2, v4 +; CHECK-NEXT: v_add_f16_e32 v2, v3, v2 +; CHECK-NEXT: global_store_short v[0:1], v2, off ; CHECK-NEXT: s_endpgm - %res1 = call half @llvm.fptrunc.round(float %a, metadata !"round.upward") - %res2 = call half @llvm.fptrunc.round(float %b, metadata !"round.upward") - %res3 = call half @llvm.fptrunc.round(float %b, metadata !"round.downward") + %res1 = call half @llvm.fptrunc.round.f16.f32(float %a, metadata !"round.upward") + %res2 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.upward") + %res3 = call half @llvm.fptrunc.round.f16.f32(float %b, metadata !"round.downward") %res4 = fadd half %res1, %res2 %res5 = fadd half %res3, %res4 store half %res5, ptr addrspace(1) %out, align 4 ret void } -declare half @llvm.fptrunc.round(float, metadata) +define amdgpu_gs <2 x half> @v_fptrunc_round_v2f32_to_v2f16_upward(<2 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: ; return to shader part epilog + %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward") + ret <2 x half> %res +} + +define amdgpu_gs <2 x half> @v_fptrunc_round_v2f32_to_v2f16_downward(<2 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v2f32_to_v2f16_downward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v2f32_to_v2f16_downward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: ; return to shader part epilog + %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.downward") + ret <2 x half> %res +} + +define amdgpu_gs void @v_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x float> %a, <2 x float> %b, ptr addrspace(1) %out) { +; SDAG-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v3 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v3 +; SDAG-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; SDAG-NEXT: v_perm_b32 v1, v2, v1, 0x5040100 +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0 +; SDAG-NEXT: v_pk_add_f16 v0, v0, v3 +; SDAG-NEXT: v_pk_add_f16 v0, v1, v0 +; SDAG-NEXT: global_store_dword v[4:5], v0, off +; SDAG-NEXT: s_endpgm +; +; GISEL-LABEL: v_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v3 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_lshl_or_b32 v1, v7, 16, v6 +; GISEL-NEXT: v_lshl_or_b32 v2, v3, 16, v2 +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0 +; GISEL-NEXT: v_pk_add_f16 v0, v0, v1 +; GISEL-NEXT: v_pk_add_f16 v0, v2, v0 +; GISEL-NEXT: global_store_dword v[4:5], v0, off +; GISEL-NEXT: s_endpgm + %res1 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward") + %res2 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.upward") + %res3 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.downward") + %res4 = fadd <2 x half> %res1, %res2 + %res5 = fadd <2 x half> %res3, %res4 + store <2 x half> %res5, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_upward(<2 x float> inreg %a, ptr addrspace(1) %out) { +; CHECK-LABEL: s_fptrunc_round_v2f32_to_v2f16_upward: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v0, s0 +; CHECK-NEXT: v_mov_b32_e32 v1, s1 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1 +; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; CHECK-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: v_readfirstlane_b32 s1, v1 +; CHECK-NEXT: ; return to shader part epilog + %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward") + %bitcast = bitcast <2 x half> %res to <2 x i16> + %ret = zext <2 x i16> %bitcast to <2 x i32> + ret <2 x i32> %ret +} + +define amdgpu_gs <2 x i32> @s_fptrunc_round_v2f32_to_v2f16_downward(<2 x float> inreg %a, ptr addrspace(1) %out) { +; CHECK-LABEL: s_fptrunc_round_v2f32_to_v2f16_downward: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v0, s0 +; CHECK-NEXT: v_mov_b32_e32 v1, s1 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v0, v0 +; CHECK-NEXT: v_cvt_f16_f32_e32 v1, v1 +; CHECK-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; CHECK-NEXT: v_and_b32_e32 v1, 0xffff, v1 +; CHECK-NEXT: v_readfirstlane_b32 s0, v0 +; CHECK-NEXT: v_readfirstlane_b32 s1, v1 +; CHECK-NEXT: ; return to shader part epilog + %res = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.downward") + %bitcast = bitcast <2 x half> %res to <2 x i16> + %ret = zext <2 x i16> %bitcast to <2 x i32> + ret <2 x i32> %ret +} + +define amdgpu_gs void @s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls(<2 x float> inreg %a, <2 x float> inreg %b, ptr addrspace(1) %out) { +; CHECK-LABEL: s_fptrunc_round_v2f32_to_v2f16_upward_multiple_calls: +; CHECK: ; %bb.0: +; CHECK-NEXT: v_mov_b32_e32 v2, s0 +; CHECK-NEXT: v_mov_b32_e32 v3, s2 +; CHECK-NEXT: v_mov_b32_e32 v4, s1 +; CHECK-NEXT: v_mov_b32_e32 v5, s3 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; CHECK-NEXT: v_cvt_f16_f32_e32 v2, v2 +; CHECK-NEXT: v_cvt_f16_f32_e32 v6, v3 +; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v4 +; CHECK-NEXT: v_cvt_f16_f32_e32 v7, v5 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 2 +; CHECK-NEXT: v_cvt_f16_f32_e32 v3, v3 +; CHECK-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; CHECK-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; CHECK-NEXT: v_and_b32_e32 v3, 0xffff, v3 +; CHECK-NEXT: v_lshl_or_b32 v2, v4, 16, v2 +; CHECK-NEXT: v_cvt_f16_f32_e32 v4, v5 +; CHECK-NEXT: v_lshl_or_b32 v5, v7, 16, v6 +; CHECK-NEXT: v_lshl_or_b32 v3, v4, 16, v3 +; CHECK-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 0 +; CHECK-NEXT: v_pk_add_f16 v2, v2, v5 +; CHECK-NEXT: v_pk_add_f16 v2, v3, v2 +; CHECK-NEXT: global_store_dword v[0:1], v2, off +; CHECK-NEXT: s_endpgm + %res1 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %a, metadata !"round.upward") + %res2 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.upward") + %res3 = call <2 x half> @llvm.fptrunc.round.v2f16.v2f32(<2 x float> %b, metadata !"round.downward") + %res4 = fadd <2 x half> %res1, %res2 + %res5 = fadd <2 x half> %res3, %res4 + store <2 x half> %res5, ptr addrspace(1) %out, align 4 + ret void +} + +define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_upward(<3 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v3f32_to_v3f16_upward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v2 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v3f32_to_v3f16_upward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2 +; GISEL-NEXT: ; return to shader part epilog + %res = call <3 x half> @llvm.fptrunc.round.v3f16.v3f32(<3 x float> %a, metadata !"round.upward") + ret <3 x half> %res +} + +define amdgpu_gs <3 x half> @v_fptrunc_round_v3f32_to_v3f16_downward(<3 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v3f32_to_v3f16_downward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v2 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v3f32_to_v3f16_downward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v2 +; GISEL-NEXT: ; return to shader part epilog + %res = call <3 x half> @llvm.fptrunc.round.v3f16.v3f32(<3 x float> %a, metadata !"round.downward") + ret <3 x half> %res +} + +define amdgpu_gs <4 x half> @v_fptrunc_round_v4f32_to_v4f16_upward(<4 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v4f32_to_v4f16_upward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v4f32_to_v4f16_upward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2 +; GISEL-NEXT: ; return to shader part epilog + %res = call <4 x half> @llvm.fptrunc.round.v4f16.v4f32(<4 x float> %a, metadata !"round.upward") + ret <4 x half> %res +} + +define amdgpu_gs <4 x half> @v_fptrunc_round_v4f32_to_v4f16_downward(<4 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v4f32_to_v4f16_downward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v4f32_to_v4f16_downward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2 +; GISEL-NEXT: ; return to shader part epilog + %res = call <4 x half> @llvm.fptrunc.round.v4f16.v4f32(<4 x float> %a, metadata !"round.downward") + ret <4 x half> %res +} + +define amdgpu_gs <8 x half> @v_fptrunc_round_v8f32_to_v8f16_upward(<8 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v8f32_to_v8f16_upward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v6 +; SDAG-NEXT: v_cvt_f16_f32_e32 v4, v4 +; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SDAG-NEXT: v_cvt_f16_f32_e32 v5, v5 +; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v7 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; SDAG-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 +; SDAG-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v8f32_to_v8f16_upward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v6 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GISEL-NEXT: v_cvt_f16_f32_e32 v5, v5 +; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2 +; GISEL-NEXT: v_lshl_or_b32 v2, v5, 16, v4 +; GISEL-NEXT: v_lshl_or_b32 v3, v7, 16, v6 +; GISEL-NEXT: ; return to shader part epilog + %res = call <8 x half> @llvm.fptrunc.round.v8f16.v8f32(<8 x float> %a, metadata !"round.upward") + ret <8 x half> %res +} + +define amdgpu_gs <8 x half> @v_fptrunc_round_v8f32_to_v8f16_downward(<8 x float> %a) { +; SDAG-LABEL: v_fptrunc_round_v8f32_to_v8f16_downward: +; SDAG: ; %bb.0: +; SDAG-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v6, v6 +; SDAG-NEXT: v_cvt_f16_f32_e32 v4, v4 +; SDAG-NEXT: v_cvt_f16_f32_e32 v2, v2 +; SDAG-NEXT: v_cvt_f16_f32_e32 v0, v0 +; SDAG-NEXT: v_cvt_f16_f32_e32 v1, v1 +; SDAG-NEXT: v_cvt_f16_f32_e32 v3, v3 +; SDAG-NEXT: v_cvt_f16_f32_e32 v5, v5 +; SDAG-NEXT: v_cvt_f16_f32_e32 v7, v7 +; SDAG-NEXT: v_perm_b32 v0, v1, v0, 0x5040100 +; SDAG-NEXT: v_perm_b32 v1, v3, v2, 0x5040100 +; SDAG-NEXT: v_perm_b32 v2, v5, v4, 0x5040100 +; SDAG-NEXT: v_perm_b32 v3, v7, v6, 0x5040100 +; SDAG-NEXT: ; return to shader part epilog +; +; GISEL-LABEL: v_fptrunc_round_v8f32_to_v8f16_downward: +; GISEL: ; %bb.0: +; GISEL-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 3, 1), 1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v0, v0 +; GISEL-NEXT: v_cvt_f16_f32_e32 v2, v2 +; GISEL-NEXT: v_cvt_f16_f32_e32 v4, v4 +; GISEL-NEXT: v_cvt_f16_f32_e32 v6, v6 +; GISEL-NEXT: v_cvt_f16_f32_e32 v1, v1 +; GISEL-NEXT: v_cvt_f16_f32_e32 v3, v3 +; GISEL-NEXT: v_cvt_f16_f32_e32 v5, v5 +; GISEL-NEXT: v_cvt_f16_f32_e32 v7, v7 +; GISEL-NEXT: v_and_b32_e32 v0, 0xffff, v0 +; GISEL-NEXT: v_and_b32_e32 v2, 0xffff, v2 +; GISEL-NEXT: v_and_b32_e32 v4, 0xffff, v4 +; GISEL-NEXT: v_and_b32_e32 v6, 0xffff, v6 +; GISEL-NEXT: v_lshl_or_b32 v0, v1, 16, v0 +; GISEL-NEXT: v_lshl_or_b32 v1, v3, 16, v2 +; GISEL-NEXT: v_lshl_or_b32 v2, v5, 16, v4 +; GISEL-NEXT: v_lshl_or_b32 v3, v7, 16, v6 +; GISEL-NEXT: ; return to shader part epilog + %res = call <8 x half> @llvm.fptrunc.round.v8f16.v8f32(<8 x float> %a, metadata !"round.downward") + ret <8 x half> %res +} diff --git a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll index cfff0a969da9e7f9c7ca6526d87e29312c6adf0c..14fe4e5f48c67cfdea4c33fe53ca902defb3d618 100644 --- a/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll +++ b/llvm/test/CodeGen/AMDGPU/lower-work-group-id-intrinsics-pal.ll @@ -1,8 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-SDAG %s -; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9,GFX9-GISEL %s -; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-SDAG %s -; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH,GFX9ARCH-GISEL %s +; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=-architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9 %s +; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-SDAG %s +; RUN: llc -mtriple=amdgcn-amd-hsa -mcpu=gfx900 -mattr=+architected-sgprs -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX9ARCH-GISEL %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=0 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-SDAG %s ; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -global-isel=1 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12,GFX12-GISEL %s @@ -156,10 +156,37 @@ define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace( ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_setpc_b64 s[30:31] ; -; GFX9ARCH-LABEL: workgroup_ids_gfx: -; GFX9ARCH: ; %bb.0: -; GFX9ARCH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) -; GFX9ARCH-NEXT: s_setpc_b64 s[30:31] +; GFX9ARCH-SDAG-LABEL: workgroup_ids_gfx: +; GFX9ARCH-SDAG: ; %bb.0: +; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v6, ttmp9 +; GFX9ARCH-SDAG-NEXT: s_and_b32 s34, ttmp7, 0xffff +; GFX9ARCH-SDAG-NEXT: global_store_dword v[0:1], v6, off +; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, s34 +; GFX9ARCH-SDAG-NEXT: s_lshr_b32 s34, ttmp7, 16 +; GFX9ARCH-SDAG-NEXT: global_store_dword v[2:3], v0, off +; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9ARCH-SDAG-NEXT: v_mov_b32_e32 v0, s34 +; GFX9ARCH-SDAG-NEXT: global_store_dword v[4:5], v0, off +; GFX9ARCH-SDAG-NEXT: s_waitcnt vmcnt(0) +; GFX9ARCH-SDAG-NEXT: s_setpc_b64 s[30:31] +; +; GFX9ARCH-GISEL-LABEL: workgroup_ids_gfx: +; GFX9ARCH-GISEL: ; %bb.0: +; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v6, ttmp9 +; GFX9ARCH-GISEL-NEXT: s_and_b32 s34, ttmp7, 0xffff +; GFX9ARCH-GISEL-NEXT: s_lshr_b32 s35, ttmp7, 16 +; GFX9ARCH-GISEL-NEXT: global_store_dword v[0:1], v6, off +; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s34 +; GFX9ARCH-GISEL-NEXT: global_store_dword v[2:3], v0, off +; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9ARCH-GISEL-NEXT: v_mov_b32_e32 v0, s35 +; GFX9ARCH-GISEL-NEXT: global_store_dword v[4:5], v0, off +; GFX9ARCH-GISEL-NEXT: s_waitcnt vmcnt(0) +; GFX9ARCH-GISEL-NEXT: s_setpc_b64 s[30:31] ; ; GFX12-LABEL: workgroup_ids_gfx: ; GFX12: ; %bb.0: @@ -168,6 +195,18 @@ define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace( ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 +; GFX12-NEXT: s_and_b32 s0, ttmp7, 0xffff +; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1) +; GFX12-NEXT: v_dual_mov_b32 v6, ttmp9 :: v_dual_mov_b32 v7, s0 +; GFX12-NEXT: s_lshr_b32 s1, ttmp7, 16 +; GFX12-NEXT: v_mov_b32_e32 v8, s1 +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: global_store_b32 v[0:1], v6, off scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: global_store_b32 v[2:3], v7, off scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 +; GFX12-NEXT: global_store_b32 v[4:5], v8, off scope:SCOPE_SYS +; GFX12-NEXT: s_wait_storecnt 0x0 ; GFX12-NEXT: s_setpc_b64 s[30:31] %id.x = call i32 @llvm.amdgcn.workgroup.id.x() %id.y = call i32 @llvm.amdgcn.workgroup.id.y() @@ -177,11 +216,3 @@ define amdgpu_gfx void @workgroup_ids_gfx(ptr addrspace(1) %outx, ptr addrspace( store volatile i32 %id.z, ptr addrspace(1) %outz ret void } - -declare i32 @llvm.amdgcn.workgroup.id.x() -declare i32 @llvm.amdgcn.workgroup.id.y() -declare i32 @llvm.amdgcn.workgroup.id.z() -declare void @llvm.amdgcn.raw.ptr.buffer.store.v3i32(<3 x i32>, ptr addrspace(8), i32, i32, i32 immarg) -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; GFX9-GISEL: {{.*}} -; GFX9-SDAG: {{.*}} diff --git a/llvm/test/CodeGen/AMDGPU/mmra.ll b/llvm/test/CodeGen/AMDGPU/mmra.ll new file mode 100644 index 0000000000000000000000000000000000000000..d9b48f79739b677b6a4d6bfcde153c2bddac69f0 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/mmra.ll @@ -0,0 +1,189 @@ +; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -march=amdgcn -mcpu=gfx900 -stop-after=finalize-isel < %s | FileCheck %s + +declare void @readsMem(ptr) #0 +declare void @writesMem(ptr) #1 + +define void @fence_loads(ptr %ptr) { + ; CHECK-LABEL: name: fence_loads + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; CHECK-NEXT: ATOMIC_FENCE 5, 1, mmra !0 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], mmra !1 + ; CHECK-NEXT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr, mmra !1 :: (load acquire (s8) from %ir.ptr, align 4) + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 1, mmra !2 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], mmra !2 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[S_MOV_B32_]], mmra !2 + ; CHECK-NEXT: FLAT_STORE_BYTE [[COPY3]], killed [[COPY4]], 0, 0, implicit $exec, implicit $flat_scr, mmra !2 :: (store release (s8) into %ir.ptr, align 4) + ; CHECK-NEXT: SI_RETURN + fence release, !mmra !0 + %ld = load atomic i8, ptr %ptr acquire, align 4, !mmra !2 + store atomic i8 1, ptr %ptr release, align 4, !mmra !1 + ret void +} + +define void @atomicrmw_acq(ptr %ptr) { + ; CHECK-LABEL: name: atomicrmw_acq + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], mmra !1 + ; CHECK-NEXT: [[FLAT_LOAD_UBYTE:%[0-9]+]]:vgpr_32 = FLAT_LOAD_UBYTE killed [[COPY2]], 0, 0, implicit $exec, implicit $flat_scr, mmra !1 :: (load acquire (s8) from %ir.ptr) + ; CHECK-NEXT: SI_RETURN + %old.2 = atomicrmw add ptr %ptr, i8 0 acquire, !mmra !2 + ret void +} + +define void @atomicrmw_rel(ptr %ptr) { + ; CHECK-LABEL: name: atomicrmw_rel + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 + ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], killed [[S_MOV_B32_]], implicit $exec + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] + ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3 + ; CHECK-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[S_MOV_B32_1]], implicit $exec + ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[S_MOV_B32_1]], killed [[V_AND_B32_e64_1]], implicit $exec + ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 255 + ; CHECK-NEXT: [[V_LSHLREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 killed [[V_LSHLREV_B32_e64_]], killed [[S_MOV_B32_2]], implicit $exec + ; CHECK-NEXT: [[V_NOT_B32_e32_:%[0-9]+]]:vgpr_32 = V_NOT_B32_e32 [[V_LSHLREV_B32_e64_1]], implicit $exec + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], mmra !2 + ; CHECK-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, mmra !2 :: (load (s32) from %ir.AlignedAddr) + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.atomicrmw.start: + ; CHECK-NEXT: successors: %bb.2(0x04000000), %bb.1(0x7c000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.0, %7, %bb.1 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:vgpr_32 = PHI [[FLAT_LOAD_DWORD]], %bb.0, %6, %bb.1 + ; CHECK-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[V_NOT_B32_e32_]], [[V_LSHLREV_B32_e64_1]], implicit $exec + ; CHECK-NEXT: [[V_AND_B32_e64_2:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI1]], killed [[V_OR_B32_e64_]], implicit $exec + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_2]], %subreg.sub0, [[PHI1]], %subreg.sub1, mmra !2 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE2]], mmra !2 + ; CHECK-NEXT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY4]], killed [[COPY6]], 0, 1, implicit $exec, implicit $flat_scr, mmra !2 :: (load store release monotonic (s32) on %ir.AlignedAddr) + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[FLAT_ATOMIC_CMPSWAP_RTN]], [[PHI1]], implicit $exec, mmra !2 + ; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK killed [[V_CMP_EQ_U32_e64_]], [[PHI]], implicit-def dead $scc + ; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.atomicrmw.end: + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_64 = PHI [[SI_IF_BREAK]], %bb.1 + ; CHECK-NEXT: SI_END_CF [[PHI2]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: SI_RETURN + %old.2 = atomicrmw add ptr %ptr, i8 0 release, !mmra !1 + ret void +} + +define void @cmpxchg(ptr %ptr) { + ; CHECK-LABEL: name: cmpxchg + ; CHECK: bb.0 (%ir-block.0): + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: liveins: $vgpr0, $vgpr1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr1 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, [[COPY]], %subreg.sub1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub1 + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE]].sub0 + ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 -4 + ; CHECK-NEXT: [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], killed [[S_MOV_B32_]], implicit $exec + ; CHECK-NEXT: [[DEF2:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF3:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[COPY2]], %subreg.sub1 + ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]] + ; CHECK-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 3 + ; CHECK-NEXT: [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY3]], [[S_MOV_B32_1]], implicit $exec + ; CHECK-NEXT: [[V_LSHLREV_B32_e64_:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[S_MOV_B32_1]], killed [[V_AND_B32_e64_1]], implicit $exec + ; CHECK-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32 = S_MOV_B32 255 + ; CHECK-NEXT: [[V_LSHLREV_B32_e64_1:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[V_LSHLREV_B32_e64_]], killed [[S_MOV_B32_2]], implicit $exec + ; CHECK-NEXT: [[V_NOT_B32_e32_:%[0-9]+]]:vgpr_32 = V_NOT_B32_e32 killed [[V_LSHLREV_B32_e64_1]], implicit $exec + ; CHECK-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32 = S_MOV_B32 1 + ; CHECK-NEXT: [[V_LSHLREV_B32_e64_2:%[0-9]+]]:vgpr_32 = V_LSHLREV_B32_e64 [[V_LSHLREV_B32_e64_]], killed [[S_MOV_B32_3]], implicit $exec + ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], mmra !1 + ; CHECK-NEXT: [[FLAT_LOAD_DWORD:%[0-9]+]]:vgpr_32 = FLAT_LOAD_DWORD [[COPY5]], 0, 0, implicit $exec, implicit $flat_scr, mmra !1 :: (load (s32) from %ir.AlignedAddr) + ; CHECK-NEXT: [[V_AND_B32_e64_2:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 killed [[FLAT_LOAD_DWORD]], [[V_NOT_B32_e32_]], implicit $exec + ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 0 + ; CHECK-NEXT: [[DEF4:%[0-9]+]]:sreg_64 = IMPLICIT_DEF + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1.partword.cmpxchg.loop: + ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI:%[0-9]+]]:sreg_64 = PHI [[DEF4]], %bb.0, %12, %bb.3 + ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_64 = PHI [[S_MOV_B64_]], %bb.0, %13, %bb.3 + ; CHECK-NEXT: [[PHI2:%[0-9]+]]:vgpr_32 = PHI [[V_AND_B32_e64_2]], %bb.0, %11, %bb.3 + ; CHECK-NEXT: [[V_OR_B32_e64_:%[0-9]+]]:vgpr_32 = V_OR_B32_e64 [[PHI2]], [[V_LSHLREV_B32_e64_2]], implicit $exec + ; CHECK-NEXT: [[DEF5:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[DEF6:%[0-9]+]]:sgpr_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_OR_B32_e64_]], %subreg.sub0, [[PHI2]], %subreg.sub1, mmra !1 + ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE2]], mmra !1 + ; CHECK-NEXT: [[FLAT_ATOMIC_CMPSWAP_RTN:%[0-9]+]]:vgpr_32 = FLAT_ATOMIC_CMPSWAP_RTN [[COPY4]], killed [[COPY6]], 0, 1, implicit $exec, implicit $flat_scr, mmra !1 :: (load store acquire acquire (s32) on %ir.AlignedAddr) + ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_NE_U32_e64 [[FLAT_ATOMIC_CMPSWAP_RTN]], [[PHI2]], implicit $exec + ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 -1 + ; CHECK-NEXT: [[DEF7:%[0-9]+]]:sreg_32 = IMPLICIT_DEF + ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[DEF7]] + ; CHECK-NEXT: [[S_OR_B64_:%[0-9]+]]:sreg_64 = S_OR_B64 [[PHI]], $exec, implicit-def $scc + ; CHECK-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_NE_U32_e64_]], %bb.3, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.2 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.2.partword.cmpxchg.failure: + ; CHECK-NEXT: successors: %bb.3(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[V_AND_B32_e64_3:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[FLAT_ATOMIC_CMPSWAP_RTN]], [[V_NOT_B32_e32_]], implicit $exec + ; CHECK-NEXT: [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[PHI2]], [[V_AND_B32_e64_3]], implicit $exec + ; CHECK-NEXT: [[S_ANDN2_B64_:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[S_OR_B64_]], $exec, implicit-def $scc + ; CHECK-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], $exec, implicit-def $scc + ; CHECK-NEXT: [[S_OR_B64_1:%[0-9]+]]:sreg_64 = S_OR_B64 [[S_ANDN2_B64_]], [[S_AND_B64_]], implicit-def $scc + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.3.Flow: + ; CHECK-NEXT: successors: %bb.4(0x04000000), %bb.1(0x7c000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[PHI3:%[0-9]+]]:sreg_64 = PHI [[S_OR_B64_]], %bb.1, [[S_OR_B64_1]], %bb.2 + ; CHECK-NEXT: [[PHI4:%[0-9]+]]:vgpr_32 = PHI [[COPY7]], %bb.1, [[V_AND_B32_e64_3]], %bb.2 + ; CHECK-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: [[COPY8:%[0-9]+]]:sreg_64 = COPY [[PHI3]] + ; CHECK-NEXT: [[SI_IF_BREAK:%[0-9]+]]:sreg_64 = SI_IF_BREAK [[COPY8]], [[PHI1]], implicit-def dead $scc + ; CHECK-NEXT: SI_LOOP [[SI_IF_BREAK]], %bb.1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: S_BRANCH %bb.4 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.4.partword.cmpxchg.end: + ; CHECK-NEXT: [[PHI5:%[0-9]+]]:sreg_64 = PHI [[SI_IF_BREAK]], %bb.3 + ; CHECK-NEXT: [[PHI6:%[0-9]+]]:vgpr_32 = PHI [[FLAT_ATOMIC_CMPSWAP_RTN]], %bb.3 + ; CHECK-NEXT: SI_END_CF [[PHI5]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec + ; CHECK-NEXT: SI_RETURN + %pair = cmpxchg ptr %ptr, i8 0, i8 1 acquire acquire, !mmra !2 + ret void +} + +attributes #0 = { memory(read) } +attributes #1 = { memory(write) } + +!0 = !{!"foo", !"bar"} +!1 = !{!"bux", !"baz"} +!2 = !{!0, !1} diff --git a/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll new file mode 100644 index 0000000000000000000000000000000000000000..2403aeaa4428ad2523acf28722fc0d0a6535da09 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/mode-register-fpconstrain.ll @@ -0,0 +1,43 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 %s -o - | FileCheck -check-prefix=GCN %s + +; The si-mode-register pass is changing the default mode for FP constrained operations. +; It must ignore for strictfp functions. + +define double @ignoreStrictfp(double noundef %a, double noundef %b) #0 { +; GCN-LABEL: ignoreStrictfp: +; GCN: ; %bb.0: +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 2), 1 +; GCN-NEXT: s_nop 1 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0 +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] + tail call void @llvm.amdgcn.s.setreg(i32 2177, i32 1) + %val = tail call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 + ret double %val +} + +define double @set_fpenv(double noundef %a, double noundef %b) #0 { +; GCN-LABEL: set_fpenv: +; GCN: ; %bb.0: ; %entry +; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 0, 23), 4 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_TRAPSTS, 0, 5), 0 +; GCN-NEXT: s_nop 0 +; GCN-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 2, 1), 0 +; GCN-NEXT: v_add_f64 v[0:1], v[0:1], v[2:3] +; GCN-NEXT: s_setpc_b64 s[30:31] +entry: + call void @llvm.set.fpenv.i64(i64 4) + %val = tail call double @llvm.experimental.constrained.fadd.f64(double %a, double %b, metadata !"round.dynamic", metadata !"fpexcept.strict") #0 + ret double %val +} + +declare void @llvm.amdgcn.s.setreg(i32 immarg, i32) + +declare double @llvm.experimental.constrained.fadd.f64(double, double, metadata, metadata) + +declare void @llvm.set.fpenv.i64(i64) + +attributes #0 = { strictfp } diff --git a/llvm/test/CodeGen/AMDGPU/trap-abis.ll b/llvm/test/CodeGen/AMDGPU/trap-abis.ll index 3cd6c98ef4b8e0002e58e9524d6d56798c9fcc1b..dcc5fbd142c42723fe6ad74435c5b9e47ab3af2c 100644 --- a/llvm/test/CodeGen/AMDGPU/trap-abis.ll +++ b/llvm/test/CodeGen/AMDGPU/trap-abis.ll @@ -3,6 +3,8 @@ ; RUN: llc %s -o - -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX803 %s ; RUN: llc %s -o - -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX900 %s ; RUN: llc %s -o - -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -mattr=-trap-handler -verify-machineinstrs | FileCheck --check-prefix=HSA-NOTRAP-GFX900 %s +; RUN: llc %s -o - -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX1100 %s +; RUN: llc %s -o - -O0 -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-machineinstrs | FileCheck --check-prefix=HSA-TRAP-GFX1100-O0 %s declare void @llvm.trap() #0 declare void @llvm.debugtrap() #1 @@ -49,6 +51,48 @@ define amdgpu_kernel void @trap(ptr addrspace(1) nocapture readonly %arg0) { ; HSA-NOTRAP-GFX900-NEXT: global_store_dword v0, v1, s[0:1] ; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-NEXT: s_endpgm +; +; HSA-TRAP-GFX1100-LABEL: trap: +; HSA-TRAP-GFX1100: ; %bb.0: +; HSA-TRAP-GFX1100-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; HSA-TRAP-GFX1100-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1 +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 ttmp2, m0 +; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: global_store_b32 v0, v1, s[0:1] dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-NEXT: s_trap 2 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: s_and_b32 s0, s0, 0x3ff +; HSA-TRAP-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; HSA-TRAP-GFX1100-NEXT: s_bitset1_b32 s0, 10 +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, s0 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, ttmp2 +; HSA-TRAP-GFX1100-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1 +; HSA-TRAP-GFX1100-NEXT: s_sethalt 5 +; HSA-TRAP-GFX1100-NEXT: s_branch .LBB0_1 +; +; HSA-TRAP-GFX1100-O0-LABEL: trap: +; HSA-TRAP-GFX1100-O0: ; %bb.0: +; HSA-TRAP-GFX1100-O0-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v0, 0 +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v1, 1 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v0, v1, s[0:1] dlc +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-O0-NEXT: s_trap 2 +; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 ttmp2, m0 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: s_and_b32 s0, s0, 0x3ff +; HSA-TRAP-GFX1100-O0-NEXT: s_or_b32 s0, s0, 0x400 +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, s0 +; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, ttmp2 +; HSA-TRAP-GFX1100-O0-NEXT: .LBB0_1: ; =>This Inner Loop Header: Depth=1 +; HSA-TRAP-GFX1100-O0-NEXT: s_sethalt 5 +; HSA-TRAP-GFX1100-O0-NEXT: s_branch .LBB0_1 store volatile i32 1, ptr addrspace(1) %arg0 call void @llvm.trap() unreachable @@ -128,6 +172,84 @@ define amdgpu_kernel void @non_entry_trap(ptr addrspace(1) nocapture readonly %a ; HSA-NOTRAP-GFX900-NEXT: s_endpgm ; HSA-NOTRAP-GFX900-NEXT: .LBB1_2: ; %trap ; HSA-NOTRAP-GFX900-NEXT: s_endpgm +; +; HSA-TRAP-GFX1100-LABEL: non_entry_trap: +; HSA-TRAP-GFX1100: ; %bb.0: ; %entry +; HSA-TRAP-GFX1100-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v0, 0 +; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: global_load_b32 v1, v0, s[0:1] glc dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX1100-NEXT: v_cmp_eq_u32_e32 vcc_lo, -1, v1 +; HSA-TRAP-GFX1100-NEXT: s_cbranch_vccz .LBB1_2 +; HSA-TRAP-GFX1100-NEXT: ; %bb.1: ; %ret +; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v1, 3 +; HSA-TRAP-GFX1100-NEXT: global_store_b32 v0, v1, s[0:1] dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-NEXT: s_nop 0 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; HSA-TRAP-GFX1100-NEXT: s_endpgm +; HSA-TRAP-GFX1100-NEXT: .LBB1_2: ; %trap +; HSA-TRAP-GFX1100-NEXT: s_trap 2 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 ttmp2, m0 +; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: s_and_b32 s0, s0, 0x3ff +; HSA-TRAP-GFX1100-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1) +; HSA-TRAP-GFX1100-NEXT: s_bitset1_b32 s0, 10 +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, s0 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) +; HSA-TRAP-GFX1100-NEXT: s_mov_b32 m0, ttmp2 +; HSA-TRAP-GFX1100-NEXT: .LBB1_3: ; =>This Inner Loop Header: Depth=1 +; HSA-TRAP-GFX1100-NEXT: s_sethalt 5 +; HSA-TRAP-GFX1100-NEXT: s_branch .LBB1_3 +; +; HSA-TRAP-GFX1100-O0-LABEL: non_entry_trap: +; HSA-TRAP-GFX1100-O0: ; %bb.0: ; %entry +; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $vgpr0 : SGPR spill to VGPR lane +; HSA-TRAP-GFX1100-O0-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b64 s[2:3], s[0:1] +; HSA-TRAP-GFX1100-O0-NEXT: v_writelane_b32 v0, s2, 0 +; HSA-TRAP-GFX1100-O0-NEXT: v_writelane_b32 v0, s3, 1 +; HSA-TRAP-GFX1100-O0-NEXT: s_or_saveexec_b32 s6, -1 +; HSA-TRAP-GFX1100-O0-NEXT: scratch_store_b32 off, v0, off ; 4-byte Folded Spill +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 exec_lo, s6 +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v0, 0 +; HSA-TRAP-GFX1100-O0-NEXT: global_load_b32 v0, v0, s[0:1] glc dlc +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 s0, -1 +; HSA-TRAP-GFX1100-O0-NEXT: ; implicit-def: $sgpr1 +; HSA-TRAP-GFX1100-O0-NEXT: v_cmp_eq_u32_e64 s0, v0, s0 +; HSA-TRAP-GFX1100-O0-NEXT: s_and_b32 vcc_lo, exec_lo, s0 +; HSA-TRAP-GFX1100-O0-NEXT: s_cbranch_vccnz .LBB1_2 +; HSA-TRAP-GFX1100-O0-NEXT: ; %bb.1: ; %trap +; HSA-TRAP-GFX1100-O0-NEXT: s_trap 2 +; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg_rtn_b32 s0, sendmsg(MSG_RTN_GET_DOORBELL) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 ttmp2, m0 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: s_and_b32 s0, s0, 0x3ff +; HSA-TRAP-GFX1100-O0-NEXT: s_or_b32 s0, s0, 0x400 +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, s0 +; HSA-TRAP-GFX1100-O0-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 m0, ttmp2 +; HSA-TRAP-GFX1100-O0-NEXT: s_branch .LBB1_3 +; HSA-TRAP-GFX1100-O0-NEXT: .LBB1_2: ; %ret +; HSA-TRAP-GFX1100-O0-NEXT: s_or_saveexec_b32 s6, -1 +; HSA-TRAP-GFX1100-O0-NEXT: scratch_load_b32 v0, off, off ; 4-byte Folded Reload +; HSA-TRAP-GFX1100-O0-NEXT: s_mov_b32 exec_lo, s6 +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt vmcnt(0) +; HSA-TRAP-GFX1100-O0-NEXT: v_readlane_b32 s0, v0, 0 +; HSA-TRAP-GFX1100-O0-NEXT: v_readlane_b32 s1, v0, 1 +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v1, 0 +; HSA-TRAP-GFX1100-O0-NEXT: v_mov_b32_e32 v2, 3 +; HSA-TRAP-GFX1100-O0-NEXT: global_store_b32 v1, v2, s[0:1] dlc +; HSA-TRAP-GFX1100-O0-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-O0-NEXT: ; kill: killed $vgpr0 +; HSA-TRAP-GFX1100-O0-NEXT: s_endpgm +; HSA-TRAP-GFX1100-O0-NEXT: .LBB1_3: ; =>This Inner Loop Header: Depth=1 +; HSA-TRAP-GFX1100-O0-NEXT: s_sethalt 5 +; HSA-TRAP-GFX1100-O0-NEXT: s_branch .LBB1_3 entry: %tmp29 = load volatile i32, ptr addrspace(1) %arg0 %cmp = icmp eq i32 %tmp29, -1 @@ -197,6 +319,21 @@ define amdgpu_kernel void @debugtrap(ptr addrspace(1) nocapture readonly %arg0) ; HSA-NOTRAP-GFX900-NEXT: global_store_dword v0, v2, s[0:1] ; HSA-NOTRAP-GFX900-NEXT: s_waitcnt vmcnt(0) ; HSA-NOTRAP-GFX900-NEXT: s_endpgm +; +; HSA-TRAP-GFX1100-LABEL: debugtrap: +; HSA-TRAP-GFX1100: ; %bb.0: +; HSA-TRAP-GFX1100-NEXT: s_load_b64 s[0:1], s[0:1], 0x0 +; HSA-TRAP-GFX1100-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, 1 +; HSA-TRAP-GFX1100-NEXT: v_mov_b32_e32 v2, 2 +; HSA-TRAP-GFX1100-NEXT: s_waitcnt lgkmcnt(0) +; HSA-TRAP-GFX1100-NEXT: global_store_b32 v0, v1, s[0:1] dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-NEXT: s_trap 3 +; HSA-TRAP-GFX1100-NEXT: global_store_b32 v0, v2, s[0:1] dlc +; HSA-TRAP-GFX1100-NEXT: s_waitcnt_vscnt null, 0x0 +; HSA-TRAP-GFX1100-NEXT: s_nop 0 +; HSA-TRAP-GFX1100-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) +; HSA-TRAP-GFX1100-NEXT: s_endpgm store volatile i32 1, ptr addrspace(1) %arg0 call void @llvm.debugtrap() store volatile i32 2, ptr addrspace(1) %arg0 diff --git a/llvm/test/CodeGen/Mips/atomic-min-max.ll b/llvm/test/CodeGen/Mips/atomic-min-max.ll index 2f07d70808c16aecaae0a3913245381afad8a739..3d3225509d1ae14eeb2f101538d331ba2db146e3 100644 --- a/llvm/test/CodeGen/Mips/atomic-min-max.ll +++ b/llvm/test/CodeGen/Mips/atomic-min-max.ll @@ -2156,8 +2156,7 @@ define i16 @test_umax_16(ptr nocapture %ptr, i16 signext %val) { ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS32-NEXT: ll $2, 0($6) ; MIPS32-NEXT: srav $4, $2, $10 -; MIPS32-NEXT: sll $4, $4, 16 -; MIPS32-NEXT: srl $4, $4, 16 +; MIPS32-NEXT: andi $4, $4, 65535 ; MIPS32-NEXT: or $1, $zero, $4 ; MIPS32-NEXT: sllv $4, $4, $10 ; MIPS32-NEXT: sltu $5, $4, $7 @@ -2695,8 +2694,7 @@ define i16 @test_umin_16(ptr nocapture %ptr, i16 signext %val) { ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS32-NEXT: ll $2, 0($6) ; MIPS32-NEXT: srav $4, $2, $10 -; MIPS32-NEXT: sll $4, $4, 16 -; MIPS32-NEXT: srl $4, $4, 16 +; MIPS32-NEXT: andi $4, $4, 65535 ; MIPS32-NEXT: or $1, $zero, $4 ; MIPS32-NEXT: sllv $4, $4, $10 ; MIPS32-NEXT: sltu $5, $4, $7 @@ -4313,8 +4311,7 @@ define i8 @test_umax_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS32-NEXT: ll $2, 0($6) ; MIPS32-NEXT: srav $4, $2, $10 -; MIPS32-NEXT: sll $4, $4, 24 -; MIPS32-NEXT: srl $4, $4, 24 +; MIPS32-NEXT: andi $4, $4, 255 ; MIPS32-NEXT: or $1, $zero, $4 ; MIPS32-NEXT: sllv $4, $4, $10 ; MIPS32-NEXT: sltu $5, $4, $7 @@ -4852,8 +4849,7 @@ define i8 @test_umin_8(ptr nocapture %ptr, i8 signext %val) { ; MIPS32-NEXT: # =>This Inner Loop Header: Depth=1 ; MIPS32-NEXT: ll $2, 0($6) ; MIPS32-NEXT: srav $4, $2, $10 -; MIPS32-NEXT: sll $4, $4, 24 -; MIPS32-NEXT: srl $4, $4, 24 +; MIPS32-NEXT: andi $4, $4, 255 ; MIPS32-NEXT: or $1, $zero, $4 ; MIPS32-NEXT: sllv $4, $4, $10 ; MIPS32-NEXT: sltu $5, $4, $7 diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index faf37545e1a1171c70a7e52eaf85f865aa4013f0..56bd4bd0c08f0961e2b85d7dc36394207ac1ad7f 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -47,6 +47,10 @@ ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass ; CHECK-NEXT: Fast Register Allocator +; CHECK-NEXT: MachineDominator Tree Construction +; CHECK-NEXT: Slot index numbering +; CHECK-NEXT: Live Interval Analysis +; CHECK-NEXT: RISC-V Coalesce VSETVLI pass ; CHECK-NEXT: Fast Register Allocator ; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis ; CHECK-NEXT: Fixup Statepoint Caller Saved diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 90472f246918f342f683dd09edd6507b6706cb0e..4121d111091117e07ac6804d91dcd8fd73c008a5 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -143,6 +143,7 @@ ; CHECK-NEXT: Machine Optimization Remark Emitter ; CHECK-NEXT: Greedy Register Allocator ; CHECK-NEXT: Virtual Register Rewriter +; CHECK-NEXT: RISC-V Coalesce VSETVLI pass ; CHECK-NEXT: Virtual Register Map ; CHECK-NEXT: Live Register Matrix ; CHECK-NEXT: Greedy Register Allocator diff --git a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll index 736c8e7d55c75ba16802551cd57215578a81cdf0..8fb251a75bd142c9691ba3c4bb0595a6d2438ced 100644 --- a/llvm/test/CodeGen/RISCV/addimm-mulimm.ll +++ b/llvm/test/CodeGen/RISCV/addimm-mulimm.ll @@ -10,15 +10,17 @@ define i32 @add_mul_combine_accept_a1(i32 %x) { ; RV32IMB-LABEL: add_mul_combine_accept_a1: ; RV32IMB: # %bb.0: -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 1073 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_a1: ; RV64IMB: # %bb.0: -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 1073 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 37 @@ -29,15 +31,17 @@ define i32 @add_mul_combine_accept_a1(i32 %x) { define signext i32 @add_mul_combine_accept_a2(i32 signext %x) { ; RV32IMB-LABEL: add_mul_combine_accept_a2: ; RV32IMB: # %bb.0: -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 1073 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_accept_a2: ; RV64IMB: # %bb.0: -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 1073 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 37 @@ -49,10 +53,14 @@ define i64 @add_mul_combine_accept_a3(i64 %x) { ; RV32IMB-LABEL: add_mul_combine_accept_a3: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: li a2, 29 -; RV32IMB-NEXT: mul a1, a1, a2 -; RV32IMB-NEXT: mulhu a3, a0, a2 -; RV32IMB-NEXT: add a1, a3, a1 -; RV32IMB-NEXT: mul a2, a0, a2 +; RV32IMB-NEXT: mulhu a2, a0, a2 +; RV32IMB-NEXT: sh1add a3, a1, a1 +; RV32IMB-NEXT: slli a1, a1, 5 +; RV32IMB-NEXT: sub a1, a1, a3 +; RV32IMB-NEXT: add a1, a2, a1 +; RV32IMB-NEXT: sh1add a2, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a2, a0, a2 ; RV32IMB-NEXT: addi a0, a2, 1073 ; RV32IMB-NEXT: sltu a2, a0, a2 ; RV32IMB-NEXT: add a1, a1, a2 @@ -60,8 +68,9 @@ define i64 @add_mul_combine_accept_a3(i64 %x) { ; ; RV64IMB-LABEL: add_mul_combine_accept_a3: ; RV64IMB: # %bb.0: -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: sub a0, a0, a1 ; RV64IMB-NEXT: addi a0, a0, 1073 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 37 @@ -72,8 +81,9 @@ define i64 @add_mul_combine_accept_a3(i64 %x) { define i32 @add_mul_combine_accept_b1(i32 %x) { ; RV32IMB-LABEL: add_mul_combine_accept_b1: ; RV32IMB: # %bb.0: -; RV32IMB-NEXT: li a1, 23 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh3add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: lui a1, 50 ; RV32IMB-NEXT: addi a1, a1, 1119 ; RV32IMB-NEXT: add a0, a0, a1 @@ -81,8 +91,9 @@ define i32 @add_mul_combine_accept_b1(i32 %x) { ; ; RV64IMB-LABEL: add_mul_combine_accept_b1: ; RV64IMB: # %bb.0: -; RV64IMB-NEXT: li a1, 23 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh3add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: lui a1, 50 ; RV64IMB-NEXT: addi a1, a1, 1119 ; RV64IMB-NEXT: addw a0, a0, a1 @@ -95,8 +106,9 @@ define i32 @add_mul_combine_accept_b1(i32 %x) { define signext i32 @add_mul_combine_accept_b2(i32 signext %x) { ; RV32IMB-LABEL: add_mul_combine_accept_b2: ; RV32IMB: # %bb.0: -; RV32IMB-NEXT: li a1, 23 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh3add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: lui a1, 50 ; RV32IMB-NEXT: addi a1, a1, 1119 ; RV32IMB-NEXT: add a0, a0, a1 @@ -104,8 +116,9 @@ define signext i32 @add_mul_combine_accept_b2(i32 signext %x) { ; ; RV64IMB-LABEL: add_mul_combine_accept_b2: ; RV64IMB: # %bb.0: -; RV64IMB-NEXT: li a1, 23 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh3add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: lui a1, 50 ; RV64IMB-NEXT: addi a1, a1, 1119 ; RV64IMB-NEXT: addw a0, a0, a1 @@ -119,10 +132,14 @@ define i64 @add_mul_combine_accept_b3(i64 %x) { ; RV32IMB-LABEL: add_mul_combine_accept_b3: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: li a2, 23 -; RV32IMB-NEXT: mul a1, a1, a2 -; RV32IMB-NEXT: mulhu a3, a0, a2 -; RV32IMB-NEXT: add a1, a3, a1 -; RV32IMB-NEXT: mul a2, a0, a2 +; RV32IMB-NEXT: mulhu a2, a0, a2 +; RV32IMB-NEXT: sh3add a3, a1, a1 +; RV32IMB-NEXT: slli a1, a1, 5 +; RV32IMB-NEXT: sub a1, a1, a3 +; RV32IMB-NEXT: add a1, a2, a1 +; RV32IMB-NEXT: sh3add a2, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a2, a0, a2 ; RV32IMB-NEXT: lui a0, 50 ; RV32IMB-NEXT: addi a0, a0, 1119 ; RV32IMB-NEXT: add a0, a2, a0 @@ -132,8 +149,9 @@ define i64 @add_mul_combine_accept_b3(i64 %x) { ; ; RV64IMB-LABEL: add_mul_combine_accept_b3: ; RV64IMB: # %bb.0: -; RV64IMB-NEXT: li a1, 23 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh3add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: sub a0, a0, a1 ; RV64IMB-NEXT: lui a1, 50 ; RV64IMB-NEXT: addiw a1, a1, 1119 ; RV64IMB-NEXT: add a0, a0, a1 @@ -147,15 +165,17 @@ define i32 @add_mul_combine_reject_a1(i32 %x) { ; RV32IMB-LABEL: add_mul_combine_reject_a1: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: addi a0, a0, 1971 -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_a1: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1971 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1971 %tmp1 = mul i32 %tmp0, 29 @@ -166,15 +186,17 @@ define signext i32 @add_mul_combine_reject_a2(i32 signext %x) { ; RV32IMB-LABEL: add_mul_combine_reject_a2: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: addi a0, a0, 1971 -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_a2: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1971 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: ret %tmp0 = add i32 %x, 1971 %tmp1 = mul i32 %tmp0, 29 @@ -185,10 +207,14 @@ define i64 @add_mul_combine_reject_a3(i64 %x) { ; RV32IMB-LABEL: add_mul_combine_reject_a3: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: li a2, 29 -; RV32IMB-NEXT: mul a1, a1, a2 -; RV32IMB-NEXT: mulhu a3, a0, a2 -; RV32IMB-NEXT: add a1, a3, a1 -; RV32IMB-NEXT: mul a2, a0, a2 +; RV32IMB-NEXT: mulhu a2, a0, a2 +; RV32IMB-NEXT: sh1add a3, a1, a1 +; RV32IMB-NEXT: slli a1, a1, 5 +; RV32IMB-NEXT: sub a1, a1, a3 +; RV32IMB-NEXT: add a1, a2, a1 +; RV32IMB-NEXT: sh1add a2, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a2, a0, a2 ; RV32IMB-NEXT: lui a0, 14 ; RV32IMB-NEXT: addi a0, a0, -185 ; RV32IMB-NEXT: add a0, a2, a0 @@ -199,8 +225,9 @@ define i64 @add_mul_combine_reject_a3(i64 %x) { ; RV64IMB-LABEL: add_mul_combine_reject_a3: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1971 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: sub a0, a0, a1 ; RV64IMB-NEXT: ret %tmp0 = add i64 %x, 1971 %tmp1 = mul i64 %tmp0, 29 @@ -345,15 +372,17 @@ define i32 @add_mul_combine_reject_e1(i32 %x) { ; RV32IMB-LABEL: add_mul_combine_reject_e1: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: addi a0, a0, 1971 -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_e1: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1971 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 %tmp1 = add i32 %tmp0, 57159 @@ -364,15 +393,17 @@ define signext i32 @add_mul_combine_reject_e2(i32 signext %x) { ; RV32IMB-LABEL: add_mul_combine_reject_e2: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: addi a0, a0, 1971 -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_e2: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1971 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mulw a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 %tmp1 = add i32 %tmp0, 57159 @@ -383,10 +414,14 @@ define i64 @add_mul_combine_reject_e3(i64 %x) { ; RV32IMB-LABEL: add_mul_combine_reject_e3: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: li a2, 29 -; RV32IMB-NEXT: mul a1, a1, a2 -; RV32IMB-NEXT: mulhu a3, a0, a2 -; RV32IMB-NEXT: add a1, a3, a1 -; RV32IMB-NEXT: mul a2, a0, a2 +; RV32IMB-NEXT: mulhu a2, a0, a2 +; RV32IMB-NEXT: sh1add a3, a1, a1 +; RV32IMB-NEXT: slli a1, a1, 5 +; RV32IMB-NEXT: sub a1, a1, a3 +; RV32IMB-NEXT: add a1, a2, a1 +; RV32IMB-NEXT: sh1add a2, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a2, a0, a2 ; RV32IMB-NEXT: lui a0, 14 ; RV32IMB-NEXT: addi a0, a0, -185 ; RV32IMB-NEXT: add a0, a2, a0 @@ -397,8 +432,9 @@ define i64 @add_mul_combine_reject_e3(i64 %x) { ; RV64IMB-LABEL: add_mul_combine_reject_e3: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1971 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: sub a0, a0, a1 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 29 %tmp1 = add i64 %tmp0, 57159 @@ -409,16 +445,18 @@ define i32 @add_mul_combine_reject_f1(i32 %x) { ; RV32IMB-LABEL: add_mul_combine_reject_f1: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: addi a0, a0, 1972 -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 11 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_f1: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1972 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 11 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 @@ -430,16 +468,18 @@ define signext i32 @add_mul_combine_reject_f2(i32 signext %x) { ; RV32IMB-LABEL: add_mul_combine_reject_f2: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: addi a0, a0, 1972 -; RV32IMB-NEXT: li a1, 29 -; RV32IMB-NEXT: mul a0, a0, a1 +; RV32IMB-NEXT: sh1add a1, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a0, a0, a1 ; RV32IMB-NEXT: addi a0, a0, 11 ; RV32IMB-NEXT: ret ; ; RV64IMB-LABEL: add_mul_combine_reject_f2: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1972 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: subw a0, a0, a1 ; RV64IMB-NEXT: addiw a0, a0, 11 ; RV64IMB-NEXT: ret %tmp0 = mul i32 %x, 29 @@ -451,10 +491,14 @@ define i64 @add_mul_combine_reject_f3(i64 %x) { ; RV32IMB-LABEL: add_mul_combine_reject_f3: ; RV32IMB: # %bb.0: ; RV32IMB-NEXT: li a2, 29 -; RV32IMB-NEXT: mul a1, a1, a2 -; RV32IMB-NEXT: mulhu a3, a0, a2 -; RV32IMB-NEXT: add a1, a3, a1 -; RV32IMB-NEXT: mul a2, a0, a2 +; RV32IMB-NEXT: mulhu a2, a0, a2 +; RV32IMB-NEXT: sh1add a3, a1, a1 +; RV32IMB-NEXT: slli a1, a1, 5 +; RV32IMB-NEXT: sub a1, a1, a3 +; RV32IMB-NEXT: add a1, a2, a1 +; RV32IMB-NEXT: sh1add a2, a0, a0 +; RV32IMB-NEXT: slli a0, a0, 5 +; RV32IMB-NEXT: sub a2, a0, a2 ; RV32IMB-NEXT: lui a0, 14 ; RV32IMB-NEXT: addi a0, a0, -145 ; RV32IMB-NEXT: add a0, a2, a0 @@ -465,8 +509,9 @@ define i64 @add_mul_combine_reject_f3(i64 %x) { ; RV64IMB-LABEL: add_mul_combine_reject_f3: ; RV64IMB: # %bb.0: ; RV64IMB-NEXT: addi a0, a0, 1972 -; RV64IMB-NEXT: li a1, 29 -; RV64IMB-NEXT: mul a0, a0, a1 +; RV64IMB-NEXT: sh1add a1, a0, a0 +; RV64IMB-NEXT: slli a0, a0, 5 +; RV64IMB-NEXT: sub a0, a0, a1 ; RV64IMB-NEXT: addi a0, a0, 11 ; RV64IMB-NEXT: ret %tmp0 = mul i64 %x, 29 diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 080783fdeec0241082ae43e15a3b72eb545c66b4..141d5ea4182892d5cb0b1e6f7dd9ddcf779814a7 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -112,12 +112,12 @@ ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFMIN %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV32ZVFBFWMA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV32ZAAMO %s -; RUN: llc -mtriple=riscv32 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s +; RUN: llc -mtriple=riscv32 -mattr=+a,zacas %s -o - | FileCheck --check-prefix=RV32ZACAS %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV32ZALASR %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV32ZALRSC %s ; RUN: llc -mtriple=riscv32 -mattr=+zama16b %s -o - | FileCheck --check-prefixes=CHECK,RV32ZAMA16B %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV32ZICFILP %s -; RUN: llc -mtriple=riscv32 -mattr=+experimental-zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s ; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s @@ -244,11 +244,11 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfmin %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFMIN %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zvfbfwma %s -o - | FileCheck --check-prefixes=CHECK,RV64ZVFBFWMA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zaamo %s -o - | FileCheck --check-prefix=RV64ZAAMO %s -; RUN: llc -mtriple=riscv64 -mattr=+zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s +; RUN: llc -mtriple=riscv64 -mattr=+a,zacas %s -o - | FileCheck --check-prefix=RV64ZACAS %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalasr %s -o - | FileCheck --check-prefix=RV64ZALASR %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zalrsc %s -o - | FileCheck --check-prefix=RV64ZALRSC %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zicfilp %s -o - | FileCheck --check-prefix=RV64ZICFILP %s -; RUN: llc -mtriple=riscv64 -mattr=+experimental-zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s @@ -326,7 +326,7 @@ ; RV32XSFVFWMACCQQQ: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvl32b1p0_xsfvfwmaccqqq1p0" ; RV32XTHEADCMO: .attribute 5, "rv32i2p1_xtheadcmo1p0" ; RV32XTHEADCONDMOV: .attribute 5, "rv32i2p1_xtheadcondmov1p0" -; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0" +; RV32XTHEADFMEMIDX: .attribute 5, "rv32i2p1_xtheadfmemidx1p0" ; RV32XTHEADMAC: .attribute 5, "rv32i2p1_xtheadmac1p0" ; RV32XTHEADMEMIDX: .attribute 5, "rv32i2p1_xtheadmemidx1p0" ; RV32XTHEADMEMPAIR: .attribute 5, "rv32i2p1_xtheadmempair1p0" @@ -452,7 +452,7 @@ ; RV64XTHEADBS: .attribute 5, "rv64i2p1_xtheadbs1p0" ; RV64XTHEADCMO: .attribute 5, "rv64i2p1_xtheadcmo1p0" ; RV64XTHEADCONDMOV: .attribute 5, "rv64i2p1_xtheadcondmov1p0" -; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_xtheadfmemidx1p0" +; RV64XTHEADFMEMIDX: .attribute 5, "rv64i2p1_xtheadfmemidx1p0" ; RV64XTHEADMAC: .attribute 5, "rv64i2p1_xtheadmac1p0" ; RV64XTHEADMEMIDX: .attribute 5, "rv64i2p1_xtheadmemidx1p0" ; RV64XTHEADMEMPAIR: .attribute 5, "rv64i2p1_xtheadmempair1p0" diff --git a/llvm/test/CodeGen/RISCV/bitreverse-shift.ll b/llvm/test/CodeGen/RISCV/bitreverse-shift.ll index f29b16991726266d1f44e232fea49e67a9fa51c0..b0281ba7d2385401971f120b690a0ae37d43177a 100644 --- a/llvm/test/CodeGen/RISCV/bitreverse-shift.ll +++ b/llvm/test/CodeGen/RISCV/bitreverse-shift.ll @@ -4,7 +4,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+zbkb -verify-machineinstrs < %s \ ; RUN: | FileCheck %s -check-prefixes=RV64ZBKB -; TODO: These tests can be optmised +; TODO: These tests can be optimised ; fold (bitreverse(srl (bitreverse c), x)) -> (shl c, x) ; fold (bitreverse(shl (bitreverse c), x)) -> (srl c, x) diff --git a/llvm/test/CodeGen/RISCV/fixups-diff.ll b/llvm/test/CodeGen/RISCV/fixups-diff.ll index cc1c87b1fe377f6ff4abc542d8ccc33d0ba5f43e..84a7d18ed15068c9892f108c7634c501a0444dee 100644 --- a/llvm/test/CodeGen/RISCV/fixups-diff.ll +++ b/llvm/test/CodeGen/RISCV/fixups-diff.ll @@ -27,7 +27,7 @@ entry: ; CHECK: } ; CHECK: Section {{.*}} .rela.eh_frame { -; CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +; CHECK-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 ; CHECK-NEXT: } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/CodeGen/RISCV/pr89833.ll b/llvm/test/CodeGen/RISCV/pr89833.ll new file mode 100644 index 0000000000000000000000000000000000000000..54a985040e758ad960c302ef72b590ae8481ec2c --- /dev/null +++ b/llvm/test/CodeGen/RISCV/pr89833.ll @@ -0,0 +1,16 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=riscv64 -mattr=+v | FileCheck %s + +declare void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64(, ptr, i64, ) + +define void @test( %value, %mask) { +; CHECK-LABEL: test: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma +; CHECK-NEXT: vnsrl.wi v12, v8, 0 +; CHECK-NEXT: vse8.v v12, (zero), v0.t +; CHECK-NEXT: ret + %trunc = trunc %value to + call void @llvm.riscv.masked.strided.store.nxv16i8.p0.i64( %trunc, ptr null, i64 1, %mask) + ret void +} diff --git a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll index a1de326d16b536a27220b96f862c0f2ad0d478eb..1c794a1bd1684d8d691bd9adc3fbbeaf2dfa0498 100644 --- a/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/rv64-legal-i32/xaluo.ll @@ -810,9 +810,9 @@ define zeroext i1 @umulo2.i32(i32 signext %v1, ptr %res) { ; ; RV64ZBA-LABEL: umulo2.i32: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: zext.w a0, a0 -; RV64ZBA-NEXT: sh1add a2, a0, a0 -; RV64ZBA-NEXT: sh2add a2, a2, a0 +; RV64ZBA-NEXT: zext.w a2, a0 +; RV64ZBA-NEXT: sh1add.uw a0, a0, a2 +; RV64ZBA-NEXT: sh2add a2, a0, a2 ; RV64ZBA-NEXT: srli a0, a2, 32 ; RV64ZBA-NEXT: snez a0, a0 ; RV64ZBA-NEXT: sw a2, 0(a1) diff --git a/llvm/test/CodeGen/RISCV/rv64zba.ll b/llvm/test/CodeGen/RISCV/rv64zba.ll index 4eb493d642e85356e9813ebebfa345065fbb052f..0efc45b99289a7d104d80afa01d49e0410a59f73 100644 --- a/llvm/test/CodeGen/RISCV/rv64zba.ll +++ b/llvm/test/CodeGen/RISCV/rv64zba.ll @@ -641,31 +641,52 @@ define i64 @mul96(i64 %a) { } define i64 @mul119(i64 %a) { -; CHECK-LABEL: mul119: -; CHECK: # %bb.0: -; CHECK-NEXT: li a1, 119 -; CHECK-NEXT: mul a0, a0, a1 -; CHECK-NEXT: ret +; RV64I-LABEL: mul119: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 119 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: mul119: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh3add a1, a0, a0 +; RV64ZBA-NEXT: slli a0, a0, 7 +; RV64ZBA-NEXT: sub a0, a0, a1 +; RV64ZBA-NEXT: ret %c = mul i64 %a, 119 ret i64 %c } define i64 @mul123(i64 %a) { -; CHECK-LABEL: mul123: -; CHECK: # %bb.0: -; CHECK-NEXT: li a1, 123 -; CHECK-NEXT: mul a0, a0, a1 -; CHECK-NEXT: ret +; RV64I-LABEL: mul123: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 123 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: mul123: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh2add a1, a0, a0 +; RV64ZBA-NEXT: slli a0, a0, 7 +; RV64ZBA-NEXT: sub a0, a0, a1 +; RV64ZBA-NEXT: ret %c = mul i64 %a, 123 ret i64 %c } define i64 @mul125(i64 %a) { -; CHECK-LABEL: mul125: -; CHECK: # %bb.0: -; CHECK-NEXT: li a1, 125 -; CHECK-NEXT: mul a0, a0, a1 -; CHECK-NEXT: ret +; RV64I-LABEL: mul125: +; RV64I: # %bb.0: +; RV64I-NEXT: li a1, 125 +; RV64I-NEXT: mul a0, a0, a1 +; RV64I-NEXT: ret +; +; RV64ZBA-LABEL: mul125: +; RV64ZBA: # %bb.0: +; RV64ZBA-NEXT: sh1add a1, a0, a0 +; RV64ZBA-NEXT: slli a0, a0, 7 +; RV64ZBA-NEXT: sub a0, a0, a1 +; RV64ZBA-NEXT: ret %c = mul i64 %a, 125 ret i64 %c } diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll b/llvm/test/CodeGen/RISCV/rvv/commutable.ll new file mode 100644 index 0000000000000000000000000000000000000000..b59df3b743cd52febac3abc8fb75c02b4478ea8f --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll @@ -0,0 +1,651 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+f,+d,+zvfh,+v \ +; RUN: -verify-machineinstrs | FileCheck %s +; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+f,+d,+zvfh,+v \ +; RUN: -verify-machineinstrs | FileCheck %s + +; vadd.vv +declare @llvm.riscv.vadd.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vadd_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vadd_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vadd.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vadd.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vadd.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vadd_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vadd_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vadd.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vadd.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vand.vv +declare @llvm.riscv.vand.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vand_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vand_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vand.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vand.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vand.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vand.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vand_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vand_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vand.vv v10, v8, v9, v0.t +; CHECK-NEXT: vand.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vand.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vand.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vor.vv +declare @llvm.riscv.vor.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vor_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vor_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vor.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vor.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vor.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vor.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vor_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vor_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vor.vv v10, v8, v9, v0.t +; CHECK-NEXT: vor.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vor.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vor.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vxor.vv +declare @llvm.riscv.vxor.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vxor_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vxor_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vxor.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vxor.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vxor.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vxor.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vxor_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vxor_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vxor.vv v10, v8, v9, v0.t +; CHECK-NEXT: vxor.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vxor.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vxor.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vmseq.vv +declare @llvm.riscv.vmseq.nxv1i64(, , iXLen); +define @commutable_vmseq_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmseq_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmseq.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-NEXT: vmxor.mm v0, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmseq.nxv1i64( %0, %1, iXLen %2) + %b = call @llvm.riscv.vmseq.nxv1i64( %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmseq.mask.nxv1i64(, , , , iXLen); +define @commutable_vmseq_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmseq_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmseq.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmseq.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-NEXT: vmxor.mm v0, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmseq.mask.nxv1i64( undef, %0, %1, %mask, iXLen %2) + %b = call @llvm.riscv.vmseq.mask.nxv1i64( undef, %1, %0, %mask, iXLen %2) + %ret = add %a, %b + ret %ret +} + +; vmsne.vv +declare @llvm.riscv.vmsne.nxv1i64(, , iXLen); +define @commutable_vmsne_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmsne_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmsne.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-NEXT: vmxor.mm v0, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmsne.nxv1i64( %0, %1, iXLen %2) + %b = call @llvm.riscv.vmsne.nxv1i64( %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmsne.mask.nxv1i64(, , , , iXLen); +define @commutable_vmsne_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmsne_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmsne.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmsne.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma +; CHECK-NEXT: vmxor.mm v0, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmsne.mask.nxv1i64( undef, %0, %1, %mask, iXLen %2) + %b = call @llvm.riscv.vmsne.mask.nxv1i64( undef, %1, %0, %mask, iXLen %2) + %ret = add %a, %b + ret %ret +} + +; vmin.vv +declare @llvm.riscv.vmin.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vmin_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmin_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmin.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmin.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vmin.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmin.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vmin_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmin_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmin.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmin.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmin.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vmin.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vminu.vv +declare @llvm.riscv.vminu.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vminu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vminu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vminu.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vminu.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vminu.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vminu.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vminu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vminu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vminu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vminu.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vminu.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vminu.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vmax.vv +declare @llvm.riscv.vmax.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vmax_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmax_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmax.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmax.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vmax.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmax.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vmax_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmax_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmax.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmax.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmax.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vmax.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vmaxu.vv +declare @llvm.riscv.vmaxu.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vmaxu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmaxu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmaxu.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmaxu.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vmaxu.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmaxu.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vmaxu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmaxu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmaxu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmaxu.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmaxu.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vmaxu.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vmul.vv +declare @llvm.riscv.vmul.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vmul_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmul_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmul.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmul.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vmul.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmul.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vmul_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmul_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmul.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmul.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmul.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vmul.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vmulh.vv +declare @llvm.riscv.vmulh.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vmulh_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmulh_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmulh.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmulh.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vmulh.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vmulh_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmulh_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmulh.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmulh.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vmulh.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vmulhu.vv +declare @llvm.riscv.vmulhu.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vmulhu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vmulhu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmulhu.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vmulhu.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vmulhu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vmulhu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vmulhu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vmulhu.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vmulhu.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vwadd.vv +declare @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32(, , , iXLen); +define @commutable_vwadd_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vwadd_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vwadd.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.nxv1i32(, , , , iXLen, iXLen); +define @commutable_vwadd_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vwadd_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vwadd.vv v11, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v11 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwadd.mask.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vwaddu.vv +declare @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32(, , , iXLen); +define @commutable_vwaddu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vwaddu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vwaddu.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32(, , , , iXLen, iXLen); +define @commutable_vwaddu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vwaddu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwaddu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vwaddu.vv v11, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v11 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwaddu.mask.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vwmul.vv +declare @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32(, , , iXLen); +define @commutable_vwmul_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vwmul_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmul.vv v10, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vwmul.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32(, , , , iXLen, iXLen); +define @commutable_vwmul_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vwmul_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmul.vv v10, v8, v9, v0.t +; CHECK-NEXT: vwmul.vv v11, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v11 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwmul.mask.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vwmulu.vv +declare @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32(, , , iXLen); +define @commutable_vwmulu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vwmulu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmulu.vv v10, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vwmulu.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.nxv1i32(, , , , iXLen, iXLen); +define @commutable_vwmulu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vwmulu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmulu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vwmulu.vv v11, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v11 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.nxv1i32( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwmulu.mask.nxv1i64.nxv1i32.nxv1i32( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vwmacc.vv +declare @llvm.riscv.vwmacc.nxv1i64.nxv1i32(, , , iXLen, iXLen); +define @commutable_vwmacc_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vwmacc_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmacc.vv v10, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vwmacc.nxv1i64.nxv1i32( undef, %0, %1, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwmacc.nxv1i64.nxv1i32( undef, %1, %0, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32(, , , , iXLen, iXLen); +define @commutable_vwmacc_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vwmacc_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmacc.vv v10, v8, v9, v0.t +; CHECK-NEXT: vwmacc.vv v11, v9, v8, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v11 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwmacc.mask.nxv1i64.nxv1i32( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vwmaccu.vv +declare @llvm.riscv.vwmaccu.nxv1i64.nxv1i32(, , , iXLen, iXLen); +define @commutable_vwmaccu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vwmaccu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmaccu.vv v10, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v10 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( undef, %0, %1, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwmaccu.nxv1i64.nxv1i32( undef, %1, %0, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32(, , , , iXLen, iXLen); +define @commutable_vwmaccu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vwmaccu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma +; CHECK-NEXT: vwmaccu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vwmaccu.vv v11, v9, v8, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v11 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vwmaccu.mask.nxv1i64.nxv1i32( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vadc.vvm +declare @llvm.riscv.vadc.nxv1i64.nxv1i64(, , , , iXLen); +define @commutable_vadc_vv( %0, %1, %mask, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vadc_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vadc.vvm v10, v8, v9, v0 +; CHECK-NEXT: vadc.vvm v8, v8, v9, v0 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vadc.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2) + %b = call @llvm.riscv.vadc.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2) + %ret = add %a, %b + ret %ret +} + diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll index 8e214e40547832d49e151e6b5ee82dcba12803c6..9e83efd351953921358bb78ae9f38ed87b46ae8f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-buildvec.ll @@ -1407,8 +1407,8 @@ define <8 x float> @buildvec_v8f32_zvl256(float %e0, float %e1, float %e2, float ; CHECK-NEXT: vfmv.v.f v8, fa4 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa5 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa6 -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa7 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t ; CHECK-NEXT: ret %v0 = insertelement <8 x float> poison, float %e0, i64 0 @@ -1458,8 +1458,8 @@ define <8 x double> @buildvec_v8f64_zvl512(double %e0, double %e1, double %e2, d ; CHECK-NEXT: vfmv.v.f v8, fa4 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa5 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa6 -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vfslide1down.vf v8, v8, fa7 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t ; CHECK-NEXT: ret %v0 = insertelement <8 x double> poison, double %e0, i64 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll index 6bfd0ac932672f51793b7b64eca7b46f0122eafd..ed152e64a91ef49dd2661d803d01e12f1b9be750 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp-interleave.ll @@ -57,8 +57,8 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) { ; RV32-V512-NEXT: vid.v v10 ; RV32-V512-NEXT: vsrl.vi v11, v10, 1 ; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV32-V512-NEXT: vmv.v.i v0, 10 ; RV32-V512-NEXT: vrgatherei16.vv v10, v8, v11 +; RV32-V512-NEXT: vmv.v.i v0, 10 ; RV32-V512-NEXT: vrgatherei16.vv v10, v9, v11, v0.t ; RV32-V512-NEXT: vmv.v.v v8, v10 ; RV32-V512-NEXT: ret @@ -68,8 +68,8 @@ define <4 x double> @interleave_v2f64(<2 x double> %x, <2 x double> %y) { ; RV64-V512-NEXT: vsetivli zero, 4, e64, m1, ta, mu ; RV64-V512-NEXT: vid.v v10 ; RV64-V512-NEXT: vsrl.vi v11, v10, 1 -; RV64-V512-NEXT: vmv.v.i v0, 10 ; RV64-V512-NEXT: vrgather.vv v10, v8, v11 +; RV64-V512-NEXT: vmv.v.i v0, 10 ; RV64-V512-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV64-V512-NEXT: vmv.v.v v8, v10 ; RV64-V512-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll index 85b849045e8ceecdcf7f000d162ee2b97cd8dd67..a8e4af2d7368e885d234890aac3e41eee5ccdfde 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp2i-sat.ll @@ -395,8 +395,8 @@ define void @fp2si_v8f64_v8i8(ptr %x, ptr %y) { ; RV32-NEXT: fmin.d fa5, fa5, fa4 ; RV32-NEXT: fcvt.w.d a2, fa5, rtz ; RV32-NEXT: and a0, a0, a2 -; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vslide1down.vx v9, v9, a0 +; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vslidedown.vi v9, v8, 4, v0.t ; RV32-NEXT: vse8.v v9, (a1) ; RV32-NEXT: addi sp, s0, -128 @@ -496,8 +496,8 @@ define void @fp2si_v8f64_v8i8(ptr %x, ptr %y) { ; RV64-NEXT: fmin.d fa5, fa5, fa4 ; RV64-NEXT: fcvt.l.d a2, fa5, rtz ; RV64-NEXT: and a0, a0, a2 -; RV64-NEXT: vmv.v.i v0, 15 ; RV64-NEXT: vslide1down.vx v9, v9, a0 +; RV64-NEXT: vmv.v.i v0, 15 ; RV64-NEXT: vslidedown.vi v9, v8, 4, v0.t ; RV64-NEXT: vse8.v v9, (a1) ; RV64-NEXT: addi sp, s0, -128 @@ -580,8 +580,8 @@ define void @fp2ui_v8f64_v8i8(ptr %x, ptr %y) { ; RV32-NEXT: fmax.d fa4, fa4, fa3 ; RV32-NEXT: fmin.d fa5, fa4, fa5 ; RV32-NEXT: fcvt.wu.d a0, fa5, rtz -; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vslide1down.vx v9, v9, a0 +; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vslidedown.vi v9, v8, 4, v0.t ; RV32-NEXT: vse8.v v9, (a1) ; RV32-NEXT: addi sp, s0, -128 @@ -656,8 +656,8 @@ define void @fp2ui_v8f64_v8i8(ptr %x, ptr %y) { ; RV64-NEXT: fmax.d fa4, fa4, fa3 ; RV64-NEXT: fmin.d fa5, fa4, fa5 ; RV64-NEXT: fcvt.lu.d a0, fa5, rtz -; RV64-NEXT: vmv.v.i v0, 15 ; RV64-NEXT: vslide1down.vx v9, v9, a0 +; RV64-NEXT: vmv.v.i v0, 15 ; RV64-NEXT: vslidedown.vi v9, v8, 4, v0.t ; RV64-NEXT: vse8.v v9, (a1) ; RV64-NEXT: addi sp, s0, -128 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll index 6da83644413bc2e9e7932ab20d853351edf6119d..40ff8b50d99d8d58f512dd09b5a41b70d3444209 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-interleave.ll @@ -70,8 +70,8 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) { ; RV32-V512-NEXT: vid.v v10 ; RV32-V512-NEXT: vsrl.vi v11, v10, 1 ; RV32-V512-NEXT: vsetvli zero, zero, e64, m1, ta, mu -; RV32-V512-NEXT: vmv.v.i v0, 10 ; RV32-V512-NEXT: vrgatherei16.vv v10, v8, v11 +; RV32-V512-NEXT: vmv.v.i v0, 10 ; RV32-V512-NEXT: vrgatherei16.vv v10, v9, v11, v0.t ; RV32-V512-NEXT: vmv.v.v v8, v10 ; RV32-V512-NEXT: ret @@ -81,8 +81,8 @@ define <4 x i64> @interleave_v2i64(<2 x i64> %x, <2 x i64> %y) { ; RV64-V512-NEXT: vsetivli zero, 4, e64, m1, ta, mu ; RV64-V512-NEXT: vid.v v10 ; RV64-V512-NEXT: vsrl.vi v11, v10, 1 -; RV64-V512-NEXT: vmv.v.i v0, 10 ; RV64-V512-NEXT: vrgather.vv v10, v8, v11 +; RV64-V512-NEXT: vmv.v.i v0, 10 ; RV64-V512-NEXT: vrgather.vv v10, v9, v11, v0.t ; RV64-V512-NEXT: vmv.v.v v8, v10 ; RV64-V512-NEXT: ret @@ -195,8 +195,8 @@ define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) { ; V128-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; V128-NEXT: vid.v v8 ; V128-NEXT: vsrl.vi v8, v8, 1 -; V128-NEXT: vmv.v.i v0, 10 ; V128-NEXT: vadd.vi v8, v8, 1 +; V128-NEXT: vmv.v.i v0, 10 ; V128-NEXT: vrgather.vv v10, v9, v8, v0.t ; V128-NEXT: vmv.v.v v8, v10 ; V128-NEXT: ret @@ -210,8 +210,8 @@ define <4 x i32> @interleave_v4i32_offset_1(<4 x i32> %x, <4 x i32> %y) { ; V512-NEXT: vsetivli zero, 4, e32, mf2, ta, mu ; V512-NEXT: vid.v v8 ; V512-NEXT: vsrl.vi v8, v8, 1 -; V512-NEXT: vmv.v.i v0, 10 ; V512-NEXT: vadd.vi v8, v8, 1 +; V512-NEXT: vmv.v.i v0, 10 ; V512-NEXT: vrgather.vv v10, v9, v8, v0.t ; V512-NEXT: vmv1r.v v8, v10 ; V512-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll index 0e8d9cf030669064fe98cfc913deee35fc60915c..58af6ac246d1619e1ae8c1e0923f73f216e920f6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll @@ -89,8 +89,8 @@ define <4 x i16> @vrgather_shuffle_vv_v4i16(<4 x i16> %x, <4 x i16> %y) { ; CHECK-NEXT: addi a0, a0, %lo(.LCPI6_0) ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, mu ; CHECK-NEXT: vle16.v v11, (a0) -; CHECK-NEXT: vmv.v.i v0, 8 ; CHECK-NEXT: vrgather.vv v10, v8, v11 +; CHECK-NEXT: vmv.v.i v0, 8 ; CHECK-NEXT: vrgather.vi v10, v9, 1, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -162,16 +162,16 @@ define <8 x i64> @vrgather_shuffle_vv_v8i64(<8 x i64> %x, <8 x i64> %y) { ; RV32: # %bb.0: ; RV32-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; RV32-NEXT: vmv.v.i v16, 2 -; RV32-NEXT: li a0, 5 -; RV32-NEXT: vslide1down.vx v20, v16, a0 ; RV32-NEXT: lui a0, %hi(.LCPI11_0) ; RV32-NEXT: addi a0, a0, %lo(.LCPI11_0) -; RV32-NEXT: vle16.v v21, (a0) +; RV32-NEXT: vle16.v v20, (a0) +; RV32-NEXT: li a0, 5 +; RV32-NEXT: vslide1down.vx v21, v16, a0 ; RV32-NEXT: vsetvli zero, zero, e64, m4, ta, mu +; RV32-NEXT: vrgatherei16.vv v16, v8, v20 ; RV32-NEXT: li a0, 164 ; RV32-NEXT: vmv.s.x v0, a0 -; RV32-NEXT: vrgatherei16.vv v16, v8, v21 -; RV32-NEXT: vrgatherei16.vv v16, v12, v20, v0.t +; RV32-NEXT: vrgatherei16.vv v16, v12, v21, v0.t ; RV32-NEXT: vmv.v.v v8, v16 ; RV32-NEXT: ret ; @@ -210,13 +210,13 @@ define <8 x i64> @vrgather_shuffle_xv_v8i64(<8 x i64> %x) { ; RV32-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: vmv.v.i v20, -1 +; RV32-NEXT: vrgatherei16.vv v12, v20, v16 ; RV32-NEXT: lui a0, %hi(.LCPI12_1) ; RV32-NEXT: addi a0, a0, %lo(.LCPI12_1) -; RV32-NEXT: vle16.v v17, (a0) +; RV32-NEXT: vle16.v v16, (a0) ; RV32-NEXT: li a0, 113 ; RV32-NEXT: vmv.s.x v0, a0 -; RV32-NEXT: vrgatherei16.vv v12, v20, v16 -; RV32-NEXT: vrgatherei16.vv v12, v8, v17, v0.t +; RV32-NEXT: vrgatherei16.vv v12, v8, v16, v0.t ; RV32-NEXT: vmv.v.v v8, v12 ; RV32-NEXT: ret ; @@ -368,9 +368,9 @@ define <8 x i8> @splat_ve2_we0(<8 x i8> %v, <8 x i8> %w) { ; CHECK-LABEL: splat_ve2_we0: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu +; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: li a0, 66 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -387,9 +387,9 @@ define <8 x i8> @splat_ve2_we0_ins_i0ve4(<8 x i8> %v, <8 x i8> %w) { ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, tu, ma ; CHECK-NEXT: vmv.s.x v11, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, mu +; CHECK-NEXT: vrgather.vv v10, v8, v11 ; CHECK-NEXT: li a0, 66 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vrgather.vv v10, v8, v11 ; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -422,9 +422,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4(<8 x i8> %v, <8 x i8> %w) { ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vmv.v.x v11, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu +; CHECK-NEXT: vrgather.vv v10, v8, v11 ; CHECK-NEXT: li a0, 66 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vrgather.vv v10, v8, v11 ; CHECK-NEXT: vrgather.vi v10, v9, 0, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -441,9 +441,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2we4(<8 x i8> %v, <8 x i8> %w) { ; CHECK-NEXT: vsetivli zero, 3, e8, mf2, tu, ma ; CHECK-NEXT: vslideup.vi v11, v10, 2 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu +; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: li a0, 70 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vrgather.vi v10, v8, 2 ; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -464,9 +464,9 @@ define <8 x i8> @splat_ve2_we0_ins_i2ve4_i5we6(<8 x i8> %v, <8 x i8> %w) { ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vmv.v.x v12, a0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu +; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: li a0, 98 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vrgather.vv v10, v9, v11, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -681,9 +681,9 @@ define <8 x i8> @merge_non_contiguous_slideup_slidedown(<8 x i8> %v, <8 x i8> %w ; CHECK-LABEL: merge_non_contiguous_slideup_slidedown: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu +; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: li a0, 234 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vslideup.vi v8, v9, 1, v0.t ; CHECK-NEXT: ret %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> @@ -695,12 +695,12 @@ define <8 x i8> @unmergable(<8 x i8> %v, <8 x i8> %w) { ; CHECK-LABEL: unmergable: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, mu +; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: lui a0, %hi(.LCPI46_0) ; CHECK-NEXT: addi a0, a0, %lo(.LCPI46_0) ; CHECK-NEXT: vle8.v v10, (a0) ; CHECK-NEXT: li a0, 234 ; CHECK-NEXT: vmv.s.x v0, a0 -; CHECK-NEXT: vslidedown.vi v8, v8, 2 ; CHECK-NEXT: vrgather.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret %res = shufflevector <8 x i8> %v, <8 x i8> %w, <8 x i32> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll index f98cb343a2ab429bc6c2ba485f7eac464950f946..99364264de8293b2aac7a74474749334765b18e8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleaved-access.ll @@ -159,16 +159,17 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: addi sp, sp, -16 ; RV32-NEXT: .cfi_def_cfa_offset 16 ; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: li a3, 56 +; RV32-NEXT: li a3, 54 ; RV32-NEXT: mul a2, a2, a3 ; RV32-NEXT: sub sp, sp, a2 -; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb +; RV32-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x36, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 54 * vlenb ; RV32-NEXT: addi a3, a1, 256 ; RV32-NEXT: li a2, 32 ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, ma ; RV32-NEXT: vle32.v v16, (a3) ; RV32-NEXT: csrr a3, vlenb -; RV32-NEXT: slli a3, a3, 5 +; RV32-NEXT: li a4, 21 +; RV32-NEXT: mul a3, a3, a4 ; RV32-NEXT: add a3, sp, a3 ; RV32-NEXT: addi a3, a3, 16 ; RV32-NEXT: vs8r.v v16, (a3) # Unknown-size Folded Spill @@ -176,31 +177,30 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vslideup.vi v8, v16, 4 ; RV32-NEXT: csrr a4, vlenb -; RV32-NEXT: slli a4, a4, 4 +; RV32-NEXT: slli a5, a4, 3 +; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: vs4r.v v8, (a4) # Unknown-size Folded Spill ; RV32-NEXT: lui a4, 12 -; RV32-NEXT: vmv.s.x v3, a4 +; RV32-NEXT: vmv.s.x v0, a4 +; RV32-NEXT: csrr a4, vlenb +; RV32-NEXT: add a4, sp, a4 +; RV32-NEXT: addi a4, a4, 16 +; RV32-NEXT: vs1r.v v0, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 16, e32, m8, ta, ma ; RV32-NEXT: vslidedown.vi v16, v16, 16 ; RV32-NEXT: csrr a4, vlenb -; RV32-NEXT: li a5, 24 +; RV32-NEXT: li a5, 37 ; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: vs8r.v v16, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV32-NEXT: vmv1r.v v0, v3 -; RV32-NEXT: csrr a4, vlenb -; RV32-NEXT: slli a4, a4, 2 -; RV32-NEXT: add a4, sp, a4 -; RV32-NEXT: addi a4, a4, 16 -; RV32-NEXT: vs1r.v v3, (a4) # Unknown-size Folded Spill ; RV32-NEXT: vslideup.vi v8, v16, 10, v0.t ; RV32-NEXT: csrr a4, vlenb -; RV32-NEXT: li a5, 20 -; RV32-NEXT: mul a4, a4, a5 +; RV32-NEXT: slli a5, a4, 4 +; RV32-NEXT: add a4, a5, a4 ; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: vs4r.v v8, (a4) # Unknown-size Folded Spill @@ -209,71 +209,82 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu ; RV32-NEXT: vle16.v v8, (a4) ; RV32-NEXT: csrr a4, vlenb -; RV32-NEXT: slli a4, a4, 3 +; RV32-NEXT: li a5, 13 +; RV32-NEXT: mul a4, a4, a5 ; RV32-NEXT: add a4, sp, a4 ; RV32-NEXT: addi a4, a4, 16 ; RV32-NEXT: vs4r.v v8, (a4) # Unknown-size Folded Spill -; RV32-NEXT: lui a4, %hi(.LCPI6_1) -; RV32-NEXT: addi a4, a4, %lo(.LCPI6_1) -; RV32-NEXT: lui a5, 1 -; RV32-NEXT: vle16.v v8, (a4) -; RV32-NEXT: addi a4, sp, 16 -; RV32-NEXT: vs4r.v v8, (a4) # Unknown-size Folded Spill -; RV32-NEXT: vle32.v v16, (a1) +; RV32-NEXT: vle32.v v24, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a4, 40 +; RV32-NEXT: li a4, 45 ; RV32-NEXT: mul a1, a1, a4 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill -; RV32-NEXT: vle32.v v24, (a3) +; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, %hi(.LCPI6_1) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_1) +; RV32-NEXT: lui a4, 1 +; RV32-NEXT: addi a4, a4, -64 +; RV32-NEXT: vle16.v v8, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 48 -; RV32-NEXT: mul a1, a1, a3 +; RV32-NEXT: slli a5, a1, 2 +; RV32-NEXT: add a1, a5, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill -; RV32-NEXT: addi a1, a5, -64 -; RV32-NEXT: vmv.s.x v0, a1 +; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vle32.v v16, (a3) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 12 +; RV32-NEXT: li a3, 29 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vmv.s.x v2, a4 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: li a3, 13 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v4, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v16, v4 -; RV32-NEXT: addi a1, sp, 16 -; RV32-NEXT: vl4r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v24, v16, v0.t +; RV32-NEXT: vrgatherei16.vv v8, v24, v4 +; RV32-NEXT: vmv1r.v v0, v2 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: slli a3, a1, 2 +; RV32-NEXT: add a1, a3, a1 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 20 -; RV32-NEXT: mul a1, a1, a3 +; RV32-NEXT: slli a3, a1, 4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vmv.v.v v12, v8 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 20 -; RV32-NEXT: mul a1, a1, a3 +; RV32-NEXT: slli a3, a1, 4 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 5 +; RV32-NEXT: li a3, 21 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vmv4r.v v16, v8 ; RV32-NEXT: vslideup.vi v8, v16, 2 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vl1r.v v3, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vmv1r.v v0, v3 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 24 +; RV32-NEXT: li a3, 37 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 @@ -283,36 +294,45 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: lui a1, %hi(.LCPI6_2) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_2) ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; RV32-NEXT: lui a3, %hi(.LCPI6_3) -; RV32-NEXT: addi a3, a3, %lo(.LCPI6_3) -; RV32-NEXT: vle16.v v24, (a1) -; RV32-NEXT: vle16.v v8, (a3) +; RV32-NEXT: vle16.v v8, (a1) +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: li a3, 13 +; RV32-NEXT: mul a1, a1, a3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, %hi(.LCPI6_3) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_3) +; RV32-NEXT: vle16.v v8, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: slli a3, a1, 2 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 40 +; RV32-NEXT: li a3, 45 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v0, v24 +; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 12 +; RV32-NEXT: li a3, 13 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vl4r.v v4, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vrgatherei16.vv v8, v24, v4 +; RV32-NEXT: vmv1r.v v0, v2 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 48 +; RV32-NEXT: li a3, 29 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: slli a3, a1, 2 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v4, (a1) # Unknown-size Folded Reload @@ -320,8 +340,8 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: vsetivli zero, 12, e32, m4, tu, ma ; RV32-NEXT: vmv.v.v v20, v8 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 12 -; RV32-NEXT: mul a1, a1, a3 +; RV32-NEXT: slli a3, a1, 2 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill @@ -330,171 +350,178 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vle16.v v8, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 5 +; RV32-NEXT: li a3, 21 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vrgatherei16.vv v12, v24, v8 +; RV32-NEXT: vmv1r.v v0, v3 +; RV32-NEXT: vslideup.vi v12, v16, 6, v0.t ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 2 +; RV32-NEXT: li a3, 13 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl1r.v v3, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vmv1r.v v0, v3 -; RV32-NEXT: vslideup.vi v12, v16, 6, v0.t -; RV32-NEXT: vmv.v.v v4, v12 +; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV32-NEXT: lui a1, %hi(.LCPI6_5) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_5) ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; RV32-NEXT: lui a3, %hi(.LCPI6_6) -; RV32-NEXT: addi a3, a3, %lo(.LCPI6_6) ; RV32-NEXT: vle16.v v24, (a1) -; RV32-NEXT: vle16.v v8, (a3) -; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 3 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill -; RV32-NEXT: li a1, 960 -; RV32-NEXT: vmv.s.x v2, a1 +; RV32-NEXT: lui a1, %hi(.LCPI6_6) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_6) +; RV32-NEXT: li a3, 960 +; RV32-NEXT: vle16.v v4, (a1) +; RV32-NEXT: vmv.s.x v0, a3 +; RV32-NEXT: addi a1, sp, 16 +; RV32-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 40 +; RV32-NEXT: li a3, 45 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vrgatherei16.vv v8, v16, v24 -; RV32-NEXT: vmv1r.v v0, v2 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 48 +; RV32-NEXT: li a3, 29 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vrgatherei16.vv v8, v24, v4, v0.t +; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: li a3, 13 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl4r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v24, v16, v0.t -; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma -; RV32-NEXT: vmv.v.v v4, v8 +; RV32-NEXT: vl4r.v v12, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vmv.v.v v12, v8 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 3 +; RV32-NEXT: li a3, 13 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill +; RV32-NEXT: vs4r.v v12, (a1) # Unknown-size Folded Spill ; RV32-NEXT: lui a1, %hi(.LCPI6_7) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_7) ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vle16.v v8, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 5 +; RV32-NEXT: li a3, 21 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v28, v24, v8 +; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vrgatherei16.vv v4, v16, v8 ; RV32-NEXT: vmv1r.v v0, v3 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 24 +; RV32-NEXT: li a3, 37 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vslideup.vi v28, v8, 4, v0.t -; RV32-NEXT: vmv.v.v v4, v28 +; RV32-NEXT: vslideup.vi v4, v8, 4, v0.t ; RV32-NEXT: lui a1, %hi(.LCPI6_8) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_8) ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; RV32-NEXT: lui a3, %hi(.LCPI6_9) -; RV32-NEXT: addi a3, a3, %lo(.LCPI6_9) -; RV32-NEXT: vle16.v v28, (a1) -; RV32-NEXT: vle16.v v24, (a3) +; RV32-NEXT: vle16.v v0, (a1) +; RV32-NEXT: lui a1, %hi(.LCPI6_9) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_9) +; RV32-NEXT: vle16.v v8, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 40 -; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v16, v28 -; RV32-NEXT: vmv1r.v v0, v2 +; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 48 +; RV32-NEXT: li a3, 45 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v16, v24, v0.t +; RV32-NEXT: vrgatherei16.vv v8, v16, v0 +; RV32-NEXT: addi a1, sp, 16 +; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vl4r.v v16, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vrgatherei16.vv v8, v24, v16, v0.t ; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma ; RV32-NEXT: vmv.v.v v4, v8 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 2 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu -; RV32-NEXT: lui a1, %hi(.LCPI6_10) -; RV32-NEXT: addi a1, a1, %lo(.LCPI6_10) -; RV32-NEXT: vle16.v v4, (a1) -; RV32-NEXT: lui a1, 15 -; RV32-NEXT: vmv.s.x v6, a1 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 5 +; RV32-NEXT: li a3, 21 +; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vslideup.vi v28, v24, 6 -; RV32-NEXT: vmv1r.v v0, v6 +; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vslideup.vi v12, v8, 6 +; RV32-NEXT: lui a1, %hi(.LCPI6_10) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_10) +; RV32-NEXT: vle16.v v8, (a1) +; RV32-NEXT: lui a1, 15 +; RV32-NEXT: vmv.s.x v24, a1 +; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 24 +; RV32-NEXT: li a3, 37 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v28, v8, v4, v0.t +; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV32-NEXT: vrgatherei16.vv v12, v16, v8, v0.t +; RV32-NEXT: vmv.v.v v28, v12 ; RV32-NEXT: lui a1, %hi(.LCPI6_11) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_11) ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; RV32-NEXT: lui a3, %hi(.LCPI6_12) -; RV32-NEXT: addi a3, a3, %lo(.LCPI6_12) ; RV32-NEXT: vle16.v v0, (a1) -; RV32-NEXT: vle16.v v24, (a3) -; RV32-NEXT: li a1, 1008 -; RV32-NEXT: vmv.s.x v7, a1 -; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 5 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs1r.v v7, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, %hi(.LCPI6_12) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_12) +; RV32-NEXT: li a3, 1008 +; RV32-NEXT: vle16.v v4, (a1) +; RV32-NEXT: vmv.s.x v25, a3 +; RV32-NEXT: addi a1, sp, 16 +; RV32-NEXT: vs1r.v v25, (a1) # Unknown-size Folded Spill ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 40 +; RV32-NEXT: li a3, 45 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vrgatherei16.vv v8, v16, v0 -; RV32-NEXT: vmv1r.v v0, v7 +; RV32-NEXT: vmv1r.v v0, v25 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 48 +; RV32-NEXT: li a3, 29 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v16, v24, v0.t +; RV32-NEXT: vrgatherei16.vv v8, v16, v4, v0.t ; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma ; RV32-NEXT: vmv.v.v v28, v8 +; RV32-NEXT: csrr a1, vlenb +; RV32-NEXT: li a3, 21 +; RV32-NEXT: mul a1, a1, a3 +; RV32-NEXT: add a1, sp, a1 +; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: vs4r.v v28, (a1) # Unknown-size Folded Spill ; RV32-NEXT: lui a1, %hi(.LCPI6_13) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_13) ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, mu ; RV32-NEXT: vle16.v v8, (a1) -; RV32-NEXT: vmv1r.v v0, v6 +; RV32-NEXT: vmv1r.v v0, v24 ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 4 +; RV32-NEXT: slli a3, a1, 3 +; RV32-NEXT: add a1, a3, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v24, (a1) # Unknown-size Folded Reload ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a3, 24 +; RV32-NEXT: li a3, 37 ; RV32-NEXT: mul a1, a1, a3 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 @@ -503,79 +530,70 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV32-NEXT: lui a1, %hi(.LCPI6_14) ; RV32-NEXT: addi a1, a1, %lo(.LCPI6_14) ; RV32-NEXT: vsetvli zero, a2, e32, m8, ta, mu -; RV32-NEXT: lui a2, %hi(.LCPI6_15) -; RV32-NEXT: addi a2, a2, %lo(.LCPI6_15) ; RV32-NEXT: vle16.v v16, (a1) -; RV32-NEXT: vle16.v v8, (a2) -; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a2, 24 -; RV32-NEXT: mul a1, a1, a2 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vs4r.v v8, (a1) # Unknown-size Folded Spill +; RV32-NEXT: lui a1, %hi(.LCPI6_15) +; RV32-NEXT: addi a1, a1, %lo(.LCPI6_15) +; RV32-NEXT: vle16.v v28, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a2, 40 +; RV32-NEXT: li a2, 45 ; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vrgatherei16.vv v8, v0, v16 -; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: slli a1, a1, 5 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: addi a1, a1, 16 +; RV32-NEXT: addi a1, sp, 16 ; RV32-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a2, 48 +; RV32-NEXT: li a2, 29 ; RV32-NEXT: mul a1, a1, a2 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a2, 24 -; RV32-NEXT: mul a1, a1, a2 -; RV32-NEXT: add a1, sp, a1 -; RV32-NEXT: addi a1, a1, 16 -; RV32-NEXT: vl4r.v v4, (a1) # Unknown-size Folded Reload -; RV32-NEXT: vrgatherei16.vv v8, v16, v4, v0.t +; RV32-NEXT: vrgatherei16.vv v8, v16, v28, v0.t ; RV32-NEXT: vsetivli zero, 10, e32, m4, tu, ma ; RV32-NEXT: vmv.v.v v24, v8 ; RV32-NEXT: addi a1, a0, 320 ; RV32-NEXT: vsetivli zero, 16, e32, m4, ta, ma ; RV32-NEXT: vse32.v v24, (a1) ; RV32-NEXT: addi a1, a0, 256 -; RV32-NEXT: vse32.v v28, (a1) +; RV32-NEXT: csrr a2, vlenb +; RV32-NEXT: li a3, 21 +; RV32-NEXT: mul a2, a2, a3 +; RV32-NEXT: add a2, sp, a2 +; RV32-NEXT: addi a2, a2, 16 +; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload +; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: addi a1, a0, 192 ; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: slli a2, a2, 2 ; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: addi a1, a0, 128 ; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: slli a2, a2, 3 +; RV32-NEXT: li a3, 13 +; RV32-NEXT: mul a2, a2, a3 ; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: addi a1, a0, 64 ; RV32-NEXT: csrr a2, vlenb -; RV32-NEXT: li a3, 12 -; RV32-NEXT: mul a2, a2, a3 +; RV32-NEXT: slli a3, a2, 2 +; RV32-NEXT: add a2, a3, a2 ; RV32-NEXT: add a2, sp, a2 ; RV32-NEXT: addi a2, a2, 16 ; RV32-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV32-NEXT: vse32.v v8, (a1) ; RV32-NEXT: csrr a1, vlenb -; RV32-NEXT: li a2, 20 -; RV32-NEXT: mul a1, a1, a2 +; RV32-NEXT: slli a2, a1, 4 +; RV32-NEXT: add a1, a2, a1 ; RV32-NEXT: add a1, sp, a1 ; RV32-NEXT: addi a1, a1, 16 ; RV32-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV32-NEXT: vse32.v v8, (a0) ; RV32-NEXT: csrr a0, vlenb -; RV32-NEXT: li a1, 56 +; RV32-NEXT: li a1, 54 ; RV32-NEXT: mul a0, a0, a1 ; RV32-NEXT: add sp, sp, a0 ; RV32-NEXT: addi sp, sp, 16 @@ -586,320 +604,324 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV64-NEXT: addi sp, sp, -16 ; RV64-NEXT: .cfi_def_cfa_offset 16 ; RV64-NEXT: csrr a2, vlenb -; RV64-NEXT: li a3, 52 +; RV64-NEXT: li a3, 56 ; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: sub sp, sp, a2 -; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x34, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 52 * vlenb +; RV64-NEXT: .cfi_escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x38, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 # sp + 16 + 56 * vlenb ; RV64-NEXT: vsetivli zero, 16, e64, m8, ta, ma ; RV64-NEXT: addi a2, a1, 256 ; RV64-NEXT: vle64.v v16, (a2) ; RV64-NEXT: csrr a2, vlenb -; RV64-NEXT: li a3, 27 -; RV64-NEXT: mul a2, a2, a3 +; RV64-NEXT: slli a2, a2, 5 ; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: vs8r.v v16, (a2) # Unknown-size Folded Spill ; RV64-NEXT: addi a2, a1, 128 ; RV64-NEXT: vle64.v v8, (a2) ; RV64-NEXT: csrr a2, vlenb -; RV64-NEXT: li a3, 35 +; RV64-NEXT: li a3, 40 ; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: vs8r.v v8, (a2) # Unknown-size Folded Spill -; RV64-NEXT: vle64.v v8, (a1) -; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 43 -; RV64-NEXT: mul a1, a1, a2 -; RV64-NEXT: add a1, sp, a1 -; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs8r.v v8, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vle64.v v24, (a1) ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vrgather.vi v8, v16, 4 ; RV64-NEXT: li a1, 128 -; RV64-NEXT: vmv.s.x v0, a1 +; RV64-NEXT: vmv.s.x v4, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m8, ta, ma -; RV64-NEXT: vslidedown.vi v24, v16, 8 -; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu -; RV64-NEXT: vmv1r.v v28, v0 +; RV64-NEXT: vslidedown.vi v16, v16, 8 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a2, a1, 1 -; RV64-NEXT: add a1, a2, a1 +; RV64-NEXT: li a2, 24 +; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill -; RV64-NEXT: vrgather.vi v8, v24, 2, v0.t +; RV64-NEXT: vs8r.v v16, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu +; RV64-NEXT: vmv1r.v v0, v4 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 19 +; RV64-NEXT: li a2, 20 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill -; RV64-NEXT: vmv.v.v v4, v8 +; RV64-NEXT: vs1r.v v4, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vrgather.vi v8, v16, 2, v0.t +; RV64-NEXT: vmv.v.v v20, v8 ; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; RV64-NEXT: li a1, 6 ; RV64-NEXT: vid.v v8 -; RV64-NEXT: vmul.vx v2, v8, a1 +; RV64-NEXT: vmul.vx v6, v8, a1 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma +; RV64-NEXT: vrgatherei16.vv v8, v24, v6 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 43 +; RV64-NEXT: li a2, 48 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v16, v2 +; RV64-NEXT: vs8r.v v24, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; RV64-NEXT: li a1, 56 -; RV64-NEXT: vmv.s.x v1, a1 -; RV64-NEXT: vadd.vi v30, v2, -16 +; RV64-NEXT: vmv.s.x v5, a1 +; RV64-NEXT: vadd.vi v16, v6, -16 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v1 +; RV64-NEXT: vmv1r.v v0, v5 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 35 +; RV64-NEXT: li a2, 40 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v16, v30, v0.t +; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v8, v24, v16, v0.t ; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma -; RV64-NEXT: vmv.v.v v4, v8 +; RV64-NEXT: vmv.v.v v20, v8 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a2, a1, 4 -; RV64-NEXT: sub a1, a2, a1 +; RV64-NEXT: slli a1, a1, 4 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 27 -; RV64-NEXT: mul a1, a1, a2 +; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgather.vi v4, v16, 5 -; RV64-NEXT: vmv1r.v v0, v28 -; RV64-NEXT: vrgather.vi v4, v24, 3, v0.t -; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; RV64-NEXT: addi a1, sp, 16 -; RV64-NEXT: vs2r.v v2, (a1) # Unknown-size Folded Spill -; RV64-NEXT: vadd.vi v16, v2, 1 -; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma +; RV64-NEXT: vrgather.vi v24, v16, 5 +; RV64-NEXT: vmv1r.v v0, v4 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 43 +; RV64-NEXT: li a2, 24 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v24, v16 -; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; RV64-NEXT: vadd.vi v16, v2, -15 +; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgather.vi v24, v16, 3, v0.t +; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; RV64-NEXT: vadd.vi v28, v6, 1 +; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 11 +; RV64-NEXT: li a2, 48 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs2r.v v16, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v8, v16, v28 +; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma +; RV64-NEXT: vadd.vi v28, v6, -15 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v1 +; RV64-NEXT: vmv1r.v v0, v5 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 35 +; RV64-NEXT: li a2, 40 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v8, v16, v28, v0.t +; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma +; RV64-NEXT: vmv.v.v v24, v8 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 11 +; RV64-NEXT: li a2, 12 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl2r.v v2, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v16, v2, v0.t -; RV64-NEXT: vsetivli zero, 6, e64, m4, tu, ma -; RV64-NEXT: vmv.v.v v4, v8 +; RV64-NEXT: vs4r.v v24, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma +; RV64-NEXT: vmv2r.v v26, v6 +; RV64-NEXT: vadd.vi v24, v6, 2 +; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 11 +; RV64-NEXT: li a2, 48 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs4r.v v4, (a1) # Unknown-size Folded Spill -; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; RV64-NEXT: addi a1, sp, 16 -; RV64-NEXT: vl2r.v v2, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vadd.vi v6, v2, 2 -; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma -; RV64-NEXT: vrgatherei16.vv v8, v24, v6 +; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v8, v0, v24 ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; RV64-NEXT: li a1, 24 -; RV64-NEXT: vmv.s.x v7, a1 -; RV64-NEXT: vadd.vi v26, v2, -14 +; RV64-NEXT: vmv.s.x v0, a1 +; RV64-NEXT: csrr a1, vlenb +; RV64-NEXT: slli a1, a1, 1 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: addi a1, a1, 16 +; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vadd.vi v24, v26, -14 +; RV64-NEXT: vmv2r.v v6, v26 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v7 -; RV64-NEXT: vrgatherei16.vv v8, v16, v26, v0.t +; RV64-NEXT: vrgatherei16.vv v8, v16, v24, v0.t ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vmv.v.i v12, 6 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 27 -; RV64-NEXT: mul a1, a1, a2 +; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v16, v24, v12 +; RV64-NEXT: vrgatherei16.vv v20, v24, v12 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a2, a1, 1 -; RV64-NEXT: add a1, a2, a1 +; RV64-NEXT: li a2, 20 +; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl1r.v v6, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vmv1r.v v0, v6 +; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 19 +; RV64-NEXT: li a2, 24 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgather.vi v16, v24, 4, v0.t +; RV64-NEXT: vrgather.vi v20, v24, 4, v0.t ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma -; RV64-NEXT: vmv.v.v v16, v8 +; RV64-NEXT: vmv.v.v v20, v8 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a2, a1, 3 -; RV64-NEXT: sub a1, a2, a1 +; RV64-NEXT: slli a1, a1, 3 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill ; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; RV64-NEXT: vadd.vi v28, v2, 3 +; RV64-NEXT: vmv2r.v v10, v6 +; RV64-NEXT: csrr a1, vlenb +; RV64-NEXT: li a2, 6 +; RV64-NEXT: mul a1, a1, a2 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: addi a1, a1, 16 +; RV64-NEXT: vs2r.v v6, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vadd.vi v8, v6, 3 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 43 +; RV64-NEXT: li a2, 48 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v16, v28 +; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v16, v0, v8 ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; RV64-NEXT: vadd.vi v28, v2, -13 +; RV64-NEXT: vadd.vi v28, v10, -13 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v7 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 35 +; RV64-NEXT: slli a1, a1, 1 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: addi a1, a1, 16 +; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: csrr a1, vlenb +; RV64-NEXT: li a2, 40 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v16, v28, v0.t +; RV64-NEXT: vl8r.v v8, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v16, v8, v28, v0.t ; RV64-NEXT: lui a1, 16 ; RV64-NEXT: addi a1, a1, 7 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vmv.v.x v12, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 27 -; RV64-NEXT: mul a1, a1, a2 +; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v16, v24, v12 -; RV64-NEXT: vmv1r.v v0, v6 +; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vmv4r.v v8, v0 +; RV64-NEXT: vrgatherei16.vv v20, v0, v12 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 19 +; RV64-NEXT: li a2, 20 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgather.vi v16, v24, 5, v0.t +; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgather.vi v20, v24, 5, v0.t ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma -; RV64-NEXT: vmv.v.v v16, v8 +; RV64-NEXT: vmv.v.v v20, v16 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a2, a1, 1 -; RV64-NEXT: add a1, a2, a1 +; RV64-NEXT: li a2, 20 +; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vs4r.v v16, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vs4r.v v20, (a1) # Unknown-size Folded Spill ; RV64-NEXT: lui a1, 96 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma -; RV64-NEXT: vmv.v.x v8, a1 +; RV64-NEXT: vmv.v.x v12, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: li a1, 192 ; RV64-NEXT: vmv.s.x v0, a1 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a1, a1, 1 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vrgather.vi v28, v8, 2 +; RV64-NEXT: vrgatherei16.vv v28, v24, v12, v0.t +; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 27 +; RV64-NEXT: li a2, 6 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgather.vi v4, v16, 2 -; RV64-NEXT: vrgatherei16.vv v4, v24, v8, v0.t -; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; RV64-NEXT: vadd.vi v16, v2, 4 +; RV64-NEXT: vl2r.v v24, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vadd.vi v16, v24, 4 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 43 +; RV64-NEXT: li a2, 48 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v24, v16 +; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v8, v0, v16 ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; RV64-NEXT: li a1, 28 -; RV64-NEXT: vmv.s.x v1, a1 -; RV64-NEXT: vadd.vi v16, v2, -12 +; RV64-NEXT: vmv.s.x v0, a1 +; RV64-NEXT: addi a1, sp, 16 +; RV64-NEXT: vs1r.v v0, (a1) # Unknown-size Folded Spill +; RV64-NEXT: vadd.vi v26, v24, -12 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v1 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 35 +; RV64-NEXT: li a2, 40 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v8, v24, v16, v0.t +; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v8, v16, v26, v0.t ; RV64-NEXT: vsetivli zero, 5, e64, m4, tu, ma -; RV64-NEXT: vmv.v.v v4, v8 +; RV64-NEXT: vmv.v.v v28, v8 +; RV64-NEXT: csrr a1, vlenb +; RV64-NEXT: slli a1, a1, 1 +; RV64-NEXT: add a1, sp, a1 +; RV64-NEXT: addi a1, a1, 16 +; RV64-NEXT: vs4r.v v28, (a1) # Unknown-size Folded Spill ; RV64-NEXT: lui a1, 112 ; RV64-NEXT: addi a1, a1, 1 ; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; RV64-NEXT: vmv.v.x v12, a1 ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, mu ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 27 -; RV64-NEXT: mul a1, a1, a2 +; RV64-NEXT: slli a1, a1, 5 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vrgather.vi v8, v16, 3 ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a1, a1, 1 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 19 +; RV64-NEXT: li a2, 24 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl8r.v v16, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vrgatherei16.vv v8, v16, v12, v0.t ; RV64-NEXT: vsetivli zero, 16, e16, m2, ta, ma -; RV64-NEXT: vadd.vi v12, v2, 5 +; RV64-NEXT: vadd.vi v12, v24, 5 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 43 +; RV64-NEXT: li a2, 48 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 -; RV64-NEXT: vl8r.v v24, (a1) # Unknown-size Folded Reload -; RV64-NEXT: vrgatherei16.vv v16, v24, v12 +; RV64-NEXT: vl8r.v v0, (a1) # Unknown-size Folded Reload +; RV64-NEXT: vrgatherei16.vv v16, v0, v12 ; RV64-NEXT: vsetvli zero, zero, e16, m2, ta, ma -; RV64-NEXT: vadd.vi v12, v2, -11 +; RV64-NEXT: vadd.vi v12, v24, -11 ; RV64-NEXT: vsetvli zero, zero, e64, m8, ta, mu -; RV64-NEXT: vmv1r.v v0, v1 +; RV64-NEXT: addi a1, sp, 16 +; RV64-NEXT: vl1r.v v0, (a1) # Unknown-size Folded Reload ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: li a2, 35 +; RV64-NEXT: li a2, 40 ; RV64-NEXT: mul a1, a1, a2 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 @@ -911,40 +933,43 @@ define {<8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>, <8 x i64>} @load_ ; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: addi a1, a0, 256 -; RV64-NEXT: vse64.v v4, (a1) +; RV64-NEXT: csrr a2, vlenb +; RV64-NEXT: slli a2, a2, 1 +; RV64-NEXT: add a2, sp, a2 +; RV64-NEXT: addi a2, a2, 16 +; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload +; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: addi a1, a0, 192 ; RV64-NEXT: csrr a2, vlenb -; RV64-NEXT: slli a3, a2, 1 -; RV64-NEXT: add a2, a3, a2 +; RV64-NEXT: li a3, 20 +; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: addi a1, a0, 128 ; RV64-NEXT: csrr a2, vlenb -; RV64-NEXT: slli a3, a2, 3 -; RV64-NEXT: sub a2, a3, a2 +; RV64-NEXT: slli a2, a2, 3 ; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: addi a1, a0, 64 ; RV64-NEXT: csrr a2, vlenb -; RV64-NEXT: li a3, 11 +; RV64-NEXT: li a3, 12 ; RV64-NEXT: mul a2, a2, a3 ; RV64-NEXT: add a2, sp, a2 ; RV64-NEXT: addi a2, a2, 16 ; RV64-NEXT: vl4r.v v8, (a2) # Unknown-size Folded Reload ; RV64-NEXT: vse64.v v8, (a1) ; RV64-NEXT: csrr a1, vlenb -; RV64-NEXT: slli a2, a1, 4 -; RV64-NEXT: sub a1, a2, a1 +; RV64-NEXT: slli a1, a1, 4 ; RV64-NEXT: add a1, sp, a1 ; RV64-NEXT: addi a1, a1, 16 ; RV64-NEXT: vl4r.v v8, (a1) # Unknown-size Folded Reload ; RV64-NEXT: vse64.v v8, (a0) ; RV64-NEXT: csrr a0, vlenb -; RV64-NEXT: li a1, 52 +; RV64-NEXT: li a1, 56 ; RV64-NEXT: mul a0, a0, a1 ; RV64-NEXT: add sp, sp, a0 ; RV64-NEXT: addi sp, sp, 16 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll index c295fed2c28c1011366a83227b133fff399c9bf3..023d707f07bff7a88865d518515576e13e601f1f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-buildvec.ll @@ -286,8 +286,8 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) { ; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a3 ; CHECK-NEXT: vslide1down.vx v8, v8, zero -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslide1down.vx v8, v8, a2 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 @@ -303,8 +303,8 @@ define <8 x i1> @buildvec_mask_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 %w) { ; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a3 ; ZVE32F-NEXT: vslide1down.vx v8, v8, zero -; ZVE32F-NEXT: vmv.v.i v0, 15 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; ZVE32F-NEXT: vmv.v.i v0, 15 ; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0 @@ -331,8 +331,8 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 % ; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a3 ; CHECK-NEXT: vslide1down.vx v8, v8, zero -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslide1down.vx v8, v8, a2 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 @@ -348,8 +348,8 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1_2(i1 %x, i1 %y, i1 %z, i1 % ; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a3 ; ZVE32F-NEXT: vslide1down.vx v8, v8, zero -; ZVE32F-NEXT: vmv.v.i v0, 15 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a2 +; ZVE32F-NEXT: vmv.v.i v0, 15 ; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0 @@ -375,8 +375,8 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize { ; CHECK-NEXT: vslide1down.vx v9, v9, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1 ; CHECK-NEXT: vslide1down.vx v8, v8, a1 -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslide1down.vx v8, v8, a1 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vslidedown.vi v8, v9, 4, v0.t ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 @@ -391,8 +391,8 @@ define <8 x i1> @buildvec_mask_optsize_nonconst_v8i1(i1 %x, i1 %y) optsize { ; ZVE32F-NEXT: vslide1down.vx v9, v9, a1 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 -; ZVE32F-NEXT: vmv.v.i v0, 15 ; ZVE32F-NEXT: vslide1down.vx v8, v8, a1 +; ZVE32F-NEXT: vmv.v.i v0, 15 ; ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; ZVE32F-NEXT: vand.vi v8, v8, 1 ; ZVE32F-NEXT: vmsne.vi v0, v8, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll index 4f7b885d998e5b1d044e67d6b77075d2545c8de5..7fc442c88d101bafa12d10a656cc9e2d7fc42176 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-mask-splat.ll @@ -25,10 +25,10 @@ define void @splat_v1i1(ptr %x, i1 %y) { ; CHECK-LABEL: splat_v1i1: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 1, e8, mf8, ta, ma -; CHECK-NEXT: andi a1, a1, 1 -; CHECK-NEXT: vmv.s.x v8, a1 -; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: andi a1, a1, 1 +; CHECK-NEXT: vmv.s.x v9, a1 +; CHECK-NEXT: vmsne.vi v0, v9, 0 ; CHECK-NEXT: vmerge.vim v8, v8, 1, v0 ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vmv.v.i v9, 0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll index 9fbc22221f99bd14bc6b987862a049de9df68efd..539a8403c93521ac5c485ca3f347a60e9e623cd3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-gather.ll @@ -12728,8 +12728,8 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV32-NEXT: vmv.v.x v8, a3 ; RV32-NEXT: vslide1down.vx v8, v8, a5 ; RV32-NEXT: vslide1down.vx v8, v8, a6 -; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vslide1down.vx v8, v8, a7 +; RV32-NEXT: vmv.v.i v0, 15 ; RV32-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV32-NEXT: ret ; @@ -12803,8 +12803,8 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV64V-NEXT: vmv.v.x v8, a3 ; RV64V-NEXT: vslide1down.vx v8, v8, a5 ; RV64V-NEXT: vslide1down.vx v8, v8, a6 -; RV64V-NEXT: vmv.v.i v0, 15 ; RV64V-NEXT: vslide1down.vx v8, v8, a7 +; RV64V-NEXT: vmv.v.i v0, 15 ; RV64V-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64V-NEXT: addi sp, s0, -128 ; RV64V-NEXT: ld ra, 120(sp) # 8-byte Folded Reload @@ -12854,8 +12854,8 @@ define <8 x i16> @mgather_strided_unaligned(ptr %base) { ; RV64ZVE32F-NEXT: vmv.v.x v8, a5 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a0 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -12896,8 +12896,8 @@ define <8 x i16> @mgather_strided_2xSEW(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -12941,8 +12941,8 @@ define <8 x i16> @mgather_strided_2xSEW_with_offset(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> @@ -12986,8 +12986,8 @@ define <8 x i16> @mgather_reverse_unit_strided_2xSEW(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> @@ -13031,8 +13031,8 @@ define <8 x i16> @mgather_reverse_strided_2xSEW(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a7 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> @@ -13074,8 +13074,8 @@ define <8 x i16> @mgather_gather_2xSEW(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -13120,8 +13120,8 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -13167,8 +13167,8 @@ define <8 x i16> @mgather_gather_2xSEW_unaligned2(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a5 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a2 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -13217,8 +13217,8 @@ define <8 x i16> @mgather_gather_4xSEW(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -13264,8 +13264,8 @@ define <8 x i16> @mgather_gather_4xSEW_partial_align(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i32> @@ -13320,8 +13320,8 @@ define <8 x i16> @mgather_shuffle_rotate(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 ; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a1 ; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a2 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v9, v9, a3 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v9, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> @@ -13367,8 +13367,8 @@ define <8 x i16> @mgather_shuffle_vrgather(ptr %base) { ; RV64ZVE32F-NEXT: vslide1down.vx v10, v8, a3 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v9, a4 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a5 -; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslide1down.vx v8, v8, a6 +; RV64ZVE32F-NEXT: vmv.v.i v0, 15 ; RV64ZVE32F-NEXT: vslidedown.vi v8, v10, 4, v0.t ; RV64ZVE32F-NEXT: ret %ptrs = getelementptr inbounds i16, ptr %base, <8 x i64> diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll index 2a0ec47a3de01c9a483e1a1e264d6c3a65a5566a..5f456c7824316b2e985592795e4e9b16a0fdbdde 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-reduction-formation.ll @@ -221,10 +221,10 @@ define i32 @reduce_sum_16xi32_prefix7(ptr %p) { ; CHECK-LABEL: reduce_sum_16xi32_prefix7: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmv.s.x v10, zero -; CHECK-NEXT: vslideup.vi v8, v10, 7 -; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vslideup.vi v10, v8, 7 +; CHECK-NEXT: vredsum.vs v8, v10, v8 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, ptr %p, align 256 @@ -248,9 +248,9 @@ define i32 @reduce_sum_16xi32_prefix8(ptr %p) { ; CHECK-LABEL: reduce_sum_16xi32_prefix8: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmv.s.x v10, zero -; CHECK-NEXT: vredsum.vs v8, v8, v10 +; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: vle32.v v10, (a0) +; CHECK-NEXT: vredsum.vs v8, v10, v8 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, ptr %p, align 256 @@ -670,15 +670,15 @@ define i32 @reduce_smax_16xi32_prefix5(ptr %p) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmv.s.x v10, a1 +; CHECK-NEXT: vmv.s.x v8, a1 +; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 5 +; CHECK-NEXT: vslideup.vi v10, v8, 5 ; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 6 +; CHECK-NEXT: vslideup.vi v10, v8, 6 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vslideup.vi v8, v10, 7 -; CHECK-NEXT: vredmax.vs v8, v8, v8 +; CHECK-NEXT: vslideup.vi v10, v8, 7 +; CHECK-NEXT: vredmax.vs v8, v10, v10 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, ptr %p, align 256 @@ -715,15 +715,15 @@ define i32 @reduce_smin_16xi32_prefix5(ptr %p) { ; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: addi a1, a1, -1 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmv.s.x v10, a1 +; CHECK-NEXT: vmv.s.x v8, a1 +; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 5 +; CHECK-NEXT: vslideup.vi v10, v8, 5 ; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 6 +; CHECK-NEXT: vslideup.vi v10, v8, 6 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vslideup.vi v8, v10, 7 -; CHECK-NEXT: vredmin.vs v8, v8, v8 +; CHECK-NEXT: vslideup.vi v10, v8, 7 +; CHECK-NEXT: vredmin.vs v8, v10, v10 ; CHECK-NEXT: vmv.x.s a0, v8 ; CHECK-NEXT: ret %v = load <16 x i32>, ptr %p, align 256 @@ -830,9 +830,9 @@ define float @reduce_fadd_16xf32_prefix2(ptr %p) { ; CHECK-LABEL: reduce_fadd_16xf32_prefix2: ; CHECK: # %bb.0: ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmv.s.x v9, zero -; CHECK-NEXT: vfredusum.vs v8, v8, v9 +; CHECK-NEXT: vmv.s.x v8, zero +; CHECK-NEXT: vle32.v v9, (a0) +; CHECK-NEXT: vfredusum.vs v8, v9, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <16 x float>, ptr %p, align 256 @@ -847,15 +847,15 @@ define float @reduce_fadd_16xi32_prefix5(ptr %p) { ; CHECK: # %bb.0: ; CHECK-NEXT: lui a1, 524288 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vle32.v v8, (a0) -; CHECK-NEXT: vmv.s.x v10, a1 +; CHECK-NEXT: vmv.s.x v8, a1 +; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vsetivli zero, 6, e32, m2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 5 +; CHECK-NEXT: vslideup.vi v10, v8, 5 ; CHECK-NEXT: vsetivli zero, 7, e32, m2, tu, ma -; CHECK-NEXT: vslideup.vi v8, v10, 6 +; CHECK-NEXT: vslideup.vi v10, v8, 6 ; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma -; CHECK-NEXT: vslideup.vi v8, v10, 7 -; CHECK-NEXT: vfredusum.vs v8, v8, v10 +; CHECK-NEXT: vslideup.vi v10, v8, 7 +; CHECK-NEXT: vfredusum.vs v8, v10, v8 ; CHECK-NEXT: vfmv.f.s fa0, v8 ; CHECK-NEXT: ret %v = load <16 x float>, ptr %p, align 256 diff --git a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll index 032d32109933f3badf0fd1b550e6d0c9bf38c6ce..ab7da9e0faf2b9323b405b75c2dfd1b5d13de550 100644 --- a/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/shuffle-reverse.ll @@ -49,8 +49,8 @@ define <8 x i8> @v4i8_2(<4 x i8> %a, <4 x i8> %b) { ; CHECK-NEXT: vid.v v11 ; CHECK-NEXT: vrsub.vi v12, v11, 7 ; CHECK-NEXT: vrgather.vv v10, v8, v12 -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vrsub.vi v8, v11, 3 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret @@ -174,8 +174,8 @@ define <8 x i16> @v4i16_2(<4 x i16> %a, <4 x i16> %b) { ; CHECK-NEXT: vid.v v11 ; CHECK-NEXT: vrsub.vi v12, v11, 7 ; CHECK-NEXT: vrgather.vv v10, v8, v12 -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vrsub.vi v8, v11, 3 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -492,8 +492,8 @@ define <8 x half> @v4f16_2(<4 x half> %a, <4 x half> %b) { ; CHECK-NEXT: vid.v v11 ; CHECK-NEXT: vrsub.vi v12, v11, 7 ; CHECK-NEXT: vrgather.vv v10, v8, v12 -; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vrsub.vi v8, v11, 3 +; CHECK-NEXT: vmv.v.i v0, 15 ; CHECK-NEXT: vrgather.vv v10, v9, v8, v0.t ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll index 9a5e86d61c265ea18634174a401c73675ab72c76..922692ed88c9f264746e0c9b98b3517f7a44befd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll @@ -107,14 +107,14 @@ define void @vector_interleave_store_nxv16i64_nxv8i64( %a, %a, @vector_interleave_nxv4i64_nxv2i64( ; CHECK-NEXT: srli a0, a0, 2 ; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; CHECK-NEXT: vid.v v12 -; CHECK-NEXT: vand.vi v13, v12, 1 -; CHECK-NEXT: vmsne.vi v0, v13, 0 ; CHECK-NEXT: vsrl.vi v16, v12, 1 +; CHECK-NEXT: vand.vi v12, v12, 1 +; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: vadd.vx v16, v16, a0, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 @@ -137,9 +137,9 @@ define @vector_interleave_nxv4i64_nxv2i64( ; ZVBB-NEXT: srli a0, a0, 2 ; ZVBB-NEXT: vsetvli a1, zero, e16, m1, ta, mu ; ZVBB-NEXT: vid.v v12 -; ZVBB-NEXT: vand.vi v13, v12, 1 -; ZVBB-NEXT: vmsne.vi v0, v13, 0 ; ZVBB-NEXT: vsrl.vi v16, v12, 1 +; ZVBB-NEXT: vand.vi v12, v12, 1 +; ZVBB-NEXT: vmsne.vi v0, v12, 0 ; ZVBB-NEXT: vadd.vx v16, v16, a0, v0.t ; ZVBB-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; ZVBB-NEXT: vrgatherei16.vv v12, v8, v16 @@ -288,32 +288,44 @@ define @vector_interleave_nxv16i64_nxv8i64( @vector_interleave_nxv16i64_nxv8i64( @vector_interleave_nxv4f64_nxv2f64( @vector_interleave_nxv4f64_nxv2f64( @vector_interleave_nxv16f64_nxv8f64( @vector_interleave_nxv16f64_nxv8f64( @llvm.riscv.vmfeq.mask.nxv1f16( define @intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmfeq.mask.nxv2f16( define @intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmfeq.mask.nxv4f16( define @intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -190,12 +187,11 @@ declare @llvm.riscv.vmfeq.mask.nxv8f16( define @intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmfeq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vmfeq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfeq.nxv8f16( @@ -242,12 +238,11 @@ declare @llvm.riscv.vmfeq.mask.nxv16f16( define @intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmfeq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vmfeq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfeq.nxv16f16( @@ -294,10 +289,9 @@ declare @llvm.riscv.vmfeq.mask.nxv1f32( define @intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -346,10 +340,9 @@ declare @llvm.riscv.vmfeq.mask.nxv2f32( define @intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -398,12 +391,11 @@ declare @llvm.riscv.vmfeq.mask.nxv4f32( define @intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmfeq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vmfeq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfeq.nxv4f32( @@ -450,12 +442,11 @@ declare @llvm.riscv.vmfeq.mask.nxv8f32( define @intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmfeq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vmfeq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfeq.nxv8f32( @@ -502,10 +493,9 @@ declare @llvm.riscv.vmfeq.mask.nxv1f64( define @intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmfeq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmfeq.vv v0, v8, v9 ; CHECK-NEXT: vmfeq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -554,12 +544,11 @@ declare @llvm.riscv.vmfeq.mask.nxv2f64( define @intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmfeq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfeq.vv v0, v8, v10 +; CHECK-NEXT: vmfeq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfeq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfeq.nxv2f64( @@ -606,12 +595,11 @@ declare @llvm.riscv.vmfeq.mask.nxv4f64( define @intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfeq_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmfeq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfeq.vv v0, v8, v12 +; CHECK-NEXT: vmfeq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfeq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfeq.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfge.ll b/llvm/test/CodeGen/RISCV/rvv/vmfge.ll index 993b50a1c81ce885ca54840c85d209952cfbd653..a6dad9eaa4f35814bc6f02c8c6f1484bd6feac68 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfge.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfge.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmfge.mask.nxv1f16( define @intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmfge.mask.nxv2f16( define @intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmfge.mask.nxv4f16( define @intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -190,12 +187,11 @@ declare @llvm.riscv.vmfge.mask.nxv8f16( define @intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmfle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v10, v8 +; CHECK-NEXT: vmfle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfge.nxv8f16( @@ -242,12 +238,11 @@ declare @llvm.riscv.vmfge.mask.nxv16f16( define @intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmfle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v12, v8 +; CHECK-NEXT: vmfle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfge.nxv16f16( @@ -294,10 +289,9 @@ declare @llvm.riscv.vmfge.mask.nxv1f32( define @intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -346,10 +340,9 @@ declare @llvm.riscv.vmfge.mask.nxv2f32( define @intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -398,12 +391,11 @@ declare @llvm.riscv.vmfge.mask.nxv4f32( define @intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmfle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v10, v8 +; CHECK-NEXT: vmfle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfge.nxv4f32( @@ -450,12 +442,11 @@ declare @llvm.riscv.vmfge.mask.nxv8f32( define @intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmfle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v12, v8 +; CHECK-NEXT: vmfle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfge.nxv8f32( @@ -502,10 +493,9 @@ declare @llvm.riscv.vmfge.mask.nxv1f64( define @intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmfle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmfle.vv v0, v9, v8 ; CHECK-NEXT: vmfle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -554,12 +544,11 @@ declare @llvm.riscv.vmfge.mask.nxv2f64( define @intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmfle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v10, v8 +; CHECK-NEXT: vmfle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfge.nxv2f64( @@ -606,12 +595,11 @@ declare @llvm.riscv.vmfge.mask.nxv4f64( define @intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfge_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmfle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v12, v8 +; CHECK-NEXT: vmfle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfge.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll index 427f0eb28e7df5ed3d5e5ffcb997861e86f23723..f643a4036381c3b67e1aa44bc07324a25ec9dbad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfgt.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmfgt.mask.nxv1f16( define @intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmfgt.mask.nxv2f16( define @intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmfgt.mask.nxv4f16( define @intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -190,12 +187,11 @@ declare @llvm.riscv.vmfgt.mask.nxv8f16( define @intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v10, v8 +; CHECK-NEXT: vmflt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfgt.nxv8f16( @@ -242,12 +238,11 @@ declare @llvm.riscv.vmfgt.mask.nxv16f16( define @intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmflt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v12, v8 +; CHECK-NEXT: vmflt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfgt.nxv16f16( @@ -294,10 +289,9 @@ declare @llvm.riscv.vmfgt.mask.nxv1f32( define @intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -346,10 +340,9 @@ declare @llvm.riscv.vmfgt.mask.nxv2f32( define @intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -398,12 +391,11 @@ declare @llvm.riscv.vmfgt.mask.nxv4f32( define @intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmflt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v10, v8 +; CHECK-NEXT: vmflt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfgt.nxv4f32( @@ -450,12 +442,11 @@ declare @llvm.riscv.vmfgt.mask.nxv8f32( define @intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v12, v8 +; CHECK-NEXT: vmflt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfgt.nxv8f32( @@ -502,10 +493,9 @@ declare @llvm.riscv.vmfgt.mask.nxv1f64( define @intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmflt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmflt.vv v0, v9, v8 ; CHECK-NEXT: vmflt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -554,12 +544,11 @@ declare @llvm.riscv.vmfgt.mask.nxv2f64( define @intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmflt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v10, v8 +; CHECK-NEXT: vmflt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmflt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfgt.nxv2f64( @@ -606,12 +595,11 @@ declare @llvm.riscv.vmfgt.mask.nxv4f64( define @intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfgt_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmflt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v12, v8 +; CHECK-NEXT: vmflt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmflt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfgt.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfle.ll b/llvm/test/CodeGen/RISCV/rvv/vmfle.ll index e5327632fc04f6bbbc436c2387dfcf0934233407..6c52364c1fbd56f7273f3d2682016537807b23ab 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfle.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfle.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmfle.mask.nxv1f16( define @intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmfle.mask.nxv2f16( define @intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmfle.mask.nxv4f16( define @intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -190,12 +187,11 @@ declare @llvm.riscv.vmfle.mask.nxv8f16( define @intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmfle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv8f16( @@ -242,12 +238,11 @@ declare @llvm.riscv.vmfle.mask.nxv16f16( define @intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmfle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv16f16( @@ -294,10 +289,9 @@ declare @llvm.riscv.vmfle.mask.nxv1f32( define @intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -346,10 +340,9 @@ declare @llvm.riscv.vmfle.mask.nxv2f32( define @intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -398,12 +391,11 @@ declare @llvm.riscv.vmfle.mask.nxv4f32( define @intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmfle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv4f32( @@ -450,12 +442,11 @@ declare @llvm.riscv.vmfle.mask.nxv8f32( define @intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmfle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv8f32( @@ -502,10 +493,9 @@ declare @llvm.riscv.vmfle.mask.nxv1f64( define @intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmfle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmfle.vv v0, v8, v9 ; CHECK-NEXT: vmfle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -554,12 +544,11 @@ declare @llvm.riscv.vmfle.mask.nxv2f64( define @intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmfle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v8, v10 +; CHECK-NEXT: vmfle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv2f64( @@ -606,12 +595,11 @@ declare @llvm.riscv.vmfle.mask.nxv4f64( define @intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfle_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmfle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfle.vv v0, v8, v12 +; CHECK-NEXT: vmfle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfle.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmflt.ll b/llvm/test/CodeGen/RISCV/rvv/vmflt.ll index 64f257e355ceae91433e4b852d9c3a6b7e38c913..37a9c6b081a1dfc6ce0f10275b8c1391d80d1f34 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmflt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmflt.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmflt.mask.nxv1f16( define @intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmflt.mask.nxv2f16( define @intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmflt.mask.nxv4f16( define @intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -190,12 +187,11 @@ declare @llvm.riscv.vmflt.mask.nxv8f16( define @intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmflt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vmflt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmflt.nxv8f16( @@ -242,12 +238,11 @@ declare @llvm.riscv.vmflt.mask.nxv16f16( define @intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmflt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vmflt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmflt.nxv16f16( @@ -294,10 +289,9 @@ declare @llvm.riscv.vmflt.mask.nxv1f32( define @intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -346,10 +340,9 @@ declare @llvm.riscv.vmflt.mask.nxv2f32( define @intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -398,12 +391,11 @@ declare @llvm.riscv.vmflt.mask.nxv4f32( define @intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmflt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vmflt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmflt.nxv4f32( @@ -450,12 +442,11 @@ declare @llvm.riscv.vmflt.mask.nxv8f32( define @intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmflt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vmflt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmflt.nxv8f32( @@ -502,10 +493,9 @@ declare @llvm.riscv.vmflt.mask.nxv1f64( define @intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmflt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmflt.vv v0, v8, v9 ; CHECK-NEXT: vmflt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -554,12 +544,11 @@ declare @llvm.riscv.vmflt.mask.nxv2f64( define @intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmflt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v8, v10 +; CHECK-NEXT: vmflt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmflt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmflt.nxv2f64( @@ -606,12 +595,11 @@ declare @llvm.riscv.vmflt.mask.nxv4f64( define @intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmflt_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmflt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmflt.vv v0, v8, v12 +; CHECK-NEXT: vmflt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmflt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmflt.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmfne.ll b/llvm/test/CodeGen/RISCV/rvv/vmfne.ll index 6f6a2a5e8783c6b6cf8546785358144116746e65..5defce42091e55a51ed3928bcd5b0e9a08e58149 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmfne.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmfne.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmfne.mask.nxv1f16( define @intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmfne.mask.nxv2f16( define @intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmfne.mask.nxv4f16( define @intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -190,12 +187,11 @@ declare @llvm.riscv.vmfne.mask.nxv8f16( define @intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmfne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vmfne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfne.nxv8f16( @@ -242,12 +238,11 @@ declare @llvm.riscv.vmfne.mask.nxv16f16( define @intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmfne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vmfne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfne.nxv16f16( @@ -294,10 +289,9 @@ declare @llvm.riscv.vmfne.mask.nxv1f32( define @intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -346,10 +340,9 @@ declare @llvm.riscv.vmfne.mask.nxv2f32( define @intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -398,12 +391,11 @@ declare @llvm.riscv.vmfne.mask.nxv4f32( define @intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmfne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vmfne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfne.nxv4f32( @@ -450,12 +442,11 @@ declare @llvm.riscv.vmfne.mask.nxv8f32( define @intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmfne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vmfne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfne.nxv8f32( @@ -502,10 +493,9 @@ declare @llvm.riscv.vmfne.mask.nxv1f64( define @intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmfne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmfne.vv v0, v8, v9 ; CHECK-NEXT: vmfne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -554,12 +544,11 @@ declare @llvm.riscv.vmfne.mask.nxv2f64( define @intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmfne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfne.vv v0, v8, v10 +; CHECK-NEXT: vmfne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmfne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfne.nxv2f64( @@ -606,12 +595,11 @@ declare @llvm.riscv.vmfne.mask.nxv4f64( define @intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmfne_mask_vv_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmfne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmfne.vv v0, v8, v12 +; CHECK-NEXT: vmfne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmfne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmfne.nxv4f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll index da1c751b566304bfda51494c0ea6b7aa10daa634..cc6c1f585bb7d8f87d00b6c06791094a61fada1e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmseq.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmseq.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmseq.mask.nxv1i8( define @intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmseq.mask.nxv2i8( define @intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmseq.mask.nxv4i8( define @intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmseq.mask.nxv8i8( define @intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmseq.mask.nxv16i8( define @intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmseq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vmseq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmseq.mask.nxv32i8( define @intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmseq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vmseq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmseq.mask.nxv1i16( define @intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmseq.mask.nxv2i16( define @intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmseq.mask.nxv4i16( define @intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i16( define @intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmseq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vmseq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmseq.mask.nxv16i16( define @intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmseq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vmseq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmseq.mask.nxv1i32( define @intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmseq.mask.nxv2i32( define @intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i32( define @intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmseq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vmseq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmseq.mask.nxv8i32( define @intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmseq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vmseq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmseq.mask.nxv1i64( define @intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmseq.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmseq.vv v0, v8, v9 ; CHECK-NEXT: vmseq.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmseq.mask.nxv2i64( define @intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmseq.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v10 +; CHECK-NEXT: vmseq.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmseq.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmseq.mask.nxv4i64( define @intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmseq_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmseq.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmseq.vv v0, v8, v12 +; CHECK-NEXT: vmseq.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmseq.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmseq.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll index 502fb9b24148f7123e8729808394049b0b8ea248..c8f9b60a3f2da6c6d8979c1b29d11b0526ad122e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsge.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsge.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsge.mask.nxv1i8( define @intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsge.mask.nxv2i8( define @intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsge.mask.nxv4i8( define @intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsge.mask.nxv8i8( define @intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsge.mask.nxv16i8( define @intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 +; CHECK-NEXT: vmsle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsge.mask.nxv32i8( define @intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 +; CHECK-NEXT: vmsle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsge.mask.nxv1i16( define @intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsge.mask.nxv2i16( define @intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsge.mask.nxv4i16( define @intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i16( define @intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 +; CHECK-NEXT: vmsle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsge.mask.nxv16i16( define @intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 +; CHECK-NEXT: vmsle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsge.mask.nxv1i32( define @intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsge.mask.nxv2i32( define @intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i32( define @intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 +; CHECK-NEXT: vmsle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsge.mask.nxv8i32( define @intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 +; CHECK-NEXT: vmsle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsge.mask.nxv1i64( define @intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v9, v8 ; CHECK-NEXT: vmsle.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsge.mask.nxv2i64( define @intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v10, v8 +; CHECK-NEXT: vmsle.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsge.mask.nxv4i64( define @intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsge_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v12, v8 +; CHECK-NEXT: vmsle.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsge.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll index 9410a99d81423f5f63821e9d2b620e74c8f29c6f..b6c6d9e90f6109b42fb82c99091618a3b54c2bca 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgeu.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i8( define @intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i8( define @intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i8( define @intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i8( define @intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv16i8( define @intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 +; CHECK-NEXT: vmsleu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv32i8( define @intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 +; CHECK-NEXT: vmsleu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i16( define @intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i16( define @intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i16( define @intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i16( define @intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 +; CHECK-NEXT: vmsleu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv16i16( define @intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 +; CHECK-NEXT: vmsleu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i32( define @intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i32( define @intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i32( define @intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 +; CHECK-NEXT: vmsleu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv8i32( define @intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 +; CHECK-NEXT: vmsleu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsgeu.mask.nxv1i64( define @intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v9, v8 ; CHECK-NEXT: vmsleu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv2i64( define @intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v10, v8 +; CHECK-NEXT: vmsleu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsgeu.mask.nxv4i64( define @intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgeu_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v12, v8 +; CHECK-NEXT: vmsleu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgeu.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll index b7a676e7f2dd37c1cf260b5beb4521748ac16623..dfd7096a65ebb98a5a77c7ac8c48318edf013030 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgt.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsgt.mask.nxv1i8( define @intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsgt.mask.nxv2i8( define @intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsgt.mask.nxv4i8( define @intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsgt.mask.nxv8i8( define @intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsgt.mask.nxv16i8( define @intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v10, v8 +; CHECK-NEXT: vmslt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsgt.mask.nxv32i8( define @intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v12, v8 +; CHECK-NEXT: vmslt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsgt.mask.nxv1i16( define @intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsgt.mask.nxv2i16( define @intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsgt.mask.nxv4i16( define @intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i16( define @intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v10, v8 +; CHECK-NEXT: vmslt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsgt.mask.nxv16i16( define @intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v12, v8 +; CHECK-NEXT: vmslt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsgt.mask.nxv1i32( define @intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsgt.mask.nxv2i32( define @intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i32( define @intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v10, v8 +; CHECK-NEXT: vmslt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsgt.mask.nxv8i32( define @intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v12, v8 +; CHECK-NEXT: vmslt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsgt.mask.nxv1i64( define @intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v9, v8 ; CHECK-NEXT: vmslt.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsgt.mask.nxv2i64( define @intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v10, v8 +; CHECK-NEXT: vmslt.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsgt.mask.nxv4i64( define @intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgt_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v12, v8 +; CHECK-NEXT: vmslt.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgt.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll index 88a632de067a68cca31715c983b009e2c4a3adf3..8826be03bbebb8962ec0819c1c99f02eb16ff942 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsgtu.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i8( define @intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i8( define @intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i8( define @intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i8( define @intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv16i8( define @intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 +; CHECK-NEXT: vmsltu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv32i8( define @intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 +; CHECK-NEXT: vmsltu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i16( define @intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i16( define @intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i16( define @intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i16( define @intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 +; CHECK-NEXT: vmsltu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv16i16( define @intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 +; CHECK-NEXT: vmsltu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i32( define @intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i32( define @intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i32( define @intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 +; CHECK-NEXT: vmsltu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv8i32( define @intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 +; CHECK-NEXT: vmsltu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsgtu.mask.nxv1i64( define @intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v9, v8 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v9, v8 ; CHECK-NEXT: vmsltu.vv v11, v10, v9, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv2i64( define @intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v10, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v10, v8 +; CHECK-NEXT: vmsltu.vv v14, v12, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v12, v10, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsgtu.mask.nxv4i64( define @intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsgtu_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v12, v8 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v12, v8 +; CHECK-NEXT: vmsltu.vv v20, v16, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v16, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsgtu.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll index 2248ba03adfe7986cd82888bb13345ee2e25e29a..5d5a28edbfe1519c8f03bedf09cd7236dffba949 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsle.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsle.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsle.mask.nxv1i8( define @intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsle.mask.nxv2i8( define @intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsle.mask.nxv4i8( define @intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsle.mask.nxv8i8( define @intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsle.mask.nxv16i8( define @intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vmsle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsle.mask.nxv32i8( define @intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vmsle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsle.mask.nxv1i16( define @intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsle.mask.nxv2i16( define @intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsle.mask.nxv4i16( define @intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i16( define @intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vmsle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsle.mask.nxv16i16( define @intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vmsle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsle.mask.nxv1i32( define @intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsle.mask.nxv2i32( define @intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i32( define @intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vmsle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsle.mask.nxv8i32( define @intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vmsle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsle.mask.nxv1i64( define @intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsle.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsle.vv v0, v8, v9 ; CHECK-NEXT: vmsle.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsle.mask.nxv2i64( define @intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsle.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v10 +; CHECK-NEXT: vmsle.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsle.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsle.mask.nxv4i64( define @intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsle_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsle.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsle.vv v0, v8, v12 +; CHECK-NEXT: vmsle.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsle.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsle.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll index 57bae83b25e0e5a7f93dade81b910e054d02a7bd..c58ac2d0718314196ae2f7f781768b89711c4df7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsleu.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsleu.mask.nxv1i8( define @intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsleu.mask.nxv2i8( define @intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsleu.mask.nxv4i8( define @intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsleu.mask.nxv8i8( define @intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsleu.mask.nxv16i8( define @intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vmsleu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsleu.mask.nxv32i8( define @intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vmsleu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsleu.mask.nxv1i16( define @intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsleu.mask.nxv2i16( define @intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsleu.mask.nxv4i16( define @intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i16( define @intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vmsleu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsleu.mask.nxv16i16( define @intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vmsleu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsleu.mask.nxv1i32( define @intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsleu.mask.nxv2i32( define @intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i32( define @intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vmsleu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsleu.mask.nxv8i32( define @intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vmsleu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsleu.mask.nxv1i64( define @intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsleu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsleu.vv v0, v8, v9 ; CHECK-NEXT: vmsleu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsleu.mask.nxv2i64( define @intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsleu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v10 +; CHECK-NEXT: vmsleu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsleu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsleu.mask.nxv4i64( define @intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsleu_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsleu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsleu.vv v0, v8, v12 +; CHECK-NEXT: vmsleu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsleu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsleu.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll index 6783f7feb624c5674117d6c93b0a9cf32067242c..6c6e580b043d1aebc66e6c072cf9b783efe5bf53 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmslt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmslt.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmslt.mask.nxv1i8( define @intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmslt.mask.nxv2i8( define @intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmslt.mask.nxv4i8( define @intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmslt.mask.nxv8i8( define @intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmslt.mask.nxv16i8( define @intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmslt.mask.nxv32i8( define @intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmslt.mask.nxv1i16( define @intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmslt.mask.nxv2i16( define @intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmslt.mask.nxv4i16( define @intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i16( define @intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmslt.mask.nxv16i16( define @intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmslt.mask.nxv1i32( define @intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmslt.mask.nxv2i32( define @intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i32( define @intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmslt.mask.nxv8i32( define @intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmslt.mask.nxv1i64( define @intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmslt.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmslt.vv v0, v8, v9 ; CHECK-NEXT: vmslt.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmslt.mask.nxv2i64( define @intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmslt.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v10 +; CHECK-NEXT: vmslt.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmslt.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmslt.mask.nxv4i64( define @intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmslt_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmslt.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmslt.vv v0, v8, v12 +; CHECK-NEXT: vmslt.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmslt.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmslt.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll index b082b735a0207295ce4b6795573ba0dc72dfb294..76f3e449ab58f59ab8b22408bd8794b0b7f2ec57 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsltu.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsltu.mask.nxv1i8( define @intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsltu.mask.nxv2i8( define @intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsltu.mask.nxv4i8( define @intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsltu.mask.nxv8i8( define @intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsltu.mask.nxv16i8( define @intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vmsltu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsltu.mask.nxv32i8( define @intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vmsltu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsltu.mask.nxv1i16( define @intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsltu.mask.nxv2i16( define @intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsltu.mask.nxv4i16( define @intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i16( define @intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vmsltu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsltu.mask.nxv16i16( define @intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vmsltu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsltu.mask.nxv1i32( define @intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsltu.mask.nxv2i32( define @intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i32( define @intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vmsltu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsltu.mask.nxv8i32( define @intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vmsltu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsltu.mask.nxv1i64( define @intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsltu.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsltu.vv v0, v8, v9 ; CHECK-NEXT: vmsltu.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsltu.mask.nxv2i64( define @intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsltu.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v10 +; CHECK-NEXT: vmsltu.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsltu.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsltu.mask.nxv4i64( define @intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsltu_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsltu.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsltu.vv v0, v8, v12 +; CHECK-NEXT: vmsltu.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsltu.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsltu.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll index bb4575e5d72cbed8d8fb95e357a2f1b3eb8461b4..161c1bc4314fcbb688f3ec5af81976a02e0961b5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vmsne.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vmsne.ll @@ -34,10 +34,9 @@ declare @llvm.riscv.vmsne.mask.nxv1i8( define @intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -86,10 +85,9 @@ declare @llvm.riscv.vmsne.mask.nxv2i8( define @intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -138,10 +136,9 @@ declare @llvm.riscv.vmsne.mask.nxv4i8( define @intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -190,10 +187,9 @@ declare @llvm.riscv.vmsne.mask.nxv8i8( define @intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -242,12 +238,11 @@ declare @llvm.riscv.vmsne.mask.nxv16i8( define @intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: vmsne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vmsne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv16i8( @@ -294,12 +289,11 @@ declare @llvm.riscv.vmsne.mask.nxv32i8( define @intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: vmsne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vmsne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv32i8( @@ -346,10 +340,9 @@ declare @llvm.riscv.vmsne.mask.nxv1i16( define @intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -398,10 +391,9 @@ declare @llvm.riscv.vmsne.mask.nxv2i16( define @intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -450,10 +442,9 @@ declare @llvm.riscv.vmsne.mask.nxv4i16( define @intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -502,12 +493,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i16( define @intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: vmsne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vmsne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv8i16( @@ -554,12 +544,11 @@ declare @llvm.riscv.vmsne.mask.nxv16i16( define @intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: vmsne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vmsne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv16i16( @@ -606,10 +595,9 @@ declare @llvm.riscv.vmsne.mask.nxv1i32( define @intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv1r.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv1r.v v0, v11 ; CHECK-NEXT: ret @@ -658,10 +646,9 @@ declare @llvm.riscv.vmsne.mask.nxv2i32( define @intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -710,12 +697,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i32( define @intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: vmsne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vmsne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv4i32( @@ -762,12 +748,11 @@ declare @llvm.riscv.vmsne.mask.nxv8i32( define @intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: vmsne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vmsne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv8i32( @@ -814,10 +799,9 @@ declare @llvm.riscv.vmsne.mask.nxv1i64( define @intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: vmsne.vv v8, v8, v9 ; CHECK-NEXT: vmv1r.v v11, v0 -; CHECK-NEXT: vmv.v.v v0, v8 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu +; CHECK-NEXT: vmsne.vv v0, v8, v9 ; CHECK-NEXT: vmsne.vv v11, v9, v10, v0.t ; CHECK-NEXT: vmv.v.v v0, v11 ; CHECK-NEXT: ret @@ -866,12 +850,11 @@ declare @llvm.riscv.vmsne.mask.nxv2i64( define @intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v14, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: vmsne.vv v14, v8, v10 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v10 +; CHECK-NEXT: vmsne.vv v14, v10, v12, v0.t ; CHECK-NEXT: vmv1r.v v0, v14 -; CHECK-NEXT: vmsne.vv v8, v10, v12, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv2i64( @@ -918,12 +901,11 @@ declare @llvm.riscv.vmsne.mask.nxv4i64( define @intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vmsne_mask_vv_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vmv1r.v v20, v0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: vmsne.vv v20, v8, v12 -; CHECK-NEXT: vmv1r.v v8, v0 +; CHECK-NEXT: vmsne.vv v0, v8, v12 +; CHECK-NEXT: vmsne.vv v20, v12, v16, v0.t ; CHECK-NEXT: vmv1r.v v0, v20 -; CHECK-NEXT: vmsne.vv v8, v12, v16, v0.t -; CHECK-NEXT: vmv1r.v v0, v8 ; CHECK-NEXT: ret entry: %mask = call @llvm.riscv.vmsne.nxv4i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir index e8620c848f8d3d59509c8ce7920b6fc5a76d7e99..39f517a100f5273f3f1cc6df7bbe052099909d07 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert.mir @@ -1,6 +1,6 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc %s -o - -mtriple=riscv64 -mattr=v \ -# RUN: -run-pass=riscv-insert-vsetvli | FileCheck %s +# RUN: -run-pass=riscv-insert-vsetvli,riscv-coalesce-vsetvli | FileCheck %s --- | source_filename = "vsetvli-insert.ll" @@ -166,7 +166,7 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY2]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: PseudoRET implicit $v8 %2:gprnox0 = COPY $x11 @@ -208,7 +208,7 @@ body: | ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: [[PseudoVLE32_V_MF2_:%[0-9]+]]:vr = PseudoVLE32_V_MF2 %pt, [[COPY1]], $noreg, 5 /* e32 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: %dead:vr = IMPLICIT_DEF - ; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 %dead, killed [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: early-clobber %3:vr = PseudoVZEXT_VF2_M1 %dead, [[PseudoVLE32_V_MF2_]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY %3 ; CHECK-NEXT: PseudoRET implicit $v8 %1:gprnox0 = COPY $x11 @@ -282,8 +282,8 @@ body: | ; CHECK-NEXT: [[PseudoVLE64_V_M1_:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt, [[COPY1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.x) ; CHECK-NEXT: [[PseudoVLE64_V_M1_1:%[0-9]+]]:vr = PseudoVLE64_V_M1 %pt2, [[COPY]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype :: (load (s128) from %ir.y) ; CHECK-NEXT: %pt3:vr = IMPLICIT_DEF - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt3, killed [[PseudoVLE64_V_M1_]], killed [[PseudoVLE64_V_M1_1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: PseudoVSE64_V_M1 killed [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x) + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt3, [[PseudoVLE64_V_M1_]], [[PseudoVLE64_V_M1_1]], 2, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: PseudoVSE64_V_M1 [[PseudoVADD_VV_M1_]], [[COPY1]], 2, 6 /* e64 */, implicit $vl, implicit $vtype :: (store (s128) into %ir.x) ; CHECK-NEXT: PseudoRET %1:gpr = COPY $x11 %0:gpr = COPY $x10 @@ -328,8 +328,8 @@ body: | ; CHECK-NEXT: [[PseudoVMV_V_I_M1_:%[0-9]+]]:vr = PseudoVMV_V_I_M1 $noreg, 0, -1, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: [[DEF:%[0-9]+]]:vr = IMPLICIT_DEF ; CHECK-NEXT: dead $x0 = PseudoVSETIVLI 2, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF]], killed [[PseudoVLE64_V_M1_]], killed [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype - ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S killed [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype + ; CHECK-NEXT: [[PseudoVREDSUM_VS_M1_E8_:%[0-9]+]]:vr = PseudoVREDSUM_VS_M1_E8 [[DEF]], [[PseudoVLE64_V_M1_]], [[PseudoVMV_V_I_M1_]], 2, 6 /* e64 */, 1 /* ta, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVMV_X_S:%[0-9]+]]:gpr = PseudoVMV_X_S [[PseudoVREDSUM_VS_M1_E8_]], 6 /* e64 */, implicit $vtype ; CHECK-NEXT: $x10 = COPY [[PseudoVMV_X_S]] ; CHECK-NEXT: PseudoRET implicit $x10 %0:gpr = COPY $x10 @@ -418,7 +418,7 @@ body: | ; CHECK-NEXT: INLINEASM &"", 1 /* sideeffect attdialect */ ; CHECK-NEXT: %pt2:vr = IMPLICIT_DEF ; CHECK-NEXT: dead $x0 = PseudoVSETVLI [[COPY]], 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype - ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, killed [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype + ; CHECK-NEXT: [[PseudoVADD_VV_M1_:%[0-9]+]]:vr = PseudoVADD_VV_M1 %pt2, [[PseudoVLE64_V_M1_]], [[COPY1]], $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $v8 = COPY [[PseudoVADD_VV_M1_]] ; CHECK-NEXT: PseudoRET implicit $v8 %2:gprnox0 = COPY $x11 diff --git a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir index d0b76e7e4535b8d925072ed4beaea954692cd11f..fcd852f1210df545477a9ea9ae47a124c7e49c95 100644 --- a/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir +++ b/llvm/test/CodeGen/RISCV/rvv/zvlsseg-spill.mir @@ -27,7 +27,7 @@ body: | ; CHECK-NEXT: $x12 = frame-setup SLLI killed $x12, 3 ; CHECK-NEXT: $x2 = frame-setup SUB $x2, killed $x12 ; CHECK-NEXT: frame-setup CFI_INSTRUCTION escape 0x0f, 0x0d, 0x72, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0xa2, 0x38, 0x00, 0x1e, 0x22 - ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 152 /* e64, m1, tu, ma */, implicit-def $vl, implicit-def $vtype + ; CHECK-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x11, 216 /* e64, m1, ta, ma */, implicit-def $vl, implicit-def $vtype ; CHECK-NEXT: $v0_v1_v2_v3_v4_v5_v6 = PseudoVLSEG7E64_V_M1 undef $v0_v1_v2_v3_v4_v5_v6, renamable $x10, $noreg, 6 /* e64 */, 0 /* tu, mu */, implicit $vl, implicit $vtype ; CHECK-NEXT: $x11 = ADDI $x2, 16 ; CHECK-NEXT: $x12 = PseudoReadVLENB diff --git a/llvm/test/CodeGen/RISCV/xaluo.ll b/llvm/test/CodeGen/RISCV/xaluo.ll index 1a88563c0ea2ede3c37a450189b74544b9005c7f..b1efe53290e8ee142bf492a1a53a94cdfcbdd961 100644 --- a/llvm/test/CodeGen/RISCV/xaluo.ll +++ b/llvm/test/CodeGen/RISCV/xaluo.ll @@ -1759,9 +1759,9 @@ define zeroext i1 @umulo2.i32(i32 signext %v1, ptr %res) { ; ; RV64ZBA-LABEL: umulo2.i32: ; RV64ZBA: # %bb.0: # %entry -; RV64ZBA-NEXT: zext.w a0, a0 -; RV64ZBA-NEXT: sh1add a2, a0, a0 -; RV64ZBA-NEXT: sh2add a2, a2, a0 +; RV64ZBA-NEXT: zext.w a2, a0 +; RV64ZBA-NEXT: sh1add.uw a0, a0, a2 +; RV64ZBA-NEXT: sh2add a2, a0, a2 ; RV64ZBA-NEXT: srli a0, a2, 32 ; RV64ZBA-NEXT: snez a0, a0 ; RV64ZBA-NEXT: sw a2, 0(a1) diff --git a/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll new file mode 100644 index 0000000000000000000000000000000000000000..ac72ec28c37d9d77f9a9beb16ad9de9700ba1c35 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/pointers/argument-ptr-to-struct.ll @@ -0,0 +1,37 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#VOID:]] = OpTypeVoid +; CHECK-DAG: %[[#FLOAT:]] = OpTypeFloat 32 +; CHECK-DAG: %[[#UCHAR:]] = OpTypeInt 8 0 +; CHECK-DAG: %[[#UINT:]] = OpTypeInt 32 0 +; CHECK-DAG: %[[#STRUCT_S:]] = OpTypeStruct %[[#FLOAT]] %[[#UCHAR]] %[[#UINT]] +; CHECK-DAG: %[[#PTR_STRUCT_S:]] = OpTypePointer Function %[[#STRUCT_S]] +; CHECK-DAG: %[[#FUNC_TYPE_K:]] = OpTypeFunction %[[#VOID]] %[[#PTR_STRUCT_S]] +; CHECK-DAG: %[[#FUNC_TYPE_H:]] = OpTypeFunction %[[#UINT]] %[[#PTR_STRUCT_S]] + +; CHECK: %[[#]] = OpFunction %[[#VOID]] None %[[#FUNC_TYPE_K]] +; CHECK: %[[#]] = OpFunctionParameter %[[#PTR_STRUCT_S]] + +; CHECK: %[[#]] = OpFunction %[[#UINT]] None %[[#FUNC_TYPE_H]] +; CHECK: %[[#]] = OpFunctionParameter %[[#PTR_STRUCT_S]] + +%struct.s = type { float, i8, i32 } + +define spir_kernel void @k(ptr noundef byval(%struct.s) align 4 %x) { +entry: + %c = getelementptr inbounds %struct.s, ptr %x, i32 0, i32 2 + %l = load i32, ptr %c, align 4 + %add = add nsw i32 %l, 1 + %c1 = getelementptr inbounds %struct.s, ptr %x, i32 0, i32 2 + store i32 %add, ptr %c1, align 4 + ret void +} + +define spir_func i32 @h(ptr noundef byval(%struct.s) align 4 %x) { +entry: + %c = getelementptr inbounds %struct.s, ptr %x, i32 0, i32 2 + %l = load i32, ptr %c, align 4 + %add = add nsw i32 %l, 1 + ret i32 %add +} diff --git a/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll new file mode 100644 index 0000000000000000000000000000000000000000..d0c64b4353ec684d5963d9230cc4f9a02551c155 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/pointers/global-ptrtoint.ll @@ -0,0 +1,28 @@ +; This test is to check that correct virtual register type is created after ptrtoint. + +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: OpName %[[GlobalValue:.*]] "dev_global" +; CHECK-DAG: %[[TyI64:.*]] = OpTypeInt 64 0 +; CHECK-DAG: %[[TyStruct:.*]] = OpTypeStruct %[[TyI64]] %[[TyI64]] +; CHECK-DAG: %[[Const128:.*]] = OpConstant %[[TyI64]] 128 +; CHECK-DAG: %[[GlobalValue]] = OpVariable +; CHECK-DAG: %[[PtrToInt:.*]] = OpSpecConstantOp %[[TyI64]] 117 %12 +; TODO: The following bitcast line looks unneeded and we may expect it to be removed in future +; CHECK-DAG: %[[UseGlobalValue:.*]] = OpSpecConstantOp %[[TyI64]] 124 %[[PtrToInt]] +; CHECK-DAG: %[[ConstComposite:.*]] = OpConstantComposite %[[TyStruct]] %[[Const128]] %[[UseGlobalValue]] +; CHECK-DAG: %[[TyPtrStruct:.*]] = OpTypePointer CrossWorkgroup %[[TyStruct]] +; CHECK: OpVariable %[[TyPtrStruct]] CrossWorkgroup %[[ConstComposite]] +; CHECK: OpFunction + +@dev_global = addrspace(1) global [2 x i32] zeroinitializer +@__AsanDeviceGlobalMetadata = addrspace(1) global { i64, i64 } { i64 128, i64 ptrtoint (ptr addrspace(1) @dev_global to i64) } + +define void @foo() { +entry: + ret void +} diff --git a/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll new file mode 100644 index 0000000000000000000000000000000000000000..034feed72dc7bc9217f4bbe2d6f69917ec7edc21 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/pointers/variables-storage-class.ll @@ -0,0 +1,19 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +@Ptr = addrspace(1) global ptr addrspace(1) null +@Init = private addrspace(2) constant i32 123 + +; CHECK-DAG: %[[#PTR:]] = OpVariable %[[#]] UniformConstant %[[#]] +; CHECK-DAG: %[[#INIT:]] = OpVariable %[[#]] CrossWorkgroup %[[#]] + +; CHECK: %[[#]] = OpLoad %[[#]] %[[#INIT]] Aligned 8 +; CHECK: OpCopyMemorySized %[[#]] %[[#PTR]] %[[#]] Aligned 4 + +define spir_kernel void @Foo() { + %l = load ptr addrspace(1), ptr addrspace(1) @Ptr, align 8 + call void @llvm.memcpy.p1.p2.i64(ptr addrspace(1) align 4 %l, ptr addrspace(2) align 1 @Init, i64 4, i1 false) + ret void +} + +declare void @llvm.memcpy.p1.p2.i64(ptr addrspace(1) noalias nocapture writeonly, ptr addrspace(2) noalias nocapture readonly, i64, i1 immarg) diff --git a/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll b/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll index ea0197548a8154926059530bf15d3ea92d0b758d..89fa93b4fcda1cbb8b73e34aca020dbc0b445439 100644 --- a/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll +++ b/llvm/test/CodeGen/SPIRV/transcoding/memcpy-zext.ll @@ -3,8 +3,7 @@ ; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s --check-prefixes=CHECK,CHECK-64 ; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} -; CHECK-64-DAG: %[[#i64:]] = OpTypeInt 64 0 - +; CHECK-DAG: %[[#i64:]] = OpTypeInt 64 0 ; CHECK-DAG: %[[#i8:]] = OpTypeInt 8 0 ; CHECK-DAG: %[[#i32:]] = OpTypeInt 32 0 ; CHECK-DAG: %[[#one:]] = OpConstant %[[#i32]] 1 @@ -14,19 +13,28 @@ ; CHECK-DAG: %[[#test_arr_init:]] = OpConstantComposite %[[#i32x3]] %[[#one]] %[[#two]] %[[#three]] ; CHECK-DAG: %[[#szconst1024:]] = OpConstant %[[#i32]] 1024 ; CHECK-DAG: %[[#szconst42:]] = OpConstant %[[#i8]] 42 +; CHECK-DAG: %[[#szconst123:]] = OpConstant %[[#i64]] 123 ; CHECK-DAG: %[[#const_i32x3_ptr:]] = OpTypePointer UniformConstant %[[#i32x3]] ; CHECK-DAG: %[[#test_arr:]] = OpVariable %[[#const_i32x3_ptr]] UniformConstant %[[#test_arr_init]] ; CHECK-DAG: %[[#i32x3_ptr:]] = OpTypePointer Function %[[#i32x3]] ; CHECK: %[[#arr:]] = OpVariable %[[#i32x3_ptr]] Function ; CHECK-32: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconst1024]] -; CHECK-64: %[[#szconstext1024:]] = OpUConvert %[[#i64:]] %[[#szconst1024:]] -; CHECK-64: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconstext1024]] - ; CHECK-32: %[[#szconstext42:]] = OpUConvert %[[#i32:]] %[[#szconst42:]] ; CHECK-32: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconstext42]] +; CHECK-32: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconst123]] + +; If/when Backend stoped rewrite actual reg size of i8/i16/i32/i64 with i32, +; i32 = G_TRUNC i64 would appear for the 32-bit target, switching the following +; TODO patterns instead of the last line above. +; TODO: %[[#szconstext123:]] = OpUConvert %[[#i32:]] %[[#szconst123:]] +; TODO: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconst123]] + +; CHECK-64: %[[#szconstext1024:]] = OpUConvert %[[#i64:]] %[[#szconst1024:]] +; CHECK-64: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconstext1024]] ; CHECK-64: %[[#szconstext42:]] = OpUConvert %[[#i64:]] %[[#szconst42:]] ; CHECK-64: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconstext42]] +; CHECK-64: OpCopyMemorySized %[[#arr]] %[[#test_arr]] %[[#szconst123]] @__const.test.arr = private unnamed_addr addrspace(2) constant [3 x i32] [i32 1, i32 2, i32 3] @@ -36,8 +44,10 @@ entry: %dest = bitcast ptr %arr to ptr call void @llvm.memcpy.p0.p2.i32(ptr align 4 %dest, ptr addrspace(2) align 4 @__const.test.arr, i32 1024, i1 false) call void @llvm.memcpy.p0.p2.i8(ptr align 4 %dest, ptr addrspace(2) align 4 @__const.test.arr, i8 42, i1 false) + call void @llvm.memcpy.p0.p2.i64(ptr align 4 %dest, ptr addrspace(2) align 4 @__const.test.arr, i64 123, i1 false) ret void } declare void @llvm.memcpy.p0.p2.i32(ptr nocapture writeonly, ptr addrspace(2) nocapture readonly, i32, i1) declare void @llvm.memcpy.p0.p2.i8(ptr nocapture writeonly, ptr addrspace(2) nocapture readonly, i8, i1) +declare void @llvm.memcpy.p0.p2.i64(ptr nocapture writeonly, ptr addrspace(2) nocapture readonly, i64, i1) diff --git a/llvm/test/CodeGen/SPIRV/types/or-i1.ll b/llvm/test/CodeGen/SPIRV/types/or-i1.ll new file mode 100644 index 0000000000000000000000000000000000000000..32dc258d85554fd10db67a8f224529941923b10f --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/types/or-i1.ll @@ -0,0 +1,17 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#BOOL:]] = OpTypeBool +; CHECK: %[[#BOOL:]] = OpLogicalOr %[[#BOOL]] %[[#]] %[[#]] + +define spir_kernel void @foo( + ptr addrspace(1) nocapture noundef writeonly %Dst, + i32 %a, i32 %b) local_unnamed_addr #0 { +entry: + %a1 = trunc i32 %a to i1 + %b1 = trunc i32 %b to i1 + %ab1 = or i1 %a1, %b1 + %ab32 = zext i1 %ab1 to i32 + store i32 %ab32, ptr addrspace(1) %Dst + ret void +} diff --git a/llvm/test/CodeGen/Xtensa/call.ll b/llvm/test/CodeGen/Xtensa/call.ll new file mode 100644 index 0000000000000000000000000000000000000000..24c7c4f558e1388be7b3596cdcbce2f3ba222748 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/call.ll @@ -0,0 +1,49 @@ +; RUN: llc --mtriple=xtensa < %s | FileCheck %s + +declare i32 @external_function(i32) + +define i32 @test_call_external(i32 %a) nounwind { +; CHECK-LABEL: test_call_external: +; CHECK: # %bb.0: +; CHECK-NEXT: s32i a0, a1, 0 +; CHECK-NEXT: l32r a8, .LCPI0_0 +; CHECK-NEXT: callx0 a8 +; CHECK-NEXT: l32i a0, a1, 0 +; CHECK-NEXT: ret + %1 = call i32 @external_function(i32 %a) + ret i32 %1 +} + +define i32 @defined_function(i32 %a) nounwind { +; CHECK-LABEL: defined_function: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a2, a2, 1 +; CHECK-NEXT: ret + %1 = add i32 %a, 1 + ret i32 %1 +} + +define i32 @test_call_defined(i32 %a) nounwind { +; CHECK-LABEL: test_call_defined: +; CHECK: # %bb.0: +; CHECK-NEXT: s32i a0, a1, 0 +; CHECK-NEXT: l32r a8, .LCPI2_0 +; CHECK-NEXT: callx0 a8 +; CHECK-NEXT: l32i a0, a1, 0 +; CHECK-NEXT: ret + %1 = call i32 @defined_function(i32 %a) nounwind + ret i32 %1 +} + +define i32 @test_call_indirect(ptr %a, i32 %b) nounwind { +; CHECK-LABEL: test_call_indirect: +; CHECK: # %bb.0: +; CHECK-NEXT: s32i a0, a1, 0 +; CHECK-NEXT: or a8, a2, a2 +; CHECK-NEXT: or a2, a3, a3 +; CHECK-NEXT: callx0 a8 +; CHECK-NEXT: l32i a0, a1, 0 +; CHECK-NEXT: ret + %1 = call i32 %a(i32 %b) + ret i32 %1 +} diff --git a/llvm/test/CodeGen/Xtensa/calling-conv.ll b/llvm/test/CodeGen/Xtensa/calling-conv.ll new file mode 100644 index 0000000000000000000000000000000000000000..41ae4220145c27c6e44bc4a56cca72490d898328 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/calling-conv.ll @@ -0,0 +1,78 @@ +; RUN: llc -mtriple=xtensa -O1 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=XTENSA + +; Check placement of first 6 arguments in registers and 7th argument on stack +define dso_local i32 @test1(i32 noundef %0, i32 noundef %1, i32 noundef %2, i32 noundef %3, i32 noundef %4, i32 noundef %5, ptr nocapture noundef readonly byval(i32) align 4 %6) { +; XTENSA-LABEL: @test1 +; XTENSA: add a8, a7, a2 +; XTENSA: l32i a9, a1, 0 +; XTENSA: add a2, a8, a9 +; XTENSA: ret + %8 = load i32, ptr %6, align 4 + %9 = add nsw i32 %5, %0 + %10 = add nsw i32 %9, %8 + ret i32 %10 +} + +; Check placement of second i64 argument in registers +define dso_local i32 @test2(i32 noundef %0, i64 noundef %1, i32 noundef %2) { +; XTENSA-LABEL: @test2 +; XTENSA: add a8, a6, a2 +; XTENSA: add a2, a8, a4 +; XTENSA: ret + %4 = trunc i64 %1 to i32 + %5 = add nsw i32 %2, %0 + %6 = add nsw i32 %5, %4 + ret i32 %6 +} + +; Check placement of first argument typeof i8 in register +define dso_local i32 @test3(i8 noundef signext %0, i64 noundef %1, i32 noundef %2) { +; XTENSA-LABEL: @test3 +; XTENSA: add a8, a2, a6 +; XTENSA: add a2, a8, a4 +; XTENSA: ret + %4 = trunc i64 %1 to i32 + %5 = sext i8 %0 to i32 + %6 = add nsw i32 %5, %2 + %7 = add nsw i32 %6, %4 + ret i32 %7 +} + +; Check placement of 4th argument typeof i64 on stack +define dso_local i32 @test4(i8 noundef signext %0, i64 noundef %1, i32 noundef %2, ptr nocapture noundef readonly byval(i64) align 8 %3) { +; XTENSA-LABEL: @test4 +; XTENSA: add a8, a2, a6 +; XTENSA: add a8, a8, a4 +; XTENSA: l32i a9, a1, 0 +; XTENSA: add a2, a8, a9 +; XTENSA: ret + %5 = load i64, ptr %3, align 8 + %6 = trunc i64 %1 to i32 + %7 = trunc i64 %5 to i32 + %8 = sext i8 %0 to i32 + %9 = add nsw i32 %8, %2 + %10 = add nsw i32 %9, %6 + %11 = add nsw i32 %10, %7 + ret i32 %11 +} + +; Check placement of 128 bit structure on registers +define dso_local i32 @test5([4 x i32] %0, i32 noundef %1) { +; XTENSA-LABEL: @test5 +; XTENSA: add a2, a2, a6 +; XTENSA: ret + %3 = extractvalue [4 x i32] %0, 0 + %4 = add nsw i32 %3, %1 + ret i32 %4 +} + +; Check placement of 128 bit structure on stack +define dso_local i32 @test6(i32 noundef %0, [4 x i32] %1) { +; XTENSA-LABEL: @test6 +; XTENSA: add a2, a3, a2 +; XTENSA: ret + %3 = extractvalue [4 x i32] %1, 0 + %4 = add nsw i32 %3, %0 + ret i32 %4 +} diff --git a/llvm/test/CodeGen/Xtensa/constantpool.ll b/llvm/test/CodeGen/Xtensa/constantpool.ll new file mode 100644 index 0000000000000000000000000000000000000000..9b380d2c37b9e0012d3767e85ec7f40ac408b043 --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/constantpool.ll @@ -0,0 +1,28 @@ +; RUN: llc -mtriple=xtensa -verify-machineinstrs < %s \ +; RUN: | FileCheck %s + +; Test placement of the i32,i64, float and double constants in constantpool + +define dso_local i32 @const_i32() #0 { +; CHECK: .literal_position +; CHECK-NEXT: .literal .LCPI0_0, 74565 +; CHECK-LABEL: const_i32: +; CHECK: l32r a2, .LCPI0_0 + %1 = alloca i32, align 4 + store i32 74565, ptr %1, align 4 + %2 = load i32, ptr %1, align 4 + ret i32 %2 +} + +define dso_local i64 @const_int64() #0 { +; CHECK: .literal_position +; CHECK-NEXT: .literal .LCPI1_0, 305419896 +; CHECK-NEXT: .literal .LCPI1_1, -1859959449 +; CHECK-LABEL: const_int64: +; CHECK: l32r a3, .LCPI1_0 +; CHECK: l32r a2, .LCPI1_1 + %1 = alloca i64, align 8 + store i64 1311768467302729063, ptr %1, align 8 + %2 = load i64, ptr %1, align 8 + ret i64 %2 +} diff --git a/llvm/test/CodeGen/Xtensa/stack-access.ll b/llvm/test/CodeGen/Xtensa/stack-access.ll new file mode 100644 index 0000000000000000000000000000000000000000..1590d24f228f2e1636e8e007f3becebc3fc80c5e --- /dev/null +++ b/llvm/test/CodeGen/Xtensa/stack-access.ll @@ -0,0 +1,35 @@ +; RUN: llc -mtriple=xtensa -O0 -verify-machineinstrs < %s \ +; RUN: | FileCheck %s -check-prefix=XTENSA + +define i8 @loadi8(i8 %a) { +; XTENSA-LABEL: loadi8: +; XTENSA: s8i a2, a1, 3 +; XTENSA: l8ui a2, a1, 3 +; XTENSA: ret + %b = alloca i8, align 1 + store i8 %a, ptr %b, align 1 + %1 = load i8, ptr %b, align 1 + ret i8 %1 +} + +define i16 @loadi16(i16 %a) { +; XTENSA-LABEL: loadi16: +; XTENSA: s16i a2, a1, 2 +; XTENSA: l16ui a2, a1, 2 +; XTENSA: ret + %b = alloca i16, align 2 + store i16 %a, ptr %b, align 2 + %1 = load i16, ptr %b, align 2 + ret i16 %1 +} + +define i32 @loadi32(i32 %a) { +; XTENSA-LABEL: loadi32: +; XTENSA: s32i a2, a1, 0 +; XTENSA: l32i a2, a1, 0 +; XTENSA: ret + %b = alloca i32, align 4 + store i32 %a, ptr %b, align 4 + %1 = load i32, ptr %b, align 4 + ret i32 %1 +} diff --git a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll index d6a1d8d6e1366fa1b2768f4e8021015c76036b1e..d28836d560377e213d7e699c7a686d5078a40097 100644 --- a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll +++ b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll @@ -18,21 +18,21 @@ ; RELOCS-BOTH: Section ({{.*}}) .rela.debug_frame { ; RELOCS-NORL-NEXT: 0x1C R_LARCH_32 .debug_frame 0x0 ; RELOCS-NORL-NEXT: 0x20 R_LARCH_64 .text 0x0 -; RELOCS-ENRL-NEXT: 0x1C R_LARCH_32 0x0 -; RELOCS-ENRL-NEXT: 0x20 R_LARCH_64 0x0 -; RELOCS-ENRL-NEXT: 0x28 R_LARCH_ADD64 0x0 -; RELOCS-ENRL-NEXT: 0x28 R_LARCH_SUB64 0x0 -; RELOCS-ENRL-NEXT: 0x3F R_LARCH_ADD6 0x0 -; RELOCS-ENRL-NEXT: 0x3F R_LARCH_SUB6 0x0 +; RELOCS-ENRL-NEXT: 0x1C R_LARCH_32 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x20 R_LARCH_64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x28 R_LARCH_ADD64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x28 R_LARCH_SUB64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x3F R_LARCH_ADD6 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x3F R_LARCH_SUB6 .L0 0x0 ; RELOCS-BOTH-NEXT: } ; RELOCS-BOTH: Section ({{.*}}) .rela.debug_line { ; RELOCS-BOTH-NEXT: 0x22 R_LARCH_32 .debug_line_str 0x0 ; RELOCS-BOTH-NEXT: 0x31 R_LARCH_32 .debug_line_str 0x2 ; RELOCS-BOTH-NEXT: 0x46 R_LARCH_32 .debug_line_str 0x1B ; RELOCS-NORL-NEXT: 0x4F R_LARCH_64 .text 0x0 -; RELOCS-ENRL-NEXT: 0x4F R_LARCH_64 0x0 -; RELOCS-ENRL-NEXT: 0x5F R_LARCH_ADD16 0x0 -; RELOCS-ENRL-NEXT: 0x5F R_LARCH_SUB16 0x0 +; RELOCS-ENRL-NEXT: 0x4F R_LARCH_64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x5F R_LARCH_ADD16 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x5F R_LARCH_SUB16 .L0 0x0 ; RELOCS-BOTH-NEXT: } ; RELOCS-BOTH-NEXT: ] diff --git a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll index e5de1713f4e00df6dbc350757e351d2b10906e2d..99594b5e01e955c9f959dd1e5d44debd4416f77b 100644 --- a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll +++ b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll @@ -6,14 +6,14 @@ ; Check that we actually have relocations, otherwise this is kind of pointless. ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_info { -; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 0x0 -; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 0x0 +; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 .L0 0x0 +; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 .L0 0x0 ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_frame { -; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 0x0 -; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 0x0 +; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 .L0 0x0 +; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_line { -; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 0x0 -; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 0x0 +; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 .L0 0x0 +; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 .L0 0x0 ; Check that we can print the source, even with relocations. ; OBJDUMP-SOURCE: Disassembly of section .text: diff --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll index f655a7c0a7ef42a64e5d861636b72d60fe1ba37f..ffef0ec2340684a43ac466349365af984ca64086 100644 --- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll +++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll @@ -4,11 +4,11 @@ ; RUN: | FileCheck -check-prefix=RELAX-DWARFDUMP %s ; ; RELAX: Section ({{.*}}) .rela.eh_frame { -; RELAX-NEXT: 0x1C R_RISCV_32_PCREL 0x0 -; RELAX-NEXT: 0x30 R_RISCV_32_PCREL 0x0 -; RELAX-NEXT: 0x44 R_RISCV_32_PCREL 0x0 -; RELAX-NEXT: 0x48 R_RISCV_ADD32 0x0 -; RELAX-NEXT: 0x48 R_RISCV_SUB32 0x0 +; RELAX-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 +; RELAX-NEXT: 0x30 R_RISCV_32_PCREL .L0 0x0 +; RELAX-NEXT: 0x44 R_RISCV_32_PCREL .L0 0x0 +; RELAX-NEXT: 0x48 R_RISCV_ADD32 .L0 0x0 +; RELAX-NEXT: 0x48 R_RISCV_SUB32 .L0 0x0 ; RELAX-NEXT: } ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation diff --git a/llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s b/llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s similarity index 71% rename from llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s rename to llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s index 1e0fa8a3061830cad60f06edf716a5cda98759c5..0b54f104ab953e0b4a9e0d2742ba1d47f044a9be 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s @@ -1,10 +1,11 @@ # REQUIRES: riscv-registered-target -## Ignore empty name symbols. +## Ignore .L0 symbols that are generated by LLVM integrated assembler and GNU +## assembler for .debug_line/.eh_frame related assembler directives. # RUN: llvm-mc -filetype=obj -triple=riscv64 %s -o %t # RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=SYM -# SYM: 0000000000000004 0 NOTYPE LOCAL DEFAULT [[#]] {{$}} +# SYM: 0000000000000004 0 NOTYPE LOCAL DEFAULT [[#]] .L0 {{$}} # SYM: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [[#]] foo ## Make sure we test at an address larger than or equal to an empty name symbol. diff --git a/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s b/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s index a5038022dfe0c38990cf06aad694e2f42d6f3d60..e7114e4d643c6f65880697ebc3fb4843770257b5 100644 --- a/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s +++ b/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s @@ -7,7 +7,7 @@ # the section start and section end. So that by relocating these symbol, the section length # can be calculated. # -# CHECK: Creating defined graph symbol for ELF symbol "" +# CHECK: Creating defined graph symbol for ELF symbol ".L0 " # CHECK: Creating defined graph symbol for ELF symbol "main" .text .globl main diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll b/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll index 5dededaccaad0d1e24b8c5db56470a0206559006..4212293f42545e22bbfdf75865c2cb6d6fdb2a8c 100644 --- a/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/basic.ll @@ -9,8 +9,6 @@ ; RUN: opt < %s -passes=hwasan -hwasan-recover=0 -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=ABORT-ZERO-BASED-SHADOW ; RUN: opt < %s -passes=hwasan -hwasan-recover=1 -hwasan-mapping-offset=0 -S | FileCheck %s --check-prefixes=RECOVER-ZERO-BASED-SHADOW -; CHECK: @llvm.used = appending global [1 x ptr] [ptr @hwasan.module_ctor] -; CHECK: @llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 0, ptr @hwasan.module_ctor, ptr @hwasan.module_ctor }] target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" target triple = "aarch64--linux-android10000" @@ -101,7 +99,7 @@ define i8 @test_load8(ptr %a) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 0) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 0, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret i8 [[B]] ; @@ -233,7 +231,7 @@ define i16 @test_load16(ptr %a) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 1) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 1, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: [[B:%.*]] = load i16, ptr [[A]], align 4 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret i16 [[B]] ; @@ -365,7 +363,7 @@ define i32 @test_load32(ptr %a) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 2) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 2, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: [[B:%.*]] = load i32, ptr [[A]], align 4 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret i32 [[B]] ; @@ -497,7 +495,7 @@ define i64 @test_load64(ptr %a) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 3) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 3, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: [[B:%.*]] = load i64, ptr [[A]], align 8 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret i64 [[B]] ; @@ -629,7 +627,7 @@ define i128 @test_load128(ptr %a) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 4) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 4, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: [[B:%.*]] = load i128, ptr [[A]], align 16 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret i128 [[B]] ; @@ -830,7 +828,7 @@ define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 16) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 16, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: store i8 [[B]], ptr [[A]], align 4 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret void ; @@ -962,7 +960,7 @@ define void @test_store16(ptr %a, i16 %b) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 17) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 17, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: store i16 [[B]], ptr [[A]], align 4 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret void ; @@ -1094,7 +1092,7 @@ define void @test_store32(ptr %a, i32 %b) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 18) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 18, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: store i32 [[B]], ptr [[A]], align 4 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret void ; @@ -1226,7 +1224,7 @@ define void @test_store64(ptr %a, i64 %b) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 19) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 19, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: store i64 [[B]], ptr [[A]], align 8 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret void ; @@ -1358,7 +1356,7 @@ define void @test_store128(ptr %a, i128 %b) sanitize_hwaddress { ; ABORT-ZERO-BASED-SHADOW-SAME: (ptr [[A:%.*]], i128 [[B:%.*]]) #[[ATTR0]] { ; ABORT-ZERO-BASED-SHADOW-NEXT: entry: ; ABORT-ZERO-BASED-SHADOW-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 20) +; ABORT-ZERO-BASED-SHADOW-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 20, i64 0) ; ABORT-ZERO-BASED-SHADOW-NEXT: store i128 [[B]], ptr [[A]], align 16 ; ABORT-ZERO-BASED-SHADOW-NEXT: ret void ; diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll b/llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll new file mode 100644 index 0000000000000000000000000000000000000000..980189c5607f31ea9e96d25f5c4e2bf521232b9d --- /dev/null +++ b/llvm/test/Instrumentation/HWAddressSanitizer/fixed-shadow.ll @@ -0,0 +1,229 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 2 +; Test basic address sanitizer instrumentation. +; +; RUN: opt < %s -passes=hwasan -hwasan-mapping-offset=4398046511104 -S | FileCheck %s + + +target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" +target triple = "aarch64--linux-android9001" + +define i8 @test_load8(ptr %a) sanitize_hwaddress { +; CHECK-LABEL: define i8 @test_load8 +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 0, i64 4398046511104) +; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 +; CHECK-NEXT: ret i8 [[B]] +; +entry: + %b = load i8, ptr %a, align 4 + ret i8 %b +} + +define i16 @test_load16(ptr %a) sanitize_hwaddress { +; CHECK-LABEL: define i16 @test_load16 +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 1, i64 4398046511104) +; CHECK-NEXT: [[B:%.*]] = load i16, ptr [[A]], align 4 +; CHECK-NEXT: ret i16 [[B]] +; +entry: + %b = load i16, ptr %a, align 4 + ret i16 %b +} + +define i32 @test_load32(ptr %a) sanitize_hwaddress { +; CHECK-LABEL: define i32 @test_load32 +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 2, i64 4398046511104) +; CHECK-NEXT: [[B:%.*]] = load i32, ptr [[A]], align 4 +; CHECK-NEXT: ret i32 [[B]] +; +entry: + %b = load i32, ptr %a, align 4 + ret i32 %b +} + +define i64 @test_load64(ptr %a) sanitize_hwaddress { +; CHECK-LABEL: define i64 @test_load64 +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 3, i64 4398046511104) +; CHECK-NEXT: [[B:%.*]] = load i64, ptr [[A]], align 8 +; CHECK-NEXT: ret i64 [[B]] +; +entry: + %b = load i64, ptr %a, align 8 + ret i64 %b +} + +define i128 @test_load128(ptr %a) sanitize_hwaddress { +; CHECK-LABEL: define i128 @test_load128 +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 4, i64 4398046511104) +; CHECK-NEXT: [[B:%.*]] = load i128, ptr [[A]], align 16 +; CHECK-NEXT: ret i128 [[B]] +; +entry: + %b = load i128, ptr %a, align 16 + ret i128 %b +} + +define i40 @test_load40(ptr %a) sanitize_hwaddress { +; CHECK-LABEL: define i40 @test_load40 +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: call void @__hwasan_loadN(i64 [[TMP0]], i64 5) +; CHECK-NEXT: [[B:%.*]] = load i40, ptr [[A]], align 4 +; CHECK-NEXT: ret i40 [[B]] +; +entry: + %b = load i40, ptr %a, align 4 + ret i40 %b +} + +define void @test_store8(ptr %a, i8 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store8 +; CHECK-SAME: (ptr [[A:%.*]], i8 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 16, i64 4398046511104) +; CHECK-NEXT: store i8 [[B]], ptr [[A]], align 4 +; CHECK-NEXT: ret void +; +entry: + store i8 %b, ptr %a, align 4 + ret void +} + +define void @test_store16(ptr %a, i16 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store16 +; CHECK-SAME: (ptr [[A:%.*]], i16 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 17, i64 4398046511104) +; CHECK-NEXT: store i16 [[B]], ptr [[A]], align 4 +; CHECK-NEXT: ret void +; +entry: + store i16 %b, ptr %a, align 4 + ret void +} + +define void @test_store32(ptr %a, i32 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store32 +; CHECK-SAME: (ptr [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 18, i64 4398046511104) +; CHECK-NEXT: store i32 [[B]], ptr [[A]], align 4 +; CHECK-NEXT: ret void +; +entry: + store i32 %b, ptr %a, align 4 + ret void +} + +define void @test_store64(ptr %a, i64 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store64 +; CHECK-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 19, i64 4398046511104) +; CHECK-NEXT: store i64 [[B]], ptr [[A]], align 8 +; CHECK-NEXT: ret void +; +entry: + store i64 %b, ptr %a, align 8 + ret void +} + +define void @test_store128(ptr %a, i128 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store128 +; CHECK-SAME: (ptr [[A:%.*]], i128 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 20, i64 4398046511104) +; CHECK-NEXT: store i128 [[B]], ptr [[A]], align 16 +; CHECK-NEXT: ret void +; +entry: + store i128 %b, ptr %a, align 16 + ret void +} + +define void @test_store40(ptr %a, i40 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store40 +; CHECK-SAME: (ptr [[A:%.*]], i40 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 5) +; CHECK-NEXT: store i40 [[B]], ptr [[A]], align 4 +; CHECK-NEXT: ret void +; +entry: + store i40 %b, ptr %a, align 4 + ret void +} + +define void @test_store_unaligned(ptr %a, i64 %b) sanitize_hwaddress { +; CHECK-LABEL: define void @test_store_unaligned +; CHECK-SAME: (ptr [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr inttoptr (i64 4398046511104 to ptr)) +; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: call void @__hwasan_storeN(i64 [[TMP0]], i64 8) +; CHECK-NEXT: store i64 [[B]], ptr [[A]], align 4 +; CHECK-NEXT: ret void +; +entry: + store i64 %b, ptr %a, align 4 + ret void +} + +define i8 @test_load_noattr(ptr %a) { +; CHECK-LABEL: define i8 @test_load_noattr +; CHECK-SAME: (ptr [[A:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 +; CHECK-NEXT: ret i8 [[B]] +; +entry: + %b = load i8, ptr %a, align 4 + ret i8 %b +} + +define i8 @test_load_notmyattr(ptr %a) sanitize_address { +; CHECK-LABEL: define i8 @test_load_notmyattr +; CHECK-SAME: (ptr [[A:%.*]]) #[[ATTR1:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[B:%.*]] = load i8, ptr [[A]], align 4 +; CHECK-NEXT: ret i8 [[B]] +; +entry: + %b = load i8, ptr %a, align 4 + ret i8 %b +} + +define i8 @test_load_addrspace(ptr addrspace(256) %a) sanitize_hwaddress { +; CHECK-LABEL: define i8 @test_load_addrspace +; CHECK-SAME: (ptr addrspace(256) [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[B:%.*]] = load i8, ptr addrspace(256) [[A]], align 4 +; CHECK-NEXT: ret i8 [[B]] +; +entry: + %b = load i8, ptr addrspace(256) %a, align 4 + ret i8 %b +} diff --git a/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll b/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll index f8e0364ba19f4625e72a2a6fae9964786a3b41b8..49f0bf739cb6925a98aca749e34180303686f795 100644 --- a/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll +++ b/llvm/test/Instrumentation/HWAddressSanitizer/prologue.ll @@ -69,7 +69,7 @@ define i32 @test_load(ptr %a) sanitize_hwaddress { ; FUCHSIA-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] { ; FUCHSIA-NEXT: entry: ; FUCHSIA-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; FUCHSIA-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 2) +; FUCHSIA-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 2, i64 0) ; FUCHSIA-NEXT: [[X:%.*]] = load i32, ptr [[A]], align 4 ; FUCHSIA-NEXT: ret i32 [[X]] ; @@ -77,7 +77,7 @@ define i32 @test_load(ptr %a) sanitize_hwaddress { ; FUCHSIA-LIBCALL-SAME: (ptr [[A:%.*]]) #[[ATTR0:[0-9]+]] { ; FUCHSIA-LIBCALL-NEXT: entry: ; FUCHSIA-LIBCALL-NEXT: [[DOTHWASAN_SHADOW:%.*]] = call ptr asm "", "=r,0"(ptr null) -; FUCHSIA-LIBCALL-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules(ptr [[DOTHWASAN_SHADOW]], ptr [[A]], i32 2) +; FUCHSIA-LIBCALL-NEXT: call void @llvm.hwasan.check.memaccess.shortgranules.fixedshadow(ptr [[A]], i32 2, i64 0) ; FUCHSIA-LIBCALL-NEXT: [[X:%.*]] = load i32, ptr [[A]], align 4 ; FUCHSIA-LIBCALL-NEXT: ret i32 [[X]] ; diff --git a/llvm/test/LTO/X86/codemodel-2.ll b/llvm/test/LTO/X86/codemodel-2.ll index 5cd9731606f2bd106a4e3b66c78781527ee8883e..fc1074bcf2235c5d927b590ca284e0cf057edf17 100644 --- a/llvm/test/LTO/X86/codemodel-2.ll +++ b/llvm/test/LTO/X86/codemodel-2.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as %s -o %t.o -; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s +; RUN: llvm-lto2 run -r %t.o,_start,px -r %t.o,_GLOBAL_OFFSET_TABLE_, %t.o -o %t.s ; RUN: llvm-objdump --no-print-imm-hex -d %t.s.0 | FileCheck %s --check-prefix=CHECK-LARGE target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/LTO/X86/codemodel-3.ll b/llvm/test/LTO/X86/codemodel-3.ll index 947221e9f36dc56ec271589552343917b6f132a6..13702dfbca2da410b785c71f113b90d968b22f3f 100644 --- a/llvm/test/LTO/X86/codemodel-3.ll +++ b/llvm/test/LTO/X86/codemodel-3.ll @@ -1,6 +1,7 @@ ; RUN: llvm-as %s -o %t0.o ; RUN: llvm-as < %p/Inputs/codemodel-3.ll > %t1.o -; RUN: not llvm-lto2 run -r %t0.o,_start,px -r %t1.o,bar,px %t0.o %t1.o -o %t2.s 2>&1 | FileCheck %s +; RUN: not llvm-lto2 run -r %t0.o,_start,px -r %t1.o,bar,px -r %t0.o,_GLOBAL_OFFSET_TABLE_, \ +; RUN: -r %t1.o,_GLOBAL_OFFSET_TABLE_, %t0.o %t1.o -o %t2.s 2>&1 | FileCheck %s target triple = "x86_64-unknown-linux-gnu" target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128" diff --git a/llvm/test/LTO/X86/largedatathreshold-1.ll b/llvm/test/LTO/X86/largedatathreshold-1.ll index e3be5c11baaac252c9958805f9898e76f0705860..dfd8319511b6176a0062fd0edd988d6411fb6cad 100644 --- a/llvm/test/LTO/X86/largedatathreshold-1.ll +++ b/llvm/test/LTO/X86/largedatathreshold-1.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as %s -o %t.o -; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s +; RUN: llvm-lto2 run -r %t.o,_start,px -r %t.o,_GLOBAL_OFFSET_TABLE_, %t.o -o %t.s ; RUN: llvm-objdump -d %t.s.0 | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/LTO/X86/largedatathreshold-2.ll b/llvm/test/LTO/X86/largedatathreshold-2.ll index 103c066b744d0fa439c74078ba2e8ae0218bf88b..59438bbdb5027f87fad3a8ced46c3e940d4be6f6 100644 --- a/llvm/test/LTO/X86/largedatathreshold-2.ll +++ b/llvm/test/LTO/X86/largedatathreshold-2.ll @@ -1,5 +1,5 @@ ; RUN: llvm-as %s -o %t.o -; RUN: llvm-lto2 run -r %t.o,_start,px %t.o -o %t.s +; RUN: llvm-lto2 run -r %t.o,_start,px -r %t.o,_GLOBAL_OFFSET_TABLE_, %t.o -o %t.s ; RUN: llvm-objdump -d %t.s.0 | FileCheck %s target triple = "x86_64-unknown-linux-gnu" diff --git a/llvm/test/LTO/X86/largedatathreshold-3.ll b/llvm/test/LTO/X86/largedatathreshold-3.ll index 3c0653db334d85f9a857da36dbb73084132a515d..fea7987ff155669e2e2ef886909c28b2ec41d672 100644 --- a/llvm/test/LTO/X86/largedatathreshold-3.ll +++ b/llvm/test/LTO/X86/largedatathreshold-3.ll @@ -1,6 +1,7 @@ ; RUN: llvm-as %s -o %t0.o ; RUN: llvm-as < %p/Inputs/largedatathreshold.ll > %t1.o -; RUN: not llvm-lto2 run -r %t0.o,_start,px -r %t1.o,bar,px %t0.o %t1.o -o %t2.s 2>&1 | FileCheck %s +; RUN: not llvm-lto2 run -r %t0.o,_start,px -r %t1.o,bar,px -r %t0.o,_GLOBAL_OFFSET_TABLE_, \ +; RUN: -r %t1.o,_GLOBAL_OFFSET_TABLE_, %t0.o %t1.o -o %t2.s 2>&1 | FileCheck %s ; CHECK: 'Large Data Threshold': IDs have conflicting values diff --git a/llvm/test/MC/ELF/RISCV/gen-dwarf.s b/llvm/test/MC/ELF/RISCV/gen-dwarf.s index 342ed1cc0e7ef9b04d5c5387604b4f70afe45584..34d02f5da44f297e020c71e7abfcb7c963a65cad 100644 --- a/llvm/test/MC/ELF/RISCV/gen-dwarf.s +++ b/llvm/test/MC/ELF/RISCV/gen-dwarf.s @@ -40,28 +40,28 @@ # CHECK-NEXT: 0x00000020: [DW_RLE_end_of_list ] # RELOC: Section ([[#]]) .rela.eh_frame { -# RELOC-NEXT: 0x1C R_RISCV_32_PCREL 0x0 -# RELOC-NEXT: 0x20 R_RISCV_ADD32 0x0 -# RELOC-NEXT: 0x20 R_RISCV_SUB32 0x0 -# RELOC-NEXT: 0x25 R_RISCV_SET6 0x0 -# RELOC-NEXT: 0x25 R_RISCV_SUB6 0x0 -# RELOC-NEXT: 0x34 R_RISCV_32_PCREL 0x0 +# RELOC-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 +# RELOC-NEXT: 0x20 R_RISCV_ADD32 .L0 0x0 +# RELOC-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 +# RELOC-NEXT: 0x25 R_RISCV_SET6 .L0 0x0 +# RELOC-NEXT: 0x25 R_RISCV_SUB6 .L0 0x0 +# RELOC-NEXT: 0x34 R_RISCV_32_PCREL .L0 0x0 # RELOC-NEXT: } # RELOC: Section ([[#]]) .rela.debug_rnglists { # RELOC-NEXT: 0xD R_RISCV_64 .text.foo 0x0 -# RELOC-NEXT: 0x15 R_RISCV_SET_ULEB128 0x0 +# RELOC-NEXT: 0x15 R_RISCV_SET_ULEB128 .L0 0x0 # RELOC-NEXT: 0x15 R_RISCV_SUB_ULEB128 .text.foo 0x0 # RELOC-NEXT: 0x17 R_RISCV_64 .text.bar 0x0 # RELOC-NEXT: } # RELOC: Section ([[#]]) .rela.debug_line { -# RELOC: R_RISCV_ADD16 0x0 -# RELOC-NEXT: R_RISCV_SUB16 0x0 -# RELOC-NEXT: R_RISCV_ADD16 0x0 -# RELOC-NEXT: R_RISCV_SUB16 0x0 -# RELOC-NEXT: R_RISCV_ADD16 0x0 -# RELOC-NEXT: R_RISCV_SUB16 0x0 +# RELOC: R_RISCV_ADD16 .L0 0x0 +# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 +# RELOC-NEXT: R_RISCV_ADD16 .L0 0x0 +# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 +# RELOC-NEXT: R_RISCV_ADD16 .L0 0x0 +# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 # RELOC: } # RELOC: Hex dump of section '.eh_frame': diff --git a/llvm/test/MC/RISCV/attribute-arch.s b/llvm/test/MC/RISCV/attribute-arch.s index 8835ff22446c8d1700cc0c7b2ffc938e3017c0d2..aea27146e37047841af93d10ede0008add1cee2f 100644 --- a/llvm/test/MC/RISCV/attribute-arch.s +++ b/llvm/test/MC/RISCV/attribute-arch.s @@ -366,7 +366,7 @@ .attribute arch, "rv32i_zvfbfwma1p0" # CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin1p0_zve32f1p0_zve32x1p0_zvfbfmin1p0_zvfbfwma1p0_zvl32b1p0" -.attribute arch, "rv32izacas1p0" +.attribute arch, "rv32ia_zacas1p0" # CHECK: attribute 5, "rv32i2p1_a2p1_zacas1p0" .attribute arch, "rv32izalasr0p1" diff --git a/llvm/test/MC/RISCV/cfi-advance.s b/llvm/test/MC/RISCV/cfi-advance.s index c4af390be757da5f758aefbc1d2e3dc31ae1a808..b99af38f553aa0f978a86b6291bcc61b1dfcea99 100644 --- a/llvm/test/MC/RISCV/cfi-advance.s +++ b/llvm/test/MC/RISCV/cfi-advance.s @@ -1,13 +1,27 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 %s -o %t.o -# RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=CHECK %s +# RUN: llvm-readelf -sr %t.o | FileCheck %s # RUN: llvm-dwarfdump --debug-frame %t.o 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-DWARFDUMP %s -# CHECK: .rela.eh_frame { -# CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 -# CHECK-NEXT: 0x35 R_RISCV_SET6 0x0 -# CHECK-NEXT: 0x35 R_RISCV_SUB6 0x0 -# CHECK-NEXT: } + +# CHECK: Relocation section '.rela.text1' at offset {{.*}} contains 1 entries: +# CHECK-NEXT: Offset Info Type Sym. Value Symbol's Name + Addend +# CHECK-NEXT: 00000000 00000313 R_RISCV_CALL_PLT 00000004 .L0 + 0 +# CHECK-EMPTY: +# CHECK-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 3 entries: +# CHECK: Offset Info Type Sym. Value Symbol's Name + Addend +# CHECK-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0 +# CHECK-NEXT: 00000035 00000b35 R_RISCV_SET6 00010178 .L0 + 0 +# CHECK-NEXT: 00000035 00000934 R_RISCV_SUB6 0001016e .L0 + 0 +# CHECK-EMPTY: +# CHECK: Symbol table '.symtab' contains 15 entries: +# CHECK-NEXT: Num: Value Size Type Bind Vis Ndx Name +# CHECK-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# CHECK-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# CHECK: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}} +# CHECK: 9: 0001016e 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# CHECK: 11: 00010178 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} + # CHECK-DWARFDUMP: DW_CFA_advance_loc1: 104 # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 # CHECK-DWARFDUMP-NEXT: DW_CFA_advance_loc2: 259 @@ -23,6 +37,9 @@ test: .cfi_startproc nop +## This looks similar to fake label names ".L0 ". Even if this is ".L0 ", +## the assembler will not conflate it with fake labels. +.L0: .zero 100, 0x90 .cfi_def_cfa_offset 8 nop @@ -36,3 +53,6 @@ test: .cfi_def_cfa_offset 8 nop .cfi_endproc + +.section .text1,"ax" +call .L0 diff --git a/llvm/test/MC/RISCV/fde-reloc.s b/llvm/test/MC/RISCV/fde-reloc.s index 1db8929e0747037fe3b0199a090110c794836e3c..81ec426c8b6165c3d36bc6e86b51d0f837e7cf3e 100644 --- a/llvm/test/MC/RISCV/fde-reloc.s +++ b/llvm/test/MC/RISCV/fde-reloc.s @@ -12,7 +12,7 @@ func: .cfi_endproc # CHECK: Section (4) .rela.eh_frame { -# CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +# CHECK-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 # CHECK-NEXT: } # CHECK: Hex dump of section '.eh_frame': # CHECK-NEXT: 0x00000000 10000000 00000000 017a5200 017c0101 diff --git a/llvm/test/MC/RISCV/rv32dc-valid.s b/llvm/test/MC/RISCV/rv32dc-valid.s index 4e30fadac34bc2e7caa09ffe6e346a07fdaa4cad..201aee545d4a420a3575ca4be8f089aa24956604 100644 --- a/llvm/test/MC/RISCV/rv32dc-valid.s +++ b/llvm/test/MC/RISCV/rv32dc-valid.s @@ -12,9 +12,6 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s -# RUN: not llvm-mc -triple riscv32 -mattr=+zcd \ -# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s # RUN: not llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s diff --git a/llvm/test/MC/RISCV/rv32fc-valid.s b/llvm/test/MC/RISCV/rv32fc-valid.s index f8be0336779472f40fdd7103ed2752a6820d4a38..936032594457f6755a033dfc347f6b56d77e0c85 100644 --- a/llvm/test/MC/RISCV/rv32fc-valid.s +++ b/llvm/test/MC/RISCV/rv32fc-valid.s @@ -12,9 +12,6 @@ # RUN: not llvm-mc -triple riscv32 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-F %s -# RUN: not llvm-mc -triple riscv32 -mattr=+zcf \ -# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-F %s # RUN: not llvm-mc -triple riscv32 \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-FC %s diff --git a/llvm/test/MC/RISCV/rv32zacas-invalid.s b/llvm/test/MC/RISCV/rv32zacas-invalid.s index 11d20dacd8a78834de57ad3027940b46e51f08e8..66f939d139a1268e6613f18ec2d2e8e99e6b17e8 100644 --- a/llvm/test/MC/RISCV/rv32zacas-invalid.s +++ b/llvm/test/MC/RISCV/rv32zacas-invalid.s @@ -1,4 +1,4 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+zacas < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+a,zacas < %s 2>&1 | FileCheck %s # Non-zero offsets not supported for the third operand (rs1). amocas.w a1, a3, 1(a5) # CHECK: :[[@LINE]]:18: error: optional integer offset must be 0 diff --git a/llvm/test/MC/RISCV/rv32zacas-valid.s b/llvm/test/MC/RISCV/rv32zacas-valid.s index 05a9cdd5cc2188b284a1e3a50a6452bd2af573bc..0e76f023994833b493b6c78955a67981e898230a 100644 --- a/llvm/test/MC/RISCV/rv32zacas-valid.s +++ b/llvm/test/MC/RISCV/rv32zacas-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+zacas -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+zacas -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+zacas -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+zacas -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zacas < %s \ -# RUN: | llvm-objdump --mattr=+zacas -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+zacas < %s \ +# RUN: | llvm-objdump --mattr=+a,+zacas -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zacas < %s \ -# RUN: | llvm-objdump --mattr=+zacas -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+zacas < %s \ +# RUN: | llvm-objdump --mattr=+a,+zacas -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: not llvm-mc -triple=riscv32 -mattr=+a -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR diff --git a/llvm/test/MC/RISCV/rv64dc-valid.s b/llvm/test/MC/RISCV/rv64dc-valid.s index 5347714761dc8c08940e9bba5fd9cd5ac2b2691c..83225b2c68562c568939e24a9bd51e84b7a5d77a 100644 --- a/llvm/test/MC/RISCV/rv64dc-valid.s +++ b/llvm/test/MC/RISCV/rv64dc-valid.s @@ -12,9 +12,6 @@ # RUN: not llvm-mc -triple riscv64 -mattr=+c \ # RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s -# RUN: not llvm-mc -triple riscv64 -mattr=+zcd \ -# RUN: -riscv-no-aliases -show-encoding < %s 2>&1 \ -# RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-D %s # RUN: not llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding < %s 2>&1 \ # RUN: | FileCheck -check-prefixes=CHECK-NO-EXT-DC %s diff --git a/llvm/test/MC/RISCV/rv64zacas-valid.s b/llvm/test/MC/RISCV/rv64zacas-valid.s index 694f43b9b4407b3a88a1800ab186958ca2b451a4..c6bf1252fa40d631102479dece2a862d2f910dc3 100644 --- a/llvm/test/MC/RISCV/rv64zacas-valid.s +++ b/llvm/test/MC/RISCV/rv64zacas-valid.s @@ -1,7 +1,7 @@ -# RUN: llvm-mc %s -triple=riscv64 -mattr=+zacas -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,zacas -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zacas < %s \ -# RUN: | llvm-objdump --mattr=+zacas -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,zacas < %s \ +# RUN: | llvm-objdump --mattr=+a,zacas -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # RUN: not llvm-mc -triple=riscv64 -mattr=+a -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR diff --git a/llvm/test/MC/RISCV/rvzabha-invalid.s b/llvm/test/MC/RISCV/rvzabha-invalid.s index 091f7e59ae184430780e66ced1459891a9beda38..62cb1d8c8913948d681c389b1f3c69831675fa79 100644 --- a/llvm/test/MC/RISCV/rvzabha-invalid.s +++ b/llvm/test/MC/RISCV/rvzabha-invalid.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mc -triple riscv32 -mattr=+experimental-zabha < %s 2>&1 | FileCheck %s -# RUN: not llvm-mc -triple riscv64 -mattr=+experimental-zabha < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv32 -mattr=+a,+experimental-zabha < %s 2>&1 | FileCheck %s +# RUN: not llvm-mc -triple riscv64 -mattr=+a,+experimental-zabha < %s 2>&1 | FileCheck %s # Final operand must have parentheses amoswap.b a1, a2, a3 # CHECK: :[[@LINE]]:19: error: expected '(' or optional integer offset diff --git a/llvm/test/MC/RISCV/rvzabha-valid.s b/llvm/test/MC/RISCV/rvzabha-valid.s index c1f7f44a04ddd081a4d2a850f7b7e35dea3b451b..333e58d1268e6ed68a1a2d049a7bca09a0f01629 100644 --- a/llvm/test/MC/RISCV/rvzabha-valid.s +++ b/llvm/test/MC/RISCV/rvzabha-valid.s @@ -1,12 +1,12 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zabha -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+experimental-zabha -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zabha -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+experimental-zabha -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zabha < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zabha -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+experimental-zabha < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zabha -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zabha < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zabha -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+experimental-zabha < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zabha -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s # CHECK-ASM-AND-OBJ: amoswap.b a4, ra, (s0) diff --git a/llvm/test/MC/RISCV/rvzabha-zacas-valid.s b/llvm/test/MC/RISCV/rvzabha-zacas-valid.s index f1f705e625b87a2f717314ec82b67b0c90f79f85..994112c6b6e5b86f122fcc031517b6806a879feb 100644 --- a/llvm/test/MC/RISCV/rvzabha-zacas-valid.s +++ b/llvm/test/MC/RISCV/rvzabha-zacas-valid.s @@ -1,16 +1,16 @@ -# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-zabha,+zacas -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv32 -mattr=+a,+experimental-zabha,+zacas -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-zabha,+zacas -riscv-no-aliases -show-encoding \ +# RUN: llvm-mc %s -triple=riscv64 -mattr=+a,+experimental-zabha,+zacas -riscv-no-aliases -show-encoding \ # RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+experimental-zabha,+zacas < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zabha,+zacas -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+a,+experimental-zabha,+zacas < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zabha,+zacas -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+experimental-zabha,+zacas < %s \ -# RUN: | llvm-objdump --mattr=+experimental-zabha,+zacas -M no-aliases -d -r - \ +# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+a,+experimental-zabha,+zacas < %s \ +# RUN: | llvm-objdump --mattr=+a,+experimental-zabha,+zacas -M no-aliases -d -r - \ # RUN: | FileCheck --check-prefix=CHECK-ASM-AND-OBJ %s -# RUN: not llvm-mc -triple=riscv32 -mattr=+experimental-zabha -show-encoding %s 2>&1 \ +# RUN: not llvm-mc -triple=riscv32 -mattr=+a,+experimental-zabha -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR -# RUN: not llvm-mc -triple=riscv64 -mattr=+experimental-zabha -show-encoding %s 2>&1 \ +# RUN: not llvm-mc -triple=riscv64 -mattr=+a,+experimental-zabha -show-encoding %s 2>&1 \ # RUN: | FileCheck %s --check-prefix=CHECK-ERROR # CHECK-ASM-AND-OBJ: amocas.b a1, a3, (a5) diff --git a/llvm/test/MC/RISCV/scoped-relaxation.s b/llvm/test/MC/RISCV/scoped-relaxation.s index 0b797ee5aca5eb01fb9e4dc1317f305b9ca9e7d5..56394fd8053282b46319ecae00ac979ac671a3df 100644 --- a/llvm/test/MC/RISCV/scoped-relaxation.s +++ b/llvm/test/MC/RISCV/scoped-relaxation.s @@ -9,7 +9,7 @@ .dword function - . # CHECK: 0x0 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x0 R_RISCV_SUB64 0x0 +# CHECK-NEXT: 0x0 R_RISCV_SUB64 .L0 0x0 # Relaxed reference, this will resolve to a pair of `RISCV_ADD64` and # `RISCV_SUB64` relocation. @@ -19,7 +19,7 @@ .option pop # CHECK: 0x8 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x8 R_RISCV_SUB64 0x0 +# CHECK-NEXT: 0x8 R_RISCV_SUB64 .L0 0x0 # Unrelaxed reference, this will resolve to a pair of `RISCV_ADD64` and # `RISCV_SUB64` relocation due to relaxation being sticky to the file. @@ -29,6 +29,6 @@ .option pop # CHECK: 0x10 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x10 R_RISCV_SUB64 0x0 +# CHECK-NEXT: 0x10 R_RISCV_SUB64 .L0 0x0 # CHECK: } diff --git a/llvm/test/MC/Xtensa/Core/invalid.s b/llvm/test/MC/Xtensa/Core/invalid.s index d3d8fba8169a6d2206621184398ea0accd97f358..c7473e90c10ba378c4dca713fae1ef1dc7fead07 100644 --- a/llvm/test/MC/Xtensa/Core/invalid.s +++ b/llvm/test/MC/Xtensa/Core/invalid.s @@ -4,10 +4,6 @@ LBL0: # Out of range immediates -# imm12m -movi a1, 3000 -# CHECK: :[[#@LINE-1]]:10: error: expected immediate in range [-2048, 2047] - # imm8 addi a1, a2, 300 # CHECK: :[[#@LINE-1]]:14: error: expected immediate in range [-128, 127] diff --git a/llvm/test/MC/Xtensa/directive-literal.s b/llvm/test/MC/Xtensa/directive-literal.s new file mode 100644 index 0000000000000000000000000000000000000000..269cf20ed45eb2a5edd6a0b2625d6d8df0119a1c --- /dev/null +++ b/llvm/test/MC/Xtensa/directive-literal.s @@ -0,0 +1,42 @@ +# RUN: llvm-mc -triple=xtensa -filetype obj -o - %s \ +# RUN: | llvm-readobj -S --sd - \ +# RUN: | FileCheck -check-prefix=CHECK-LITERAL %s + +# RUN: llvm-mc %s -triple=xtensa -show-encoding \ +# RUN: | FileCheck -check-prefix=CHECK-INST %s + + .text + .literal_position + .literal .LCPI0_0, 305419896 + .literal .LCPI1_0, ext_var + .global test_literal + .p2align 2 + .type test_literal,@function +test_literal: + l32r a2, .LCPI0_0 + l32r a3, .LCPI1_0 + movi a4, 30000 + movi a5, 1000 + ret + +# CHECK-LITERAL: Section { +# CHECK-LITERAL: Name: .literal +# CHECK-LITERAL: SectionData ( +# CHECK-LITERAL: 0000: 78563412 00000000 30750000 +# CHECK-LITERAL: ) +# CHECK-LITERAL: } + +# CHECK-INST: .literal_position +# CHECK-INST: .literal .LCPI0_0, 305419896 +# CHECK-INST: .literal .LCPI1_0, ext_var +# CHECK-INST: .global test_literal +# CHECK-INST: .p2align 2 +# CHECK-INST: .type test_literal,@function +# CHECK-INST: test_literal: +# CHECK-INST: l32r a2, .LCPI0_0 +# CHECK-INST: l32r a3, .LCPI1_0 +# CHECK-INST: .literal .Ltmp0, 30000 +# CHECK-INST: l32r a4, .Ltmp0 +# CHECK-INST: movi a5, 1000 +# CHECK-INST: ret + diff --git a/llvm/test/MC/Xtensa/invalid-literal.s b/llvm/test/MC/Xtensa/invalid-literal.s new file mode 100644 index 0000000000000000000000000000000000000000..ebb37441059cad4eed300cce15bed01ec65a4042 --- /dev/null +++ b/llvm/test/MC/Xtensa/invalid-literal.s @@ -0,0 +1,10 @@ +# RUN: not llvm-mc %s -triple=xtensa -filetype=asm 2>&1 | FileCheck %s + +.text +.literal_position +.literal .LCPI0_0 a +# CHECK: [[@LINE-1]]:20: error: expected comma +.literal 123, a +# CHECK: [[@LINE-1]]:10: error: literal label must be a symbol +.literal .LCPI1_0, +# CHECK: [[@LINE-1]]:19: error: expected value diff --git a/llvm/test/TableGen/ContextlessPredicates.td b/llvm/test/TableGen/ContextlessPredicates.td index 5e4e69069c3e3298226908411baa85de5646e559..eead9655111e6815c962dd6883830dc6655484ba 100644 --- a/llvm/test/TableGen/ContextlessPredicates.td +++ b/llvm/test/TableGen/ContextlessPredicates.td @@ -22,26 +22,26 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , // CHECK_NOPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { // CHECK_NOPT-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(58), // Rule ID 0 // +// CHECK_NOPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(52), // Rule ID 0 // // CHECK_NOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK_NOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG), // CHECK_NOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), // CHECK_NOPT-NEXT: // MIs[0] DstI[dst] -// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_NOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_NOPT-NEXT: // MIs[0] ptr // CHECK_NOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_NOPT-NEXT: // MIs[0] val -// CHECK_NOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK_NOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_NOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// CHECK_NOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_NOPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag), // CHECK_NOPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) // CHECK_NOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN), -// CHECK_NOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK_NOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK_NOPT-NEXT: // GIR_Coverage, 0, // CHECK_NOPT-NEXT: GIR_Done, -// CHECK_NOPT-NEXT: // Label 0: @58 +// CHECK_NOPT-NEXT: // Label 0: @52 // CHECK_NOPT-NEXT: GIM_Reject, // CHECK_NOPT-NEXT: }; // CHECK_NOPT-NEXT: return MatchTable0; @@ -49,23 +49,23 @@ def : Pat<(test_atomic_op_frag GPR32:$ptr, GPR32:$val) , // CHECK_OPT-LABEL: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { // CHECK_OPT-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(55), // Rule ID 0 // +// CHECK_OPT-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(49), // Rule ID 0 // // CHECK_OPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_XCHG), -// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK_OPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK_OPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK_OPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK_OPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), -// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_OPT-NEXT: // MIs[0] ptr // CHECK_OPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK_OPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK_OPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK_OPT-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_test_atomic_op_frag), // CHECK_OPT-NEXT: // (atomic_swap:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val)<> => (INSN:{ *:[i32] } GPR32:{ *:[i32] }:$ptr, GPR32:{ *:[i32] }:$val) // CHECK_OPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN), -// CHECK_OPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK_OPT-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK_OPT-NEXT: // GIR_Coverage, 0, // CHECK_OPT-NEXT: GIR_Done, -// CHECK_OPT-NEXT: // Label 0: @55 +// CHECK_OPT-NEXT: // Label 0: @49 // CHECK_OPT-NEXT: GIM_Reject, // CHECK_OPT-NEXT: }; // CHECK_OPT-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/DefaultOpsGlobalISel.td b/llvm/test/TableGen/DefaultOpsGlobalISel.td index 0c5aa0b912f5492f20a33af0b86ffa97e7e360f2..8f4176a2aa730b8f6f1802f0e160fcefb983b422 100644 --- a/llvm/test/TableGen/DefaultOpsGlobalISel.td +++ b/llvm/test/TableGen/DefaultOpsGlobalISel.td @@ -33,101 +33,97 @@ def clamp : OperandWithDefaultOps ; // CHECK: const uint8_t *MyTargetInstructionSelector::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(79), // Rule ID 3 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(69), // Rule ID 3 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FMAXNUM), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectSrcMods:src0:mods0 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods), // CHECK-NEXT: // MIs[0] SelectSrcMods:src1:mods1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_SelectSrcMods), // CHECK-NEXT: // (fmaxnum:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods0), (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src1, src_mods:{ *:[i32] }:$mods1)) => (FMAX:{ *:[f32] } src_mods:{ *:[i32] }:$mods0, f32:{ *:[f32] }:$src0, src_mods:{ *:[i32] }:$mods1, f32:{ *:[f32] }:$src1) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // mods1 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 3, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @79 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(139), // Rule ID 2 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 0: @69 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(120), // Rule ID 2 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FFLOOR), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectClampOMod:src0:omod:clamp -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClampOMod), // CHECK-NEXT: // (ffloor:{ *:[f32] } (SelectClampOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod, i1:{ *:[i1] }:$clamp)) => (FLOMP:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, omod:{ *:[i32] }:$omod) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FLOMP), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLOMP), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 1: @139 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(207), // Rule ID 8 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 1: @120 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(179), // Rule ID 8 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectSrcMods:src:mods -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectSrcMods), // CHECK-NEXT: // (fcanonicalize:{ *:[f32] } (SelectSrcMods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$mods)) => (FMAX:{ *:[f32] } ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$mods, ?:{ *:[f32] }:$src, 0:{ *:[i1] }) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FMAX), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 8, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 2: @207 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(265), // Rule ID 5 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 2: @179 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(228), // Rule ID 5 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCOS), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectOMod:src0:omod -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectOMod), // CHECK-NEXT: // (fcos:{ *:[f32] } (SelectOMod:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$omod)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, omod:{ *:[i32] }:$omod) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // omod // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 5, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @265 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(345), // Rule ID 7 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 3: @228 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(299), // Rule ID 7 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FEXP2), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), // CHECK-NEXT: // (fexp2:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FEEPLE:{ *:[f32] } FPR32:{ *:[f32] }:$src0, (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0), clamp:{ *:[i1] }:$clamp) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, @@ -136,93 +132,88 @@ def clamp : OperandWithDefaultOps ; // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FEEPLE), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FEEPLE), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 7, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @345 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(400), // Rule ID 0 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 4: @299 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(345), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSIN), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), // CHECK-NEXT: // (fsin:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FFOO:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 5: @400 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(458), // Rule ID 6 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 5: @345 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(394), // Rule ID 6 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FSQRT), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] SelectClamp:src0:clamp -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_SelectClamp), // CHECK-NEXT: // (fsqrt:{ *:[f32] } (SelectClamp:{ *:[f32] } f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp)) => (FLAMP:{ *:[f32] } FPR32:{ *:[f32] }:$src0, 93:{ *:[i32] }, clamp:{ *:[i1] }:$clamp) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FLAMP), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/93, // CHECK-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 6, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 6: @458 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(503), // Rule ID 1 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 6: @394 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(428), // Rule ID 1 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_ROUND), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // (fround:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FBAR:{ *:[f32] } f32:{ *:[f32] }:$src0) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FBAR), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FBAR), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 7: @503 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(548), // Rule ID 4 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 7: @428 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(462), // Rule ID 4 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_TRUNC), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // CHECK-NEXT: // MIs[0] src0 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0) => (FFOO:{ *:[f32] } FPR32:{ *:[f32] }:$src0) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FFOO), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 4, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 8: @548 +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 8: @462 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 549 bytes +// CHECK-NEXT: }; // Size: 463 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td index 25fdd887b20b50b4b41b30fd61ffa299cf9df3fa..c227737080e195eb3dc63e250e19bd654fa00543 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-eraseroot.td @@ -19,7 +19,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(15), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(13), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_STORE), // CHECK-NEXT: // MIs[0] a @@ -27,9 +27,8 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[0] b // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // Combiner Rule #0: Test0 -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @15 +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 0: @13 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td index ebb95ccb2104082d7ea851824d14599537c62d4c..9c9b39027f8f957524cd45a1b7974ba92c4a8c15 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/builtins/match-table-replacerreg.td @@ -47,16 +47,15 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[1] y // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #1: ReplaceTemp -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UNMERGE_VALUES), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // y // CHECK-NEXT: GIR_ReplaceRegWithTempReg, /*OldInsnID*/0, /*OldOpIdx*/1, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 3: @[[L529]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 1: @[[L530]] @@ -70,11 +69,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[1] src // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckCanReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #0: ReplaceMatched // CHECK-NEXT: GIR_ReplaceReg, /*OldInsnID*/0, /*OldOpIdx*/0, /*NewInsnId*/1, /*NewOpIdx*/1, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 4: @[[L561]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @[[L562]] diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td index 6004a17d351be76017601522492bb4c054e274f8..d9a8854cd018f87c7ff623e9061dcfb3096e1581 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-imms.td @@ -41,31 +41,29 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // Label 0: @[[L462]] // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4([[L492:[0-9]+]]), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 4: @[[L492]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 1: @[[L493]] // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4([[L538:[0-9]+]]), // Rule ID 2 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule2Enabled), -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] a // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #2: CImmInstTest1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/GILLT_s32, /*Imm*/GIMT_Encode8(42), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 5: @[[L538]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @{{[0-9]+}} @@ -78,11 +76,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #1: InstTest1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // a +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 6: @[[L578]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 3: @[[L579]] diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td index b2dd8b6684b1d3f49fda6d0ea2cb14198284253c..365d0c9fbff4940f8d54b4820bf3ac08ea58ceee 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-intrinsics.td @@ -43,15 +43,14 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #0: IntrinTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::0in_1out), // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::1in_1out), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 3: @[[L72]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 1: @[[L73]] @@ -65,21 +64,20 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: // Combiner Rule #1: SpecialIntrins -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/0, GIMT_Encode2(Intrinsic::convergent_1in_1out), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // b +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // b // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_AddIntrinsicID, /*MI*/1, GIMT_Encode2(Intrinsic::convergent_sideeffects_1in_1out), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 4: @[[L131]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @[[L132]] // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 133 bytes +// CHECK-NEXT: }; // Size: 125 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td index 22e4d2d5d9d14b7058d08f233061ac9676f819f9..24864e8aef45690ffc48fc4b31721534ecd016da 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-miflags.td @@ -17,7 +17,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>; // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(68), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(63), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT), // CHECK-NEXT: // MIs[0] dst @@ -29,18 +29,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [MIFlagsTest]>; // CHECK-NEXT: GIM_MIFlagsNot, /*MI*/1, GIMT_Encode4(MachineInstr::FmArcp | MachineInstr::FmNoNans), // CHECK-NEXT: // MIs[1] src // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #0: MIFlagsTest -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_MUL), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_CopyMIFlags, /*InsnID*/0, /*OldInsnID*/1, // CHECK-NEXT: GIR_SetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmReassoc), // CHECK-NEXT: GIR_UnsetMIFlags, /*InsnID*/0, GIMT_Encode4(MachineInstr::FmNsz | MachineInstr::FmArcp), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @68 +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 0: @63 // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; // CHECK-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td index 0fb63bce1d6a6ea759a80d420f001e2e6709553a..a23b54afb51252f1481f38990cc168307da313c0 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-operand-types.td @@ -21,32 +21,31 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(81), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(73), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s8, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s8, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[1] b // CHECK-NEXT: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, // CHECK-NEXT: // Combiner Rule #0: InstTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // b +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // b // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // c // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // a // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // b // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @81 +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 0: @73 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 82 bytes +// CHECK-NEXT: }; // Size: 74 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td index 016ab05ca01e4ea0135baa729ea81f751f6f6f13..5a8b51dfc8324a2892751ae40b2693eb5e002a7c 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-patfrag-root.td @@ -42,11 +42,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 4: @[[L297]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 1: @[[L298]] @@ -59,15 +58,14 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), // CHECK-NEXT: // MIs[1] __Test0_match_0.x // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 5: @[[L343]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @[[L344]] @@ -80,11 +78,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [__Test0_match_0[2]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // root +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // root // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 6: @[[L379]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 3: @[[L380]] diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td index c38c4be9d54558533c276b19aabf7da506a14a0c..fda57d5b64e028c57673383aa699e0dd4ee04a53 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-permutations.td @@ -159,9 +159,9 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(850), +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(738), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(99), // Rule ID 7 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(88), // Rule ID 7 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -186,21 +186,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner21), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner22), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner23), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/4, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[1], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 1: @99 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(199), // Rule ID 6 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 1: @88 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(175), // Rule ID 6 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -228,22 +224,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner18), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner19), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner20), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/5, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[1], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 2: @199 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(299), // Rule ID 5 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 2: @175 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(262), // Rule ID 5 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -271,22 +262,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner15), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner16), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner17), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/5, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[0], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @299 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(409), // Rule ID 4 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 3: @262 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(357), // Rule ID 4 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -317,23 +303,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner12), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner13), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner14), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/6, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[1], b[0], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @409 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(509), // Rule ID 3 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 4: @357 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(444), // Rule ID 3 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -361,22 +341,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner9), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner10), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner11), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/5, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[1], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 5: @509 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(619), // Rule ID 2 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 5: @444 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(539), // Rule ID 2 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -407,23 +382,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner6), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner7), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner8), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/6, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[1], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 6: @619 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(729), // Rule ID 1 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 6: @539 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(634), // Rule ID 1 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -454,23 +423,17 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner3), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner4), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner5), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/6, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[0], c[1]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 7: @729 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(849), // Rule ID 0 // +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 7: @634 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(737), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates @@ -504,26 +467,19 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner0), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner1), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner2), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/3, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/4, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/5, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/6, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/7, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/7, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #0: Test0 @ [a[0], b[0], c[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 8: @849 +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 8: @737 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 0: @850 +// CHECK-NEXT: // Label 0: @738 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 851 bytes +// CHECK-NEXT: }; // Size: 739 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td index 4e473355e14c36c2f17f6531d4e157f40fbcc00b..9a7716e54b27ffaa60a35ca9a7a9464edd22d106 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-temp-defs.td @@ -36,21 +36,21 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ ]>; // CHECK: // Combiner Rule #0: Test0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // lhs -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rhs +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs // CHECK: // Combiner Rule #1: Test1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_UDIVREM), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // lhs -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // rhs +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // rhs // CHECK: // Combiner Rule #2: Test2 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // lhs +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // lhs diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td index ca653674d9c2569cec48c866f7850c5ec7f7cadb..7fe63b1298ae7ed4d683f00084609fda15563d81 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table-typeof.td @@ -16,7 +16,7 @@ def Test0 : GICombineRule< // CHECK: const uint8_t *GenMyCombiner::getMatchTable() const { // CHECK-NEXT: constexpr static uint8_t MatchTable0[] = { -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(77), // Rule ID 0 // +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(74), // Rule ID 0 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule0Enabled), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] dst @@ -29,18 +29,17 @@ def Test0 : GICombineRule< // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/1, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/uint8_t(-1), // CHECK-NEXT: // Combiner Rule #0: Test0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_CONSTANT), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_AddCImm, /*InsnID*/0, /*Type*/uint8_t(-2), /*Imm*/GIMT_Encode8(42), // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 0: @77 +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 0: @74 // CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: }; // Size: 78 bytes +// CHECK-NEXT: }; // Size: 75 bytes // CHECK-NEXT: return MatchTable0; // CHECK-NEXT: } diff --git a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td index 02085c1fd2666b969fb648d5d80de55e6e9700eb..1052e31b2d051e0555f3eda09516bcea980d0f03 100644 --- a/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td +++ b/llvm/test/TableGen/GlobalISelCombinerEmitter/match-table.td @@ -154,7 +154,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[1] c // CHECK-NEXT: // No operand predicates // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_GICombiner0), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #3: InstTest1 // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner0), // CHECK-NEXT: GIR_Done, @@ -173,7 +173,7 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // Label 1: @[[L504]] // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 9*/ GIMT_Encode4([[L556:[0-9]+]]), // Rule ID 6 // // CHECK-NEXT: GIM_CheckSimplePredicate, GIMT_Encode2(GICXXPred_Simple_IsRule5Enabled), -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] dst // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] x @@ -182,13 +182,12 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // MIs[1] z // CHECK-NEXT: GIM_CheckLiteralInt, /*MI*/1, /*Op*/1, GIMT_Encode8(-42), // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 43, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #5: InOutInstTest1 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_TRUNC), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_TRUNC), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // z -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 9: @[[L556]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 2: @[[L557]] @@ -201,15 +200,14 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: // No operand predicates // CHECK-NEXT: // MIs[0] ptr // CHECK-NEXT: // No operand predicates -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // Combiner Rule #4: InOutInstTest0 -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::G_STORE), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::G_STORE), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // ext -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // ptr +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // ptr // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, // CHECK-NEXT: GIR_CustomAction, GIMT_Encode2(GICXXCustomAction_CombineApplyGICombiner2), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 10: @[[L598]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 3: @[[L599]] @@ -245,11 +243,10 @@ def MyCombiner: GICombiner<"GenMyCombiner", [ // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildConstant, /*TempRegID*/0, /*Val*/GIMT_Encode8(0), // CHECK-NEXT: // Combiner Rule #6: PatFragTest0 @ [__PatFragTest0_match_1[0]] -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // dst +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // dst // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 14: @[[L676]] // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: // Label 6: @[[L677]] diff --git a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td index 081c9e8634592064658fb9cdbdbe1dcf996ab092..da2dfe8004289de71d2c024a28c09382bb5eb246 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td +++ b/llvm/test/TableGen/GlobalISelEmitter-atomic_store.td @@ -9,7 +9,7 @@ def ST_ATOM_B32 : I<(outs), (ins GPR32Op:$val, GPR32Op:$ptr), []>; // GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), // GISEL-NEXT: GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, // GISEL-NEXT: // MIs[0] val -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, // GISEL-NEXT: // MIs[0] ptr // GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // GISEL-NEXT: // (atomic_store i32:{ *:[i32] }:$val, iPTR:{ *:[iPTR] }:$ptr)<> => (ST_ATOM_B32 GPR32Op:{ *:[i32] }:$val, GPR32Op:{ *:[i32] }:$ptr) diff --git a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td index eae29308aa1bdc9946ed735fbd8403509dcb56cd..0125aa5c30fa6d27f0194e58f1bad5aaf408e8ea 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td +++ b/llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td @@ -11,12 +11,12 @@ include "GlobalISelEmitterCommon.td" // GISEL-OPT: GIM_Try, -// GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, +// GISEL-OPT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, // GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-OPT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1, // GISEL-OPT: GIM_Try, -// GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, +// GISEL-OPT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, // GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-OPT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1, @@ -24,13 +24,13 @@ include "GlobalISelEmitterCommon.td" // GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_LSHR), // GISEL-NOOPT: // MIs[0] Operand 2 -// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, +// GISEL-NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] // GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1, // GISEL-NOOPT-NEXT: // MIs[1] Operand 0 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16, -// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // GISEL-NOOPT-NEXT: // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllOnesV:{ *:[v4i16] }) => (VFOOONES:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0) def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0), [(set v4i32:$dst, (srl v4i32:$src0, (v4i16 immAllOnesV)))] @@ -39,13 +39,13 @@ def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0), // GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SHL), // GISEL-NOOPT: // MIs[0] Operand 2 -// GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16, +// GISEL-NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] // GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), // GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1, // GISEL-NOOPT-NEXT: // MIs[1] Operand 0 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16, -// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // GISEL-NOOPT-NEXT: // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllZerosV:{ *:[v4i16] }) => (VFOOZERO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0) def VFOOZERO : I<(outs VecReg128:$dst), (ins VecReg128:$src0), [(set v4i32:$dst, (shl v4i32:$src0, (v4i16 immAllZerosV)))] diff --git a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td index bfbeee466b1cc3723debec76fb39d1d8155139db..6b4012eb736cb35849db4d3d808a743b532921d2 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td +++ b/llvm/test/TableGen/GlobalISelEmitter-immarg-literal-pattern.td @@ -43,7 +43,7 @@ def : Pat< // Check a non-intrinsic instruction with an immediate parameter. // GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TGT_CAT), -// GISEL: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // GISEL-NEXT: // MIs[0] Operand 2 // GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(0), def : Pat< @@ -52,7 +52,7 @@ def : Pat< >; // GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TGT_CAT), -// GISEL: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// GISEL: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // GISEL-NEXT: // MIs[0] Operand 2 // GISEL-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/2, GIMT_Encode8(93), def : Pat< diff --git a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td index 8d3c6cb180aea16c56e075d8167978329b6213c0..202ff4a5758d7f95669461b49c21af251a7f5fff 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-input-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter-input-discard.td @@ -11,21 +11,22 @@ def FOO : I<(outs GPR32:$dst), (ins GPR32Op:$src0, GPR32Op:$src1), []>; // GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS), // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, // GISEL-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::tgt_foo), -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, srcvalue:{ *:[i32] }, i32:{ *:[i32] }:$src1) => (FOO:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), GPR32:{ *:[i32] }:$src1) // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::FOO), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::FOO), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // src1 -// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // src1 +// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, +// GISEL-NEXT: // GIR_Coverage +// GISEL-NEXT: GIR_EraseRootFromParent_Done, def : Pat < (int_tgt_foo (i32 srcvalue), i32:$src1), (FOO (IMPLICIT_DEF), GPR32:$src1) diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td index 70991ea3b69c07fda638fb2aa9a01ad384bcbe5e..2d968bebbc65e05476456ee33db74d6fc5149021 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output-discard.td @@ -23,20 +23,21 @@ def : Pat<(two_out GPR32:$val), (THREE_OUTS GPR32:$val)>; // CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_OUT), // CHECK-NEXT: // MIs[0] DstI[out1] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] DstI[out2] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] val -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (two_out:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) => (THREE_OUTS:{ *:[i32] }:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$val) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::THREE_OUTS), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[out1] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::THREE_OUTS), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2] // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // val -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // val +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage +// CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td index 94c9f60eabd3bce7c86ae68a65a54e9e45fa3e50..dea3b54960717050efe42a96432e7ca20f84ac30 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td +++ b/llvm/test/TableGen/GlobalISelEmitter-multiple-output.td @@ -32,20 +32,20 @@ def : Pat<(loadpost (p0 GPR32:$addr), (i32 GPR32:$off)), // CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_POST_LOAD), // CHECK-NEXT: // MIs[0] DstI[val] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] DstI[ptr_out] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_p0s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_p0s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] addr -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_p0s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] off -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (loadpost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) => (LDPost:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$addr, GPR32:{ *:[i32] }:$off) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LDPost), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, //----------------------------------------------------------------------------- // Test where a whole new MIR instruction is created during ISel @@ -67,25 +67,26 @@ def : Pat<(two_in GPR32:$i1, GPR32:$i2), (TWO_INS GPR32:$i2, GPR32:$i1)>; // CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(MyTarget::G_TWO_IN), // CHECK-NEXT: // MIs[0] DstI[out1] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] DstI[out2] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] i1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] i2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (two_in:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i1, GPR32:{ *:[i32] }:$i2) => (TWO_INS:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$i2, GPR32:{ *:[i32] }:$i1) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO_INS), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[out1] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // DstI[out2] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, // i2 -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // i1 -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::TWO_INS), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[out1] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // DstI[out2] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/3, // i2 +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // i1 +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage +// CHECK-NEXT: GIR_EraseRootFromParent_Done, //----------------------------------------------------------------------------- // Test where implicit defs are added using Defs. @@ -99,10 +100,10 @@ def : Pat<(i32 (add i32:$src, i32:$src)), // CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] src -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (ImplicitDefInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src)) @@ -112,21 +113,22 @@ def : Pat<(i32 (add i32:$src, i32:$src)), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for MyTarget::R0*/0, // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage +// CHECK-NEXT: GIR_EraseRootFromParent_Done, //----------------------------------------------------------------------------- // Test when the inner instruction in the output pattern has two outs // CHECK: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] src -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // CHECK-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$src) => (OtherInstr:{ *:[i32] } (TwoOutsInstr:{ *:[i32] }:{ *:[i32] } GPR32:{ *:[i32] }:$src)) @@ -137,11 +139,12 @@ def : Pat<(i32 (add i32:$src, i32:$src)), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::OtherInstr), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage +// CHECK-NEXT: GIR_EraseRootFromParent_Done, def TwoOutsInstr : I<(outs GPR32:$out1, GPR32:$out2), (ins GPR32:$src), []>; diff --git a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td index 234b19a146c150ff8368dc50d7506c3cc108f7d0..25a39a40da6188e06e70cf236cefa8ff1eba5bbd 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td +++ b/llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td @@ -33,10 +33,10 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>; // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ANYEXT), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s16, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::A0RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::A0RegClassID), // CHECK-NEXT: // MIs[0] src -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s8, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s8, // CHECK-NEXT: // (anyext:{ *:[i16] } i8:{ *:[i8] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } (INSERT_SUBREG:{ *:[i32] } (IMPLICIT_DEF:{ *:[i32] }), A0b:{ *:[i8] }:$src, lo8:{ *:[i32] }), lo16:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, @@ -51,12 +51,13 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>; // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(MyTarget::A0RegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(MyTarget::A0bRegClassID), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(MyTarget::lo16), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::A0wRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage +// CHECK-NEXT: GIR_EraseRootFromParent_Done, def : Pat<(i16 (anyext i8:$src)), (i16 (EXTRACT_SUBREG (i32 (INSERT_SUBREG diff --git a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td index 86a6e1651fca503946dc9d20f269789037ca9821..622d7fa1f7955ccf9d29b9d48c0284e331035241 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td +++ b/llvm/test/TableGen/GlobalISelEmitter-notype-output-pattern.td @@ -6,11 +6,11 @@ include "GlobalISelEmitterCommon.td" // CHECK: constexpr static uint8_t MatchTable0[] = { // CHECK-NEXT: GIM_Try, // CHECK-NEXT: GIM_CheckOpcode{{.*}}GIMT_Encode2(TargetOpcode::G_ANYEXT), -// CHECK-NEXT: GIM_CheckType{{.*}}/*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType{{.*}}/*Type*/GILLT_s8, -// CHECK-NEXT: GIM_CheckRegBankForClass{{.*}}/*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType{{.*}}/*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType{{.*}}/*Type*/GILLT_s8, +// CHECK-NEXT: GIM_RootCheckRegBankForClass{{.*}}/*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (anyext:{{.*}}=>{{.*}}(SELECT_I4: -// CHECK: GIR_Done, +// CHECK: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label 0: // CHECK-NEXT: GIM_Reject, // CHECK-NEXT: }; diff --git a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td index 30f9c5f4755550dee1edd3917ecd46a86db5c158..7a0242d9a992437ef89baa4d56f5b6fff67dfec5 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-output-discard.td +++ b/llvm/test/TableGen/GlobalISelEmitter-output-discard.td @@ -8,19 +8,20 @@ def ADD_CO : I<(outs GPR32:$dst, GPR8:$flag), (ins GPR32Op:$src0, GPR32Op:$src1), []>; // GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (ADD_CO:{ *:[i32] }:{ *:[i8] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) // GISEL-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s8, -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD_CO), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_CO), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // GISEL-NEXT: GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 -// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1 +// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, +// GISEL-NEXT: // GIR_Coverage +// GISEL-NEXT: GIR_EraseRootFromParent_Done, def : Pat < (add i32:$src0, i32:$src1), (ADD_CO GPR32:$src0, GPR32:$src1) diff --git a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td index dd47b905e57d1707b8829f15900bd3fc96ed2fd6..ddf02240ee1f8badf680a52a2ae016c568eb4a87 100644 --- a/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td +++ b/llvm/test/TableGen/GlobalISelEmitter-zero-reg.td @@ -25,18 +25,19 @@ def INST : PredI<(outs GPR32:$dst), (ins GPR32:$src), []>; // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<><> => (INST:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INST), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INST), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src // CHECK-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::NoRegister), /*AddRegisterRegFlags*/GIMT_Encode2(0), // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage +// CHECK-NEXT: GIR_EraseRootFromParent_Done, def : Pat<(i32 (load GPR32:$src)), (INST GPR32:$src)>; diff --git a/llvm/test/TableGen/GlobalISelEmitter.td b/llvm/test/TableGen/GlobalISelEmitter.td index 961200d9b63542de33a76ac1d21f1e25215d9f83..23b3d6f59b381e0bf9d22240102f7eae228a892c 100644 --- a/llvm/test/TableGen/GlobalISelEmitter.td +++ b/llvm/test/TableGen/GlobalISelEmitter.td @@ -237,29 +237,29 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; } // R19O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R19O: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]] // R19O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), -// R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R19O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, +// R19O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R19O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R19O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R19O-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // // R19C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // -// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R19O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R19O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, // R19N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), // R19N-NEXT: // MIs[0] DstI[dst] -// R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R19N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R19N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: // MIs[0] src1 -// R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R19N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R19N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R19N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R19N-NEXT: // MIs[0] complex_rr:src2a:src2b -// R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// R19N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // // R19N-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex_rr), // R19N-NEXT: // MIs[0] Operand 3 -// R19N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, +// R19N-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // R19C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/3, // MIs[1] // R19N-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, // R19C-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SELECT), @@ -277,7 +277,7 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; } // R19N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, // R19N-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_complex), // R19O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// R19C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// R19C-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // R19O-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex_rr), // R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_complex), // R19O-NEXT: GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_complex), @@ -290,16 +290,15 @@ def HasC : Predicate<"Subtarget->hasC()"> { let RecomputePerFunction = 1; } // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src5a // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src5b // R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// R19C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN3), -// R19C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// R19C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 +// R19C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN3), +// R19C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// R19C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2b // R19C-NEXT: GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2a // R19C-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// R19C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// R19C-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// R19C-NEXT: GIR_RootConstrainSelectedInstOperands, // R19C-NEXT: // GIR_Coverage, 20, -// R19C-NEXT: GIR_Done, +// R19C-NEXT: GIR_EraseRootFromParent_Done, // R19C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // // R19O: // Label [[GROUP_NUM]]: @[[GROUP]] @@ -326,49 +325,48 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), // R21O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R21O: // Label [[CASE_SELECT_NUM]]: @[[CASE_SELECT]] // R21O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), -// R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R21O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, +// R21O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R21O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R21O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R21O-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // // R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 20 // -// R21C-NOT: GIR_Done, +// R21C-NOT: GIR_EraseRootFromParent_Done, // R21C: // GIR_Coverage, 20, -// R21C-NEXT: GIR_Done, +// R21C-NEXT: GIR_EraseRootFromParent_Done, // R21C-NEXT: // Label [[PREV_NUM]]: @[[PREV]] // R21C-NEXT: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), // Rule ID 22 // // -// R21O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// R21O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R21O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R21O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R21N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, // R21N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), // R21N-NEXT: // MIs[0] DstI[dst] -// R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R21N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R21N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R21N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R21N-NEXT: // MIs[0] src1 -// R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R21N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R21N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R21N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R21N-NEXT: // MIs[0] src2 -// R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// R21N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // // R21O-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag), // R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex), // R21N-NEXT: // MIs[0] src3 -// R21N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, +// R21N-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, // R21C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_complex), // R21N-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag), // R21C-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2, complex:{ *:[i32] }:$src3)<> => (INSN2:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src3, complex:{ *:[i32] }:$src2) -// R21C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN2), -// R21C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// R21C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 +// R21C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN2), +// R21C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// R21C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), // R21C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), // R21C-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0 -// R21C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// R21C-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// R21C-NEXT: GIR_RootConstrainSelectedInstOperands, // R21C-NEXT: // GIR_Coverage, 22, -// R21C-NEXT: GIR_Done, +// R21C-NEXT: GIR_EraseRootFromParent_Done, // R21C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // // R21O-NEXT: GIM_Reject, @@ -386,10 +384,10 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), // R20O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R20O: // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]] // R20O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), -// R20O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R20O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R20O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R20O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R20O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R20O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R20O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R20O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // // R20N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 22 // // R20N: // Label [[PREV_NUM]]: @[[PREV]] @@ -399,25 +397,24 @@ def : Pat<(select GPR32:$src1, (complex_rr GPR32:$src2a, GPR32:$src2b), // R20N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // R20N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), // R20N-NEXT: // MIs[0] DstI[dst] -// R20N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R20N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R20N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R20N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R20N-NEXT: // MIs[0] src1 -// R20N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// R20N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // -// R20N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R20N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R20N-NEXT: // MIs[0] src2 -// R20N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R20O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R20N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R20O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R20C-NEXT: GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_complex), // R20C-NEXT: // (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) => (INSN1:{ *:[i32] } GPR32:{ *:[i32] }:$src1, complex:{ *:[i32] }:$src2) -// R20C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSN1), -// R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// R20C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 +// R20C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSN1), +// R20C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// R20C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 // R20C-NEXT: GIR_ComplexRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), -// R20C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// R20C-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// R20C-NEXT: GIR_RootConstrainSelectedInstOperands, // R20C-NEXT: // GIR_Coverage, 21, -// R20C-NEXT: GIR_Done, +// R20C-NEXT: GIR_EraseRootFromParent_Done, // R20C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // // R20O: // Label [[GROUP_NUM]]: @[[GROUP]] @@ -451,10 +448,10 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R00O: // Label [[CASE_SUB_NUM]]: @[[CASE_SUB]] // R00O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), -// R00O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R00O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R00O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R00O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R00O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R00O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R00O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // // R00C: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 21 // // R00C: // Label [[PREV_NUM]]: @[[PREV]] @@ -464,10 +461,10 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // R00N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), // R00N-NEXT: // MIs[0] DstI[dst] -// R00N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R00N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R00N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00N-NEXT: // MIs[0] Operand 1 -// R00N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// R00N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // R00C-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // R00N-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // R00C-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), @@ -481,7 +478,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00N-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00N-NEXT: // MIs[0] Operand 2 -// R00N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// R00N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00C-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] @@ -498,19 +495,17 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00N-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R00O-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// R00C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// R00C-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, +// R00C-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, // R00C-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4)) => (INSNBOB:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3, GPR32:{ *:[i32] }:$src4) -// R00C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::INSNBOB), -// R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R00C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::INSNBOB), +// R00C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src3 // R00C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src4 -// R00C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// R00C-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// R00C-NEXT: GIR_RootConstrainSelectedInstOperands, // R00C-NEXT: // GIR_Coverage, 0, -// R00C-NEXT: GIR_Done, +// R00C-NEXT: GIR_EraseRootFromParent_Done, // R00C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // // R00O-NEXT: GIM_Reject, @@ -518,7 +513,7 @@ def : Pat<(frag GPR32:$src1, complex:$src2, complex:$src3), // R00O-NEXT: GIM_Reject, // R00O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]] // R00O-NEXT: GIM_Reject, -// R00O-NEXT: }; // Size: 2027 bytes +// R00O-NEXT: }; // Size: 1804 bytes def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, GPR32:$src4), [(set GPR32:$dst, @@ -540,28 +535,27 @@ def INSNBOB : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3, G // R01C-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // // R01O-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop), -// R01O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R01O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R01O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R01O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R01O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R01O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // // R01N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_INTRINSIC), // R01N-NEXT: // MIs[0] DstI[dst] -// R01N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R01N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R01N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R01N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R01N-NEXT: // MIs[0] Operand 1 // R01N-NEXT: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_nop), // R01N-NEXT: // MIs[0] src1 -// R01N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// R01N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // -// R01C-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R01C-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R01C-NEXT: // (intrinsic_wo_chain:{ *:[i32] } [[ID:[0-9]+]]:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src1) => (MOV:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// R01C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOV), -// R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// R01C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 -// R01C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// R01C-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// R01C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOV), +// R01C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// R01C-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1 +// R01C-NEXT: GIR_RootConstrainSelectedInstOperands, // R01C-NEXT: // GIR_Coverage, 1, -// R01C-NEXT: GIR_Done, +// R01C-NEXT: GIR_EraseRootFromParent_Done, // R01C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // // R01O-NEXT: GIM_Reject, @@ -579,11 +573,11 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), // R02O: // Label [[CASE_ADD_NUM]]: @[[CASE_ADD]] // R02O: // Label [[CASE_XOR_NUM]]: @[[CASE_XOR]] // R02O-NEXT: GIM_Try, /*On fail goto*//*Label [[GROUP_NUM:[0-9]+]]*/ GIMT_Encode4([[GROUP:[0-9]+]]), -// R02O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R02O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R02O-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// R02O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// R02O-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R02O-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R02O-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R02O-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// R02O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R02O-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // // R02N: GIM_Try, /*On fail goto*//*Label [[PREV_NUM:[0-9]+]]*/ GIMT_Encode4([[PREV:[0-9]+]]), // Rule ID 1 // // R02N: // Label [[PREV_NUM]]: @[[PREV]] @@ -593,24 +587,23 @@ def MOV : I<(outs GPR32:$dst), (ins GPR32:$src1), // R02N-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // R02N-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // R02N-NEXT: // MIs[0] DstI[dst] -// R02N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// R02N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R02N-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// R02N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R02N-NEXT: // MIs[0] src1 -// R02N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// R02N-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// R02N-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// R02N-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // R02N-NEXT: // MIs[0] Operand 2 -// R02N-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// R02N-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // // R02C-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-2) // R02C-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -2:{ *:[i32] }) => (XORI:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// R02C-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORI), -// R02C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// R02C-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORI), +// R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // R02C-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), -// R02C-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// R02C-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// R02C-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// R02C-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 +// R02C-NEXT: GIR_RootConstrainSelectedInstOperands, // R02C-NEXT: // GIR_Coverage, 2, -// R02C-NEXT: GIR_Done, +// R02C-NEXT: GIR_EraseRootFromParent_Done, // R02C-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // // R02O: // Label [[DEFAULT_NUM]]: @[[DEFAULT]] @@ -626,23 +619,22 @@ def XORI : I<(outs GPR32:$dst), (ins m1:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-3) // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -3:{ *:[i32] }) => (XOR:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XOR), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XOR), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 3, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // The -3 is just to distinguish it from the 'not' case below and the other default op case above. @@ -655,24 +647,23 @@ def XOR : I<(outs GPR32:$dst), (ins Z:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-4) // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -4:{ *:[i32] }) => (XORlike:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORlike), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORlike), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 4, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // The -4 is just to distinguish it from the other 'not' cases. @@ -685,25 +676,24 @@ def XORlike : I<(outs GPR32:$dst), (ins m1Z:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-5), // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -5:{ *:[i32] }) => (XORManyDefaults:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORManyDefaults), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORManyDefaults), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 5, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // The -5 is just to distinguish it from the other cases. @@ -716,23 +706,22 @@ def XORManyDefaults : I<(outs GPR32:$dst), (ins m1Z:$src3, Z:$src2, GPR32:$src1) // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-6) // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$src1, -6:{ *:[i32] }) => (XORIb:{ *:[i32] } GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::XORIb), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::XORIb), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/13, -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 6, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // The -6 is just to distinguish it from the other cases. @@ -748,23 +737,22 @@ def XORIb : I<(outs GPR32:$dst), (ins mb:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_XOR), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Wm -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), // NOOPT-NEXT: // (xor:{ *:[i32] } GPR32:{ *:[i32] }:$Wm, -1:{ *:[i32] }) => (ORN:{ *:[i32] } R0:{ *:[i32] }, GPR32:{ *:[i32] }:$Wm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ORN), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ORN), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(MyTarget::R0), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // Wm -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // Wm +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 23, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def ORN : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; @@ -777,10 +765,10 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), @@ -793,19 +781,18 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src3 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // NOOPT-NEXT: // (mul:{ *:[i32] } (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src3) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src3 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src3 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 7, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] // We also get a second rule by commutativity. @@ -815,13 +802,13 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src3 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), @@ -833,17 +820,16 @@ def : Pat<(not GPR32:$Wm), (ORN R0, GPR32:$Wm)>; // NOOPT-NEXT: // MIs[1] src2 // NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// NOOPT-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src3, (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2)) => (MULADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src3) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MULADD), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 // NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src3 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src3 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 28, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3), @@ -857,17 +843,16 @@ def MULADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2, GPR32:$src3), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: GIM_CheckLiteralInt, /*MI*/0, /*Op*/1, GIMT_Encode8(1), // NOOPT-NEXT: // 1:{ *:[i32] } => (MOV1:{ *:[i32] }) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOV1), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOV1), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 8, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>; @@ -879,18 +864,17 @@ def MOV1 : I<(outs GPR32:$dst), (ins), [(set GPR32:$dst, 1)]>; // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_simm8), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<>:$imm => (MOVimm8:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm8), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm8), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 9, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def simm8 : ImmLeaf(Imm); }]>; @@ -903,18 +887,17 @@ def MOVimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm8:$i // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_simm9), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<>:$imm => (MOVimm9:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm9), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm9), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 10, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def simm9 : IntImmLeaf(Imm->getSExtValue()); }]>; @@ -927,18 +910,17 @@ def MOVimm9 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, simm9:$i // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: GIM_CheckI64ImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_cimm8), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] })<><>:$imm => (MOVcimm8:{ *:[i32] } (cimm8_xform:{ *:[i32] } (imm:{ *:[i32] }):$imm)) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVcimm8), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVcimm8), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderImm), // imm -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 11, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$imm)]>; @@ -950,18 +932,17 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$ // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FCONSTANT), // NOOPT-NEXT: GIM_CheckAPFloatImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimmz), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (fpimm:{ *:[f32] })<>:$imm => (MOVfpimmz:{ *:[f32] } (fpimm:{ *:[f32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVfpimmz), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVfpimmz), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyFConstantAsFPImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 18, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] //===- Test a simple pattern with inferred pointer operands. ---------------===// @@ -972,14 +953,14 @@ def MOVcimm8 : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, cimm8:$ // NOOPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<><> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 12, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -995,14 +976,14 @@ def LOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), // NOOPT-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src)<><> => (LOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 24, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1018,14 +999,14 @@ def : Pat<(load GPR32:$src), // NOOPT-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), // NOOPT-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 // NOOPT-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (ld:{ *:[i32] } GPR32:{ *:[i32] }:$src1)<><><> => (SEXTLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SEXTLOAD), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 13, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1039,17 +1020,17 @@ def SEXTLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID) +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID) // NOOPT-NEXT: // MIs[0] src2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 14, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1063,21 +1044,20 @@ def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src{{$}} -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src{{$}} // NOOPT-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, // NOOPT-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src, GPR32:{ *:[i32] }:$src) => (DOUBLE:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::DOUBLE), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::DOUBLE), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 15, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32:$src, GPR32:$src))]>; @@ -1094,15 +1074,15 @@ def DOUBLE : I<(outs GPR32:$dst), (ins GPR32:$src), [(set GPR32:$dst, (add GPR32 // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[samename] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] samename -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: // MIs[0] othername -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) => (InsnWithSpeciallyNamedDef:{ *:[i32] } i32:{ *:[i32] }:$samename, i32:{ *:[i32] }:$othername) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InsnWithSpeciallyNamedDef), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 25, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1117,15 +1097,15 @@ def : Pat<(add i32:$samename, i32:$othername), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // NOOPT-NEXT: // MIs[0] src2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // NOOPT-NEXT: // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (ADD:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 26, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1140,23 +1120,22 @@ def : Pat<(add i32:$src1, i32:$src2), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src2 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (MUL:{ *:[i32] } GPR32:{ *:[i32] }:$src2, GPR32:{ *:[i32] }:$src1) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src2 -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src1 -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src2 +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src1 +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 16, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1), @@ -1170,11 +1149,11 @@ def MUL : I<(outs GPR32:$dst), (ins GPR32:$src2, GPR32:$src1), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BITCAST), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] src1 -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::FPR32RegClassID), // NOOPT-NEXT: // (bitconvert:{ *:[i32] } FPR32:{ *:[f32] }:$src1) => (COPY_TO_REGCLASS:{ *:[i32] } FPR32:{ *:[f32] }:$src1, GPR32:{ *:[i32] }) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // NOOPT-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(MyTarget::GPR32RegClassID), @@ -1191,18 +1170,17 @@ def : Pat<(i32 (bitconvert FPR32:$src1)), // NOOPT-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // NOOPT-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_CONSTANT), // NOOPT-NEXT: // MIs[0] DstI[dst] -// NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// NOOPT-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// NOOPT-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// NOOPT-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // NOOPT-NEXT: // MIs[0] Operand 1 // NOOPT-NEXT: // No operand predicates // NOOPT-NEXT: // (imm:{ *:[i32] }):$imm => (MOVimm:{ *:[i32] } (imm:{ *:[i32] }):$imm) -// NOOPT-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm), -// NOOPT-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// NOOPT-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MOVimm), +// NOOPT-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // NOOPT-NEXT: GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// NOOPT-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 17, -// NOOPT-NEXT: GIR_Done, +// NOOPT-NEXT: GIR_EraseRootFromParent_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] def MOVimm : I<(outs GPR32:$dst), (ins i32imm:$imm), [(set GPR32:$dst, imm:$imm)]>; @@ -1219,7 +1197,7 @@ def MOVfpimmz : I<(outs FPR32:$dst), (ins f32imm:$imm), [(set FPR32:$dst, fpimmz // NOOPT-NEXT: GIM_CheckIsMBB, /*MI*/0, /*Op*/0, // NOOPT-NEXT: // (br (bb:{ *:[Other] }):$target) => (BR (bb:{ *:[Other] }):$target) // NOOPT-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::BR), -// NOOPT-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// NOOPT-NEXT: GIR_RootConstrainSelectedInstOperands, // NOOPT-NEXT: // GIR_Coverage, 19, // NOOPT-NEXT: GIR_Done, // NOOPT-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -1228,5 +1206,5 @@ def BR : I<(outs), (ins unknown:$target), [(br bb:$target)]>; // NOOPT-NEXT: GIM_Reject, -// NOOPT-NEXT: }; // Size: 1738 bytes +// NOOPT-NEXT: }; // Size: 1459 bytes // NOOPT-NEXT: return MatchTable0; diff --git a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td index ed43ff2f14fa2afcb43fd18b5109d8bedbbd8eab..3ceadf32f06425e7818fceb86a6e9f30f3f3905d 100644 --- a/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td +++ b/llvm/test/TableGen/GlobalISelEmitterCustomPredicate.td @@ -73,18 +73,18 @@ def and_or_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(110), // Rule ID 7 // +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(97), // Rule ID 7 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] Operand 2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), @@ -99,18 +99,18 @@ def and_or_pat : PatFrag< // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (and:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:3:z, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y))<> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), -// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(220), // Rule ID 3 // +// CHECK: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(194), // Rule ID 3 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_AND), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), @@ -125,13 +125,13 @@ def and_or_pat : PatFrag< // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_and_or_pat), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (and:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0:$pred:3:x, DOP:{ *:[i32] }:$src1:$pred:3:y), DOP:{ *:[i32] }:$src2:$pred:3:z)<> => (AND_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::AND_OR), // Test commutative, standalone pattern. def : Pat< @@ -148,14 +148,14 @@ def mul_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(326), // Rule ID 4 // +// CHECK: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(287), // Rule ID 4 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, @@ -169,26 +169,26 @@ def mul_pat : PatFrag< // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (mul:{ *:[i32] } (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x, DOP:{ *:[i32] }:$src2:$pred:4:y)<> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), -// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(432), // Rule ID 8 // +// CHECK: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(380), // Rule ID 8 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/1, // Name : pred:4:y -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] Operand 2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/0, // Name : pred:4:x // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, @@ -202,9 +202,9 @@ def mul_pat : PatFrag< // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_mul_pat), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (mul:{ *:[i32] } DOP:{ *:[i32] }:$src2:$pred:4:y, (or:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1):$pred:4:x)<> => (MUL_OR:{ *:[i32] } DOP:{ *:[i32] }:$src0, DOP:{ *:[i32] }:$src1, DOP:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_OR), // Test commutative patterns where named operands in the source pattern are not // directly bound to PatFrag's operands. @@ -223,14 +223,14 @@ def sub3_pat : PatFrag< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(527), // Rule ID 0 // +// CHECK: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(463), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SUB), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] Operand 1 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), @@ -243,12 +243,12 @@ def sub3_pat : PatFrag< // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y // CHECK-NEXT: // MIs[0] src2 -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_sub3_pat), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (sub:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y), i32:{ *:[i32] }:$src2:$pred:1:z)<> => (SUB3:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUB3) +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUB3) // Test a non-commutative pattern. def SUB3 : I<(outs DRegs:$dst), @@ -269,16 +269,16 @@ def patfrags_test_pat : PatFrags< let PredicateCodeUsesOperands = 1; } -// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(622), // Rule ID 1 // +// CHECK: GIM_Try, /*On fail goto*//*Label 5*/ GIMT_Encode4(546), // Rule ID 1 // // CHECK: // (xor:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(717), // Rule ID 2 // +// CHECK: GIM_Try, /*On fail goto*//*Label 6*/ GIMT_Encode4(629), // Rule ID 2 // // CHECK: // (xor:{ *:[i32] } (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y), i32:{ *:[i32] }:$src2:$pred:2:z)<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(812), // Rule ID 5 // +// CHECK: GIM_Try, /*On fail goto*//*Label 7*/ GIMT_Encode4(712), // Rule ID 5 // // CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) -// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(907), // Rule ID 6 // +// CHECK: GIM_Try, /*On fail goto*//*Label 8*/ GIMT_Encode4(795), // Rule ID 6 // // CHECK: // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (sub:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y))<> => (PATFRAGS:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) diff --git a/llvm/test/TableGen/GlobalISelEmitterFlags.td b/llvm/test/TableGen/GlobalISelEmitterFlags.td index 2025a2c1048e0216583fca4166d1ba1e50f25046..fa8f2a79fbce89ab268af013a1e2935c278afe0a 100644 --- a/llvm/test/TableGen/GlobalISelEmitterFlags.td +++ b/llvm/test/TableGen/GlobalISelEmitterFlags.td @@ -42,7 +42,7 @@ def : Pat< // CHECK: GIM_CheckIsSameOperand, /*MI*/2, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: // (srl:{ *:[i32] } (srl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0) -// CHECK: GIR_Done +// CHECK: GIR_EraseRootFromParent_Done // CHECK: GIM_Try // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL) @@ -51,10 +51,10 @@ def : Pat< // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1 // CHECK: // (srl:{ *:[i32] } (shl:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src0) -// CHECK: GIR_Done +// CHECK: GIR_EraseRootFromParent_Done // CHECK: GIM_Try // CHECK: GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] // CHECK: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL) // CHECK: GIM_CheckIsSameOperandIgnoreCopies, /*MI*/1, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1 // CHECK: // (sub:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src1) -// CHECK: GIR_Done +// CHECK: GIR_EraseRootFromParent_Done diff --git a/llvm/test/TableGen/GlobalISelEmitterHwModes.td b/llvm/test/TableGen/GlobalISelEmitterHwModes.td index b96e9db0134bfe36b486ee24c6b890f44af35dd2..7c8340a154e8bee6b91f65889b645180bd52b19f 100644 --- a/llvm/test/TableGen/GlobalISelEmitterHwModes.td +++ b/llvm/test/TableGen/GlobalISelEmitterHwModes.td @@ -134,14 +134,14 @@ class I Pat> // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src1 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src1)<><> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src1) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -152,14 +152,14 @@ class I Pat> // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src1 // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src1)<><> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src1) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -176,14 +176,14 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i64] } GPR:{ *:[i64] }:$src)<><> => (LOAD:{ *:[i64] } GPR:{ *:[i64] }:$src) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] @@ -194,14 +194,14 @@ def LOAD : I<(outs GPR:$dst), (ins GPR:$src1), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_p0s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPRRegClassID), // CHECK-NEXT: // (ld:{ *:[i32] } GPR:{ *:[i32] }:$src)<><> => (LOAD:{ *:[i32] } GPR:{ *:[i32] }:$src) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 3, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td index 5b534970d4d4fcd4e2da5876d0f231ac75885e45..3db31bea8612eefd7a0a841972a2823071a2bccc 100644 --- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td +++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizer.td @@ -11,24 +11,24 @@ def LOAD32 : I<(outs GPR8:$dst), (ins GPR32:$src), []>; // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ GIMT_Encode4([[L1_AT:[0-9]+]]), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ GIMT_Encode4([[L2_AT:[0-9]+]]), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/8, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR8RegClassID), // CHECK-NEXT: // (ld:{ *:[i8] } GPR8:{ *:[i8] }:$src)<><> => (LOAD8:{ *:[i8] } GPR8:{ *:[i8] }:$src) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD8), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[L2_ID]]: @[[L2_AT]] // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (ld:{ *:[i8] } GPR32:{ *:[i32] }:$src)<><> => (LOAD32:{ *:[i8] } GPR32:{ *:[i32] }:$src) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD32), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[L3_ID]]: @[[L3_AT]] @@ -49,7 +49,7 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>; // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L1_ID:[0-9]+]]*/ GIMT_Encode4([[L1_AT:[0-9]+]]), // CHECK-NEXT: GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // CHECK-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/16, // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L2_ID:[0-9]+]]*/ GIMT_Encode4([[L2_AT:[0-9]+]]), // CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] @@ -58,22 +58,21 @@ def LOAD16Imm : I<(outs GPR16:$dst), (ins GPR16:$src), []>; // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), // CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 10, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (ld:{ *:[i16] } (add:{ *:[i16] } GPR16:{ *:[i16] }:$src, 10:{ *:[i16] }))<><> => (LOAD16Imm:{ *:[i16] } GPR16:{ *:[i16] }:$src) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16Imm), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 3, -// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // CHECK-NEXT: // Label [[L2_ID]]: @[[L2_AT]] // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label [[L3_ID:[0-9]+]]*/ GIMT_Encode4([[L3_AT:[0-9]+]]), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR16RegClassID), // CHECK-NEXT: // (ld:{ *:[i16] } GPR16:{ *:[i16] }:$src)<><> => (LOAD16:{ *:[i16] } GPR16:{ *:[i16] }:$src) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::LOAD16), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 2, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label [[L3_ID]]: @[[L3_AT]] diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td index 729a30e8cbf3001cec476c6e0661c7b6345497b2..d93805b612a19e85a158919be146425c7d29678c 100644 --- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td +++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand-invalid.td @@ -5,88 +5,83 @@ include "GlobalISelEmitterCommon.td" def InstTwoOperands : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32:$src2), []>; - -// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(255), -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(217), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2, -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(126), // Rule ID 1 // -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] Operand 1 -// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0, -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), -// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: // GIR_Coverage, 1, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 2: @126 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(216), // Rule ID 2 // -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: // MIs[1] Operand 1 -// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0, -// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] -// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), -// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/2, -// CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, -// CHECK-NEXT: // GIR_Coverage, 2, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 3: @216 -// CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 1: @217 -// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(254), // Rule ID 0 // -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/3, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) -// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: // GIR_Coverage, 0, -// CHECK-NEXT: GIR_Done, -// CHECK-NEXT: // Label 4: @254 -// CHECK-NEXT: GIM_Reject, -// CHECK-NEXT: // Label 0: @255 -// CHECK-NEXT: GIM_Reject, +// CHECK: GIM_Try, /*On fail goto*//*Label 0*/ GIMT_Encode4(229), +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SELECT), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4(197), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/2, +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4(114), // Rule ID 1 // +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] Operand 1 +// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0, +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), +// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, +// CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETEQ:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 1, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 2: @114 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 3*/ GIMT_Encode4(196), // Rule ID 2 // +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ICMP), +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, +// CHECK-NEXT: // MIs[1] Operand 1 +// CHECK-NEXT: GIM_CheckCmpPredicate, /*MI*/1, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckConstantInt8, /*MI*/1, /*Op*/3, 0, +// CHECK-NEXT: GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SUB), +// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/2, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/2, +// CHECK-NEXT: // (select:{ *:[i32] } (setcc:{ *:[i32] } GPR32:{ *:[i32] }:$cond, 0:{ *:[i32] }, SETNE:{ *:[Other] }), (sub:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2), GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // cond +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 +// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 2, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label 3: @196 +// CHECK-NEXT: GIM_Reject, +// CHECK-NEXT: // Label 1: @197 +// CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 4*/ GIMT_Encode4(228), // Rule ID 0 // +// CHECK-NEXT: GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: // (select:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (InstThreeOperands:{ *:[i32] } GPR32:{ *:[i32] }:$cond, GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) +// CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::InstThreeOperands), +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 0, +// CHECK-NEXT: GIR_Done, +// CHECK-NEXT: // Label 4: @228 +// CHECK-NEXT: GIM_Reject, +// CHECK-NEXT: // Label 0: @229 +// CHECK-NEXT: GIM_Reject, def : Pat<(i32 (select GPR32:$cond, GPR32:$src1, GPR32:$src2)), (InstThreeOperands GPR32:$cond, GPR32:$src1, GPR32:$src2)>; diff --git a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td index 00ece5f4ca7989bce7c0e4af7f3711d05a73a4af..1ac33990ab3b10ce19bb2777c82e80919dfbc39e 100644 --- a/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td +++ b/llvm/test/TableGen/GlobalISelEmitterMatchTableOptimizerSameOperand.td @@ -9,7 +9,7 @@ def InstThreeOperands : I<(outs GPR32:$dst), (ins GPR32:$cond, GPR32:$src,GPR32: // Make sure the GIM_CheckIsSameOperand check is not hoisted into the common header group // CHECK: GIM_Try, /*On fail goto*//*Label 1*/ -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NOT: GIM_CheckIsSameOperand // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ // CHECK: GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/3, /*OtherMI*/2, /*OtherOpIdx*/1, diff --git a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td index 64723a0bbd4b68b64d4fa98a7757d7a225f578df..422edbba0e7a0f042d7ed0b771ff4c44566e3cb0 100644 --- a/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td +++ b/llvm/test/TableGen/GlobalISelEmitterOverloadedPtr.td @@ -12,14 +12,14 @@ let TargetPrefix = "mytarget" in { // GIM_CheckPointerToAny rather than a GIM_CheckType. // // CHECK: GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::mytarget_anyptr), -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // MIs[0] src // CHECK-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_frag_anyptr), // CHECK-NEXT: // (intrinsic_w_chain:{ *:[i32] } {{[0-9]+}}:{ *:[iPTR] }, GPR32:{ *:[i32] }:$src)<> => (ANYLOAD:{ *:[i32] } GPR32:{ *:[i32] }:$src) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ANYLOAD), let hasSideEffects = 1 in { def ANYLOAD : I<(outs GPR32:$dst), (ins GPR32:$src1), [(set GPR32:$dst, (load GPR32:$src1))]>; diff --git a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td index 42ac68b9d91d97efe76750aedd39068e0f877d50..3829070b28efebac6cb11db4c004b1435afd179a 100644 --- a/llvm/test/TableGen/GlobalISelEmitterRegSequence.td +++ b/llvm/test/TableGen/GlobalISelEmitterRegSequence.td @@ -33,11 +33,11 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>; // CHECK: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_SEXT), // CHECK-NEXT: // MIs[0] DstI[dst] -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: // MIs[0] src -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s16, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: // (sext:{ *:[i32] } SOP:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i32] } DRegs:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub0:{ *:[i32] }, (SUBSOME_INSN:{ *:[i16] } SOP:{ *:[i16] }:$src), sub1:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, @@ -49,8 +49,8 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>; // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/1, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, @@ -58,7 +58,8 @@ def SUBSOME_INSN : I<(outs SRegs:$dst), (ins SOP:$src), []>; // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 0, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, def : Pat<(i32 (sext SOP:$src)), (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, (SUBSOME_INSN SOP:$src), sub1)>; @@ -74,7 +75,7 @@ def : Pat<(i32 (sext SOP:$src)), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // Make sure operands are constrained when REG_SEQUENCE isn't the root instruction. def : Pat<(i32 (zext SOP:$src)), (SOME_INSN (REG_SEQUENCE DRegs, (SUBSOME_INSN SOP:$src), sub0, diff --git a/llvm/test/TableGen/GlobalISelEmitterSubreg.td b/llvm/test/TableGen/GlobalISelEmitterSubreg.td index 94e321e638c5f13ce9fda0ab76e645f3dfe785a2..8df3238f6cc21e42aa20e875738f8bf3c502f9b2 100644 --- a/llvm/test/TableGen/GlobalISelEmitterSubreg.td +++ b/llvm/test/TableGen/GlobalISelEmitterSubreg.td @@ -71,12 +71,13 @@ def : Pat<(sub (complex DOP:$src1, DOP:$src2), 77), // CHECK-NEXT: GIR_ComplexSubOperandSubRegRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, /*SubRegIdx*/GIMT_Encode2(1), // src1 // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN2), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN2), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 2, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // Test that we import INSERT_SUBREG when its subregister source has a given // class. @@ -86,15 +87,16 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), SOP:$src // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 3, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // Test that we can import INSERT_SUBREG when it is a subinstruction of another @@ -114,11 +116,12 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF) // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 4, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // Test that we correctly infer the super register class for INSERT_SUBREG when @@ -126,7 +129,7 @@ def : Pat<(i32 (anyext i16:$src)), (SOME_INSN (INSERT_SUBREG (i32 (IMPLICIT_DEF) // not a D register. def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (COPY_TO_REGCLASS SOP:$src, ERegs)), SOP:$src, sub0)>; // CHECK-LABEL: (anyext:{ *:[i32] } i16:{ *:[i16] }:$src) => (INSERT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } SOP:{ *:[i16] }:$src, ERegs:{ *:[i32] }), SOP:{ *:[i16] }:$src, sub0:{ *:[i32] }) -// CHECK: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), +// CHECK: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), // CHECK-DAG: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::ERegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::ERegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), @@ -144,15 +147,16 @@ def : Pat<(i32 (anyext i16:$src)), (INSERT_SUBREG (i32 (IMPLICIT_DEF)), (SUBSOME // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::INSERT_SUBREG), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 6, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // Test an EXTRACT_SUBREG that is a sub instruction. The individual // operands should be constrained to specific register classes, and @@ -166,7 +170,7 @@ def : Pat<(i16 (trunc (not DOP:$src))), // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN), // Test an extract from an output instruction result (nonleaf) def : Pat<(i16 (trunc (bitreverse DOP:$src))), @@ -174,26 +178,27 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))), // CHECK-LABEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITREVERSE), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (trunc:{ *:[i16] } (bitreverse:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] }) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, // CHECK-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(MyTarget::SOME_INSN), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 8, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // EXTRACT_SUBREG is subinstruction, but also doesn't have a leaf input // CHECK-LABEL: GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP), // CHECK-NEXT: GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, // CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1, +// CHECK-NEXT: GIM_CheckIsSafeToFold, /*NumInsns*/1, // CHECK-NEXT: // (trunc:{ *:[i16] } (ctpop:{ *:[i32] } DOP:{ *:[i32] }:$src)) => (SUBSOME_INSN2:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i16] } (SOME_INSN:{ *:[i32] } DOP:{ *:[i32] }:$src), sub0:{ *:[i32] })) // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, // CHECK-NEXT: GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, @@ -206,11 +211,12 @@ def : Pat<(i16 (trunc (bitreverse DOP:$src))), // CHECK-NEXT: GIR_AddTempSubRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(sub0), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN2), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SUBSOME_INSN2), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 9, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, def : Pat<(i16 (trunc (ctpop DOP:$src))), (SUBSOME_INSN2 (EXTRACT_SUBREG (SOME_INSN DOP:$src), sub0))>; @@ -218,13 +224,13 @@ def : Pat<(i16 (trunc (ctpop DOP:$src))), def : Pat<(i16 (trunc DOP:$src)), (EXTRACT_SUBREG DOP:$src, sub0)>; // CHECK-LABEL: // (trunc:{ *:[i16] } DOP:{ *:[i32] }:$src) => (EXTRACT_SUBREG:{ *:[i16] } DOP:{ *:[i32] }:$src, sub0:{ *:[i32] }) -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_CopySubReg, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(1), // src // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::SRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(Test::DRegsRegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, - +// CHECK-NEXT: // GIR_Coverage, 10, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, // Test that we can import SUBREG_TO_REG def : Pat<(i32 (zext SOP:$src)), @@ -235,11 +241,12 @@ def : Pat<(i32 (zext SOP:$src)), // CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), // CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src // CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/1, -// CHECK-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), -// CHECK-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::SUBREG_TO_REG), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, // CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, // CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/1, // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(Test::DRegsRegClassID), // CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/2, GIMT_Encode2(Test::SRegsRegClassID), -// CHECK-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// CHECK-NEXT: // GIR_Coverage, 11, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, diff --git a/llvm/test/TableGen/GlobalISelEmitterVariadic.td b/llvm/test/TableGen/GlobalISelEmitterVariadic.td index ba6a93bd4837f23b68b1362f3105c8f6d1ef065e..992e1a4b907c309bb94ff8af0e7ee29d3b7d8360 100644 --- a/llvm/test/TableGen/GlobalISelEmitterVariadic.td +++ b/llvm/test/TableGen/GlobalISelEmitterVariadic.td @@ -26,27 +26,27 @@ def : Pat<(build_vector GPR32:$src1, GPR32:$src2), // CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 1*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_1:[0-9]+]]), // Rule ID 0 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1) => (ONE:{ *:[i32] } GPR32:{ *:[i32] }:$src1) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ONE), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 0, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label 1: @[[NEXT_NUM_OPERANDS_LABEL_1]] // CHECK-NEXT: GIM_Try, /*On fail goto*//*Label 2*/ GIMT_Encode4([[NEXT_NUM_OPERANDS_LABEL_2:[0-9]+]]), // Rule ID 1 // // CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), -// CHECK-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // CHECK-NEXT: // (build_vector:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) => (TWO:{ *:[i32] } GPR32:{ *:[i32] }:$src1, GPR32:{ *:[i32] }:$src2) // CHECK-NEXT: GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::TWO), -// CHECK-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, // CHECK-NEXT: // GIR_Coverage, 1, // CHECK-NEXT: GIR_Done, // CHECK-NEXT: // Label 2: @[[NEXT_NUM_OPERANDS_LABEL_2]] diff --git a/llvm/test/TableGen/HasNoUse.td b/llvm/test/TableGen/HasNoUse.td index 4fe10cd44e4fbc90a562dd2dd3ff01f77e824676..030598d1cbeec0b8c9d0dcdb1117e61702c3f69b 100644 --- a/llvm/test/TableGen/HasNoUse.td +++ b/llvm/test/TableGen/HasNoUse.td @@ -17,19 +17,20 @@ def NO_RET_ATOMIC_ADD : I<(outs), (ins GPR32Op:$src0, GPR32Op:$src1), []>; // SDAG-NEXT: return true; // GISEL: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ATOMICRMW_ADD), -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, // GISEL-NEXT: GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), // GISEL-NEXT: GIM_CheckHasNoUse, /*MI*/0, // GISEL-NEXT: // MIs[0] src0 // GISEL-NEXT: GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, // GISEL-NEXT: // (atomic_load_add:{ *:[i32] } iPTR:{ *:[iPTR] }:$src0, i32:{ *:[i32] }:$src1)<> => (NO_RET_ATOMIC_ADD GPR32:{ *:[i32] }:$src0, GPR32:{ *:[i32] }:$src1) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::NO_RET_ATOMIC_ADD), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src1 +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::NO_RET_ATOMIC_ADD), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/2, // src1 // GISEL-NEXT: GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, -// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, +// GISEL-NEXT: // GIR_Coverage, 0, +// GISEL-NEXT: GIR_EraseRootFromParent_Done, let HasNoUse = true in defm atomic_load_add_no_ret : binary_atomic_op; diff --git a/llvm/test/TableGen/address-space-patfrags.td b/llvm/test/TableGen/address-space-patfrags.td index 46050a70720fbe1713cd6f49ca719a882293533d..582b97d55a518579782a955967b7def9da1200f3 100644 --- a/llvm/test/TableGen/address-space-patfrags.td +++ b/llvm/test/TableGen/address-space-patfrags.td @@ -102,7 +102,7 @@ def truncstorei16_addrspace : PatFrag<(ops node:$val, node:$ptr), // GISEL-NEXT: GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, // GISEL-NEXT: GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, // GISEL-NEXT: // MIs[0] src0 -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, def : Pat < (truncstore GPR32:$src0, GPR32:$src1), (inst_c GPR32:$src0, GPR32:$src1) diff --git a/llvm/test/TableGen/gisel-physreg-input.td b/llvm/test/TableGen/gisel-physreg-input.td index b0af5b7dd3c117d0389d34c8e9a7712ddff6087c..f19872a331fc89c064994520d939eca87b7274f1 100644 --- a/llvm/test/TableGen/gisel-physreg-input.td +++ b/llvm/test/TableGen/gisel-physreg-input.td @@ -28,23 +28,24 @@ class I Pat> // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_ADD), // GISEL-NEXT: // MIs[0] DstI[dst] -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] src0 -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] Operand 2 -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: // (add:{ *:[i32] } GPR32:{ *:[i32] }:$src0, SPECIAL:{ *:[i32] }) => (ADD_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$src0) // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src0 -// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD_PHYS), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src0 +// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, +// GISEL-NEXT: // GIR_Coverage, 0, +// GISEL-NEXT: GIR_EraseRootFromParent_Done, def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0), [(set GPR32:$dst, (add GPR32:$src0, SPECIAL))]> { let Uses = [SPECIAL]; @@ -56,23 +57,24 @@ def ADD_PHYS : I<(outs GPR32:$dst), (ins GPR32:$src0), // GISEL-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, // GISEL-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_MUL), // GISEL-NEXT: // MIs[0] DstI[dst] -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/0, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] SPECIAL -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/1, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), // GISEL-NEXT: // MIs[0] Operand 2 -// GISEL-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_s32, -// GISEL-NEXT: GIM_CheckRegBankForClass, /*MI*/0, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), +// GISEL-NEXT: GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, +// GISEL-NEXT: GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(MyTarget::Special32RegClassID), // GISEL-NEXT: // (mul:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL, SPECIAL:{ *:[i32] }) => (MUL_PHYS:{ *:[i32] } GPR32:{ *:[i32] }:$SPECIAL) // GISEL-NEXT: GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), // GISEL-NEXT: GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(MyTarget::SPECIAL), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), // GISEL-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // SPECIAL -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst] -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // SPECIAL -// GISEL-NEXT: GIR_ConstrainSelectedInstOperands, /*InsnID*/0, -// GISEL-NEXT: GIR_EraseFromParent, /*InsnID*/0, +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::MUL_PHYS), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // SPECIAL +// GISEL-NEXT: GIR_RootConstrainSelectedInstOperands, +// GISEL-NEXT: // GIR_Coverage, 1, +// GISEL-NEXT: GIR_EraseRootFromParent_Done, def MUL_PHYS : I<(outs GPR32:$dst), (ins GPR32:$SPECIAL), [(set GPR32:$dst, (mul GPR32:$SPECIAL, SPECIAL))]> { let Uses = [SPECIAL]; diff --git a/llvm/test/TableGen/immarg-predicated.td b/llvm/test/TableGen/immarg-predicated.td index 320018010cc7fec571b1a4b035a0fe700cb8e6c6..dcacb2f8f1de35ac4c0599ee925c576f1d8cd7c2 100644 --- a/llvm/test/TableGen/immarg-predicated.td +++ b/llvm/test/TableGen/immarg-predicated.td @@ -14,8 +14,8 @@ def int_mytarget_sleep0 : Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, // GISEL-NEXT: GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_tuimm9), // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] })<>:$src) => (SLEEP0 (timm:{ *:[i32] }):$src) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src def tuimm9 : TImmLeaf(Imm); }]>; def SLEEP0 : I<(outs), (ins i32imm:$src), [(int_mytarget_sleep0 tuimm9:$src)] diff --git a/llvm/test/TableGen/immarg.td b/llvm/test/TableGen/immarg.td index 80849d512bee3013ee6b0096af9f76c777adb57a..e5fd06ce6c083f833f325e2e406afac5fffd190d 100644 --- a/llvm/test/TableGen/immarg.td +++ b/llvm/test/TableGen/immarg.td @@ -14,8 +14,8 @@ def int_mytarget_sleep1 : Intrinsic<[], [llvm_i32_ty], [ImmArg>]>; // GISEL-NEXT: // MIs[0] src // GISEL-NEXT: GIM_CheckIsImm, /*MI*/0, /*Op*/1, // GISEL-NEXT: // (intrinsic_void {{[0-9]+}}:{ *:[iPTR] }, (timm:{ *:[i32] }):$src) => (SLEEP0 (timm:{ *:[i32] }):$src) -// GISEL-NEXT: GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), -// GISEL-NEXT: GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, // src +// GISEL-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::SLEEP0), +// GISEL-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // src def SLEEP0 : I<(outs), (ins i32imm:$src), [(int_mytarget_sleep0 timm:$src)] >; diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll index 3806159ab7303c199ad9ec67b424c0471dc0409a..324b6d2f65964abdeb02ba56153a2530f35c5ffb 100644 --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-i16.ll @@ -918,7 +918,7 @@ define half @test_atomicrmw_xchg_f16_global_agent(ptr addrspace(1) %ptr, half %v ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP5]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] syncscope("agent") seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -942,7 +942,7 @@ define half @test_atomicrmw_xchg_f16_global_agent_align4(ptr addrspace(1) %ptr, ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -65536 ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP2]] -; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] syncscope("agent") seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -973,7 +973,7 @@ define half @test_atomicrmw_xchg_f16_flat_agent(ptr %ptr, half %value) { ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP5]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] syncscope("agent") seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -997,7 +997,7 @@ define half @test_atomicrmw_xchg_f16_flat_agent_align4(ptr %ptr, half %value) { ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -65536 ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP2]] -; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr [[PTR]], i32 [[LOADED]], i32 [[TMP5]] syncscope("agent") seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1028,7 +1028,7 @@ define bfloat @test_atomicrmw_xchg_bf16_global_agent(ptr addrspace(1) %ptr, bflo ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP5]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP6:%.*]] = and i32 [[LOADED]], [[INV_MASK]] ; CHECK-NEXT: [[TMP7:%.*]] = or i32 [[TMP6]], [[VALOPERAND_SHIFTED]] -; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP7]] syncscope("agent") seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP8]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] @@ -1052,7 +1052,7 @@ define bfloat @test_atomicrmw_xchg_bf16_global_agent_align4(ptr addrspace(1) %pt ; CHECK-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP3]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[LOADED]], -65536 ; CHECK-NEXT: [[TMP5:%.*]] = or i32 [[TMP4]], [[TMP2]] -; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] seq_cst seq_cst, align 4 +; CHECK-NEXT: [[TMP6:%.*]] = cmpxchg ptr addrspace(1) [[PTR]], i32 [[LOADED]], i32 [[TMP5]] syncscope("agent") seq_cst seq_cst, align 4 ; CHECK-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP6]], 1 ; CHECK-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP6]], 0 ; CHECK-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll new file mode 100644 index 0000000000000000000000000000000000000000..d51e9291a6119ca3b9561e14bfa6c4039ff8b3e2 --- /dev/null +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/expand-atomic-mmra.ll @@ -0,0 +1,204 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 + +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a -verify-each -atomic-expand %s | FileCheck -check-prefix=GFX90A %s +; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 -verify-each -atomic-expand %s | FileCheck -check-prefix=GFX1100 %s + +; Contains a variety of tests with different types of atomic expansions to check that MMRAs are +; preserved. + +define i16 @test_atomicrmw_xchg_i16_global_agent(ptr addrspace(1) %ptr, i16 %value) { +; GFX90A-LABEL: define i16 @test_atomicrmw_xchg_i16_global_agent( +; GFX90A-SAME: ptr addrspace(1) [[PTR:%.*]], i16 [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +; GFX90A-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR]], i64 -4) +; GFX90A-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 +; GFX90A-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 +; GFX90A-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 +; GFX90A-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 +; GFX90A-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] +; GFX90A-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 +; GFX90A-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE]] to i32 +; GFX90A-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] +; GFX90A-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4, !mmra [[META0:![0-9]+]] +; GFX90A-NEXT: br label [[ATOMICRMW_START:%.*]] +; GFX90A: atomicrmw.start: +; GFX90A-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; GFX90A-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]] +; GFX90A-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]] +; GFX90A-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] syncscope("agent") seq_cst seq_cst, align 4, !mmra [[META0]] +; GFX90A-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; GFX90A-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; GFX90A-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; GFX90A: atomicrmw.end: +; GFX90A-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] +; GFX90A-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 +; GFX90A-NEXT: ret i16 [[EXTRACTED]] +; +; GFX1100-LABEL: define i16 @test_atomicrmw_xchg_i16_global_agent( +; GFX1100-SAME: ptr addrspace(1) [[PTR:%.*]], i16 [[VALUE:%.*]]) #[[ATTR0:[0-9]+]] { +; GFX1100-NEXT: [[ALIGNEDADDR:%.*]] = call ptr addrspace(1) @llvm.ptrmask.p1.i64(ptr addrspace(1) [[PTR]], i64 -4) +; GFX1100-NEXT: [[TMP1:%.*]] = ptrtoint ptr addrspace(1) [[PTR]] to i64 +; GFX1100-NEXT: [[PTRLSB:%.*]] = and i64 [[TMP1]], 3 +; GFX1100-NEXT: [[TMP2:%.*]] = shl i64 [[PTRLSB]], 3 +; GFX1100-NEXT: [[SHIFTAMT:%.*]] = trunc i64 [[TMP2]] to i32 +; GFX1100-NEXT: [[MASK:%.*]] = shl i32 65535, [[SHIFTAMT]] +; GFX1100-NEXT: [[INV_MASK:%.*]] = xor i32 [[MASK]], -1 +; GFX1100-NEXT: [[TMP3:%.*]] = zext i16 [[VALUE]] to i32 +; GFX1100-NEXT: [[VALOPERAND_SHIFTED:%.*]] = shl i32 [[TMP3]], [[SHIFTAMT]] +; GFX1100-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[ALIGNEDADDR]], align 4, !mmra [[META0:![0-9]+]] +; GFX1100-NEXT: br label [[ATOMICRMW_START:%.*]] +; GFX1100: atomicrmw.start: +; GFX1100-NEXT: [[LOADED:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[NEWLOADED:%.*]], [[ATOMICRMW_START]] ] +; GFX1100-NEXT: [[TMP5:%.*]] = and i32 [[LOADED]], [[INV_MASK]] +; GFX1100-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[VALOPERAND_SHIFTED]] +; GFX1100-NEXT: [[TMP7:%.*]] = cmpxchg ptr addrspace(1) [[ALIGNEDADDR]], i32 [[LOADED]], i32 [[TMP6]] syncscope("agent") seq_cst seq_cst, align 4, !mmra [[META0]] +; GFX1100-NEXT: [[SUCCESS:%.*]] = extractvalue { i32, i1 } [[TMP7]], 1 +; GFX1100-NEXT: [[NEWLOADED]] = extractvalue { i32, i1 } [[TMP7]], 0 +; GFX1100-NEXT: br i1 [[SUCCESS]], label [[ATOMICRMW_END:%.*]], label [[ATOMICRMW_START]] +; GFX1100: atomicrmw.end: +; GFX1100-NEXT: [[SHIFTED:%.*]] = lshr i32 [[NEWLOADED]], [[SHIFTAMT]] +; GFX1100-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[SHIFTED]] to i16 +; GFX1100-NEXT: ret i16 [[EXTRACTED]] +; + %res = atomicrmw xchg ptr addrspace(1) %ptr, i16 %value syncscope("agent") seq_cst, !mmra !2 + ret i16 %res +} + +define i16 @test_cmpxchg_i16_global_agent_align4(ptr addrspace(1) %out, i16 %in, i16 %old) { +; GFX90A-LABEL: define i16 @test_cmpxchg_i16_global_agent_align4( +; GFX90A-SAME: ptr addrspace(1) [[OUT:%.*]], i16 [[IN:%.*]], i16 [[OLD:%.*]]) #[[ATTR0]] { +; GFX90A-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT]], i64 4 +; GFX90A-NEXT: [[TMP1:%.*]] = zext i16 [[IN]] to i32 +; GFX90A-NEXT: [[TMP2:%.*]] = zext i16 [[OLD]] to i32 +; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !mmra [[META0]] +; GFX90A-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], -65536 +; GFX90A-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] +; GFX90A: partword.cmpxchg.loop: +; GFX90A-NEXT: [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[TMP11:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] +; GFX90A-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP1]] +; GFX90A-NEXT: [[TMP7:%.*]] = or i32 [[TMP5]], [[TMP2]] +; GFX90A-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[GEP]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4, !mmra [[META0]] +; GFX90A-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0 +; GFX90A-NEXT: [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 +; GFX90A-NEXT: br i1 [[TMP10]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] +; GFX90A: partword.cmpxchg.failure: +; GFX90A-NEXT: [[TMP11]] = and i32 [[TMP9]], -65536 +; GFX90A-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP5]], [[TMP11]] +; GFX90A-NEXT: br i1 [[TMP12]], label [[PARTWORD_CMPXCHG_LOOP]], label [[PARTWORD_CMPXCHG_END]] +; GFX90A: partword.cmpxchg.end: +; GFX90A-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP9]] to i16 +; GFX90A-NEXT: [[TMP13:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 +; GFX90A-NEXT: [[TMP14:%.*]] = insertvalue { i16, i1 } [[TMP13]], i1 [[TMP10]], 1 +; GFX90A-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP14]], 0 +; GFX90A-NEXT: ret i16 [[EXTRACT]] +; +; GFX1100-LABEL: define i16 @test_cmpxchg_i16_global_agent_align4( +; GFX1100-SAME: ptr addrspace(1) [[OUT:%.*]], i16 [[IN:%.*]], i16 [[OLD:%.*]]) #[[ATTR0]] { +; GFX1100-NEXT: [[GEP:%.*]] = getelementptr i16, ptr addrspace(1) [[OUT]], i64 4 +; GFX1100-NEXT: [[TMP1:%.*]] = zext i16 [[IN]] to i32 +; GFX1100-NEXT: [[TMP2:%.*]] = zext i16 [[OLD]] to i32 +; GFX1100-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(1) [[GEP]], align 4, !mmra [[META0]] +; GFX1100-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], -65536 +; GFX1100-NEXT: br label [[PARTWORD_CMPXCHG_LOOP:%.*]] +; GFX1100: partword.cmpxchg.loop: +; GFX1100-NEXT: [[TMP5:%.*]] = phi i32 [ [[TMP4]], [[TMP0:%.*]] ], [ [[TMP11:%.*]], [[PARTWORD_CMPXCHG_FAILURE:%.*]] ] +; GFX1100-NEXT: [[TMP6:%.*]] = or i32 [[TMP5]], [[TMP1]] +; GFX1100-NEXT: [[TMP7:%.*]] = or i32 [[TMP5]], [[TMP2]] +; GFX1100-NEXT: [[TMP8:%.*]] = cmpxchg ptr addrspace(1) [[GEP]], i32 [[TMP7]], i32 [[TMP6]] seq_cst seq_cst, align 4, !mmra [[META0]] +; GFX1100-NEXT: [[TMP9:%.*]] = extractvalue { i32, i1 } [[TMP8]], 0 +; GFX1100-NEXT: [[TMP10:%.*]] = extractvalue { i32, i1 } [[TMP8]], 1 +; GFX1100-NEXT: br i1 [[TMP10]], label [[PARTWORD_CMPXCHG_END:%.*]], label [[PARTWORD_CMPXCHG_FAILURE]] +; GFX1100: partword.cmpxchg.failure: +; GFX1100-NEXT: [[TMP11]] = and i32 [[TMP9]], -65536 +; GFX1100-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP5]], [[TMP11]] +; GFX1100-NEXT: br i1 [[TMP12]], label [[PARTWORD_CMPXCHG_LOOP]], label [[PARTWORD_CMPXCHG_END]] +; GFX1100: partword.cmpxchg.end: +; GFX1100-NEXT: [[EXTRACTED:%.*]] = trunc i32 [[TMP9]] to i16 +; GFX1100-NEXT: [[TMP13:%.*]] = insertvalue { i16, i1 } poison, i16 [[EXTRACTED]], 0 +; GFX1100-NEXT: [[TMP14:%.*]] = insertvalue { i16, i1 } [[TMP13]], i1 [[TMP10]], 1 +; GFX1100-NEXT: [[EXTRACT:%.*]] = extractvalue { i16, i1 } [[TMP14]], 0 +; GFX1100-NEXT: ret i16 [[EXTRACT]] +; + %gep = getelementptr i16, ptr addrspace(1) %out, i64 4 + %res = cmpxchg ptr addrspace(1) %gep, i16 %old, i16 %in seq_cst seq_cst, align 4, !mmra !2 + %extract = extractvalue {i16, i1} %res, 0 + ret i16 %extract +} + +define void @syncscope_workgroup_nortn(ptr %addr, float %val) #0 { +; GFX90A-LABEL: define void @syncscope_workgroup_nortn( +; GFX90A-SAME: ptr [[ADDR:%.*]], float [[VAL:%.*]]) #[[ATTR1:[0-9]+]] { +; GFX90A-NEXT: br label [[ATOMICRMW_CHECK_SHARED:%.*]] +; GFX90A: atomicrmw.check.shared: +; GFX90A-NEXT: [[IS_SHARED:%.*]] = call i1 @llvm.amdgcn.is.shared(ptr [[ADDR]]) +; GFX90A-NEXT: br i1 [[IS_SHARED]], label [[ATOMICRMW_SHARED:%.*]], label [[ATOMICRMW_CHECK_PRIVATE:%.*]] +; GFX90A: atomicrmw.shared: +; GFX90A-NEXT: [[TMP1:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(3) +; GFX90A-NEXT: [[TMP2:%.*]] = atomicrmw fadd ptr addrspace(3) [[TMP1]], float [[VAL]] syncscope("workgroup") seq_cst, align 4, !mmra [[META0]] +; GFX90A-NEXT: br label [[ATOMICRMW_PHI:%.*]] +; GFX90A: atomicrmw.check.private: +; GFX90A-NEXT: [[IS_PRIVATE:%.*]] = call i1 @llvm.amdgcn.is.private(ptr [[ADDR]]) +; GFX90A-NEXT: br i1 [[IS_PRIVATE]], label [[ATOMICRMW_PRIVATE:%.*]], label [[ATOMICRMW_GLOBAL:%.*]] +; GFX90A: atomicrmw.private: +; GFX90A-NEXT: [[TMP3:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(5) +; GFX90A-NEXT: [[LOADED_PRIVATE:%.*]] = load float, ptr addrspace(5) [[TMP3]], align 4 +; GFX90A-NEXT: [[VAL_NEW:%.*]] = fadd float [[LOADED_PRIVATE]], [[VAL]] +; GFX90A-NEXT: store float [[VAL_NEW]], ptr addrspace(5) [[TMP3]], align 4 +; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] +; GFX90A: atomicrmw.global: +; GFX90A-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[ADDR]] to ptr addrspace(1) +; GFX90A-NEXT: [[TMP5:%.*]] = atomicrmw fadd ptr addrspace(1) [[TMP4]], float [[VAL]] syncscope("workgroup") seq_cst, align 4, !mmra [[META0]] +; GFX90A-NEXT: br label [[ATOMICRMW_PHI]] +; GFX90A: atomicrmw.phi: +; GFX90A-NEXT: [[LOADED_PHI:%.*]] = phi float [ [[TMP2]], [[ATOMICRMW_SHARED]] ], [ [[LOADED_PRIVATE]], [[ATOMICRMW_PRIVATE]] ], [ [[TMP5]], [[ATOMICRMW_GLOBAL]] ] +; GFX90A-NEXT: br label [[ATOMICRMW_END:%.*]] +; GFX90A: atomicrmw.end: +; GFX90A-NEXT: ret void +; +; GFX1100-LABEL: define void @syncscope_workgroup_nortn( +; GFX1100-SAME: ptr [[ADDR:%.*]], float [[VAL:%.*]]) #[[ATTR1:[0-9]+]] { +; GFX1100-NEXT: [[RES:%.*]] = atomicrmw fadd ptr [[ADDR]], float [[VAL]] syncscope("workgroup") seq_cst, align 4, !mmra [[META0]] +; GFX1100-NEXT: ret void +; + %res = atomicrmw fadd ptr %addr, float %val syncscope("workgroup") seq_cst, !mmra !2 + ret void +} + +define i32 @atomic_load_global_align1(ptr addrspace(1) %ptr) { +; GFX90A-LABEL: define i32 @atomic_load_global_align1( +; GFX90A-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] { +; GFX90A-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; GFX90A-NEXT: [[TMP2:%.*]] = alloca i32, align 4, addrspace(5) +; GFX90A-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; GFX90A-NEXT: call void @__atomic_load(i64 4, ptr [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5) +; GFX90A-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(5) [[TMP2]], align 4 +; GFX90A-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; GFX90A-NEXT: ret i32 [[TMP3]] +; +; GFX1100-LABEL: define i32 @atomic_load_global_align1( +; GFX1100-SAME: ptr addrspace(1) [[PTR:%.*]]) #[[ATTR0]] { +; GFX1100-NEXT: [[TMP1:%.*]] = addrspacecast ptr addrspace(1) [[PTR]] to ptr +; GFX1100-NEXT: [[TMP2:%.*]] = alloca i32, align 4, addrspace(5) +; GFX1100-NEXT: call void @llvm.lifetime.start.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; GFX1100-NEXT: call void @__atomic_load(i64 4, ptr [[TMP1]], ptr addrspace(5) [[TMP2]], i32 5) +; GFX1100-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(5) [[TMP2]], align 4 +; GFX1100-NEXT: call void @llvm.lifetime.end.p5(i64 4, ptr addrspace(5) [[TMP2]]) +; GFX1100-NEXT: ret i32 [[TMP3]] +; + %val = load atomic i32, ptr addrspace(1) %ptr seq_cst, align 1, !mmra !2 + ret i32 %val +} + +attributes #0 = { "amdgpu-unsafe-fp-atomics"="true" } + +!0 = !{!"foo", !"bar"} +!1 = !{!"bux", !"baz"} +!2 = !{!0, !1} +;. +; GFX90A: [[META0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]]} +; GFX90A: [[META1]] = !{!"foo", !"bar"} +; GFX90A: [[META2]] = !{!"bux", !"baz"} +;. +; GFX1100: [[META0]] = !{[[META1:![0-9]+]], [[META2:![0-9]+]]} +; GFX1100: [[META1]] = !{!"foo", !"bar"} +; GFX1100: [[META2]] = !{!"bux", !"baz"} +;. diff --git a/llvm/test/Transforms/GVN/condprop.ll b/llvm/test/Transforms/GVN/condprop.ll index 6b1e4d10601099b8b9dbbce969eb9499d0e3664b..6402a23157729cecae151b9b9994b942cbf37e28 100644 --- a/llvm/test/Transforms/GVN/condprop.ll +++ b/llvm/test/Transforms/GVN/condprop.ll @@ -214,11 +214,11 @@ define void @test4(i1 %b, i32 %x) { ; CHECK-NEXT: br i1 [[B:%.*]], label [[SW:%.*]], label [[CASE3:%.*]] ; CHECK: sw: ; CHECK-NEXT: switch i32 [[X:%.*]], label [[DEFAULT:%.*]] [ -; CHECK-NEXT: i32 0, label [[CASE0:%.*]] -; CHECK-NEXT: i32 1, label [[CASE1:%.*]] -; CHECK-NEXT: i32 2, label [[CASE0]] -; CHECK-NEXT: i32 3, label [[CASE3]] -; CHECK-NEXT: i32 4, label [[DEFAULT]] +; CHECK-NEXT: i32 0, label [[CASE0:%.*]] +; CHECK-NEXT: i32 1, label [[CASE1:%.*]] +; CHECK-NEXT: i32 2, label [[CASE0]] +; CHECK-NEXT: i32 3, label [[CASE3]] +; CHECK-NEXT: i32 4, label [[DEFAULT]] ; CHECK-NEXT: ] ; CHECK: default: ; CHECK-NEXT: call void @bar(i32 [[X]]) @@ -521,15 +521,16 @@ define i32 @test13(ptr %ptr1, ptr %ptr2) { ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr i32, ptr [[PTR2:%.*]], i32 1 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr i32, ptr [[PTR2]], i32 2 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq ptr [[PTR1:%.*]], [[PTR2]] -; CHECK-NEXT: [[VAL2_PRE:%.*]] = load i32, ptr [[GEP2]], align 4 ; CHECK-NEXT: br i1 [[CMP]], label [[IF:%.*]], label [[END:%.*]] ; CHECK: if: +; CHECK-NEXT: [[VAL1:%.*]] = load i32, ptr [[GEP2]], align 4 ; CHECK-NEXT: br label [[END]] ; CHECK: end: -; CHECK-NEXT: [[PHI1:%.*]] = phi ptr [ [[PTR2]], [[IF]] ], [ [[GEP1]], [[ENTRY:%.*]] ] -; CHECK-NEXT: [[PHI2:%.*]] = phi i32 [ [[VAL2_PRE]], [[IF]] ], [ 0, [[ENTRY]] ] +; CHECK-NEXT: [[PHI1:%.*]] = phi ptr [ [[PTR1]], [[IF]] ], [ [[GEP1]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[PHI2:%.*]] = phi i32 [ [[VAL1]], [[IF]] ], [ 0, [[ENTRY]] ] ; CHECK-NEXT: store i32 0, ptr [[PHI1]], align 4 -; CHECK-NEXT: [[RET:%.*]] = add i32 [[PHI2]], [[VAL2_PRE]] +; CHECK-NEXT: [[VAL2:%.*]] = load i32, ptr [[GEP2]], align 4 +; CHECK-NEXT: [[RET:%.*]] = add i32 [[PHI2]], [[VAL2]] ; CHECK-NEXT: ret i32 [[RET]] ; entry: @@ -552,14 +553,14 @@ end: ret i32 %ret } -define void @test14(ptr %ptr1, ptr noalias %ptr2) { +define void @test14(ptr %ptr1, ptr noalias %ptr2, i1 %b1, i1 %b2) { ; CHECK-LABEL: @test14( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds i32, ptr [[PTR1:%.*]], i32 1 ; CHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds i32, ptr [[PTR1]], i32 2 ; CHECK-NEXT: br label [[LOOP:%.*]] ; CHECK: loop: -; CHECK-NEXT: br i1 undef, label [[LOOP_IF1_CRIT_EDGE:%.*]], label [[THEN:%.*]] +; CHECK-NEXT: br i1 [[B1:%.*]], label [[LOOP_IF1_CRIT_EDGE:%.*]], label [[THEN:%.*]] ; CHECK: loop.if1_crit_edge: ; CHECK-NEXT: [[VAL2_PRE:%.*]] = load i32, ptr [[GEP2]], align 4 ; CHECK-NEXT: br label [[IF1:%.*]] @@ -574,10 +575,10 @@ define void @test14(ptr %ptr1, ptr noalias %ptr2) { ; CHECK: if2: ; CHECK-NEXT: br label [[LOOP_END]] ; CHECK: loop.end: -; CHECK-NEXT: [[PHI3:%.*]] = phi ptr [ [[PTR2]], [[THEN]] ], [ [[PTR1]], [[IF2]] ] +; CHECK-NEXT: [[PHI3:%.*]] = phi ptr [ [[GEP2]], [[THEN]] ], [ [[PTR1]], [[IF2]] ] ; CHECK-NEXT: [[VAL3]] = load i32, ptr [[GEP2]], align 4 ; CHECK-NEXT: store i32 [[VAL3]], ptr [[PHI3]], align 4 -; CHECK-NEXT: br i1 undef, label [[LOOP]], label [[IF1]] +; CHECK-NEXT: br i1 [[B2:%.*]], label [[LOOP]], label [[IF1]] ; entry: %gep1 = getelementptr inbounds i32, ptr %ptr1, i32 1 @@ -586,7 +587,7 @@ entry: loop: %phi1 = phi ptr [ %gep3, %loop.end ], [ %gep1, %entry ] - br i1 undef, label %if1, label %then + br i1 %b1, label %if1, label %then if1: @@ -607,5 +608,201 @@ loop.end: %val3 = load i32, ptr %gep2, align 4 store i32 %val3, ptr %phi3, align 4 %gep3 = getelementptr inbounds i32, ptr %ptr1, i32 1 - br i1 undef, label %loop, label %if1 + br i1 %b2, label %loop, label %if1 +} + +; Make sure that the call to use_ptr does not have %p1 +define void @single_phi1(ptr %p0, ptr %p1, i8 %s) { +; CHECK-LABEL: @single_phi1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr [[P0:%.*]], align 8 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[P2]], [[P1:%.*]] +; CHECK-NEXT: br i1 [[CMP1]], label [[BB4:%.*]], label [[BB1:%.*]] +; CHECK: bb1: +; CHECK-NEXT: switch i8 [[S:%.*]], label [[BB2:%.*]] [ +; CHECK-NEXT: i8 0, label [[BB1]] +; CHECK-NEXT: i8 1, label [[BB3:%.*]] +; CHECK-NEXT: ] +; CHECK: bb2: +; CHECK-NEXT: unreachable +; CHECK: bb3: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb4: +; CHECK-NEXT: call void @use_bool(i1 [[CMP1]]) +; CHECK-NEXT: call void @use_ptr(ptr [[P2]]) +; CHECK-NEXT: ret void +; +entry: + %p2 = load ptr, ptr %p0, align 8 + %cmp1 = icmp eq ptr %p2, %p1 + br i1 %cmp1, label %bb4, label %bb1 + +bb1: + switch i8 %s, label %bb2 [ + i8 0, label %bb1 + i8 1, label %bb3 + ] + +bb2: + unreachable + +bb3: + br label %bb4 + +bb4: + %phi1 = phi ptr [ %p2, %entry ], [ %p2, %bb3 ] + %cmp2 = icmp eq ptr %phi1, %p1 + call void @use_bool(i1 %cmp2) + call void @use_ptr(ptr %phi1) + ret void +} + +define void @single_phi2(ptr %p0, ptr %p1, i8 %s) { +; CHECK-LABEL: @single_phi2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr [[P0:%.*]], align 8 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[P2]], [[P1:%.*]] +; CHECK-NEXT: br i1 [[CMP1]], label [[BB4:%.*]], label [[BB1:%.*]] +; CHECK: bb1: +; CHECK-NEXT: switch i8 [[S:%.*]], label [[BB2:%.*]] [ +; CHECK-NEXT: i8 0, label [[BB1]] +; CHECK-NEXT: i8 1, label [[BB3:%.*]] +; CHECK-NEXT: ] +; CHECK: bb2: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb3: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb4: +; CHECK-NEXT: call void @use_bool(i1 [[CMP1]]) +; CHECK-NEXT: call void @use_ptr(ptr [[P2]]) +; CHECK-NEXT: ret void +; +entry: + %p2 = load ptr, ptr %p0, align 8 + %cmp1 = icmp eq ptr %p2, %p1 + br i1 %cmp1, label %bb4, label %bb1 + +bb1: + switch i8 %s, label %bb2 [ + i8 0, label %bb1 + i8 1, label %bb3 + ] + +bb2: + br label %bb4 + +bb3: + br label %bb4 + +bb4: + %phi1 = phi ptr [ %p2, %entry ], [ %p2, %bb2 ], [ %p2, %bb3 ] + %cmp2 = icmp eq ptr %phi1, %p1 + call void @use_bool(i1 %cmp2) + call void @use_ptr(ptr %phi1) + ret void } + +define void @multiple_phi1(ptr %p0, ptr %p1, i8 %s) { +; CHECK-LABEL: @multiple_phi1( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr [[P0:%.*]], align 8 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[P2]], [[P1:%.*]] +; CHECK-NEXT: br i1 [[CMP1]], label [[BB4:%.*]], label [[BB1:%.*]] +; CHECK: bb1: +; CHECK-NEXT: switch i8 [[S:%.*]], label [[BB2:%.*]] [ +; CHECK-NEXT: i8 0, label [[BB1]] +; CHECK-NEXT: i8 1, label [[BB3:%.*]] +; CHECK-NEXT: ] +; CHECK: bb2: +; CHECK-NEXT: unreachable +; CHECK: bb3: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb4: +; CHECK-NEXT: call void @use_bool(i1 [[CMP1]]) +; CHECK-NEXT: br label [[BB5:%.*]] +; CHECK: bb5: +; CHECK-NEXT: call void @use_ptr(ptr [[P2]]) +; CHECK-NEXT: br label [[BB5]] +; +entry: + %p2 = load ptr, ptr %p0, align 8 + %cmp1 = icmp eq ptr %p2, %p1 + br i1 %cmp1, label %bb4, label %bb1 + +bb1: + switch i8 %s, label %bb2 [ + i8 0, label %bb1 + i8 1, label %bb3 + ] + +bb2: + unreachable + +bb3: + br label %bb4 + +bb4: + %phi1 = phi ptr [ %p2, %entry ], [ poison, %bb3 ] + %cmp2 = icmp eq ptr %phi1, %p1 + call void @use_bool(i1 %cmp2) + br label %bb5 + +bb5: + %phi2 = phi ptr [ poison, %bb5 ], [ %phi1, %bb4 ] + call void @use_ptr(ptr %phi2) + br label %bb5 +} + +define void @multiple_phi2(ptr %p0, ptr %p1, i8 %s) { +; CHECK-LABEL: @multiple_phi2( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr [[P0:%.*]], align 8 +; CHECK-NEXT: [[CMP1:%.*]] = icmp eq ptr [[P2]], [[P1:%.*]] +; CHECK-NEXT: br i1 [[CMP1]], label [[BB4:%.*]], label [[BB1:%.*]] +; CHECK: bb1: +; CHECK-NEXT: switch i8 [[S:%.*]], label [[BB2:%.*]] [ +; CHECK-NEXT: i8 0, label [[BB1]] +; CHECK-NEXT: i8 1, label [[BB3:%.*]] +; CHECK-NEXT: ] +; CHECK: bb2: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb3: +; CHECK-NEXT: br label [[BB4]] +; CHECK: bb4: +; CHECK-NEXT: call void @use_bool(i1 [[CMP1]]) +; CHECK-NEXT: br label [[BB5:%.*]] +; CHECK: bb5: +; CHECK-NEXT: call void @use_ptr(ptr [[P2]]) +; CHECK-NEXT: br label [[BB5]] +; +entry: + %p2 = load ptr, ptr %p0, align 8 + %cmp1 = icmp eq ptr %p2, %p1 + br i1 %cmp1, label %bb4, label %bb1 + +bb1: + switch i8 %s, label %bb2 [ + i8 0, label %bb1 + i8 1, label %bb3 + ] + +bb2: + br label %bb4 + +bb3: + br label %bb4 + +bb4: + %phi1 = phi ptr [ %p2, %entry ], [ %p2, %bb2 ], [ poison, %bb3 ] + %cmp2 = icmp eq ptr %phi1, %p1 + call void @use_bool(i1 %cmp2) + br label %bb5 + +bb5: + %phi2 = phi ptr [ poison, %bb5 ], [ %phi1, %bb4 ] + call void @use_ptr(ptr %phi2) + br label %bb5 +} + +declare void @use_bool(i1) +declare void @use_ptr(ptr) diff --git a/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll b/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll new file mode 100644 index 0000000000000000000000000000000000000000..4a9c576f02719e789360361dcfeef201d815f516 --- /dev/null +++ b/llvm/test/Transforms/Inline/inline-deferred-instsimplify.ll @@ -0,0 +1,76 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -passes=inline -S | FileCheck %s +; RUN: opt < %s -passes='cgscc(inline)' -S | FileCheck %s + +%struct.a = type { i32, i32, i32, i32, i32 } + +@g_var = global %struct.a { i32 1, i32 0, i32 0, i32 0, i32 0 }, align 8 +@other_g_var = global %struct.a zeroinitializer, align 4 + +define void @callee(ptr noundef byval(%struct.a) align 8 %ptr) { +; CHECK-LABEL: define void @callee( +; CHECK-SAME: ptr noundef byval([[STRUCT_A:%.*]]) align 8 [[PTR:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[VAL:%.*]] = load i32, ptr [[PTR]], align 8 +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp eq i32 [[VAL]], 0 +; CHECK-NEXT: br i1 [[DOTNOT]], label [[CHECK_POINTERS_ARE_EQUAL:%.*]], label [[STORE_PTR_IN_GVAR:%.*]] +; CHECK: store_ptr_in_gvar: +; CHECK-NEXT: store ptr [[PTR]], ptr @other_g_var, align 8 +; CHECK-NEXT: br label [[CHECK_POINTERS_ARE_EQUAL]] +; CHECK: check_pointers_are_equal: +; CHECK-NEXT: [[PHI:%.*]] = phi ptr [ [[PTR]], [[STORE_PTR_IN_GVAR]] ], [ @other_g_var, [[ENTRY:%.*]] ] +; CHECK-NEXT: [[DOTNOT1:%.*]] = icmp eq ptr [[PHI]], [[PTR]] +; CHECK-NEXT: br i1 [[DOTNOT1]], label [[RETURN:%.*]], label [[ABORT:%.*]] +; CHECK: abort: +; CHECK-NEXT: call void @abort() +; CHECK-NEXT: unreachable +; CHECK: return: +; CHECK-NEXT: ret void +; +entry: + %val = load i32, ptr %ptr, align 8 + %.not = icmp eq i32 %val, 0 + br i1 %.not, label %check_pointers_are_equal, label %store_ptr_in_gvar + +store_ptr_in_gvar: ; preds = %entry + store ptr %ptr, ptr @other_g_var, align 8 + br label %check_pointers_are_equal + +check_pointers_are_equal: ; preds = %store_ptr_in_gvar, %entry + %phi = phi ptr [ %ptr, %store_ptr_in_gvar ], [ @other_g_var, %entry ] +; FIXME: While inlining, the following is miscompiled to i1 false, +; as %ptr in the phi-node is not taken into account. + %.not1 = icmp eq ptr %phi, %ptr + br i1 %.not1, label %return, label %abort + +abort: ; preds = %check_pointers_are_equal + call void @abort() + unreachable + +return: ; preds = %check_pointers_are_equal + ret void +} + +define i32 @main() { +; CHECK-LABEL: define i32 @main() { +; CHECK-NEXT: [[G_VAR:%.*]] = alloca [[STRUCT_A:%.*]], align 8 +; CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 20, ptr [[G_VAR]]) +; CHECK-NEXT: call void @llvm.memcpy.p0.p0.i64(ptr align 1 [[G_VAR]], ptr align 1 @g_var, i64 20, i1 false) +; CHECK-NEXT: [[VAL_I:%.*]] = load i32, ptr [[G_VAR]], align 8 +; CHECK-NEXT: [[DOTNOT_I:%.*]] = icmp eq i32 [[VAL_I]], 0 +; CHECK-NEXT: br i1 [[DOTNOT_I]], label [[CHECK_POINTERS_ARE_EQUAL_I:%.*]], label [[STORE_PTR_IN_GVAR_I:%.*]] +; CHECK: store_ptr_in_gvar.i: +; CHECK-NEXT: store ptr [[G_VAR]], ptr @other_g_var, align 8 +; CHECK-NEXT: br label [[CHECK_POINTERS_ARE_EQUAL_I]] +; CHECK: check_pointers_are_equal.i: +; CHECK-NEXT: [[PHI_I:%.*]] = phi ptr [ [[G_VAR]], [[STORE_PTR_IN_GVAR_I]] ], [ @other_g_var, [[TMP0:%.*]] ] +; CHECK-NEXT: call void @abort() +; CHECK-NEXT: unreachable +; CHECK: callee.exit: +; CHECK-NEXT: ret i32 0 +; + call void @callee(ptr noundef byval(%struct.a) align 8 @g_var) + ret i32 0 +} + +declare void @abort() diff --git a/llvm/test/Transforms/InstCombine/add4.ll b/llvm/test/Transforms/InstCombine/add4.ll index 7fc164c8b9a7c99b2ae5a2e68024cf1812f39db0..77f7fc7b35cd44a4e6d751b7a31d0e4138d4ec33 100644 --- a/llvm/test/Transforms/InstCombine/add4.ll +++ b/llvm/test/Transforms/InstCombine/add4.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; RUN: opt < %s -passes=instcombine -S | FileCheck %s +declare void @use(i32) + define i64 @match_unsigned(i64 %x) { ; CHECK-LABEL: @match_unsigned( ; CHECK-NEXT: [[UREM:%.*]] = urem i64 [[X:%.*]], 19136 @@ -127,3 +129,163 @@ define i32 @not_match_overflow(i32 %x) { %t4 = add i32 %t, %t3 ret i32 %t4 } + +; Tests from PR76128. +define i32 @fold_add_udiv_urem(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_urem( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = mul nuw i32 [[DIV]], 6 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[VAL]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 10 + %shl = shl i32 %div, 4 + %rem = urem i32 %val, 10 + %add = add i32 %shl, %rem + ret i32 %add +} +define i32 @fold_add_sdiv_srem(i32 noundef %val) { +; CHECK-LABEL: @fold_add_sdiv_srem( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = mul nsw i32 [[DIV]], 6 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[VAL]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = sdiv i32 %val, 10 + %shl = shl i32 %div, 4 + %rem = srem i32 %val, 10 + %add = add i32 %shl, %rem + ret i32 %add +} +define i32 @fold_add_udiv_urem_to_mul(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_urem_to_mul( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[ADD:%.*]] = mul i32 [[VAL:%.*]], 3 +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 7 + %mul1 = mul i32 %div, 21 + %rem = urem i32 %val, 7 + %mul2 = mul i32 %rem, 3 + %add = add i32 %mul1, %mul2 + ret i32 %add +} +define i32 @fold_add_udiv_urem_to_mul_multiuse(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_urem_to_mul_multiuse( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[REM:%.*]] = urem i32 [[VAL:%.*]], 7 +; CHECK-NEXT: call void @use(i32 [[REM]]) +; CHECK-NEXT: [[ADD:%.*]] = mul i32 [[VAL]], 3 +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 7 + %mul1 = mul i32 %div, 21 + %rem = urem i32 %val, 7 + call void @use(i32 %rem) + %mul2 = mul i32 %rem, 3 + %add = add i32 %mul1, %mul2 + ret i32 %add +} +define i32 @fold_add_udiv_urem_commuted(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_urem_commuted( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = mul nuw i32 [[DIV]], 6 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[VAL]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 10 + %shl = shl i32 %div, 4 + %rem = urem i32 %val, 10 + %add = add i32 %rem, %shl + ret i32 %add +} +define i32 @fold_add_udiv_urem_or_disjoint(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_urem_or_disjoint( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = mul nuw i32 [[DIV]], 6 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[TMP0]], [[VAL]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 10 + %shl = shl i32 %div, 4 + %rem = urem i32 %val, 10 + %add = or disjoint i32 %shl, %rem + ret i32 %add +} +; Negative tests +define i32 @fold_add_udiv_urem_without_noundef(i32 %val) { +; CHECK-LABEL: @fold_add_udiv_urem_without_noundef( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[DIV]], 4 +; CHECK-NEXT: [[REM:%.*]] = urem i32 [[VAL]], 10 +; CHECK-NEXT: [[ADD:%.*]] = or disjoint i32 [[SHL]], [[REM]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 10 + %shl = shl i32 %div, 4 + %rem = urem i32 %val, 10 + %add = add i32 %shl, %rem + ret i32 %add +} +define i32 @fold_add_udiv_urem_multiuse_mul(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_urem_multiuse_mul( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[DIV]], 4 +; CHECK-NEXT: call void @use(i32 [[SHL]]) +; CHECK-NEXT: [[REM:%.*]] = urem i32 [[VAL]], 10 +; CHECK-NEXT: [[ADD:%.*]] = or disjoint i32 [[SHL]], [[REM]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 10 + %shl = shl i32 %div, 4 + call void @use(i32 %shl) + %rem = urem i32 %val, 10 + %add = add i32 %shl, %rem + ret i32 %add +} +define i32 @fold_add_udiv_srem(i32 noundef %val) { +; CHECK-LABEL: @fold_add_udiv_srem( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], 10 +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[DIV]], 4 +; CHECK-NEXT: [[REM:%.*]] = srem i32 [[VAL]], 10 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[REM]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, 10 + %shl = shl i32 %div, 4 + %rem = srem i32 %val, 10 + %add = add i32 %shl, %rem + ret i32 %add +} +define i32 @fold_add_udiv_urem_non_constant(i32 noundef %val, i32 noundef %c) { +; CHECK-LABEL: @fold_add_udiv_urem_non_constant( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[DIV:%.*]] = udiv i32 [[VAL:%.*]], [[C:%.*]] +; CHECK-NEXT: [[SHL:%.*]] = shl i32 [[DIV]], 4 +; CHECK-NEXT: [[REM:%.*]] = urem i32 [[VAL]], [[C]] +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[SHL]], [[REM]] +; CHECK-NEXT: ret i32 [[ADD]] +; +entry: + %div = udiv i32 %val, %c + %shl = shl i32 %div, 4 + %rem = urem i32 %val, %c + %add = add i32 %shl, %rem + ret i32 %add +} diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll b/llvm/test/Transforms/InstCombine/bit_ceil.ll index 52e70c78ba54289f212a04509449c6f3400958f0..16631afa4878da6b5a47e93c7255998825be38da 100644 --- a/llvm/test/Transforms/InstCombine/bit_ceil.ll +++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll @@ -5,7 +5,7 @@ define i32 @bit_ceil_32(i32 %x) { ; CHECK-LABEL: @bit_ceil_32( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP2]] @@ -24,7 +24,7 @@ define i32 @bit_ceil_32(i32 %x) { define i64 @bit_ceil_64(i64 %x) { ; CHECK-LABEL: @bit_ceil_64( ; CHECK-NEXT: [[DEC:%.*]] = add i64 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[DEC]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[DEC]], i1 false) ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i64 0, [[CTLZ]] ; CHECK-NEXT: [[TMP2:%.*]] = and i64 [[TMP1]], 63 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i64 1, [[TMP2]] @@ -44,7 +44,7 @@ define i32 @bit_ceil_32_minus_1(i32 %x) { ; CHECK-LABEL: @bit_ceil_32_minus_1( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[X:%.*]], -2 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false) ; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP1]] @@ -64,7 +64,7 @@ entry: ; std::bit_ceil(x + 1) define i32 @bit_ceil_32_plus_1(i32 %x) { ; CHECK-LABEL: @bit_ceil_32_plus_1( -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP2:%.*]] = and i32 [[TMP1]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP2]] @@ -84,7 +84,7 @@ define i32 @bit_ceil_plus_2(i32 %x) { ; CHECK-LABEL: @bit_ceil_plus_2( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SUB:%.*]] = add i32 [[X:%.*]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false) ; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP1]] @@ -105,7 +105,7 @@ define i32 @bit_ceil_32_neg(i32 %x) { ; CHECK-LABEL: @bit_ceil_32_neg( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false) ; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP1]] @@ -127,7 +127,7 @@ define i32 @bit_ceil_not(i32 %x) { ; CHECK-LABEL: @bit_ceil_not( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[SUB:%.*]] = sub i32 -2, [[X:%.*]] -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[SUB]], i1 false) ; CHECK-NEXT: [[TMP0:%.*]] = sub nsw i32 0, [[CTLZ]] ; CHECK-NEXT: [[TMP1:%.*]] = and i32 [[TMP0]], 31 ; CHECK-NEXT: [[SEL:%.*]] = shl nuw i32 1, [[TMP1]] @@ -147,7 +147,7 @@ entry: define i32 @bit_ceil_commuted_operands(i32 %x) { ; CHECK-LABEL: @bit_ceil_commuted_operands( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: ret i32 [[SHL]] @@ -165,7 +165,7 @@ define i32 @bit_ceil_commuted_operands(i32 %x) { define i32 @bit_ceil_wrong_select_constant(i32 %x) { ; CHECK-LABEL: @bit_ceil_wrong_select_constant( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[UGT_INV:%.*]] = icmp ult i32 [[X]], 2 @@ -185,7 +185,7 @@ define i32 @bit_ceil_wrong_select_constant(i32 %x) { define i32 @bit_ceil_32_wrong_cond(i32 %x) { ; CHECK-LABEL: @bit_ceil_32_wrong_cond( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[UGT:%.*]] = icmp ugt i32 [[X]], 2 @@ -205,7 +205,7 @@ define i32 @bit_ceil_32_wrong_cond(i32 %x) { define i32 @bit_ceil_wrong_sub_constant(i32 %x) { ; CHECK-LABEL: @bit_ceil_wrong_sub_constant( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 33, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[UGT:%.*]] = icmp ugt i32 [[X]], 1 @@ -225,7 +225,7 @@ define i32 @bit_ceil_wrong_sub_constant(i32 %x) { define i32 @bit_ceil_32_shl_used_twice(i32 %x, ptr %p) { ; CHECK-LABEL: @bit_ceil_32_shl_used_twice( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[UGT:%.*]] = icmp ugt i32 [[X]], 1 @@ -247,7 +247,7 @@ define i32 @bit_ceil_32_shl_used_twice(i32 %x, ptr %p) { define i32 @bit_ceil_32_sub_used_twice(i32 %x, ptr %p) { ; CHECK-LABEL: @bit_ceil_32_sub_used_twice( ; CHECK-NEXT: [[DEC:%.*]] = add i32 [[X:%.*]], -1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[DEC]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[UGT:%.*]] = icmp ugt i32 [[X]], 1 @@ -269,7 +269,7 @@ define i32 @bit_ceil_32_sub_used_twice(i32 %x, ptr %p) { define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) { ; CHECK-LABEL: @bit_ceil_v4i32( ; CHECK-NEXT: [[DEC:%.*]] = add <4 x i32> [[X:%.*]], -; CHECK-NEXT: [[CTLZ:%.*]] = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[DEC]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[DEC]], i1 false) ; CHECK-NEXT: [[TMP1:%.*]] = sub nsw <4 x i32> zeroinitializer, [[CTLZ]] ; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i32> [[TMP1]], ; CHECK-NEXT: [[SEL:%.*]] = shl nuw <4 x i32> , [[TMP2]] diff --git a/llvm/test/Transforms/InstCombine/bit_floor.ll b/llvm/test/Transforms/InstCombine/bit_floor.ll index 9daa8eee8969c0edca518db1fda4b68f069abd2a..bd8aabf4431c0a367cbf3e5c8ecb2c5f620f5105 100644 --- a/llvm/test/Transforms/InstCombine/bit_floor.ll +++ b/llvm/test/Transforms/InstCombine/bit_floor.ll @@ -5,7 +5,7 @@ define i32 @bit_floor_32(i32 %x) { ; CHECK-LABEL: @bit_floor_32( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i32 0, i32 [[SHL]] @@ -24,7 +24,7 @@ define i64 @bit_floor_64(i64 %x) { ; CHECK-LABEL: @bit_floor_64( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i64 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i64 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[LSHR]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i64 1, 65) i64 @llvm.ctlz.i64(i64 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i64 64, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i64 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i64 0, i64 [[SHL]] @@ -44,7 +44,7 @@ define i32 @bit_floor_commuted_operands(i32 %x) { ; CHECK-LABEL: @bit_floor_commuted_operands( ; CHECK-NEXT: [[NE0_NOT:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[NE0_NOT]], i32 0, i32 [[SHL]] @@ -64,7 +64,7 @@ define i32 @bit_floor_lshr_used_twice(i32 %x, ptr %p) { ; CHECK-LABEL: @bit_floor_lshr_used_twice( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i32 0, i32 [[SHL]] @@ -86,7 +86,7 @@ define i32 @bit_floor_ctlz_used_twice(i32 %x, ptr %p) { ; CHECK-LABEL: @bit_floor_ctlz_used_twice( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i32 0, i32 [[SHL]] @@ -108,7 +108,7 @@ define i32 @bit_floor_sub_used_twice(i32 %x, ptr %p) { ; CHECK-LABEL: @bit_floor_sub_used_twice( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i32 0, i32 [[SHL]] @@ -130,7 +130,7 @@ define i32 @bit_floor_shl_used_twice(i32 %x, ptr %p) { ; CHECK-LABEL: @bit_floor_shl_used_twice( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq i32 [[X:%.*]], 0 ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 [[X]], 1 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw i32 32, [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[EQ0]], i32 0, i32 [[SHL]] @@ -152,7 +152,7 @@ define <4 x i32> @bit_floor_v4i32(<4 x i32> %x) { ; CHECK-LABEL: @bit_floor_v4i32( ; CHECK-NEXT: [[EQ0:%.*]] = icmp eq <4 x i32> [[X:%.*]], zeroinitializer ; CHECK-NEXT: [[LSHR:%.*]] = lshr <4 x i32> [[X]], -; CHECK-NEXT: [[CTLZ:%.*]] = tail call <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[LSHR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 1, 33) <4 x i32> @llvm.ctlz.v4i32(<4 x i32> [[LSHR]], i1 false) ; CHECK-NEXT: [[SUB:%.*]] = sub nuw nsw <4 x i32> , [[CTLZ]] ; CHECK-NEXT: [[SHL:%.*]] = shl nuw <4 x i32> , [[SUB]] ; CHECK-NEXT: [[SEL:%.*]] = select <4 x i1> [[EQ0]], <4 x i32> zeroinitializer, <4 x i32> [[SHL]] diff --git a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll index 66cbb2636cbc2bc1d418076d370203dc3eaacaed..9a9f359fa80b4a2a6c32f0174e80dfe99f144290 100644 --- a/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll +++ b/llvm/test/Transforms/InstCombine/cmp-intrinsic.ll @@ -125,7 +125,7 @@ define <2 x i1> @ctlz_ne_other_v2i32(<2 x i32> %a) { define i1 @ctlz_eq_other_i32_multiuse(i32 %x, ptr %p) { ; CHECK-LABEL: @ctlz_eq_other_i32_multiuse( -; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: store i32 [[LZ]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[LZ]], 24 ; CHECK-NEXT: ret i1 [[CMP]] @@ -178,7 +178,7 @@ define i1 @ctlz_ugt_other_i32(i32 %x) { define i1 @ctlz_ugt_other_multiuse_i32(i32 %x, ptr %p) { ; CHECK-LABEL: @ctlz_ugt_other_multiuse_i32( -; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: store i32 [[LZ]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[X]], 32768 ; CHECK-NEXT: ret i1 [[CMP]] @@ -221,7 +221,7 @@ define <2 x i1> @ctlz_ult_other_v2i32(<2 x i32> %x) { define <2 x i1> @ctlz_ult_other_multiuse_v2i32(<2 x i32> %x, ptr %p) { ; CHECK-LABEL: @ctlz_ult_other_multiuse_v2i32( -; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false) ; CHECK-NEXT: store <2 x i32> [[LZ]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[X]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] @@ -338,7 +338,7 @@ define <2 x i1> @cttz_ne_other_v2i32(<2 x i32> %a) { define i1 @cttz_eq_other_i33_multiuse(i33 %x, ptr %p) { ; CHECK-LABEL: @cttz_eq_other_i33_multiuse( -; CHECK-NEXT: [[TZ:%.*]] = tail call i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i33 0, 34) i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 false) ; CHECK-NEXT: store i33 [[TZ]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i33 [[TZ]], 4 ; CHECK-NEXT: ret i1 [[CMP]] @@ -384,7 +384,7 @@ define i1 @cttz_ugt_other_i33(i33 %x) { define i1 @cttz_ugt_other_multiuse_i33(i33 %x, ptr %p) { ; CHECK-LABEL: @cttz_ugt_other_multiuse_i33( -; CHECK-NEXT: [[TZ:%.*]] = tail call i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i33 0, 34) i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 false) ; CHECK-NEXT: store i33 [[TZ]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i33 [[TZ]], 16 ; CHECK-NEXT: ret i1 [[CMP]] @@ -428,7 +428,7 @@ define <2 x i1> @cttz_ult_other_v2i32(<2 x i32> %x) { define <2 x i1> @cttz_ult_other_multiuse_v2i32(<2 x i32> %x, ptr %p) { ; CHECK-LABEL: @cttz_ult_other_multiuse_v2i32( -; CHECK-NEXT: [[TZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false) ; CHECK-NEXT: store <2 x i32> [[TZ]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[TZ]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] @@ -502,7 +502,7 @@ define <2 x i1> @ctpop_ne_bitwidth_v2i32(<2 x i32> %x) { define i1 @ctpop_ugt_bitwidth_minus_one_i8(i8 %x, ptr %p) { ; CHECK-LABEL: @ctpop_ugt_bitwidth_minus_one_i8( -; CHECK-NEXT: [[POP:%.*]] = tail call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[POP:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: store i8 [[POP]], ptr [[P:%.*]], align 1 ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i8 [[X]], -1 ; CHECK-NEXT: ret i1 [[CMP]] @@ -563,7 +563,7 @@ define i1 @trunc_cttz_ult_other_i33_i6(i33 %x) { define i1 @trunc_cttz_ult_other_i33_i5(i33 %x) { ; CHECK-LABEL: @trunc_cttz_ult_other_i33_i5( -; CHECK-NEXT: [[TZ:%.*]] = tail call i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i33 0, 34) i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 true) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i33 [[TZ]] to i5 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i5 [[TRUNC]], 7 ; CHECK-NEXT: ret i1 [[CMP]] @@ -590,7 +590,7 @@ define i1 @trunc_cttz_true_ult_other_i32_i5(i32 %x) { define i1 @trunc_cttz_false_ult_other_i32_i5(i32 %x) { ; CHECK-LABEL: @trunc_cttz_false_ult_other_i32_i5( -; CHECK-NEXT: [[TZ:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[TZ]] to i5 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i5 [[TRUNC]], 7 ; CHECK-NEXT: ret i1 [[CMP]] @@ -617,7 +617,7 @@ define i1 @trunc_cttz_false_ult_other_i32_i6(i32 %x) { define i1 @trunc_cttz_false_ult_other_i32_i6_extra_use(i32 %x) { ; CHECK-LABEL: @trunc_cttz_false_ult_other_i32_i6_extra_use( -; CHECK-NEXT: [[TZ:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw i32 [[TZ]] to i6 ; CHECK-NEXT: call void @use6(i6 [[TRUNC]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i6 [[TRUNC]], 7 @@ -667,7 +667,7 @@ define i1 @trunc_ctlz_ugt_other_i33_i6(i33 %x) { define i1 @trunc_ctlz_ugt_other_i33_i5(i33 %x) { ; CHECK-LABEL: @trunc_ctlz_ugt_other_i33_i5( -; CHECK-NEXT: [[LZ:%.*]] = tail call i33 @llvm.ctlz.i33(i33 [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i33 0, 34) i33 @llvm.ctlz.i33(i33 [[X:%.*]], i1 true) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i33 [[LZ]] to i5 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i5 [[TRUNC]], 4 ; CHECK-NEXT: ret i1 [[CMP]] @@ -693,7 +693,7 @@ define i1 @trunc_ctlz_true_ugt_other_i32_i5(i32 %x) { define i1 @trunc_ctlz_false_ugt_other_i32_i5(i32 %x) { ; CHECK-LABEL: @trunc_ctlz_false_ugt_other_i32_i5( -; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[LZ]] to i5 ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i5 [[TRUNC]], 4 ; CHECK-NEXT: ret i1 [[CMP]] @@ -719,7 +719,7 @@ define i1 @trunc_ctlz_false_ugt_other_i32_i6(i32 %x) { define i1 @trunc_ctlz_false_ugt_other_i32_i6_extra_use(i32 %x) { ; CHECK-LABEL: @trunc_ctlz_false_ugt_other_i32_i6_extra_use( -; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw i32 [[LZ]] to i6 ; CHECK-NEXT: call void @use6(i6 [[TRUNC]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i6 [[TRUNC]], 4 @@ -758,7 +758,7 @@ define i1 @trunc_ctpop_eq_bitwidth_i8(i8 %x) { define i1 @trunc_negative_destbits_not_enough(i33 %x) { ; CHECK-LABEL: @trunc_negative_destbits_not_enough( -; CHECK-NEXT: [[TZ:%.*]] = tail call i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i33 0, 34) i33 @llvm.cttz.i33(i33 [[X:%.*]], i1 false) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i33 [[TZ]] to i4 ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i4 [[TRUNC]], 7 ; CHECK-NEXT: ret i1 [[CMP]] diff --git a/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll b/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll index a5189f47650569778cfdd8b3a7ebc9ea0658a9b3..ec822f4b8fb3a5d100abbf041ff79103bd928bfa 100644 --- a/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll +++ b/llvm/test/Transforms/InstCombine/ctlz-cttz-bitreverse.ll @@ -3,7 +3,7 @@ define i32 @ctlz_true_bitreverse(i32 %x) { ; CHECK-LABEL: @ctlz_true_bitreverse( -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[B]] ; %a = tail call i32 @llvm.bitreverse.i32(i32 %x) @@ -13,7 +13,7 @@ define i32 @ctlz_true_bitreverse(i32 %x) { define <2 x i64> @ctlz_true_bitreverse_vec(<2 x i64> %x) { ; CHECK-LABEL: @ctlz_true_bitreverse_vec( -; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 true) ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = tail call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %x) @@ -23,7 +23,7 @@ define <2 x i64> @ctlz_true_bitreverse_vec(<2 x i64> %x) { define i32 @ctlz_false_bitreverse(i32 %x) { ; CHECK-LABEL: @ctlz_false_bitreverse( -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[B]] ; %a = tail call i32 @llvm.bitreverse.i32(i32 %x) @@ -33,7 +33,7 @@ define i32 @ctlz_false_bitreverse(i32 %x) { define i32 @cttz_true_bitreverse(i32 %x) { ; CHECK-LABEL: @cttz_true_bitreverse( -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[B]] ; %a = tail call i32 @llvm.bitreverse.i32(i32 %x) @@ -43,7 +43,7 @@ define i32 @cttz_true_bitreverse(i32 %x) { define <2 x i64> @cttz_true_bitreverse_vec(<2 x i64> %x) { ; CHECK-LABEL: @cttz_true_bitreverse_vec( -; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[B:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.ctlz.v2i64(<2 x i64> [[X:%.*]], i1 true) ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = tail call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %x) @@ -53,7 +53,7 @@ define <2 x i64> @cttz_true_bitreverse_vec(<2 x i64> %x) { define i32 @cttz_false_bitreverse(i32 %x) { ; CHECK-LABEL: @cttz_false_bitreverse( -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[B]] ; %a = tail call i32 @llvm.bitreverse.i32(i32 %x) diff --git a/llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll b/llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll index 86fef51872b1908685c27a24b60fc2ac2676c14a..15aa87f72c49a1a95ea9f0121cafcc22f4d5479c 100644 --- a/llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll +++ b/llvm/test/Transforms/InstCombine/ctlz-cttz-shifts.ll @@ -122,7 +122,7 @@ define <2 x i32> @vec2_shl_nsw_ctlz_true_neg(<2 x i32>) { ; CHECK-LABEL: define <2 x i32> @vec2_shl_nsw_ctlz_true_neg( ; CHECK-SAME: <2 x i32> [[TMP0:%.*]]) { ; CHECK-NEXT: [[SHL:%.*]] = shl nsw <2 x i32> , [[TMP0]] -; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[SHL]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 1, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[SHL]], i1 true) ; CHECK-NEXT: ret <2 x i32> [[CTLZ]] ; %shl = shl nsw <2 x i32> , %0 @@ -134,7 +134,7 @@ define <2 x i32> @vec2_lshr_ctlz_false_neg(<2 x i32>) { ; CHECK-LABEL: define <2 x i32> @vec2_lshr_ctlz_false_neg( ; CHECK-SAME: <2 x i32> [[TMP0:%.*]]) { ; CHECK-NEXT: [[DIV:%.*]] = lshr <2 x i32> , [[TMP0]] -; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[DIV]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 9, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[DIV]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CTLZ]] ; %div = lshr <2 x i32> , %0 @@ -146,7 +146,7 @@ define <2 x i32> @vec2_shl_ctlz_false_neg(<2 x i32>) { ; CHECK-LABEL: define <2 x i32> @vec2_shl_ctlz_false_neg( ; CHECK-SAME: <2 x i32> [[TMP0:%.*]]) { ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> , [[TMP0]] -; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[SHL]], i1 false), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[SHL]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CTLZ]] ; %shl = shl <2 x i32> , %0 @@ -158,7 +158,7 @@ define <2 x i32> @vec2_lshr_cttz_false_neg(<2 x i32>) { ; CHECK-LABEL: define <2 x i32> @vec2_lshr_cttz_false_neg( ; CHECK-SAME: <2 x i32> [[TMP0:%.*]]) { ; CHECK-NEXT: [[LSHR:%.*]] = lshr <2 x i32> , [[TMP0]] -; CHECK-NEXT: [[CTTZ:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[LSHR]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[LSHR]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CTTZ]] ; %lshr = lshr <2 x i32> , %0 @@ -170,7 +170,7 @@ define <2 x i32> @vec2_shl_cttz_false_neg(<2 x i32>) { ; CHECK-LABEL: define <2 x i32> @vec2_shl_cttz_false_neg( ; CHECK-SAME: <2 x i32> [[TMP0:%.*]]) { ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i32> , [[TMP0]] -; CHECK-NEXT: [[CTTZ:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[SHL]], i1 false), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 3, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[SHL]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CTTZ]] ; %shl = shl <2 x i32> , %0 @@ -182,7 +182,7 @@ define i32 @lshr_ctlz_faslse_neg(i32) { ; CHECK-LABEL: define i32 @lshr_ctlz_faslse_neg( ; CHECK-SAME: i32 [[TMP0:%.*]]) { ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 8387584, [[TMP0]] -; CHECK-NEXT: [[CTLZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 9, 33) i32 @llvm.ctlz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: ret i32 [[CTLZ]] ; %lshr = lshr i32 8387584, %0 @@ -194,7 +194,7 @@ define i32 @shl_ctlz_false_neg(i32) { ; CHECK-LABEL: define i32 @shl_ctlz_false_neg( ; CHECK-SAME: i32 [[TMP0:%.*]]) { ; CHECK-NEXT: [[SHL:%.*]] = shl i32 8387584, [[TMP0]] -; CHECK-NEXT: [[CTLZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[SHL]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[SHL]], i1 false) ; CHECK-NEXT: ret i32 [[CTLZ]] ; %shl = shl i32 8387584, %0 @@ -206,7 +206,7 @@ define i32 @lshr_cttz_false_neg(i32) { ; CHECK-LABEL: define i32 @lshr_cttz_false_neg( ; CHECK-SAME: i32 [[TMP0:%.*]]) { ; CHECK-NEXT: [[LSHR:%.*]] = lshr i32 8387584, [[TMP0]] -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[LSHR]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[LSHR]], i1 false) ; CHECK-NEXT: ret i32 [[CTTZ]] ; %lshr = lshr i32 8387584, %0 @@ -218,17 +218,10 @@ define i32 @shl_cttz_false_neg(i32) { ; CHECK-LABEL: define i32 @shl_cttz_false_neg( ; CHECK-SAME: i32 [[TMP0:%.*]]) { ; CHECK-NEXT: [[SHL:%.*]] = shl i32 8387584, [[TMP0]] -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[SHL]], i1 false), !range [[RNG4:![0-9]+]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 10, 33) i32 @llvm.cttz.i32(i32 [[SHL]], i1 false) ; CHECK-NEXT: ret i32 [[CTTZ]] ; %shl = shl i32 8387584, %0 %cttz = call i32 @llvm.cttz.i32(i32 %shl, i1 false) ret i32 %cttz } -;. -; CHECK: [[RNG0]] = !{i32 1, i32 33} -; CHECK: [[RNG1]] = !{i32 9, i32 33} -; CHECK: [[RNG2]] = !{i32 0, i32 33} -; CHECK: [[RNG3]] = !{i32 3, i32 33} -; CHECK: [[RNG4]] = !{i32 10, i32 33} -;. diff --git a/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll b/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll index 2f523f90edda8871193f1ed38225cf50261fec24..7e4050873dc924b9f0765c6a4c1096b07fe2d352 100644 --- a/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll +++ b/llvm/test/Transforms/InstCombine/ctpop-bswap-bitreverse.ll @@ -3,7 +3,7 @@ define i32 @ctpop_bitreverse(i32 %x) { ; CHECK-LABEL: @ctpop_bitreverse( -; CHECK-NEXT: [[B:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: ret i32 [[B]] ; %a = tail call i32 @llvm.bitreverse.i32(i32 %x) @@ -13,7 +13,7 @@ define i32 @ctpop_bitreverse(i32 %x) { define <2 x i64> @ctpop_bitreverse_vec(<2 x i64> %x) { ; CHECK-LABEL: @ctpop_bitreverse_vec( -; CHECK-NEXT: [[B:%.*]] = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]]), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = tail call range(i64 0, 65) <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]]) ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = tail call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> %x) @@ -23,7 +23,7 @@ define <2 x i64> @ctpop_bitreverse_vec(<2 x i64> %x) { define i32 @ctpop_bswap(i32 %x) { ; CHECK-LABEL: @ctpop_bswap( -; CHECK-NEXT: [[B:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[B:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: ret i32 [[B]] ; %a = tail call i32 @llvm.bswap.i32(i32 %x) @@ -33,7 +33,7 @@ define i32 @ctpop_bswap(i32 %x) { define <2 x i64> @ctpop_bswap_vec(<2 x i64> %x) { ; CHECK-LABEL: @ctpop_bswap_vec( -; CHECK-NEXT: [[B:%.*]] = tail call <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[B:%.*]] = tail call range(i64 0, 65) <2 x i64> @llvm.ctpop.v2i64(<2 x i64> [[X:%.*]]) ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = tail call <2 x i64> @llvm.bswap.v2i64(<2 x i64> %x) diff --git a/llvm/test/Transforms/InstCombine/ctpop-cttz.ll b/llvm/test/Transforms/InstCombine/ctpop-cttz.ll index 70868554bdc1bbfacf662b70dd2a871713063a5c..a505654fa96e7fbb6e90fabf6c21059ca2189a7b 100644 --- a/llvm/test/Transforms/InstCombine/ctpop-cttz.ll +++ b/llvm/test/Transforms/InstCombine/ctpop-cttz.ll @@ -8,7 +8,7 @@ declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) ; __builtin_popcount(i | -i) -> 32 - __builtin_cttz(i, false) define i32 @ctpop1(i32 %0) { ; CHECK-LABEL: @ctpop1( -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP0:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[TMP2]] ; %2 = sub i32 0, %0 @@ -20,7 +20,7 @@ define i32 @ctpop1(i32 %0) { define <2 x i32> @ctpop1v(<2 x i32> %0) { ; CHECK-LABEL: @ctpop1v( -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false) ; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw <2 x i32> , [[TMP2]] ; CHECK-NEXT: ret <2 x i32> [[TMP3]] ; @@ -35,7 +35,7 @@ define i32 @ctpop1_multiuse(i32 %0) { ; CHECK-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP0:%.*]] ; CHECK-NEXT: [[TMP3:%.*]] = or i32 [[TMP2]], [[TMP0]] ; CHECK-NEXT: [[TMP4:%.*]] = xor i32 [[TMP3]], -1 -; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP4]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP5:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[TMP4]]) ; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], [[TMP3]] ; CHECK-NEXT: ret i32 [[TMP6]] ; @@ -51,7 +51,7 @@ define i32 @ctpop1_multiuse(i32 %0) { ; __builtin_popcount(~i & (i-1)) -> __builtin_cttz(i, false) define i32 @ctpop2(i32 %0) { ; CHECK-LABEL: @ctpop2( -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP0:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[TMP2]] ; %2 = xor i32 %0, -1 @@ -63,7 +63,7 @@ define i32 @ctpop2(i32 %0) { define <2 x i32> @ctpop2v(<2 x i32> %0) { ; CHECK-LABEL: @ctpop2v( -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[TMP2]] ; %2 = xor <2 x i32> %0, @@ -78,7 +78,7 @@ define i32 @ctpop2_multiuse(i32 %0) { ; CHECK-NEXT: [[TMP2:%.*]] = xor i32 [[TMP0:%.*]], -1 ; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP0]], -1 ; CHECK-NEXT: [[TMP4:%.*]] = and i32 [[TMP3]], [[TMP2]] -; CHECK-NEXT: [[TMP5:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP5:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) ; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], [[TMP4]] ; CHECK-NEXT: ret i32 [[TMP6]] ; @@ -94,7 +94,7 @@ define i32 @ctpop2_multiuse(i32 %0) { ; __builtin_popcount((i & -i) - 1) -> __builtin_cttz(i, false) define i32 @ctpop3(i32 %0) { ; CHECK-LABEL: @ctpop3( -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP0:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP0:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[TMP2]] ; %2 = sub i32 0, %0 @@ -106,7 +106,7 @@ define i32 @ctpop3(i32 %0) { define <2 x i32> @ctpop3v(<2 x i32> %0) { ; CHECK-LABEL: @ctpop3v( -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[TMP2]] ; %2 = sub <2 x i32> zeroinitializer, %0 @@ -118,7 +118,7 @@ define <2 x i32> @ctpop3v(<2 x i32> %0) { define <2 x i32> @ctpop3v_poison(<2 x i32> %0) { ; CHECK-LABEL: @ctpop3v_poison( -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[TMP0:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[TMP2]] ; %2 = sub <2 x i32> zeroinitializer, %0 diff --git a/llvm/test/Transforms/InstCombine/ctpop-pow2.ll b/llvm/test/Transforms/InstCombine/ctpop-pow2.ll index f6757c2ff33cfaea99832a313c34219a22c0ce63..7facdaf7590d386c504e1630c0526a8630d63220 100644 --- a/llvm/test/Transforms/InstCombine/ctpop-pow2.ll +++ b/llvm/test/Transforms/InstCombine/ctpop-pow2.ll @@ -60,7 +60,7 @@ define i8 @ctpop_imin_plus1_lshr_nz(i8 %x) { ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i8 [[X:%.*]], 0 ; CHECK-NEXT: call void @llvm.assume(i1 [[CMP]]) ; CHECK-NEXT: [[V:%.*]] = lshr i8 -127, [[X]] -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[V]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[V]]) ; CHECK-NEXT: ret i8 [[CNT]] ; %cmp = icmp ne i8 %x, 0 @@ -104,7 +104,7 @@ define <2 x i32> @ctpop_lshr_intmin_intmin_plus1_vec_nz(<2 x i32> %x) { ; CHECK-LABEL: @ctpop_lshr_intmin_intmin_plus1_vec_nz( ; CHECK-NEXT: [[X1:%.*]] = or <2 x i32> [[X:%.*]], ; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i32> , [[X1]] -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHR]]), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 0, 17) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHR]]) ; CHECK-NEXT: ret <2 x i32> [[CNT]] ; %x1 = or <2 x i32> %x, diff --git a/llvm/test/Transforms/InstCombine/ctpop.ll b/llvm/test/Transforms/InstCombine/ctpop.ll index b3653e5071ba252e0ee41f3ade0aae637a309fc6..83700e72de080952b9314b10b30efbe5b5ef53bf 100644 --- a/llvm/test/Transforms/InstCombine/ctpop.ll +++ b/llvm/test/Transforms/InstCombine/ctpop.ll @@ -49,7 +49,7 @@ define i1 @test3(i32 %arg) { ; Negative test for when we know nothing define i1 @test4(i8 %arg) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[ARG:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[ARG:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = icmp eq i8 [[CNT]], 2 ; CHECK-NEXT: ret i1 [[RES]] ; @@ -118,7 +118,7 @@ define <2 x i32> @mask_one_bit_splat(<2 x i32> %x, ptr %p) { define i32 @_parity_of_not(i32 %x) { ; CHECK-LABEL: @_parity_of_not( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = and i32 [[TMP1]], 1 ; CHECK-NEXT: ret i32 [[R]] ; @@ -133,7 +133,7 @@ define i32 @_parity_of_not(i32 %x) { define i7 @_parity_of_not_odd_type(i7 %x) { ; CHECK-LABEL: @_parity_of_not_odd_type( ; CHECK-NEXT: [[NEG:%.*]] = xor i7 [[X:%.*]], -1 -; CHECK-NEXT: [[CNT:%.*]] = tail call i7 @llvm.ctpop.i7(i7 [[NEG]]), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = tail call range(i7 0, 8) i7 @llvm.ctpop.i7(i7 [[NEG]]) ; CHECK-NEXT: [[R:%.*]] = and i7 [[CNT]], 1 ; CHECK-NEXT: ret i7 [[R]] ; @@ -145,7 +145,7 @@ define i7 @_parity_of_not_odd_type(i7 %x) { define <2 x i32> @_parity_of_not_vec(<2 x i32> %x) { ; CHECK-LABEL: @_parity_of_not_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = and <2 x i32> [[TMP1]], ; CHECK-NEXT: ret <2 x i32> [[R]] ; @@ -157,7 +157,7 @@ define <2 x i32> @_parity_of_not_vec(<2 x i32> %x) { define <2 x i32> @_parity_of_not_poison(<2 x i32> %x) { ; CHECK-LABEL: @_parity_of_not_poison( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = and <2 x i32> [[TMP1]], ; CHECK-NEXT: ret <2 x i32> [[R]] ; @@ -169,7 +169,7 @@ define <2 x i32> @_parity_of_not_poison(<2 x i32> %x) { define <2 x i32> @_parity_of_not_poison2(<2 x i32> %x) { ; CHECK-LABEL: @_parity_of_not_poison2( -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = and <2 x i32> [[CNT]], ; CHECK-NEXT: ret <2 x i32> [[R]] ; @@ -200,7 +200,7 @@ define i32 @ctpop_add(i32 %a, i32 %b) { define i32 @ctpop_add_no_common_bits(i32 %a, i32 %b) { ; CHECK-LABEL: @ctpop_add_no_common_bits( ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.fshl.i32(i32 [[A:%.*]], i32 [[B:%.*]], i32 16) -; CHECK-NEXT: [[RES:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[RES:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[TMP1]]) ; CHECK-NEXT: ret i32 [[RES]] ; %shl16 = shl i32 %a, 16 @@ -214,7 +214,7 @@ define i32 @ctpop_add_no_common_bits(i32 %a, i32 %b) { define <2 x i32> @ctpop_add_no_common_bits_vec(<2 x i32> %a, <2 x i32> %b) { ; CHECK-LABEL: @ctpop_add_no_common_bits_vec( ; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> [[A:%.*]], <2 x i32> [[B:%.*]], <2 x i32> ) -; CHECK-NEXT: [[RES:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[RES:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) ; CHECK-NEXT: ret <2 x i32> [[RES]] ; %shl16 = shl <2 x i32> %a, @@ -228,9 +228,9 @@ define <2 x i32> @ctpop_add_no_common_bits_vec(<2 x i32> %a, <2 x i32> %b) { define <2 x i32> @ctpop_add_no_common_bits_vec_use(<2 x i32> %a, <2 x i32> %b, ptr %p) { ; CHECK-LABEL: @ctpop_add_no_common_bits_vec_use( ; CHECK-NEXT: [[SHL16:%.*]] = shl <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[CTPOP1:%.*]] = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHL16]]), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[CTPOP1:%.*]] = tail call range(i32 0, 17) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHL16]]) ; CHECK-NEXT: [[LSHL16:%.*]] = lshr <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[CTPOP2:%.*]] = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[LSHL16]]), !range [[RNG3]] +; CHECK-NEXT: [[CTPOP2:%.*]] = tail call range(i32 0, 17) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[LSHL16]]) ; CHECK-NEXT: store <2 x i32> [[CTPOP2]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: [[RES:%.*]] = add nuw nsw <2 x i32> [[CTPOP1]], [[CTPOP2]] ; CHECK-NEXT: ret <2 x i32> [[RES]] @@ -247,10 +247,10 @@ define <2 x i32> @ctpop_add_no_common_bits_vec_use(<2 x i32> %a, <2 x i32> %b, p define <2 x i32> @ctpop_add_no_common_bits_vec_use2(<2 x i32> %a, <2 x i32> %b, ptr %p) { ; CHECK-LABEL: @ctpop_add_no_common_bits_vec_use2( ; CHECK-NEXT: [[SHL16:%.*]] = shl <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[CTPOP1:%.*]] = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHL16]]), !range [[RNG3]] +; CHECK-NEXT: [[CTPOP1:%.*]] = tail call range(i32 0, 17) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[SHL16]]) ; CHECK-NEXT: store <2 x i32> [[CTPOP1]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: [[LSHL16:%.*]] = lshr <2 x i32> [[B:%.*]], -; CHECK-NEXT: [[CTPOP2:%.*]] = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[LSHL16]]), !range [[RNG3]] +; CHECK-NEXT: [[CTPOP2:%.*]] = tail call range(i32 0, 17) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[LSHL16]]) ; CHECK-NEXT: [[RES:%.*]] = add nuw nsw <2 x i32> [[CTPOP1]], [[CTPOP2]] ; CHECK-NEXT: ret <2 x i32> [[RES]] ; @@ -265,7 +265,7 @@ define <2 x i32> @ctpop_add_no_common_bits_vec_use2(<2 x i32> %a, <2 x i32> %b, define i8 @ctpop_rotate_left(i8 %a, i8 %amt) { ; CHECK-LABEL: @ctpop_rotate_left( -; CHECK-NEXT: [[RES:%.*]] = tail call i8 @llvm.ctpop.i8(i8 [[A:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[RES:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[A:%.*]]) ; CHECK-NEXT: ret i8 [[RES]] ; %rotl = tail call i8 @llvm.fshl.i8(i8 %a, i8 %a, i8 %amt) @@ -275,7 +275,7 @@ define i8 @ctpop_rotate_left(i8 %a, i8 %amt) { define i8 @ctpop_rotate_right(i8 %a, i8 %amt) { ; CHECK-LABEL: @ctpop_rotate_right( -; CHECK-NEXT: [[RES:%.*]] = tail call i8 @llvm.ctpop.i8(i8 [[A:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[RES:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[A:%.*]]) ; CHECK-NEXT: ret i8 [[RES]] ; %rotr = tail call i8 @llvm.fshr.i8(i8 %a, i8 %a, i8 %amt) @@ -289,7 +289,7 @@ declare i8 @llvm.fshr.i8(i8, i8, i8) define i8 @sub_ctpop(i8 %a) { ; CHECK-LABEL: @sub_ctpop( ; CHECK-NEXT: [[TMP1:%.*]] = xor i8 [[A:%.*]], -1 -; CHECK-NEXT: [[RES:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] +; CHECK-NEXT: [[RES:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: ret i8 [[RES]] ; %cnt = tail call i8 @llvm.ctpop.i8(i8 %a) @@ -299,7 +299,7 @@ define i8 @sub_ctpop(i8 %a) { define i8 @sub_ctpop_wrong_cst(i8 %a) { ; CHECK-LABEL: @sub_ctpop_wrong_cst( -; CHECK-NEXT: [[CNT:%.*]] = tail call i8 @llvm.ctpop.i8(i8 [[A:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[A:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = sub nsw i8 5, [[CNT]] ; CHECK-NEXT: ret i8 [[RES]] ; @@ -310,7 +310,7 @@ define i8 @sub_ctpop_wrong_cst(i8 %a) { define i8 @sub_ctpop_unknown(i8 %a, i8 %b) { ; CHECK-LABEL: @sub_ctpop_unknown( -; CHECK-NEXT: [[CNT:%.*]] = tail call i8 @llvm.ctpop.i8(i8 [[A:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = tail call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[A:%.*]]) ; CHECK-NEXT: [[RES:%.*]] = sub i8 [[B:%.*]], [[CNT]] ; CHECK-NEXT: ret i8 [[RES]] ; @@ -322,7 +322,7 @@ define i8 @sub_ctpop_unknown(i8 %a, i8 %b) { define <2 x i32> @sub_ctpop_vec(<2 x i32> %a) { ; CHECK-LABEL: @sub_ctpop_vec( ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[RES:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[RES:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) ; CHECK-NEXT: ret <2 x i32> [[RES]] ; %cnt = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> %a) @@ -332,7 +332,7 @@ define <2 x i32> @sub_ctpop_vec(<2 x i32> %a) { define <2 x i32> @sub_ctpop_vec_extra_use(<2 x i32> %a, ptr %p) { ; CHECK-LABEL: @sub_ctpop_vec_extra_use( -; CHECK-NEXT: [[CNT:%.*]] = tail call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[A:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[CNT:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[A:%.*]]) ; CHECK-NEXT: store <2 x i32> [[CNT]], ptr [[P:%.*]], align 8 ; CHECK-NEXT: [[RES:%.*]] = sub nuw nsw <2 x i32> , [[CNT]] ; CHECK-NEXT: ret <2 x i32> [[RES]] @@ -345,7 +345,7 @@ define <2 x i32> @sub_ctpop_vec_extra_use(<2 x i32> %a, ptr %p) { define i32 @zext_ctpop(i16 %x) { ; CHECK-LABEL: @zext_ctpop( -; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.ctpop.i16(i16 [[X:%.*]]), !range [[RNG4:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 [[X:%.*]]) ; CHECK-NEXT: [[P:%.*]] = zext nneg i16 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[P]] ; @@ -356,7 +356,7 @@ define i32 @zext_ctpop(i16 %x) { define <2 x i32> @zext_ctpop_vec(<2 x i7> %x) { ; CHECK-LABEL: @zext_ctpop_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i7> @llvm.ctpop.v2i7(<2 x i7> [[X:%.*]]), !range [[RNG2]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i7 0, 8) <2 x i7> @llvm.ctpop.v2i7(<2 x i7> [[X:%.*]]) ; CHECK-NEXT: [[P:%.*]] = zext nneg <2 x i7> [[TMP1]] to <2 x i32> ; CHECK-NEXT: ret <2 x i32> [[P]] ; @@ -369,7 +369,7 @@ define i32 @zext_ctpop_extra_use(i16 %x, ptr %q) { ; CHECK-LABEL: @zext_ctpop_extra_use( ; CHECK-NEXT: [[Z:%.*]] = zext i16 [[X:%.*]] to i32 ; CHECK-NEXT: store i32 [[Z]], ptr [[Q:%.*]], align 4 -; CHECK-NEXT: [[P:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Z]]), !range [[RNG3]] +; CHECK-NEXT: [[P:%.*]] = call range(i32 0, 17) i32 @llvm.ctpop.i32(i32 [[Z]]) ; CHECK-NEXT: ret i32 [[P]] ; %z = zext i16 %x to i32 @@ -381,7 +381,7 @@ define i32 @zext_ctpop_extra_use(i16 %x, ptr %q) { define i32 @parity_xor(i32 %arg, i32 %arg1) { ; CHECK-LABEL: @parity_xor( ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[ARG1:%.*]], [[ARG:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[TMP1]]) ; CHECK-NEXT: [[I4:%.*]] = and i32 [[TMP2]], 1 ; CHECK-NEXT: ret i32 [[I4]] ; @@ -395,7 +395,7 @@ define i32 @parity_xor(i32 %arg, i32 %arg1) { define i32 @parity_xor_trunc(i64 %arg, i64 %arg1) { ; CHECK-LABEL: @parity_xor_trunc( ; CHECK-NEXT: [[TMP1:%.*]] = xor i64 [[ARG1:%.*]], [[ARG:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[TMP1]]), !range [[RNG5:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 [[TMP1]]) ; CHECK-NEXT: [[I4:%.*]] = trunc nuw nsw i64 [[TMP2]] to i32 ; CHECK-NEXT: [[I5:%.*]] = and i32 [[I4]], 1 ; CHECK-NEXT: ret i32 [[I5]] @@ -411,7 +411,7 @@ define i32 @parity_xor_trunc(i64 %arg, i64 %arg1) { define <2 x i32> @parity_xor_vec(<2 x i32> %arg, <2 x i32> %arg1) { ; CHECK-LABEL: @parity_xor_vec( ; CHECK-NEXT: [[TMP1:%.*]] = xor <2 x i32> [[ARG1:%.*]], [[ARG:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[TMP1]]) ; CHECK-NEXT: [[I4:%.*]] = and <2 x i32> [[TMP2]], ; CHECK-NEXT: ret <2 x i32> [[I4]] ; @@ -424,8 +424,8 @@ define <2 x i32> @parity_xor_vec(<2 x i32> %arg, <2 x i32> %arg1) { define i32 @parity_xor_wrong_cst(i32 %arg, i32 %arg1) { ; CHECK-LABEL: @parity_xor_wrong_cst( -; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[ARG:%.*]]), !range [[RNG1]] -; CHECK-NEXT: [[I2:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[ARG1:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[I:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[ARG:%.*]]) +; CHECK-NEXT: [[I2:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[ARG1:%.*]]) ; CHECK-NEXT: [[I3:%.*]] = xor i32 [[I2]], [[I]] ; CHECK-NEXT: [[I4:%.*]] = and i32 [[I3]], 3 ; CHECK-NEXT: ret i32 [[I4]] @@ -439,11 +439,11 @@ define i32 @parity_xor_wrong_cst(i32 %arg, i32 %arg1) { define i32 @parity_xor_extra_use(i32 %arg, i32 %arg1) { ; CHECK-LABEL: @parity_xor_extra_use( -; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[ARG:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[I:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[ARG:%.*]]) ; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], 1 ; CHECK-NEXT: tail call void @use(i32 [[I2]]) ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[ARG1:%.*]], [[ARG]] -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[TMP1]]) ; CHECK-NEXT: [[I5:%.*]] = and i32 [[TMP2]], 1 ; CHECK-NEXT: ret i32 [[I5]] ; @@ -458,11 +458,11 @@ define i32 @parity_xor_extra_use(i32 %arg, i32 %arg1) { define i32 @parity_xor_extra_use2(i32 %arg, i32 %arg1) { ; CHECK-LABEL: @parity_xor_extra_use2( -; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[ARG1:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[I:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[ARG1:%.*]]) ; CHECK-NEXT: [[I2:%.*]] = and i32 [[I]], 1 ; CHECK-NEXT: tail call void @use(i32 [[I2]]) ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[ARG1]], [[ARG:%.*]] -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctpop.i32(i32 [[TMP1]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[TMP1]]) ; CHECK-NEXT: [[I5:%.*]] = and i32 [[TMP2]], 1 ; CHECK-NEXT: ret i32 [[I5]] ; @@ -477,7 +477,7 @@ define i32 @parity_xor_extra_use2(i32 %arg, i32 %arg1) { define i32 @select_ctpop_zero(i32 %x) { ; CHECK-LABEL: @select_ctpop_zero( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: ret i32 [[CTPOP]] ; %ctpop = call i32 @llvm.ctpop.i32(i32 %x) diff --git a/llvm/test/Transforms/InstCombine/cttz-abs.ll b/llvm/test/Transforms/InstCombine/cttz-abs.ll index 0141b2cd71cec9a5dfc7105a9d42883bf09bd39c..9d3b6168e710be1dbbdf9f7b45bd11e0c397068a 100644 --- a/llvm/test/Transforms/InstCombine/cttz-abs.ll +++ b/llvm/test/Transforms/InstCombine/cttz-abs.ll @@ -3,7 +3,7 @@ define i32 @cttz_abs(i32 %x) { ; CHECK-LABEL: @cttz_abs( -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 0 @@ -15,7 +15,7 @@ define i32 @cttz_abs(i32 %x) { define <2 x i64> @cttz_abs_vec(<2 x i64> %x) { ; CHECK-LABEL: @cttz_abs_vec( -; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[R:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[R]] ; %c = icmp slt <2 x i64> %x, zeroinitializer @@ -29,7 +29,7 @@ define i32 @cttz_abs2(i32 %x) { ; CHECK-LABEL: @cttz_abs2( ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], 0 ; CHECK-NEXT: call void @use_cond(i1 [[C]]) -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp sgt i32 %x, 0 @@ -44,7 +44,7 @@ define i32 @cttz_abs3(i32 %x) { ; CHECK-LABEL: @cttz_abs3( ; CHECK-NEXT: [[C:%.*]] = icmp sgt i32 [[X:%.*]], -1 ; CHECK-NEXT: call void @use_cond(i1 [[C]]) -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp sgt i32 %x, -1 @@ -57,7 +57,7 @@ define i32 @cttz_abs3(i32 %x) { define i32 @cttz_abs4(i32 %x) { ; CHECK-LABEL: @cttz_abs4( -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 1 @@ -69,7 +69,7 @@ define i32 @cttz_abs4(i32 %x) { define i32 @cttz_nabs(i32 %x) { ; CHECK-LABEL: @cttz_nabs( -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 0 @@ -81,7 +81,7 @@ define i32 @cttz_nabs(i32 %x) { define <2 x i64> @cttz_nabs_vec(<2 x i64> %x) { ; CHECK-LABEL: @cttz_nabs_vec( -; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[R:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[R]] ; %c = icmp slt <2 x i64> %x, zeroinitializer @@ -93,7 +93,7 @@ define <2 x i64> @cttz_nabs_vec(<2 x i64> %x) { define i64 @cttz_abs_64(i64 %x) { ; CHECK-LABEL: @cttz_abs_64( -; CHECK-NEXT: [[R:%.*]] = call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[R:%.*]] = call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i64 [[R]] ; %c = icmp slt i64 %x, 0 @@ -107,7 +107,7 @@ define i32 @cttz_abs_multiuse(i32 %x) { ; CHECK-LABEL: @cttz_abs_multiuse( ; CHECK-NEXT: [[D:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: call void @use_abs(i32 [[D]]) -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 1 @@ -123,7 +123,7 @@ define i32 @cttz_nabs_multiuse(i32 %x) { ; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.abs.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[D:%.*]] = sub i32 0, [[TMP1]] ; CHECK-NEXT: call void @use_abs(i32 [[D]]) -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 1 @@ -141,7 +141,7 @@ define i32 @no_cttz_abs(i32 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 2 ; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]] ; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]] -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[D]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 2 @@ -156,7 +156,7 @@ define i32 @no_cttz_abs2(i32 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i32 [[X:%.*]], 0 ; CHECK-NEXT: [[S:%.*]] = sub i32 1, [[X]] ; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[S]], i32 [[X]] -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[D]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp slt i32 %x, 0 @@ -172,7 +172,7 @@ define i32 @no_cttz_abs3(i32 %x) { ; CHECK-NEXT: call void @use_cond(i1 [[C]]) ; CHECK-NEXT: [[S:%.*]] = sub i32 0, [[X]] ; CHECK-NEXT: [[D:%.*]] = select i1 [[C]], i32 [[X]], i32 [[S]] -; CHECK-NEXT: [[R:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[D]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[D]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %c = icmp sgt i32 %x, -2 @@ -188,7 +188,7 @@ define <2 x i64> @no_cttz_abs_vec(<2 x i64> %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[X:%.*]], ; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> , [[X]] ; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[C]], <2 x i64> [[S]], <2 x i64> [[X]] -; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[R:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[R]] ; %c = icmp slt <2 x i64> %x, @@ -203,7 +203,7 @@ define <2 x i64> @no_cttz_nabs_vec(<2 x i64> %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt <2 x i64> [[X:%.*]], ; CHECK-NEXT: [[S:%.*]] = sub <2 x i64> , [[X]] ; CHECK-NEXT: [[D:%.*]] = select <2 x i1> [[C]], <2 x i64> [[X]], <2 x i64> [[S]] -; CHECK-NEXT: [[R:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[R:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[D]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[R]] ; %c = icmp slt <2 x i64> %x, @@ -215,7 +215,7 @@ define <2 x i64> @no_cttz_nabs_vec(<2 x i64> %x) { define i32 @cttz_abs_intrin(i32 %x) { ; CHECK-LABEL: @cttz_abs_intrin( -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[R]] ; %a = call i32 @llvm.abs.i32(i32 %x, i1 false) @@ -225,7 +225,7 @@ define i32 @cttz_abs_intrin(i32 %x) { define i32 @cttz_nabs_intrin(i32 %x) { ; CHECK-LABEL: @cttz_nabs_intrin( -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[R:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[R]] ; %a = call i32 @llvm.abs.i32(i32 %x, i1 false) diff --git a/llvm/test/Transforms/InstCombine/cttz-negative.ll b/llvm/test/Transforms/InstCombine/cttz-negative.ll index 139da840af9e4efb536de5cb89d3bf141b3c3d41..6f812e420935db9da70d3a1ff963ca12b692f6a7 100644 --- a/llvm/test/Transforms/InstCombine/cttz-negative.ll +++ b/llvm/test/Transforms/InstCombine/cttz-negative.ll @@ -3,7 +3,7 @@ define i32 @cttz_neg_value(i32 %x) { ; CHECK-LABEL: @cttz_neg_value( -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[B]] ; %a = sub i32 0, %x @@ -15,7 +15,7 @@ define i32 @cttz_neg_value_multiuse(i32 %x) { ; CHECK-LABEL: @cttz_neg_value_multiuse( ; CHECK-NEXT: [[A:%.*]] = sub i32 0, [[X:%.*]] ; CHECK-NEXT: call void @use(i32 [[A]]) -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[X]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 false) ; CHECK-NEXT: ret i32 [[B]] ; %a = sub i32 0, %x @@ -26,7 +26,7 @@ define i32 @cttz_neg_value_multiuse(i32 %x) { define i64 @cttz_neg_value_64(i64 %x) { ; CHECK-LABEL: @cttz_neg_value_64( -; CHECK-NEXT: [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[B:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i64 [[B]] ; %a = sub i64 0, %x @@ -36,7 +36,7 @@ define i64 @cttz_neg_value_64(i64 %x) { define i64 @cttz_neg_value2_64(i64 %x) { ; CHECK-LABEL: @cttz_neg_value2_64( -; CHECK-NEXT: [[B:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[B:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i64 [[B]] ; %a = sub i64 0, %x @@ -46,7 +46,7 @@ define i64 @cttz_neg_value2_64(i64 %x) { define <2 x i64> @cttz_neg_value_vec(<2 x i64> %x) { ; CHECK-LABEL: @cttz_neg_value_vec( -; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[B:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = sub <2 x i64> zeroinitializer, %x @@ -59,7 +59,7 @@ define <2 x i64> @cttz_neg_value_vec(<2 x i64> %x) { define i32 @cttz_nonneg_value(i32 %x) { ; CHECK-LABEL: @cttz_nonneg_value( ; CHECK-NEXT: [[A:%.*]] = sub i32 1, [[X:%.*]] -; CHECK-NEXT: [[B:%.*]] = call i32 @llvm.cttz.i32(i32 [[A]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[B:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A]], i1 false) ; CHECK-NEXT: ret i32 [[B]] ; %a = sub i32 1, %x @@ -70,7 +70,7 @@ define i32 @cttz_nonneg_value(i32 %x) { define <2 x i64> @cttz_nonneg_value_vec(<2 x i64> %x) { ; CHECK-LABEL: @cttz_nonneg_value_vec( ; CHECK-NEXT: [[A:%.*]] = sub <2 x i64> , [[X:%.*]] -; CHECK-NEXT: [[B:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[A]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[B:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[A]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[B]] ; %a = sub <2 x i64> , %x diff --git a/llvm/test/Transforms/InstCombine/cttz.ll b/llvm/test/Transforms/InstCombine/cttz.ll index 6ea5e5e141b2edfe0bda80defb1e8f1bc6186c7e..3595cff5f1aed062c923989bb86e04483b00f640 100644 --- a/llvm/test/Transforms/InstCombine/cttz.ll +++ b/llvm/test/Transforms/InstCombine/cttz.ll @@ -8,7 +8,7 @@ declare void @use(i32) define i32 @cttz_zext_zero_undef(i16 %x) { ; CHECK-LABEL: @cttz_zext_zero_undef( -; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true) ; CHECK-NEXT: [[TZ:%.*]] = zext nneg i16 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[TZ]] ; @@ -20,7 +20,7 @@ define i32 @cttz_zext_zero_undef(i16 %x) { define i32 @cttz_zext_zero_def(i16 %x) { ; CHECK-LABEL: @cttz_zext_zero_def( ; CHECK-NEXT: [[Z:%.*]] = zext i16 [[X:%.*]] to i32 -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Z]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Z]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %z = zext i16 %x to i32 @@ -32,7 +32,7 @@ define i32 @cttz_zext_zero_undef_extra_use(i16 %x) { ; CHECK-LABEL: @cttz_zext_zero_undef_extra_use( ; CHECK-NEXT: [[Z:%.*]] = zext i16 [[X:%.*]] to i32 ; CHECK-NEXT: call void @use(i32 [[Z]]) -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Z]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Z]], i1 true) ; CHECK-NEXT: ret i32 [[TZ]] ; %z = zext i16 %x to i32 @@ -43,7 +43,7 @@ define i32 @cttz_zext_zero_undef_extra_use(i16 %x) { define <2 x i64> @cttz_zext_zero_undef_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_zext_zero_undef_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true) ; CHECK-NEXT: [[TZ:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[TZ]] ; @@ -55,7 +55,7 @@ define <2 x i64> @cttz_zext_zero_undef_vec(<2 x i32> %x) { define <2 x i64> @cttz_zext_zero_def_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_zext_zero_def_vec( ; CHECK-NEXT: [[Z:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64> -; CHECK-NEXT: [[TZ:%.*]] = tail call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[Z]], i1 false), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[TZ:%.*]] = tail call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[Z]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %z = zext <2 x i32> %x to <2 x i64> @@ -65,7 +65,7 @@ define <2 x i64> @cttz_zext_zero_def_vec(<2 x i32> %x) { define i32 @cttz_sext_zero_undef(i16 %x) { ; CHECK-LABEL: @cttz_sext_zero_undef( -; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true) ; CHECK-NEXT: [[TZ:%.*]] = zext nneg i16 [[TMP1]] to i32 ; CHECK-NEXT: ret i32 [[TZ]] ; @@ -77,7 +77,7 @@ define i32 @cttz_sext_zero_undef(i16 %x) { define i32 @cttz_sext_zero_def(i16 %x) { ; CHECK-LABEL: @cttz_sext_zero_def( ; CHECK-NEXT: [[TMP1:%.*]] = zext i16 [[X:%.*]] to i32 -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[TMP1]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %s = sext i16 %x to i32 @@ -89,7 +89,7 @@ define i32 @cttz_sext_zero_undef_extra_use(i16 %x) { ; CHECK-LABEL: @cttz_sext_zero_undef_extra_use( ; CHECK-NEXT: [[S:%.*]] = sext i16 [[X:%.*]] to i32 ; CHECK-NEXT: call void @use(i32 [[S]]) -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[S]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[S]], i1 true) ; CHECK-NEXT: ret i32 [[TZ]] ; %s = sext i16 %x to i32 @@ -100,7 +100,7 @@ define i32 @cttz_sext_zero_undef_extra_use(i16 %x) { define <2 x i64> @cttz_sext_zero_undef_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_sext_zero_undef_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true) ; CHECK-NEXT: [[TZ:%.*]] = zext nneg <2 x i32> [[TMP1]] to <2 x i64> ; CHECK-NEXT: ret <2 x i64> [[TZ]] ; @@ -112,7 +112,7 @@ define <2 x i64> @cttz_sext_zero_undef_vec(<2 x i32> %x) { define <2 x i64> @cttz_sext_zero_def_vec(<2 x i32> %x) { ; CHECK-LABEL: @cttz_sext_zero_def_vec( ; CHECK-NEXT: [[TMP1:%.*]] = zext <2 x i32> [[X:%.*]] to <2 x i64> -; CHECK-NEXT: [[TZ:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[TMP1]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[TMP1]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %s = sext <2 x i32> %x to <2 x i64> @@ -122,7 +122,7 @@ define <2 x i64> @cttz_sext_zero_def_vec(<2 x i32> %x) { define i32 @cttz_of_lowest_set_bit(i32 %x) { ; CHECK-LABEL: @cttz_of_lowest_set_bit( -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %sub = sub i32 0, %x @@ -134,7 +134,7 @@ define i32 @cttz_of_lowest_set_bit(i32 %x) { define i32 @cttz_of_lowest_set_bit_commuted(i32 %xx) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_commuted( ; CHECK-NEXT: [[X:%.*]] = udiv i32 42, [[XX:%.*]] -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %x = udiv i32 42, %xx ; thwart complexity-based canonicalization @@ -146,7 +146,7 @@ define i32 @cttz_of_lowest_set_bit_commuted(i32 %xx) { define i32 @cttz_of_lowest_set_bit_poison_flag(i32 %x) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_poison_flag( -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[TZ]] ; %sub = sub i32 0, %x @@ -157,7 +157,7 @@ define i32 @cttz_of_lowest_set_bit_poison_flag(i32 %x) { define <2 x i64> @cttz_of_lowest_set_bit_vec(<2 x i64> %x) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_vec( -; CHECK-NEXT: [[TZ:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %sub = sub <2 x i64> zeroinitializer, %x @@ -168,7 +168,7 @@ define <2 x i64> @cttz_of_lowest_set_bit_vec(<2 x i64> %x) { define <2 x i64> @cttz_of_lowest_set_bit_vec_undef(<2 x i64> %x) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_vec_undef( -; CHECK-NEXT: [[TZ:%.*]] = call <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i64 0, 65) <2 x i64> @llvm.cttz.v2i64(<2 x i64> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i64> [[TZ]] ; %sub = sub <2 x i64> zeroinitializer, %x @@ -181,7 +181,7 @@ define i32 @cttz_of_lowest_set_bit_wrong_const(i32 %x) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_wrong_const( ; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[X:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[X]] -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[AND]], i1 false), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 1, 33) i32 @llvm.cttz.i32(i32 [[AND]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %sub = sub i32 1, %x @@ -194,7 +194,7 @@ define i32 @cttz_of_lowest_set_bit_wrong_operand(i32 %x, i32 %y) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_wrong_operand( ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[Y:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[X:%.*]] -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[AND]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[AND]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %sub = sub i32 0, %y @@ -207,7 +207,7 @@ define i32 @cttz_of_lowest_set_bit_wrong_intrinsic(i32 %x) { ; CHECK-LABEL: @cttz_of_lowest_set_bit_wrong_intrinsic( ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[X:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[X]] -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[AND]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[AND]], i1 false) ; CHECK-NEXT: ret i32 [[TZ]] ; %sub = sub i32 0, %x diff --git a/llvm/test/Transforms/InstCombine/ffs-1.ll b/llvm/test/Transforms/InstCombine/ffs-1.ll index 7cf080765bb1b6857f1dfee724ccef2056eaa01e..db01801b1225cd36c1073b473680c296ee383791 100644 --- a/llvm/test/Transforms/InstCombine/ffs-1.ll +++ b/llvm/test/Transforms/InstCombine/ffs-1.ll @@ -148,7 +148,7 @@ define i32 @test_simplify12() { define i32 @test_simplify13(i32 %x) { ; ALL-LABEL: @test_simplify13( -; ALL-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0 +; ALL-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %x, i1 true) ; ALL-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1 ; ALL-NEXT: [[TMP2:%.*]] = icmp eq i32 %x, 0 ; ALL-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 0, i32 [[TMP1]] @@ -164,7 +164,7 @@ define i32 @test_simplify14(i32 %x) { ; GENERIC-NEXT: ret i32 [[RET]] ; ; TARGET-LABEL: @test_simplify14( -; TARGET-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 %x, i1 true), !range !0 +; TARGET-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 %x, i1 true) ; TARGET-NEXT: [[TMP1:%.*]] = add nuw nsw i32 [[CTTZ]], 1 ; TARGET-NEXT: [[TMP2:%.*]] = icmp eq i32 %x, 0 ; TARGET-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 0, i32 [[TMP1]] @@ -180,7 +180,7 @@ define i32 @test_simplify15(i64 %x) { ; GENERIC-NEXT: ret i32 [[RET]] ; ; TARGET-LABEL: @test_simplify15( -; TARGET-NEXT: [[CTTZ:%.*]] = call i64 @llvm.cttz.i64(i64 %x, i1 true), !range !1 +; TARGET-NEXT: [[CTTZ:%.*]] = call range(i64 0, 65) i64 @llvm.cttz.i64(i64 %x, i1 true) ; TARGET-NEXT: [[TMP1:%.*]] = trunc nuw nsw i64 [[CTTZ]] to i32 ; TARGET-NEXT: [[TMP2:%.*]] = add nuw nsw i32 [[TMP1]], 1 ; TARGET-NEXT: [[TMP3:%.*]] = icmp eq i64 %x, 0 diff --git a/llvm/test/Transforms/InstCombine/ffs-i16.ll b/llvm/test/Transforms/InstCombine/ffs-i16.ll index f2b1f074f86d562d41aa8f047411ec2e65734132..ab5f1307f4d9d33e4acde3477be75e389233447e 100644 --- a/llvm/test/Transforms/InstCombine/ffs-i16.ll +++ b/llvm/test/Transforms/InstCombine/ffs-i16.ll @@ -17,7 +17,7 @@ define void @fold_ffs(i16 %x) { ; AVR-LABEL: @fold_ffs( ; AVR-NEXT: call addrspace(1) void @sink(i16 0) ; AVR-NEXT: call addrspace(1) void @sink(i16 1) -; AVR-NEXT: [[CTTZ:%.*]] = call addrspace(1) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; AVR-NEXT: [[CTTZ:%.*]] = call range(i16 0, 17) addrspace(1) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true) ; AVR-NEXT: [[TMP1:%.*]] = add nuw nsw i16 [[CTTZ]], 1 ; AVR-NEXT: [[DOTNOT:%.*]] = icmp eq i16 [[X]], 0 ; AVR-NEXT: [[NX:%.*]] = select i1 [[DOTNOT]], i16 0, i16 [[TMP1]] @@ -27,7 +27,7 @@ define void @fold_ffs(i16 %x) { ; MSP430-LABEL: @fold_ffs( ; MSP430-NEXT: call void @sink(i16 0) ; MSP430-NEXT: call void @sink(i16 1) -; MSP430-NEXT: [[CTTZ:%.*]] = call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; MSP430-NEXT: [[CTTZ:%.*]] = call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 true) ; MSP430-NEXT: [[TMP1:%.*]] = add nuw nsw i16 [[CTTZ]], 1 ; MSP430-NEXT: [[DOTNOT:%.*]] = icmp eq i16 [[X]], 0 ; MSP430-NEXT: [[NX:%.*]] = select i1 [[DOTNOT]], i16 0, i16 [[TMP1]] diff --git a/llvm/test/Transforms/InstCombine/fls-i16.ll b/llvm/test/Transforms/InstCombine/fls-i16.ll index 54692fde5303ebcde85b2761b3460b05345b4461..e48397f5116a4b6c08c4070900608ba5c43efc81 100644 --- a/llvm/test/Transforms/InstCombine/fls-i16.ll +++ b/llvm/test/Transforms/InstCombine/fls-i16.ll @@ -17,7 +17,7 @@ define void @fold_fls(i16 %x) { ; AVR-LABEL: @fold_fls( ; AVR-NEXT: call addrspace(1) void @sink(i16 0) ; AVR-NEXT: call addrspace(1) void @sink(i16 1) -; AVR-NEXT: [[CTLZ:%.*]] = call addrspace(1) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; AVR-NEXT: [[CTLZ:%.*]] = call range(i16 0, 17) addrspace(1) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; AVR-NEXT: [[NX:%.*]] = sub nuw nsw i16 16, [[CTLZ]] ; AVR-NEXT: call addrspace(1) void @sink(i16 [[NX]]) ; AVR-NEXT: ret void @@ -25,7 +25,7 @@ define void @fold_fls(i16 %x) { ; MSP430-LABEL: @fold_fls( ; MSP430-NEXT: call void @sink(i16 0) ; MSP430-NEXT: call void @sink(i16 1) -; MSP430-NEXT: [[CTLZ:%.*]] = call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; MSP430-NEXT: [[CTLZ:%.*]] = call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; MSP430-NEXT: [[NX:%.*]] = sub nuw nsw i16 16, [[CTLZ]] ; MSP430-NEXT: call void @sink(i16 [[NX]]) ; MSP430-NEXT: ret void diff --git a/llvm/test/Transforms/InstCombine/fls.ll b/llvm/test/Transforms/InstCombine/fls.ll index 7710093e195a11f0c2ac53de84802ff4d53e7389..68bc0a2fc8a1d195e7b855c112a957e814605f96 100644 --- a/llvm/test/Transforms/InstCombine/fls.ll +++ b/llvm/test/Transforms/InstCombine/fls.ll @@ -31,7 +31,7 @@ define i32 @myflsll() { define i32 @flsnotconst(i64 %z) { ; CHECK-LABEL: @flsnotconst( -; CHECK-NEXT: [[CTLZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[Z:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[Z:%.*]], i1 false) ; CHECK-NEXT: [[TMP1:%.*]] = trunc nuw nsw i64 [[CTLZ]] to i32 ; CHECK-NEXT: [[GOO:%.*]] = sub nsw i32 64, [[TMP1]] ; CHECK-NEXT: ret i32 [[GOO]] diff --git a/llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll b/llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll index bbce5c2d625ec8d8eac5e2babfd024b220578986..4626d19bd2899ddde2579fa4ba93178191f28d66 100644 --- a/llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll +++ b/llvm/test/Transforms/InstCombine/fold-ctpop-of-not.ll @@ -8,7 +8,7 @@ declare <2 x i8> @llvm.ctpop.v2i8(<2 x i8>) define i8 @fold_sub_c_ctpop(i8 %x) { ; CHECK-LABEL: @fold_sub_c_ctpop( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = add nuw nsw i8 [[TMP1]], 4 ; CHECK-NEXT: ret i8 [[R]] ; @@ -21,7 +21,7 @@ define i8 @fold_sub_c_ctpop(i8 %x) { define i8 @fold_sub_var_ctpop_fail(i8 %x, i8 %y) { ; CHECK-LABEL: @fold_sub_var_ctpop_fail( ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1 -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[NX]]) ; CHECK-NEXT: [[R:%.*]] = sub i8 [[Y:%.*]], [[CNT]] ; CHECK-NEXT: ret i8 [[R]] ; @@ -33,7 +33,7 @@ define i8 @fold_sub_var_ctpop_fail(i8 %x, i8 %y) { define <2 x i8> @fold_sub_ctpop_c(<2 x i8> %x) { ; CHECK-LABEL: @fold_sub_ctpop_c( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = sub nuw nsw <2 x i8> , [[TMP1]] ; CHECK-NEXT: ret <2 x i8> [[R]] ; @@ -45,7 +45,7 @@ define <2 x i8> @fold_sub_ctpop_c(<2 x i8> %x) { define i8 @fold_add_ctpop_c(i8 %x) { ; CHECK-LABEL: @fold_add_ctpop_c( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i8 71, [[TMP1]] ; CHECK-NEXT: ret i8 [[R]] ; @@ -57,7 +57,7 @@ define i8 @fold_add_ctpop_c(i8 %x) { define i8 @fold_distjoint_or_ctpop_c(i8 %x) { ; CHECK-LABEL: @fold_distjoint_or_ctpop_c( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = sub nuw nsw i8 72, [[TMP1]] ; CHECK-NEXT: ret i8 [[R]] ; @@ -70,7 +70,7 @@ define i8 @fold_distjoint_or_ctpop_c(i8 %x) { define i8 @fold_or_ctpop_c_fail(i8 %x) { ; CHECK-LABEL: @fold_or_ctpop_c_fail( ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1 -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[NX]]) ; CHECK-NEXT: [[R:%.*]] = or i8 [[CNT]], 65 ; CHECK-NEXT: ret i8 [[R]] ; @@ -83,7 +83,7 @@ define i8 @fold_or_ctpop_c_fail(i8 %x) { define i8 @fold_add_ctpop_var_fail(i8 %x, i8 %y) { ; CHECK-LABEL: @fold_add_ctpop_var_fail( ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1 -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[NX]]) ; CHECK-NEXT: [[R:%.*]] = add i8 [[CNT]], [[Y:%.*]] ; CHECK-NEXT: ret i8 [[R]] ; @@ -105,7 +105,7 @@ define i1 @fold_icmp_sgt_ctpop_c_i2_fail(i2 %x, i2 %C) { define i1 @fold_cmp_eq_ctpop_c(i8 %x) { ; CHECK-LABEL: @fold_cmp_eq_ctpop_c( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP1]], 6 ; CHECK-NEXT: ret i1 [[R]] ; @@ -118,7 +118,7 @@ define i1 @fold_cmp_eq_ctpop_c(i8 %x) { define i1 @fold_cmp_eq_ctpop_c_multiuse_fail(i8 %x) { ; CHECK-LABEL: @fold_cmp_eq_ctpop_c_multiuse_fail( ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -1 -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[NX]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[CNT]], 2 ; CHECK-NEXT: call void @use.i8(i8 [[CNT]]) ; CHECK-NEXT: ret i1 [[R]] @@ -132,7 +132,7 @@ define i1 @fold_cmp_eq_ctpop_c_multiuse_fail(i8 %x) { define <2 x i1> @fold_cmp_ne_ctpop_c(<2 x i8> %x) { ; CHECK-LABEL: @fold_cmp_ne_ctpop_c( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -145,7 +145,7 @@ define <2 x i1> @fold_cmp_ne_ctpop_c(<2 x i8> %x) { define <2 x i1> @fold_cmp_ne_ctpop_var_fail(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @fold_cmp_ne_ctpop_var_fail( ; CHECK-NEXT: [[NX:%.*]] = xor <2 x i8> [[X:%.*]], -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[NX]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[CNT]], [[Y:%.*]] ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -159,7 +159,7 @@ define i1 @fold_cmp_ult_ctpop_c(i8 %x, i8 %y, i1 %cond) { ; CHECK-LABEL: @fold_cmp_ult_ctpop_c( ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 -16, [[Y:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i8 [[X:%.*]], i8 [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP2]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP3:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP2]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[TMP3]], 3 ; CHECK-NEXT: ret i1 [[R]] ; @@ -175,7 +175,7 @@ define i1 @fold_cmp_sle_ctpop_c(i8 %x, i8 %y, i1 %cond) { ; CHECK-LABEL: @fold_cmp_sle_ctpop_c( ; CHECK-NEXT: [[TMP1:%.*]] = sub i8 -16, [[Y:%.*]] ; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[COND:%.*]], i8 [[X:%.*]], i8 [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP2]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP3:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP2]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[TMP3]], 4 ; CHECK-NEXT: ret i1 [[R]] ; @@ -190,7 +190,7 @@ define i1 @fold_cmp_sle_ctpop_c(i8 %x, i8 %y, i1 %cond) { define i1 @fold_cmp_ult_ctpop_c_no_not_inst_save_fail(i8 %x) { ; CHECK-LABEL: @fold_cmp_ult_ctpop_c_no_not_inst_save_fail( ; CHECK-NEXT: [[NX:%.*]] = xor i8 [[X:%.*]], -2 -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctpop.i8(i8 [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[NX]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[CNT]], 5 ; CHECK-NEXT: ret i1 [[R]] ; @@ -202,7 +202,7 @@ define i1 @fold_cmp_ult_ctpop_c_no_not_inst_save_fail(i8 %x) { define <2 x i1> @fold_cmp_ugt_ctpop_c(<2 x i8> %x) { ; CHECK-LABEL: @fold_cmp_ugt_ctpop_c( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -215,7 +215,7 @@ define <2 x i1> @fold_cmp_ugt_ctpop_c(<2 x i8> %x) { define <2 x i1> @fold_cmp_ugt_ctpop_c_out_of_range_fail(<2 x i8> %x) { ; CHECK-LABEL: @fold_cmp_ugt_ctpop_c_out_of_range_fail( ; CHECK-NEXT: [[NX:%.*]] = xor <2 x i8> [[X:%.*]], -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[NX]]), !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[NX]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[CNT]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll b/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll index a631aacd97ff947ab2fc89bc1f721c33d617d110..17e51e73201b168a240c55cf41115409cc636dd3 100644 --- a/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll +++ b/llvm/test/Transforms/InstCombine/fold-log2-ceil-idiom.ll @@ -5,7 +5,7 @@ define i32 @log2_ceil_idiom(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom( ; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] ; CHECK-NEXT: ret i32 [[RET]] ; @@ -22,7 +22,7 @@ define i5 @log2_ceil_idiom_trunc(i32 %x) { ; CHECK-LABEL: define i5 @log2_ceil_idiom_trunc( ; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: [[TMP3:%.*]] = sub nsw i32 0, [[TMP2]] ; CHECK-NEXT: [[RET:%.*]] = trunc i32 [[TMP3]] to i5 ; CHECK-NEXT: ret i5 [[RET]] @@ -41,7 +41,7 @@ define i64 @log2_ceil_idiom_zext(i32 %x) { ; CHECK-LABEL: define i64 @log2_ceil_idiom_zext( ; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 32, [[TMP2]] ; CHECK-NEXT: [[RET:%.*]] = zext nneg i32 [[TMP3]] to i64 ; CHECK-NEXT: ret i64 [[RET]] @@ -60,7 +60,7 @@ define i32 @log2_ceil_idiom_power2_test2(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_power2_test2( ; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] ; CHECK-NEXT: ret i32 [[RET]] ; @@ -77,7 +77,7 @@ define i32 @log2_ceil_idiom_commuted(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_commuted( ; CHECK-SAME: i32 [[X:%.*]]) { ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] ; CHECK-NEXT: ret i32 [[RET]] ; @@ -93,10 +93,10 @@ define i32 @log2_ceil_idiom_commuted(i32 %x) { define i32 @log2_ceil_idiom_multiuse1(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_multiuse1( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: call void @use32(i32 [[CTPOP]]) ; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[X]], -1 -; CHECK-NEXT: [[TMP2:%.*]] = call i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[TMP1]], i1 false) ; CHECK-NEXT: [[RET:%.*]] = sub nuw nsw i32 32, [[TMP2]] ; CHECK-NEXT: ret i32 [[RET]] ; @@ -115,9 +115,9 @@ define i32 @log2_ceil_idiom_multiuse1(i32 %x) { define i32 @log2_ceil_idiom_x_may_be_zero(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_x_may_be_zero( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 false) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -135,10 +135,10 @@ define i32 @log2_ceil_idiom_x_may_be_zero(i32 %x) { define i4 @log2_ceil_idiom_trunc_too_short(i32 %x) { ; CHECK-LABEL: define i4 @log2_ceil_idiom_trunc_too_short( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i32 [[CTLZ]] to i4 ; CHECK-NEXT: [[XOR:%.*]] = xor i4 [[TRUNC]], -1 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i4 ; CHECK-NEXT: [[RET:%.*]] = add i4 [[XOR]], [[ZEXT]] @@ -157,9 +157,9 @@ define i4 @log2_ceil_idiom_trunc_too_short(i32 %x) { define i32 @log2_ceil_idiom_mismatched_operands(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_mismatched_operands( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[Y]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -177,9 +177,9 @@ define i32 @log2_ceil_idiom_mismatched_operands(i32 %x, i32 %y) { define i32 @log2_ceil_idiom_wrong_constant(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_wrong_constant( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 30 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -197,9 +197,9 @@ define i32 @log2_ceil_idiom_wrong_constant(i32 %x) { define i32 @log2_ceil_idiom_not_a_power2_test1(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_not_a_power2_test1( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -217,9 +217,9 @@ define i32 @log2_ceil_idiom_not_a_power2_test1(i32 %x) { define i32 @log2_ceil_idiom_not_a_power2_test2(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_not_a_power2_test2( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 2 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -237,10 +237,10 @@ define i32 @log2_ceil_idiom_not_a_power2_test2(i32 %x) { define i32 @log2_ceil_idiom_multiuse2(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_multiuse2( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: call void @use32(i32 [[CTLZ]]) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -259,10 +259,10 @@ define i32 @log2_ceil_idiom_multiuse2(i32 %x) { define i32 @log2_ceil_idiom_multiuse3(i32 %x) { ; CHECK-LABEL: define i32 @log2_ceil_idiom_multiuse3( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 ; CHECK-NEXT: call void @use32(i32 [[XOR]]) -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i32 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i32 [[XOR]], [[ZEXT]] @@ -281,11 +281,11 @@ define i32 @log2_ceil_idiom_multiuse3(i32 %x) { define i5 @log2_ceil_idiom_trunc_multiuse4(i32 %x) { ; CHECK-LABEL: define i5 @log2_ceil_idiom_trunc_multiuse4( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw i32 [[CTLZ]] to i5 ; CHECK-NEXT: call void @use5(i5 [[TRUNC]]) ; CHECK-NEXT: [[XOR:%.*]] = xor i5 [[TRUNC]], -1 -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i5 ; CHECK-NEXT: [[RET:%.*]] = add i5 [[XOR]], [[ZEXT]] @@ -305,11 +305,11 @@ define i5 @log2_ceil_idiom_trunc_multiuse4(i32 %x) { define i64 @log2_ceil_idiom_zext_multiuse5(i32 %x) { ; CHECK-LABEL: define i64 @log2_ceil_idiom_zext_multiuse5( ; CHECK-SAME: i32 [[X:%.*]]) { -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X]], i1 true) ; CHECK-NEXT: [[XOR:%.*]] = xor i32 [[CTLZ]], 31 ; CHECK-NEXT: [[EXT:%.*]] = zext nneg i32 [[XOR]] to i64 ; CHECK-NEXT: call void @use64(i64 [[EXT]]) -; CHECK-NEXT: [[CTPOP:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[CTPOP]], 1 ; CHECK-NEXT: [[ZEXT:%.*]] = zext i1 [[CMP]] to i64 ; CHECK-NEXT: [[RET:%.*]] = add nuw nsw i64 [[EXT]], [[ZEXT]] @@ -332,6 +332,3 @@ declare void @use64(i64) declare i32 @llvm.ctlz.i32(i32, i1) declare i32 @llvm.ctpop.i32(i32) -;. -; CHECK: [[RNG0]] = !{i32 0, i32 33} -;. diff --git a/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll b/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll index 105bd28fb052e8c76e22187ff86f22fc8969663c..c4a590e1a12bfaa475531bfa5916def66db807af 100644 --- a/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll +++ b/llvm/test/Transforms/InstCombine/freeze-integer-intrinsics.ll @@ -3,7 +3,7 @@ define i32 @ctlz_true_freeze(i32 %arg) { ; CHECK-LABEL: @ctlz_true_freeze( -; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.ctlz.i32(i32 [[ARG:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CALL:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[ARG:%.*]], i1 true) ; CHECK-NEXT: [[FREEZE:%.*]] = freeze i32 [[CALL]] ; CHECK-NEXT: ret i32 [[FREEZE]] ; @@ -15,7 +15,7 @@ define i32 @ctlz_true_freeze(i32 %arg) { define i32 @ctlz_false_freeze(i32 %arg) { ; CHECK-LABEL: @ctlz_false_freeze( ; CHECK-NEXT: [[ARG_FR:%.*]] = freeze i32 [[ARG:%.*]] -; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.ctlz.i32(i32 [[ARG_FR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[ARG_FR]], i1 false) ; CHECK-NEXT: ret i32 [[CALL]] ; %call = call i32 @llvm.ctlz.i32(i32 %arg, i1 false) @@ -25,7 +25,7 @@ define i32 @ctlz_false_freeze(i32 %arg) { define i32 @ctlz_true_noundef_freeze(i32 %arg) { ; CHECK-LABEL: @ctlz_true_noundef_freeze( -; CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @llvm.ctlz.i32(i32 [[ARG:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call noundef range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[ARG:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[CALL]] ; %call = call noundef i32 @llvm.ctlz.i32(i32 %arg, i1 true) @@ -35,7 +35,7 @@ define i32 @ctlz_true_noundef_freeze(i32 %arg) { define i32 @cttz_true_freeze(i32 %arg) { ; CHECK-LABEL: @cttz_true_freeze( -; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true) ; CHECK-NEXT: [[FREEZE:%.*]] = freeze i32 [[CALL]] ; CHECK-NEXT: ret i32 [[FREEZE]] ; @@ -46,7 +46,7 @@ define i32 @cttz_true_freeze(i32 %arg) { define i32 @cttz_true_noundef_freeze(i32 %arg) { ; CHECK-LABEL: @cttz_true_noundef_freeze( -; CHECK-NEXT: [[CALL:%.*]] = call noundef i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call noundef range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[CALL]] ; %call = call noundef i32 @llvm.cttz.i32(i32 %arg, i1 true) @@ -57,7 +57,7 @@ define i32 @cttz_true_noundef_freeze(i32 %arg) { define i32 @freeze_cttz_true(i32 %arg) { ; CHECK-LABEL: @freeze_cttz_true( ; CHECK-NEXT: [[FREEZE:%.*]] = freeze i32 [[ARG:%.*]] -; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.cttz.i32(i32 [[FREEZE]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[FREEZE]], i1 true) ; CHECK-NEXT: ret i32 [[CALL]] ; %freeze = freeze i32 %arg @@ -68,7 +68,7 @@ define i32 @freeze_cttz_true(i32 %arg) { define i32 @cttz_false_freeze(i32 %arg) { ; CHECK-LABEL: @cttz_false_freeze( ; CHECK-NEXT: [[ARG_FR:%.*]] = freeze i32 [[ARG:%.*]] -; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.cttz.i32(i32 [[ARG_FR]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG_FR]], i1 false) ; CHECK-NEXT: ret i32 [[CALL]] ; %call = call i32 @llvm.cttz.i32(i32 %arg, i1 false) @@ -79,7 +79,7 @@ define i32 @cttz_false_freeze(i32 %arg) { define i32 @freeze_cttz_false(i32 %arg) { ; CHECK-LABEL: @freeze_cttz_false( ; CHECK-NEXT: [[FREEZE:%.*]] = freeze i32 [[ARG:%.*]] -; CHECK-NEXT: [[CALL:%.*]] = call i32 @llvm.cttz.i32(i32 [[FREEZE]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CALL:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[FREEZE]], i1 false) ; CHECK-NEXT: ret i32 [[CALL]] ; %freeze = freeze i32 %arg diff --git a/llvm/test/Transforms/InstCombine/freeze.ll b/llvm/test/Transforms/InstCombine/freeze.ll index adcf7d50f413bea83eeb010010924d6d49c7496e..391d626a795c7d06b7b355878dfbd006ee1f7b5c 100644 --- a/llvm/test/Transforms/InstCombine/freeze.ll +++ b/llvm/test/Transforms/InstCombine/freeze.ll @@ -1107,7 +1107,7 @@ define i32 @freeze_ctpop(i32 %x) { ; CHECK-LABEL: @freeze_ctpop( ; CHECK-NEXT: [[Y:%.*]] = lshr i32 2047, [[X:%.*]] ; CHECK-NEXT: [[Y_FR:%.*]] = freeze i32 [[Y]] -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y_FR]]), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y_FR]]) ; CHECK-NEXT: ret i32 [[CTPOP]] ; %y = lshr i32 2047, %x @@ -1209,5 +1209,4 @@ define ptr @freeze_ptrmask_nonnull(ptr %p, i64 noundef %m) { ; CHECK: [[META0]] = !{} ; CHECK: [[META1]] = !{i64 4} ; CHECK: [[RNG2]] = !{i32 0, i32 100} -; CHECK: [[RNG3]] = !{i32 0, i32 33} ;. diff --git a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll index 70a2b33d17dd7caa533133092bd2bcf833a3ec5c..e9ec6b415d4621251491b15124cf8a6689f6be95 100644 --- a/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll +++ b/llvm/test/Transforms/InstCombine/icmp-ne-pow2.ll @@ -284,7 +284,7 @@ False: define i32 @pow2_32_nonconst_assume(i32 %x, i32 %y) { ; CHECK-LABEL: @pow2_32_nonconst_assume( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]] @@ -306,7 +306,7 @@ define i32 @pow2_32_nonconst_assume(i32 %x, i32 %y) { define i32 @pow2_32_gtnonconst_assume(i32 %x, i32 %y) { ; CHECK-LABEL: @pow2_32_gtnonconst_assume( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[YGT:%.*]] = icmp ugt i32 [[Y]], [[X:%.*]] @@ -327,7 +327,7 @@ define i32 @pow2_32_gtnonconst_assume(i32 %x, i32 %y) { define i32 @not_pow2_32_nonconst_assume(i32 %x, i32 %y) { ; CHECK-LABEL: @not_pow2_32_nonconst_assume( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp ne i32 [[CTPOP]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]] @@ -349,7 +349,7 @@ define i32 @not_pow2_32_nonconst_assume(i32 %x, i32 %y) { define i32 @pow2_or_zero_32_nonconst_assume(i32 %x, i32 %y) { ; CHECK-LABEL: @pow2_or_zero_32_nonconst_assume( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp ult i32 [[CTPOP]], 2 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]] @@ -371,7 +371,7 @@ define i32 @pow2_or_zero_32_nonconst_assume(i32 %x, i32 %y) { define i32 @pow2_32_nonconst_assume_br(i32 %x, i32 %y) { ; CHECK-LABEL: @pow2_32_nonconst_assume_br( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]] @@ -398,7 +398,7 @@ False: define i32 @not_pow2_32_nonconst_assume_br(i32 %x, i32 %y) { ; CHECK-LABEL: @not_pow2_32_nonconst_assume_br( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp ne i32 [[CTPOP]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]] @@ -425,7 +425,7 @@ False: define i32 @pow2_or_zero_32_nonconst_assume_br(i32 %x, i32 %y) { ; CHECK-LABEL: @pow2_or_zero_32_nonconst_assume_br( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp ult i32 [[CTPOP]], 2 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: [[AND:%.*]] = and i32 [[X:%.*]], [[Y]] @@ -452,7 +452,7 @@ False: define i32 @pow2_32_nonconst_br1_br(i32 %x, i32 %y) { ; CHECK-LABEL: @pow2_32_nonconst_br1_br( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: br i1 [[YP2]], label [[CONT:%.*]], label [[FALSE:%.*]] ; CHECK: Cont: @@ -481,7 +481,7 @@ False: define i32 @not_pow2_32_nonconst_br1_br(i32 %x, i32 %y) { ; CHECK-LABEL: @not_pow2_32_nonconst_br1_br( -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y:%.*]]) ; CHECK-NEXT: [[YP2_NOT:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: br i1 [[YP2_NOT]], label [[FALSE:%.*]], label [[CONT:%.*]] ; CHECK: Cont: @@ -513,7 +513,7 @@ define i32 @maybe_pow2_32_noncont(i32 %x, i32 %y) { ; CHECK-NEXT: [[YGT8:%.*]] = icmp ugt i32 [[Y:%.*]], 8 ; CHECK-NEXT: br i1 [[YGT8]], label [[CONT1:%.*]], label [[CONT2:%.*]] ; CHECK: Cont1: -; CHECK-NEXT: [[CTPOP:%.*]] = call i32 @llvm.ctpop.i32(i32 [[Y]]), !range [[RNG0]] +; CHECK-NEXT: [[CTPOP:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[Y]]) ; CHECK-NEXT: [[YP2:%.*]] = icmp eq i32 [[CTPOP]], 1 ; CHECK-NEXT: call void @llvm.assume(i1 [[YP2]]) ; CHECK-NEXT: br i1 true, label [[CONT2]], label [[FALSE:%.*]] diff --git a/llvm/test/Transforms/InstCombine/intrinsic-select.ll b/llvm/test/Transforms/InstCombine/intrinsic-select.ll index 1727d8f2758b01a3ea2292af2a3de3ed32bd71eb..f110d7765830efa3b594bd3fe950200c250cb19a 100644 --- a/llvm/test/Transforms/InstCombine/intrinsic-select.ll +++ b/llvm/test/Transforms/InstCombine/intrinsic-select.ll @@ -26,7 +26,7 @@ define i32 @ctlz_sel_const_true_false(i1 %b) { define i32 @ctlz_sel_const_true(i1 %b, i32 %x) { ; CHECK-LABEL: @ctlz_sel_const_true( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[C:%.*]] = select i1 [[B:%.*]], i32 29, i32 [[TMP1]] ; CHECK-NEXT: ret i32 [[C]] ; @@ -37,7 +37,7 @@ define i32 @ctlz_sel_const_true(i1 %b, i32 %x) { define <3 x i17> @ctlz_sel_const_false(<3 x i1> %b, <3 x i17> %x) { ; CHECK-LABEL: @ctlz_sel_const_false( -; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i17> @llvm.ctlz.v3i17(<3 x i17> [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i17 0, 18) <3 x i17> @llvm.ctlz.v3i17(<3 x i17> [[X:%.*]], i1 true) ; CHECK-NEXT: [[C:%.*]] = select <3 x i1> [[B:%.*]], <3 x i17> [[TMP1]], <3 x i17> ; CHECK-NEXT: ret <3 x i17> [[C]] ; @@ -50,7 +50,7 @@ define i32 @ctlz_sel_const_true_false_extra_use(i1 %b) { ; CHECK-LABEL: @ctlz_sel_const_true_false_extra_use( ; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 -1, i32 7 ; CHECK-NEXT: call void @use(i32 [[S]]) -; CHECK-NEXT: [[C:%.*]] = call i32 @llvm.ctlz.i32(i32 [[S]], i1 true), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[C:%.*]] = call range(i32 0, 30) i32 @llvm.ctlz.i32(i32 [[S]], i1 true) ; CHECK-NEXT: ret i32 [[C]] ; %s = select i1 %b, i32 -1, i32 7 @@ -71,7 +71,7 @@ define i32 @cttz_sel_const_true_false(i1 %b) { define i32 @cttz_sel_const_true(i1 %b, i32 %x) { ; CHECK-LABEL: @cttz_sel_const_true( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: [[C:%.*]] = select i1 [[B:%.*]], i32 0, i32 [[TMP1]] ; CHECK-NEXT: ret i32 [[C]] ; @@ -82,7 +82,7 @@ define i32 @cttz_sel_const_true(i1 %b, i32 %x) { define <3 x i5> @cttz_sel_const_false(<3 x i1> %b, <3 x i5> %x) { ; CHECK-LABEL: @cttz_sel_const_false( -; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i5> @llvm.cttz.v3i5(<3 x i5> [[X:%.*]], i1 false), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i5 0, 6) <3 x i5> @llvm.cttz.v3i5(<3 x i5> [[X:%.*]], i1 false) ; CHECK-NEXT: [[C:%.*]] = select <3 x i1> [[B:%.*]], <3 x i5> [[TMP1]], <3 x i5> ; CHECK-NEXT: ret <3 x i5> [[C]] ; @@ -95,7 +95,7 @@ define i32 @cttz_sel_const_true_false_extra_use(i1 %b) { ; CHECK-LABEL: @cttz_sel_const_true_false_extra_use( ; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 5, i32 -8 ; CHECK-NEXT: call void @use(i32 [[S]]) -; CHECK-NEXT: [[C:%.*]] = call i32 @llvm.cttz.i32(i32 [[S]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[C:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[S]], i1 true) ; CHECK-NEXT: ret i32 [[C]] ; %s = select i1 %b, i32 5, i32 -8 @@ -116,7 +116,7 @@ define i32 @ctpop_sel_const_true_false(i1 %b) { define i32 @ctpop_sel_const_true(i1 %b, i32 %x) { ; CHECK-LABEL: @ctpop_sel_const_true( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[C:%.*]] = select i1 [[B:%.*]], i32 2, i32 [[TMP1]] ; CHECK-NEXT: ret i32 [[C]] ; @@ -127,7 +127,7 @@ define i32 @ctpop_sel_const_true(i1 %b, i32 %x) { define <3 x i7> @ctpop_sel_const_false(<3 x i1> %b, <3 x i7> %x) { ; CHECK-LABEL: @ctpop_sel_const_false( -; CHECK-NEXT: [[TMP1:%.*]] = call <3 x i7> @llvm.ctpop.v3i7(<3 x i7> [[X:%.*]]), !range [[RNG4:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i7 0, 8) <3 x i7> @llvm.ctpop.v3i7(<3 x i7> [[X:%.*]]) ; CHECK-NEXT: [[C:%.*]] = select <3 x i1> [[B:%.*]], <3 x i7> [[TMP1]], <3 x i7> ; CHECK-NEXT: ret <3 x i7> [[C]] ; @@ -140,7 +140,7 @@ define i32 @ctpop_sel_const_true_false_extra_use(i1 %b) { ; CHECK-LABEL: @ctpop_sel_const_true_false_extra_use( ; CHECK-NEXT: [[S:%.*]] = select i1 [[B:%.*]], i32 5, i32 7 ; CHECK-NEXT: call void @use(i32 [[S]]) -; CHECK-NEXT: [[C:%.*]] = call i32 @llvm.ctpop.i32(i32 [[S]]), !range [[RNG5:![0-9]+]] +; CHECK-NEXT: [[C:%.*]] = call range(i32 2, 4) i32 @llvm.ctpop.i32(i32 [[S]]) ; CHECK-NEXT: ret i32 [[C]] ; %s = select i1 %b, i32 5, i32 7 diff --git a/llvm/test/Transforms/InstCombine/intrinsics.ll b/llvm/test/Transforms/InstCombine/intrinsics.ll index d90b0ebd400c721ded351f65a9eca6679c2d1b58..c8d70e17cd392112e96bd52a937d569c6bc1be39 100644 --- a/llvm/test/Transforms/InstCombine/intrinsics.ll +++ b/llvm/test/Transforms/InstCombine/intrinsics.ll @@ -139,7 +139,7 @@ define @cttz_knownbits_scalable_vec( %arg) { define i32 @cttz_knownbits2(i32 %arg) { ; CHECK-LABEL: @cttz_knownbits2( ; CHECK-NEXT: [[OR:%.*]] = or i32 [[ARG:%.*]], 4 -; CHECK-NEXT: [[CNT:%.*]] = call i32 @llvm.cttz.i32(i32 [[OR]], i1 true) #[[ATTR2:[0-9]+]], !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 0, 3) i32 @llvm.cttz.i32(i32 [[OR]], i1 true) #[[ATTR2:[0-9]+]] ; CHECK-NEXT: ret i32 [[CNT]] ; %or = or i32 %arg, 4 @@ -150,7 +150,7 @@ define i32 @cttz_knownbits2(i32 %arg) { define <2 x i32> @cttz_knownbits2_vec(<2 x i32> %arg) { ; CHECK-LABEL: @cttz_knownbits2_vec( ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[ARG:%.*]], -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true) #[[ATTR2]], !range [[RNG0]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 0, 3) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true) #[[ATTR2]] ; CHECK-NEXT: ret <2 x i32> [[CNT]] ; %or = or <2 x i32> %arg, @@ -256,7 +256,7 @@ define <2 x i1> @ctlz_knownbits_vec(<2 x i8> %arg) { define i8 @ctlz_knownbits2(i8 %arg) { ; CHECK-LABEL: @ctlz_knownbits2( ; CHECK-NEXT: [[OR:%.*]] = or i8 [[ARG:%.*]], 32 -; CHECK-NEXT: [[CNT:%.*]] = call i8 @llvm.ctlz.i8(i8 [[OR]], i1 true) #[[ATTR2]], !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 3) i8 @llvm.ctlz.i8(i8 [[OR]], i1 true) #[[ATTR2]] ; CHECK-NEXT: ret i8 [[CNT]] ; %or = or i8 %arg, 32 @@ -267,7 +267,7 @@ define i8 @ctlz_knownbits2(i8 %arg) { define <2 x i8> @ctlz_knownbits2_vec(<2 x i8> %arg) { ; CHECK-LABEL: @ctlz_knownbits2_vec( ; CHECK-NEXT: [[OR:%.*]] = or <2 x i8> [[ARG:%.*]], -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[OR]], i1 true) #[[ATTR2]], !range [[RNG1]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i8 0, 3) <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[OR]], i1 true) #[[ATTR2]] ; CHECK-NEXT: ret <2 x i8> [[CNT]] ; %or = or <2 x i8> %arg, @@ -314,7 +314,7 @@ define <2 x i32> @ctlz_poison_vec(<2 x i32> %Value) { define i32 @ctlz_no_zero(i32 %a) { ; CHECK-LABEL: @ctlz_no_zero( ; CHECK-NEXT: [[OR:%.*]] = or i32 [[A:%.*]], 8 -; CHECK-NEXT: [[CTLZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[OR]], i1 true), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 29) i32 @llvm.ctlz.i32(i32 [[OR]], i1 true) ; CHECK-NEXT: ret i32 [[CTLZ]] ; %or = or i32 %a, 8 @@ -325,7 +325,7 @@ define i32 @ctlz_no_zero(i32 %a) { define <2 x i32> @ctlz_no_zero_vec(<2 x i32> %a) { ; CHECK-LABEL: @ctlz_no_zero_vec( ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[CTLZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[OR]], i1 true), !range [[RNG2]] +; CHECK-NEXT: [[CTLZ:%.*]] = tail call range(i32 0, 29) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[OR]], i1 true) ; CHECK-NEXT: ret <2 x i32> [[CTLZ]] ; %or = or <2 x i32> %a, @@ -352,7 +352,7 @@ define <2 x i32> @cttz_poison_vec(<2 x i32> %Value) { define i32 @cttz_no_zero(i32 %a) { ; CHECK-LABEL: @cttz_no_zero( ; CHECK-NEXT: [[OR:%.*]] = or i32 [[A:%.*]], 8 -; CHECK-NEXT: [[CTTZ:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[OR]], i1 true), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[CTTZ:%.*]] = tail call range(i32 0, 4) i32 @llvm.cttz.i32(i32 [[OR]], i1 true) ; CHECK-NEXT: ret i32 [[CTTZ]] ; %or = or i32 %a, 8 @@ -363,7 +363,7 @@ define i32 @cttz_no_zero(i32 %a) { define <2 x i32> @cttz_no_zero_vec(<2 x i32> %a) { ; CHECK-LABEL: @cttz_no_zero_vec( ; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[A:%.*]], -; CHECK-NEXT: [[CTTZ:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true), !range [[RNG3]] +; CHECK-NEXT: [[CTTZ:%.*]] = tail call range(i32 0, 4) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[OR]], i1 true) ; CHECK-NEXT: ret <2 x i32> [[CTTZ]] ; %or = or <2 x i32> %a, @@ -373,7 +373,7 @@ define <2 x i32> @cttz_no_zero_vec(<2 x i32> %a) { define i32 @ctlz_select(i32 %Value) nounwind { ; CHECK-LABEL: @ctlz_select( -; CHECK-NEXT: [[CTLZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[VALUE:%.*]], i1 false), !range [[RNG4:![0-9]+]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[VALUE:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[CTLZ]] ; %tobool = icmp ne i32 %Value, 0 @@ -384,7 +384,7 @@ define i32 @ctlz_select(i32 %Value) nounwind { define <2 x i32> @ctlz_select_vec(<2 x i32> %Value) nounwind { ; CHECK-LABEL: @ctlz_select_vec( -; CHECK-NEXT: [[CTLZ:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false), !range [[RNG4]] +; CHECK-NEXT: [[CTLZ:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CTLZ]] ; %tobool = icmp ne <2 x i32> %Value, zeroinitializer @@ -395,7 +395,7 @@ define <2 x i32> @ctlz_select_vec(<2 x i32> %Value) nounwind { define i32 @cttz_select(i32 %Value) nounwind { ; CHECK-LABEL: @cttz_select( -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[VALUE:%.*]], i1 false), !range [[RNG4]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[VALUE:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[CTTZ]] ; %tobool = icmp ne i32 %Value, 0 @@ -406,7 +406,7 @@ define i32 @cttz_select(i32 %Value) nounwind { define <2 x i32> @cttz_select_vec(<2 x i32> %Value) nounwind { ; CHECK-LABEL: @cttz_select_vec( -; CHECK-NEXT: [[CTTZ:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false), !range [[RNG4]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[VALUE:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CTTZ]] ; %tobool = icmp ne <2 x i32> %Value, zeroinitializer diff --git a/llvm/test/Transforms/InstCombine/ispow2.ll b/llvm/test/Transforms/InstCombine/ispow2.ll index cc50c5cd1e6680a8353087ddfaa3c50f49c76808..a143b1347ccee5b85c2f366705f4b9b29218edab 100644 --- a/llvm/test/Transforms/InstCombine/ispow2.ll +++ b/llvm/test/Transforms/InstCombine/ispow2.ll @@ -3,7 +3,7 @@ define i1 @is_pow2or0_negate_op(i32 %x) { ; CHECK-LABEL: @is_pow2or0_negate_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -15,7 +15,7 @@ define i1 @is_pow2or0_negate_op(i32 %x) { define <2 x i1> @is_pow2or0_negate_op_vec(<2 x i32> %x) { ; CHECK-LABEL: @is_pow2or0_negate_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i32> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -27,7 +27,7 @@ define <2 x i1> @is_pow2or0_negate_op_vec(<2 x i32> %x) { define i1 @is_pow2or0_decrement_op(i8 %x) { ; CHECK-LABEL: @is_pow2or0_decrement_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i8 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -39,7 +39,7 @@ define i1 @is_pow2or0_decrement_op(i8 %x) { define <2 x i1> @is_pow2or0_decrement_op_vec(<2 x i8> %x) { ; CHECK-LABEL: @is_pow2or0_decrement_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -51,7 +51,7 @@ define <2 x i1> @is_pow2or0_decrement_op_vec(<2 x i8> %x) { define i1 @isnot_pow2or0_negate_op(i32 %x) { ; CHECK-LABEL: @isnot_pow2or0_negate_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -63,7 +63,7 @@ define i1 @isnot_pow2or0_negate_op(i32 %x) { define <2 x i1> @isnot_pow2or0_negate_op_vec(<2 x i32> %x) { ; CHECK-LABEL: @isnot_pow2or0_negate_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i32> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -75,7 +75,7 @@ define <2 x i1> @isnot_pow2or0_negate_op_vec(<2 x i32> %x) { define i1 @isnot_pow2or0_decrement_op(i8 %x) { ; CHECK-LABEL: @isnot_pow2or0_decrement_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -87,7 +87,7 @@ define i1 @isnot_pow2or0_decrement_op(i8 %x) { define <2 x i1> @isnot_pow2or0_decrement_op_vec(<2 x i8> %x) { ; CHECK-LABEL: @isnot_pow2or0_decrement_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[CMP]] ; @@ -100,7 +100,7 @@ define <2 x i1> @isnot_pow2or0_decrement_op_vec(<2 x i8> %x) { define i1 @is_pow2or0_negate_op_commute1(i32 %p) { ; CHECK-LABEL: @is_pow2or0_negate_op_commute1( ; CHECK-NEXT: [[X:%.*]] = srem i32 42, [[P:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 7) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -116,7 +116,7 @@ define i1 @is_pow2or0_negate_op_commute1(i32 %p) { define i1 @isnot_pow2or0_negate_op_commute2(i32 %p) { ; CHECK-LABEL: @isnot_pow2or0_negate_op_commute2( ; CHECK-NEXT: [[X:%.*]] = urem i32 42, [[P:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG2]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 7) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -130,7 +130,7 @@ define i1 @isnot_pow2or0_negate_op_commute2(i32 %p) { define i1 @isnot_pow2or0_negate_op_commute3(i32 %p) { ; CHECK-LABEL: @isnot_pow2or0_negate_op_commute3( ; CHECK-NEXT: [[X:%.*]] = urem i32 42, [[P:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG2]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 7) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -147,7 +147,7 @@ define i1 @is_pow2or0_negate_op_extra_use1(i32 %x) { ; CHECK-LABEL: @is_pow2or0_negate_op_extra_use1( ; CHECK-NEXT: [[NEG:%.*]] = sub i32 0, [[X:%.*]] ; CHECK-NEXT: call void @use(i32 [[NEG]]) -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -181,7 +181,7 @@ declare void @llvm.assume(i1) define i1 @is_pow2_ctpop(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -197,7 +197,7 @@ define i1 @is_pow2_non_zero_ult_2(i32 %x) { ; CHECK-LABEL: @is_pow2_non_zero_ult_2( ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X:%.*]], 0 ; CHECK-NEXT: call void @llvm.assume(i1 [[NOTZERO]]) -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -212,7 +212,7 @@ define i1 @is_pow2_non_zero_eq_1(i32 %x) { ; CHECK-LABEL: @is_pow2_non_zero_eq_1( ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X:%.*]], 0 ; CHECK-NEXT: call void @llvm.assume(i1 [[NOTZERO]]) -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -227,7 +227,7 @@ define i1 @is_pow2_non_zero_ugt_1(i32 %x) { ; CHECK-LABEL: @is_pow2_non_zero_ugt_1( ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X:%.*]], 0 ; CHECK-NEXT: call void @llvm.assume(i1 [[NOTZERO]]) -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -242,7 +242,7 @@ define i1 @is_pow2_non_zero_ne_1(i32 %x) { ; CHECK-LABEL: @is_pow2_non_zero_ne_1( ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X:%.*]], 0 ; CHECK-NEXT: call void @llvm.assume(i1 [[NOTZERO]]) -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -255,7 +255,7 @@ define i1 @is_pow2_non_zero_ne_1(i32 %x) { define i1 @is_pow2_ctpop_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -271,7 +271,7 @@ declare void @use_i1(i1) define i1 @is_pow2_ctpop_extra_uses(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_extra_uses( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 @@ -290,7 +290,7 @@ define i1 @is_pow2_ctpop_extra_uses(i32 %x) { define i1 @is_pow2_ctpop_extra_uses_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_extra_uses_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 @@ -311,7 +311,7 @@ define i1 @is_pow2_ctpop_extra_uses_logical(i32 %x) { define <2 x i1> @is_pow2_ctpop_commute_vec(<2 x i8> %x) { ; CHECK-LABEL: @is_pow2_ctpop_commute_vec( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[T0]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -326,7 +326,7 @@ define <2 x i1> @is_pow2_ctpop_commute_vec(<2 x i8> %x) { define i1 @is_pow2_ctpop_wrong_cmp_op1(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_cmp_op1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 3 ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = and i1 [[NOTZERO]], [[CMP]] @@ -341,7 +341,7 @@ define i1 @is_pow2_ctpop_wrong_cmp_op1(i32 %x) { define i1 @is_pow2_ctpop_wrong_cmp_op1_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_cmp_op1_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 3 ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false @@ -358,7 +358,7 @@ define i1 @is_pow2_ctpop_wrong_cmp_op1_logical(i32 %x) { define i1 @is_pow2_ctpop_wrong_cmp_op2(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_cmp_op2( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 1 ; CHECK-NEXT: [[R:%.*]] = and i1 [[NOTZERO]], [[CMP]] @@ -373,7 +373,7 @@ define i1 @is_pow2_ctpop_wrong_cmp_op2(i32 %x) { define i1 @is_pow2_ctpop_wrong_cmp_op2_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_cmp_op2_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false @@ -390,7 +390,7 @@ define i1 @is_pow2_ctpop_wrong_cmp_op2_logical(i32 %x) { define i1 @is_pow2_ctpop_wrong_pred1(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_pred1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -403,7 +403,7 @@ define i1 @is_pow2_ctpop_wrong_pred1(i32 %x) { define i1 @is_pow2_ctpop_wrong_pred1_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_pred1_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 2 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -418,7 +418,7 @@ define i1 @is_pow2_ctpop_wrong_pred1_logical(i32 %x) { define i1 @is_pow2_ctpop_wrong_pred2(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_pred2( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = and i1 [[CMP2]], [[CMP]] @@ -433,7 +433,7 @@ define i1 @is_pow2_ctpop_wrong_pred2(i32 %x) { define i1 @is_pow2_ctpop_wrong_pred2_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_ctpop_wrong_pred2_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP2]], i1 [[CMP]], i1 false @@ -450,7 +450,7 @@ define i1 @is_pow2_ctpop_wrong_pred2_logical(i32 %x) { define i1 @isnot_pow2_ctpop(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -463,7 +463,7 @@ define i1 @isnot_pow2_ctpop(i32 %x) { define i1 @isnot_pow2_ctpop_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -478,7 +478,7 @@ define i1 @isnot_pow2_ctpop_logical(i32 %x) { define i1 @isnot_pow2_ctpop_extra_uses(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_extra_uses( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 @@ -497,7 +497,7 @@ define i1 @isnot_pow2_ctpop_extra_uses(i32 %x) { define i1 @isnot_pow2_ctpop_extra_uses_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_extra_uses_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 @@ -518,7 +518,7 @@ define i1 @isnot_pow2_ctpop_extra_uses_logical(i32 %x) { define <2 x i1> @isnot_pow2_ctpop_commute_vec(<2 x i8> %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_commute_vec( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[T0]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -533,7 +533,7 @@ define <2 x i1> @isnot_pow2_ctpop_commute_vec(<2 x i8> %x) { define i1 @isnot_pow2_ctpop_wrong_cmp_op1(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_wrong_cmp_op1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 2 ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = or i1 [[ISZERO]], [[CMP]] @@ -548,7 +548,7 @@ define i1 @isnot_pow2_ctpop_wrong_cmp_op1(i32 %x) { define i1 @isnot_pow2_ctpop_wrong_cmp_op1_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_wrong_cmp_op1_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 2 ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] @@ -565,7 +565,7 @@ define i1 @isnot_pow2_ctpop_wrong_cmp_op1_logical(i32 %x) { define i1 @isnot_pow2_ctpop_wrong_cmp_op2(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_wrong_cmp_op2( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 1 ; CHECK-NEXT: [[R:%.*]] = or i1 [[ISZERO]], [[CMP]] @@ -580,7 +580,7 @@ define i1 @isnot_pow2_ctpop_wrong_cmp_op2(i32 %x) { define i1 @isnot_pow2_ctpop_wrong_cmp_op2_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_wrong_cmp_op2_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] @@ -597,7 +597,7 @@ define i1 @isnot_pow2_ctpop_wrong_cmp_op2_logical(i32 %x) { define i1 @isnot_pow2_ctpop_wrong_pred2(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_wrong_pred2( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = or i1 [[CMP2]], [[CMP]] @@ -612,7 +612,7 @@ define i1 @isnot_pow2_ctpop_wrong_pred2(i32 %x) { define i1 @isnot_pow2_ctpop_wrong_pred2_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2_ctpop_wrong_pred2_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: [[CMP2:%.*]] = icmp slt i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[CMP2]], i1 true, i1 [[CMP]] @@ -627,7 +627,7 @@ define i1 @isnot_pow2_ctpop_wrong_pred2_logical(i32 %x) { define i1 @is_pow2_negate_op(i32 %x) { ; CHECK-LABEL: @is_pow2_negate_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -641,7 +641,7 @@ define i1 @is_pow2_negate_op(i32 %x) { define i1 @is_pow2_negate_op_logical(i32 %x) { ; CHECK-LABEL: @is_pow2_negate_op_logical( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -655,7 +655,7 @@ define i1 @is_pow2_negate_op_logical(i32 %x) { define <2 x i1> @is_pow2_negate_op_vec(<2 x i32> %x) { ; CHECK-LABEL: @is_pow2_negate_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i32> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -669,7 +669,7 @@ define <2 x i1> @is_pow2_negate_op_vec(<2 x i32> %x) { define i1 @is_pow2_decrement_op(i8 %x) { ; CHECK-LABEL: @is_pow2_decrement_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -683,7 +683,7 @@ define i1 @is_pow2_decrement_op(i8 %x) { define i1 @is_pow2_decrement_op_logical(i8 %x) { ; CHECK-LABEL: @is_pow2_decrement_op_logical( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -697,7 +697,7 @@ define i1 @is_pow2_decrement_op_logical(i8 %x) { define <2 x i1> @is_pow2_decrement_op_vec(<2 x i8> %x) { ; CHECK-LABEL: @is_pow2_decrement_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -711,7 +711,7 @@ define <2 x i1> @is_pow2_decrement_op_vec(<2 x i8> %x) { define i1 @isnot_pow2_negate_op(i32 %x) { ; CHECK-LABEL: @isnot_pow2_negate_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -725,7 +725,7 @@ define i1 @isnot_pow2_negate_op(i32 %x) { define i1 @isnot_pow2_negate_op_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2_negate_op_logical( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -739,7 +739,7 @@ define i1 @isnot_pow2_negate_op_logical(i32 %x) { define <2 x i1> @isnot_pow2_negate_op_vec(<2 x i32> %x) { ; CHECK-LABEL: @isnot_pow2_negate_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i32> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -753,7 +753,7 @@ define <2 x i1> @isnot_pow2_negate_op_vec(<2 x i32> %x) { define i1 @isnot_pow2_decrement_op(i8 %x) { ; CHECK-LABEL: @isnot_pow2_decrement_op( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -767,7 +767,7 @@ define i1 @isnot_pow2_decrement_op(i8 %x) { define i1 @isnot_pow2_decrement_op_logical(i8 %x) { ; CHECK-LABEL: @isnot_pow2_decrement_op_logical( -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -781,7 +781,7 @@ define i1 @isnot_pow2_decrement_op_logical(i8 %x) { define <2 x i1> @isnot_pow2_decrement_op_vec(<2 x i8> %x) { ; CHECK-LABEL: @isnot_pow2_decrement_op_vec( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -797,7 +797,7 @@ define <2 x i1> @isnot_pow2_decrement_op_vec(<2 x i8> %x) { define i1 @is_pow2or0_ctpop(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: ret i1 [[R]] ; @@ -810,7 +810,7 @@ define i1 @is_pow2or0_ctpop(i32 %x) { define i1 @is_pow2or0_ctpop_swap_cmp(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_swap_cmp( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: ret i1 [[R]] ; @@ -823,7 +823,7 @@ define i1 @is_pow2or0_ctpop_swap_cmp(i32 %x) { define i1 @is_pow2or0_ctpop_logical(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i32 [[T0]], 2 ; CHECK-NEXT: ret i1 [[R]] ; @@ -836,7 +836,7 @@ define i1 @is_pow2or0_ctpop_logical(i32 %x) { define <2 x i1> @is_pow2or0_ctpop_commute_vec(<2 x i8> %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_commute_vec( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult <2 x i8> [[T0]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -851,7 +851,7 @@ define <2 x i1> @is_pow2or0_ctpop_commute_vec(<2 x i8> %x) { define i1 @is_pow2or0_ctpop_extra_uses(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_extra_uses( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: call void @use(i32 [[T0]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 1 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) @@ -872,7 +872,7 @@ define i1 @is_pow2or0_ctpop_extra_uses(i32 %x) { define i1 @is_pow2or0_ctpop_logical_extra_uses(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_logical_extra_uses( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: call void @use(i32 [[T0]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 1 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) @@ -895,7 +895,7 @@ define i1 @is_pow2or0_ctpop_logical_extra_uses(i32 %x) { define i1 @is_pow2or0_ctpop_wrong_cmp_op1(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_wrong_cmp_op1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 2 ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = or i1 [[ISZERO]], [[CMP]] @@ -910,7 +910,7 @@ define i1 @is_pow2or0_ctpop_wrong_cmp_op1(i32 %x) { define i1 @is_pow2or0_ctpop_wrong_cmp_op1_logical(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_wrong_cmp_op1_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 3 ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[ISZERO]], i1 true, i1 [[CMP]] @@ -925,7 +925,7 @@ define i1 @is_pow2or0_ctpop_wrong_cmp_op1_logical(i32 %x) { define <2 x i1> @is_pow2or0_ctpop_commute_vec_wrong_cmp_op1(<2 x i8> %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_commute_vec_wrong_cmp_op1( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[T0]], ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq <2 x i8> [[X]], zeroinitializer ; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[CMP]], [[ISZERO]] @@ -942,7 +942,7 @@ define <2 x i1> @is_pow2or0_ctpop_commute_vec_wrong_cmp_op1(<2 x i8> %x) { define i1 @is_pow2or0_ctpop_wrong_pred1(i32 %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_wrong_pred1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -977,7 +977,7 @@ define i1 @is_pow2or0_ctpop_wrong_pred2_logical(i32 %x) { define <2 x i1> @is_pow2or0_ctpop_commute_vec_wrong_pred3(<2 x i8> %x) { ; CHECK-LABEL: @is_pow2or0_ctpop_commute_vec_wrong_pred3( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i8> [[T0]], ; CHECK-NEXT: [[ISZERO:%.*]] = icmp eq <2 x i8> [[X]], zeroinitializer ; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[CMP]], [[ISZERO]] @@ -994,7 +994,7 @@ define <2 x i1> @is_pow2or0_ctpop_commute_vec_wrong_pred3(<2 x i8> %x) { define i1 @isnot_pow2nor0_ctpop(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1007,7 +1007,7 @@ define i1 @isnot_pow2nor0_ctpop(i32 %x) { define i1 @isnot_pow2nor0_ctpop_swap_cmp(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_swap_cmp( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1020,7 +1020,7 @@ define i1 @isnot_pow2nor0_ctpop_swap_cmp(i32 %x) { define i1 @isnot_pow2nor0_ctpop_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1033,7 +1033,7 @@ define i1 @isnot_pow2nor0_ctpop_logical(i32 %x) { define <2 x i1> @isnot_pow2nor0_ctpop_commute_vec(<2 x i8> %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_commute_vec( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i8> [[T0]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; @@ -1048,7 +1048,7 @@ define <2 x i1> @isnot_pow2nor0_ctpop_commute_vec(<2 x i8> %x) { define i1 @isnot_pow2nor0_ctpop_extra_uses(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_extra_uses( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: call void @use(i32 [[T0]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[T0]], 1 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) @@ -1069,7 +1069,7 @@ define i1 @isnot_pow2nor0_ctpop_extra_uses(i32 %x) { define i1 @isnot_pow2nor0_ctpop_logical_extra_uses(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_logical_extra_uses( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: call void @use(i32 [[T0]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[T0]], 1 ; CHECK-NEXT: call void @use_i1(i1 [[CMP]]) @@ -1092,7 +1092,7 @@ define i1 @isnot_pow2nor0_ctpop_logical_extra_uses(i32 %x) { define i1 @isnot_pow2nor0_ctpop_wrong_cmp_op1(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_wrong_cmp_op1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[T0]], 4 ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = and i1 [[NOTZERO]], [[CMP]] @@ -1107,7 +1107,7 @@ define i1 @isnot_pow2nor0_ctpop_wrong_cmp_op1(i32 %x) { define i1 @isnot_pow2nor0_ctpop_wrong_cmp_op1_logical(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_wrong_cmp_op1_logical( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne i32 [[T0]], 5 ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne i32 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[NOTZERO]], i1 [[CMP]], i1 false @@ -1122,7 +1122,7 @@ define i1 @isnot_pow2nor0_ctpop_wrong_cmp_op1_logical(i32 %x) { define <2 x i1> @isnot_pow2nor0_ctpop_commute_vec_wrong_cmp_op1(<2 x i8> %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_commute_vec_wrong_cmp_op1( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i8> [[T0]], ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne <2 x i8> [[X]], zeroinitializer ; CHECK-NEXT: [[R:%.*]] = and <2 x i1> [[CMP]], [[NOTZERO]] @@ -1139,7 +1139,7 @@ define <2 x i1> @isnot_pow2nor0_ctpop_commute_vec_wrong_cmp_op1(<2 x i8> %x) { define i1 @isnot_pow2nor0_ctpop_wrong_pred1(i32 %x) { ; CHECK-LABEL: @isnot_pow2nor0_ctpop_wrong_pred1( -; CHECK-NEXT: [[T0:%.*]] = tail call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[T0]], 1 ; CHECK-NEXT: ret i1 [[CMP]] ; @@ -1174,7 +1174,7 @@ define i1 @isnot_pow2nor0_ctpop_wrong_pred2_logical(i32 %x) { define <2 x i1> @isnot_pow2nor0_wrong_pred3_ctpop_commute_vec(<2 x i8> %x) { ; CHECK-LABEL: @isnot_pow2nor0_wrong_pred3_ctpop_commute_vec( -; CHECK-NEXT: [[T0:%.*]] = tail call <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]), !range [[RNG1]] +; CHECK-NEXT: [[T0:%.*]] = tail call range(i8 0, 9) <2 x i8> @llvm.ctpop.v2i8(<2 x i8> [[X:%.*]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ne <2 x i8> [[T0]], ; CHECK-NEXT: [[NOTZERO:%.*]] = icmp ne <2 x i8> [[X]], zeroinitializer ; CHECK-NEXT: [[R:%.*]] = or <2 x i1> [[CMP]], [[NOTZERO]] @@ -1217,7 +1217,7 @@ define i1 @blsmsk_is_p2_or_z(i32 %xx, i32 %yy) { define i1 @blsmsk_isnt_p2_or_z(i32 %x) { ; CHECK-LABEL: @blsmsk_isnt_p2_or_z( -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1230,7 +1230,7 @@ define i1 @blsmsk_isnt_p2_or_z(i32 %x) { define i1 @blsmsk_is_p2_or_z_fail(i32 %xx, i32 %yy) { ; CHECK-LABEL: @blsmsk_is_p2_or_z_fail( ; CHECK-NEXT: [[X:%.*]] = or i32 [[XX:%.*]], [[YY:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i32 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1315,7 +1315,7 @@ define i1 @blsmsk_is_p2_or_z_fail_bad_cmp(i32 %x, i32 %z) { define i1 @blsmsk_is_p2_or_z_ule_xy(i8 %xx, i8 %yy) { ; CHECK-LABEL: @blsmsk_is_p2_or_z_ule_xy( ; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], [[YY:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1346,7 +1346,7 @@ define i1 @blsmsk_is_p2_or_z_ule_yx_fail(i8 %xx, i8 %yy) { define i1 @blsmsk_is_p2_or_z_uge_yx(i8 %xx, i8 %yy) { ; CHECK-LABEL: @blsmsk_is_p2_or_z_uge_yx( ; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], [[YY:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ult i8 [[TMP1]], 2 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1376,7 +1376,7 @@ define i1 @blsmsk_is_p2_or_z_uge_xy_fail(i8 %xx, i8 %yy) { define i1 @blsmsk_isnt_p2_or_z_ugt_xy(i8 %xx, i8 %yy) { ; CHECK-LABEL: @blsmsk_isnt_p2_or_z_ugt_xy( ; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], [[YY:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1407,7 +1407,7 @@ define i1 @blsmsk_isnt_p2_or_z_ugt_yx_fail(i8 %xx, i8 %yy) { define i1 @blsmsk_isnt_p2_or_z_ult_yx(i8 %xx, i8 %yy) { ; CHECK-LABEL: @blsmsk_isnt_p2_or_z_ult_yx( ; CHECK-NEXT: [[X:%.*]] = or i8 [[XX:%.*]], [[YY:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = call i8 @llvm.ctpop.i8(i8 [[X]]), !range [[RNG1]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt i8 [[TMP1]], 1 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1450,7 +1450,7 @@ define i1 @is_pow2_nz_known_bits(i32 %xin) { define i1 @is_pow2_nz_known_bits_fail_multiuse(i32 %xin) { ; CHECK-LABEL: @is_pow2_nz_known_bits_fail_multiuse( ; CHECK-NEXT: [[X:%.*]] = or i32 [[XIN:%.*]], 64 -; CHECK-NEXT: [[CNT:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: call void @use.i32(i32 [[CNT]]) ; CHECK-NEXT: [[R:%.*]] = icmp eq i32 [[CNT]], 1 ; CHECK-NEXT: ret i1 [[R]] @@ -1476,7 +1476,7 @@ define i1 @not_pow2_nz_known_bits(i32 %xin) { define i1 @not_pow2_nz_known_bits_fail_not_p2_test(i32 %xin) { ; CHECK-LABEL: @not_pow2_nz_known_bits_fail_not_p2_test( ; CHECK-NEXT: [[X:%.*]] = or i32 [[XIN:%.*]], 1 -; CHECK-NEXT: [[CNT:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X]]), !range [[RNG3]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 1, 33) i32 @llvm.ctpop.i32(i32 [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ne i32 [[CNT]], 2 ; CHECK-NEXT: ret i1 [[R]] ; @@ -1513,7 +1513,7 @@ define <2 x i1> @not_pow2_or_z_known_bits(<2 x i32> %xin) { define <2 x i1> @not_pow2_or_z_known_bits_fail_wrong_cmp(<2 x i32> %xin) { ; CHECK-LABEL: @not_pow2_or_z_known_bits_fail_wrong_cmp( ; CHECK-NEXT: [[X:%.*]] = or <2 x i32> [[XIN:%.*]], -; CHECK-NEXT: [[CNT:%.*]] = call <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X]]), !range [[RNG3]] +; CHECK-NEXT: [[CNT:%.*]] = call range(i32 1, 33) <2 x i32> @llvm.ctpop.v2i32(<2 x i32> [[X]]) ; CHECK-NEXT: [[R:%.*]] = icmp ugt <2 x i32> [[CNT]], ; CHECK-NEXT: ret <2 x i1> [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/known-non-zero.ll b/llvm/test/Transforms/InstCombine/known-non-zero.ll index f1c757cafefb0fd54a269440662f8318a8f11f1a..b77c04eb81475a4534ae7a87b041a544ad995adf 100644 --- a/llvm/test/Transforms/InstCombine/known-non-zero.ll +++ b/llvm/test/Transforms/InstCombine/known-non-zero.ll @@ -13,7 +13,7 @@ define i32 @test0(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[X:%.*]], 0 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.cttz.i64(i64 [[X]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X]], i1 true) ; CHECK-NEXT: [[CTZ32:%.*]] = trunc nuw nsw i64 [[CTZ]] to i32 ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: @@ -40,7 +40,7 @@ define i32 @test1(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp eq i64 [[X:%.*]], 0 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 true) ; CHECK-NEXT: [[CTZ32:%.*]] = trunc nuw nsw i64 [[CTZ]] to i32 ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: @@ -69,7 +69,7 @@ define <8 x i64> @test2(<8 x i64> %x) { ; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[B]], 0 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call <8 x i64> @llvm.cttz.v8i64(<8 x i64> [[X]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) <8 x i64> @llvm.cttz.v8i64(<8 x i64> [[X]], i1 false) ; CHECK-NEXT: br label [[EXIT]] ; CHECK: exit: ; CHECK-NEXT: [[RES:%.*]] = phi <8 x i64> [ [[CTZ]], [[NON_ZERO]] ], [ zeroinitializer, [[START:%.*]] ] @@ -140,7 +140,7 @@ define i64 @test_sgt_zero(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], 0 ; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 1, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 true) ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -185,7 +185,7 @@ define i64 @test_slt_ten(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], 10 ; CHECK-NEXT: br i1 [[C]], label [[MAYBE_ZERO:%.*]], label [[EXIT:%.*]] ; CHECK: maybe_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 false) ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -208,7 +208,7 @@ define i64 @test_ugt_unknown(i64 %x, i64 %y) { ; CHECK-NEXT: [[C:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: br i1 [[C]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 true) ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -231,7 +231,7 @@ define i64 @test_sle_zero(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp slt i64 [[X:%.*]], 1 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[NON_ZERO:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 1, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 true) ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -276,7 +276,7 @@ define i64 @test_sge_ten(i64 %x) { ; CHECK-NEXT: [[C:%.*]] = icmp sgt i64 [[X:%.*]], 9 ; CHECK-NEXT: br i1 [[C]], label [[EXIT:%.*]], label [[MAYBE_ZERO:%.*]] ; CHECK: maybe_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 false) ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 @@ -299,7 +299,7 @@ define i64 @test_ule_unknown(i64 %x, i64 %y) { ; CHECK-NEXT: [[C_NOT:%.*]] = icmp ugt i64 [[X:%.*]], [[Y:%.*]] ; CHECK-NEXT: br i1 [[C_NOT]], label [[NON_ZERO:%.*]], label [[EXIT:%.*]] ; CHECK: non_zero: -; CHECK-NEXT: [[CTZ:%.*]] = call i64 @llvm.ctlz.i64(i64 [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTZ:%.*]] = call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X]], i1 true) ; CHECK-NEXT: ret i64 [[CTZ]] ; CHECK: exit: ; CHECK-NEXT: ret i64 -1 diff --git a/llvm/test/Transforms/InstCombine/known-phi-recurse.ll b/llvm/test/Transforms/InstCombine/known-phi-recurse.ll index d33e08ffaf9b77d40d2534714d768f32fd6c636a..c2007d16ae93be0e18da35caacb00385f585d7a6 100644 --- a/llvm/test/Transforms/InstCombine/known-phi-recurse.ll +++ b/llvm/test/Transforms/InstCombine/known-phi-recurse.ll @@ -16,7 +16,7 @@ define i32 @single_entry_phi(i64 %x, i1 %c) { ; CHECK: body: ; CHECK-NEXT: br i1 [[C:%.*]], label [[END:%.*]], label [[BODY]] ; CHECK: end: -; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[Y:%.*]] = call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 [[X:%.*]]) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: ret i32 [[TRUNC]] ; @@ -36,7 +36,7 @@ end: define i32 @two_entry_phi_with_constant(i64 %x, i1 %c) { ; CHECK-LABEL: @two_entry_phi_with_constant( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[Y:%.*]] = call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 [[X:%.*]]) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: br i1 [[C:%.*]], label [[END:%.*]], label [[BODY:%.*]] ; CHECK: body: @@ -61,11 +61,11 @@ end: define i32 @two_entry_phi_non_constant(i64 %x, i64 %x2, i1 %c) { ; CHECK-LABEL: @two_entry_phi_non_constant( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[Y:%.*]] = call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 [[X:%.*]]) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: br i1 [[C:%.*]], label [[END:%.*]], label [[BODY:%.*]] ; CHECK: body: -; CHECK-NEXT: [[Y2:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X2:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[Y2:%.*]] = call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 [[X2:%.*]]) ; CHECK-NEXT: [[TRUNC2:%.*]] = trunc nuw nsw i64 [[Y2]] to i32 ; CHECK-NEXT: br label [[END]] ; CHECK: end: @@ -90,7 +90,7 @@ end: define i32 @neg_many_branches(i64 %x) { ; CHECK-LABEL: @neg_many_branches( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[Y:%.*]] = call i64 @llvm.ctpop.i64(i64 [[X:%.*]]), !range [[RNG0]] +; CHECK-NEXT: [[Y:%.*]] = call range(i64 0, 65) i64 @llvm.ctpop.i64(i64 [[X:%.*]]) ; CHECK-NEXT: [[TRUNC:%.*]] = trunc nuw nsw i64 [[Y]] to i32 ; CHECK-NEXT: switch i32 [[TRUNC]], label [[END:%.*]] [ ; CHECK-NEXT: i32 1, label [[ONE:%.*]] diff --git a/llvm/test/Transforms/InstCombine/loadstore-alignment.ll b/llvm/test/Transforms/InstCombine/loadstore-alignment.ll index 0fc82a1d5343699cacb8c600a86a144e515f72af..1027468d6715e8096e4d3031d77f74cc6fd4287c 100644 --- a/llvm/test/Transforms/InstCombine/loadstore-alignment.ll +++ b/llvm/test/Transforms/InstCombine/loadstore-alignment.ll @@ -9,24 +9,24 @@ target datalayout = "E-p:64:64:64-p1:64:64:64-p2:32:32:32-a0:0:8-f32:32:32-f64:6 define <2 x i64> @static_hem() { ; CHECK-LABEL: @static_hem( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr getelementptr (<2 x i64>, ptr @x, i64 7), align 1 -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr getelementptr (<2 x i64>, ptr @x, i64 7), align 1 +; CHECK-NEXT: ret <2 x i64> [[L]] ; %t = getelementptr <2 x i64>, ptr @x, i32 7 - %tmp1 = load <2 x i64>, ptr %t, align 1 - ret <2 x i64> %tmp1 + %l = load <2 x i64>, ptr %t, align 1 + ret <2 x i64> %l } define <2 x i64> @hem(i32 %i) { ; CHECK-LABEL: @hem( ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I:%.*]] to i64 ; CHECK-NEXT: [[T:%.*]] = getelementptr <2 x i64>, ptr @x, i64 [[TMP1]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[T]], align 1 -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr [[T]], align 1 +; CHECK-NEXT: ret <2 x i64> [[L]] ; %t = getelementptr <2 x i64>, ptr @x, i32 %i - %tmp1 = load <2 x i64>, ptr %t, align 1 - ret <2 x i64> %tmp1 + %l = load <2 x i64>, ptr %t, align 1 + ret <2 x i64> %l } define <2 x i64> @hem_2d(i32 %i, i32 %j) { @@ -34,34 +34,34 @@ define <2 x i64> @hem_2d(i32 %i, i32 %j) { ; CHECK-NEXT: [[TMP1:%.*]] = sext i32 [[I:%.*]] to i64 ; CHECK-NEXT: [[TMP2:%.*]] = sext i32 [[J:%.*]] to i64 ; CHECK-NEXT: [[T:%.*]] = getelementptr [13 x <2 x i64>], ptr @xx, i64 [[TMP1]], i64 [[TMP2]] -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[T]], align 1 -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr [[T]], align 1 +; CHECK-NEXT: ret <2 x i64> [[L]] ; %t = getelementptr [13 x <2 x i64>], ptr @xx, i32 %i, i32 %j - %tmp1 = load <2 x i64>, ptr %t, align 1 - ret <2 x i64> %tmp1 + %l = load <2 x i64>, ptr %t, align 1 + ret <2 x i64> %l } define <2 x i64> @foo() { ; CHECK-LABEL: @foo( -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @x, align 1 -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr @x, align 1 +; CHECK-NEXT: ret <2 x i64> [[L]] ; - %tmp1 = load <2 x i64>, ptr @x, align 1 - ret <2 x i64> %tmp1 + %l = load <2 x i64>, ptr @x, align 1 + ret <2 x i64> %l } define <2 x i64> @bar() { ; CHECK-LABEL: @bar( ; CHECK-NEXT: [[T:%.*]] = alloca <2 x i64>, align 16 ; CHECK-NEXT: call void @kip(ptr nonnull [[T]]) -; CHECK-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr [[T]], align 1 -; CHECK-NEXT: ret <2 x i64> [[TMP1]] +; CHECK-NEXT: [[L:%.*]] = load <2 x i64>, ptr [[T]], align 1 +; CHECK-NEXT: ret <2 x i64> [[L]] ; %t = alloca <2 x i64> call void @kip(ptr %t) - %tmp1 = load <2 x i64>, ptr %t, align 1 - ret <2 x i64> %tmp1 + %l = load <2 x i64>, ptr %t, align 1 + ret <2 x i64> %l } define void @static_hem_store(<2 x i64> %y) { diff --git a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll index aeca0cd2924ea5c39b524e0dd27579db56c187b8..e9ff34735f1cf1194ce6ce90f63d86d51e3e478e 100644 --- a/llvm/test/Transforms/InstCombine/memcpy-from-global.ll +++ b/llvm/test/Transforms/InstCombine/memcpy-from-global.ll @@ -6,60 +6,60 @@ target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f3 define float @test1(i32 %hash, float %x, float %y, float %z, float %w) { ; CHECK-LABEL: @test1( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[TMP3:%.*]] = shl i32 [[HASH:%.*]], 2 -; CHECK-NEXT: [[TMP5:%.*]] = and i32 [[TMP3]], 124 -; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[TMP5]] to i64 -; CHECK-NEXT: [[TMP753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]] -; CHECK-NEXT: [[TMP9:%.*]] = load float, ptr [[TMP753]], align 4 -; CHECK-NEXT: [[TMP11:%.*]] = fmul float [[TMP9]], [[X:%.*]] -; CHECK-NEXT: [[TMP13:%.*]] = fadd float [[TMP11]], 0.000000e+00 -; CHECK-NEXT: [[TMP17_SUM52:%.*]] = or disjoint i32 [[TMP5]], 1 -; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[TMP17_SUM52]] to i64 -; CHECK-NEXT: [[TMP1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]] -; CHECK-NEXT: [[TMP19:%.*]] = load float, ptr [[TMP1851]], align 4 -; CHECK-NEXT: [[TMP21:%.*]] = fmul float [[TMP19]], [[Y:%.*]] -; CHECK-NEXT: [[TMP23:%.*]] = fadd float [[TMP21]], [[TMP13]] -; CHECK-NEXT: [[TMP27_SUM50:%.*]] = or disjoint i32 [[TMP5]], 2 -; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[TMP27_SUM50]] to i64 -; CHECK-NEXT: [[TMP2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]] -; CHECK-NEXT: [[TMP29:%.*]] = load float, ptr [[TMP2849]], align 4 -; CHECK-NEXT: [[TMP31:%.*]] = fmul float [[TMP29]], [[Z:%.*]] -; CHECK-NEXT: [[TMP33:%.*]] = fadd float [[TMP31]], [[TMP23]] -; CHECK-NEXT: [[TMP37_SUM48:%.*]] = or disjoint i32 [[TMP5]], 3 -; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[TMP37_SUM48]] to i64 -; CHECK-NEXT: [[TMP3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]] -; CHECK-NEXT: [[TMP39:%.*]] = load float, ptr [[TMP3847]], align 4 -; CHECK-NEXT: [[TMP41:%.*]] = fmul float [[TMP39]], [[W:%.*]] -; CHECK-NEXT: [[TMP43:%.*]] = fadd float [[TMP41]], [[TMP33]] -; CHECK-NEXT: ret float [[TMP43]] +; CHECK-NEXT: [[T3:%.*]] = shl i32 [[HASH:%.*]], 2 +; CHECK-NEXT: [[T5:%.*]] = and i32 [[T3]], 124 +; CHECK-NEXT: [[TMP0:%.*]] = zext nneg i32 [[T5]] to i64 +; CHECK-NEXT: [[T753:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP0]] +; CHECK-NEXT: [[T9:%.*]] = load float, ptr [[T753]], align 4 +; CHECK-NEXT: [[T11:%.*]] = fmul float [[T9]], [[X:%.*]] +; CHECK-NEXT: [[T13:%.*]] = fadd float [[T11]], 0.000000e+00 +; CHECK-NEXT: [[T17_SUM52:%.*]] = or disjoint i32 [[T5]], 1 +; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[T17_SUM52]] to i64 +; CHECK-NEXT: [[T1851:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP1]] +; CHECK-NEXT: [[T19:%.*]] = load float, ptr [[T1851]], align 4 +; CHECK-NEXT: [[T21:%.*]] = fmul float [[T19]], [[Y:%.*]] +; CHECK-NEXT: [[T23:%.*]] = fadd float [[T21]], [[T13]] +; CHECK-NEXT: [[T27_SUM50:%.*]] = or disjoint i32 [[T5]], 2 +; CHECK-NEXT: [[TMP2:%.*]] = zext nneg i32 [[T27_SUM50]] to i64 +; CHECK-NEXT: [[T2849:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP2]] +; CHECK-NEXT: [[T29:%.*]] = load float, ptr [[T2849]], align 4 +; CHECK-NEXT: [[T31:%.*]] = fmul float [[T29]], [[Z:%.*]] +; CHECK-NEXT: [[T33:%.*]] = fadd float [[T31]], [[T23]] +; CHECK-NEXT: [[T37_SUM48:%.*]] = or disjoint i32 [[T5]], 3 +; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i32 [[T37_SUM48]] to i64 +; CHECK-NEXT: [[T3847:%.*]] = getelementptr [128 x float], ptr @C.0.1248, i64 0, i64 [[TMP3]] +; CHECK-NEXT: [[T39:%.*]] = load float, ptr [[T3847]], align 4 +; CHECK-NEXT: [[T41:%.*]] = fmul float [[T39]], [[W:%.*]] +; CHECK-NEXT: [[T43:%.*]] = fadd float [[T41]], [[T33]] +; CHECK-NEXT: ret float [[T43]] ; entry: - %lookupTable = alloca [128 x float], align 16 ; [#uses=5] + %lookupTable = alloca [128 x float], align 16 call void @llvm.memcpy.p0.p0.i64(ptr align 16 %lookupTable, ptr align 16 @C.0.1248, i64 512, i1 false) - %tmp3 = shl i32 %hash, 2 ; [#uses=1] - %tmp5 = and i32 %tmp3, 124 ; [#uses=4] - %tmp753 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp5 ; [#uses=1] - %tmp9 = load float, ptr %tmp753 ; [#uses=1] - %tmp11 = fmul float %tmp9, %x ; [#uses=1] - %tmp13 = fadd float %tmp11, 0.000000e+00 ; [#uses=1] - %tmp17.sum52 = or i32 %tmp5, 1 ; [#uses=1] - %tmp1851 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp17.sum52 ; [#uses=1] - %tmp19 = load float, ptr %tmp1851 ; [#uses=1] - %tmp21 = fmul float %tmp19, %y ; [#uses=1] - %tmp23 = fadd float %tmp21, %tmp13 ; [#uses=1] - %tmp27.sum50 = or i32 %tmp5, 2 ; [#uses=1] - %tmp2849 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp27.sum50 ; [#uses=1] - %tmp29 = load float, ptr %tmp2849 ; [#uses=1] - %tmp31 = fmul float %tmp29, %z ; [#uses=1] - %tmp33 = fadd float %tmp31, %tmp23 ; [#uses=1] - %tmp37.sum48 = or i32 %tmp5, 3 ; [#uses=1] - %tmp3847 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %tmp37.sum48 ; [#uses=1] - %tmp39 = load float, ptr %tmp3847 ; [#uses=1] - %tmp41 = fmul float %tmp39, %w ; [#uses=1] - %tmp43 = fadd float %tmp41, %tmp33 ; [#uses=1] - ret float %tmp43 + %t3 = shl i32 %hash, 2 + %t5 = and i32 %t3, 124 + %t753 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t5 + %t9 = load float, ptr %t753 + %t11 = fmul float %t9, %x + %t13 = fadd float %t11, 0.000000e+00 + %t17.sum52 = or i32 %t5, 1 + %t1851 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t17.sum52 + %t19 = load float, ptr %t1851 + %t21 = fmul float %t19, %y + %t23 = fadd float %t21, %t13 + %t27.sum50 = or i32 %t5, 2 + %t2849 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t27.sum50 + %t29 = load float, ptr %t2849 + %t31 = fmul float %t29, %z + %t33 = fadd float %t31, %t23 + %t37.sum48 = or i32 %t5, 3 + %t3847 = getelementptr [128 x float], ptr %lookupTable, i32 0, i32 %t37.sum48 + %t39 = load float, ptr %t3847 + %t41 = fmul float %t39, %w + %t43 = fadd float %t41, %t33 + ret float %t43 } declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture, i64, i1) nounwind diff --git a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll index 866381ff2887f93b4fc7ce13f3488919519af865..9c5bf3cb5a41bf38c58ff59a68981a373400d6cd 100644 --- a/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll +++ b/llvm/test/Transforms/InstCombine/merging-multiple-stores-into-successor.ll @@ -105,11 +105,11 @@ define i32 @diff_types_diff_width_no_merge(i1 %cond, i32 %a, i64 %b) { ; CHECK-LABEL: @diff_types_diff_width_no_merge( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8 -; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]] -; CHECK: A: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF:%.*]], label [[ELSE:%.*]] +; CHECK: if: ; CHECK-NEXT: store i32 [[A:%.*]], ptr [[ALLOCA]], align 4 ; CHECK-NEXT: br label [[SINK:%.*]] -; CHECK: B: +; CHECK: else: ; CHECK-NEXT: store i64 [[B:%.*]], ptr [[ALLOCA]], align 4 ; CHECK-NEXT: br label [[SINK]] ; CHECK: sink: @@ -118,11 +118,11 @@ define i32 @diff_types_diff_width_no_merge(i1 %cond, i32 %a, i64 %b) { ; entry: %alloca = alloca i64 - br i1 %cond, label %A, label %B -A: + br i1 %cond, label %if, label %else +if: store i32 %a, ptr %alloca br label %sink -B: + else: store i64 %b, ptr %alloca br label %sink sink: @@ -134,11 +134,11 @@ define <4 x i32> @vec_no_merge(i1 %cond, <2 x i32> %a, <4 x i32> %b) { ; CHECK-LABEL: @vec_no_merge( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8 -; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]] -; CHECK: A: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF:%.*]], label [[ELSE:%.*]] +; CHECK: if: ; CHECK-NEXT: store <2 x i32> [[A:%.*]], ptr [[ALLOCA]], align 8 ; CHECK-NEXT: br label [[SINK:%.*]] -; CHECK: B: +; CHECK: else: ; CHECK-NEXT: store <4 x i32> [[B:%.*]], ptr [[ALLOCA]], align 16 ; CHECK-NEXT: br label [[SINK]] ; CHECK: sink: @@ -147,11 +147,11 @@ define <4 x i32> @vec_no_merge(i1 %cond, <2 x i32> %a, <4 x i32> %b) { ; entry: %alloca = alloca i64 - br i1 %cond, label %A, label %B -A: + br i1 %cond, label %if, label %else +if: store <2 x i32> %a, ptr %alloca br label %sink -B: +else: store <4 x i32> %b, ptr %alloca br label %sink sink: @@ -195,11 +195,11 @@ define %struct.tup @multi_elem_struct_no_merge(i1 %cond, %struct.tup %a, half %b ; CHECK-LABEL: @multi_elem_struct_no_merge( ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ALLOCA:%.*]] = alloca i64, align 8 -; CHECK-NEXT: br i1 [[COND:%.*]], label [[A:%.*]], label [[B:%.*]] -; CHECK: A: +; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF:%.*]], label [[ELSE:%.*]] +; CHECK: if: ; CHECK-NEXT: store [[STRUCT_TUP:%.*]] [[A:%.*]], ptr [[ALLOCA]], align 4 ; CHECK-NEXT: br label [[SINK:%.*]] -; CHECK: B: +; CHECK: else: ; CHECK-NEXT: store half [[B:%.*]], ptr [[ALLOCA]], align 2 ; CHECK-NEXT: br label [[SINK]] ; CHECK: sink: @@ -208,11 +208,11 @@ define %struct.tup @multi_elem_struct_no_merge(i1 %cond, %struct.tup %a, half %b ; entry: %alloca = alloca i64 - br i1 %cond, label %A, label %B -A: + br i1 %cond, label %if, label %else +if: store %struct.tup %a, ptr %alloca br label %sink -B: +else: store half %b, ptr %alloca br label %sink sink: diff --git a/llvm/test/Transforms/InstCombine/minmax-fold.ll b/llvm/test/Transforms/InstCombine/minmax-fold.ll index 8b47dc7a28079ec95e9dc1f2b9d7d9a0fc39cca6..3e870c695cf1a5ffa14d35c9d6a3772757d12353 100644 --- a/llvm/test/Transforms/InstCombine/minmax-fold.ll +++ b/llvm/test/Transforms/InstCombine/minmax-fold.ll @@ -1524,7 +1524,7 @@ define i32 @test_smin_umin4(i32 %x) { define i32 @test_umax_nonminmax(i32 %x) { ; CHECK-LABEL: @test_umax_nonminmax( -; CHECK-NEXT: [[Y:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[Y:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[UMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[Y]], i32 1) ; CHECK-NEXT: ret i32 [[UMAX]] ; diff --git a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll index b94be990199bf547845899efdadae9787788b9bf..ca586a71b42c8cd0bd9fb965365d40824f03e04c 100644 --- a/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll +++ b/llvm/test/Transforms/InstCombine/reduction-add-sext-zext-i1.ll @@ -4,7 +4,7 @@ define i1 @reduce_add_self(<8 x i1> %x) { ; CHECK-LABEL: @reduce_add_self( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: [[RES:%.*]] = trunc i8 [[TMP2]] to i1 ; CHECK-NEXT: ret i1 [[RES]] ; @@ -15,7 +15,7 @@ define i1 @reduce_add_self(<8 x i1> %x) { define i32 @reduce_add_sext(<4 x i1> %x) { ; CHECK-LABEL: @reduce_add_sext( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4 -; CHECK-NEXT: [[TMP2:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP1]]), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = zext nneg i4 [[TMP2]] to i32 ; CHECK-NEXT: [[RES:%.*]] = sub nsw i32 0, [[TMP3]] ; CHECK-NEXT: ret i32 [[RES]] @@ -28,7 +28,7 @@ define i32 @reduce_add_sext(<4 x i1> %x) { define i64 @reduce_add_zext(<8 x i1> %x) { ; CHECK-LABEL: @reduce_add_zext( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i64 ; CHECK-NEXT: ret i64 [[RES]] ; @@ -40,7 +40,7 @@ define i64 @reduce_add_zext(<8 x i1> %x) { define i16 @reduce_add_sext_same(<16 x i1> %x) { ; CHECK-LABEL: @reduce_add_sext_same( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16 -; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.ctpop.i16(i16 [[TMP1]]), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 [[TMP1]]) ; CHECK-NEXT: [[RES:%.*]] = sub nsw i16 0, [[TMP2]] ; CHECK-NEXT: ret i16 [[RES]] ; @@ -52,7 +52,7 @@ define i16 @reduce_add_sext_same(<16 x i1> %x) { define i8 @reduce_add_zext_long(<128 x i1> %x) { ; CHECK-LABEL: @reduce_add_zext_long( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 -; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i8 ; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]] ; CHECK-NEXT: ret i8 [[RES]] @@ -66,7 +66,7 @@ define i8 @reduce_add_zext_long(<128 x i1> %x) { define i8 @reduce_add_zext_long_external_use(<128 x i1> %x) { ; CHECK-LABEL: @reduce_add_zext_long_external_use( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 -; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = trunc nuw i128 [[TMP2]] to i8 ; CHECK-NEXT: [[RES:%.*]] = sub i8 0, [[TMP3]] ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <128 x i1> [[X]], i64 0 @@ -85,7 +85,7 @@ define i8 @reduce_add_zext_long_external_use(<128 x i1> %x) { define i64 @reduce_add_zext_external_use(<8 x i1> %x) { ; CHECK-LABEL: @reduce_add_zext_external_use( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP2]] to i64 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <8 x i1> [[X]], i64 0 ; CHECK-NEXT: [[EXT:%.*]] = zext i1 [[TMP3]] to i64 diff --git a/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll b/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll index 84ac9369b5ff066c0211ef34cf5dc7535bf258c9..b5baf8ec71a4893e75329547b41c017c21b23751 100644 --- a/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll +++ b/llvm/test/Transforms/InstCombine/reduction-xor-sext-zext-i1.ll @@ -4,7 +4,7 @@ define i1 @reduce_xor_self(<8 x i1> %x) { ; CHECK-LABEL: @reduce_xor_self( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: [[RES:%.*]] = trunc i8 [[TMP2]] to i1 ; CHECK-NEXT: ret i1 [[RES]] ; @@ -15,7 +15,7 @@ define i1 @reduce_xor_self(<8 x i1> %x) { define i32 @reduce_xor_sext(<4 x i1> %x) { ; CHECK-LABEL: @reduce_xor_sext( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <4 x i1> [[X:%.*]] to i4 -; CHECK-NEXT: [[TMP2:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP1]]), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = trunc i4 [[TMP2]] to i1 ; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP3]] to i32 ; CHECK-NEXT: ret i32 [[RES]] @@ -28,7 +28,7 @@ define i32 @reduce_xor_sext(<4 x i1> %x) { define i64 @reduce_xor_zext(<8 x i1> %x) { ; CHECK-LABEL: @reduce_xor_zext( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1 ; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP3]] to i64 ; CHECK-NEXT: ret i64 [[RES]] @@ -41,7 +41,7 @@ define i64 @reduce_xor_zext(<8 x i1> %x) { define i16 @reduce_xor_sext_same(<16 x i1> %x) { ; CHECK-LABEL: @reduce_xor_sext_same( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <16 x i1> [[X:%.*]] to i16 -; CHECK-NEXT: [[TMP2:%.*]] = call i16 @llvm.ctpop.i16(i16 [[TMP1]]), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i16 0, 17) i16 @llvm.ctpop.i16(i16 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = and i16 [[TMP2]], 1 ; CHECK-NEXT: [[SEXT:%.*]] = sub nsw i16 0, [[TMP3]] ; CHECK-NEXT: ret i16 [[SEXT]] @@ -54,7 +54,7 @@ define i16 @reduce_xor_sext_same(<16 x i1> %x) { define i8 @reduce_xor_zext_long(<128 x i1> %x) { ; CHECK-LABEL: @reduce_xor_zext_long( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 -; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i1 ; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP3]] to i8 ; CHECK-NEXT: ret i8 [[RES]] @@ -68,7 +68,7 @@ define i8 @reduce_xor_zext_long(<128 x i1> %x) { define i8 @reduce_xor_zext_long_external_use(<128 x i1> %x) { ; CHECK-LABEL: @reduce_xor_zext_long_external_use( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <128 x i1> [[X:%.*]] to i128 -; CHECK-NEXT: [[TMP2:%.*]] = call i128 @llvm.ctpop.i128(i128 [[TMP1]]), !range [[RNG3]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i128 0, 129) i128 @llvm.ctpop.i128(i128 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = trunc i128 [[TMP2]] to i1 ; CHECK-NEXT: [[RES:%.*]] = sext i1 [[TMP3]] to i8 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <128 x i1> [[X]], i64 0 @@ -87,7 +87,7 @@ define i8 @reduce_xor_zext_long_external_use(<128 x i1> %x) { define i64 @reduce_xor_zext_external_use(<8 x i1> %x) { ; CHECK-LABEL: @reduce_xor_zext_external_use( ; CHECK-NEXT: [[TMP1:%.*]] = bitcast <8 x i1> [[X:%.*]] to i8 -; CHECK-NEXT: [[TMP2:%.*]] = call i8 @llvm.ctpop.i8(i8 [[TMP1]]), !range [[RNG0]] +; CHECK-NEXT: [[TMP2:%.*]] = call range(i8 0, 9) i8 @llvm.ctpop.i8(i8 [[TMP1]]) ; CHECK-NEXT: [[TMP3:%.*]] = and i8 [[TMP2]], 1 ; CHECK-NEXT: [[RES:%.*]] = zext nneg i8 [[TMP3]] to i64 ; CHECK-NEXT: [[TMP4:%.*]] = extractelement <8 x i1> [[X]], i64 0 diff --git a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll index 69896f855f5f1615c009e44e7bb739dc8912e502..3d5f2c209edf3b540b81532ff8ef8f77a6f2f64a 100644 --- a/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll +++ b/llvm/test/Transforms/InstCombine/select-cmp-cttz-ctlz.ll @@ -7,7 +7,7 @@ define i16 @test1(i16 %x) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i16 [[CT]] ; %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true) @@ -18,7 +18,7 @@ define i16 @test1(i16 %x) { define i32 @test2(i32 %x) { ; CHECK-LABEL: @test2( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[CT]] ; %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) @@ -29,7 +29,7 @@ define i32 @test2(i32 %x) { define i64 @test3(i64 %x) { ; CHECK-LABEL: @test3( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i64 [[CT]] ; %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true) @@ -40,7 +40,7 @@ define i64 @test3(i64 %x) { define i16 @test4(i16 %x) { ; CHECK-LABEL: @test4( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i16 [[CT]] ; %ct = tail call i16 @llvm.ctlz.i16(i16 %x, i1 true) @@ -51,7 +51,7 @@ define i16 @test4(i16 %x) { define i32 @test5(i32 %x) { ; CHECK-LABEL: @test5( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[CT]] ; %ct = tail call i32 @llvm.ctlz.i32(i32 %x, i1 true) @@ -62,7 +62,7 @@ define i32 @test5(i32 %x) { define i64 @test6(i64 %x) { ; CHECK-LABEL: @test6( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i64 [[CT]] ; %ct = tail call i64 @llvm.ctlz.i64(i64 %x, i1 true) @@ -73,7 +73,7 @@ define i64 @test6(i64 %x) { define i16 @test1b(i16 %x) { ; CHECK-LABEL: @test1b( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i16 [[CT]] ; %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true) @@ -84,7 +84,7 @@ define i16 @test1b(i16 %x) { define i32 @test2b(i32 %x) { ; CHECK-LABEL: @test2b( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[CT]] ; %ct = tail call i32 @llvm.cttz.i32(i32 %x, i1 true) @@ -95,7 +95,7 @@ define i32 @test2b(i32 %x) { define i64 @test3b(i64 %x) { ; CHECK-LABEL: @test3b( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i64 [[CT]] ; %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true) @@ -106,7 +106,7 @@ define i64 @test3b(i64 %x) { define i16 @test4b(i16 %x) { ; CHECK-LABEL: @test4b( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i16 [[CT]] ; %ct = tail call i16 @llvm.cttz.i16(i16 %x, i1 true) @@ -118,7 +118,7 @@ define i16 @test4b(i16 %x) { define i32 @test5b(i32 %x) { ; CHECK-LABEL: @test5b( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[CT]] ; entry: @@ -130,7 +130,7 @@ entry: define i64 @test6b(i64 %x) { ; CHECK-LABEL: @test6b( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i64 [[CT]] ; %ct = tail call i64 @llvm.cttz.i64(i64 %x, i1 true) @@ -141,7 +141,7 @@ define i64 @test6b(i64 %x) { define i32 @test1c(i16 %x) { ; CHECK-LABEL: @test1c( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST2:%.*]] = zext nneg i16 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST2]] ; @@ -154,7 +154,7 @@ define i32 @test1c(i16 %x) { define i64 @test2c(i16 %x) { ; CHECK-LABEL: @test2c( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.cttz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = zext nneg i16 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CONV]] ; @@ -167,7 +167,7 @@ define i64 @test2c(i16 %x) { define i64 @test3c(i32 %x) { ; CHECK-LABEL: @test3c( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CONV]] ; @@ -180,7 +180,7 @@ define i64 @test3c(i32 %x) { define i32 @test4c(i16 %x) { ; CHECK-LABEL: @test4c( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = zext nneg i16 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; @@ -193,7 +193,7 @@ define i32 @test4c(i16 %x) { define i64 @test5c(i16 %x) { ; CHECK-LABEL: @test5c( -; CHECK-NEXT: [[CT:%.*]] = tail call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = zext nneg i16 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CAST]] ; @@ -206,7 +206,7 @@ define i64 @test5c(i16 %x) { define i64 @test6c(i32 %x) { ; CHECK-LABEL: @test6c( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CAST]] ; @@ -219,7 +219,7 @@ define i64 @test6c(i32 %x) { define i16 @test1d(i64 %x) { ; CHECK-LABEL: @test1d( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CONV]] ; @@ -232,7 +232,7 @@ define i16 @test1d(i64 %x) { define i32 @test2d(i64 %x) { ; CHECK-LABEL: @test2d( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; @@ -245,7 +245,7 @@ define i32 @test2d(i64 %x) { define i16 @test3d(i32 %x) { ; CHECK-LABEL: @test3d( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i32 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CAST]] ; @@ -258,7 +258,7 @@ define i16 @test3d(i32 %x) { define i16 @test4d(i64 %x) { ; CHECK-LABEL: @test4d( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CAST]] ; @@ -271,7 +271,7 @@ define i16 @test4d(i64 %x) { define i32 @test5d(i64 %x) { ; CHECK-LABEL: @test5d( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; @@ -287,7 +287,7 @@ define i32 @test5d(i64 %x) { define i32 @not_op_ctlz(i64 %x) { ; CHECK-LABEL: @not_op_ctlz( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -1 -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[N]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[N]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; @@ -302,7 +302,7 @@ define i32 @not_op_ctlz(i64 %x) { define i32 @not_op_cttz(i64 %x) { ; CHECK-LABEL: @not_op_cttz( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -1 -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[N]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[N]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: ret i32 [[CAST]] ; @@ -319,7 +319,7 @@ define i32 @not_op_cttz(i64 %x) { define i32 @not_op_ctlz_wrong_xor_op1(i64 %x) { ; CHECK-LABEL: @not_op_ctlz_wrong_xor_op1( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -2 -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[N]], i1 true), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[N]], i1 true) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X]], -1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]] @@ -338,7 +338,7 @@ define i32 @not_op_ctlz_wrong_xor_op1(i64 %x) { define i32 @not_op_ctlz_wrong_xor_op0(i64 %x, i64 %y) { ; CHECK-LABEL: @not_op_ctlz_wrong_xor_op0( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[Y:%.*]], -1 -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[N]], i1 true), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[N]], i1 true) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X:%.*]], -1 ; CHECK-NEXT: [[R:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]] @@ -357,7 +357,7 @@ define i32 @not_op_ctlz_wrong_xor_op0(i64 %x, i64 %y) { define i32 @not_op_cttz_wrong_cmp(i64 %x) { ; CHECK-LABEL: @not_op_cttz_wrong_cmp( ; CHECK-NEXT: [[N:%.*]] = xor i64 [[X:%.*]], -1 -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[N]], i1 true), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[N]], i1 true) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i64 [[CT]] to i32 ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[X]], 0 ; CHECK-NEXT: [[R:%.*]] = select i1 [[TOBOOL]], i32 64, i32 [[CAST]] @@ -373,7 +373,7 @@ define i32 @not_op_cttz_wrong_cmp(i64 %x) { define i16 @test6d(i32 %x) { ; CHECK-LABEL: @test6d( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CAST:%.*]] = trunc nuw nsw i32 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CAST]] ; @@ -386,7 +386,7 @@ define i16 @test6d(i32 %x) { define i64 @select_bug1(i32 %x) { ; CHECK-LABEL: @select_bug1( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: ret i64 [[CONV]] ; @@ -399,7 +399,7 @@ define i64 @select_bug1(i32 %x) { define i16 @select_bug2(i32 %x) { ; CHECK-LABEL: @select_bug2( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i32 [[CT]] to i16 ; CHECK-NEXT: ret i16 [[CONV]] ; @@ -412,7 +412,7 @@ define i16 @select_bug2(i32 %x) { define i128 @test7(i128 %x) { ; CHECK-LABEL: @test7( -; CHECK-NEXT: [[CT:%.*]] = tail call i128 @llvm.ctlz.i128(i128 [[X:%.*]], i1 false), !range [[RNG3:![0-9]+]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i128 0, 129) i128 @llvm.ctlz.i128(i128 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i128 [[CT]] ; %ct = tail call i128 @llvm.ctlz.i128(i128 %x, i1 true) @@ -423,7 +423,7 @@ define i128 @test7(i128 %x) { define i128 @test8(i128 %x) { ; CHECK-LABEL: @test8( -; CHECK-NEXT: [[CT:%.*]] = tail call i128 @llvm.cttz.i128(i128 [[X:%.*]], i1 false), !range [[RNG3]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i128 0, 129) i128 @llvm.cttz.i128(i128 [[X:%.*]], i1 false) ; CHECK-NEXT: ret i128 [[CT]] ; %ct = tail call i128 @llvm.cttz.i128(i128 %x, i1 true) @@ -434,7 +434,7 @@ define i128 @test8(i128 %x) { define i32 @test_ctlz_not_bw(i32 %x) { ; CHECK-LABEL: @test_ctlz_not_bw( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP_NOT]], i32 123, i32 [[CT]] ; CHECK-NEXT: ret i32 [[RES]] @@ -447,7 +447,7 @@ define i32 @test_ctlz_not_bw(i32 %x) { define i32 @test_ctlz_not_bw_multiuse(i32 %x) { ; CHECK-LABEL: @test_ctlz_not_bw_multiuse( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], i32 123, i32 [[CT]] ; CHECK-NEXT: [[RES:%.*]] = or i32 [[SEL]], [[CT]] @@ -462,7 +462,7 @@ define i32 @test_ctlz_not_bw_multiuse(i32 %x) { define i32 @test_cttz_not_bw(i32 %x) { ; CHECK-LABEL: @test_cttz_not_bw( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[RES:%.*]] = select i1 [[CMP_NOT]], i32 123, i32 [[CT]] ; CHECK-NEXT: ret i32 [[RES]] @@ -475,7 +475,7 @@ define i32 @test_cttz_not_bw(i32 %x) { define i32 @test_cttz_not_bw_multiuse(i32 %x) { ; CHECK-LABEL: @test_cttz_not_bw_multiuse( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[X]], 0 ; CHECK-NEXT: [[SEL:%.*]] = select i1 [[CMP_NOT]], i32 123, i32 [[CT]] ; CHECK-NEXT: [[RES:%.*]] = or i32 [[SEL]], [[CT]] @@ -490,7 +490,7 @@ define i32 @test_cttz_not_bw_multiuse(i32 %x) { define <2 x i32> @test_ctlz_bw_vec(<2 x i32> %x) { ; CHECK-LABEL: @test_ctlz_bw_vec( -; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CT]] ; %ct = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> %x, i1 true) @@ -501,7 +501,7 @@ define <2 x i32> @test_ctlz_bw_vec(<2 x i32> %x) { define <2 x i32> @test_ctlz_not_bw_vec(<2 x i32> %x) { ; CHECK-LABEL: @test_ctlz_not_bw_vec( -; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[X:%.*]], i1 true) ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[CMP_NOT]], <2 x i32> zeroinitializer, <2 x i32> [[CT]] ; CHECK-NEXT: ret <2 x i32> [[RES]] @@ -514,7 +514,7 @@ define <2 x i32> @test_ctlz_not_bw_vec(<2 x i32> %x) { define <2 x i32> @test_cttz_bw_vec(<2 x i32> %x) { ; CHECK-LABEL: @test_cttz_bw_vec( -; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 false) ; CHECK-NEXT: ret <2 x i32> [[CT]] ; %ct = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> %x, i1 true) @@ -525,7 +525,7 @@ define <2 x i32> @test_cttz_bw_vec(<2 x i32> %x) { define <2 x i32> @test_cttz_not_bw_vec(<2 x i32> %x) { ; CHECK-LABEL: @test_cttz_not_bw_vec( -; CHECK-NEXT: [[CT:%.*]] = tail call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[X:%.*]], i1 true) ; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq <2 x i32> [[X]], zeroinitializer ; CHECK-NEXT: [[RES:%.*]] = select <2 x i1> [[CMP_NOT]], <2 x i32> zeroinitializer, <2 x i32> [[CT]] ; CHECK-NEXT: ret <2 x i32> [[RES]] @@ -538,7 +538,7 @@ define <2 x i32> @test_cttz_not_bw_vec(<2 x i32> %x) { define i32 @test_multiuse_def(i32 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_def( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: store i32 [[CT]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: ret i32 [[CT]] ; @@ -551,7 +551,7 @@ define i32 @test_multiuse_def(i32 %x, ptr %p) { define i32 @test_multiuse_undef(i32 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_undef( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: store i32 [[CT]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: ret i32 [[CT]] ; @@ -564,7 +564,7 @@ define i32 @test_multiuse_undef(i32 %x, ptr %p) { define i64 @test_multiuse_zext_def(i32 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_zext_def( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: store i64 [[CONV]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: ret i64 [[CONV]] @@ -579,7 +579,7 @@ define i64 @test_multiuse_zext_def(i32 %x, ptr %p) { define i64 @test_multiuse_zext_undef(i32 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_zext_undef( -; CHECK-NEXT: [[CT:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG1]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = zext nneg i32 [[CT]] to i64 ; CHECK-NEXT: store i64 [[CONV]], ptr [[P:%.*]], align 4 ; CHECK-NEXT: ret i64 [[CONV]] @@ -594,7 +594,7 @@ define i64 @test_multiuse_zext_undef(i32 %x, ptr %p) { define i16 @test_multiuse_trunc_def(i64 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_trunc_def( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: store i16 [[CONV]], ptr [[P:%.*]], align 2 ; CHECK-NEXT: ret i16 [[CONV]] @@ -609,7 +609,7 @@ define i16 @test_multiuse_trunc_def(i64 %x, ptr %p) { define i16 @test_multiuse_trunc_undef(i64 %x, ptr %p) { ; CHECK-LABEL: @test_multiuse_trunc_undef( -; CHECK-NEXT: [[CT:%.*]] = tail call i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[CT:%.*]] = tail call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[X:%.*]], i1 false) ; CHECK-NEXT: [[CONV:%.*]] = trunc nuw nsw i64 [[CT]] to i16 ; CHECK-NEXT: store i16 [[CONV]], ptr [[P:%.*]], align 2 ; CHECK-NEXT: ret i16 [[CONV]] diff --git a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll index fa8443d4c9578ecf368c2e6b5764da76a8af52d8..59d33ee3b39df5f584361ad76244ee250b7ccad2 100644 --- a/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll +++ b/llvm/test/Transforms/InstCombine/select-ctlz-to-cttz.ll @@ -16,7 +16,7 @@ declare void @use2(i1) define i32 @select_clz_to_ctz(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz( -; CHECK-NEXT: [[SUB1:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[SUB1:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[SUB1]] ; %sub = sub i32 0, %a @@ -30,7 +30,7 @@ define i32 @select_clz_to_ctz(i32 %a) { define i32 @select_clz_to_ctz_preserve_flag(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_preserve_flag( -; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[COND:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[COND]] ; %sub = sub i32 0, %a @@ -44,7 +44,7 @@ define i32 @select_clz_to_ctz_preserve_flag(i32 %a) { define i32 @select_clz_to_ctz_constant_for_zero(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_constant_for_zero( -; CHECK-NEXT: [[COND:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[COND:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 false) ; CHECK-NEXT: ret i32 [[COND]] ; %sub = sub i32 0, %a @@ -58,7 +58,7 @@ define i32 @select_clz_to_ctz_constant_for_zero(i32 %a) { define <2 x i32> @select_clz_to_ctz_vec(<2 x i32> %a) { ; CHECK-LABEL: @select_clz_to_ctz_vec( -; CHECK-NEXT: [[COND:%.*]] = call <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[A:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[COND:%.*]] = call range(i32 0, 33) <2 x i32> @llvm.cttz.v2i32(<2 x i32> [[A:%.*]], i1 true) ; CHECK-NEXT: ret <2 x i32> [[COND]] ; %sub = sub <2 x i32> zeroinitializer, %a @@ -72,7 +72,7 @@ define <2 x i32> @select_clz_to_ctz_vec(<2 x i32> %a) { define i32 @select_clz_to_ctz_extra_use(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_extra_use( -; CHECK-NEXT: [[SUB1:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[SUB1:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true) ; CHECK-NEXT: call void @use(i32 [[SUB1]]) ; CHECK-NEXT: ret i32 [[SUB1]] ; @@ -88,7 +88,7 @@ define i32 @select_clz_to_ctz_extra_use(i32 %a) { define i32 @select_clz_to_ctz_and_commuted(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_and_commuted( -; CHECK-NEXT: [[SUB1:%.*]] = call i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[SUB1:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[SUB1]] ; %sub = sub i32 0, %a @@ -104,7 +104,7 @@ define i32 @select_clz_to_ctz_icmp_ne(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_icmp_ne( ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[A:%.*]], 0 ; CHECK-NEXT: call void @use2(i1 [[TOBOOL]]) -; CHECK-NEXT: [[SUB1:%.*]] = call i32 @llvm.cttz.i32(i32 [[A]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[SUB1:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[A]], i1 true) ; CHECK-NEXT: ret i32 [[SUB1]] ; %sub = sub i32 0, %a @@ -119,7 +119,7 @@ define i32 @select_clz_to_ctz_icmp_ne(i32 %a) { define i64 @select_clz_to_ctz_i64(i64 %a) { ; CHECK-LABEL: @select_clz_to_ctz_i64( -; CHECK-NEXT: [[SUB1:%.*]] = call i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[SUB1:%.*]] = call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[A:%.*]], i1 true) ; CHECK-NEXT: ret i64 [[SUB1]] ; %sub = sub i64 0, %a @@ -137,7 +137,7 @@ define i32 @select_clz_to_ctz_wrong_sub(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_wrong_sub( ; CHECK-NEXT: [[SUB:%.*]] = sub i32 1, [[A:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[A]] -; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[AND]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[AND]], i1 true) ; CHECK-NEXT: [[SUB1:%.*]] = xor i32 [[LZ]], 31 ; CHECK-NEXT: ret i32 [[SUB1]] ; @@ -155,7 +155,7 @@ define i64 @select_clz_to_ctz_i64_wrong_xor(i64 %a) { ; CHECK-LABEL: @select_clz_to_ctz_i64_wrong_xor( ; CHECK-NEXT: [[SUB:%.*]] = sub i64 0, [[A:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i64 [[SUB]], [[A]] -; CHECK-NEXT: [[LZ:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[AND]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[AND]], i1 true) ; CHECK-NEXT: [[SUB11:%.*]] = or disjoint i64 [[LZ]], 64 ; CHECK-NEXT: ret i64 [[SUB11]] ; @@ -171,7 +171,7 @@ define i64 @select_clz_to_ctz_i64_wrong_xor(i64 %a) { define i64 @select_clz_to_ctz_i64_wrong_icmp_cst(i64 %a) { ; CHECK-LABEL: @select_clz_to_ctz_i64_wrong_icmp_cst( ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i64 [[A:%.*]], 1 -; CHECK-NEXT: [[SUB1:%.*]] = call i64 @llvm.cttz.i64(i64 [[A]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[SUB1:%.*]] = call range(i64 0, 65) i64 @llvm.cttz.i64(i64 [[A]], i1 true) ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 63, i64 [[SUB1]] ; CHECK-NEXT: ret i64 [[COND]] ; @@ -188,7 +188,7 @@ define i64 @select_clz_to_ctz_i64_wrong_icmp_pred(i64 %a) { ; CHECK-LABEL: @select_clz_to_ctz_i64_wrong_icmp_pred( ; CHECK-NEXT: [[SUB:%.*]] = sub i64 0, [[A:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i64 [[SUB]], [[A]] -; CHECK-NEXT: [[LZ:%.*]] = tail call i64 @llvm.ctlz.i64(i64 [[AND]], i1 true), !range [[RNG1]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i64 0, 65) i64 @llvm.ctlz.i64(i64 [[AND]], i1 true) ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp slt i64 [[A]], 0 ; CHECK-NEXT: [[SUB1:%.*]] = xor i64 [[LZ]], 63 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i64 [[LZ]], i64 [[SUB1]] @@ -207,7 +207,7 @@ define <2 x i32> @select_clz_to_ctz_vec_with_undef(<2 x i32> %a) { ; CHECK-LABEL: @select_clz_to_ctz_vec_with_undef( ; CHECK-NEXT: [[SUB:%.*]] = sub <2 x i32> zeroinitializer, [[A:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[SUB]], [[A]] -; CHECK-NEXT: [[LZ:%.*]] = tail call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[AND]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[AND]], i1 true) ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq <2 x i32> [[A]], zeroinitializer ; CHECK-NEXT: [[SUB1:%.*]] = xor <2 x i32> [[LZ]], ; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[TOBOOL]], <2 x i32> [[LZ]], <2 x i32> [[SUB1]] @@ -226,7 +226,7 @@ define i32 @select_clz_to_ctz_wrong_constant_for_zero(i32 %a) { ; CHECK-LABEL: @select_clz_to_ctz_wrong_constant_for_zero( ; CHECK-NEXT: [[SUB:%.*]] = sub i32 0, [[A:%.*]] ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SUB]], [[A]] -; CHECK-NEXT: [[LZ:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[AND]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[LZ:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[AND]], i1 false) ; CHECK-NEXT: [[TOBOOL:%.*]] = icmp eq i32 [[A]], 0 ; CHECK-NEXT: [[SUB1:%.*]] = xor i32 [[LZ]], 31 ; CHECK-NEXT: [[COND:%.*]] = select i1 [[TOBOOL]], i32 31, i32 [[SUB1]] @@ -243,7 +243,7 @@ define i32 @select_clz_to_ctz_wrong_constant_for_zero(i32 %a) { define i4 @PR45762(i3 %x4) { ; CHECK-LABEL: @PR45762( -; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[T4:%.*]] = call range(i3 0, -4) i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false) ; CHECK-NEXT: [[T7:%.*]] = zext nneg i3 [[T4]] to i4 ; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]] ; CHECK-NEXT: [[OR_69_NOT:%.*]] = icmp eq i3 [[X4]], 0 @@ -272,7 +272,7 @@ define i4 @PR45762(i3 %x4) { define i4 @PR45762_logical(i3 %x4) { ; CHECK-LABEL: @PR45762_logical( -; CHECK-NEXT: [[T4:%.*]] = call i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false), !range [[RNG2]] +; CHECK-NEXT: [[T4:%.*]] = call range(i3 0, -4) i3 @llvm.cttz.i3(i3 [[X4:%.*]], i1 false) ; CHECK-NEXT: [[T7:%.*]] = zext nneg i3 [[T4]] to i4 ; CHECK-NEXT: [[ONE_HOT_16:%.*]] = shl nuw i4 1, [[T7]] ; CHECK-NEXT: [[OR_69_NOT:%.*]] = icmp eq i3 [[X4]], 0 diff --git a/llvm/test/Transforms/InstCombine/select.ll b/llvm/test/Transforms/InstCombine/select.ll index 2ec092a745c52c7a043ff7ea66c26c2a26d8b7b9..2efe2742ca4916427b3873247622cb75b84d5d62 100644 --- a/llvm/test/Transforms/InstCombine/select.ll +++ b/llvm/test/Transforms/InstCombine/select.ll @@ -2736,7 +2736,7 @@ define void @select_freeze_icmp_multuses(i32 %x, i32 %y) { define i32 @pr47322_more_poisonous_replacement(i32 %arg) { ; CHECK-LABEL: @pr47322_more_poisonous_replacement( ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[ARG:%.*]], 0 -; CHECK-NEXT: [[TRAILING:%.*]] = call i32 @llvm.cttz.i32(i32 [[ARG]], i1 immarg true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TRAILING:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[ARG]], i1 immarg true) ; CHECK-NEXT: [[SHIFTED:%.*]] = lshr i32 [[ARG]], [[TRAILING]] ; CHECK-NEXT: [[R1_SROA_0_1:%.*]] = select i1 [[CMP]], i32 0, i32 [[SHIFTED]] ; CHECK-NEXT: ret i32 [[R1_SROA_0_1]] @@ -3830,14 +3830,17 @@ entry: ret i32 %cond } -; FIXME: This is a miscompile. define <2 x i32> @src_and_eq_C_xor_OrAndNotC_vec_poison(<2 x i32> %0, <2 x i32> %1, <2 x i32> %2) { ; CHECK-LABEL: @src_and_eq_C_xor_OrAndNotC_vec_poison( ; CHECK-NEXT: entry: -; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1:%.*]], [[TMP0:%.*]] -; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i32> [[TMP2:%.*]], +; CHECK-NEXT: [[AND:%.*]] = and <2 x i32> [[TMP1:%.*]], [[TMP0:%.*]] +; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[AND]], [[TMP2:%.*]] +; CHECK-NEXT: [[XOR:%.*]] = xor <2 x i32> [[TMP1]], [[TMP0]] +; CHECK-NEXT: [[OR:%.*]] = or <2 x i32> [[TMP1]], [[TMP0]] +; CHECK-NEXT: [[NOT:%.*]] = xor <2 x i32> [[TMP2]], ; CHECK-NEXT: [[AND1:%.*]] = and <2 x i32> [[OR]], [[NOT]] -; CHECK-NEXT: ret <2 x i32> [[AND1]] +; CHECK-NEXT: [[COND:%.*]] = select <2 x i1> [[CMP]], <2 x i32> [[XOR]], <2 x i32> [[AND1]] +; CHECK-NEXT: ret <2 x i32> [[COND]] ; entry: %and = and <2 x i32> %1, %0 diff --git a/llvm/test/Transforms/InstCombine/sext.ll b/llvm/test/Transforms/InstCombine/sext.ll index 6d263cfcda057797347f1086eb48c58973c98fa3..a554f2b28d6f29905cf5bf1170754abf40c626fe 100644 --- a/llvm/test/Transforms/InstCombine/sext.ll +++ b/llvm/test/Transforms/InstCombine/sext.ll @@ -11,7 +11,7 @@ declare void @use_vec(<2 x i5>) define i64 @test1(i32 %x) { ; CHECK-LABEL: @test1( -; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctpop.i32(i32 [[X:%.*]]), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[T:%.*]] = call range(i32 0, 33) i32 @llvm.ctpop.i32(i32 [[X:%.*]]) ; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; @@ -22,7 +22,7 @@ define i64 @test1(i32 %x) { define i64 @test2(i32 %x) { ; CHECK-LABEL: @test2( -; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[T:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; @@ -33,7 +33,7 @@ define i64 @test2(i32 %x) { define i64 @test3(i32 %x) { ; CHECK-LABEL: @test3( -; CHECK-NEXT: [[T:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[T:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: [[S:%.*]] = zext nneg i32 [[T]] to i64 ; CHECK-NEXT: ret i64 [[S]] ; diff --git a/llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll b/llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll index 2b2f820c9a095608edb1addadd9481857fba0fb2..1c381d0839071598a1fd1a018835a511e70fb2e0 100644 --- a/llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll +++ b/llvm/test/Transforms/InstCombine/shift-cttz-ctlz.ll @@ -5,7 +5,7 @@ define i32 @shl_cttz_false(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @shl_cttz_false( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Y]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Y]], i1 true) ; CHECK-NEXT: [[RES:%.*]] = shl i32 [[X]], [[CTTZ]] ; CHECK-NEXT: ret i32 [[RES]] ; @@ -19,7 +19,7 @@ define i32 @shl_ctlz_false(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @shl_ctlz_false( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.ctlz.i32(i32 [[Y]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[Y]], i1 true) ; CHECK-NEXT: [[RES:%.*]] = shl i32 [[X]], [[CTTZ]] ; CHECK-NEXT: ret i32 [[RES]] ; @@ -33,7 +33,7 @@ define i32 @lshr_cttz_false(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @lshr_cttz_false( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Y]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Y]], i1 true) ; CHECK-NEXT: [[RES:%.*]] = lshr i32 [[X]], [[CTTZ]] ; CHECK-NEXT: ret i32 [[RES]] ; @@ -47,7 +47,7 @@ define i32 @ashr_cttz_false(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @ashr_cttz_false( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Y]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Y]], i1 true) ; CHECK-NEXT: [[RES:%.*]] = ashr i32 [[X]], [[CTTZ]] ; CHECK-NEXT: ret i32 [[RES]] ; @@ -61,7 +61,7 @@ define i32 @shl_cttz_false_multiuse(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @shl_cttz_false_multiuse( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Y]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Y]], i1 false) ; CHECK-NEXT: call void @use(i32 [[CTTZ]]) ; CHECK-NEXT: [[RES:%.*]] = shl i32 [[X]], [[CTTZ]] ; CHECK-NEXT: ret i32 [[RES]] @@ -77,7 +77,7 @@ define i32 @shl_cttz_as_lhs(i32 %x, i32 %y) { ; CHECK-LABEL: define i32 @shl_cttz_as_lhs( ; CHECK-SAME: i32 [[X:%.*]], i32 [[Y:%.*]]) { ; CHECK-NEXT: entry: -; CHECK-NEXT: [[CTTZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[Y]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[CTTZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[Y]], i1 false) ; CHECK-NEXT: [[RES:%.*]] = shl i32 [[CTTZ]], [[X]] ; CHECK-NEXT: ret i32 [[RES]] ; @@ -88,6 +88,3 @@ entry: } declare void @use(i32) -;. -; CHECK: [[RNG0]] = !{i32 0, i32 33} -;. diff --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll index bb8661919c89f5e4d33997062816d33dba791f3b..5692202fcb4c7681d0d248c2cbd40cb87451891c 100644 --- a/llvm/test/Transforms/InstCombine/shift.ll +++ b/llvm/test/Transforms/InstCombine/shift.ll @@ -2055,7 +2055,7 @@ define <2 x i8> @shl1_cttz_vec_poison(<2 x i8> %x) { define i32 @shl1_cttz_extra_use(i32 %x) { ; CHECK-LABEL: @shl1_cttz_extra_use( -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 false) ; CHECK-NEXT: call void @use_i32(i32 [[TZ]]) ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i32 1, [[TZ]] ; CHECK-NEXT: ret i32 [[SHL]] @@ -2070,7 +2070,7 @@ define i32 @shl1_cttz_extra_use(i32 %x) { define i32 @shl2_cttz(i32 %x) { ; CHECK-LABEL: @shl2_cttz( -; CHECK-NEXT: [[TZ:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[TZ:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: [[SHL:%.*]] = shl i32 2, [[TZ]] ; CHECK-NEXT: ret i32 [[SHL]] ; diff --git a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll index 72fd7f7be2b04cb203c29de8f8639de75d07dfc5..b2e14ceaca1b084ce1b01bea67bcb76877162aea 100644 --- a/llvm/test/Transforms/InstCombine/sub-of-negatible.ll +++ b/llvm/test/Transforms/InstCombine/sub-of-negatible.ll @@ -1385,12 +1385,12 @@ define i8 @dont_negate_ordinary_select(i8 %x, i8 %y, i8 %z, i1 %c) { ret i8 %t1 } -; FIXME: This is a miscompile. define <2 x i32> @negate_select_of_negation_poison(<2 x i1> %c, <2 x i32> %x) { ; CHECK-LABEL: @negate_select_of_negation_poison( ; CHECK-NEXT: [[NEG:%.*]] = sub <2 x i32> , [[X:%.*]] -; CHECK-NEXT: [[TMP1:%.*]] = select <2 x i1> [[C:%.*]], <2 x i32> [[X]], <2 x i32> [[NEG]] -; CHECK-NEXT: ret <2 x i32> [[TMP1]] +; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[C:%.*]], <2 x i32> [[NEG]], <2 x i32> [[X]] +; CHECK-NEXT: [[NEG2:%.*]] = sub <2 x i32> zeroinitializer, [[SEL]] +; CHECK-NEXT: ret <2 x i32> [[NEG2]] ; %neg = sub <2 x i32> , %x %sel = select <2 x i1> %c, <2 x i32> %neg, <2 x i32> %x diff --git a/llvm/test/Transforms/InstCombine/sub-xor.ll b/llvm/test/Transforms/InstCombine/sub-xor.ll index 2976598e043fee5c5e03c363cc34395cc999cd6d..b4add9698b160915d6c9713e8868b9046f57f600 100644 --- a/llvm/test/Transforms/InstCombine/sub-xor.ll +++ b/llvm/test/Transforms/InstCombine/sub-xor.ll @@ -97,7 +97,7 @@ declare i32 @llvm.ctlz.i32(i32, i1) define i32 @range_masked_sub(i32 %x) { ; CHECK-LABEL: @range_masked_sub( -; CHECK-NEXT: [[COUNT:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true) #[[ATTR1:[0-9]+]], !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[COUNT:%.*]] = tail call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[X:%.*]], i1 true) #[[ATTR1:[0-9]+]] ; CHECK-NEXT: [[SUB:%.*]] = xor i32 [[COUNT]], 31 ; CHECK-NEXT: ret i32 [[SUB]] ; diff --git a/llvm/test/Transforms/InstCombine/xor.ll b/llvm/test/Transforms/InstCombine/xor.ll index ba9e992a9443c9dd4b5c3167b4181a2e5ed64f2c..9a59db40ef8b1e5e756d0dc2d3b1989b1c31176c 100644 --- a/llvm/test/Transforms/InstCombine/xor.ll +++ b/llvm/test/Transforms/InstCombine/xor.ll @@ -1336,7 +1336,7 @@ define i32 @xor_orn_2use(i32 %a, i32 %b, ptr %s1, ptr %s2) { define i32 @ctlz_pow2(i32 %x) { ; CHECK-LABEL: @ctlz_pow2( -; CHECK-NEXT: [[R:%.*]] = call i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[R:%.*]] = call range(i32 0, 33) i32 @llvm.cttz.i32(i32 [[X:%.*]], i1 true) ; CHECK-NEXT: ret i32 [[R]] ; %n = sub i32 0, %x @@ -1352,7 +1352,7 @@ define <2 x i8> @cttz_pow2(<2 x i8> %x, <2 x i8> %y) { ; CHECK-LABEL: @cttz_pow2( ; CHECK-NEXT: [[S:%.*]] = shl nuw <2 x i8> , [[X:%.*]] ; CHECK-NEXT: [[D:%.*]] = udiv exact <2 x i8> [[S]], [[Y:%.*]] -; CHECK-NEXT: [[R:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[D]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[R:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[D]], i1 true) ; CHECK-NEXT: ret <2 x i8> [[R]] ; %s = shl <2 x i8> , %x @@ -1368,7 +1368,7 @@ define i32 @ctlz_pow2_or_zero(i32 %x) { ; CHECK-LABEL: @ctlz_pow2_or_zero( ; CHECK-NEXT: [[N:%.*]] = sub i32 0, [[X:%.*]] ; CHECK-NEXT: [[A:%.*]] = and i32 [[N]], [[X]] -; CHECK-NEXT: [[Z:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[Z:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[A]], i1 false) ; CHECK-NEXT: [[R:%.*]] = xor i32 [[Z]], 31 ; CHECK-NEXT: ret i32 [[R]] ; @@ -1385,7 +1385,7 @@ define i32 @ctlz_pow2_wrong_const(i32 %x) { ; CHECK-LABEL: @ctlz_pow2_wrong_const( ; CHECK-NEXT: [[N:%.*]] = sub i32 0, [[X:%.*]] ; CHECK-NEXT: [[A:%.*]] = and i32 [[N]], [[X]] -; CHECK-NEXT: [[Z:%.*]] = call i32 @llvm.ctlz.i32(i32 [[A]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[Z:%.*]] = call range(i32 0, 33) i32 @llvm.ctlz.i32(i32 [[A]], i1 true) ; CHECK-NEXT: [[R:%.*]] = xor i32 [[Z]], 30 ; CHECK-NEXT: ret i32 [[R]] ; diff --git a/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll b/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll index c8eb513a8440b493b8c41f12bdb4fb8bac637c34..384ff8d2b7a3a3f9e1a597bb8135ebbc8ef455eb 100644 --- a/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll +++ b/llvm/test/Transforms/InstCombine/zext-ctlz-trunc-to-ctlz-add.ll @@ -13,7 +13,7 @@ declare void @use1() define i16 @trunc_ctlz_zext_i16_i32(i16 %x) { ; CHECK-LABEL: @trunc_ctlz_zext_i16_i32( -; CHECK-NEXT: [[TMP1:%.*]] = call i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false), !range [[RNG0:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) i16 @llvm.ctlz.i16(i16 [[X:%.*]], i1 false) ; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw i16 [[TMP1]], 16 ; CHECK-NEXT: ret i16 [[ZZ]] ; @@ -27,7 +27,7 @@ define i16 @trunc_ctlz_zext_i16_i32(i16 %x) { define <2 x i8> @trunc_ctlz_zext_v2i8_v2i33(<2 x i8> %x) { ; CHECK-LABEL: @trunc_ctlz_zext_v2i8_v2i33( -; CHECK-NEXT: [[TMP1:%.*]] = call <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[X:%.*]], i1 true), !range [[RNG1:![0-9]+]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i8 0, 9) <2 x i8> @llvm.ctlz.v2i8(<2 x i8> [[X:%.*]], i1 true) ; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw <2 x i8> [[TMP1]], ; CHECK-NEXT: ret <2 x i8> [[ZZ]] ; @@ -41,7 +41,7 @@ define <2 x i8> @trunc_ctlz_zext_v2i8_v2i33(<2 x i8> %x) { define @trunc_ctlz_zext_nxv2i16_nxv2i64( %x) { ; CHECK-LABEL: @trunc_ctlz_zext_nxv2i16_nxv2i64( -; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.ctlz.nxv2i16( [[X:%.*]], i1 false), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) @llvm.ctlz.nxv2i16( [[X:%.*]], i1 false) ; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw [[TMP1]], shufflevector ( insertelement ( poison, i16 48, i64 0), poison, zeroinitializer) ; CHECK-NEXT: ret [[ZZ]] ; @@ -56,7 +56,7 @@ define @trunc_ctlz_zext_nxv2i16_nxv2i64( %x define <2 x i17> @trunc_ctlz_zext_v2i17_v2i32_multiple_uses(<2 x i17> %x) { ; CHECK-LABEL: @trunc_ctlz_zext_v2i17_v2i32_multiple_uses( ; CHECK-NEXT: [[Z:%.*]] = zext <2 x i17> [[X:%.*]] to <2 x i32> -; CHECK-NEXT: [[P:%.*]] = call <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[Z]], i1 false), !range [[RNG2:![0-9]+]] +; CHECK-NEXT: [[P:%.*]] = call range(i32 15, 33) <2 x i32> @llvm.ctlz.v2i32(<2 x i32> [[Z]], i1 false) ; CHECK-NEXT: [[ZZ:%.*]] = trunc nuw nsw <2 x i32> [[P]] to <2 x i17> ; CHECK-NEXT: call void @use(<2 x i32> [[P]]) ; CHECK-NEXT: ret <2 x i17> [[ZZ]] @@ -73,7 +73,7 @@ define <2 x i17> @trunc_ctlz_zext_v2i17_v2i32_multiple_uses(<2 x i17> %x) { define @trunc_ctlz_zext_nxv2i16_nxv2i63_multiple_uses( %x) { ; CHECK-LABEL: @trunc_ctlz_zext_nxv2i16_nxv2i63_multiple_uses( ; CHECK-NEXT: [[Z:%.*]] = zext [[X:%.*]] to -; CHECK-NEXT: [[TMP1:%.*]] = call @llvm.ctlz.nxv2i16( [[X]], i1 true), !range [[RNG0]] +; CHECK-NEXT: [[TMP1:%.*]] = call range(i16 0, 17) @llvm.ctlz.nxv2i16( [[X]], i1 true) ; CHECK-NEXT: [[ZZ:%.*]] = add nuw nsw [[TMP1]], shufflevector ( insertelement ( poison, i16 47, i64 0), poison, zeroinitializer) ; CHECK-NEXT: call void @use1( [[Z]]) ; CHECK-NEXT: ret [[ZZ]] @@ -90,7 +90,7 @@ define @trunc_ctlz_zext_nxv2i16_nxv2i63_multiple_uses( [[TMP19]], ; CHECK-NEXT: [[TMP47:%.*]] = select <4 x i1> [[TMP46]], <4 x i1> , <4 x i1> [[TMP44]] ; CHECK-NEXT: [[TMP48:%.*]] = bitcast <4 x i1> [[TMP47]] to i4 -; CHECK-NEXT: [[TMP49:%.*]] = call i4 @llvm.ctpop.i4(i4 [[TMP48]]), !range [[RNG42:![0-9]+]] +; CHECK-NEXT: [[TMP49:%.*]] = call range(i4 0, 5) i4 @llvm.ctpop.i4(i4 [[TMP48]]) ; CHECK-NEXT: [[TMP50:%.*]] = zext nneg i4 [[TMP49]] to i32 ; CHECK-NEXT: [[TMP51]] = add i32 [[VEC_PHI]], [[TMP50]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4 ; CHECK-NEXT: [[TMP52:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1000 -; CHECK-NEXT: br i1 [[TMP52]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP43:![0-9]+]] +; CHECK-NEXT: br i1 [[TMP52]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP42:![0-9]+]] ; CHECK: middle.block: ; CHECK-NEXT: br i1 true, label [[FOR_COND_CLEANUP:%.*]], label [[SCALAR_PH]] ; CHECK: scalar.ph: @@ -1377,7 +1377,7 @@ define i32 @predicated_or_dominates_reduction(ptr %b) { ; CHECK: if.then: ; CHECK-NEXT: br label [[FOR_INC]] ; CHECK: for.inc: -; CHECK-NEXT: br i1 poison, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP44:![0-9]+]] +; CHECK-NEXT: br i1 poison, label [[FOR_COND_CLEANUP]], label [[FOR_BODY]], !llvm.loop [[LOOP43:![0-9]+]] ; entry: br label %for.body diff --git a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll index 6132c35c96ca32e4cbcb537028ef0969d00a478a..b32f4e2a258cd7528039cb1f014e7cc1d9747283 100644 --- a/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll +++ b/llvm/test/Transforms/PhaseOrdering/AArch64/extra-unroll-simplifications.ll @@ -72,6 +72,86 @@ exit: ret void } +define void @cse_matching_load_from_previous_unrolled_iteration(i32 %N, ptr %src, ptr noalias %dst) { +; CHECK-LABEL: define void @cse_matching_load_from_previous_unrolled_iteration( +; CHECK-SAME: i32 [[N:%.*]], ptr nocapture readonly [[SRC:%.*]], ptr noalias nocapture writeonly [[DST:%.*]]) local_unnamed_addr #[[ATTR0]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SRC_4:%.*]] = getelementptr i8, ptr [[SRC]], i64 4 +; CHECK-NEXT: [[SRC_12:%.*]] = getelementptr i8, ptr [[SRC]], i64 12 +; CHECK-NEXT: [[CMP141:%.*]] = icmp sgt i32 [[N]], 0 +; CHECK-NEXT: br i1 [[CMP141]], label [[LOOP_LATCH_PREHEADER:%.*]], label [[EXIT:%.*]] +; CHECK: loop.latch.preheader: +; CHECK-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext nneg i32 [[N]] to i64 +; CHECK-NEXT: [[XTRAITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[N]], 1 +; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT_LOOPEXIT_UNR_LCSSA:%.*]], label [[LOOP_LATCH_PREHEADER_NEW:%.*]] +; CHECK: loop.latch.preheader.new: +; CHECK-NEXT: [[UNROLL_ITER:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 2147483646 +; CHECK-NEXT: br label [[LOOP_LATCH:%.*]] +; CHECK: loop.latch: +; CHECK-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[NITER:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER_NEW]] ], [ [[NITER_NEXT_1:%.*]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[GEP_SRC_12:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV]] +; CHECK-NEXT: [[L_12:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12]], align 8 +; CHECK-NEXT: [[GEP_SRC_4:%.*]] = getelementptr <2 x i32>, ptr [[SRC_4]], i64 [[INDVARS_IV]] +; CHECK-NEXT: [[L_4:%.*]] = load <2 x i32>, ptr [[GEP_SRC_4]], align 8 +; CHECK-NEXT: [[MUL:%.*]] = mul <2 x i32> [[L_4]], [[L_12]] +; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr <2 x i32>, ptr [[DST]], i64 [[INDVARS_IV]] +; CHECK-NEXT: store <2 x i32> [[MUL]], ptr [[GEP_DST]], align 8 +; CHECK-NEXT: [[INDVARS_IV_NEXT:%.*]] = or disjoint i64 [[INDVARS_IV]], 1 +; CHECK-NEXT: [[GEP_SRC_12_1:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV_NEXT]] +; CHECK-NEXT: [[L_12_1:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12_1]], align 8 +; CHECK-NEXT: [[GEP_SRC_4_1:%.*]] = getelementptr <2 x i32>, ptr [[SRC_4]], i64 [[INDVARS_IV_NEXT]] +; CHECK-NEXT: [[L_4_1:%.*]] = load <2 x i32>, ptr [[GEP_SRC_4_1]], align 8 +; CHECK-NEXT: [[MUL_1:%.*]] = mul <2 x i32> [[L_4_1]], [[L_12_1]] +; CHECK-NEXT: [[GEP_DST_1:%.*]] = getelementptr <2 x i32>, ptr [[DST]], i64 [[INDVARS_IV_NEXT]] +; CHECK-NEXT: store <2 x i32> [[MUL_1]], ptr [[GEP_DST_1]], align 8 +; CHECK-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV]], 2 +; CHECK-NEXT: [[NITER_NEXT_1]] = add i64 [[NITER]], 2 +; CHECK-NEXT: [[NITER_NCMP_1:%.*]] = icmp eq i64 [[NITER_NEXT_1]], [[UNROLL_ITER]] +; CHECK-NEXT: br i1 [[NITER_NCMP_1]], label [[EXIT_LOOPEXIT_UNR_LCSSA]], label [[LOOP_LATCH]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: exit.loopexit.unr-lcssa: +; CHECK-NEXT: [[INDVARS_IV_UNR:%.*]] = phi i64 [ 0, [[LOOP_LATCH_PREHEADER]] ], [ [[INDVARS_IV_NEXT_1]], [[LOOP_LATCH]] ] +; CHECK-NEXT: [[LCMP_MOD_NOT:%.*]] = icmp eq i64 [[XTRAITER]], 0 +; CHECK-NEXT: br i1 [[LCMP_MOD_NOT]], label [[EXIT]], label [[LOOP_LATCH_EPIL:%.*]] +; CHECK: loop.latch.epil: +; CHECK-NEXT: [[GEP_SRC_12_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[SRC_12]], i64 [[INDVARS_IV_UNR]] +; CHECK-NEXT: [[L_12_EPIL:%.*]] = load <2 x i32>, ptr [[GEP_SRC_12_EPIL]], align 8 +; CHECK-NEXT: [[GEP_SRC_4_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[SRC_4]], i64 [[INDVARS_IV_UNR]] +; CHECK-NEXT: [[L_4_EPIL:%.*]] = load <2 x i32>, ptr [[GEP_SRC_4_EPIL]], align 8 +; CHECK-NEXT: [[MUL_EPIL:%.*]] = mul <2 x i32> [[L_4_EPIL]], [[L_12_EPIL]] +; CHECK-NEXT: [[GEP_DST_EPIL:%.*]] = getelementptr <2 x i32>, ptr [[DST]], i64 [[INDVARS_IV_UNR]] +; CHECK-NEXT: store <2 x i32> [[MUL_EPIL]], ptr [[GEP_DST_EPIL]], align 8 +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %src.4 = getelementptr i8, ptr %src, i64 4 + %src.12 = getelementptr i8, ptr %src, i64 12 + br label %loop.header + +loop.header: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ] + %cmp14 = icmp slt i32 %iv, %N + br i1 %cmp14, label %loop.latch, label %exit + +loop.latch: + %iv.ext = zext i32 %iv to i64 + %gep.src.12 = getelementptr <2 x i32>, ptr %src.12, i64 %iv.ext + %l.12 = load <2 x i32>, ptr %gep.src.12, align 8 + %gep.src.4 = getelementptr <2 x i32>, ptr %src.4, i64 %iv.ext + %l.4 = load <2 x i32>, ptr %gep.src.4, align 8 + %mul = mul <2 x i32> %l.12, %l.4 + %gep.dst = getelementptr <2 x i32>, ptr %dst, i64 %iv.ext + store <2 x i32> %mul, ptr %gep.dst + %iv.next = add nuw nsw i32 %iv, 1 + br label %loop.header, !llvm.loop !0 + +exit: + ret void +} + !0 = distinct !{!0, !1, !2} !1 = !{!"llvm.loop.mustprogress"} !2 = !{!"llvm.loop.unroll.count", i32 2} @@ -79,4 +159,5 @@ exit: ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} ; CHECK: [[META1]] = !{!"llvm.loop.mustprogress"} ; CHECK: [[META2]] = !{!"llvm.loop.unroll.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]} ;. diff --git a/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll b/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll index 4b5f3107466c8bbb9c509910d9b1428a3a36dd67..7382c3c80d427300dc0f420bb8b9f52f9bd72836 100644 --- a/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll +++ b/llvm/test/Transforms/PhaseOrdering/X86/loop-idiom-vs-indvars.ll @@ -12,7 +12,7 @@ define i32 @cttz(i32 %n, ptr %p1) { ; ALL-LABEL: @cttz( ; ALL-NEXT: entry: ; ALL-NEXT: [[TMP0:%.*]] = shl i32 [[N:%.*]], 1 -; ALL-NEXT: [[TMP1:%.*]] = tail call i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false), !range [[RNG0:![0-9]+]] +; ALL-NEXT: [[TMP1:%.*]] = tail call range(i32 1, 33) i32 @llvm.cttz.i32(i32 [[TMP0]], i1 false) ; ALL-NEXT: [[TMP2:%.*]] = sub nuw nsw i32 32, [[TMP1]] ; ALL-NEXT: [[TMP3:%.*]] = sub nuw nsw i32 75, [[TMP1]] ; ALL-NEXT: store i32 [[TMP3]], ptr [[P1:%.*]], align 4 diff --git a/llvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll b/llvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll index 284873a9737624a6bd8562301ffef35d93bb63fa..19fbc1f1ae64e38d27cc8f17bacf5c05030d32dc 100644 --- a/llvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll +++ b/llvm/test/Transforms/PhaseOrdering/lower-table-based-cttz.ll @@ -15,7 +15,7 @@ ; RUN: opt -O3 -S < %s | FileCheck %s -; CHECK: call i32 @llvm.cttz.i32 +; CHECK: call range(i32 0, 33) i32 @llvm.cttz.i32 @ctz1.table = internal constant [32 x i8] c"\00\01\1C\02\1D\0E\18\03\1E\16\14\0F\19\11\04\08\1F\1B\0D\17\15\13\10\07\1A\0C\12\06\0B\05\0A\09", align 16 diff --git a/llvm/test/Transforms/SimplifyCFG/mmra.ll b/llvm/test/Transforms/SimplifyCFG/mmra.ll new file mode 100644 index 0000000000000000000000000000000000000000..6670657471376bdbb494a355f551341f0f7a37f5 --- /dev/null +++ b/llvm/test/Transforms/SimplifyCFG/mmra.ll @@ -0,0 +1,150 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=simplifycfg -simplifycfg-require-and-preserve-domtree=1 -S %s | FileCheck %s + +; RUN: opt -passes='simplifycfg,verify' -S %s | FileCheck %s + +declare void @clobber1() +declare void @clobber2() + +define void @sink(ptr %arg, i1 %c) { +; CHECK-LABEL: define void @sink( +; CHECK-SAME: ptr [[ARG:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: call void @clobber1() +; CHECK-NEXT: store ptr null, ptr [[ARG]], align 8 +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: else: +; CHECK-NEXT: call void @clobber2() +; CHECK-NEXT: store ptr null, ptr [[ARG]], align 8, !mmra [[META0:![0-9]+]] +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +bb: + br i1 %c, label %then, label %else + +then: + call void @clobber1() + store ptr null, ptr %arg, align 8 + br label %exit + +else: + call void @clobber2() + store ptr null, ptr %arg, align 8, !mmra !0 + br label %exit + +exit: + ret void +} + +define void @hoist_store(ptr %arg, i1 %c) { +; CHECK-LABEL: define void @hoist_store( +; CHECK-SAME: ptr [[ARG:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: store ptr null, ptr [[ARG]], align 8 +; CHECK-NEXT: call void @clobber1() +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: else: +; CHECK-NEXT: store ptr null, ptr [[ARG]], align 8, !mmra [[META0]] +; CHECK-NEXT: call void @clobber2() +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +bb: + br i1 %c, label %then, label %else + +then: + store ptr null, ptr %arg, align 8 + call void @clobber1() + br label %exit + +else: + store ptr null, ptr %arg, align 8, !mmra !0 + call void @clobber2() + br label %exit + +exit: + ret void +} + +define ptr @sink_load(ptr %arg, i1 %c) { +; CHECK-LABEL: define ptr @sink_load( +; CHECK-SAME: ptr [[ARG:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: call void @clobber1() +; CHECK-NEXT: [[L1:%.*]] = load ptr, ptr [[ARG]], align 8 +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: else: +; CHECK-NEXT: call void @clobber2() +; CHECK-NEXT: [[L2:%.*]] = load ptr, ptr [[ARG]], align 8, !mmra [[META0]] +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[L1]], [[THEN]] ], [ [[L2]], [[ELSE]] ] +; CHECK-NEXT: ret ptr [[P]] +; +bb: + br i1 %c, label %then, label %else + +then: + call void @clobber1() + %l1 = load ptr, ptr %arg, align 8 + br label %exit + +else: + call void @clobber2() + %l2 = load ptr, ptr %arg, align 8, !mmra !0 + br label %exit + +exit: + %p = phi ptr [ %l1, %then ], [ %l2, %else ] + ret ptr %p +} + +define ptr @hoist_load(ptr %arg, i1 %c) { +; CHECK-LABEL: define ptr @hoist_load( +; CHECK-SAME: ptr [[ARG:%.*]], i1 [[C:%.*]]) { +; CHECK-NEXT: bb: +; CHECK-NEXT: br i1 [[C]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: [[L1:%.*]] = load ptr, ptr [[ARG]], align 8 +; CHECK-NEXT: call void @clobber1() +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: else: +; CHECK-NEXT: [[L2:%.*]] = load ptr, ptr [[ARG]], align 8, !mmra [[META0]] +; CHECK-NEXT: call void @clobber2() +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: [[P:%.*]] = phi ptr [ [[L1]], [[THEN]] ], [ [[L2]], [[ELSE]] ] +; CHECK-NEXT: ret ptr [[P]] +; +bb: + br i1 %c, label %then, label %else + +then: + %l1 = load ptr, ptr %arg, align 8 + call void @clobber1() + br label %exit + +else: + %l2 = load ptr, ptr %arg, align 8, !mmra !0 + call void @clobber2() + br label %exit + +exit: + %p = phi ptr [ %l1, %then ], [ %l2, %else ] + ret ptr %p +} + + +!0 = !{!"foo", !"bar"} + +;. +; CHECK: [[META0]] = !{!"foo", !"bar"} +;. diff --git a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll index a19b205e68a62d92c9bb0db1700edbfa87bb6128..c423053a9a4839adaa7b2def3e405e65e2f3856a 100644 --- a/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll +++ b/llvm/test/Transforms/VectorCombine/X86/shuffle-of-binops.ll @@ -25,9 +25,9 @@ define <4 x float> @shuf_fdiv_v4f32_yy(<4 x float> %x, <4 x float> %y, <4 x floa define <4 x i32> @shuf_add_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { ; CHECK-LABEL: define <4 x i32> @shuf_add_v4i32_xx( ; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> poison, <4 x i32> -; CHECK-NEXT: [[R1:%.*]] = shufflevector <4 x i32> [[Y]], <4 x i32> [[Z]], <4 x i32> -; CHECK-NEXT: [[R2:%.*]] = add <4 x i32> [[TMP1]], [[R1]] +; CHECK-NEXT: [[B0:%.*]] = add <4 x i32> [[X]], [[Y]] +; CHECK-NEXT: [[B1:%.*]] = add <4 x i32> [[X]], [[Z]] +; CHECK-NEXT: [[R2:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> ; CHECK-NEXT: ret <4 x i32> [[R2]] ; %b0 = add <4 x i32> %x, %y @@ -36,15 +36,22 @@ define <4 x i32> @shuf_add_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { ret <4 x i32> %r } -; For commutative instructions, common operand may be swapped. +; For commutative instructions, common operand may be swapped (SSE - expensive fmul vs AVX - cheap fmul) define <4 x float> @shuf_fmul_v4f32_xx_swap(<4 x float> %x, <4 x float> %y, <4 x float> %z) { -; CHECK-LABEL: define <4 x float> @shuf_fmul_v4f32_xx_swap( -; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[Z]], <4 x i32> -; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[X]], <4 x float> poison, <4 x i32> -; CHECK-NEXT: [[R:%.*]] = fmul <4 x float> [[TMP1]], [[TMP2]] -; CHECK-NEXT: ret <4 x float> [[R]] +; SSE-LABEL: define <4 x float> @shuf_fmul_v4f32_xx_swap( +; SSE-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]]) #[[ATTR0]] { +; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[Z]], <4 x i32> +; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[X]], <4 x float> poison, <4 x i32> +; SSE-NEXT: [[R:%.*]] = fmul <4 x float> [[TMP1]], [[TMP2]] +; SSE-NEXT: ret <4 x float> [[R]] +; +; AVX-LABEL: define <4 x float> @shuf_fmul_v4f32_xx_swap( +; AVX-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]]) #[[ATTR0]] { +; AVX-NEXT: [[B0:%.*]] = fmul <4 x float> [[X]], [[Y]] +; AVX-NEXT: [[B1:%.*]] = fmul <4 x float> [[Z]], [[X]] +; AVX-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> +; AVX-NEXT: ret <4 x float> [[R]] ; %b0 = fmul <4 x float> %x, %y %b1 = fmul <4 x float> %z, %x @@ -57,9 +64,9 @@ define <4 x float> @shuf_fmul_v4f32_xx_swap(<4 x float> %x, <4 x float> %y, <4 x define <2 x i64> @shuf_and_v2i64_yy_swap(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z) { ; CHECK-LABEL: define <2 x i64> @shuf_and_v2i64_yy_swap( ; CHECK-SAME: <2 x i64> [[X:%.*]], <2 x i64> [[Y:%.*]], <2 x i64> [[Z:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <2 x i64> [[Y]], <2 x i64> poison, <2 x i32> -; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <2 x i64> [[X]], <2 x i64> [[Z]], <2 x i32> -; CHECK-NEXT: [[R:%.*]] = and <2 x i64> [[TMP1]], [[TMP2]] +; CHECK-NEXT: [[B0:%.*]] = and <2 x i64> [[X]], [[Y]] +; CHECK-NEXT: [[B1:%.*]] = and <2 x i64> [[Y]], [[Z]] +; CHECK-NEXT: [[R:%.*]] = shufflevector <2 x i64> [[B0]], <2 x i64> [[B1]], <2 x i32> ; CHECK-NEXT: ret <2 x i64> [[R]] ; %b0 = and <2 x i64> %x, %y @@ -84,15 +91,22 @@ define <4 x i32> @shuf_shl_v4i32_xx(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { ret <4 x i32> %r } -; negative test - common operand, but not commutable +; common operand, but not commutable (SSE - expensive vector shift vs AVX2 - cheap vector shift) define <4 x i32> @shuf_shl_v4i32_xx_swap(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z) { -; CHECK-LABEL: define <4 x i32> @shuf_shl_v4i32_xx_swap( -; CHECK-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[B0:%.*]] = shl <4 x i32> [[X]], [[Y]] -; CHECK-NEXT: [[B1:%.*]] = shl <4 x i32> [[Z]], [[X]] -; CHECK-NEXT: [[R1:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> -; CHECK-NEXT: ret <4 x i32> [[R1]] +; SSE-LABEL: define <4 x i32> @shuf_shl_v4i32_xx_swap( +; SSE-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { +; SSE-NEXT: [[TMP1:%.*]] = shufflevector <4 x i32> [[X]], <4 x i32> [[Z]], <4 x i32> +; SSE-NEXT: [[TMP2:%.*]] = shufflevector <4 x i32> [[Y]], <4 x i32> [[X]], <4 x i32> +; SSE-NEXT: [[R:%.*]] = shl <4 x i32> [[TMP1]], [[TMP2]] +; SSE-NEXT: ret <4 x i32> [[R]] +; +; AVX-LABEL: define <4 x i32> @shuf_shl_v4i32_xx_swap( +; AVX-SAME: <4 x i32> [[X:%.*]], <4 x i32> [[Y:%.*]], <4 x i32> [[Z:%.*]]) #[[ATTR0]] { +; AVX-NEXT: [[B0:%.*]] = shl <4 x i32> [[X]], [[Y]] +; AVX-NEXT: [[B1:%.*]] = shl <4 x i32> [[Z]], [[X]] +; AVX-NEXT: [[R:%.*]] = shufflevector <4 x i32> [[B0]], <4 x i32> [[B1]], <4 x i32> +; AVX-NEXT: ret <4 x i32> [[R]] ; %b0 = shl <4 x i32> %x, %y %b1 = shl <4 x i32> %z, %x @@ -116,7 +130,7 @@ define <2 x i64> @shuf_sub_add_v2i64_yy(<2 x i64> %x, <2 x i64> %y, <2 x i64> %z ret <2 x i64> %r } -; negative test - type change via shuffle +; type change via shuffle define <8 x float> @shuf_fmul_v4f32_xx_type(<4 x float> %x, <4 x float> %y, <4 x float> %z) { ; CHECK-LABEL: define <8 x float> @shuf_fmul_v4f32_xx_type( @@ -168,14 +182,14 @@ define <4 x i32> @shuf_mul_v4i32_yy_use2(<4 x i32> %x, <4 x i32> %y, <4 x i32> % ret <4 x i32> %r } -; negative test - must have matching operand +; non-matching operands (not commutable) define <4 x float> @shuf_fdiv_v4f32_no_common_op(<4 x float> %x, <4 x float> %y, <4 x float> %z, <4 x float> %w) { ; CHECK-LABEL: define <4 x float> @shuf_fdiv_v4f32_no_common_op( ; CHECK-SAME: <4 x float> [[X:%.*]], <4 x float> [[Y:%.*]], <4 x float> [[Z:%.*]], <4 x float> [[W:%.*]]) #[[ATTR0]] { -; CHECK-NEXT: [[B0:%.*]] = fdiv <4 x float> [[X]], [[Y]] -; CHECK-NEXT: [[B1:%.*]] = fdiv <4 x float> [[Z]], [[W]] -; CHECK-NEXT: [[R:%.*]] = shufflevector <4 x float> [[B0]], <4 x float> [[B1]], <4 x i32> +; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x float> [[X]], <4 x float> [[Z]], <4 x i32> +; CHECK-NEXT: [[TMP2:%.*]] = shufflevector <4 x float> [[Y]], <4 x float> [[W]], <4 x i32> +; CHECK-NEXT: [[R:%.*]] = fdiv <4 x float> [[TMP1]], [[TMP2]] ; CHECK-NEXT: ret <4 x float> [[R]] ; %b0 = fdiv <4 x float> %x, %y @@ -216,6 +230,3 @@ define <4 x i32> @shuf_srem_v4i32_poison(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %r } -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; AVX: {{.*}} -; SSE: {{.*}} diff --git a/llvm/test/Verifier/mmra-allowed.ll b/llvm/test/Verifier/mmra-allowed.ll new file mode 100644 index 0000000000000000000000000000000000000000..76dff3f207cdf3cd848046c57ea58999a43df08b --- /dev/null +++ b/llvm/test/Verifier/mmra-allowed.ll @@ -0,0 +1,31 @@ +; RUN: opt -S -passes=verify < %s + +; This file contains MMRA metadata that is okay and should pass the verifier. + +define void @test(ptr %ptr) { + %ld = load i8, ptr %ptr, !mmra !0 + store i8 1, ptr %ptr, !mmra !1 + call void @writesMem(), !mmra !2 + call void @readsMem(), !mmra !2 + fence release, !mmra !0 + %rmw.1 = atomicrmw add ptr %ptr, i8 0 release, !mmra !0 + %rmw.2 = atomicrmw add ptr %ptr, i8 0 acquire, !mmra !0 + %pair = cmpxchg ptr %ptr, i8 0, i8 1 acquire acquire, !mmra !1 + %ld.atomic = load atomic i8, ptr %ptr acquire, align 4, !mmra !1 + store atomic i8 1, ptr %ptr release, align 4, !mmra !2 + %mld = call <2 x i64> @llvm.vp.load.v2i64.p0(ptr undef, <2 x i1> undef, i32 undef), !mmra !2 + ; TODO: barrier + ret void +} + +declare <2 x i64> @llvm.vp.load.v2i64.p0(ptr, <2 x i1>, i32) + +declare void @readsMem(ptr) #0 +declare void @writesMem(ptr) #1 + +attributes #0 = { memory(read) } +attributes #1 = { memory(write) } + +!0 = !{!"scope", !"workgroup"} +!1 = !{!"as", !"private"} +!2 = !{!0, !1} diff --git a/llvm/test/Verifier/mmra.ll b/llvm/test/Verifier/mmra.ll new file mode 100644 index 0000000000000000000000000000000000000000..b506d593a1c433f4e5b2151a3762049660c7f245 --- /dev/null +++ b/llvm/test/Verifier/mmra.ll @@ -0,0 +1,43 @@ +; RUN: not opt -S -passes=verify < %s 2>&1 | FileCheck %s + +define void @foo(ptr %ptr, i32 %x) { + + ; CHECK: !mmra metadata attached to unexpected instruction kind + ; CHECK-NEXT: %bad.add + %bad.add = add i32 %x, 42, !mmra !{} + + ; CHECK: !mmra metadata attached to unexpected instruction kind + ; CHECK-NEXT: %bad.sub + %bad.sub = sub i32 %x, 42, !mmra !{} + + ; CHECK: !mmra metadata attached to unexpected instruction kind + ; CHECK-NEXT: %bad.sqrt + %bad.sqrt = call float @llvm.sqrt.f32(float undef), !mmra !{} + + ; CHECK: !mmra expected to be a metadata tuple + ; CHECK-NEXT: %bad.md0 + ; CHECK-NEXT: !DIFile + %bad.md0 = load atomic i32, ptr %ptr acquire, align 4, !mmra !0 + + ; CHECK: !mmra expected to be a metadata tuple + ; CHECK-NEXT: %bad.md1 + ; CHECK-NEXT: !DIFile + %bad.md1 = load atomic i32, ptr %ptr acquire, align 4, !mmra !0 + + ; CHECK: !mmra metadata tuple operand is not an MMRA tag + ; CHECK-NEXT: %bad.md2 + ; CHECK-NEXT: !"foo" + %bad.md2 = load atomic i32, ptr %ptr acquire, align 4, !mmra !1 + + ; CHECK: !mmra metadata tuple operand is not an MMRA tag + ; CHECK-NEXT: %bad.md3 + ; CHECK-NEXT: !"baz" + %bad.md3 = load atomic i32, ptr %ptr acquire, align 4, !mmra !2 + ret void +} + +declare float @llvm.sqrt.f32(float) + +!0 = !DIFile(filename: "test.c", directory: "") +!1 = !{!"foo", !"bar", !"bux"} +!2 = !{!"baz", !0} diff --git a/llvm/test/lit.cfg.py b/llvm/test/lit.cfg.py index 4c05317036d1a3802ad0c1160351f1f434967164..affd87b98c1410b4d08f3d0ad4250ecb8815a436 100644 --- a/llvm/test/lit.cfg.py +++ b/llvm/test/lit.cfg.py @@ -306,6 +306,9 @@ def enable_ptxas(ptxas_executable): (11, 8), (12, 0), (12, 1), + (12, 2), + (12, 3), + (12, 4), ] def version_int(ver): diff --git a/llvm/test/tools/llvm-profdata/memprof-merge-v0.test b/llvm/test/tools/llvm-profdata/memprof-merge-v0.test index 03ccbdd42efdad9acbf02aa543f4fa45074b08d6..28f65e0781bc630297ae9fc8bb02517147b4dc35 100644 --- a/llvm/test/tools/llvm-profdata/memprof-merge-v0.test +++ b/llvm/test/tools/llvm-profdata/memprof-merge-v0.test @@ -16,6 +16,9 @@ RUN: llvm-profdata show %t.prof.v1 | FileCheck %s RUN: llvm-profdata merge %t.proftext %p/Inputs/basic.memprofraw --memprof-version=2 --profiled-binary %p/Inputs/basic.memprofexe -o %t.prof.v2 RUN: llvm-profdata show %t.prof.v2 | FileCheck %s +RUN: llvm-profdata merge %t.proftext %p/Inputs/basic.memprofraw --memprof-version=2 --memprof-full-schema --profiled-binary %p/Inputs/basic.memprofexe -o %t.prof.v2 +RUN: llvm-profdata show %t.prof.v2 | FileCheck %s + For now we only check the validity of the instrumented profile since we don't have a way to display the contents of the memprof indexed format yet. diff --git a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp index 09b2a5900eb0b7f272747c0cf76c91ce037c8762..bff05b9ca4bebc90d93d8168b75c8fc962185f9c 100644 --- a/llvm/tools/llvm-jitlink/llvm-jitlink.cpp +++ b/llvm/tools/llvm-jitlink/llvm-jitlink.cpp @@ -807,8 +807,8 @@ static Expected> launchExecutor() { S.CreateMemoryManager = createSharedMemoryManager; return SimpleRemoteEPC::Create( - std::make_unique(), std::move(S), - FromExecutor[ReadEnd], ToExecutor[WriteEnd]); + std::make_unique(std::nullopt), + std::move(S), FromExecutor[ReadEnd], ToExecutor[WriteEnd]); #endif } @@ -897,7 +897,7 @@ static Expected> connectToExecutor() { S.CreateMemoryManager = createSharedMemoryManager; return SimpleRemoteEPC::Create( - std::make_unique(), + std::make_unique(std::nullopt), std::move(S), *SockFD, *SockFD); #endif } diff --git a/llvm/tools/llvm-profdata/llvm-profdata.cpp b/llvm/tools/llvm-profdata/llvm-profdata.cpp index 78daf9f7dc109a2429a38bf7fb34d0ca97f86750..ec046ebfab130b783fb37dab8417e5c6bd9786f3 100644 --- a/llvm/tools/llvm-profdata/llvm-profdata.cpp +++ b/llvm/tools/llvm-profdata/llvm-profdata.cpp @@ -308,6 +308,10 @@ cl::opt MemProfVersionRequested( clEnumValN(memprof::Version1, "1", "version 1"), clEnumValN(memprof::Version2, "2", "version 2"))); +cl::opt MemProfFullSchema( + "memprof-full-schema", cl::Hidden, cl::sub(MergeSubcommand), + cl::desc("Use the full schema for serialization"), cl::init(false)); + // Options specific to overlap subcommand. cl::opt BaseFilename(cl::Positional, cl::Required, cl::desc(""), @@ -600,7 +604,7 @@ struct WriterContext { SmallSet &WriterErrorCodes, uint64_t ReservoirSize = 0, uint64_t MaxTraceLength = 0) : Writer(IsSparse, ReservoirSize, MaxTraceLength, DoWritePrevVersion, - MemProfVersionRequested), + MemProfVersionRequested, MemProfFullSchema), ErrLock(ErrLock), WriterErrorCodes(WriterErrorCodes) {} }; diff --git a/llvm/unittests/Analysis/LoadsTest.cpp b/llvm/unittests/Analysis/LoadsTest.cpp index 0111cfeefa41aecf5a6920cd79d0d865e217e82e..5da3feaf762f37c945bce821cec313233d78a371 100644 --- a/llvm/unittests/Analysis/LoadsTest.cpp +++ b/llvm/unittests/Analysis/LoadsTest.cpp @@ -68,35 +68,49 @@ TEST(LoadsTest, CanReplacePointersIfEqual) { R"IR( @y = common global [1 x i32] zeroinitializer, align 4 @x = common global [1 x i32] zeroinitializer, align 4 - declare void @use(i32*) -define void @f(i32* %p) { +define void @f(i32* %p1, i32* %p2, i64 %i) { call void @use(i32* getelementptr inbounds ([1 x i32], [1 x i32]* @y, i64 0, i64 0)) - call void @use(i32* getelementptr inbounds (i32, i32* getelementptr inbounds ([1 x i32], [1 x i32]* @x, i64 0, i64 0), i64 1)) + + %p1_idx = getelementptr inbounds i32, i32* %p1, i64 %i + call void @use(i32* %p1_idx) + + %icmp = icmp eq i32* %p1, getelementptr inbounds ([1 x i32], [1 x i32]* @y, i64 0, i64 0) + %ptrInt = ptrtoint i32* %p1 to i64 ret void } )IR"); - const auto &DL = M->getDataLayout(); + const DataLayout &DL = M->getDataLayout(); auto *GV = M->getNamedValue("f"); ASSERT_TRUE(GV); auto *F = dyn_cast(GV); ASSERT_TRUE(F); - // NOTE: the implementation of canReplacePointersIfEqual is incomplete. - // Currently the only the cases it returns false for are really sound and - // returning true means unknown. - Value *P = &*F->arg_begin(); + Value *P1 = &*F->arg_begin(); + Value *P2 = F->getArg(1); + Value *NullPtr = Constant::getNullValue(P1->getType()); auto InstIter = F->front().begin(); - Value *ConstDerefPtr = *cast(&*InstIter)->arg_begin(); - // ConstDerefPtr is a constant pointer that is provably de-referenceable. We - // can replace an arbitrary pointer with it. - EXPECT_TRUE(canReplacePointersIfEqual(P, ConstDerefPtr, DL, nullptr)); + CallInst *UserOfY = cast(&*InstIter); + Value *ConstDerefPtr = UserOfY->getArgOperand(0); + // We cannot replace two pointers in arbitrary instructions unless we are + // replacing with null, a constant dereferencable pointer or they have the + // same underlying object. + EXPECT_FALSE(canReplacePointersIfEqual(ConstDerefPtr, P1, DL)); + EXPECT_FALSE(canReplacePointersIfEqual(P1, P2, DL)); + EXPECT_TRUE(canReplacePointersIfEqual(P1, ConstDerefPtr, DL)); + EXPECT_TRUE(canReplacePointersIfEqual(P1, NullPtr, DL)); + + GetElementPtrInst *BasedOnP1 = cast(&*++InstIter); + EXPECT_TRUE(canReplacePointersIfEqual(BasedOnP1, P1, DL)); + EXPECT_FALSE(canReplacePointersIfEqual(BasedOnP1, P2, DL)); - ++InstIter; - Value *ConstUnDerefPtr = *cast(&*InstIter)->arg_begin(); - // ConstUndDerefPtr is a constant pointer that is provably not - // de-referenceable. We cannot replace an arbitrary pointer with it. - EXPECT_FALSE( - canReplacePointersIfEqual(ConstDerefPtr, ConstUnDerefPtr, DL, nullptr)); + // We can replace two arbitrary pointers in icmp and ptrtoint instructions. + auto P1UseIter = P1->use_begin(); + const Use &PtrToIntUse = *P1UseIter; + const Use &IcmpUse = *++P1UseIter; + const Use &GEPUse = *++P1UseIter; + EXPECT_FALSE(canReplacePointersInUseIfEqual(GEPUse, P2, DL)); + EXPECT_TRUE(canReplacePointersInUseIfEqual(PtrToIntUse, P2, DL)); + EXPECT_TRUE(canReplacePointersInUseIfEqual(IcmpUse, P2, DL)); } diff --git a/llvm/unittests/CodeGen/MachineInstrTest.cpp b/llvm/unittests/CodeGen/MachineInstrTest.cpp index 49da0c38eefdca505a0f84b89103cb5e22bf2b19..8ea12a6ec6453cf6dc5a2361fe5359a00539bb56 100644 --- a/llvm/unittests/CodeGen/MachineInstrTest.cpp +++ b/llvm/unittests/CodeGen/MachineInstrTest.cpp @@ -18,6 +18,7 @@ #include "llvm/CodeGen/TargetSubtargetInfo.h" #include "llvm/IR/DebugInfoMetadata.h" #include "llvm/IR/IRBuilder.h" +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" #include "llvm/IR/ModuleSlotTracker.h" #include "llvm/MC/MCAsmInfo.h" #include "llvm/MC/MCSymbol.h" @@ -277,12 +278,14 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) { MCSymbol *Sym2 = MC->createTempSymbol("post_label", false); MDNode *HAM = MDNode::getDistinct(Ctx, std::nullopt); MDNode *PCS = MDNode::getDistinct(Ctx, std::nullopt); + MDNode *MMRA = MMRAMetadata::getTagMD(Ctx, "foo", "bar"); ASSERT_TRUE(MI->memoperands_empty()); ASSERT_FALSE(MI->getPreInstrSymbol()); ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_FALSE(MI->getMMRAMetadata()); MI->setMemRefs(*MF, MMOs); ASSERT_TRUE(MI->memoperands().size() == 1); @@ -290,6 +293,7 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_FALSE(MI->getMMRAMetadata()); MI->setPreInstrSymbol(*MF, Sym1); ASSERT_TRUE(MI->memoperands().size() == 1); @@ -297,6 +301,7 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_FALSE(MI->getMMRAMetadata()); MI->setPostInstrSymbol(*MF, Sym2); ASSERT_TRUE(MI->memoperands().size() == 1); @@ -304,6 +309,7 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) { ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_FALSE(MI->getMMRAMetadata()); MI->setHeapAllocMarker(*MF, HAM); ASSERT_TRUE(MI->memoperands().size() == 1); @@ -311,6 +317,7 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) { ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); ASSERT_FALSE(MI->getPCSections()); + ASSERT_FALSE(MI->getMMRAMetadata()); MI->setPCSections(*MF, PCS); ASSERT_TRUE(MI->memoperands().size() == 1); @@ -318,6 +325,21 @@ TEST(MachineInstrExtraInfo, AddExtraInfo) { ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_FALSE(MI->getMMRAMetadata()); + + MI->setMMRAMetadata(*MF, MMRA); + ASSERT_TRUE(MI->memoperands().size() == 1); + ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); + ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); + ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); + ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA); + + // Check with nothing but MMRAs. + MachineInstr *MMRAMI = MF->CreateMachineInstr(MCID, DebugLoc()); + ASSERT_FALSE(MMRAMI->getMMRAMetadata()); + MMRAMI->setMMRAMetadata(*MF, MMRA); + ASSERT_TRUE(MMRAMI->getMMRAMetadata() == MMRA); } TEST(MachineInstrExtraInfo, ChangeExtraInfo) { @@ -338,11 +360,15 @@ TEST(MachineInstrExtraInfo, ChangeExtraInfo) { MDNode *HAM = MDNode::getDistinct(Ctx, std::nullopt); MDNode *PCS = MDNode::getDistinct(Ctx, std::nullopt); + MDNode *MMRA1 = MMRAMetadata::getTagMD(Ctx, "foo", "bar"); + MDNode *MMRA2 = MMRAMetadata::getTagMD(Ctx, "bar", "bux"); + MI->setMemRefs(*MF, MMOs); MI->setPreInstrSymbol(*MF, Sym1); MI->setPostInstrSymbol(*MF, Sym2); MI->setHeapAllocMarker(*MF, HAM); MI->setPCSections(*MF, PCS); + MI->setMMRAMetadata(*MF, MMRA1); MMOs.push_back(MMO); @@ -352,6 +378,7 @@ TEST(MachineInstrExtraInfo, ChangeExtraInfo) { ASSERT_TRUE(MI->getPostInstrSymbol() == Sym2); ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA1); MI->setPostInstrSymbol(*MF, Sym1); ASSERT_TRUE(MI->memoperands().size() == 2); @@ -359,6 +386,15 @@ TEST(MachineInstrExtraInfo, ChangeExtraInfo) { ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1); ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA1); + + MI->setMMRAMetadata(*MF, MMRA2); + ASSERT_TRUE(MI->memoperands().size() == 2); + ASSERT_TRUE(MI->getPreInstrSymbol() == Sym1); + ASSERT_TRUE(MI->getPostInstrSymbol() == Sym1); + ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); + ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA2); } TEST(MachineInstrExtraInfo, RemoveExtraInfo) { @@ -380,11 +416,14 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) { MDNode *HAM = MDNode::getDistinct(Ctx, std::nullopt); MDNode *PCS = MDNode::getDistinct(Ctx, std::nullopt); + MDNode *MMRA = MDTuple::get(Ctx, {}); + MI->setMemRefs(*MF, MMOs); MI->setPreInstrSymbol(*MF, Sym1); MI->setPostInstrSymbol(*MF, Sym2); MI->setHeapAllocMarker(*MF, HAM); MI->setPCSections(*MF, PCS); + MI->setMMRAMetadata(*MF, MMRA); MI->setPostInstrSymbol(*MF, nullptr); ASSERT_TRUE(MI->memoperands().size() == 2); @@ -392,6 +431,7 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_TRUE(MI->getHeapAllocMarker() == HAM); ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA); MI->setHeapAllocMarker(*MF, nullptr); ASSERT_TRUE(MI->memoperands().size() == 2); @@ -399,6 +439,7 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_TRUE(MI->getPCSections() == PCS); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA); MI->setPCSections(*MF, nullptr); ASSERT_TRUE(MI->memoperands().size() == 2); @@ -406,6 +447,7 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA); MI->setPreInstrSymbol(*MF, nullptr); ASSERT_TRUE(MI->memoperands().size() == 2); @@ -413,6 +455,7 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA); MI->setMemRefs(*MF, {}); ASSERT_TRUE(MI->memoperands_empty()); @@ -420,6 +463,15 @@ TEST(MachineInstrExtraInfo, RemoveExtraInfo) { ASSERT_FALSE(MI->getPostInstrSymbol()); ASSERT_FALSE(MI->getHeapAllocMarker()); ASSERT_FALSE(MI->getPCSections()); + ASSERT_TRUE(MI->getMMRAMetadata() == MMRA); + + MI->setMMRAMetadata(*MF, nullptr); + ASSERT_TRUE(MI->memoperands_empty()); + ASSERT_FALSE(MI->getPreInstrSymbol()); + ASSERT_FALSE(MI->getPostInstrSymbol()); + ASSERT_FALSE(MI->getHeapAllocMarker()); + ASSERT_FALSE(MI->getPCSections()); + ASSERT_FALSE(MI->getMMRAMetadata()); } TEST(MachineInstrDebugValue, AddDebugValueOperand) { diff --git a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp index 5e2b5f35bcf47178ee132f33597b0978d6f6643e..3b24e29e1ed38606529f001a53b512899db890de 100644 --- a/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/CoreAPIsTest.cpp @@ -1005,11 +1005,11 @@ TEST_F(CoreAPIsStandardTest, RedefineBoundWeakSymbol) { TEST_F(CoreAPIsStandardTest, DefineMaterializingSymbol) { bool ExpectNoMoreMaterialization = false; - ES.setDispatchTask([&](std::unique_ptr T) { + DispatchOverride = [&](std::unique_ptr T) { if (ExpectNoMoreMaterialization && isa(*T)) ADD_FAILURE() << "Unexpected materialization"; T->run(); - }); + }; auto MU = std::make_unique( SymbolFlagsMap({{Foo, FooSym.getFlags()}}), @@ -1403,7 +1403,7 @@ TEST_F(CoreAPIsStandardTest, TestLookupWithThreadedMaterialization) { std::mutex WorkThreadsMutex; std::vector WorkThreads; - ES.setDispatchTask([&](std::unique_ptr T) { + DispatchOverride = [&](std::unique_ptr T) { std::promise WaitP; std::lock_guard Lock(WorkThreadsMutex); WorkThreads.push_back( @@ -1412,7 +1412,7 @@ TEST_F(CoreAPIsStandardTest, TestLookupWithThreadedMaterialization) { T->run(); })); WaitP.set_value(); - }); + }; cantFail(JD.define(absoluteSymbols({{Foo, FooSym}}))); diff --git a/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.cpp b/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.cpp index bc87df1fe8c6a911785279f24082752a63e0a66a..307f14dfe24d034ede6953cbb676e68e13c46087 100644 --- a/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.cpp @@ -22,3 +22,18 @@ ModuleBuilder::ModuleBuilder(LLVMContext &Context, StringRef Triple, if (Triple != "") M->setTargetTriple(Triple); } + +void llvm::orc::CoreAPIsBasedStandardTest::OverridableDispatcher::dispatch( + std::unique_ptr T) { + if (Parent.DispatchOverride) + Parent.DispatchOverride(std::move(T)); + else + InPlaceTaskDispatcher::dispatch(std::move(T)); +} + +std::unique_ptr +llvm::orc::CoreAPIsBasedStandardTest::makeEPC( + std::shared_ptr SSP) { + return std::make_unique( + std::move(SSP), std::make_unique(*this)); +} diff --git a/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h b/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h index ce7da76c9653a32aba24a57e64c672833c57b022..0981f4b8132bd0aebb389fa813f89ea074c00877 100644 --- a/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h +++ b/llvm/unittests/ExecutionEngine/Orc/OrcTestCommon.h @@ -52,8 +52,20 @@ public: } protected: + class OverridableDispatcher : public InPlaceTaskDispatcher { + public: + OverridableDispatcher(CoreAPIsBasedStandardTest &Parent) : Parent(Parent) {} + void dispatch(std::unique_ptr T) override; + + private: + CoreAPIsBasedStandardTest &Parent; + }; + + std::unique_ptr + makeEPC(std::shared_ptr SSP); + std::shared_ptr SSP = std::make_shared(); - ExecutionSession ES{std::make_unique(SSP)}; + ExecutionSession ES{makeEPC(SSP)}; JITDylib &JD = ES.createBareJITDylib("JD"); SymbolStringPtr Foo = ES.intern("foo"); SymbolStringPtr Bar = ES.intern("bar"); @@ -67,6 +79,7 @@ protected: ExecutorSymbolDef BarSym{BarAddr, JITSymbolFlags::Exported}; ExecutorSymbolDef BazSym{BazAddr, JITSymbolFlags::Exported}; ExecutorSymbolDef QuxSym{QuxAddr, JITSymbolFlags::Exported}; + unique_function)> DispatchOverride; }; } // end namespace orc diff --git a/llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp b/llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp index 83d386c631dddb2ce41fd922bc5ac8d3b9ca76a9..6af0d60cf8ae6a00b56c0d21380942fcae35fb15 100644 --- a/llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp +++ b/llvm/unittests/ExecutionEngine/Orc/TaskDispatchTest.cpp @@ -24,7 +24,7 @@ TEST(InPlaceTaskDispatchTest, GenericNamedTask) { #if LLVM_ENABLE_THREADS TEST(DynamicThreadPoolDispatchTest, GenericNamedTask) { - auto D = std::make_unique(); + auto D = std::make_unique(std::nullopt); std::promise P; auto F = P.get_future(); D->dispatch(makeGenericNamedTask( diff --git a/llvm/unittests/Frontend/OpenMPCompositionTest.cpp b/llvm/unittests/Frontend/OpenMPCompositionTest.cpp index 8a5117226d5a894de73b62bacece4f366153c2ac..920b445427e7e8adcc56eae79dfdc0a5605f396c 100644 --- a/llvm/unittests/Frontend/OpenMPCompositionTest.cpp +++ b/llvm/unittests/Frontend/OpenMPCompositionTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallVector.h" #include "llvm/Frontend/OpenMP/OMP.h" #include "gtest/gtest.h" @@ -40,6 +41,37 @@ TEST(Composition, GetCompoundConstruct) { ASSERT_EQ(C7, OMPD_do_simd); // Make sure it's not OMPD_end_do_simd } +TEST(Composition, GetLeafOrCompositeConstructs) { + SmallVector Out1; + auto Ret1 = getLeafOrCompositeConstructs( + OMPD_target_teams_distribute_parallel_for, Out1); + ASSERT_EQ(Ret1, ArrayRef(Out1)); + ASSERT_EQ((ArrayRef(Out1)), + (ArrayRef{OMPD_target, OMPD_teams, + OMPD_distribute_parallel_for})); + + SmallVector Out2; + auto Ret2 = + getLeafOrCompositeConstructs(OMPD_parallel_masked_taskloop_simd, Out2); + ASSERT_EQ(Ret2, ArrayRef(Out2)); + ASSERT_EQ( + (ArrayRef(Out2)), + (ArrayRef{OMPD_parallel, OMPD_masked, OMPD_taskloop_simd})); + + SmallVector Out3; + auto Ret3 = + getLeafOrCompositeConstructs(OMPD_distribute_parallel_do_simd, Out3); + ASSERT_EQ(Ret3, ArrayRef(Out3)); + ASSERT_EQ((ArrayRef(Out3)), + (ArrayRef{OMPD_distribute_parallel_do_simd})); + + SmallVector Out4; + auto Ret4 = getLeafOrCompositeConstructs(OMPD_target_parallel_loop, Out4); + ASSERT_EQ(Ret4, ArrayRef(Out4)); + ASSERT_EQ((ArrayRef(Out4)), + (ArrayRef{OMPD_target, OMPD_parallel, OMPD_loop})); +} + TEST(Composition, IsLeafConstruct) { ASSERT_TRUE(isLeafConstruct(OMPD_loop)); ASSERT_TRUE(isLeafConstruct(OMPD_teams)); diff --git a/llvm/unittests/IR/CMakeLists.txt b/llvm/unittests/IR/CMakeLists.txt index 803164b8f1eac635fe224a725558b390c24570ba..a03b0711ba33f018a5640893f1de17332994796b 100644 --- a/llvm/unittests/IR/CMakeLists.txt +++ b/llvm/unittests/IR/CMakeLists.txt @@ -31,6 +31,7 @@ add_llvm_unittest(IRTests IntrinsicsTest.cpp LegacyPassManagerTest.cpp MDBuilderTest.cpp + MemoryModelRelaxationAnnotationsTest.cpp ManglerTest.cpp MetadataTest.cpp ModuleTest.cpp diff --git a/llvm/unittests/IR/IntrinsicsTest.cpp b/llvm/unittests/IR/IntrinsicsTest.cpp index a500346b66a5e40d895a8fc7191ddb42850e7975..3fa4b2cf73b6be73471e30e6df28802e2f6f7a40 100644 --- a/llvm/unittests/IR/IntrinsicsTest.cpp +++ b/llvm/unittests/IR/IntrinsicsTest.cpp @@ -6,7 +6,12 @@ // //===----------------------------------------------------------------------===// +#include "llvm/IR/Intrinsics.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/IR/Constant.h" +#include "llvm/IR/IRBuilder.h" #include "llvm/IR/IntrinsicInst.h" +#include "llvm/IR/Module.h" #include "gtest/gtest.h" using namespace llvm; @@ -14,14 +19,41 @@ using namespace llvm; namespace { static const char *const NameTable1[] = { - "llvm.foo", - "llvm.foo.a", - "llvm.foo.b", - "llvm.foo.b.a", - "llvm.foo.c", + "llvm.foo", "llvm.foo.a", "llvm.foo.b", "llvm.foo.b.a", "llvm.foo.c", }; -TEST(IntrinNameLookup, Basic) { +class IntrinsicsTest : public ::testing::Test { + LLVMContext Context; + std::unique_ptr M; + BasicBlock *BB = nullptr; + + void TearDown() override { M.reset(); } + + void SetUp() override { + M = std::make_unique("Test", Context); + auto F = M->getOrInsertFunction( + "test", FunctionType::get(Type::getVoidTy(Context), false)); + BB = BasicBlock::Create(Context, "", cast(F.getCallee())); + EXPECT_NE(BB, nullptr); + } + +public: + Instruction *makeIntrinsic(Intrinsic::ID ID) const { + IRBuilder<> Builder(BB); + SmallVector ProcessedArgs; + auto *Decl = Intrinsic::getDeclaration(M.get(), ID); + for (auto *Ty : Decl->getFunctionType()->params()) { + auto *Val = Constant::getNullValue(Ty); + ProcessedArgs.push_back(Val); + } + return Builder.CreateCall(Decl, ProcessedArgs); + } + template void checkIsa(const Instruction &I) { + EXPECT_TRUE(isa(I)); + } +}; + +TEST(IntrinsicNameLookup, Basic) { int I = Intrinsic::lookupLLVMIntrinsicByName(NameTable1, "llvm.foo"); EXPECT_EQ(0, I); I = Intrinsic::lookupLLVMIntrinsicByName(NameTable1, "llvm.foo.f64"); @@ -36,4 +68,43 @@ TEST(IntrinNameLookup, Basic) { EXPECT_EQ(4, I); } +TEST_F(IntrinsicsTest, InstrProfInheritance) { + auto isInstrProfInstBase = [](const Instruction &I) { + return isa(I); + }; +#define __ISA(TYPE, PARENT) \ + auto is##TYPE = [&](const Instruction &I) -> bool { \ + return isa(I) && is##PARENT(I); \ + } + __ISA(InstrProfCntrInstBase, InstrProfInstBase); + __ISA(InstrProfMCDCCondBitmapUpdate, InstrProfInstBase); + __ISA(InstrProfCoverInst, InstrProfCntrInstBase); + __ISA(InstrProfIncrementInst, InstrProfCntrInstBase); + __ISA(InstrProfIncrementInstStep, InstrProfIncrementInst); + __ISA(InstrProfTimestampInst, InstrProfCntrInstBase); + __ISA(InstrProfValueProfileInst, InstrProfCntrInstBase); + __ISA(InstrProfMCDCBitmapInstBase, InstrProfInstBase); + __ISA(InstrProfMCDCBitmapParameters, InstrProfMCDCBitmapInstBase); + __ISA(InstrProfMCDCTVBitmapUpdate, InstrProfMCDCBitmapInstBase); +#undef __ISA + + std::vector< + std::pair>> + LeafIDs = { + {Intrinsic::instrprof_cover, isInstrProfCoverInst}, + {Intrinsic::instrprof_increment, isInstrProfIncrementInst}, + {Intrinsic::instrprof_increment_step, isInstrProfIncrementInstStep}, + {Intrinsic::instrprof_mcdc_condbitmap_update, + isInstrProfMCDCCondBitmapUpdate}, + {Intrinsic::instrprof_mcdc_parameters, + isInstrProfMCDCBitmapParameters}, + {Intrinsic::instrprof_mcdc_tvbitmap_update, + isInstrProfMCDCTVBitmapUpdate}, + {Intrinsic::instrprof_timestamp, isInstrProfTimestampInst}, + {Intrinsic::instrprof_value_profile, isInstrProfValueProfileInst}}; + for (const auto &[ID, Checker] : LeafIDs) { + auto *Intr = makeIntrinsic(ID); + EXPECT_TRUE(Checker(*Intr)); + } +} } // end namespace diff --git a/llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp b/llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp new file mode 100644 index 0000000000000000000000000000000000000000..8feeb8af65a76e5730aebbd3cb103dd15e7609a2 --- /dev/null +++ b/llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp @@ -0,0 +1,212 @@ +//===- llvm/unittests/IR/MemoryModelRelaxationAnnotationsTest.cpp ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/IR/MemoryModelRelaxationAnnotations.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/IR/Metadata.h" +#include "llvm/IR/Module.h" +#include "gtest/gtest.h" + +using namespace llvm; + +namespace { + +void checkMMRA(const MMRAMetadata &MMRA, + ArrayRef Expected) { + EXPECT_EQ(MMRA.size(), Expected.size()); + for (const auto &E : Expected) + EXPECT_TRUE(MMRA.hasTag(E.first, E.second)); +} + +MMRAMetadata createFromMD(LLVMContext &Ctx, + ArrayRef Expected) { + SmallVector MD; + for (const auto &Tag : Expected) + MD.push_back(MMRAMetadata::getTagMD(Ctx, Tag)); + return MDTuple::get(Ctx, MD); +} + +TEST(MMRATest, MDParse) { + LLVMContext Ctx; + + // No nesting: + // !{!"foo", "!bar"} + MDNode *FooBar = + MDTuple::get(Ctx, {MDString::get(Ctx, "foo"), MDString::get(Ctx, "bar")}); + MMRAMetadata FooBarMMRA(FooBar); + + checkMMRA(FooBarMMRA, {{"foo", "bar"}}); + + // Nested: + // !{!{!"foo", "!bar"}, !{!"bux", !"qux"}} + MDNode *BuxQux = + MDTuple::get(Ctx, {MDString::get(Ctx, "bux"), MDString::get(Ctx, "qux")}); + MDNode *Nested = MDTuple::get(Ctx, {FooBar, BuxQux}); + MMRAMetadata NestedMMRA(Nested); + + checkMMRA(NestedMMRA, {{"foo", "bar"}, {"bux", "qux"}}); +} + +TEST(MMRATest, GetMD) { + LLVMContext Ctx; + + EXPECT_EQ(MMRAMetadata::getMD(Ctx, {}), nullptr); + + MDTuple *SingleMD = MMRAMetadata::getMD(Ctx, {{"foo", "bar"}}); + EXPECT_EQ(SingleMD->getNumOperands(), 2u); + EXPECT_EQ(cast(SingleMD->getOperand(0))->getString(), "foo"); + EXPECT_EQ(cast(SingleMD->getOperand(1))->getString(), "bar"); + + MDTuple *MultiMD = MMRAMetadata::getMD(Ctx, {{"foo", "bar"}, {"bux", "qux"}}); + EXPECT_EQ(MultiMD->getNumOperands(), 2u); + + MDTuple *FooBar = cast(MultiMD->getOperand(0)); + EXPECT_EQ(cast(FooBar->getOperand(0))->getString(), "foo"); + EXPECT_EQ(cast(FooBar->getOperand(1))->getString(), "bar"); + MDTuple *BuxQux = cast(MultiMD->getOperand(1)); + EXPECT_EQ(cast(BuxQux->getOperand(0))->getString(), "bux"); + EXPECT_EQ(cast(BuxQux->getOperand(1))->getString(), "qux"); +} + +TEST(MMRATest, Utility) { + LLVMContext Ctx; + MMRAMetadata MMRA = + createFromMD(Ctx, {{"foo", "0"}, {"foo", "1"}, {"bar", "x"}}); + + EXPECT_TRUE(MMRA.hasTagWithPrefix("foo")); + EXPECT_TRUE(MMRA.hasTagWithPrefix("bar")); + EXPECT_FALSE(MMRA.hasTagWithPrefix("x")); + + EXPECT_TRUE(MMRA.hasTag("foo", "0")); + EXPECT_TRUE(MMRA.hasTag("foo", "1")); + EXPECT_TRUE(MMRA.hasTag("bar", "x")); +} + +TEST(MMRATest, Operators) { + LLVMContext Ctx; + + MMRAMetadata A = createFromMD(Ctx, {{"foo", "0"}, {"bar", "x"}}); + MMRAMetadata B = createFromMD(Ctx, {{"foo", "0"}, {"bar", "y"}}); + + // ensure we have different objects by creating copies. + EXPECT_EQ(MMRAMetadata(A), MMRAMetadata(A)); + EXPECT_TRUE((bool)A); + + EXPECT_EQ(MMRAMetadata(B), MMRAMetadata(B)); + EXPECT_TRUE((bool)B); + + EXPECT_NE(A, B); + + EXPECT_EQ(MMRAMetadata(), MMRAMetadata()); + EXPECT_NE(A, MMRAMetadata()); + EXPECT_NE(B, MMRAMetadata()); + + MMRAMetadata Empty; + EXPECT_FALSE((bool)Empty); +} + +TEST(MMRATest, Compatibility) { + LLVMContext Ctx; + + MMRAMetadata Foo0 = createFromMD(Ctx, {{"foo", "0"}}); + MMRAMetadata Foo1 = createFromMD(Ctx, {{"foo", "1"}}); + MMRAMetadata Foo10 = createFromMD(Ctx, {{"foo", "0"}, {"foo", "1"}}); + + MMRAMetadata Bar = createFromMD(Ctx, {{"bar", "y"}}); + + MMRAMetadata Empty; + + // Other set has no tag with same prefix + EXPECT_TRUE(Foo0.isCompatibleWith(Bar)); + EXPECT_TRUE(Bar.isCompatibleWith(Foo0)); + + EXPECT_TRUE(Foo0.isCompatibleWith(Empty)); + EXPECT_TRUE(Empty.isCompatibleWith(Foo0)); + + EXPECT_TRUE(Empty.isCompatibleWith(MMRAMetadata())); + EXPECT_TRUE(MMRAMetadata().isCompatibleWith(Empty)); + + // Other set has conflicting tags. + EXPECT_FALSE(Foo1.isCompatibleWith(Foo0)); + EXPECT_FALSE(Foo0.isCompatibleWith(Foo1)); + + // Both have common tags. + EXPECT_TRUE(Foo0.isCompatibleWith(Foo0)); + EXPECT_TRUE(Foo0.isCompatibleWith(Foo10)); + EXPECT_TRUE(Foo10.isCompatibleWith(Foo0)); + + EXPECT_TRUE(Foo1.isCompatibleWith(Foo1)); + EXPECT_TRUE(Foo1.isCompatibleWith(Foo10)); + EXPECT_TRUE(Foo10.isCompatibleWith(Foo1)); + + // Try with more prefixes now: + MMRAMetadata Multiple0 = + createFromMD(Ctx, {{"foo", "y"}, {"foo", "x"}, {"bar", "z"}}); + MMRAMetadata Multiple1 = + createFromMD(Ctx, {{"foo", "z"}, {"foo", "x"}, {"bar", "y"}}); + MMRAMetadata Multiple2 = + createFromMD(Ctx, {{"foo", "z"}, {"foo", "x"}, {"bux", "y"}}); + + // Multiple0 and Multiple1 are not compatible because "bar" is getting in the + // way. + EXPECT_FALSE(Multiple0.isCompatibleWith(Multiple1)); + EXPECT_FALSE(Multiple1.isCompatibleWith(Multiple0)); + + EXPECT_TRUE(Multiple0.isCompatibleWith(Empty)); + EXPECT_TRUE(Empty.isCompatibleWith(Multiple0)); + EXPECT_TRUE(Multiple1.isCompatibleWith(Empty)); + EXPECT_TRUE(Empty.isCompatibleWith(Multiple1)); + + // Multiple2 is compatible with both 1/0 because there is always "foo:x" in + // common, and the other prefixes are unique to each set. + EXPECT_TRUE(Multiple2.isCompatibleWith(Multiple0)); + EXPECT_TRUE(Multiple0.isCompatibleWith(Multiple2)); + EXPECT_TRUE(Multiple2.isCompatibleWith(Multiple1)); + EXPECT_TRUE(Multiple1.isCompatibleWith(Multiple2)); +} + +TEST(MMRATest, Combine) { + LLVMContext Ctx; + + MMRAMetadata Foo0 = createFromMD(Ctx, {{"foo", "0"}}); + MMRAMetadata Foo10 = createFromMD(Ctx, {{"foo", "0"}, {"foo", "1"}}); + MMRAMetadata Bar0 = createFromMD(Ctx, {{"bar", "0"}}); + MMRAMetadata BarFoo0 = createFromMD(Ctx, {{"bar", "0"}, {"foo", "0"}}); + + { + // foo is common to both sets + MMRAMetadata Combined = MMRAMetadata::combine(Ctx, Foo0, Foo10); + EXPECT_EQ(Combined, Foo10); + } + + { + // nothing is common + MMRAMetadata Combined = MMRAMetadata::combine(Ctx, Foo0, Bar0); + EXPECT_TRUE(Combined.empty()); + } + + { + // only foo is common. + MMRAMetadata Combined = MMRAMetadata::combine(Ctx, BarFoo0, Foo0); + EXPECT_EQ(Combined, Foo0); + } + + { + // only bar is common. + MMRAMetadata Combined = MMRAMetadata::combine(Ctx, BarFoo0, Bar0); + EXPECT_EQ(Combined, Bar0); + } + + { + // only foo is common + MMRAMetadata Combined = MMRAMetadata::combine(Ctx, BarFoo0, Foo10); + EXPECT_EQ(Combined, Foo10); + } +} + +} // namespace diff --git a/llvm/unittests/IR/PatternMatch.cpp b/llvm/unittests/IR/PatternMatch.cpp index f0377eae9989fd640fe4a8ce503fd71bc522167b..a25885faa3a44225cfe346171d6fccf0a10c39c8 100644 --- a/llvm/unittests/IR/PatternMatch.cpp +++ b/llvm/unittests/IR/PatternMatch.cpp @@ -1995,7 +1995,7 @@ TEST_F(PatternMatchTest, VScale) { EXPECT_TRUE(match(PtrToInt2, m_VScale())); } -TEST_F(PatternMatchTest, NotForbidUndef) { +TEST_F(PatternMatchTest, NotForbidPoison) { Type *ScalarTy = IRB.getInt8Ty(); Type *VectorTy = FixedVectorType::get(ScalarTy, 3); Constant *ScalarUndef = UndefValue::get(ScalarTy); @@ -2020,23 +2020,33 @@ TEST_F(PatternMatchTest, NotForbidUndef) { Value *X; EXPECT_TRUE(match(Not, m_Not(m_Value(X)))); EXPECT_TRUE(match(X, m_Zero())); + X = nullptr; + EXPECT_TRUE(match(Not, m_NotForbidPoison(m_Value(X)))); + EXPECT_TRUE(match(X, m_Zero())); Value *NotCommute = IRB.CreateXor(VectorOnes, VectorZero); Value *Y; EXPECT_TRUE(match(NotCommute, m_Not(m_Value(Y)))); EXPECT_TRUE(match(Y, m_Zero())); + Y = nullptr; + EXPECT_TRUE(match(NotCommute, m_NotForbidPoison(m_Value(Y)))); + EXPECT_TRUE(match(Y, m_Zero())); Value *NotWithUndefs = IRB.CreateXor(VectorZero, VectorMixedUndef); EXPECT_FALSE(match(NotWithUndefs, m_Not(m_Value()))); + EXPECT_FALSE(match(NotWithUndefs, m_NotForbidPoison(m_Value()))); Value *NotWithPoisons = IRB.CreateXor(VectorZero, VectorMixedPoison); EXPECT_TRUE(match(NotWithPoisons, m_Not(m_Value()))); + EXPECT_FALSE(match(NotWithPoisons, m_NotForbidPoison(m_Value()))); Value *NotWithUndefsCommute = IRB.CreateXor(VectorMixedUndef, VectorZero); EXPECT_FALSE(match(NotWithUndefsCommute, m_Not(m_Value()))); + EXPECT_FALSE(match(NotWithUndefsCommute, m_NotForbidPoison(m_Value()))); Value *NotWithPoisonsCommute = IRB.CreateXor(VectorMixedPoison, VectorZero); EXPECT_TRUE(match(NotWithPoisonsCommute, m_Not(m_Value()))); + EXPECT_FALSE(match(NotWithPoisonsCommute, m_NotForbidPoison(m_Value()))); } template struct MutableConstTest : PatternMatchTest { }; diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index 73ba0a23ea5f450e07981a9d517fe4cabd27c989..edc427dcbc454001add8b4cd435a74fbe256c2e3 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -370,12 +370,31 @@ static CallStackIdMapTy getCallStackMapping() { return Mapping; } +// Populate all of the fields of MIB. +MemInfoBlock makeFullMIB() { + MemInfoBlock MIB; +#define MIBEntryDef(NameTag, Name, Type) MIB.NameTag; +#include "llvm/ProfileData/MIBEntryDef.inc" +#undef MIBEntryDef + return MIB; +} + +// Populate those fields returned by getHotColdSchema. +MemInfoBlock makePartialMIB() { + MemInfoBlock MIB; + MIB.AllocCount = 1; + MIB.TotalSize = 5; + MIB.TotalLifetime = 10; + MIB.TotalLifetimeAccessDensity = 23; + return MIB; +} + IndexedMemProfRecord makeRecord( std::initializer_list> AllocFrames, std::initializer_list> CallSiteFrames, - const MemInfoBlock &Block = MemInfoBlock()) { + const MemInfoBlock &Block = makeFullMIB()) { llvm::memprof::IndexedMemProfRecord MR; for (const auto &Frames : AllocFrames) MR.AllocSites.emplace_back(Frames, llvm::memprof::hashCallStack(Frames), @@ -388,7 +407,7 @@ IndexedMemProfRecord makeRecord( IndexedMemProfRecord makeRecordV2(std::initializer_list<::llvm::memprof::CallStackId> AllocFrames, std::initializer_list<::llvm::memprof::CallStackId> CallSiteFrames, - const MemInfoBlock &Block = MemInfoBlock()) { + const MemInfoBlock &Block) { llvm::memprof::IndexedMemProfRecord MR; for (const auto &CSId : AllocFrames) // We don't populate IndexedAllocationInfo::CallStack because we use it only @@ -476,15 +495,56 @@ TEST_F(InstrProfTest, test_memprof_v0) { EXPECT_THAT(WantRecord, EqualsRecord(Record)); } -TEST_F(InstrProfTest, test_memprof_v2) { +struct CallStackIdConverter { + std::optional LastUnmappedFrameId; + std::optional LastUnmappedCSId; + + const FrameIdMapTy &IdToFrameMap; + const CallStackIdMapTy &CSIdToCallStackMap; + + CallStackIdConverter() = delete; + CallStackIdConverter(const FrameIdMapTy &IdToFrameMap, + const CallStackIdMapTy &CSIdToCallStackMap) + : IdToFrameMap(IdToFrameMap), CSIdToCallStackMap(CSIdToCallStackMap) {} + + llvm::SmallVector + operator()(::llvm::memprof::CallStackId CSId) { + auto IdToFrameCallback = [&](const memprof::FrameId Id) { + auto Iter = IdToFrameMap.find(Id); + if (Iter == IdToFrameMap.end()) { + LastUnmappedFrameId = Id; + return memprof::Frame(0, 0, 0, false); + } + return Iter->second; + }; + + llvm::SmallVector Frames; + auto CSIter = CSIdToCallStackMap.find(CSId); + if (CSIter == CSIdToCallStackMap.end()) { + LastUnmappedCSId = CSId; + } else { + const ::llvm::SmallVector<::llvm::memprof::FrameId> &CS = + CSIter->getSecond(); + Frames.reserve(CS.size()); + for (::llvm::memprof::FrameId Id : CS) + Frames.push_back(IdToFrameCallback(Id)); + } + return Frames; + } +}; + +TEST_F(InstrProfTest, test_memprof_v2_full_schema) { + const MemInfoBlock MIB = makeFullMIB(); + Writer.setMemProfVersionRequested(memprof::Version2); + Writer.setMemProfFullSchema(true); ASSERT_THAT_ERROR(Writer.mergeProfileKind(InstrProfKind::MemProf), Succeeded()); const IndexedMemProfRecord IndexedMR = makeRecordV2( /*AllocFrames=*/{0x111, 0x222}, - /*CallSiteFrames=*/{0x333}); + /*CallSiteFrames=*/{0x333}, MIB); const FrameIdMapTy IdToFrameMap = getFrameMapping(); const auto CSIdToCallStackMap = getCallStackMapping(); for (const auto &I : IdToFrameMap) { @@ -502,38 +562,54 @@ TEST_F(InstrProfTest, test_memprof_v2) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - std::optional LastUnmappedFrameId; - auto IdToFrameCallback = [&](const memprof::FrameId Id) { - auto Iter = IdToFrameMap.find(Id); - if (Iter == IdToFrameMap.end()) { - LastUnmappedFrameId = Id; - return memprof::Frame(0, 0, 0, false); - } - return Iter->second; - }; + CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); - std::optional<::llvm::memprof::CallStackId> LastUnmappedCSId; - auto CSIdToCallStackCallback = [&](::llvm::memprof::CallStackId CSId) { - llvm::SmallVector Frames; - auto CSIter = CSIdToCallStackMap.find(CSId); - if (CSIter == CSIdToCallStackMap.end()) { - LastUnmappedCSId = CSId; - } else { - const ::llvm::SmallVector<::llvm::memprof::FrameId> &CS = - CSIter->getSecond(); - Frames.reserve(CS.size()); - for (::llvm::memprof::FrameId Id : CS) - Frames.push_back(IdToFrameCallback(Id)); - } - return Frames; - }; + const ::llvm::memprof::MemProfRecord WantRecord = + IndexedMR.toMemProfRecord(CSIdConv); + ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) + << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; + ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; + EXPECT_THAT(WantRecord, EqualsRecord(Record)); +} + +TEST_F(InstrProfTest, test_memprof_v2_partial_schema) { + const MemInfoBlock MIB = makePartialMIB(); + + Writer.setMemProfVersionRequested(memprof::Version2); + Writer.setMemProfFullSchema(false); + + ASSERT_THAT_ERROR(Writer.mergeProfileKind(InstrProfKind::MemProf), + Succeeded()); + + const IndexedMemProfRecord IndexedMR = makeRecordV2( + /*AllocFrames=*/{0x111, 0x222}, + /*CallSiteFrames=*/{0x333}, MIB); + const FrameIdMapTy IdToFrameMap = getFrameMapping(); + const auto CSIdToCallStackMap = getCallStackMapping(); + for (const auto &I : IdToFrameMap) { + Writer.addMemProfFrame(I.first, I.getSecond(), Err); + } + for (const auto &I : CSIdToCallStackMap) { + Writer.addMemProfCallStack(I.first, I.getSecond(), Err); + } + Writer.addMemProfRecord(/*Id=*/0x9999, IndexedMR); + + auto Profile = Writer.writeBuffer(); + readProfile(std::move(Profile)); + + auto RecordOr = Reader->getMemProfRecord(0x9999); + ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); + const memprof::MemProfRecord &Record = RecordOr.get(); + + CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); const ::llvm::memprof::MemProfRecord WantRecord = - IndexedMR.toMemProfRecord(CSIdToCallStackCallback); - ASSERT_EQ(LastUnmappedFrameId, std::nullopt) - << "could not map frame id: " << *LastUnmappedFrameId; - ASSERT_EQ(LastUnmappedCSId, std::nullopt) - << "could not map call stack id: " << *LastUnmappedCSId; + IndexedMR.toMemProfRecord(CSIdConv); + ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) + << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; + ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } diff --git a/llvm/unittests/Support/CMakeLists.txt b/llvm/unittests/Support/CMakeLists.txt index 15a126279125c5bc8e307500248d2ad5f826aa98..2718be8450f80580d52b362169ccef660e293d7d 100644 --- a/llvm/unittests/Support/CMakeLists.txt +++ b/llvm/unittests/Support/CMakeLists.txt @@ -71,7 +71,6 @@ add_llvm_unittest(SupportTests ReverseIterationTest.cpp ReplaceFileTest.cpp RISCVAttributeParserTest.cpp - RISCVISAInfoTest.cpp ScaledNumberTest.cpp ScopedPrinterTest.cpp SHA256.cpp diff --git a/llvm/unittests/TargetParser/CMakeLists.txt b/llvm/unittests/TargetParser/CMakeLists.txt index 3bbc74f3f8d3212745cf551195e3c517c51a2bc9..086c57903716f59f5bfd20873db6b052844ef3b2 100644 --- a/llvm/unittests/TargetParser/CMakeLists.txt +++ b/llvm/unittests/TargetParser/CMakeLists.txt @@ -6,6 +6,7 @@ set(LLVM_LINK_COMPONENTS add_llvm_unittest(TargetParserTests CSKYTargetParserTest.cpp Host.cpp + RISCVISAInfoTest.cpp RISCVTargetParserTest.cpp TargetParserTest.cpp TripleTest.cpp diff --git a/llvm/unittests/Support/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp similarity index 93% rename from llvm/unittests/Support/RISCVISAInfoTest.cpp rename to llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index caf7bf0a317174b56a52da48ac246f072497311c..81b7e2e527d966141aaef3a2caf453fe86a12fd4 100644 --- a/llvm/unittests/Support/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -6,8 +6,8 @@ // //===----------------------------------------------------------------------===// +#include "llvm/TargetParser/RISCVISAInfo.h" #include "llvm/ADT/StringMap.h" -#include "llvm/Support/RISCVISAInfo.h" #include "llvm/Testing/Support/Error.h" #include "gtest/gtest.h" @@ -15,8 +15,8 @@ using ::testing::ElementsAre; using namespace llvm; -bool operator==(const RISCVISAInfo::ExtensionVersion &A, - const RISCVISAInfo::ExtensionVersion &B) { +bool operator==(const RISCVISAUtils::ExtensionVersion &A, + const RISCVISAUtils::ExtensionVersion &B) { return A.Major == B.Major && A.Minor == B.Minor; } @@ -51,7 +51,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) { RISCVISAInfo &InfoRV32I = **MaybeRV32I; EXPECT_EQ(InfoRV32I.getExtensions().size(), 1UL); EXPECT_TRUE(InfoRV32I.getExtensions().at("i") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32I.getXLen(), 32U); auto MaybeRV32E = RISCVISAInfo::parseNormalizedArchString("rv32e2p0"); @@ -59,7 +59,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) { RISCVISAInfo &InfoRV32E = **MaybeRV32E; EXPECT_EQ(InfoRV32E.getExtensions().size(), 1UL); EXPECT_TRUE(InfoRV32E.getExtensions().at("e") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32E.getXLen(), 32U); auto MaybeRV64I = RISCVISAInfo::parseNormalizedArchString("rv64i2p0"); @@ -67,7 +67,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) { RISCVISAInfo &InfoRV64I = **MaybeRV64I; EXPECT_EQ(InfoRV64I.getExtensions().size(), 1UL); EXPECT_TRUE(InfoRV64I.getExtensions().at("i") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64I.getXLen(), 64U); auto MaybeRV64E = RISCVISAInfo::parseNormalizedArchString("rv64e2p0"); @@ -75,7 +75,7 @@ TEST(ParseNormalizedArchString, AcceptsValidBaseISAsAndSetsXLen) { RISCVISAInfo &InfoRV64E = **MaybeRV64E; EXPECT_EQ(InfoRV64E.getExtensions().size(), 1UL); EXPECT_TRUE(InfoRV64E.getExtensions().at("e") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64E.getXLen(), 64U); } @@ -86,15 +86,15 @@ TEST(ParseNormalizedArchString, AcceptsArbitraryExtensionsAndVersions) { RISCVISAInfo &Info = **MaybeISAInfo; EXPECT_EQ(Info.getExtensions().size(), 5UL); EXPECT_TRUE(Info.getExtensions().at("i") == - (RISCVISAInfo::ExtensionVersion{5, 1})); + (RISCVISAUtils::ExtensionVersion{5, 1})); EXPECT_TRUE(Info.getExtensions().at("m") == - (RISCVISAInfo::ExtensionVersion{3, 2})); + (RISCVISAUtils::ExtensionVersion{3, 2})); EXPECT_TRUE(Info.getExtensions().at("zmadeup") == - (RISCVISAInfo::ExtensionVersion{11, 12})); + (RISCVISAUtils::ExtensionVersion{11, 12})); EXPECT_TRUE(Info.getExtensions().at("sfoo") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(Info.getExtensions().at("xbar") == - (RISCVISAInfo::ExtensionVersion{3, 0})); + (RISCVISAUtils::ExtensionVersion{3, 0})); } TEST(ParseNormalizedArchString, UpdatesFLenMinVLenMaxELen) { @@ -139,7 +139,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV32I = **MaybeRV32I; RISCVISAInfo::OrderedExtensionMap ExtsRV32I = InfoRV32I.getExtensions(); EXPECT_EQ(ExtsRV32I.size(), 1UL); - EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_EQ(InfoRV32I.getXLen(), 32U); EXPECT_EQ(InfoRV32I.getFLen(), 0U); @@ -148,7 +148,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV32E = **MaybeRV32E; RISCVISAInfo::OrderedExtensionMap ExtsRV32E = InfoRV32E.getExtensions(); EXPECT_EQ(ExtsRV32E.size(), 1UL); - EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32E.getXLen(), 32U); EXPECT_EQ(InfoRV32E.getFLen(), 0U); @@ -157,14 +157,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV32G = **MaybeRV32G; RISCVISAInfo::OrderedExtensionMap ExtsRV32G = InfoRV32G.getExtensions(); EXPECT_EQ(ExtsRV32G.size(), 7UL); - EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); - EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAInfo::ExtensionVersion{2, 0})); - EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAInfo::ExtensionVersion{2, 1})); - EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVISAInfo::ExtensionVersion{2, 2})); - EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVISAInfo::ExtensionVersion{2, 2})); - EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV32G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV32G.at("f") == (RISCVISAUtils::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV32G.at("d") == (RISCVISAUtils::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV32G.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV32G.at("zifencei") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32G.getXLen(), 32U); EXPECT_EQ(InfoRV32G.getFLen(), 64U); @@ -173,7 +173,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV64I = **MaybeRV64I; RISCVISAInfo::OrderedExtensionMap ExtsRV64I = InfoRV64I.getExtensions(); EXPECT_EQ(ExtsRV64I.size(), 1UL); - EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_EQ(InfoRV64I.getXLen(), 64U); EXPECT_EQ(InfoRV64I.getFLen(), 0U); @@ -182,7 +182,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV64E = **MaybeRV64E; RISCVISAInfo::OrderedExtensionMap ExtsRV64E = InfoRV64E.getExtensions(); EXPECT_EQ(ExtsRV64E.size(), 1UL); - EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64E.getXLen(), 64U); EXPECT_EQ(InfoRV64E.getFLen(), 0U); @@ -191,14 +191,14 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { RISCVISAInfo &InfoRV64G = **MaybeRV64G; RISCVISAInfo::OrderedExtensionMap ExtsRV64G = InfoRV64G.getExtensions(); EXPECT_EQ(ExtsRV64G.size(), 7UL); - EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); - EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAInfo::ExtensionVersion{2, 0})); - EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAInfo::ExtensionVersion{2, 1})); - EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVISAInfo::ExtensionVersion{2, 2})); - EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVISAInfo::ExtensionVersion{2, 2})); - EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); + EXPECT_TRUE(ExtsRV64G.at("a") == (RISCVISAUtils::ExtensionVersion{2, 1})); + EXPECT_TRUE(ExtsRV64G.at("f") == (RISCVISAUtils::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV64G.at("d") == (RISCVISAUtils::ExtensionVersion{2, 2})); + EXPECT_TRUE(ExtsRV64G.at("zicsr") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_TRUE(ExtsRV64G.at("zifencei") == - (RISCVISAInfo::ExtensionVersion{2, 0})); + (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64G.getXLen(), 64U); EXPECT_EQ(InfoRV64G.getFLen(), 64U); } @@ -243,7 +243,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { RISCVISAInfo &Info = **MaybeISAInfo; RISCVISAInfo::OrderedExtensionMap Exts = Info.getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } // Checks that supported extensions aren't incorrectly ignored when a @@ -252,7 +252,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { RISCVISAInfo::parseArchString("rv32i_zbc1p0_xmadeup", true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_TRUE(Exts.at("zbc") == (RISCVISAInfo::ExtensionVersion{1, 0})); + EXPECT_TRUE(Exts.at("zbc") == (RISCVISAUtils::ExtensionVersion{1, 0})); } TEST(ParseArchString, AcceptsVersionInLongOrShortForm) { @@ -260,13 +260,13 @@ TEST(ParseArchString, AcceptsVersionInLongOrShortForm) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } for (StringRef Input : {"rv32i_zfinx1", "rv32i_zfinx1p0"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); - EXPECT_TRUE(Exts.at("zfinx") == (RISCVISAInfo::ExtensionVersion{1, 0})); + EXPECT_TRUE(Exts.at("zfinx") == (RISCVISAUtils::ExtensionVersion{1, 0})); } } @@ -295,14 +295,14 @@ TEST(ParseArchString, ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } for (StringRef Input : {"rv32e0p1", "rv32e99p99", "rv64e0p1", "rv64e99p99"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("e") == (RISCVISAInfo::ExtensionVersion{2, 0})); + EXPECT_TRUE(Exts.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0})); } } @@ -313,7 +313,7 @@ TEST(ParseArchString, ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); - EXPECT_TRUE(Exts.at("i") == (RISCVISAInfo::ExtensionVersion{2, 1})); + EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } } @@ -481,7 +481,7 @@ TEST(ParseArchString, ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); - EXPECT_TRUE(Exts.at("ztso") == (RISCVISAInfo::ExtensionVersion{9, 9})); + EXPECT_TRUE(Exts.at("ztso") == (RISCVISAUtils::ExtensionVersion{9, 9})); } TEST(ParseArchString, RejectsUnrecognizedVersionForExperimentalExtension) { diff --git a/llvm/utils/TableGen/ARMTargetDefEmitter.cpp b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp new file mode 100644 index 0000000000000000000000000000000000000000..db87ac3336c1842fdca09b69d69346a248e10be0 --- /dev/null +++ b/llvm/utils/TableGen/ARMTargetDefEmitter.cpp @@ -0,0 +1,63 @@ +//===- ARMTargetDefEmitter.cpp - Generate data about ARM Architectures ----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This tablegen backend exports information about CPUs, FPUs, architectures, +// and features into a common format that can be used by both TargetParser and +// the ARM and AArch64 backends. +// +//===----------------------------------------------------------------------===// + +#include "llvm/ADT/StringSet.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" + +using namespace llvm; + +static void EmitARMTargetDef(RecordKeeper &RK, raw_ostream &OS) { + OS << "// Autogenerated by ARMTargetDefEmitter.cpp\n\n"; + + // Look through all SubtargetFeature defs with the given FieldName, and + // collect the set of all Values that that FieldName is set to. + auto gatherSubtargetFeatureFieldValues = [&RK](StringRef FieldName) { + llvm::StringSet<> Set; + for (const Record *Rec : RK.getAllDerivedDefinitions("SubtargetFeature")) { + if (Rec->getValueAsString("FieldName") == FieldName) { + Set.insert(Rec->getValueAsString("Value")); + } + } + return Set; + }; + + // The ARMProcFamilyEnum values are initialised by SubtargetFeature defs + // which set the ARMProcFamily field. We can generate the enum from these defs + // which look like this: + // + // def ProcA5 : SubtargetFeature<"a5", "ARMProcFamily", "CortexA5", + // "Cortex-A5 ARM processors", []>; + OS << "#ifndef ARM_PROCESSOR_FAMILY\n" + << "#define ARM_PROCESSOR_FAMILY(ENUM)\n" + << "#endif\n\n"; + const StringSet<> ARMProcFamilyVals = + gatherSubtargetFeatureFieldValues("ARMProcFamily"); + for (const StringRef &Family : ARMProcFamilyVals.keys()) + OS << "ARM_PROCESSOR_FAMILY(" << Family << ")\n"; + OS << "\n#undef ARM_PROCESSOR_FAMILY\n\n"; + + OS << "#ifndef ARM_ARCHITECTURE\n" + << "#define ARM_ARCHITECTURE(ENUM)\n" + << "#endif\n\n"; + // This should correspond to instances of the Architecture tablegen class. + const StringSet<> ARMArchVals = gatherSubtargetFeatureFieldValues("ARMArch"); + for (const StringRef &Arch : ARMArchVals.keys()) + OS << "ARM_ARCHITECTURE(" << Arch << ")\n"; + OS << "\n#undef ARM_ARCHITECTURE\n\n"; +} + +static TableGen::Emitter::Opt + X("gen-arm-target-def", EmitARMTargetDef, + "Generate the ARM or AArch64 Architecture information header."); diff --git a/llvm/utils/TableGen/CMakeLists.txt b/llvm/utils/TableGen/CMakeLists.txt index 577aeded4be72c37ab76048457d24281eb77f7f3..202f33fdf8b419dee7349245072024b4f3751367 100644 --- a/llvm/utils/TableGen/CMakeLists.txt +++ b/llvm/utils/TableGen/CMakeLists.txt @@ -13,6 +13,7 @@ set(LLVM_LINK_COMPONENTS Support) # ValueType definitions. add_tablegen(llvm-min-tblgen LLVM_HEADERS TableGen.cpp + ARMTargetDefEmitter.cpp Attributes.cpp DirectiveEmitter.cpp IntrinsicEmitter.cpp @@ -32,6 +33,7 @@ set(LLVM_LINK_COMPONENTS add_tablegen(llvm-tblgen LLVM DESTINATION "${LLVM_TOOLS_INSTALL_DIR}" EXPORT LLVM + ARMTargetDefEmitter.cpp AsmMatcherEmitter.cpp AsmWriterEmitter.cpp Attributes.cpp diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp index 19d42b7688dac8f99ff66d0c413b4cb222db52af..8af219f34e18b6add76b81cfef48b99945169de2 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.cpp @@ -723,6 +723,29 @@ void RuleMatcher::optimize() { return std::tuple(L->getKind(), L->getInsnVarID(), L->getOpIdx()) < std::tuple(R->getKind(), R->getInsnVarID(), R->getOpIdx()); }); + + // Deduplicate EraseInst actions, and if an EraseInst erases the root, place + // it at the end to favor generation of GIR_EraseRootFromParent_Done + DenseSet AlreadySeenEraseInsts; + auto EraseRootIt = Actions.end(); + auto It = Actions.begin(); + while (It != Actions.end()) { + if (const auto *EI = dyn_cast(It->get())) { + unsigned InstID = EI->getInsnID(); + if (!AlreadySeenEraseInsts.insert(InstID).second) { + It = Actions.erase(It); + continue; + } + + if (InstID == 0) + EraseRootIt = It; + } + + ++It; + } + + if (EraseRootIt != Actions.end()) + Actions.splice(Actions.end(), Actions, EraseRootIt); } bool RuleMatcher::hasFirstCondition() const { @@ -966,66 +989,60 @@ void RuleMatcher::emit(MatchTable &Table) { // We must also check if it's safe to fold the matched instructions. if (InsnVariableIDs.size() >= 2) { - // Invert the map to create stable ordering (by var names) - SmallVector InsnIDs; - for (const auto &Pair : InsnVariableIDs) { - // Skip the root node since it isn't moving anywhere. Everything else is - // sinking to meet it. - if (Pair.first == Matchers.front().get()) - continue; - - InsnIDs.push_back(Pair.second); - } - llvm::sort(InsnIDs); - - for (const auto &InsnID : InsnIDs) { - // Reject the difficult cases until we have a more accurate check. - Table << MatchTable::Opcode("GIM_CheckIsSafeToFold") - << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) - << MatchTable::LineBreak; - // FIXME: Emit checks to determine it's _actually_ safe to fold and/or - // account for unsafe cases. - // - // Example: - // MI1--> %0 = ... - // %1 = ... %0 - // MI0--> %2 = ... %0 - // It's not safe to erase MI1. We currently handle this by not - // erasing %0 (even when it's dead). - // - // Example: - // MI1--> %0 = load volatile @a - // %1 = load volatile @a - // MI0--> %2 = ... %0 - // It's not safe to sink %0's def past %1. We currently handle - // this by rejecting all loads. - // - // Example: - // MI1--> %0 = load @a - // %1 = store @a - // MI0--> %2 = ... %0 - // It's not safe to sink %0's def past %1. We currently handle - // this by rejecting all loads. - // - // Example: - // G_CONDBR %cond, @BB1 - // BB0: - // MI1--> %0 = load @a - // G_BR @BB1 - // BB1: - // MI0--> %2 = ... %0 - // It's not always safe to sink %0 across control flow. In this - // case it may introduce a memory fault. We currentl handle - // this by rejecting all loads. - } + // FIXME: Emit checks to determine it's _actually_ safe to fold and/or + // account for unsafe cases. + // + // Example: + // MI1--> %0 = ... + // %1 = ... %0 + // MI0--> %2 = ... %0 + // It's not safe to erase MI1. We currently handle this by not + // erasing %0 (even when it's dead). + // + // Example: + // MI1--> %0 = load volatile @a + // %1 = load volatile @a + // MI0--> %2 = ... %0 + // It's not safe to sink %0's def past %1. We currently handle + // this by rejecting all loads. + // + // Example: + // MI1--> %0 = load @a + // %1 = store @a + // MI0--> %2 = ... %0 + // It's not safe to sink %0's def past %1. We currently handle + // this by rejecting all loads. + // + // Example: + // G_CONDBR %cond, @BB1 + // BB0: + // MI1--> %0 = load @a + // G_BR @BB1 + // BB1: + // MI0--> %2 = ... %0 + // It's not always safe to sink %0 across control flow. In this + // case it may introduce a memory fault. We currentl handle + // this by rejecting all loads. + + Table << MatchTable::Opcode("GIM_CheckIsSafeToFold") + << MatchTable::Comment("NumInsns") + << MatchTable::IntValue(1, InsnVariableIDs.size() - 1) + << MatchTable::LineBreak; } for (const auto &PM : EpilogueMatchers) PM->emitPredicateOpcodes(Table, *this); - for (const auto &MA : Actions) - MA->emitActionOpcodes(Table, *this); + // Emit all actions except the last one, then emit coverage and emit the + // final action. + // + // This is because some actions, such as GIR_EraseRootFromParent_Done, also + // double as a GIR_Done and terminate execution of the rule. + if (!Actions.empty()) { + for (const auto &MA : drop_end(Actions)) + MA->emitActionOpcodes(Table, *this); + } assert((Table.isWithCoverage() ? !Table.isCombiner() : true) && "Combiner tables don't support coverage!"); @@ -1036,8 +1053,13 @@ void RuleMatcher::emit(MatchTable &Table) { Table << MatchTable::Comment(("GIR_Coverage, " + Twine(RuleID) + ",").str()) << MatchTable::LineBreak; - Table << MatchTable::Opcode("GIR_Done", -1) << MatchTable::LineBreak - << MatchTable::Label(LabelID); + if (Actions.empty() || + !Actions.back()->emitActionOpcodesAndDone(Table, *this)) { + Table << MatchTable::Opcode("GIR_Done", -1) << MatchTable::LineBreak; + } + + Table << MatchTable::Label(LabelID); + ++NumPatternEmitted; } @@ -1140,10 +1162,14 @@ bool LLTOperandMatcher::hasValue() const { void LLTOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { - Table << MatchTable::Opcode("GIM_CheckType") << MatchTable::Comment("MI") - << MatchTable::ULEB128Value(InsnVarID) << MatchTable::Comment("Op") - << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("Type") - << getValue() << MatchTable::LineBreak; + if (InsnVarID == 0) { + Table << MatchTable::Opcode("GIM_RootCheckType"); + } else { + Table << MatchTable::Opcode("GIM_CheckType") << MatchTable::Comment("MI") + << MatchTable::ULEB128Value(InsnVarID); + } + Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::Comment("Type") << getValue() << MatchTable::LineBreak; } //===- PointerToAnyOperandMatcher -----------------------------------------===// @@ -1205,9 +1231,14 @@ bool RegisterBankOperandMatcher::isIdentical(const PredicateMatcher &B) const { void RegisterBankOperandMatcher::emitPredicateOpcodes(MatchTable &Table, RuleMatcher &Rule) const { - Table << MatchTable::Opcode("GIM_CheckRegBankForClass") - << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID) - << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) + if (InsnVarID == 0) { + Table << MatchTable::Opcode("GIM_RootCheckRegBankForClass"); + } else { + Table << MatchTable::Opcode("GIM_CheckRegBankForClass") + << MatchTable::Comment("MI") << MatchTable::ULEB128Value(InsnVarID); + } + + Table << MatchTable::Comment("Op") << MatchTable::ULEB128Value(OpIdx) << MatchTable::Comment("RC") << MatchTable::NamedValue(2, RC.getQualifiedIdName()) << MatchTable::LineBreak; @@ -1810,17 +1841,28 @@ OperandRenderer::~OperandRenderer() {} //===- CopyRenderer -------------------------------------------------------===// +void CopyRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule, + unsigned NewInsnID, unsigned OldInsnID, + unsigned OpIdx, StringRef Name) { + if (NewInsnID == 0 && OldInsnID == 0) { + Table << MatchTable::Opcode("GIR_RootToRootCopy"); + } else { + Table << MatchTable::Opcode("GIR_Copy") << MatchTable::Comment("NewInsnID") + << MatchTable::ULEB128Value(NewInsnID) + << MatchTable::Comment("OldInsnID") + << MatchTable::ULEB128Value(OldInsnID); + } + + Table << MatchTable::Comment("OpIdx") << MatchTable::ULEB128Value(OpIdx) + << MatchTable::Comment(Name) << MatchTable::LineBreak; +} + void CopyRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const { const OperandMatcher &Operand = Rule.getOperandMatcher(SymbolicName); unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); - Table << MatchTable::Opcode("GIR_Copy") << MatchTable::Comment("NewInsnID") - << MatchTable::ULEB128Value(NewInsnID) - << MatchTable::Comment("OldInsnID") - << MatchTable::ULEB128Value(OldInsnVarID) - << MatchTable::Comment("OpIdx") - << MatchTable::ULEB128Value(Operand.getOpIdx()) - << MatchTable::Comment(SymbolicName) << MatchTable::LineBreak; + emitRenderOpcodes(Table, Rule, NewInsnID, OldInsnVarID, Operand.getOpIdx(), + SymbolicName); } //===- CopyPhysRegRenderer ------------------------------------------------===// @@ -1829,13 +1871,8 @@ void CopyPhysRegRenderer::emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const { const OperandMatcher &Operand = Rule.getPhysRegOperandMatcher(PhysReg); unsigned OldInsnVarID = Rule.getInsnVarID(Operand.getInstructionMatcher()); - Table << MatchTable::Opcode("GIR_Copy") << MatchTable::Comment("NewInsnID") - << MatchTable::ULEB128Value(NewInsnID) - << MatchTable::Comment("OldInsnID") - << MatchTable::ULEB128Value(OldInsnVarID) - << MatchTable::Comment("OpIdx") - << MatchTable::ULEB128Value(Operand.getOpIdx()) - << MatchTable::Comment(PhysReg->getName()) << MatchTable::LineBreak; + CopyRenderer::emitRenderOpcodes(Table, Rule, NewInsnID, OldInsnVarID, + Operand.getOpIdx(), PhysReg->getName()); } //===- CopyOrAddZeroRegRenderer -------------------------------------------===// @@ -2185,10 +2222,17 @@ void BuildMIAction::emitActionOpcodes(MatchTable &Table, // TODO: Simple permutation looks like it could be almost as common as // mutation due to commutative operations. - Table << MatchTable::Opcode("GIR_BuildMI") << MatchTable::Comment("InsnID") - << MatchTable::ULEB128Value(InsnID) << MatchTable::Comment("Opcode") + if (InsnID == 0) { + Table << MatchTable::Opcode("GIR_BuildRootMI"); + } else { + Table << MatchTable::Opcode("GIR_BuildMI") << MatchTable::Comment("InsnID") + << MatchTable::ULEB128Value(InsnID); + } + + Table << MatchTable::Comment("Opcode") << MatchTable::NamedValue(2, I->Namespace, I->TheDef->getName()) << MatchTable::LineBreak; + for (const auto &Renderer : OperandRenderers) Renderer->emitRenderOpcodes(Table, Rule); @@ -2244,8 +2288,8 @@ void BuildConstantAction::emitActionOpcodes(MatchTable &Table, //===- EraseInstAction ----------------------------------------------------===// -void EraseInstAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule, - unsigned InsnID) { +void EraseInstAction::emitActionOpcodes(MatchTable &Table, + RuleMatcher &Rule) const { // Avoid erasing the same inst twice. if (!Rule.tryEraseInsnID(InsnID)) return; @@ -2255,9 +2299,19 @@ void EraseInstAction::emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule, << MatchTable::LineBreak; } -void EraseInstAction::emitActionOpcodes(MatchTable &Table, - RuleMatcher &Rule) const { - emitActionOpcodes(Table, Rule, InsnID); +bool EraseInstAction::emitActionOpcodesAndDone(MatchTable &Table, + RuleMatcher &Rule) const { + if (InsnID != 0) { + emitActionOpcodes(Table, Rule); + return false; + } + + if (!Rule.tryEraseInsnID(0)) + return false; + + Table << MatchTable::Opcode("GIR_EraseRootFromParent_Done", -1) + << MatchTable::LineBreak; + return true; } //===- ReplaceRegAction ---------------------------------------------------===// diff --git a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h index 871fe04465aa9639e89b82eb9edf138c7d2d8dc1..30301c28ce6c4dab4309b6efca1e4d7df975e0c5 100644 --- a/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h +++ b/llvm/utils/TableGen/Common/GlobalISel/GlobalISelMatchTable.h @@ -1884,6 +1884,10 @@ public: StringRef getSymbolicName() const { return SymbolicName; } + static void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule, + unsigned NewInsnID, unsigned OldInsnID, + unsigned OpIdx, StringRef Name); + void emitRenderOpcodes(MatchTable &Table, RuleMatcher &Rule) const override; }; @@ -2226,6 +2230,15 @@ public: virtual void emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const = 0; + /// If this opcode has an overload that can call GIR_Done directly, emit that + /// instead of the usual opcode and return "true". Return "false" if GIR_Done + /// still needs to be emitted. + virtual bool emitActionOpcodesAndDone(MatchTable &Table, + RuleMatcher &Rule) const { + emitActionOpcodes(Table, Rule); + return false; + } + private: ActionKind Kind; }; @@ -2334,13 +2347,15 @@ public: EraseInstAction(unsigned InsnID) : MatchAction(AK_EraseInst), InsnID(InsnID) {} + unsigned getInsnID() const { return InsnID; } + static bool classof(const MatchAction *A) { return A->getKind() == AK_EraseInst; } void emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const override; - static void emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule, - unsigned InsnID); + bool emitActionOpcodesAndDone(MatchTable &Table, + RuleMatcher &Rule) const override; }; class ReplaceRegAction : public MatchAction { @@ -2381,9 +2396,14 @@ public: } void emitActionOpcodes(MatchTable &Table, RuleMatcher &Rule) const override { - Table << MatchTable::Opcode("GIR_ConstrainSelectedInstOperands") - << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) - << MatchTable::LineBreak; + if (InsnID == 0) { + Table << MatchTable::Opcode("GIR_RootConstrainSelectedInstOperands") + << MatchTable::LineBreak; + } else { + Table << MatchTable::Opcode("GIR_ConstrainSelectedInstOperands") + << MatchTable::Comment("InsnID") << MatchTable::ULEB128Value(InsnID) + << MatchTable::LineBreak; + } } }; diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 653e5c5fdb4219fa4699ec086c67794d4719d3f6..26034e31ad8d1938dc348acee39611954c9838a0 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -11,7 +11,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Support/RISCVISAInfo.h" +#include "llvm/Support/RISCVISAUtils.h" #include "llvm/TableGen/Record.h" #include "llvm/TableGen/TableGenBackend.h" @@ -24,8 +24,8 @@ using namespace llvm; // This is almost the same as RISCVFeatures::parseFeatureBits, except that we // get feature name from feature records instead of feature bits. static void printMArch(raw_ostream &OS, const Record &Rec) { - std::map + std::map Extensions; unsigned XLen = 0; diff --git a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn index cd90c7752e1642fa0ce6c790f6066747065081de..bbf2b84334d9d500249b0d838dd3b5ea64bb18a7 100644 --- a/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn +++ b/llvm/utils/gn/secondary/clang-tools-extra/clang-tidy/bugprone/BUILD.gn @@ -61,6 +61,7 @@ static_library("bugprone") { "PosixReturnCheck.cpp", "RedundantBranchConditionCheck.cpp", "ReservedIdentifierCheck.cpp", + "ReturnConstRefFromParameterCheck.cpp", "SharedPtrArrayMismatchCheck.cpp", "SignalHandlerCheck.cpp", "SignedCharMisuseCheck.cpp", diff --git a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn index aecb65ab6c728de9151be2d15596c809fbb035b8..a71dfa518b1df3b214841c879cb19e2184d45828 100644 --- a/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/include/llvm/TargetParser/BUILD.gn @@ -1,5 +1,19 @@ import("//llvm/utils/TableGen/tablegen.gni") +tablegen("ARMTargetParserDef") { + visibility = [ ":gen" ] + args = [ "-gen-arm-target-def" ] + td_file = "//llvm/lib/Target/ARM/ARM.td" + tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen" +} + +tablegen("AArch64TargetParserDef") { + visibility = [ ":gen" ] + args = [ "-gen-arm-target-def" ] + td_file = "//llvm/lib/Target/AArch64/AArch64.td" + tblgen_target = "//llvm/utils/TableGen:llvm-min-tblgen" +} + tablegen("RISCVTargetParserDef") { visibility = [ ":gen" ] args = [ "-gen-riscv-target-def" ] @@ -8,5 +22,9 @@ tablegen("RISCVTargetParserDef") { } group("gen") { - deps = [ ":RISCVTargetParserDef" ] + deps = [ + ":ARMTargetParserDef", + ":AArch64TargetParserDef", + ":RISCVTargetParserDef", + ] } diff --git a/llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn index 896b031a7bd3fd4ab1c48efd481e5ab762562646..247ef480f5f1a45fc3ca93cf530b20ffe80b544f 100644 --- a/llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/IR/BUILD.gn @@ -31,8 +31,8 @@ static_library("IR") { "DataLayout.cpp", "DebugInfo.cpp", "DebugInfoMetadata.cpp", - "DebugProgramInstruction.cpp", "DebugLoc.cpp", + "DebugProgramInstruction.cpp", "DiagnosticHandler.cpp", "DiagnosticInfo.cpp", "DiagnosticPrinter.cpp", @@ -55,6 +55,7 @@ static_library("IR") { "LegacyPassManager.cpp", "MDBuilder.cpp", "Mangler.cpp", + "MemoryModelRelaxationAnnotations.cpp", "Metadata.cpp", "Module.cpp", "ModuleSummaryIndex.cpp", @@ -79,10 +80,10 @@ static_library("IR") { "TypedPointerType.cpp", "Use.cpp", "User.cpp", + "VFABIDemangler.cpp", "Value.cpp", "ValueSymbolTable.cpp", "VectorBuilder.cpp", "Verifier.cpp", - "VFABIDemangler.cpp", ] } diff --git a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn index ba0f6d8c0f8cff88b392b58aa9765c85d27772ea..941d448b3367c16467bd5602858d4ce6bdf3163d 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Support/BUILD.gn @@ -119,7 +119,7 @@ static_library("Support") { "PrettyStackTrace.cpp", "RISCVAttributeParser.cpp", "RISCVAttributes.cpp", - "RISCVISAInfo.cpp", + "RISCVISAUtils.cpp", "RWMutex.cpp", "RandomNumberGenerator.cpp", "Regex.cpp", diff --git a/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn index 1a91bb7e6fa9f5468f50395153f24a38b24a4ac0..31919badac7be3e20e99a3d4809ad429e3c2f078 100644 --- a/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/TargetParser/BUILD.gn @@ -13,6 +13,7 @@ static_library("TargetParser") { "CSKYTargetParser.cpp", "Host.cpp", "LoongArchTargetParser.cpp", + "RISCVISAInfo.cpp", "RISCVTargetParser.cpp", "SubtargetFeature.cpp", "TargetParser.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn index 4ffd6d4d182e1702dd17249acf8397dbea68be19..8f6caf2e575be68ff7c30ed6d42641010bb7433f 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/IR/BUILD.gn @@ -33,6 +33,7 @@ unittest("IRTests") { "LegacyPassManagerTest.cpp", "MDBuilderTest.cpp", "ManglerTest.cpp", + "MemoryModelRelaxationAnnotationsTest.cpp", "MetadataTest.cpp", "ModuleSummaryIndexTest.cpp", "ModuleTest.cpp", @@ -45,6 +46,7 @@ unittest("IRTests") { "TypesTest.cpp", "UseTest.cpp", "UserTest.cpp", + "VFABIDemanglerTest.cpp", "VPIntrinsicTest.cpp", "ValueHandleTest.cpp", "ValueMapTest.cpp", @@ -52,6 +54,5 @@ unittest("IRTests") { "VectorBuilderTest.cpp", "VectorTypesTest.cpp", "VerifierTest.cpp", - "VFABIDemanglerTest.cpp", ] } diff --git a/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn index 7a152fdcc0598257c14165eded0efdfacd3a6f38..c7356dd33a37b140dfd4360c3118e5a65a6217e4 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/Support/BUILD.gn @@ -71,7 +71,6 @@ unittest("SupportTests") { "ProcessTest.cpp", "ProgramTest.cpp", "RISCVAttributeParserTest.cpp", - "RISCVISAInfoTest.cpp", "RegexTest.cpp", "ReplaceFileTest.cpp", "ReverseIterationTest.cpp", diff --git a/llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn b/llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn index eebaf67767f477513df62805b378260a9a932e39..3739614c316093258dd77fc2df693930848c9312 100644 --- a/llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/unittests/TargetParser/BUILD.gn @@ -10,6 +10,7 @@ unittest("TargetParserTests") { sources = [ "CSKYTargetParserTest.cpp", "Host.cpp", + "RISCVISAInfoTest.cpp", "RISCVTargetParserTest.cpp", "TargetParserTest.cpp", "TripleTest.cpp", diff --git a/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn b/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn index 53a9d8d01519a7f0555d5e4a008f2e5439e255cc..f3ae5b5899ac6a3bb2792907628795b66f8cd17d 100644 --- a/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/utils/TableGen/BUILD.gn @@ -1,5 +1,6 @@ source_set("llvm-min-tblgen-sources") { sources = [ + "ARMTargetDefEmitter.cpp", "Attributes.cpp", "DirectiveEmitter.cpp", "IntrinsicEmitter.cpp", diff --git a/mlir/CMakeLists.txt b/mlir/CMakeLists.txt index 5c4301af040b47e2dfb51c4067e78679b1295847..4c0ef8387b8dff11530647c05216b4f40053a9c2 100644 --- a/mlir/CMakeLists.txt +++ b/mlir/CMakeLists.txt @@ -185,10 +185,13 @@ include_directories( ${MLIR_INCLUDE_DIR}) add_subdirectory(tools/mlir-linalg-ods-gen) add_subdirectory(tools/mlir-pdll) add_subdirectory(tools/mlir-tblgen) +add_subdirectory(tools/mlir-src-sharder) set(MLIR_TABLEGEN_EXE "${MLIR_TABLEGEN_EXE}" CACHE INTERNAL "") set(MLIR_TABLEGEN_TARGET "${MLIR_TABLEGEN_TARGET}" CACHE INTERNAL "") set(MLIR_PDLL_TABLEGEN_EXE "${MLIR_PDLL_TABLEGEN_EXE}" CACHE INTERNAL "") set(MLIR_PDLL_TABLEGEN_TARGET "${MLIR_PDLL_TABLEGEN_TARGET}" CACHE INTERNAL "") +set(MLIR_SRC_SHARDER_TABLEGEN_EXE "${MLIR_SRC_SHARDER_TABLEGEN_EXE}" CACHE INTERNAL "") +set(MLIR_SRC_SHARDER_TABLEGEN_TARGET "${MLIR_SRC_SHARDER_TABLEGEN_TARGET}" CACHE INTERNAL "") add_subdirectory(include/mlir) add_subdirectory(lib) diff --git a/mlir/cmake/modules/AddMLIR.cmake b/mlir/cmake/modules/AddMLIR.cmake index 1d2ed748bc2f13dc555bb808a7ffd63bbfaede20..afb74fb2d0002550c2b8e584a0a7381d8f5196ae 100644 --- a/mlir/cmake/modules/AddMLIR.cmake +++ b/mlir/cmake/modules/AddMLIR.cmake @@ -5,6 +5,28 @@ function(mlir_tablegen ofn) tablegen(MLIR ${ARGV}) set(TABLEGEN_OUTPUT ${TABLEGEN_OUTPUT} ${CMAKE_CURRENT_BINARY_DIR}/${ofn} PARENT_SCOPE) + + # Get the current set of include paths for this td file. + cmake_parse_arguments(ARG "" "" "DEPENDS;EXTRA_INCLUDES" ${ARGN}) + get_directory_property(tblgen_includes INCLUDE_DIRECTORIES) + list(APPEND tblgen_includes ${ARG_EXTRA_INCLUDES}) + # Filter out any empty include items. + list(REMOVE_ITEM tblgen_includes "") + + # Build the absolute path for the current input file. + if (IS_ABSOLUTE ${LLVM_TARGET_DEFINITIONS}) + set(LLVM_TARGET_DEFINITIONS_ABSOLUTE ${LLVM_TARGET_DEFINITIONS}) + else() + set(LLVM_TARGET_DEFINITIONS_ABSOLUTE ${CMAKE_CURRENT_SOURCE_DIR}/${LLVM_TARGET_DEFINITIONS}) + endif() + + # Append the includes used for this file to the tablegen_compile_commands + # file. + file(APPEND ${CMAKE_BINARY_DIR}/tablegen_compile_commands.yml + "--- !FileInfo:\n" + " filepath: \"${LLVM_TARGET_DEFINITIONS_ABSOLUTE}\"\n" + " includes: \"${CMAKE_CURRENT_SOURCE_DIR};${tblgen_includes}\"\n" + ) endfunction() # Clear out any pre-existing compile_commands file before processing. This @@ -149,6 +171,22 @@ function(add_mlir_dialect dialect dialect_namespace) add_dependencies(mlir-headers MLIR${dialect}IncGen) endfunction() +# Declare sharded dialect operation declarations and definitions +function(add_sharded_ops ops_target shard_count) + set(LLVM_TARGET_DEFINITIONS ${ops_target}.td) + mlir_tablegen(${ops_target}.h.inc -gen-op-decls -op-shard-count=${shard_count}) + mlir_tablegen(${ops_target}.cpp.inc -gen-op-defs -op-shard-count=${shard_count}) + set(LLVM_TARGET_DEFINITIONS ${ops_target}.cpp) + foreach(index RANGE ${shard_count}) + set(SHARDED_SRC ${ops_target}.${index}.cpp) + list(APPEND SHARDED_SRCS ${SHARDED_SRC}) + tablegen(MLIR_SRC_SHARDER ${SHARDED_SRC} -op-shard-index=${index}) + set(TABLEGEN_OUTPUT ${TABLEGEN_OUTPUT} ${CMAKE_CURRENT_BINARY_DIR}/${SHARDED_SRC}) + endforeach() + add_public_tablegen_target(MLIR${ops_target}ShardGen) + set(SHARDED_SRCS ${SHARDED_SRCS} PARENT_SCOPE) +endfunction() + # Declare a dialect in the include directory function(add_mlir_interface interface) set(LLVM_TARGET_DEFINITIONS ${interface}.td) diff --git a/mlir/cmake/modules/CMakeLists.txt b/mlir/cmake/modules/CMakeLists.txt index 8d2904ef46dfe81deb96f4175fc3a970442f2337..3ac1c79b090ed6c330b17a26bf430ad8ee1bd90d 100644 --- a/mlir/cmake/modules/CMakeLists.txt +++ b/mlir/cmake/modules/CMakeLists.txt @@ -39,6 +39,7 @@ set(MLIR_CONFIG_INCLUDE_DIRS # Refer to the best host mlir-tbgen, which might be a host-optimized version set(MLIR_CONFIG_TABLEGEN_EXE "${MLIR_TABLEGEN_EXE}") set(MLIR_CONFIG_PDLL_TABLEGEN_EXE "${MLIR_PDLL_TABLEGEN_EXE}") +set(MLIR_CONFIG_SRC_SHARDER_TABLEGEN_EXE "${MLIR_SRC_SHARDER_TABLEGEN_EXE}") configure_file( ${CMAKE_CURRENT_SOURCE_DIR}/MLIRConfig.cmake.in @@ -77,6 +78,7 @@ set(MLIR_CONFIG_INCLUDE_DIRS # if we're building with a host-optimized mlir-tblgen (with LLVM_OPTIMIZED_TABLEGEN). set(MLIR_CONFIG_TABLEGEN_EXE mlir-tblgen) set(MLIR_CONFIG_PDLL_TABLEGEN_EXE mlir-pdll) +set(MLIR_CONFIG_SRC_SHARDER_TABLEGEN_EXE mlir-src-sharder) configure_file( ${CMAKE_CURRENT_SOURCE_DIR}/MLIRConfig.cmake.in diff --git a/mlir/cmake/modules/MLIRConfig.cmake.in b/mlir/cmake/modules/MLIRConfig.cmake.in index d4da3cd98cce9816e30f45b96e6b5dbf00ad33d6..7076d94a32f2bcd06525e043b6edd9a7cdc43ddc 100644 --- a/mlir/cmake/modules/MLIRConfig.cmake.in +++ b/mlir/cmake/modules/MLIRConfig.cmake.in @@ -11,6 +11,7 @@ set(MLIR_CMAKE_DIR "@MLIR_CONFIG_CMAKE_DIR@") set(MLIR_INCLUDE_DIRS "@MLIR_CONFIG_INCLUDE_DIRS@") set(MLIR_TABLEGEN_EXE "@MLIR_CONFIG_TABLEGEN_EXE@") set(MLIR_PDLL_TABLEGEN_EXE "@MLIR_CONFIG_PDLL_TABLEGEN_EXE@") +set(MLIR_SRC_SHARDER_TABLEGEN_EXE "@MLIR_CONFIG_SRC_SHARDER_TABLEGEN_EXE@") set(MLIR_INSTALL_AGGREGATE_OBJECTS "@MLIR_INSTALL_AGGREGATE_OBJECTS@") set(MLIR_ENABLE_BINDINGS_PYTHON "@MLIR_ENABLE_BINDINGS_PYTHON@") set(MLIR_ENABLE_EXECUTION_ENGINE "@MLIR_ENABLE_EXECUTION_ENGINE@") diff --git a/mlir/docs/DefiningDialects/Operations.md b/mlir/docs/DefiningDialects/Operations.md index 729393d5362673d52816d5f760e2779dafb20382..79a0cc55f1384036f1d7b8188f200a80b1c22547 100644 --- a/mlir/docs/DefiningDialects/Operations.md +++ b/mlir/docs/DefiningDialects/Operations.md @@ -1114,6 +1114,100 @@ void process(AddOp op, ArrayRef newOperands) { } ``` +#### Sharded Operation Definitions + +Large dialects with many operations may struggle with C++ compile time of +generated op definitions, due to large compilation units. `mlir-tblgen` +provides the ability to shard op definitions by splitting them up evenly +by passing `-op-shard-count` to `-gen-op-defs` and `-gen-op-decls`. The tool +will generate a single include file for the definitions broken up by +`GET_OP_DEFS_${N}` where `${N}` is the shard number. A shard can be compiled in +a single compilation unit by adding a file like this to your dialect library: + +```c++ +#include "mlir/IR/Operation.h" +// Add any other required includes. + +// Utilities shared by generated op definitions: custom directive parsers, +// printers, etc. +#include "OpUtils.h" + +#define GET_OP_DEFS_0 +#include "MyDialectOps.cpp.inc" +``` + +Note: this requires restructing shared utility functions within the dialect +library so they can be shared by multiple compilation units. I.e. instead of +defining `static` methods in the same source file, you should declare them in a +shared header and define them in their own source file. + +The op registration hooks are also sharded, because the template instantiation +can take a very long time to compile. Operations should be registered in your +dialect like: + +```c++ +void MyDialect::initialize() { + registerMyDialectOperations(this); +} +``` + +CMake and Bazel functions are included to make sharding dialects easier. +Assuming you have organized your operation utility functions into their own +header, define a file that looks like the one above, but without the `#define`: + +```c++ +// MyDialectOps.cpp +#include "mlir/IR/Operation.h" + +#include "OpUtils.h" + +#include "MyDialectOps.cpp.inc" +``` + +In CMake, remove the manual `mlir_tablegen` invocations and replace them with: + +```cmake +set(LLVM_TARGET_DEFINITIONS MyDialectOps.td) +add_sharded_ops(MyDialectOps 8) # shard the op definitions by 8 + +add_mlir_library(MyDialect + MyDialect.cpp + MyDialectOpDefs.cpp + ${SHARDED_SRCS} + + DEPENDS + MLIRTestOpsShardGen +) +``` + +This will automatically duplicate the `MyDialectOps.cpp` source file and add the +`#define` up the number of shards indicated. + +It is recommended that any out-of-line op member functions (like verifiers) be +defined in a separate source file. In this example, it is called +`MyDialectOpDefs.cpp`. + +In Bazel, remove the `-gen-op-defs` and `-gen-op-decls` invocations, and add + +```bazel +gentbl_sharded_ops( + name = "MyDialectOpSrcs", + hdr_out = "MyDialectOps.h.inc", + shard_count = 8, + sharder = "//mlir:mlir-src-sharder", + src_file = "MyDialectOps.cpp", + src_out = "MyDialectOps.cpp.inc", + tblgen = "//mlir:mlir-tblgen", + td_file = "MyDialectOps.td", + deps = [":MyDialectOpsTdFiles"], +) + +cc_library( + name = "MyDialect", + srcs = glob(["MyDialect/*.cpp"]) + [":MyDialectOpSrcs"] +) +``` + ## Constraints Constraint is a core concept in table-driven operation definition: operation diff --git a/mlir/docs/Tutorials/UnderstandingTheIRStructure.md b/mlir/docs/Tutorials/UnderstandingTheIRStructure.md index 067a11dc435abdd9653bbc7be823c11f09635a19..ed323fc42336bc482a2c4957f19c8a054751d117 100644 --- a/mlir/docs/Tutorials/UnderstandingTheIRStructure.md +++ b/mlir/docs/Tutorials/UnderstandingTheIRStructure.md @@ -40,8 +40,8 @@ the nested regions and print them individually: if (!op->getAttrs().empty()) { printIndent() << op->getAttrs().size() << " attributes:\n"; for (NamedAttribute attr : op->getAttrs()) - printIndent() << " - '" << attr.first << "' : '" << attr.second - << "'\n"; + printIndent() << " - '" << attr.getName() << "' : '" + << attr.getValue() << "'\n"; } // Recurse into each of the regions attached to the operation. diff --git a/mlir/include/mlir-c/Dialect/LLVM.h b/mlir/include/mlir-c/Dialect/LLVM.h index bd9b7dd26f5e9ea20761db0f4ecc161b91e2305a..b3e64bd68f7b1c18b0d19def0a49a915518460ca 100644 --- a/mlir/include/mlir-c/Dialect/LLVM.h +++ b/mlir/include/mlir-c/Dialect/LLVM.h @@ -23,6 +23,13 @@ MLIR_DECLARE_CAPI_DIALECT_REGISTRATION(LLVM, llvm); MLIR_CAPI_EXPORTED MlirType mlirLLVMPointerTypeGet(MlirContext ctx, unsigned addressSpace); +/// Returns `true` if the type is an LLVM dialect pointer type. +MLIR_CAPI_EXPORTED bool mlirTypeIsALLVMPointerType(MlirType type); + +/// Returns address space of llvm.ptr +MLIR_CAPI_EXPORTED unsigned +mlirLLVMPointerTypeGetAddressSpace(MlirType pointerType); + /// Creates an llmv.void type. MLIR_CAPI_EXPORTED MlirType mlirLLVMVoidTypeGet(MlirContext ctx); diff --git a/mlir/include/mlir-c/Dialect/SparseTensor.h b/mlir/include/mlir-c/Dialect/SparseTensor.h index 52ca7ba8a1618f48c64f77a7e5c8c2ecfe6af468..125469f57c5f552768fe6b05bdeb0275e044bfc6 100644 --- a/mlir/include/mlir-c/Dialect/SparseTensor.h +++ b/mlir/include/mlir-c/Dialect/SparseTensor.h @@ -53,7 +53,8 @@ mlirAttributeIsASparseTensorEncodingAttr(MlirAttribute attr); MLIR_CAPI_EXPORTED MlirAttribute mlirSparseTensorEncodingAttrGet( MlirContext ctx, intptr_t lvlRank, MlirSparseTensorLevelType const *lvlTypes, MlirAffineMap dimToLvl, - MlirAffineMap lvlTodim, int posWidth, int crdWidth); + MlirAffineMap lvlTodim, int posWidth, int crdWidth, + MlirAttribute explicitVal, MlirAttribute implicitVal); /// Returns the level-rank of the `sparse_tensor.encoding` attribute. MLIR_CAPI_EXPORTED intptr_t @@ -85,6 +86,14 @@ mlirSparseTensorEncodingAttrGetPosWidth(MlirAttribute attr); MLIR_CAPI_EXPORTED int mlirSparseTensorEncodingAttrGetCrdWidth(MlirAttribute attr); +/// Returns the explicit value of the `sparse_tensor.encoding` attribute. +MLIR_CAPI_EXPORTED MlirAttribute +mlirSparseTensorEncodingAttrGetExplicitVal(MlirAttribute attr); + +/// Returns the implicit value of the `sparse_tensor.encoding` attribute. +MLIR_CAPI_EXPORTED MlirAttribute +mlirSparseTensorEncodingAttrGetImplicitVal(MlirAttribute attr); + MLIR_CAPI_EXPORTED unsigned mlirSparseTensorEncodingAttrGetStructuredN(MlirSparseTensorLevelType lvlType); diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h index 3c5fa23bd4a7f42168bd10073069a6b62471f15f..244cee1dd635b64e76347c8d7cf252b367a079cb 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPClauseOperands.h @@ -295,10 +295,9 @@ using TeamsClauseOps = PrivateClauseOps, ReductionClauseOps, ThreadLimitClauseOps>; using WsloopClauseOps = - detail::Clauses; + detail::Clauses; } // namespace omp } // namespace mlir diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td index f3e178c54096cd645062c5ddf486a757d01f6a87..c57a2ebd5b3b30caa634d2c2051ed9632423ab33 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOps.td @@ -600,29 +600,30 @@ def LoopNestOp : OpenMP_Op<"loop_nest", [SameVariadicOperandSize, //===----------------------------------------------------------------------===// def WsloopOp : OpenMP_Op<"wsloop", [AttrSizedOperandSegments, - AllTypesMatch<["lowerBound", "upperBound", "step"]>, DeclareOpInterfaceMethods, - RecursiveMemoryEffects, ReductionClauseInterface]> { + RecursiveMemoryEffects, ReductionClauseInterface, + SingleBlockImplicitTerminator<"TerminatorOp">]> { let summary = "worksharing-loop construct"; let description = [{ The worksharing-loop construct specifies that the iterations of the loop(s) will be executed in parallel by threads in the current context. These iterations are spread across threads that already exist in the enclosing - parallel region. The lower and upper bounds specify a half-open range: the - range includes the lower bound but does not include the upper bound. If the - `inclusive` attribute is specified then the upper bound is also included. + parallel region. - The body region can contain any number of blocks. The region is terminated - by "omp.yield" instruction without operands. + The body region can only contain a single block which must contain a single + operation and a terminator. The operation must be another compatible loop + wrapper or an `omp.loop_nest`. ``` - omp.wsloop - for (%i1, %i2) : index = (%c0, %c0) to (%c10, %c10) step (%c1, %c1) { - %a = load %arrA[%i1, %i2] : memref - %b = load %arrB[%i1, %i2] : memref - %sum = arith.addf %a, %b : f32 - store %sum, %arrC[%i1, %i2] : memref - omp.yield + omp.wsloop { + omp.loop_nest (%i1, %i2) : index = (%c0, %c0) to (%c10, %c10) step (%c1, %c1) { + %a = load %arrA[%i1, %i2] : memref + %b = load %arrB[%i1, %i2] : memref + %sum = arith.addf %a, %b : f32 + store %sum, %arrC[%i1, %i2] : memref + omp.yield + } + omp.terminator } ``` @@ -665,10 +666,7 @@ def WsloopOp : OpenMP_Op<"wsloop", [AttrSizedOperandSegments, passed by reference. }]; - let arguments = (ins Variadic:$lowerBound, - Variadic:$upperBound, - Variadic:$step, - Variadic:$linear_vars, + let arguments = (ins Variadic:$linear_vars, Variadic:$linear_step_vars, Variadic:$reduction_vars, OptionalAttr:$reductions, @@ -679,22 +677,16 @@ def WsloopOp : OpenMP_Op<"wsloop", [AttrSizedOperandSegments, UnitAttr:$nowait, UnitAttr:$byref, ConfinedAttr, [IntMinValue<0>]>:$ordered_val, - OptionalAttr:$order_val, - UnitAttr:$inclusive); + OptionalAttr:$order_val); let builders = [ - OpBuilder<(ins "ValueRange":$lowerBound, "ValueRange":$upperBound, - "ValueRange":$step, - CArg<"ArrayRef", "{}">:$attributes)>, + OpBuilder<(ins CArg<"ArrayRef", "{}">:$attributes)>, OpBuilder<(ins CArg<"const WsloopClauseOps &">:$clauses)> ]; let regions = (region AnyRegion:$region); let extraClassDeclaration = [{ - /// Returns the number of loops in the worksharing-loop nest. - unsigned getNumLoops() { return getLowerBound().size(); } - /// Returns the number of reduction variables. unsigned getNumReductionVars() { return getReductionVars().size(); } }]; @@ -711,9 +703,8 @@ def WsloopOp : OpenMP_Op<"wsloop", [AttrSizedOperandSegments, |`byref` $byref |`ordered` `(` $ordered_val `)` |`order` `(` custom($order_val) `)` - ) custom($region, $lowerBound, $upperBound, $step, type($step), - $reduction_vars, type($reduction_vars), $reductions, - $inclusive) attr-dict + ) custom($region, $reduction_vars, type($reduction_vars), + $reductions) attr-dict }]; let hasVerifier = 1; } @@ -732,7 +723,7 @@ def SimdOp : OpenMP_Op<"simd", [AttrSizedOperandSegments, transformed into a SIMD loop (that is, multiple iterations of the loop can be executed concurrently using SIMD instructions). - The body region can contain a single block which must contain a single + The body region can only contain a single block which must contain a single operation and a terminator. The operation must be another compatible loop wrapper or an `omp.loop_nest`. @@ -766,6 +757,7 @@ def SimdOp : OpenMP_Op<"simd", [AttrSizedOperandSegments, store %sum, %arrC[%i1, %i2] : memref omp.yield } + omp.terminator } ``` }]; @@ -805,8 +797,8 @@ def SimdOp : OpenMP_Op<"simd", [AttrSizedOperandSegments, def YieldOp : OpenMP_Op<"yield", [Pure, ReturnLike, Terminator, - ParentOneOf<["LoopNestOp", "WsloopOp", "DeclareReductionOp", - "AtomicUpdateOp", "PrivateClauseOp"]>]> { + ParentOneOf<["AtomicUpdateOp", "DeclareReductionOp", "LoopNestOp", + "PrivateClauseOp"]>]> { let summary = "loop yield and termination operation"; let description = [{ "omp.yield" yields SSA values from the OpenMP dialect op region and @@ -846,7 +838,7 @@ def DistributeOp : OpenMP_Op<"distribute", [AttrSizedOperandSegments, iterations are spread across threads that already exist in the enclosing region. - The body region can contain a single block which must contain a single + The body region can only contain a single block which must contain a single operation and a terminator. The operation must be another compatible loop wrapper or an `omp.loop_nest`. @@ -864,6 +856,7 @@ def DistributeOp : OpenMP_Op<"distribute", [AttrSizedOperandSegments, store %sum, %arrC[%i1, %i2] : memref omp.yield } + omp.terminator } ``` // TODO: private_var, firstprivate_var, lastprivate_var, collapse @@ -1029,7 +1022,7 @@ def TaskloopOp : OpenMP_Op<"taskloop", [AttrSizedOperandSegments, iterations are distributed across tasks generated by the construct and scheduled to be executed. - The body region can contain a single block which must contain a single + The body region can only contain a single block which must contain a single operation and a terminator. The operation must be another compatible loop wrapper or an `omp.loop_nest`. @@ -1042,6 +1035,7 @@ def TaskloopOp : OpenMP_Op<"taskloop", [AttrSizedOperandSegments, store %sum, %arrC[%i1, %i2] : memref omp.yield } + omp.terminator } ``` diff --git a/mlir/include/mlir/Dialect/SCF/Transforms/Passes.h b/mlir/include/mlir/Dialect/SCF/Transforms/Passes.h index 90b315e83a8cfdb5765c4912d27bc4a94e7004bf..31c3d0eb629d28056930ebe7935937f067541d6d 100644 --- a/mlir/include/mlir/Dialect/SCF/Transforms/Passes.h +++ b/mlir/include/mlir/Dialect/SCF/Transforms/Passes.h @@ -59,6 +59,9 @@ createParallelLoopTilingPass(llvm::ArrayRef tileSize = {}, /// loop range. std::unique_ptr createForLoopRangeFoldingPass(); +/// Creates a pass that converts SCF forall loops to SCF for loops. +std::unique_ptr createForallToForLoopPass(); + // Creates a pass which lowers for loops into while loops. std::unique_ptr createForToWhileLoopPass(); diff --git a/mlir/include/mlir/Dialect/SCF/Transforms/Passes.td b/mlir/include/mlir/Dialect/SCF/Transforms/Passes.td index 350611ad86873d08d831aa9537575ce010f78961..a7aeb42d60c0e975525b56619766e4590c4e0de8 100644 --- a/mlir/include/mlir/Dialect/SCF/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/SCF/Transforms/Passes.td @@ -120,6 +120,11 @@ def SCFForLoopRangeFolding : Pass<"scf-for-loop-range-folding"> { let constructor = "mlir::createForLoopRangeFoldingPass()"; } +def SCFForallToForLoop : Pass<"scf-forall-to-for"> { + let summary = "Convert SCF forall loops to SCF for loops"; + let constructor = "mlir::createForallToForLoopPass()"; +} + def SCFForToWhileLoop : Pass<"scf-for-to-while"> { let summary = "Convert SCF for loops to SCF while loops"; let constructor = "mlir::createForToWhileLoopPass()"; diff --git a/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h b/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h index 220dcb35571d27bb0cef3455a4872bb246963d80..b063e6e775e63402990b666e93c280a3accf239d 100644 --- a/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h +++ b/mlir/include/mlir/Dialect/SCF/Transforms/Transforms.h @@ -28,10 +28,17 @@ class Value; namespace scf { class IfOp; +class ForallOp; class ForOp; class ParallelOp; class WhileOp; +/// Try converting scf.forall into a set of nested scf.for loops. +/// The newly created scf.for ops will be returned through the `results` +/// vector if provided. +LogicalResult forallToForLoop(RewriterBase &rewriter, ForallOp forallOp, + SmallVectorImpl *results = nullptr); + /// Fuses all adjacent scf.parallel operations with identical bounds and step /// into one scf.parallel operations. Uses a naive aliasing and dependency /// analysis. diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td index 4a9b9169ae4b86904d1eeb7465b82b2c98e86004..eefa4c71bbd2caed84a47d1f1d1c63ffdf79a518 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorAttrDefs.td @@ -167,7 +167,7 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", - **soa** : only applicable to singleton levels, fuses the singleton level in SoA (structure of arrays) scheme. - In addition to the map, the following two fields are optional: + In addition to the map, the following fields are optional: - The required bitwidth for position storage (integral offsets into the sparse storage scheme). A narrow width reduces the memory @@ -183,6 +183,23 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", coordinate over all levels). The choices are `8`, `16`, `32`, `64`, or, the default, `0` to indicate a native bitwidth. + - The explicit value for the sparse tensor. If explicitVal is set, + then all the non-zero values in the tensor have the same explicit value. + The default value Attribute() indicates that it is not set. This + is useful for binary-valued sparse tensors whose values can either + be an implicit value (0 by default) or an explicit value (such as 1). + In this approach, we don't store explicit/implicit values, and metadata + (such as position and coordinate arrays) alone fully defines the original tensor. + This yields additional savings for the storage requirements, + as well as for the computational time, since we skip operating on + implicit values and can constant fold the explicit values where they are used. + + - The implicit value for the sparse tensor. If implicitVal is set, + then the "zero" value in the tensor is equal to the implicit value. + For now, we only support `0` as the implicit value but it could be + extended in the future. The default value Attribute() indicates that + the implicit value is `0` (same type as the tensor element type). + Examples: ```mlir @@ -226,6 +243,15 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", }> ... tensor<8x8xf64, #DCSC> ... + // Doubly compressed sparse column storage with specific + // explicit and implicit values. + #DCSC = #sparse_tensor.encoding<{ + map = (i, j) -> (j : compressed, i : compressed), + explicitVal = 1 : i64, + implicitVal = 0 : i64 + }> + ... tensor<8x8xi64, #DCSC> ... + // Block sparse row storage (2x3 blocks). #BSR = #sparse_tensor.encoding<{ map = ( i, j ) -> @@ -307,6 +333,12 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", // The required bitwidth for coordinate storage. "unsigned":$crdWidth, + // The required explicit value. + "::mlir::Attribute":$explicitVal, + + // The required implicit value. + "::mlir::Attribute":$implicitVal, + // A slice attribute for each dimension of the tensor type. ArrayRefParameter< "::mlir::sparse_tensor::SparseTensorDimSliceAttr", @@ -319,7 +351,9 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", CArg<"AffineMap", "{}">:$dimToLvl, CArg<"AffineMap", "{}">:$lvlToDim, CArg<"unsigned", "0">:$posWidth, - CArg<"unsigned", "0">:$crdWidth), [{ + CArg<"unsigned", "0">:$crdWidth, + CArg<"::mlir::Attribute", "{}">:$explicitVal, + CArg<"::mlir::Attribute", "{}">:$implicitVal), [{ if (!dimToLvl) { dimToLvl = ::mlir::AffineMap::getMultiDimIdentityMap(lvlTypes.size(), $_ctxt); } @@ -327,6 +361,7 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", lvlToDim = ::mlir::sparse_tensor::inferLvlToDim(dimToLvl, $_ctxt); } return $_get($_ctxt, lvlTypes, dimToLvl, lvlToDim, posWidth, crdWidth, + explicitVal, implicitVal, ArrayRef<::mlir::sparse_tensor::SparseTensorDimSliceAttr>{}); }]> ]; @@ -353,6 +388,22 @@ def SparseTensorEncodingAttr : SparseTensor_Attr<"SparseTensorEncoding", /// reset to the default, and all other fields inherited from `this`. SparseTensorEncodingAttr withoutBitWidths() const; + /// Constructs a new encoding with the given explicit value + /// and all other fields inherited from `this`. + SparseTensorEncodingAttr withExplicitVal(Attribute explicitVal) const; + + /// Constructs a new encoding with the explicit value + /// reset to the default, and all other fields inherited from `this`. + SparseTensorEncodingAttr withoutExplicitVal() const; + + /// Constructs a new encoding with the given implicit value + /// and all other fields inherited from `this`. + SparseTensorEncodingAttr withImplicitVal(Attribute implicitVal) const; + + /// Constructs a new encoding with the implicit value + /// reset to the default, and all other fields inherited from `this`. + SparseTensorEncodingAttr withoutImplicitVal() const; + /// Constructs a new encoding with the given dimSlices, and all /// other fields inherited from `this`. SparseTensorEncodingAttr withDimSlices(ArrayRef<::mlir::sparse_tensor::SparseTensorDimSliceAttr> dimSlices) const; diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h index 825d89a408febe43d729f0364bd3b6de596ca7e4..34d99913fbd51beef8f6de3b11df4eedaf59a93d 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensorType.h @@ -115,6 +115,22 @@ public: return withEncoding(enc.withoutBitWidths()); } + SparseTensorType withExplicitVal(Attribute explicitVal) const { + return withEncoding(enc.withExplicitVal(explicitVal)); + } + + SparseTensorType withoutExplicitVal() const { + return withEncoding(enc.withoutExplicitVal()); + } + + SparseTensorType withImplicitVal(Attribute implicitVal) const { + return withEncoding(enc.withImplicitVal(implicitVal)); + } + + SparseTensorType withoutImplicitVal() const { + return withEncoding(enc.withoutImplicitVal()); + } + SparseTensorType withDimSlices(ArrayRef dimSlices) const { return withEncoding(enc.withDimSlices(dimSlices)); @@ -327,6 +343,12 @@ public: /// Returns the position-overhead bitwidth, defaulting to zero. unsigned getPosWidth() const { return enc ? enc.getPosWidth() : 0; } + /// Returns the explicit value, defaulting to null Attribute for unset. + Attribute getExplicitVal() const { return enc.getExplicitVal(); } + + /// Returns the implicit value, defaulting to null Attribute for 0. + Attribute getImplicitVal() const { return enc.getImplicitVal(); } + /// Returns the coordinate-overhead MLIR type, defaulting to `IndexType`. Type getCrdType() const { return enc.getCrdElemType(); } diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt index f1740e9ed929a6ce0321a69a79ec016d7a189887..3f8cac4dc07c3cf7c45e05479811ea22edce5162 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt +++ b/mlir/include/mlir/Dialect/XeGPU/IR/CMakeLists.txt @@ -2,12 +2,12 @@ add_mlir_dialect(XeGPU xegpu) add_mlir_doc(XeGPU XeGPU Dialects/ -gen-dialect-doc -dialect=xegpu) set(LLVM_TARGET_DEFINITIONS XeGPU.td) -mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls) -mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs) +mlir_tablegen(XeGPUAttrs.h.inc -gen-attrdef-decls -attrdefs-dialect=xegpu) +mlir_tablegen(XeGPUAttrs.cpp.inc -gen-attrdef-defs -attrdefs-dialect=xegpu) add_public_tablegen_target(MLIRXeGPUAttrsIncGen) add_dependencies(mlir-headers MLIRXeGPUAttrsIncGen) -set(LLVM_TARGET_DEFINITIONS XeGPU.td) +set(LLVM_TARGET_DEFINITIONS XeGPUAttrs.td) mlir_tablegen(XeGPUEnums.h.inc -gen-enum-decls) mlir_tablegen(XeGPUEnums.cpp.inc -gen-enum-defs) add_public_tablegen_target(MLIRXeGPUEnumsIncGen) diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h index eca9255ff3974b799418acb11cef4a98cf240e83..7ac0cf77fe59bb12ea59a3f4d37d054bee96db85 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPU.h @@ -10,6 +10,7 @@ #define MLIR_DIALECT_XEGPU_IR_XEGPU_H #include "mlir/Bytecode/BytecodeOpInterface.h" +#include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/IR/BuiltinTypes.h" #include "mlir/IR/Dialect.h" #include "mlir/IR/TypeUtilities.h" @@ -19,7 +20,7 @@ namespace mlir { namespace xegpu { -// placeholder +class TensorDescType; } // namespace xegpu } // namespace mlir diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td index 6579d07ec26215c727dccd110800d6b31874e86f..f3ca09a6a68ea8c5729b6cc0903cb3f7006952e9 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td @@ -10,6 +10,7 @@ #define MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td" +include "mlir/IR/AttrTypeBase.td" include "mlir/IR/EnumAttr.td" class XeGPUAttr traits = [], @@ -98,4 +99,21 @@ def XeGPU_CacheHintAttr let assemblyFormat = "`<` $value `>`"; } +def XeGPU_FenceScopeWorkgroup: I32EnumAttrCase<"Workgroup", 0, "workgroup">; +def XeGPU_FenceScopeGPU: I32EnumAttrCase<"GPU", 1, "gpu">; +def XeGPU_FenceScope: I32EnumAttr<"FenceScope", + "The enumeration for the scope of fence operation.", + [XeGPU_FenceScopeWorkgroup, XeGPU_FenceScopeGPU]> { + let genSpecializedAttr = 0; + let cppNamespace = "::mlir::xegpu"; +} + +def XeGPU_FenceScopeAttr: + EnumAttr { + let summary = [{Describes the scope of fence. + "workgroup" means that the scope is within each work group. + "gpu" means the scope is across work groups within the gpu.}]; + let assemblyFormat = "$value"; +} + #endif // MLIR_DIALECT_XEGPU_IR_XEGPUATTRS_TD \ No newline at end of file diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td index c2f09319c790e0a7183c5561b50b135071c25ee0..765f218f95d2691e19694d72b7c62ea1cd22b32a 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td @@ -17,12 +17,14 @@ def XeGPU_Dialect : Dialect { let summary = "The XeGPU dialect that models Intel GPU's ISA"; let description = [{ The XeGPU dialect models Intel Xe ISA semantics but works at vector and - TensorDesc data type. It provides 1:1 mappings to match Xe instructions + TensorDesc data type. It provides 1:1 mappings to match Xe instructions like DPAS and 2D block load. The matrix size being processed at this level exactly matches the hardware instructions or the intrinsic supported by the lower-level GPU compiler. }]; + let dependentDialects = ["arith::ArithDialect"]; + let useDefaultTypePrinterParser = true; let useDefaultAttributePrinterParser = true; } diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td index c6f7f83441b96cf7bac64733e242265012f970bb..88f2e1acfeeb581d7a1e60738fca36e09a01eae0 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td @@ -9,7 +9,7 @@ #ifndef MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD #define MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD -include "mlir/IR/AttrTypeBase.td" +include "mlir/Dialect/Arith/IR/ArithBase.td" include "mlir/Dialect/XeGPU/IR/XeGPUAttrs.td" include "mlir/Dialect/XeGPU/IR/XeGPUDialect.td" include "mlir/Dialect/XeGPU/IR/XeGPUTypes.td" @@ -36,7 +36,7 @@ class XeGPU_Op traits = []>: static ::mlir::ParseResult parseProperties(::mlir::OpAsmParser &parser, ::mlir::OperationState &result) { - if (mlir::succeeded(parser.parseLess())) { + if (mlir::succeeded(parser.parseOptionalLess())) { if (parser.parseAttribute(result.propertiesAttr) || parser.parseGreater()) return failure(); } @@ -254,7 +254,7 @@ def XeGPU_LoadNdOp : XeGPU_Op<"load_nd", [AllElementTypesMatch<["value", "Tensor a block of data from memory to register. It takes a set of optional cache hints for each level of cache, L1, L2 and L3. If hardware does not have a correspoding cache, Corresponding cache hint attribute will be masked. - vnni transform is an hardware feature for Intel GPU, which is used to + VNNI transformation is an hardware feature for Intel GPU, which is used to do data packing during the load for B operand of matrix operation, if the bit width of the data type is less then 32 bits, e.g., fp16. And transpose is another Intel hardware feature, which will do transpose @@ -425,10 +425,6 @@ def XeGPU_CreateDescOp: XeGPU_Op<"create_tdesc", [Pure, ViewLikeOpInterface]> { %0 = memref.alloc() : memref<1024xf32> %1 = xegpu.create_tdesc %0[0, 4, 8, 12] {chunk_size = 8}: memref<1024xf32> -> TensorDesc<4x8xf32> ``` - - - - }]; let arguments = (ins XeGPU_BaseAddrType: $source, @@ -663,4 +659,153 @@ def XeGPU_UpdateOffsetOp: XeGPU_Op<"update_offset", }]; } +def XeGPU_DpasOp : XeGPU_Op<"dpas", [Pure, AllElementTypesMatch<["lhs", "rhs"]>]> { + let summary = "It performs mma computation"; + + let description = [{DPAS performs matrix multiplication on matrix A of `mxk` + size, B of `kxn` size, and accumulate on matrix C of `mxn` to the same size + matrix , `m=8`, `n=16` and `k=8 * 32/bit_width_of_elem_type`. So for fp16 + data type, the matrices are `A: vector<8x16xf16>`, `B: vector<16x16xf16>`, + and `C/D: vector<8x16xf32>`. Besides the matrix size requirements, DPAS + also requires A and B to be loaded with the required data layout. Specially, + VNNI layout is required for B operand. It is achieved via setting `vnni_axis = 0` + of the corresponding `load_nd` operator. To keep both operands as 3D vector, + operand A is loaded via setting `vnni_axis = 1` without impacting the + physical layouts change in register. Due to the VNNI transformation, A and B operands + are represented as 3D vector, with the last dimension representing the VNNI factor, + which is computed as `32/bit_width_of_elem_type`. Therefore, `A: vector<8x16xf16>` + is represented as `A: vector<8x8x2xf16>`, and `B: vector<16x16xf16>` is + represented as `B: vector<8x16x2xf16>`. + + Note: on PVC, the hardware can perform load with VNNI transformation when data + element type is 16-bit or lower precision, taking 2 or 4 elements from + the first dimension and inserted into the newly added innermost dimension. + }]; + + let arguments = (ins + XeGPU_DpasOpType : $lhs, + XeGPU_DpasOpType : $rhs, + Optional: $acc); + let results = (outs XeGPU_Vector2DType: $result); + + let extraClassDeclaration = [{ + VectorType getLhsType() { + return getLhs().getType(); + } + + VectorType getRhsType() { + return getRhs().getType(); + } + + VectorType getAccType() { + if (getAcc()) + return getAcc().getType(); + return {}; + } + + VectorType getResultType() { + return getResult().getType(); + } + }]; + + let assemblyFormat = [{ + $lhs `,` $rhs (`,` $acc^)? attr-dict `:` type($lhs)`,` type($rhs) (`,` type($acc)^)? `->` type($result) + }]; + + let hasVerifier = 1; +} + +def XeGPU_AtomicRMWOp: XeGPU_Op<"atomic_rmw", [Pure, + AllElementTypesMatch<["tensorDesc", "value", "result"]>, + AllShapesMatch<["tensorDesc", "mask", "value", "result"]>]> { + let summary = "Atomic ready-modify-write operation on the TensorDesc. "; + + let description = [{ + The `xegpu.atomic_rmw` operation provides a way to perform a read-modify-write + operation on the region described by the `TensorDesc` free from data races. The + `kind` enumeration specifies the modification to be performed, The `mask` operand + has the same shape with `TensorDesc`, and is used to enable or disable specific + data points of the `TensorDesc`. The `value` operand represents the new value to + be applied during the modification. + }]; + + let arguments = (ins + AtomicRMWKindAttr:$kind, + XeGPU_TensorDesc:$tensorDesc, + XeGPU_MaskType:$mask, + XeGPU_ValueType:$value); + + let results = (outs XeGPU_ValueType:$result); + + let assemblyFormat = [{ + $kind $tensorDesc `,` $mask `,` $value attr-dict `:` + type($tensorDesc) `,` type($mask) `,` type($value) `->` type($result) + }]; +} + +def XeGPU_AllocNbarrierOp: XeGPU_Op<"alloc_nbarrier", []> { + let summary = "It allocates a set of named barriers."; + let description = [{AllocNbarrier is to create a set of named barriers as + specified by `nbarrier_num`. Named barriers are workgroup level resources, + and are shared by all threads in the workgroup. For example, there are + up to 32 barriers (range 0-31) for each XeCore on PVC. A typical use case + is that a workgroup is partitioned into N subgroups of threads (N <= 32), + and each subgroup coordinating their work with a separate barrier with id + range from 0 to N respectively.}]; + let arguments = (ins I64Attr: $nbarrier_num); + let assemblyFormat = "$nbarrier_num attr-dict"; +} + +def XeGPU_InitNbarrierOp: XeGPU_Op<"init_nbarrier", []> { + let summary = "It assigns a named barrier to the current thread."; + let description = [{InitNbarrierOp assigns the named barrier with the specified + barrier ID (0~31) to the current thread. Multiple threads may bind to the + same named barrier, and the `participant_thread_num` specifies the total + number of threads associated with the nbarrier. It returns an object of + NbarrierType representing the barrier}]; + + let arguments = (ins I8: $nbarrier_id, + I8: $participant_thread_num); + let results = (outs XeGPU_Nbarrier: $result); + let assemblyFormat = [{ + $nbarrier_id `,` $participant_thread_num attr-dict `:` + type($nbarrier_id) `,` type($participant_thread_num) `->` qualified(type($result)) + }]; +} + +def XeGPU_NbarrierArriveOp: XeGPU_Op<"nbarrier_arrive", []> { + let summary = "It signals the arrival at the named barrier."; + let description = [{NbarrierArriveOp signals the hardware (or other threads) + that the current thread has produced its data for the consumer threads. When + the hardware signalled by `participant_thread_num` threads for the named barrier, + it will notify the threads waiting for the named barrier to continue their work.}]; + + let arguments = (ins XeGPU_Nbarrier: $nbarrier); + let assemblyFormat = [{ $nbarrier attr-dict `:` qualified(type($nbarrier))}]; +} + +def XeGPU_NbarrierWaitOp: XeGPU_Op<"nbarrier_wait", []> { + let summary = "It waits for a named barrier."; + let description = [{NbarrierWaitOp signals the hardware which named barrier + the current thread is waiting for, such that it can get notified when the + named barrier is completed.}]; + let arguments = (ins XeGPU_Nbarrier: $nbarrier); + let assemblyFormat = [{ $nbarrier attr-dict `:` qualified(type($nbarrier)) }]; +} + +def XeGPU_FenceOp: XeGPU_Op<"fence", []> { + let summary = "It synchronizes memory accesses."; + let description = [{It synchronizes the memory access between + write and following read or write. + 1. `Memory_kind` describes the memory kind. "global" means the global memory, + "slm" means the share local memory. + 2. `Fence_scope` describes the scope of fence. "Workgroup" means that the scope would be + within each workgroup. "GPU" means the scope would be across workgroups within the GPU. + }]; + let arguments = (ins XeGPU_MemoryScopeAttr: $memory_kind, + XeGPU_FenceScopeAttr: $fence_scope); + let assemblyFormat = [{`memory_kind` `=` `` $memory_kind `,` `fence_scope` `=` `` $fence_scope attr-dict}]; + let extraClassDeclaration = extraBaseClassDeclaration; +} + #endif // MLIR_DIALECT_XEGPU_IR_XEGPUOPS_TD diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td index 4cd4e5411653c1aaa44efe5fc204bdfc17fee1f6..bab0e4afb1e5ed6d2b99f513513e549ef7089bbb 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUTypes.td @@ -151,4 +151,15 @@ def XeGPU_TensorDesc: XeGPUTypeDef<"TensorDesc", "tensor_desc", } + +def XeGPU_Nbarrier: XeGPUTypeDef<"Nbarrier", "nbarrier", [], "mlir::Type"> { + let summary = "!xegpu.nbarrier a custom XeGPU type representing a barrier."; + + let extraClassDeclaration = [{ + static NbarrierType get(mlir::MLIRContext *context) { + return Base::get(context); + }; + }]; +} + #endif // MLIR_DIALECT_XEGPU_IR_XEGPUTYPES_TD diff --git a/mlir/include/mlir/Interfaces/MemorySlotInterfaces.td b/mlir/include/mlir/Interfaces/MemorySlotInterfaces.td index 8c642c0ed26aca17ad78a110c47f5092529e386b..764fa6d547b2eb52c19ca8c1dd1d591b1971739a 100644 --- a/mlir/include/mlir/Interfaces/MemorySlotInterfaces.td +++ b/mlir/include/mlir/Interfaces/MemorySlotInterfaces.td @@ -128,6 +128,7 @@ def PromotableMemOpInterface : OpInterface<"PromotableMemOpInterface"> { "::mlir::Value", "getStored", (ins "const ::mlir::MemorySlot &":$slot, "::mlir::RewriterBase &":$rewriter, + "::mlir::Value":$reachingDef, "const ::mlir::DataLayout &":$dataLayout) >, InterfaceMethod<[{ diff --git a/mlir/include/mlir/TableGen/CodeGenHelpers.h b/mlir/include/mlir/TableGen/CodeGenHelpers.h index dd17a44c889bbe383064f73b8cf2e8a1f96c1a99..c263c69c53d1e318d411a26473b475c38b6cb6dd 100644 --- a/mlir/include/mlir/TableGen/CodeGenHelpers.h +++ b/mlir/include/mlir/TableGen/CodeGenHelpers.h @@ -99,8 +99,14 @@ private: /// class StaticVerifierFunctionEmitter { public: + /// Create a constraint uniquer with a unique prefix derived from the record + /// keeper with an optional tag. StaticVerifierFunctionEmitter(raw_ostream &os, - const llvm::RecordKeeper &records); + const llvm::RecordKeeper &records, + StringRef tag = ""); + + /// Collect and unique all the constraints used by operations. + void collectOpConstraints(ArrayRef opDefs); /// Collect and unique all compatible type, attribute, successor, and region /// constraints from the operations in the file and emit them at the top of @@ -108,7 +114,7 @@ public: /// /// Constraints that do not meet the restriction that they can only reference /// `$_self` and `$_op` are not uniqued. - void emitOpConstraints(ArrayRef opDefs, bool emitDecl); + void emitOpConstraints(ArrayRef opDefs); /// Unique all compatible type and attribute constraints from a pattern file /// and emit them at the top of the generated file. @@ -177,8 +183,6 @@ private: /// Emit pattern constraints. void emitPatternConstraints(); - /// Collect and unique all the constraints used by operations. - void collectOpConstraints(ArrayRef opDefs); /// Collect and unique all pattern constraints. void collectPatternConstraints(ArrayRef constraints); diff --git a/mlir/include/mlir/Tools/lsp-server-support/Transport.h b/mlir/include/mlir/Tools/lsp-server-support/Transport.h index ce742be7a941c934519cfe47e36f6c57712f3e74..44c71058cf717c797393f126fe492cc70ff88c19 100644 --- a/mlir/include/mlir/Tools/lsp-server-support/Transport.h +++ b/mlir/include/mlir/Tools/lsp-server-support/Transport.h @@ -147,9 +147,15 @@ public: void (ThisT::*handler)(const Param &)) { notificationHandlers[method] = [method, handler, thisPtr](llvm::json::Value rawParams) { - llvm::Expected param = parse(rawParams, method, "request"); - if (!param) - return llvm::consumeError(param.takeError()); + llvm::Expected param = + parse(rawParams, method, "notification"); + if (!param) { + return llvm::consumeError( + llvm::handleErrors(param.takeError(), [](const LSPError &lspError) { + Logger::error("JSON parsing error: {0}", + lspError.message.c_str()); + })); + } (thisPtr->*handler)(*param); }; } diff --git a/mlir/lib/Bindings/Python/DialectLLVM.cpp b/mlir/lib/Bindings/Python/DialectLLVM.cpp index 843707751dd84981b8bb2f0075e1881fdd29548f..42a4c8c0793ba8a5c3acb383a461d76eb9b2b33f 100644 --- a/mlir/lib/Bindings/Python/DialectLLVM.cpp +++ b/mlir/lib/Bindings/Python/DialectLLVM.cpp @@ -19,6 +19,11 @@ using namespace mlir::python; using namespace mlir::python::adaptors; void populateDialectLLVMSubmodule(const pybind11::module &m) { + + //===--------------------------------------------------------------------===// + // StructType + //===--------------------------------------------------------------------===// + auto llvmStructType = mlir_type_subclass(m, "StructType", mlirTypeIsALLVMStructType); @@ -35,8 +40,8 @@ void populateDialectLLVMSubmodule(const pybind11::module &m) { } return cls(type); }, - py::arg("cls"), py::arg("elements"), py::kw_only(), - py::arg("packed") = false, py::arg("loc") = py::none()); + "cls"_a, "elements"_a, py::kw_only(), "packed"_a = false, + "loc"_a = py::none()); llvmStructType.def_classmethod( "get_identified", @@ -44,8 +49,7 @@ void populateDialectLLVMSubmodule(const pybind11::module &m) { return cls(mlirLLVMStructTypeIdentifiedGet( context, mlirStringRefCreate(name.data(), name.size()))); }, - py::arg("cls"), py::arg("name"), py::kw_only(), - py::arg("context") = py::none()); + "cls"_a, "name"_a, py::kw_only(), "context"_a = py::none()); llvmStructType.def_classmethod( "get_opaque", @@ -53,7 +57,7 @@ void populateDialectLLVMSubmodule(const pybind11::module &m) { return cls(mlirLLVMStructTypeOpaqueGet( context, mlirStringRefCreate(name.data(), name.size()))); }, - py::arg("cls"), py::arg("name"), py::arg("context") = py::none()); + "cls"_a, "name"_a, "context"_a = py::none()); llvmStructType.def( "set_body", @@ -65,7 +69,7 @@ void populateDialectLLVMSubmodule(const pybind11::module &m) { "Struct body already set to different content."); } }, - py::arg("elements"), py::kw_only(), py::arg("packed") = false); + "elements"_a, py::kw_only(), "packed"_a = false); llvmStructType.def_classmethod( "new_identified", @@ -75,8 +79,8 @@ void populateDialectLLVMSubmodule(const pybind11::module &m) { ctx, mlirStringRefCreate(name.data(), name.length()), elements.size(), elements.data(), packed)); }, - py::arg("cls"), py::arg("name"), py::arg("elements"), py::kw_only(), - py::arg("packed") = false, py::arg("context") = py::none()); + "cls"_a, "name"_a, "elements"_a, py::kw_only(), "packed"_a = false, + "context"_a = py::none()); llvmStructType.def_property_readonly( "name", [](MlirType type) -> std::optional { @@ -105,6 +109,29 @@ void populateDialectLLVMSubmodule(const pybind11::module &m) { llvmStructType.def_property_readonly( "opaque", [](MlirType type) { return mlirLLVMStructTypeIsOpaque(type); }); + + //===--------------------------------------------------------------------===// + // PointerType + //===--------------------------------------------------------------------===// + + mlir_type_subclass(m, "PointerType", mlirTypeIsALLVMPointerType) + .def_classmethod( + "get", + [](py::object cls, std::optional addressSpace, + MlirContext context) { + CollectDiagnosticsToStringScope scope(context); + MlirType type = mlirLLVMPointerTypeGet( + context, addressSpace.has_value() ? *addressSpace : 0); + if (mlirTypeIsNull(type)) { + throw py::value_error(scope.takeMessage()); + } + return cls(type); + }, + "cls"_a, "address_space"_a = py::none(), py::kw_only(), + "context"_a = py::none()) + .def_property_readonly("address_space", [](MlirType type) { + return mlirLLVMPointerTypeGetAddressSpace(type); + }); } PYBIND11_MODULE(_mlirDialectsLLVM, m) { diff --git a/mlir/lib/Bindings/Python/DialectSparseTensor.cpp b/mlir/lib/Bindings/Python/DialectSparseTensor.cpp index 171faf9e00874623276ed7cf746f47411b749db9..584981cfe99bf161978b6748c042ffc39b76d9ff 100644 --- a/mlir/lib/Bindings/Python/DialectSparseTensor.cpp +++ b/mlir/lib/Bindings/Python/DialectSparseTensor.cpp @@ -42,16 +42,19 @@ static void populateDialectSparseTensorSubmodule(const py::module &m) { [](py::object cls, std::vector lvlTypes, std::optional dimToLvl, std::optional lvlToDim, int posWidth, int crdWidth, - MlirContext context) { + std::optional explicitVal, + std::optional implicitVal, MlirContext context) { return cls(mlirSparseTensorEncodingAttrGet( context, lvlTypes.size(), lvlTypes.data(), dimToLvl ? *dimToLvl : MlirAffineMap{nullptr}, lvlToDim ? *lvlToDim : MlirAffineMap{nullptr}, posWidth, - crdWidth)); + crdWidth, explicitVal ? *explicitVal : MlirAttribute{nullptr}, + implicitVal ? *implicitVal : MlirAttribute{nullptr})); }, py::arg("cls"), py::arg("lvl_types"), py::arg("dim_to_lvl"), py::arg("lvl_to_dim"), py::arg("pos_width"), py::arg("crd_width"), - py::arg("context") = py::none(), + py::arg("explicit_val") = py::none(), + py::arg("implicit_val") = py::none(), py::arg("context") = py::none(), "Gets a sparse_tensor.encoding from parameters.") .def_classmethod( "build_level_type", @@ -97,6 +100,24 @@ static void populateDialectSparseTensorSubmodule(const py::module &m) { mlirSparseTensorEncodingAttrGetPosWidth) .def_property_readonly("crd_width", mlirSparseTensorEncodingAttrGetCrdWidth) + .def_property_readonly( + "explicit_val", + [](MlirAttribute self) -> std::optional { + MlirAttribute ret = + mlirSparseTensorEncodingAttrGetExplicitVal(self); + if (mlirAttributeIsNull(ret)) + return {}; + return ret; + }) + .def_property_readonly( + "implicit_val", + [](MlirAttribute self) -> std::optional { + MlirAttribute ret = + mlirSparseTensorEncodingAttrGetImplicitVal(self); + if (mlirAttributeIsNull(ret)) + return {}; + return ret; + }) .def_property_readonly( "structured_n", [](MlirAttribute self) -> unsigned { diff --git a/mlir/lib/CAPI/Dialect/LLVM.cpp b/mlir/lib/CAPI/Dialect/LLVM.cpp index 21c66f38a8af036c290d6ac11f71de39084e562a..108ebe5367d567551b63c6dc9722c2fc85eecb75 100644 --- a/mlir/lib/CAPI/Dialect/LLVM.cpp +++ b/mlir/lib/CAPI/Dialect/LLVM.cpp @@ -27,6 +27,14 @@ MlirType mlirLLVMPointerTypeGet(MlirContext ctx, unsigned addressSpace) { return wrap(LLVMPointerType::get(unwrap(ctx), addressSpace)); } +bool mlirTypeIsALLVMPointerType(MlirType type) { + return isa(unwrap(type)); +} + +unsigned mlirLLVMPointerTypeGetAddressSpace(MlirType pointerType) { + return cast(unwrap(pointerType)).getAddressSpace(); +} + MlirType mlirLLVMVoidTypeGet(MlirContext ctx) { return wrap(LLVMVoidType::get(unwrap(ctx))); } diff --git a/mlir/lib/CAPI/Dialect/SparseTensor.cpp b/mlir/lib/CAPI/Dialect/SparseTensor.cpp index 3ae06f220c5281bbf3b72cb8ccc553e1c204c34e..19171d64d4094975098144f9aa389e18f1c77b12 100644 --- a/mlir/lib/CAPI/Dialect/SparseTensor.cpp +++ b/mlir/lib/CAPI/Dialect/SparseTensor.cpp @@ -44,18 +44,20 @@ bool mlirAttributeIsASparseTensorEncodingAttr(MlirAttribute attr) { return isa(unwrap(attr)); } -MlirAttribute -mlirSparseTensorEncodingAttrGet(MlirContext ctx, intptr_t lvlRank, - MlirSparseTensorLevelType const *lvlTypes, - MlirAffineMap dimToLvl, MlirAffineMap lvlToDim, - int posWidth, int crdWidth) { +MlirAttribute mlirSparseTensorEncodingAttrGet( + MlirContext ctx, intptr_t lvlRank, + MlirSparseTensorLevelType const *lvlTypes, MlirAffineMap dimToLvl, + MlirAffineMap lvlToDim, int posWidth, int crdWidth, + MlirAttribute explicitVal, MlirAttribute implicitVal) { SmallVector cppLvlTypes; + cppLvlTypes.reserve(lvlRank); for (intptr_t l = 0; l < lvlRank; ++l) cppLvlTypes.push_back(static_cast(lvlTypes[l])); - return wrap(SparseTensorEncodingAttr::get(unwrap(ctx), cppLvlTypes, - unwrap(dimToLvl), unwrap(lvlToDim), - posWidth, crdWidth)); + + return wrap(SparseTensorEncodingAttr::get( + unwrap(ctx), cppLvlTypes, unwrap(dimToLvl), unwrap(lvlToDim), posWidth, + crdWidth, unwrap(explicitVal), unwrap(implicitVal))); } MlirAffineMap mlirSparseTensorEncodingAttrGetDimToLvl(MlirAttribute attr) { @@ -91,6 +93,14 @@ int mlirSparseTensorEncodingAttrGetCrdWidth(MlirAttribute attr) { return cast(unwrap(attr)).getCrdWidth(); } +MlirAttribute mlirSparseTensorEncodingAttrGetExplicitVal(MlirAttribute attr) { + return wrap(cast(unwrap(attr)).getExplicitVal()); +} + +MlirAttribute mlirSparseTensorEncodingAttrGetImplicitVal(MlirAttribute attr) { + return wrap(cast(unwrap(attr)).getImplicitVal()); +} + MlirSparseTensorLevelType mlirSparseTensorEncodingAttrBuildLvlType( enum MlirSparseTensorLevelFormat lvlFmt, const enum MlirSparseTensorLevelPropertyNondefault *properties, diff --git a/mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp b/mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp index 7f91367ad427a29c1abed1ea4870f9052a442bbf..d6f85451ee5d304270098a66b647598766bf6fe3 100644 --- a/mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp +++ b/mlir/lib/Conversion/SCFToOpenMP/SCFToOpenMP.cpp @@ -461,18 +461,50 @@ struct ParallelOpLowering : public OpRewritePattern { // Replace the loop. { OpBuilder::InsertionGuard allocaGuard(rewriter); - auto loop = rewriter.create( + // Create worksharing loop wrapper. + auto wsloopOp = rewriter.create(parallelOp.getLoc()); + if (!reductionVariables.empty()) { + wsloopOp.setReductionsAttr( + ArrayAttr::get(rewriter.getContext(), reductionDeclSymbols)); + wsloopOp.getReductionVarsMutable().append(reductionVariables); + } + rewriter.create(loc); // omp.parallel terminator. + + // The wrapper's entry block arguments will define the reduction + // variables. + llvm::SmallVector reductionTypes; + reductionTypes.reserve(reductionVariables.size()); + llvm::transform(reductionVariables, std::back_inserter(reductionTypes), + [](mlir::Value v) { return v.getType(); }); + rewriter.createBlock( + &wsloopOp.getRegion(), {}, reductionTypes, + llvm::SmallVector(reductionVariables.size(), + parallelOp.getLoc())); + + rewriter.setInsertionPoint( + rewriter.create(parallelOp.getLoc())); + + // Create loop nest and populate region with contents of scf.parallel. + auto loopOp = rewriter.create( parallelOp.getLoc(), parallelOp.getLowerBound(), parallelOp.getUpperBound(), parallelOp.getStep()); - rewriter.create(loc); - rewriter.inlineRegionBefore(parallelOp.getRegion(), loop.getRegion(), - loop.getRegion().begin()); + rewriter.inlineRegionBefore(parallelOp.getRegion(), loopOp.getRegion(), + loopOp.getRegion().begin()); - Block *ops = rewriter.splitBlock(&*loop.getRegion().begin(), - loop.getRegion().begin()->begin()); + // Remove reduction-related block arguments from omp.loop_nest and + // redirect uses to the corresponding omp.wsloop block argument. + mlir::Block &loopOpEntryBlock = loopOp.getRegion().front(); + unsigned numLoops = parallelOp.getNumLoops(); + rewriter.replaceAllUsesWith( + loopOpEntryBlock.getArguments().drop_front(numLoops), + wsloopOp.getRegion().getArguments()); + loopOpEntryBlock.eraseArguments( + numLoops, loopOpEntryBlock.getNumArguments() - numLoops); - rewriter.setInsertionPointToStart(&*loop.getRegion().begin()); + Block *ops = + rewriter.splitBlock(&loopOpEntryBlock, loopOpEntryBlock.begin()); + rewriter.setInsertionPointToStart(&loopOpEntryBlock); auto scope = rewriter.create(parallelOp.getLoc(), TypeRange()); @@ -481,11 +513,6 @@ struct ParallelOpLowering : public OpRewritePattern { rewriter.mergeBlocks(ops, scopeBlock); rewriter.setInsertionPointToEnd(&*scope.getBodyRegion().begin()); rewriter.create(loc, ValueRange()); - if (!reductionVariables.empty()) { - loop.setReductionsAttr( - ArrayAttr::get(rewriter.getContext(), reductionDeclSymbols)); - loop.getReductionVarsMutable().append(reductionVariables); - } } } diff --git a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp index 8fb8d16486560c08154e732a029b342022bf3096..d8fb3abc0bef8a723de5424e022fca4edfec293d 100644 --- a/mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp +++ b/mlir/lib/Conversion/TosaToLinalg/TosaToLinalgNamed.cpp @@ -101,9 +101,18 @@ static mlir::Value linalgBroadcastAndMaybeExtSI(PatternRewriter &rewriter, // The source tensor is broadcast to all the outer dimensions of the // result tensor. SmallVector sourceDims; - for (auto dim : llvm::seq(0, sourceRank)) { - auto expr = rewriter.getAffineDimExpr(dim + resultRank - sourceRank); - sourceDims.push_back(expr); + // In the case of a rank one source tensor with a single element TOSA + // specifies that the value be broadcast meaning we need an edge case for a + // constant map. + assert(sourceTy.hasStaticShape() && + "Dynamic broadcasting shapes not supported!"); + if (sourceRank == 1 && sourceTy.getDimSize(0) == 1) { + sourceDims.push_back(rewriter.getAffineConstantExpr(0)); + } else { + for (auto dim : llvm::seq(0, sourceRank)) { + auto expr = rewriter.getAffineDimExpr(dim + resultRank - sourceRank); + sourceDims.push_back(expr); + } } // Creating maps for the input and output of the broacast-like generic op. diff --git a/mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp b/mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp index f2ab3eae2c343ebd754e5bb7448bdb594b0ec1ef..6eeb13ebffb51f1ee9e361285a371cfeacf19aa6 100644 --- a/mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp +++ b/mlir/lib/Dialect/LLVMIR/IR/LLVMMemorySlot.cpp @@ -113,7 +113,7 @@ bool LLVM::LoadOp::loadsFrom(const MemorySlot &slot) { bool LLVM::LoadOp::storesTo(const MemorySlot &slot) { return false; } Value LLVM::LoadOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, - const DataLayout &dataLayout) { + Value reachingDef, const DataLayout &dataLayout) { llvm_unreachable("getStored should not be called on LoadOp"); } @@ -142,9 +142,10 @@ static bool isSupportedTypeForConversion(Type type) { } /// Checks that `rhs` can be converted to `lhs` by a sequence of casts and -/// truncations. +/// truncations. Checks for narrowing or widening conversion compatibility +/// depending on `narrowingConversion`. static bool areConversionCompatible(const DataLayout &layout, Type targetType, - Type srcType) { + Type srcType, bool narrowingConversion) { if (targetType == srcType) return true; @@ -152,13 +153,18 @@ static bool areConversionCompatible(const DataLayout &layout, Type targetType, !isSupportedTypeForConversion(srcType)) return false; + uint64_t targetSize = layout.getTypeSize(targetType); + uint64_t srcSize = layout.getTypeSize(srcType); + // Pointer casts will only be sane when the bitsize of both pointer types is // the same. if (isa(targetType) && isa(srcType)) - return layout.getTypeSize(targetType) == layout.getTypeSize(srcType); + return targetSize == srcSize; - return layout.getTypeSize(targetType) <= layout.getTypeSize(srcType); + if (narrowingConversion) + return targetSize <= srcSize; + return targetSize >= srcSize; } /// Checks if `dataLayout` describes a little endian layout. @@ -167,22 +173,49 @@ static bool isBigEndian(const DataLayout &dataLayout) { return endiannessStr && endiannessStr == "big"; } -/// The size of a byte in bits. -constexpr const static uint64_t kBitsInByte = 8; +/// Converts a value to an integer type of the same size. +/// Assumes that the type can be converted. +static Value castToSameSizedInt(RewriterBase &rewriter, Location loc, Value val, + const DataLayout &dataLayout) { + Type type = val.getType(); + assert(isSupportedTypeForConversion(type) && + "expected value to have a convertible type"); + + if (isa(type)) + return val; + + uint64_t typeBitSize = dataLayout.getTypeSizeInBits(type); + IntegerType valueSizeInteger = rewriter.getIntegerType(typeBitSize); + + if (isa(type)) + return rewriter.createOrFold(loc, valueSizeInteger, val); + return rewriter.createOrFold(loc, valueSizeInteger, val); +} + +/// Converts a value with an integer type to `targetType`. +static Value castIntValueToSameSizedType(RewriterBase &rewriter, Location loc, + Value val, Type targetType) { + assert(isa(val.getType()) && + "expected value to have an integer type"); + assert(isSupportedTypeForConversion(targetType) && + "expected the target type to be supported for conversions"); + if (val.getType() == targetType) + return val; + if (isa(targetType)) + return rewriter.createOrFold(loc, targetType, val); + return rewriter.createOrFold(loc, targetType, val); +} -/// Constructs operations that convert `inputValue` into a new value of type -/// `targetType`. Assumes that this conversion is possible. -static Value createConversionSequence(RewriterBase &rewriter, Location loc, - Value srcValue, Type targetType, - const DataLayout &dataLayout) { - // Get the types of the source and target values. +/// Constructs operations that convert `srcValue` into a new value of type +/// `targetType`. Assumes the types have the same bitsize. +static Value castSameSizedTypes(RewriterBase &rewriter, Location loc, + Value srcValue, Type targetType, + const DataLayout &dataLayout) { Type srcType = srcValue.getType(); - assert(areConversionCompatible(dataLayout, targetType, srcType) && + assert(areConversionCompatible(dataLayout, targetType, srcType, + /*narrowingConversion=*/true) && "expected that the compatibility was checked before"); - uint64_t srcTypeSize = dataLayout.getTypeSize(srcType); - uint64_t targetTypeSize = dataLayout.getTypeSize(targetType); - // Nothing has to be done if the types are already the same. if (srcType == targetType) return srcValue; @@ -196,48 +229,117 @@ static Value createConversionSequence(RewriterBase &rewriter, Location loc, return rewriter.createOrFold(loc, targetType, srcValue); - IntegerType valueSizeInteger = - rewriter.getIntegerType(srcTypeSize * kBitsInByte); - Value replacement = srcValue; + // For all other castable types, casting through integers is necessary. + Value replacement = castToSameSizedInt(rewriter, loc, srcValue, dataLayout); + return castIntValueToSameSizedType(rewriter, loc, replacement, targetType); +} + +/// Constructs operations that convert `srcValue` into a new value of type +/// `targetType`. Performs bit-level extraction if the source type is larger +/// than the target type. Assumes that this conversion is possible. +static Value createExtractAndCast(RewriterBase &rewriter, Location loc, + Value srcValue, Type targetType, + const DataLayout &dataLayout) { + // Get the types of the source and target values. + Type srcType = srcValue.getType(); + assert(areConversionCompatible(dataLayout, targetType, srcType, + /*narrowingConversion=*/true) && + "expected that the compatibility was checked before"); + + uint64_t srcTypeSize = dataLayout.getTypeSizeInBits(srcType); + uint64_t targetTypeSize = dataLayout.getTypeSizeInBits(targetType); + if (srcTypeSize == targetTypeSize) + return castSameSizedTypes(rewriter, loc, srcValue, targetType, dataLayout); // First, cast the value to a same-sized integer type. - if (isa(srcType)) - replacement = rewriter.createOrFold(loc, valueSizeInteger, - replacement); - else if (replacement.getType() != valueSizeInteger) - replacement = rewriter.createOrFold(loc, valueSizeInteger, - replacement); + Value replacement = castToSameSizedInt(rewriter, loc, srcValue, dataLayout); // Truncate the integer if the size of the target is less than the value. - if (targetTypeSize != srcTypeSize) { - if (isBigEndian(dataLayout)) { - uint64_t shiftAmount = (srcTypeSize - targetTypeSize) * kBitsInByte; - auto shiftConstant = rewriter.create( - loc, rewriter.getIntegerAttr(srcType, shiftAmount)); - replacement = - rewriter.createOrFold(loc, srcValue, shiftConstant); - } - - replacement = rewriter.create( - loc, rewriter.getIntegerType(targetTypeSize * kBitsInByte), - replacement); + if (isBigEndian(dataLayout)) { + uint64_t shiftAmount = srcTypeSize - targetTypeSize; + auto shiftConstant = rewriter.create( + loc, rewriter.getIntegerAttr(srcType, shiftAmount)); + replacement = + rewriter.createOrFold(loc, srcValue, shiftConstant); } + replacement = rewriter.create( + loc, rewriter.getIntegerType(targetTypeSize), replacement); + // Now cast the integer to the actual target type if required. - if (isa(targetType)) - replacement = - rewriter.createOrFold(loc, targetType, replacement); - else if (replacement.getType() != targetType) - replacement = - rewriter.createOrFold(loc, targetType, replacement); + return castIntValueToSameSizedType(rewriter, loc, replacement, targetType); +} + +/// Constructs operations that insert the bits of `srcValue` into the +/// "beginning" of `reachingDef` (beginning is endianness dependent). +/// Assumes that this conversion is possible. +static Value createInsertAndCast(RewriterBase &rewriter, Location loc, + Value srcValue, Value reachingDef, + const DataLayout &dataLayout) { + + assert(areConversionCompatible(dataLayout, reachingDef.getType(), + srcValue.getType(), + /*narrowingConversion=*/false) && + "expected that the compatibility was checked before"); + uint64_t valueTypeSize = dataLayout.getTypeSizeInBits(srcValue.getType()); + uint64_t slotTypeSize = dataLayout.getTypeSizeInBits(reachingDef.getType()); + if (slotTypeSize == valueTypeSize) + return castSameSizedTypes(rewriter, loc, srcValue, reachingDef.getType(), + dataLayout); + + // In the case where the store only overwrites parts of the memory, + // bit fiddling is required to construct the new value. + + // First convert both values to integers of the same size. + Value defAsInt = castToSameSizedInt(rewriter, loc, reachingDef, dataLayout); + Value valueAsInt = castToSameSizedInt(rewriter, loc, srcValue, dataLayout); + // Extend the value to the size of the reaching definition. + valueAsInt = + rewriter.createOrFold(loc, defAsInt.getType(), valueAsInt); + uint64_t sizeDifference = slotTypeSize - valueTypeSize; + if (isBigEndian(dataLayout)) { + // On big endian systems, a store to the base pointer overwrites the most + // significant bits. To accomodate for this, the stored value needs to be + // shifted into the according position. + Value bigEndianShift = rewriter.create( + loc, rewriter.getIntegerAttr(defAsInt.getType(), sizeDifference)); + valueAsInt = + rewriter.createOrFold(loc, valueAsInt, bigEndianShift); + } + + // Construct the mask that is used to erase the bits that are overwritten by + // the store. + APInt maskValue; + if (isBigEndian(dataLayout)) { + // Build a mask that has the most significant bits set to zero. + // Note: This is the same as 2^sizeDifference - 1 + maskValue = APInt::getAllOnes(sizeDifference).zext(slotTypeSize); + } else { + // Build a mask that has the least significant bits set to zero. + // Note: This is the same as -(2^valueTypeSize) + maskValue = APInt::getAllOnes(valueTypeSize).zext(slotTypeSize); + maskValue.flipAllBits(); + } + + // Mask out the affected bits ... + Value mask = rewriter.create( + loc, rewriter.getIntegerAttr(defAsInt.getType(), maskValue)); + Value masked = rewriter.createOrFold(loc, defAsInt, mask); + + // ... and combine the result with the new value. + Value combined = rewriter.createOrFold(loc, masked, valueAsInt); - return replacement; + return castIntValueToSameSizedType(rewriter, loc, combined, + reachingDef.getType()); } Value LLVM::StoreOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, + Value reachingDef, const DataLayout &dataLayout) { - return createConversionSequence(rewriter, getLoc(), getValue(), slot.elemType, - dataLayout); + assert(reachingDef && reachingDef.getType() == slot.elemType && + "expected the reaching definition's type to match the slot's type"); + return createInsertAndCast(rewriter, getLoc(), getValue(), reachingDef, + dataLayout); } bool LLVM::LoadOp::canUsesBeRemoved( @@ -249,11 +351,10 @@ bool LLVM::LoadOp::canUsesBeRemoved( Value blockingUse = (*blockingUses.begin())->get(); // If the blocking use is the slot ptr itself, there will be enough // context to reconstruct the result of the load at removal time, so it can - // be removed (provided it loads the exact stored value and is not - // volatile). + // be removed (provided it is not volatile). return blockingUse == slot.ptr && getAddr() == slot.ptr && areConversionCompatible(dataLayout, getResult().getType(), - slot.elemType) && + slot.elemType, /*narrowingConversion=*/true) && !getVolatile_(); } @@ -263,9 +364,8 @@ DeletionKind LLVM::LoadOp::removeBlockingUses( const DataLayout &dataLayout) { // `canUsesBeRemoved` checked this blocking use must be the loaded slot // pointer. - Value newResult = - createConversionSequence(rewriter, getLoc(), reachingDefinition, - getResult().getType(), dataLayout); + Value newResult = createExtractAndCast(rewriter, getLoc(), reachingDefinition, + getResult().getType(), dataLayout); rewriter.replaceAllUsesWith(getResult(), newResult); return DeletionKind::Delete; } @@ -283,7 +383,8 @@ bool LLVM::StoreOp::canUsesBeRemoved( return blockingUse == slot.ptr && getAddr() == slot.ptr && getValue() != slot.ptr && areConversionCompatible(dataLayout, slot.elemType, - getValue().getType()) && + getValue().getType(), + /*narrowingConversion=*/false) && !getVolatile_(); } @@ -838,6 +939,7 @@ bool LLVM::MemsetOp::storesTo(const MemorySlot &slot) { } Value LLVM::MemsetOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, + Value reachingDef, const DataLayout &dataLayout) { // TODO: Support non-integer types. return TypeSwitch(slot.elemType) @@ -1149,6 +1251,7 @@ bool LLVM::MemcpyOp::storesTo(const MemorySlot &slot) { } Value LLVM::MemcpyOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, + Value reachingDef, const DataLayout &dataLayout) { return memcpyGetStored(*this, slot, rewriter); } @@ -1199,7 +1302,7 @@ bool LLVM::MemcpyInlineOp::storesTo(const MemorySlot &slot) { } Value LLVM::MemcpyInlineOp::getStored(const MemorySlot &slot, - RewriterBase &rewriter, + RewriterBase &rewriter, Value reachingDef, const DataLayout &dataLayout) { return memcpyGetStored(*this, slot, rewriter); } @@ -1252,6 +1355,7 @@ bool LLVM::MemmoveOp::storesTo(const MemorySlot &slot) { } Value LLVM::MemmoveOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, + Value reachingDef, const DataLayout &dataLayout) { return memcpyGetStored(*this, slot, rewriter); } diff --git a/mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp b/mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp index ebbf20f1b76b67a56e2202bb2f532e1fbb0bdfc4..958c5f0c8dbc75b09887c044eb3822105726cd71 100644 --- a/mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp +++ b/mlir/lib/Dialect/MemRef/IR/MemRefMemorySlot.cpp @@ -161,6 +161,7 @@ bool memref::LoadOp::loadsFrom(const MemorySlot &slot) { bool memref::LoadOp::storesTo(const MemorySlot &slot) { return false; } Value memref::LoadOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, + Value reachingDef, const DataLayout &dataLayout) { llvm_unreachable("getStored should not be called on LoadOp"); } @@ -242,6 +243,7 @@ bool memref::StoreOp::storesTo(const MemorySlot &slot) { } Value memref::StoreOp::getStored(const MemorySlot &slot, RewriterBase &rewriter, + Value reachingDef, const DataLayout &dataLayout) { return getValue(); } diff --git a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp index a8f84c519da860019bc71540defdb235bbeb1762..0f3dd15b625da760f9cebb3c59b2e8ee2d8c235a 100644 --- a/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp +++ b/mlir/lib/Dialect/OpenMP/IR/OpenMPDialect.cpp @@ -1557,86 +1557,72 @@ LogicalResult SingleOp::verify() { // WsloopOp //===----------------------------------------------------------------------===// -/// loop-control ::= `(` ssa-id-list `)` `:` type `=` loop-bounds -/// loop-bounds := `(` ssa-id-list `)` to `(` ssa-id-list `)` inclusive? steps -/// steps := `step` `(`ssa-id-list`)` ParseResult parseWsloop(OpAsmParser &parser, Region ®ion, - SmallVectorImpl &lowerBound, - SmallVectorImpl &upperBound, - SmallVectorImpl &steps, - SmallVectorImpl &loopVarTypes, SmallVectorImpl &reductionOperands, - SmallVectorImpl &reductionTypes, ArrayAttr &reductionSymbols, - UnitAttr &inclusive) { - + SmallVectorImpl &reductionTypes, + ArrayAttr &reductionSymbols) { // Parse an optional reduction clause llvm::SmallVector privates; - bool hasReduction = succeeded(parser.parseOptionalKeyword("reduction")) && - succeeded(parseClauseWithRegionArgs( - parser, region, reductionOperands, reductionTypes, - reductionSymbols, privates)); - - if (parser.parseKeyword("for")) - return failure(); - - // Parse an opening `(` followed by induction variables followed by `)` - SmallVector ivs; - Type loopVarType; - if (parser.parseArgumentList(ivs, OpAsmParser::Delimiter::Paren) || - parser.parseColonType(loopVarType) || - // Parse loop bounds. - parser.parseEqual() || - parser.parseOperandList(lowerBound, ivs.size(), - OpAsmParser::Delimiter::Paren) || - parser.parseKeyword("to") || - parser.parseOperandList(upperBound, ivs.size(), - OpAsmParser::Delimiter::Paren)) - return failure(); - - if (succeeded(parser.parseOptionalKeyword("inclusive"))) - inclusive = UnitAttr::get(parser.getBuilder().getContext()); - - // Parse step values. - if (parser.parseKeyword("step") || - parser.parseOperandList(steps, ivs.size(), OpAsmParser::Delimiter::Paren)) - return failure(); - - // Now parse the body. - loopVarTypes = SmallVector(ivs.size(), loopVarType); - for (auto &iv : ivs) - iv.type = loopVarType; - - SmallVector regionArgs{ivs}; - if (hasReduction) - llvm::copy(privates, std::back_inserter(regionArgs)); - - return parser.parseRegion(region, regionArgs); + if (succeeded(parser.parseOptionalKeyword("reduction"))) { + if (failed(parseClauseWithRegionArgs(parser, region, reductionOperands, + reductionTypes, reductionSymbols, + privates))) + return failure(); + } + return parser.parseRegion(region, privates); } void printWsloop(OpAsmPrinter &p, Operation *op, Region ®ion, - ValueRange lowerBound, ValueRange upperBound, ValueRange steps, - TypeRange loopVarTypes, ValueRange reductionOperands, - TypeRange reductionTypes, ArrayAttr reductionSymbols, - UnitAttr inclusive) { + ValueRange reductionOperands, TypeRange reductionTypes, + ArrayAttr reductionSymbols) { if (reductionSymbols) { - auto reductionArgs = - region.front().getArguments().drop_front(loopVarTypes.size()); + auto reductionArgs = region.front().getArguments(); printClauseWithRegionArgs(p, op, reductionArgs, "reduction", reductionOperands, reductionTypes, reductionSymbols); } - - p << " for "; - auto args = region.front().getArguments().drop_back(reductionOperands.size()); - p << " (" << args << ") : " << args[0].getType() << " = (" << lowerBound - << ") to (" << upperBound << ") "; - if (inclusive) - p << "inclusive "; - p << "step (" << steps << ") "; p.printRegion(region, /*printEntryBlockArgs=*/false); } +void WsloopOp::build(OpBuilder &builder, OperationState &state, + ArrayRef attributes) { + build(builder, state, /*linear_vars=*/ValueRange(), + /*linear_step_vars=*/ValueRange(), /*reduction_vars=*/ValueRange(), + /*reductions=*/nullptr, /*schedule_val=*/nullptr, + /*schedule_chunk_var=*/nullptr, /*schedule_modifier=*/nullptr, + /*simd_modifier=*/false, /*nowait=*/false, /*byref=*/false, + /*ordered_val=*/nullptr, /*order_val=*/nullptr); + state.addAttributes(attributes); +} + +void WsloopOp::build(OpBuilder &builder, OperationState &state, + const WsloopClauseOps &clauses) { + MLIRContext *ctx = builder.getContext(); + // TODO: Store clauses in op: allocateVars, allocatorVars, privateVars, + // privatizers. + WsloopOp::build( + builder, state, clauses.linearVars, clauses.linearStepVars, + clauses.reductionVars, makeArrayAttr(ctx, clauses.reductionDeclSymbols), + clauses.scheduleValAttr, clauses.scheduleChunkVar, + clauses.scheduleModAttr, clauses.scheduleSimdAttr, clauses.nowaitAttr, + clauses.reductionByRefAttr, clauses.orderedAttr, clauses.orderAttr); +} + +LogicalResult WsloopOp::verify() { + if (!isWrapper()) + return emitOpError() << "must be a loop wrapper"; + + if (LoopWrapperInterface nested = getNestedWrapper()) { + // Check for the allowed leaf constructs that may appear in a composite + // construct directly after DO/FOR. + if (!isa(nested)) + return emitError() << "only supported nested wrapper is 'omp.simd'"; + } + + return verifyReductionVarList(*this, getReductions(), getReductionVars()); +} + //===----------------------------------------------------------------------===// // Simd construct [2.9.3.1] //===----------------------------------------------------------------------===// @@ -2020,42 +2006,6 @@ void LoopNestOp::gatherWrappers( } } -//===----------------------------------------------------------------------===// -// WsloopOp -//===----------------------------------------------------------------------===// - -void WsloopOp::build(OpBuilder &builder, OperationState &state, - ValueRange lowerBound, ValueRange upperBound, - ValueRange step, ArrayRef attributes) { - build(builder, state, lowerBound, upperBound, step, - /*linear_vars=*/ValueRange(), - /*linear_step_vars=*/ValueRange(), /*reduction_vars=*/ValueRange(), - /*reductions=*/nullptr, /*schedule_val=*/nullptr, - /*schedule_chunk_var=*/nullptr, /*schedule_modifier=*/nullptr, - /*simd_modifier=*/false, /*nowait=*/false, /*byref=*/false, - /*ordered_val=*/nullptr, - /*order_val=*/nullptr, /*inclusive=*/false); - state.addAttributes(attributes); -} - -void WsloopOp::build(OpBuilder &builder, OperationState &state, - const WsloopClauseOps &clauses) { - MLIRContext *ctx = builder.getContext(); - // TODO Store clauses in op: allocateVars, allocatorVars, privateVars, - // privatizers. - WsloopOp::build( - builder, state, clauses.loopLBVar, clauses.loopUBVar, clauses.loopStepVar, - clauses.linearVars, clauses.linearStepVars, clauses.reductionVars, - makeArrayAttr(ctx, clauses.reductionDeclSymbols), clauses.scheduleValAttr, - clauses.scheduleChunkVar, clauses.scheduleModAttr, - clauses.scheduleSimdAttr, clauses.nowaitAttr, clauses.reductionByRefAttr, - clauses.orderedAttr, clauses.orderAttr, clauses.loopInclusiveAttr); -} - -LogicalResult WsloopOp::verify() { - return verifyReductionVarList(*this, getReductions(), getReductionVars()); -} - //===----------------------------------------------------------------------===// // Critical construct (2.17.1) //===----------------------------------------------------------------------===// @@ -2087,6 +2037,39 @@ LogicalResult CriticalOp::verifySymbolUses(SymbolTableCollection &symbolTable) { // Ordered construct //===----------------------------------------------------------------------===// +static LogicalResult verifyOrderedParent(Operation &op) { + bool hasRegion = op.getNumRegions() > 0; + auto loopOp = op.getParentOfType(); + if (!loopOp) { + if (hasRegion) + return success(); + + // TODO: Consider if this needs to be the case only for the standalone + // variant of the ordered construct. + return op.emitOpError() << "must be nested inside of a loop"; + } + + Operation *wrapper = loopOp->getParentOp(); + if (auto wsloopOp = dyn_cast(wrapper)) { + IntegerAttr orderedAttr = wsloopOp.getOrderedValAttr(); + if (!orderedAttr) + return op.emitOpError() << "the enclosing worksharing-loop region must " + "have an ordered clause"; + + if (hasRegion && orderedAttr.getInt() != 0) + return op.emitOpError() << "the enclosing loop's ordered clause must not " + "have a parameter present"; + + if (!hasRegion && orderedAttr.getInt() == 0) + return op.emitOpError() << "the enclosing loop's ordered clause must " + "have a parameter present"; + } else if (!isa(wrapper)) { + return op.emitOpError() << "must be nested inside of a worksharing, simd " + "or worksharing simd loop"; + } + return success(); +} + void OrderedOp::build(OpBuilder &builder, OperationState &state, const OrderedOpClauseOps &clauses) { OrderedOp::build(builder, state, clauses.doacrossDependTypeAttr, @@ -2094,14 +2077,11 @@ void OrderedOp::build(OpBuilder &builder, OperationState &state, } LogicalResult OrderedOp::verify() { - auto container = (*this)->getParentOfType(); - if (!container || !container.getOrderedValAttr() || - container.getOrderedValAttr().getInt() == 0) - return emitOpError() << "ordered depend directive must be closely " - << "nested inside a worksharing-loop with ordered " - << "clause with parameter present"; - - if (container.getOrderedValAttr().getInt() != (int64_t)*getNumLoopsVal()) + if (failed(verifyOrderedParent(**this))) + return failure(); + + auto wrapper = (*this)->getParentOfType(); + if (!wrapper || *wrapper.getOrderedVal() != *getNumLoopsVal()) return emitOpError() << "number of variables in depend clause does not " << "match number of iteration variables in the " << "doacross loop"; @@ -2119,15 +2099,7 @@ LogicalResult OrderedRegionOp::verify() { if (getSimd()) return failure(); - if (auto container = (*this)->getParentOfType()) { - if (!container.getOrderedValAttr() || - container.getOrderedValAttr().getInt() != 0) - return emitOpError() << "ordered region must be closely nested inside " - << "a worksharing-loop region with an ordered " - << "clause without parameter present"; - } - - return success(); + return verifyOrderedParent(**this); } //===----------------------------------------------------------------------===// @@ -2272,15 +2244,19 @@ LogicalResult CancelOp::verify() { << "inside a parallel region"; } if (cct == ClauseCancellationConstructType::Loop) { - if (!isa(parentOp)) { - return emitOpError() << "cancel loop must appear " - << "inside a worksharing-loop region"; + auto loopOp = dyn_cast(parentOp); + auto wsloopOp = llvm::dyn_cast_if_present( + loopOp ? loopOp->getParentOp() : nullptr); + + if (!wsloopOp) { + return emitOpError() + << "cancel loop must appear inside a worksharing-loop region"; } - if (cast(parentOp).getNowaitAttr()) { + if (wsloopOp.getNowaitAttr()) { return emitError() << "A worksharing construct that is canceled " << "must not have a nowait clause"; } - if (cast(parentOp).getOrderedValAttr()) { + if (wsloopOp.getOrderedValAttr()) { return emitError() << "A worksharing construct that is canceled " << "must not have an ordered clause"; } @@ -2318,7 +2294,7 @@ LogicalResult CancellationPointOp::verify() { << "inside a parallel region"; } if ((cct == ClauseCancellationConstructType::Loop) && - !isa(parentOp)) { + (!isa(parentOp) || !isa(parentOp->getParentOp()))) { return emitOpError() << "cancellation point loop must appear " << "inside a worksharing-loop region"; } diff --git a/mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp b/mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp index 7e4faf8b73afbb9176b33ec3080ced540e95715b..69f83d8bd70da16aa1aeafc60dc35f5ca322b045 100644 --- a/mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp +++ b/mlir/lib/Dialect/SCF/TransformOps/SCFTransformOps.cpp @@ -69,16 +69,12 @@ transform::ForallToForOp::apply(transform::TransformRewriter &rewriter, return diag; } - rewriter.setInsertionPoint(target); - if (!target.getOutputs().empty()) { return emitSilenceableError() << "unsupported shared outputs (didn't bufferize?)"; } SmallVector lbs = target.getMixedLowerBound(); - SmallVector ubs = target.getMixedUpperBound(); - SmallVector steps = target.getMixedStep(); if (getNumResults() != lbs.size()) { DiagnosedSilenceableFailure diag = @@ -89,28 +85,15 @@ transform::ForallToForOp::apply(transform::TransformRewriter &rewriter, return diag; } - auto loc = target.getLoc(); - SmallVector ivs; - for (auto &&[lb, ub, step] : llvm::zip(lbs, ubs, steps)) { - Value lbValue = getValueOrCreateConstantIndexOp(rewriter, loc, lb); - Value ubValue = getValueOrCreateConstantIndexOp(rewriter, loc, ub); - Value stepValue = getValueOrCreateConstantIndexOp(rewriter, loc, step); - auto loop = rewriter.create( - loc, lbValue, ubValue, stepValue, ValueRange(), - [](OpBuilder &, Location, Value, ValueRange) {}); - ivs.push_back(loop.getInductionVar()); - rewriter.setInsertionPointToStart(loop.getBody()); - rewriter.create(loc); - rewriter.setInsertionPointToStart(loop.getBody()); + SmallVector opResults; + if (failed(scf::forallToForLoop(rewriter, target, &opResults))) { + DiagnosedSilenceableFailure diag = emitSilenceableError() + << "failed to convert forall into for"; + return diag; } - rewriter.eraseOp(target.getBody()->getTerminator()); - rewriter.inlineBlockBefore(target.getBody(), &*rewriter.getInsertionPoint(), - ivs); - rewriter.eraseOp(target); - - for (auto &&[i, iv] : llvm::enumerate(ivs)) { - results.set(cast(getTransformed()[i]), - {iv.getParentBlock()->getParentOp()}); + + for (auto &&[i, res] : llvm::enumerate(opResults)) { + results.set(cast(getTransformed()[i]), {res}); } return DiagnosedSilenceableFailure::success(); } diff --git a/mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt b/mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt index a2925aef17ca78a3901482b3c419f33c76416884..e7671c9cc28f8bfe31e355d32cd35da8b251a10c 100644 --- a/mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt +++ b/mlir/lib/Dialect/SCF/Transforms/CMakeLists.txt @@ -2,6 +2,7 @@ add_mlir_dialect_library(MLIRSCFTransforms BufferDeallocationOpInterfaceImpl.cpp BufferizableOpInterfaceImpl.cpp Bufferize.cpp + ForallToFor.cpp ForToWhile.cpp LoopCanonicalization.cpp LoopPipelining.cpp diff --git a/mlir/lib/Dialect/SCF/Transforms/ForallToFor.cpp b/mlir/lib/Dialect/SCF/Transforms/ForallToFor.cpp new file mode 100644 index 0000000000000000000000000000000000000000..198cb2e6cc69ef6e0499a7e4c31a56ec5514e3bd --- /dev/null +++ b/mlir/lib/Dialect/SCF/Transforms/ForallToFor.cpp @@ -0,0 +1,79 @@ +//===- ForallToFor.cpp - scf.forall to scf.for loop conversion ------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Transforms SCF.ForallOp's into SCF.ForOp's. +// +//===----------------------------------------------------------------------===// + +#include "mlir/Dialect/SCF/Transforms/Passes.h" + +#include "mlir/Dialect/SCF/IR/SCF.h" +#include "mlir/Dialect/SCF/Transforms/Transforms.h" +#include "mlir/IR/PatternMatch.h" + +namespace mlir { +#define GEN_PASS_DEF_SCFFORALLTOFORLOOP +#include "mlir/Dialect/SCF/Transforms/Passes.h.inc" +} // namespace mlir + +using namespace llvm; +using namespace mlir; +using scf::ForallOp; +using scf::ForOp; +using scf::LoopNest; + +LogicalResult +mlir::scf::forallToForLoop(RewriterBase &rewriter, scf::ForallOp forallOp, + SmallVectorImpl *results) { + OpBuilder::InsertionGuard guard(rewriter); + rewriter.setInsertionPoint(forallOp); + + Location loc = forallOp.getLoc(); + SmallVector lbs = getValueOrCreateConstantIndexOp( + rewriter, loc, forallOp.getMixedLowerBound()); + SmallVector ubs = getValueOrCreateConstantIndexOp( + rewriter, loc, forallOp.getMixedUpperBound()); + SmallVector steps = + getValueOrCreateConstantIndexOp(rewriter, loc, forallOp.getMixedStep()); + LoopNest loopNest = scf::buildLoopNest(rewriter, loc, lbs, ubs, steps); + + SmallVector ivs = llvm::map_to_vector( + loopNest.loops, [](scf::ForOp loop) { return loop.getInductionVar(); }); + + Block *innermostBlock = loopNest.loops.back().getBody(); + rewriter.eraseOp(forallOp.getBody()->getTerminator()); + rewriter.inlineBlockBefore(forallOp.getBody(), innermostBlock, + innermostBlock->getTerminator()->getIterator(), + ivs); + rewriter.eraseOp(forallOp); + + if (results) { + llvm::move(loopNest.loops, std::back_inserter(*results)); + } + + return success(); +} + +namespace { +struct ForallToForLoop : public impl::SCFForallToForLoopBase { + void runOnOperation() override { + Operation *parentOp = getOperation(); + IRRewriter rewriter(parentOp->getContext()); + + parentOp->walk([&](scf::ForallOp forallOp) { + if (failed(scf::forallToForLoop(rewriter, forallOp))) { + return signalPassFailure(); + } + }); + } +}; +} // namespace + +std::unique_ptr mlir::createForallToForLoopPass() { + return std::make_unique(); +} diff --git a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp index b1d44559fa5abad9e128381789758549a3c7caf4..028a69da10c1e1c16946c32a6efb9b967edae437 100644 --- a/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp +++ b/mlir/lib/Dialect/SparseTensor/IR/SparseTensorDialect.cpp @@ -326,9 +326,9 @@ SparseTensorDimSliceAttr::verify(function_ref emitError, SparseTensorEncodingAttr SparseTensorEncodingAttr::withDimToLvl(AffineMap dimToLvl) const { assert(getImpl() && "Uninitialized SparseTensorEncodingAttr"); - return SparseTensorEncodingAttr::get(getContext(), getLvlTypes(), dimToLvl, - AffineMap(), getPosWidth(), - getCrdWidth()); + return SparseTensorEncodingAttr::get( + getContext(), getLvlTypes(), dimToLvl, AffineMap(), getPosWidth(), + getCrdWidth(), getExplicitVal(), getImplicitVal()); } SparseTensorEncodingAttr @@ -344,20 +344,44 @@ SparseTensorEncodingAttr SparseTensorEncodingAttr::withBitWidths(unsigned posWidth, unsigned crdWidth) const { assert(getImpl() && "Uninitialized SparseTensorEncodingAttr"); - return SparseTensorEncodingAttr::get(getContext(), getLvlTypes(), - getDimToLvl(), getLvlToDim(), posWidth, - crdWidth); + return SparseTensorEncodingAttr::get( + getContext(), getLvlTypes(), getDimToLvl(), getLvlToDim(), posWidth, + crdWidth, getExplicitVal(), getImplicitVal()); } SparseTensorEncodingAttr SparseTensorEncodingAttr::withoutBitWidths() const { return withBitWidths(0, 0); } +SparseTensorEncodingAttr +SparseTensorEncodingAttr::withExplicitVal(Attribute explicitVal) const { + assert(getImpl() && "Uninitialized SparseTensorEncodingAttr"); + return SparseTensorEncodingAttr::get( + getContext(), getLvlTypes(), getDimToLvl(), getLvlToDim(), getPosWidth(), + getCrdWidth(), explicitVal, getImplicitVal()); +} + +SparseTensorEncodingAttr SparseTensorEncodingAttr::withoutExplicitVal() const { + return withExplicitVal(Attribute()); +} + +SparseTensorEncodingAttr +SparseTensorEncodingAttr::withImplicitVal(Attribute implicitVal) const { + assert(getImpl() && "Uninitialized SparseTensorEncodingAttr"); + return SparseTensorEncodingAttr::get( + getContext(), getLvlTypes(), getDimToLvl(), getLvlToDim(), getPosWidth(), + getCrdWidth(), getExplicitVal(), implicitVal); +} + +SparseTensorEncodingAttr SparseTensorEncodingAttr::withoutImplicitVal() const { + return withImplicitVal(Attribute()); +} + SparseTensorEncodingAttr SparseTensorEncodingAttr::withDimSlices( ArrayRef dimSlices) const { - return SparseTensorEncodingAttr::get(getContext(), getLvlTypes(), - getDimToLvl(), getLvlToDim(), - getPosWidth(), getCrdWidth(), dimSlices); + return SparseTensorEncodingAttr::get( + getContext(), getLvlTypes(), getDimToLvl(), getLvlToDim(), getPosWidth(), + getCrdWidth(), getExplicitVal(), getImplicitVal(), dimSlices); } SparseTensorEncodingAttr SparseTensorEncodingAttr::withoutDimSlices() const { @@ -553,8 +577,11 @@ Attribute SparseTensorEncodingAttr::parse(AsmParser &parser, Type type) { AffineMap lvlToDim = {}; unsigned posWidth = 0; unsigned crdWidth = 0; + Attribute explicitVal; + Attribute implicitVal; StringRef attrName; - SmallVector keys = {"map", "posWidth", "crdWidth"}; + SmallVector keys = {"map", "posWidth", "crdWidth", + "explicitVal", "implicitVal"}; while (succeeded(parser.parseOptionalKeyword(&attrName))) { // Detect admissible keyword. auto *it = find(keys, attrName); @@ -628,6 +655,36 @@ Attribute SparseTensorEncodingAttr::parse(AsmParser &parser, Type type) { crdWidth = intAttr.getInt(); break; } + case 3: { // explicitVal + Attribute attr; + if (failed(parser.parseAttribute(attr))) + return {}; + if (auto result = llvm::dyn_cast(attr)) { + explicitVal = result; + } else if (auto result = llvm::dyn_cast(attr)) { + explicitVal = result; + } else { + parser.emitError(parser.getNameLoc(), + "expected a numeric value for explicitVal"); + return {}; + } + break; + } + case 4: { // implicitVal + Attribute attr; + if (failed(parser.parseAttribute(attr))) + return {}; + if (auto result = llvm::dyn_cast(attr)) { + implicitVal = result; + } else if (auto result = llvm::dyn_cast(attr)) { + implicitVal = result; + } else { + parser.emitError(parser.getNameLoc(), + "expected a numeric value for implicitVal"); + return {}; + } + break; + } } // switch // Only last item can omit the comma. if (parser.parseOptionalComma().failed()) @@ -646,7 +703,7 @@ Attribute SparseTensorEncodingAttr::parse(AsmParser &parser, Type type) { } return parser.getChecked( parser.getContext(), lvlTypes, dimToLvl, lvlToDim, posWidth, crdWidth, - dimSlices); + explicitVal, implicitVal, dimSlices); } void SparseTensorEncodingAttr::print(AsmPrinter &printer) const { @@ -666,6 +723,11 @@ void SparseTensorEncodingAttr::print(AsmPrinter &printer) const { printer << ", posWidth = " << getPosWidth(); if (getCrdWidth()) printer << ", crdWidth = " << getCrdWidth(); + if (getExplicitVal()) { + printer << ", explicitVal = " << getExplicitVal(); + } + if (getImplicitVal()) + printer << ", implicitVal = " << getImplicitVal(); printer << " }>"; } @@ -715,7 +777,8 @@ void SparseTensorEncodingAttr::printLevels(AffineMap &map, AsmPrinter &printer, LogicalResult SparseTensorEncodingAttr::verify( function_ref emitError, ArrayRef lvlTypes, AffineMap dimToLvl, AffineMap lvlToDim, unsigned posWidth, - unsigned crdWidth, ArrayRef dimSlices) { + unsigned crdWidth, Attribute explicitVal, Attribute implicitVal, + ArrayRef dimSlices) { if (!acceptBitWidth(posWidth)) return emitError() << "unexpected position bitwidth: " << posWidth; if (!acceptBitWidth(crdWidth)) @@ -831,7 +894,8 @@ LogicalResult SparseTensorEncodingAttr::verifyEncoding( // Check structural integrity. In particular, this ensures that the // level-rank is coherent across all the fields. if (failed(verify(emitError, getLvlTypes(), getDimToLvl(), getLvlToDim(), - getPosWidth(), getCrdWidth(), getDimSlices()))) + getPosWidth(), getCrdWidth(), getExplicitVal(), + getImplicitVal(), getDimSlices()))) return failure(); // Check integrity with tensor type specifics. In particular, we // need only check that the dimension-rank of the tensor agrees with @@ -921,9 +985,9 @@ mlir::sparse_tensor::SparseTensorType::getCOOType(bool ordered) const { // Ends by a unique singleton level. lvlTypes.push_back(*buildLevelType(LevelFormat::Singleton, ordered, true)); } - auto enc = SparseTensorEncodingAttr::get(getContext(), lvlTypes, - getDimToLvl(), getLvlToDim(), - getPosWidth(), getCrdWidth()); + auto enc = SparseTensorEncodingAttr::get( + getContext(), lvlTypes, getDimToLvl(), getLvlToDim(), getPosWidth(), + getCrdWidth(), getExplicitVal(), getImplicitVal()); return RankedTensorType::get(getDimShape(), getElementType(), enc); } @@ -1115,7 +1179,10 @@ getNormalizedEncodingForSpecifier(SparseTensorEncodingAttr enc) { // `getPosWidth` and `getCrdWidth`. It allows us to reuse the same SSA // value for different bitwidth, it also avoids casting between index and // integer (returned by DimOp) - 0, 0, enc.getDimSlices()); + 0, 0, + Attribute(), // explicitVal (irrelevant to storage specifier) + Attribute(), // implicitVal (irrelevant to storage specifier) + enc.getDimSlices()); } StorageSpecifierType diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp index 02375f54d7152fe534817e2f2bad4a6fb52650ea..5a39dfc6207707fb17a6d4ba4ada7d60dc556bd6 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp @@ -209,6 +209,86 @@ static void concatSizesFromInputs(OpBuilder &builder, namespace { +/// TODO: move it to tensor dialect instead. +/// +/// Fold `tensor.concat` and `tensor.extract_slice` +/// +/// %concat = tensor.concat dim(2) %t0, %t1 +/// : (tensor<1x64x1xf32>, tensor<1x64x1xf32>) -> tensor<1x64x2xf32> +/// %extracted0 = tensor.extract_slice %concat[0, 0, 0][1, 64, 1][1, 1, 1] +/// : tensor<1x64x2xf32> to tensor<1x64x1xf32> +/// %extracted1 = tensor.extract_slice %concat[0, 0, 1][1, 64, 1][1, 1, 1] +/// : tensor<1x64x2xf32> to tensor<1x64x1xf32> +/// +/// Becomes +/// +/// %extract0, %extract1 = %t0, %t1 +struct FuseExtractSliceWithConcat + : public OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(tensor::ExtractSliceOp extractOp, + PatternRewriter &rewriter) const override { + auto concatOp = extractOp.getSource().getDefiningOp(); + if (!concatOp) + return failure(); + + Location loc = extractOp.getLoc(); + int64_t dim = concatOp.getDim(); + int64_t rank = extractOp.getResultType().getRank(); + + SmallVector srcStrides(rank, rewriter.getIndexAttr(1)); + SmallVector srcOffsets(rank, rewriter.getIndexAttr(0)); + + // Compute the partial sums for the slice offsets. + AffineExpr sum = rewriter.getAffineDimExpr(0); + SmallVector partialSums = {sum}; + SmallVector offsetStrides = {rewriter.getIndexAttr(0)}; + for (auto [idx, input] : + llvm::enumerate(concatOp.getInputs().drop_back())) { + sum = sum + rewriter.getAffineDimExpr(idx + 1); + partialSums.push_back(sum); + offsetStrides.push_back( + rewriter.createOrFold(loc, input, dim)); + } + auto partialSumMap = AffineMap::get(concatOp.getInputs().size(), 0, + partialSums, rewriter.getContext()); + SmallVector dimOffsets = + affine::makeComposedFoldedMultiResultAffineApply( + rewriter, loc, partialSumMap, offsetStrides); + + auto allEqual = [](ArrayRef lhs, ArrayRef rhs) { + for (auto [l, r] : llvm::zip(lhs, rhs)) { + std::optional staticVal = getConstantIntValue(l); + if (!staticVal.has_value() || staticVal != getConstantIntValue(r)) + return false; + } + return lhs.size() == rhs.size(); + }; + + for (auto [i, input, offset] : + llvm::enumerate(concatOp.getInputs(), dimOffsets)) { + SmallVector srcSizes = + tensor::getMixedSizes(rewriter, loc, input); + srcOffsets[dim] = offset; + + SmallVector dstSizes = extractOp.getMixedSizes(); + SmallVector dstOffsets = extractOp.getMixedOffsets(); + SmallVector dstStrides = extractOp.getMixedStrides(); + + if (allEqual(srcSizes, dstSizes) && allEqual(srcOffsets, dstOffsets) && + allEqual(srcStrides, dstStrides)) { + Value operand = concatOp.getOperand(i); + if (operand.getType() == extractOp.getResultType()) + rewriter.replaceOp(extractOp, operand); + break; + } + } + + return success(); + } +}; + /// Rewriting rule that converts direct yield of zero with initial allocation. struct FoldInvariantYield : public OpRewritePattern { public: @@ -1426,9 +1506,9 @@ struct OutRewriter : public OpRewritePattern { //===---------------------------------------------------------------------===// void mlir::populatePreSparsificationRewriting(RewritePatternSet &patterns) { - patterns.add( - patterns.getContext()); + patterns.add(patterns.getContext()); } void mlir::populateLowerSparseOpsToForeachPatterns(RewritePatternSet &patterns, diff --git a/mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt b/mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt index 617c89a84ee077104a799b00070fe51921f387bc..a0ce7f9706cef305cdd6e88174ea72582696ba4e 100644 --- a/mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt +++ b/mlir/lib/Dialect/XeGPU/IR/CMakeLists.txt @@ -11,6 +11,7 @@ add_mlir_dialect_library(MLIRXeGPUDialect MLIRXeGPUEnumsIncGen LINK_LIBS PUBLIC + MLIRArithDialect MLIRDialectUtils MLIRIR MLIRViewLikeInterface diff --git a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp index 23c5749c2309deb673e6794dcc1a3965e07ba492..22959224d56c2f30fa7623d692f2d202b17afee1 100644 --- a/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp +++ b/mlir/lib/Dialect/XeGPU/IR/XeGPUOps.cpp @@ -406,6 +406,28 @@ LogicalResult StoreScatterOp::verify() { return success(); } +//===----------------------------------------------------------------------===// +// XeGPU_DpasOp +//===----------------------------------------------------------------------===// +LogicalResult DpasOp::verify() { + int64_t lhsRank = getLhsType().getRank(); + int64_t rhsRank = getRhsType().getRank(); + + if (lhsRank != rhsRank || lhsRank != 3) + return emitOpError( + "lhs and rhs rank does not match for dpas op, or their rank is not 3."); + + if (getAcc() && getAccType() != getResultType()) + return emitOpError("Accumulator and Result for dpas op should have the " + "same type (both shape and element type)."); + + auto lhsShape = getLhsType().getShape(); + auto rhsShape = getRhsType().getShape(); + if (lhsShape[1] != rhsShape[0] || lhsShape[2] != rhsShape[2]) + return emitOpError("K-dimension or vnni-factor mismatch."); + + return success(); +} } // namespace xegpu } // namespace mlir diff --git a/mlir/lib/TableGen/CodeGenHelpers.cpp b/mlir/lib/TableGen/CodeGenHelpers.cpp index d906de6b56afc0e5520857f28640160c87705324..59865146e20bc470896e6358fd162ae34d7d9c13 100644 --- a/mlir/lib/TableGen/CodeGenHelpers.cpp +++ b/mlir/lib/TableGen/CodeGenHelpers.cpp @@ -24,7 +24,8 @@ using namespace mlir::tblgen; /// Generate a unique label based on the current file name to prevent name /// collisions if multiple generated files are included at once. -static std::string getUniqueOutputLabel(const llvm::RecordKeeper &records) { +static std::string getUniqueOutputLabel(const llvm::RecordKeeper &records, + StringRef tag) { // Use the input file name when generating a unique name. std::string inputFilename = records.getInputFilename(); @@ -33,7 +34,7 @@ static std::string getUniqueOutputLabel(const llvm::RecordKeeper &records) { nameRef.consume_back(".td"); // Sanitize any invalid characters. - std::string uniqueName; + std::string uniqueName(tag); for (char c : nameRef) { if (llvm::isAlnum(c) || c == '_') uniqueName.push_back(c); @@ -44,15 +45,11 @@ static std::string getUniqueOutputLabel(const llvm::RecordKeeper &records) { } StaticVerifierFunctionEmitter::StaticVerifierFunctionEmitter( - raw_ostream &os, const llvm::RecordKeeper &records) - : os(os), uniqueOutputLabel(getUniqueOutputLabel(records)) {} + raw_ostream &os, const llvm::RecordKeeper &records, StringRef tag) + : os(os), uniqueOutputLabel(getUniqueOutputLabel(records, tag)) {} void StaticVerifierFunctionEmitter::emitOpConstraints( - ArrayRef opDefs, bool emitDecl) { - collectOpConstraints(opDefs); - if (emitDecl) - return; - + ArrayRef opDefs) { NamespaceEmitter namespaceEmitter(os, Operator(*opDefs[0]).getCppNamespace()); emitTypeConstraints(); emitAttrConstraints(); diff --git a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp index ebcdbc02aadd079e8fab73591b72e64b2a9000fd..9f87f89d8c636b24915931a7b5ce2948f44f9a19 100644 --- a/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp +++ b/mlir/lib/Target/LLVMIR/Dialect/OpenMP/OpenMPToLLVMIRTranslation.cpp @@ -916,35 +916,37 @@ static LogicalResult inlineReductionCleanup( static LogicalResult convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, LLVM::ModuleTranslation &moduleTranslation) { - auto loop = cast(opInst); - const bool isByRef = loop.getByref(); + auto wsloopOp = cast(opInst); + auto loopOp = cast(wsloopOp.getWrappedLoop()); + const bool isByRef = wsloopOp.getByref(); + // TODO: this should be in the op verifier instead. - if (loop.getLowerBound().empty()) + if (loopOp.getLowerBound().empty()) return failure(); // Static is the default. auto schedule = - loop.getScheduleVal().value_or(omp::ClauseScheduleKind::Static); + wsloopOp.getScheduleVal().value_or(omp::ClauseScheduleKind::Static); // Find the loop configuration. - llvm::Value *step = moduleTranslation.lookupValue(loop.getStep()[0]); + llvm::Value *step = moduleTranslation.lookupValue(loopOp.getStep()[0]); llvm::Type *ivType = step->getType(); llvm::Value *chunk = nullptr; - if (loop.getScheduleChunkVar()) { + if (wsloopOp.getScheduleChunkVar()) { llvm::Value *chunkVar = - moduleTranslation.lookupValue(loop.getScheduleChunkVar()); + moduleTranslation.lookupValue(wsloopOp.getScheduleChunkVar()); chunk = builder.CreateSExtOrTrunc(chunkVar, ivType); } SmallVector reductionDecls; - collectReductionDecls(loop, reductionDecls); + collectReductionDecls(wsloopOp, reductionDecls); llvm::OpenMPIRBuilder::InsertPointTy allocaIP = findAllocaInsertPoint(builder, moduleTranslation); SmallVector privateReductionVariables; DenseMap reductionVariableMap; if (!isByRef) { - allocByValReductionVars(loop, builder, moduleTranslation, allocaIP, + allocByValReductionVars(wsloopOp, builder, moduleTranslation, allocaIP, reductionDecls, privateReductionVariables, reductionVariableMap); } @@ -952,13 +954,12 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, // Before the loop, store the initial values of reductions into reduction // variables. Although this could be done after allocas, we don't want to mess // up with the alloca insertion point. - MutableArrayRef reductionArgs = - loop.getRegion().getArguments().take_back(loop.getNumReductionVars()); - for (unsigned i = 0; i < loop.getNumReductionVars(); ++i) { + ArrayRef reductionArgs = wsloopOp.getRegion().getArguments(); + for (unsigned i = 0; i < wsloopOp.getNumReductionVars(); ++i) { SmallVector phis; // map block argument to initializer region - mapInitializationArg(loop, moduleTranslation, reductionDecls, i); + mapInitializationArg(wsloopOp, moduleTranslation, reductionDecls, i); if (failed(inlineConvertOmpRegions(reductionDecls[i].getInitializerRegion(), "omp.reduction.neutral", builder, @@ -977,7 +978,7 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, privateReductionVariables.push_back(var); moduleTranslation.mapValue(reductionArgs[i], phis[0]); - reductionVariableMap.try_emplace(loop.getReductionVars()[i], phis[0]); + reductionVariableMap.try_emplace(wsloopOp.getReductionVars()[i], phis[0]); } else { // for by-ref case the store is inside of the reduction region builder.CreateStore(phis[0], privateReductionVariables[i]); @@ -1008,33 +1009,34 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, auto bodyGen = [&](llvm::OpenMPIRBuilder::InsertPointTy ip, llvm::Value *iv) { // Make sure further conversions know about the induction variable. moduleTranslation.mapValue( - loop.getRegion().front().getArgument(loopInfos.size()), iv); + loopOp.getRegion().front().getArgument(loopInfos.size()), iv); // Capture the body insertion point for use in nested loops. BodyIP of the // CanonicalLoopInfo always points to the beginning of the entry block of // the body. bodyInsertPoints.push_back(ip); - if (loopInfos.size() != loop.getNumLoops() - 1) + if (loopInfos.size() != loopOp.getNumLoops() - 1) return; // Convert the body of the loop. builder.restoreIP(ip); - convertOmpOpRegions(loop.getRegion(), "omp.wsloop.region", builder, + convertOmpOpRegions(loopOp.getRegion(), "omp.wsloop.region", builder, moduleTranslation, bodyGenStatus); }; // Delegate actual loop construction to the OpenMP IRBuilder. - // TODO: this currently assumes Wsloop is semantically similar to SCF loop, - // i.e. it has a positive step, uses signed integer semantics. Reconsider - // this code when Wsloop clearly supports more cases. + // TODO: this currently assumes omp.loop_nest is semantically similar to SCF + // loop, i.e. it has a positive step, uses signed integer semantics. + // Reconsider this code when the nested loop operation clearly supports more + // cases. llvm::OpenMPIRBuilder *ompBuilder = moduleTranslation.getOpenMPBuilder(); - for (unsigned i = 0, e = loop.getNumLoops(); i < e; ++i) { + for (unsigned i = 0, e = loopOp.getNumLoops(); i < e; ++i) { llvm::Value *lowerBound = - moduleTranslation.lookupValue(loop.getLowerBound()[i]); + moduleTranslation.lookupValue(loopOp.getLowerBound()[i]); llvm::Value *upperBound = - moduleTranslation.lookupValue(loop.getUpperBound()[i]); - llvm::Value *step = moduleTranslation.lookupValue(loop.getStep()[i]); + moduleTranslation.lookupValue(loopOp.getUpperBound()[i]); + llvm::Value *step = moduleTranslation.lookupValue(loopOp.getStep()[i]); // Make sure loop trip count are emitted in the preheader of the outermost // loop at the latest so that they are all available for the new collapsed @@ -1047,7 +1049,7 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, } loopInfos.push_back(ompBuilder->createCanonicalLoop( loc, bodyGen, lowerBound, upperBound, step, - /*IsSigned=*/true, loop.getInclusive(), computeIP)); + /*IsSigned=*/true, loopOp.getInclusive(), computeIP)); if (failed(bodyGenStatus)) return failure(); @@ -1062,13 +1064,13 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, allocaIP = findAllocaInsertPoint(builder, moduleTranslation); // TODO: Handle doacross loops when the ordered clause has a parameter. - bool isOrdered = loop.getOrderedVal().has_value(); + bool isOrdered = wsloopOp.getOrderedVal().has_value(); std::optional scheduleModifier = - loop.getScheduleModifier(); - bool isSimd = loop.getSimdModifier(); + wsloopOp.getScheduleModifier(); + bool isSimd = wsloopOp.getSimdModifier(); ompBuilder->applyWorkshareLoop( - ompLoc.DL, loopInfo, allocaIP, !loop.getNowait(), + ompLoc.DL, loopInfo, allocaIP, !wsloopOp.getNowait(), convertToScheduleKind(schedule), chunk, isSimd, scheduleModifier == omp::ScheduleModifier::monotonic, scheduleModifier == omp::ScheduleModifier::nonmonotonic, isOrdered); @@ -1080,7 +1082,7 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, builder.restoreIP(afterIP); // Process the reductions if required. - if (loop.getNumReductionVars() == 0) + if (wsloopOp.getNumReductionVars() == 0) return success(); // Create the reduction generators. We need to own them here because @@ -1088,7 +1090,7 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, SmallVector owningReductionGens; SmallVector owningAtomicReductionGens; SmallVector reductionInfos; - collectReductionInfo(loop, builder, moduleTranslation, reductionDecls, + collectReductionInfo(wsloopOp, builder, moduleTranslation, reductionDecls, owningReductionGens, owningAtomicReductionGens, privateReductionVariables, reductionInfos); @@ -1099,9 +1101,9 @@ convertOmpWsloop(Operation &opInst, llvm::IRBuilderBase &builder, builder.SetInsertPoint(tempTerminator); llvm::OpenMPIRBuilder::InsertPointTy contInsertPoint = ompBuilder->createReductions(builder.saveIP(), allocaIP, reductionInfos, - loop.getNowait(), isByRef); + wsloopOp.getNowait(), isByRef); if (!contInsertPoint.getBlock()) - return loop->emitOpError() << "failed to convert reductions"; + return wsloopOp->emitOpError() << "failed to convert reductions"; auto nextInsertionPoint = ompBuilder->createBarrier(contInsertPoint, llvm::omp::OMPD_for); tempTerminator->eraseFromParent(); diff --git a/mlir/lib/Tools/lsp-server-support/Transport.cpp b/mlir/lib/Tools/lsp-server-support/Transport.cpp index 64dea35614c070a72ec256b1829aae620d57d706..339c5f3825165dbb09b9bbbb56d090cbe2bafcd2 100644 --- a/mlir/lib/Tools/lsp-server-support/Transport.cpp +++ b/mlir/lib/Tools/lsp-server-support/Transport.cpp @@ -51,12 +51,12 @@ private: Reply::Reply(const llvm::json::Value &id, llvm::StringRef method, JSONTransport &transport, std::mutex &transportOutputMutex) - : id(id), transport(&transport), + : method(method), id(id), transport(&transport), transportOutputMutex(transportOutputMutex) {} Reply::Reply(Reply &&other) - : replied(other.replied.load()), id(std::move(other.id)), - transport(other.transport), + : method(other.method), replied(other.replied.load()), + id(std::move(other.id)), transport(other.transport), transportOutputMutex(other.transportOutputMutex) { other.transport = nullptr; } diff --git a/mlir/lib/Transforms/Mem2Reg.cpp b/mlir/lib/Transforms/Mem2Reg.cpp index 0c1ce70f070852fd632951deab0e08e8f820fa5b..71ba5bc076f0e69962e55e8ac34ae89b4a361dda 100644 --- a/mlir/lib/Transforms/Mem2Reg.cpp +++ b/mlir/lib/Transforms/Mem2Reg.cpp @@ -191,13 +191,13 @@ private: /// Lazily-constructed default value representing the content of the slot when /// no store has been executed. This function may mutate IR. - Value getLazyDefaultValue(); + Value getOrCreateDefaultValue(); MemorySlot slot; PromotableAllocationOpInterface allocator; RewriterBase &rewriter; - /// Potentially non-initialized default value. Use `getLazyDefaultValue` to - /// initialize it on demand. + /// Potentially non-initialized default value. Use `getOrCreateDefaultValue` + /// to initialize it on demand. Value defaultValue; /// Contains the reaching definition at this operation. Reaching definitions /// are only computed for promotable memory operations with blocking uses. @@ -232,7 +232,7 @@ MemorySlotPromoter::MemorySlotPromoter( #endif // NDEBUG } -Value MemorySlotPromoter::getLazyDefaultValue() { +Value MemorySlotPromoter::getOrCreateDefaultValue() { if (defaultValue) return defaultValue; @@ -438,7 +438,7 @@ Value MemorySlotPromoter::computeReachingDefInBlock(Block *block, if (memOp.storesTo(slot)) { rewriter.setInsertionPointAfter(memOp); - Value stored = memOp.getStored(slot, rewriter, dataLayout); + Value stored = memOp.getStored(slot, rewriter, reachingDef, dataLayout); assert(stored && "a memory operation storing to a slot must provide a " "new definition of the slot"); reachingDef = stored; @@ -452,6 +452,7 @@ Value MemorySlotPromoter::computeReachingDefInBlock(Block *block, void MemorySlotPromoter::computeReachingDefInRegion(Region *region, Value reachingDef) { + assert(reachingDef && "expected an initial reaching def to be provided"); if (region->hasOneBlock()) { computeReachingDefInBlock(®ion->front(), reachingDef); return; @@ -508,12 +509,11 @@ void MemorySlotPromoter::computeReachingDefInRegion(Region *region, } job.reachingDef = computeReachingDefInBlock(block, job.reachingDef); + assert(job.reachingDef); if (auto terminator = dyn_cast(block->getTerminator())) { for (BlockOperand &blockOperand : terminator->getBlockOperands()) { if (info.mergePoints.contains(blockOperand.get())) { - if (!job.reachingDef) - job.reachingDef = getLazyDefaultValue(); rewriter.modifyOpInPlace(terminator, [&]() { terminator.getSuccessorOperands(blockOperand.getOperandNumber()) .append(job.reachingDef); @@ -567,7 +567,7 @@ void MemorySlotPromoter::removeBlockingUses() { // If no reaching definition is known, this use is outside the reach of // the slot. The default value should thus be used. if (!reachingDef) - reachingDef = getLazyDefaultValue(); + reachingDef = getOrCreateDefaultValue(); rewriter.setInsertionPointAfter(toPromote); if (toPromoteMemOp.removeBlockingUses( @@ -601,7 +601,8 @@ void MemorySlotPromoter::removeBlockingUses() { } void MemorySlotPromoter::promoteSlot() { - computeReachingDefInRegion(slot.ptr.getParentRegion(), {}); + computeReachingDefInRegion(slot.ptr.getParentRegion(), + getOrCreateDefaultValue()); // Now that reaching definitions are known, remove all users. removeBlockingUses(); @@ -617,7 +618,7 @@ void MemorySlotPromoter::promoteSlot() { succOperands.size() + 1 == mergePoint->getNumArguments()); if (succOperands.size() + 1 == mergePoint->getNumArguments()) rewriter.modifyOpInPlace( - user, [&]() { succOperands.append(getLazyDefaultValue()); }); + user, [&]() { succOperands.append(getOrCreateDefaultValue()); }); } } diff --git a/mlir/python/mlir/dialects/LLVMOps.td b/mlir/python/mlir/dialects/LLVMOps.td index dcf2f4245cf49f2c6f899611145b4e1800af25ca..30f047f21698e3dba8db905879b63fdac50eb01a 100644 --- a/mlir/python/mlir/dialects/LLVMOps.td +++ b/mlir/python/mlir/dialects/LLVMOps.td @@ -10,5 +10,6 @@ #define PYTHON_BINDINGS_LLVM_OPS include "mlir/Dialect/LLVMIR/LLVMOps.td" +include "mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td" #endif diff --git a/mlir/python/mlir/dialects/llvm.py b/mlir/python/mlir/dialects/llvm.py index 8aa16e4a2560308692ffbdd473076edaabf3ed5f..941a584966dcde94979d63cca0b25f239dab6318 100644 --- a/mlir/python/mlir/dialects/llvm.py +++ b/mlir/python/mlir/dialects/llvm.py @@ -5,3 +5,11 @@ from ._llvm_ops_gen import * from ._llvm_enum_gen import * from .._mlir_libs._mlirDialectsLLVM import * +from ..ir import Value +from ._ods_common import get_op_result_or_op_results as _get_op_result_or_op_results + + +def mlir_constant(value, *, loc=None, ip=None) -> Value: + return _get_op_result_or_op_results( + ConstantOp(res=value.type, value=value, loc=loc, ip=ip) + ) diff --git a/mlir/python/mlir/dialects/transform/interpreter/__init__.py b/mlir/python/mlir/dialects/transform/interpreter/__init__.py index 34cdc43cb617fdf491f8ce2e53651cfb16beff01..e69aa963038f2301f635ff95af04302853d05b64 100644 --- a/mlir/python/mlir/dialects/transform/interpreter/__init__.py +++ b/mlir/python/mlir/dialects/transform/interpreter/__init__.py @@ -29,7 +29,7 @@ def apply_named_sequence( if transform_options is None: _cextTransformInterpreter.apply_named_sequence(*args) else: - _cextTransformInterpreter(*args, transform_options) + _cextTransformInterpreter.apply_named_sequence(*args, transform_options) def copy_symbols_and_merge_into(target, other): diff --git a/mlir/test/CAPI/execution_engine.c b/mlir/test/CAPI/execution_engine.c index 38a8fb8c3e2137d734630f9eb16dfbe71ff0d162..81ff8477ffd7b73f39daac1bad2b1b0cd7c32786 100644 --- a/mlir/test/CAPI/execution_engine.c +++ b/mlir/test/CAPI/execution_engine.c @@ -99,8 +99,11 @@ void testOmpCreation(void) { " %1 = arith.constant 1 : i32 \n" " %2 = arith.constant 2 : i32 \n" " omp.parallel { \n" -" omp.wsloop for (%3) : i32 = (%0) to (%2) step (%1) { \n" -" omp.yield \n" +" omp.wsloop { \n" +" omp.loop_nest (%3) : i32 = (%0) to (%2) step (%1) { \n" +" omp.yield \n" +" } \n" +" omp.terminator \n" " } \n" " omp.terminator \n" " } \n" diff --git a/mlir/test/CAPI/sparse_tensor.c b/mlir/test/CAPI/sparse_tensor.c index f241e0e5c2fb560ea8665cda9795b2b552340e55..22b7052b732aa2bcdf67a12267c85f8ee3799d78 100644 --- a/mlir/test/CAPI/sparse_tensor.c +++ b/mlir/test/CAPI/sparse_tensor.c @@ -27,7 +27,7 @@ static int testRoundtripEncoding(MlirContext ctx) { const char *originalAsm = "#sparse_tensor.encoding<{ " "map = [s0](d0, d1) -> (s0 : dense, d0 : compressed, d1 : compressed), " - "posWidth = 32, crdWidth = 64 }>"; + "posWidth = 32, crdWidth = 64, explicitVal = 1 : i64}>"; // clang-format on MlirAttribute originalAttr = mlirAttributeParseGet(ctx, mlirStringRefCreateFromCString(originalAsm)); @@ -56,8 +56,21 @@ static int testRoundtripEncoding(MlirContext ctx) { // CHECK: crdWidth: 64 int crdWidth = mlirSparseTensorEncodingAttrGetCrdWidth(originalAttr); fprintf(stderr, "crdWidth: %d\n", crdWidth); + + // CHECK: explicitVal: 1 : i64 + MlirAttribute explicitVal = + mlirSparseTensorEncodingAttrGetExplicitVal(originalAttr); + fprintf(stderr, "explicitVal: "); + mlirAttributeDump(explicitVal); + // CHECK: implicitVal: <> + MlirAttribute implicitVal = + mlirSparseTensorEncodingAttrGetImplicitVal(originalAttr); + fprintf(stderr, "implicitVal: "); + mlirAttributeDump(implicitVal); + MlirAttribute newAttr = mlirSparseTensorEncodingAttrGet( - ctx, lvlRank, lvlTypes, dimToLvl, lvlToDim, posWidth, crdWidth); + ctx, lvlRank, lvlTypes, dimToLvl, lvlToDim, posWidth, crdWidth, + explicitVal, implicitVal); mlirAttributeDump(newAttr); // For debugging filecheck output. // CHECK: equal: 1 fprintf(stderr, "equal: %d\n", mlirAttributeEqual(originalAttr, newAttr)); diff --git a/mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir b/mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir index 9f45d139b81f212a87e4235aec830eec5886f7ee..3aeb9e70522d520f66ffa203839758a139fcc14e 100644 --- a/mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir +++ b/mlir/test/Conversion/OpenMPToLLVM/convert-to-llvmir.mlir @@ -71,15 +71,18 @@ func.func @branch_loop() { func.func @wsloop(%arg0: index, %arg1: index, %arg2: index, %arg3: index, %arg4: index, %arg5: index) { // CHECK: omp.parallel omp.parallel { - // CHECK: omp.wsloop for (%[[ARG6:.*]], %[[ARG7:.*]]) : i64 = (%[[ARG0]], %[[ARG1]]) to (%[[ARG2]], %[[ARG3]]) step (%[[ARG4]], %[[ARG5]]) { - "omp.wsloop"(%arg0, %arg1, %arg2, %arg3, %arg4, %arg5) ({ - ^bb0(%arg6: index, %arg7: index): - // CHECK-DAG: %[[CAST_ARG6:.*]] = builtin.unrealized_conversion_cast %[[ARG6]] : i64 to index - // CHECK-DAG: %[[CAST_ARG7:.*]] = builtin.unrealized_conversion_cast %[[ARG7]] : i64 to index - // CHECK: "test.payload"(%[[CAST_ARG6]], %[[CAST_ARG7]]) : (index, index) -> () - "test.payload"(%arg6, %arg7) : (index, index) -> () - omp.yield - }) {operandSegmentSizes = array} : (index, index, index, index, index, index) -> () + // CHECK: omp.wsloop { + "omp.wsloop"() ({ + // CHECK: omp.loop_nest (%[[ARG6:.*]], %[[ARG7:.*]]) : i64 = (%[[ARG0]], %[[ARG1]]) to (%[[ARG2]], %[[ARG3]]) step (%[[ARG4]], %[[ARG5]]) { + omp.loop_nest (%arg6, %arg7) : index = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) { + // CHECK-DAG: %[[CAST_ARG6:.*]] = builtin.unrealized_conversion_cast %[[ARG6]] : i64 to index + // CHECK-DAG: %[[CAST_ARG7:.*]] = builtin.unrealized_conversion_cast %[[ARG7]] : i64 to index + // CHECK: "test.payload"(%[[CAST_ARG6]], %[[CAST_ARG7]]) : (index, index) -> () + "test.payload"(%arg6, %arg7) : (index, index) -> () + omp.yield + } + omp.terminator + }) : () -> () omp.terminator } return @@ -323,12 +326,14 @@ llvm.func @_QPsb() { // CHECK-LABEL: @_QPsimple_reduction // CHECK: %[[RED_ACCUMULATOR:.*]] = llvm.alloca %{{.*}} x i32 {bindc_name = "x", uniq_name = "_QFsimple_reductionEx"} : (i64) -> !llvm.ptr // CHECK: omp.parallel -// CHECK: omp.wsloop reduction(@eqv_reduction %{{.+}} -> %[[PRV:.+]] : !llvm.ptr) for -// CHECK: %[[LPRV:.+]] = llvm.load %[[PRV]] : !llvm.ptr -> i32 -// CHECK: %[[CMP:.+]] = llvm.icmp "eq" %{{.*}}, %[[LPRV]] : i32 -// CHECK: %[[ZEXT:.+]] = llvm.zext %[[CMP]] : i1 to i32 -// CHECK: llvm.store %[[ZEXT]], %[[PRV]] : i32, !llvm.ptr -// CHECK: omp.yield +// CHECK: omp.wsloop reduction(@eqv_reduction %{{.+}} -> %[[PRV:.+]] : !llvm.ptr) +// CHECK-NEXT: omp.loop_nest {{.*}}{ +// CHECK: %[[LPRV:.+]] = llvm.load %[[PRV]] : !llvm.ptr -> i32 +// CHECK: %[[CMP:.+]] = llvm.icmp "eq" %{{.*}}, %[[LPRV]] : i32 +// CHECK: %[[ZEXT:.+]] = llvm.zext %[[CMP]] : i1 to i32 +// CHECK: llvm.store %[[ZEXT]], %[[PRV]] : i32, !llvm.ptr +// CHECK: omp.yield +// CHECK: omp.terminator // CHECK: omp.terminator // CHECK: llvm.return @@ -354,20 +359,23 @@ llvm.func @_QPsimple_reduction(%arg0: !llvm.ptr {fir.bindc_name = "y"}) { %4 = llvm.alloca %3 x i32 {bindc_name = "x", uniq_name = "_QFsimple_reductionEx"} : (i64) -> !llvm.ptr %5 = llvm.zext %2 : i1 to i32 llvm.store %5, %4 : i32, !llvm.ptr - omp.parallel { + omp.parallel { %6 = llvm.alloca %3 x i32 {adapt.valuebyref, in_type = i32, operandSegmentSizes = array, pinned} : (i64) -> !llvm.ptr - omp.wsloop reduction(@eqv_reduction %4 -> %prv : !llvm.ptr) for (%arg1) : i32 = (%1) to (%0) inclusive step (%1) { - llvm.store %arg1, %6 : i32, !llvm.ptr - %7 = llvm.load %6 : !llvm.ptr -> i32 - %8 = llvm.sext %7 : i32 to i64 - %9 = llvm.sub %8, %3 : i64 - %10 = llvm.getelementptr %arg0[0, %9] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<100 x i32> - %11 = llvm.load %10 : !llvm.ptr -> i32 - %12 = llvm.load %prv : !llvm.ptr -> i32 - %13 = llvm.icmp "eq" %11, %12 : i32 - %14 = llvm.zext %13 : i1 to i32 - llvm.store %14, %prv : i32, !llvm.ptr - omp.yield + omp.wsloop reduction(@eqv_reduction %4 -> %prv : !llvm.ptr) { + omp.loop_nest (%arg1) : i32 = (%1) to (%0) inclusive step (%1) { + llvm.store %arg1, %6 : i32, !llvm.ptr + %7 = llvm.load %6 : !llvm.ptr -> i32 + %8 = llvm.sext %7 : i32 to i64 + %9 = llvm.sub %8, %3 : i64 + %10 = llvm.getelementptr %arg0[0, %9] : (!llvm.ptr, i64) -> !llvm.ptr, !llvm.array<100 x i32> + %11 = llvm.load %10 : !llvm.ptr -> i32 + %12 = llvm.load %prv : !llvm.ptr -> i32 + %13 = llvm.icmp "eq" %11, %12 : i32 + %14 = llvm.zext %13 : i1 to i32 + llvm.store %14, %prv : i32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } diff --git a/mlir/test/Conversion/SCFToOpenMP/reductions.mlir b/mlir/test/Conversion/SCFToOpenMP/reductions.mlir index 3b6c145d62f1a865ac56c56024bedf945c21c6f4..fc6d56559c2618125050b2bcbf61dae87488c903 100644 --- a/mlir/test/Conversion/SCFToOpenMP/reductions.mlir +++ b/mlir/test/Conversion/SCFToOpenMP/reductions.mlir @@ -28,6 +28,7 @@ func.func @reduction1(%arg0 : index, %arg1 : index, %arg2 : index, // CHECK: omp.parallel // CHECK: omp.wsloop // CHECK-SAME: reduction(@[[$REDF]] %[[BUF]] -> %[[PVT_BUF:[a-z0-9]+]] + // CHECK: omp.loop_nest // CHECK: memref.alloca_scope scf.parallel (%i0, %i1) = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %step) init (%zero) -> (f32) { @@ -43,6 +44,7 @@ func.func @reduction1(%arg0 : index, %arg1 : index, %arg2 : index, } // CHECK: omp.yield } + // CHECK: omp.terminator // CHECK: omp.terminator // CHECK: llvm.load %[[BUF]] return @@ -107,6 +109,7 @@ func.func @reduction_muli(%arg0 : index, %arg1 : index, %arg2 : index, %one = arith.constant 1 : i32 // CHECK: %[[RED_VAR:.*]] = llvm.alloca %{{.*}} x i32 : (i64) -> !llvm.ptr // CHECK: omp.wsloop reduction(@[[$REDI]] %[[RED_VAR]] -> %[[RED_PVT_VAR:.*]] : !llvm.ptr) + // CHECK: omp.loop_nest scf.parallel (%i0, %i1) = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %step) init (%one) -> (i32) { // CHECK: %[[C2:.*]] = arith.constant 2 : i32 @@ -208,6 +211,7 @@ func.func @reduction4(%arg0 : index, %arg1 : index, %arg2 : index, // CHECK: omp.wsloop // CHECK-SAME: reduction(@[[$REDF1]] %[[BUF1]] -> %[[PVT_BUF1:[a-z0-9]+]] // CHECK-SAME: @[[$REDF2]] %[[BUF2]] -> %[[PVT_BUF2:[a-z0-9]+]] + // CHECK: omp.loop_nest // CHECK: memref.alloca_scope %res:2 = scf.parallel (%i0, %i1) = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %step) init (%zero, %ione) -> (f32, i64) { @@ -236,6 +240,7 @@ func.func @reduction4(%arg0 : index, %arg1 : index, %arg2 : index, } // CHECK: omp.yield } + // CHECK: omp.terminator // CHECK: omp.terminator // CHECK: %[[RES1:.*]] = llvm.load %[[BUF1]] : !llvm.ptr -> f32 // CHECK: %[[RES2:.*]] = llvm.load %[[BUF2]] : !llvm.ptr -> i64 diff --git a/mlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir b/mlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir index acd2690c56e2e67d5a2de9562d5e8f061f5d2140..b2f19d294cb5fe73e8b83f0ef5920383698f262b 100644 --- a/mlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir +++ b/mlir/test/Conversion/SCFToOpenMP/scf-to-openmp.mlir @@ -2,10 +2,11 @@ // CHECK-LABEL: @parallel func.func @parallel(%arg0: index, %arg1: index, %arg2: index, - %arg3: index, %arg4: index, %arg5: index) { + %arg3: index, %arg4: index, %arg5: index) { // CHECK: %[[FOUR:.+]] = llvm.mlir.constant(4 : i32) : i32 // CHECK: omp.parallel num_threads(%[[FOUR]] : i32) { - // CHECK: omp.wsloop for (%[[LVAR1:.*]], %[[LVAR2:.*]]) : index = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) { + // CHECK: omp.wsloop { + // CHECK: omp.loop_nest (%[[LVAR1:.*]], %[[LVAR2:.*]]) : index = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) { // CHECK: memref.alloca_scope scf.parallel (%i, %j) = (%arg0, %arg1) to (%arg2, %arg3) step (%arg4, %arg5) { // CHECK: "test.payload"(%[[LVAR1]], %[[LVAR2]]) : (index, index) -> () @@ -13,6 +14,8 @@ func.func @parallel(%arg0: index, %arg1: index, %arg2: index, // CHECK: omp.yield // CHECK: } } + // CHECK: omp.terminator + // CHECK: } // CHECK: omp.terminator // CHECK: } return @@ -23,20 +26,26 @@ func.func @nested_loops(%arg0: index, %arg1: index, %arg2: index, %arg3: index, %arg4: index, %arg5: index) { // CHECK: %[[FOUR:.+]] = llvm.mlir.constant(4 : i32) : i32 // CHECK: omp.parallel num_threads(%[[FOUR]] : i32) { - // CHECK: omp.wsloop for (%[[LVAR_OUT1:.*]]) : index = (%arg0) to (%arg2) step (%arg4) { - // CHECK: memref.alloca_scope + // CHECK: omp.wsloop { + // CHECK: omp.loop_nest (%[[LVAR_OUT1:.*]]) : index = (%arg0) to (%arg2) step (%arg4) { + // CHECK: memref.alloca_scope scf.parallel (%i) = (%arg0) to (%arg2) step (%arg4) { // CHECK: omp.parallel - // CHECK: omp.wsloop for (%[[LVAR_IN1:.*]]) : index = (%arg1) to (%arg3) step (%arg5) { + // CHECK: omp.wsloop { + // CHECK: omp.loop_nest (%[[LVAR_IN1:.*]]) : index = (%arg1) to (%arg3) step (%arg5) { // CHECK: memref.alloca_scope scf.parallel (%j) = (%arg1) to (%arg3) step (%arg5) { // CHECK: "test.payload"(%[[LVAR_OUT1]], %[[LVAR_IN1]]) : (index, index) -> () "test.payload"(%i, %j) : (index, index) -> () // CHECK: } } - // CHECK: omp.yield + // CHECK: omp.yield + // CHECK: } + // CHECK: omp.terminator // CHECK: } } + // CHECK: omp.terminator + // CHECK: } // CHECK: omp.terminator // CHECK: } return @@ -47,7 +56,8 @@ func.func @adjacent_loops(%arg0: index, %arg1: index, %arg2: index, %arg3: index, %arg4: index, %arg5: index) { // CHECK: %[[FOUR:.+]] = llvm.mlir.constant(4 : i32) : i32 // CHECK: omp.parallel num_threads(%[[FOUR]] : i32) { - // CHECK: omp.wsloop for (%[[LVAR_AL1:.*]]) : index = (%arg0) to (%arg2) step (%arg4) { + // CHECK: omp.wsloop { + // CHECK: omp.loop_nest (%[[LVAR_AL1:.*]]) : index = (%arg0) to (%arg2) step (%arg4) { // CHECK: memref.alloca_scope scf.parallel (%i) = (%arg0) to (%arg2) step (%arg4) { // CHECK: "test.payload1"(%[[LVAR_AL1]]) : (index) -> () @@ -55,12 +65,15 @@ func.func @adjacent_loops(%arg0: index, %arg1: index, %arg2: index, // CHECK: omp.yield // CHECK: } } + // CHECK: omp.terminator + // CHECK: } // CHECK: omp.terminator // CHECK: } // CHECK: %[[FOUR:.+]] = llvm.mlir.constant(4 : i32) : i32 // CHECK: omp.parallel num_threads(%[[FOUR]] : i32) { - // CHECK: omp.wsloop for (%[[LVAR_AL2:.*]]) : index = (%arg1) to (%arg3) step (%arg5) { + // CHECK: omp.wsloop { + // CHECK: omp.loop_nest (%[[LVAR_AL2:.*]]) : index = (%arg1) to (%arg3) step (%arg5) { // CHECK: memref.alloca_scope scf.parallel (%j) = (%arg1) to (%arg3) step (%arg5) { // CHECK: "test.payload2"(%[[LVAR_AL2]]) : (index) -> () @@ -68,6 +81,8 @@ func.func @adjacent_loops(%arg0: index, %arg1: index, %arg2: index, // CHECK: omp.yield // CHECK: } } + // CHECK: omp.terminator + // CHECK: } // CHECK: omp.terminator // CHECK: } return diff --git a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir index b4049000c50dc8b2b3723a63eb3ba995f14391a9..39699ee315e6cb30d28b2d0f1b7e0d80e641705d 100644 --- a/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir +++ b/mlir/test/Conversion/TosaToLinalg/tosa-to-linalg-named.mlir @@ -503,6 +503,19 @@ func.func @avg_pool_dyn(%arg0: tensor) -> (tensor) // ----- +// CHECK: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3) -> (0)> +// CHECK: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)> + +// CHECK-LABEL: @conv2d_scalar_bias_f32 +func.func @conv2d_scalar_bias_f32(%input: tensor<1x49x42x27xf32>, %weights: tensor<28x3x3x27xf32>, %bias: tensor<1xf32>) -> () { + // CHECK: %[[INIT:.+]] = tensor.empty() : tensor<1x45x40x28xf32> + // CHECK: %[[BROADCAST:.+]] = linalg.generic {indexing_maps = [#[[$MAP1]], #[[$MAP2]]], iterator_types = ["parallel", "parallel", "parallel", "parallel"]} ins(%arg2 : tensor<1xf32>) outs(%[[INIT]] : tensor<1x45x40x28xf32>) { + %0 = tosa.conv2d %input, %weights, %bias {pad = array, stride = array, dilation = array} : (tensor<1x49x42x27xf32>, tensor<28x3x3x27xf32>, tensor<1xf32>) -> tensor<1x45x40x28xf32> + return +} + +// ----- + // CHECK: #[[$MAP1:.+]] = affine_map<(d0, d1, d2, d3) -> (d3)> // CHECK: #[[$MAP2:.+]] = affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)> diff --git a/mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir b/mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir index d3f02c6288a240a140506cad65f5cb1fb986e897..ce0b46e0f061a462a9b7142a5cd03f1830da89a7 100644 --- a/mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir +++ b/mlir/test/Conversion/VectorToArmSME/vector-to-arm-sme.mlir @@ -620,3 +620,626 @@ func.func @vector_print_tile(%tile: vector<[4]x[4]xf32>) // CHECK-NEXT: scf.for %[[TILE_SLICE_INDEX:.*]] = %[[C0]] to %[[NUM_TILE_SLICES]] step %[[C1]] { // CHECK-NEXT: %[[TILE_SLICE:.*]] = arm_sme.move_tile_slice_to_vector %[[TILE]][%[[TILE_SLICE_INDEX]]] : vector<[4]xf32> from vector<[4]x[4]xf32> // CHECK-NEXT: vector.print %[[TILE_SLICE]] : vector<[4]xf32> + +//===----------------------------------------------------------------------===// +// vector.load +//===----------------------------------------------------------------------===// + +// ----- + +// CHECK-LABEL: @vector_load_i8_with_offset( +// CHECK-SAME: %[[MEMREF:.*]]: memref) +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[C123:.*]] = arith.constant 123 : index +// CHECK: arm_sme.tile_load %[[MEMREF]][%[[C123]], %[[C0]]] : memref, vector<[16]x[16]xi8> +func.func @vector_load_i8_with_offset(%arg0 : memref) -> vector<[16]x[16]xi8> { + %c0 = arith.constant 0 : index + %c123 = arith.constant 123 : index + %tile = vector.load %arg0[%c123, %c0] : memref, vector<[16]x[16]xi8> + return %tile : vector<[16]x[16]xi8> +} + +// ----- + +// CHECK-LABEL: @vector_load_i8_from_rank_1_memref( +// CHECK-SAME: %[[MEMREF:.*]]: memref) +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: arm_sme.tile_load %[[MEMREF]][%[[C0]]] : memref, vector<[16]x[16]xi8> +func.func @vector_load_i8_from_rank_1_memref(%arg0 : memref) -> vector<[16]x[16]xi8> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0] : memref, vector<[16]x[16]xi8> + return %tile : vector<[16]x[16]xi8> +} + +// ----- + +// CHECK-LABEL: @vector_load_i16( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[8]x[8]xi16> +func.func @vector_load_i16(%arg0 : memref) -> vector<[8]x[8]xi16> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[8]x[8]xi16> + return %tile : vector<[8]x[8]xi16> +} + +// ----- + +// CHECK-LABEL: @vector_load_i32( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[4]x[4]xi32> +func.func @vector_load_i32(%arg0 : memref) -> vector<[4]x[4]xi32> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[4]x[4]xi32> + return %tile : vector<[4]x[4]xi32> +} + +// ----- + +// CHECK-LABEL: @vector_load_i64( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[2]x[2]xi64> +func.func @vector_load_i64(%arg0 : memref) -> vector<[2]x[2]xi64> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[2]x[2]xi64> + return %tile : vector<[2]x[2]xi64> +} + +// ----- + +// CHECK-LABEL: @vector_load_f16( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[8]x[8]xf16> +func.func @vector_load_f16(%arg0 : memref) -> vector<[8]x[8]xf16> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[8]x[8]xf16> + return %tile : vector<[8]x[8]xf16> +} + +// ----- + +// CHECK-LABEL: @vector_load_bf16( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[8]x[8]xbf16> +func.func @vector_load_bf16(%arg0 : memref) -> vector<[8]x[8]xbf16> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[8]x[8]xbf16> + return %tile : vector<[8]x[8]xbf16> +} + +// ----- + +// CHECK-LABEL: @vector_load_f32( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[4]x[4]xf32> +func.func @vector_load_f32(%arg0 : memref) -> vector<[4]x[4]xf32> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[4]x[4]xf32> + return %tile : vector<[4]x[4]xf32> +} + +// ----- + +// CHECK-LABEL: @vector_load_f64( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[2]x[2]xf64> +func.func @vector_load_f64(%arg0 : memref) -> vector<[2]x[2]xf64> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[2]x[2]xf64> + return %tile : vector<[2]x[2]xf64> +} + +// ----- + +// CHECK-LABEL: @vector_load_i128( +// CHECK: arm_sme.tile_load {{.*}} : memref, vector<[1]x[1]xi128> +func.func @vector_load_i128(%arg0 : memref) -> vector<[1]x[1]xi128> { + %c0 = arith.constant 0 : index + %tile = vector.load %arg0[%c0, %c0] : memref, vector<[1]x[1]xi128> + return %tile : vector<[1]x[1]xi128> +} + + +//===----------------------------------------------------------------------===// +// vector.store +//===----------------------------------------------------------------------===// + +// ----- + +// CHECK-LABEL: @vector_store_i8( +// CHECK-SAME: %[[MEMREF:.*]]: memref) { +// CHECK: %[[C0:.*]] = arith.constant 0 : index +// CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[16]x[16]xi8> +// CHECK: arm_sme.tile_store %[[TILE]], %[[MEMREF]][%[[C0]], %[[C0]]] : memref, vector<[16]x[16]xi8> +func.func @vector_store_i8(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[16]x[16]xi8> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[16]x[16]xi8> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_i16 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[8]x[8]xi16> +func.func @vector_store_i16(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[8]x[8]xi16> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[8]x[8]xi16> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_i32 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[4]x[4]xi32> +func.func @vector_store_i32(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[4]x[4]xi32> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[4]x[4]xi32> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_i64 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[2]x[2]xi64> +func.func @vector_store_i64(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[2]x[2]xi64> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[2]x[2]xi64> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_f16 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[8]x[8]xf16> +func.func @vector_store_f16(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[8]x[8]xf16> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[8]x[8]xf16> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_bf16 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[8]x[8]xbf16> +func.func @vector_store_bf16(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[8]x[8]xbf16> + return +} +// ----- + +// CHECK-LABEL: @vector_store_f32 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[4]x[4]xf32> +func.func @vector_store_f32(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[4]x[4]xf32> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[4]x[4]xf32> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_f64 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[2]x[2]xf64> +func.func @vector_store_f64(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[2]x[2]xf64> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[2]x[2]xf64> + return +} + +// ----- + +// CHECK-LABEL: @vector_store_i128 +// CHECK: arm_sme.tile_store {{.*}} : memref, vector<[1]x[1]xi128> +func.func @vector_store_i128(%arg0 : memref) { + %c0 = arith.constant 0 : index + %tile = arm_sme.get_tile : vector<[1]x[1]xi128> + vector.store %tile, %arg0[%c0, %c0] : memref, vector<[1]x[1]xi128> + return +} + +//===----------------------------------------------------------------------===// +// vector.insert +//===----------------------------------------------------------------------===// + +// ----- + +// CHECK-LABEL: @vector_insert_slice_i32( +// CHECK-SAME: %[[SLICE:.*]]: vector<[4]xi32>, +// CHECK-SAME: %[[INDEX:.*]]: index) +func.func @vector_insert_slice_i32(%slice: vector<[4]xi32>, %row: index) -> vector<[4]x[4]xi32>{ + // CHECK-NEXT: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> + // CHECK-NEXT: arm_sme.move_vector_to_tile_slice %[[SLICE]], %[[TILE]], %[[INDEX]] : vector<[4]xi32> into vector<[4]x[4]xi32> + %tile = arm_sme.get_tile : vector<[4]x[4]xi32> + %new_tile = vector.insert %slice, %tile[%row] : vector<[4]xi32> into vector<[4]x[4]xi32> + return %new_tile : vector<[4]x[4]xi32> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_i8 +func.func @vector_insert_slice_i8(%slice: vector<[16]xi8>, %row: index) -> vector<[16]x[16]xi8> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[16]xi8> into vector<[16]x[16]xi8> + %tile = arm_sme.get_tile : vector<[16]x[16]xi8> + %new_tile = vector.insert %slice, %tile[%row] : vector<[16]xi8> into vector<[16]x[16]xi8> + return %new_tile : vector<[16]x[16]xi8> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_i16 +func.func @vector_insert_slice_i16(%slice: vector<[8]xi16>, %row: index) -> vector<[8]x[8]xi16> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[8]xi16> into vector<[8]x[8]xi16> + %tile = arm_sme.get_tile : vector<[8]x[8]xi16> + %new_tile = vector.insert %slice, %tile[%row] : vector<[8]xi16> into vector<[8]x[8]xi16> + return %new_tile : vector<[8]x[8]xi16> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_i64 +func.func @vector_insert_slice_i64(%slice: vector<[2]xi64>, %row: index) -> vector<[2]x[2]xi64> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[2]xi64> into vector<[2]x[2]xi64> + %tile = arm_sme.get_tile : vector<[2]x[2]xi64> + %new_tile = vector.insert %slice, %tile[%row] : vector<[2]xi64> into vector<[2]x[2]xi64> + return %new_tile : vector<[2]x[2]xi64> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_i128 +func.func @vector_insert_slice_i128(%slice: vector<[1]xi128>, %row: index) -> vector<[1]x[1]xi128> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[1]xi128> into vector<[1]x[1]xi128> + %tile = arm_sme.get_tile : vector<[1]x[1]xi128> + %new_tile = vector.insert %slice, %tile[%row] : vector<[1]xi128> into vector<[1]x[1]xi128> + return %new_tile : vector<[1]x[1]xi128> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_f16 +func.func @vector_insert_slice_f16(%slice: vector<[8]xf16>, %row: index) -> vector<[8]x[8]xf16> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[8]xf16> into vector<[8]x[8]xf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xf16> + %new_tile = vector.insert %slice, %tile[%row] : vector<[8]xf16> into vector<[8]x[8]xf16> + return %new_tile : vector<[8]x[8]xf16> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_bf16 +func.func @vector_insert_slice_bf16(%slice: vector<[8]xbf16>, %row: index) -> vector<[8]x[8]xbf16> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[8]xbf16> into vector<[8]x[8]xbf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> + %new_tile = vector.insert %slice, %tile[%row] : vector<[8]xbf16> into vector<[8]x[8]xbf16> + return %new_tile : vector<[8]x[8]xbf16> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_f32 +func.func @vector_insert_slice_f32(%slice: vector<[4]xf32>, %row: index) -> vector<[4]x[4]xf32> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[4]xf32> into vector<[4]x[4]xf32> + %tile = arm_sme.get_tile : vector<[4]x[4]xf32> + %new_tile = vector.insert %slice, %tile[%row] : vector<[4]xf32> into vector<[4]x[4]xf32> + return %new_tile : vector<[4]x[4]xf32> +} + +// ----- + +// CHECK-LABEL: @vector_insert_slice_f64 +func.func @vector_insert_slice_f64(%slice: vector<[2]xf64>, %row: index) -> vector<[2]x[2]xf64> { + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}} : vector<[2]xf64> into vector<[2]x[2]xf64> + %tile = arm_sme.get_tile : vector<[2]x[2]xf64> + %new_tile = vector.insert %slice, %tile[%row] : vector<[2]xf64> into vector<[2]x[2]xf64> + return %new_tile : vector<[2]x[2]xf64> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_i32( +// CHECK-SAME: %[[EL:.*]]: i32, +// CHECK-SAME: %[[ROW:.*]]: index, +// CHECK-SAME: %[[COL:.*]]: index) +func.func @vector_insert_element_i32(%el: i32, %row: index, %col: index) -> vector<[4]x[4]xi32> { + // CHECK-NEXT: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> + // CHECK-NEXT: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %[[TILE]][%[[ROW]]] : vector<[4]xi32> from vector<[4]x[4]xi32> + // CHECK-NEXT: %[[NEW_SLICE:.*]] = vector.insert %[[EL]], %[[SLICE]] [%[[COL]]] : i32 into vector<[4]xi32> + // CHECK-NEXT: arm_sme.move_vector_to_tile_slice %[[NEW_SLICE]], %[[TILE]], %[[ROW]] : vector<[4]xi32> into vector<[4]x[4]xi32> + %tile = arm_sme.get_tile : vector<[4]x[4]xi32> + %new_tile = vector.insert %el, %tile[%row, %col] : i32 into vector<[4]x[4]xi32> + return %new_tile : vector<[4]x[4]xi32> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_i8 +func.func @vector_insert_element_i8(%el: i8, %row: index, %col: index) -> vector<[16]x[16]xi8> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[16]x[16]xi8> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[16]xi8> from vector<[16]x[16]xi8> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[16]xi8> into vector<[16]x[16]xi8> + %tile = arm_sme.get_tile : vector<[16]x[16]xi8> + %new_tile = vector.insert %el, %tile[%row, %col] : i8 into vector<[16]x[16]xi8> + return %new_tile : vector<[16]x[16]xi8> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_i16 +func.func @vector_insert_element_i16(%el: i16, %row: index, %col: index) -> vector<[8]x[8]xi16> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[8]x[8]xi16> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[8]xi16> from vector<[8]x[8]xi16> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[8]xi16> into vector<[8]x[8]xi16> + %tile = arm_sme.get_tile : vector<[8]x[8]xi16> + %new_tile = vector.insert %el, %tile[%row, %col] : i16 into vector<[8]x[8]xi16> + return %new_tile : vector<[8]x[8]xi16> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_i64 +func.func @vector_insert_element_i64(%el: i64, %row: index, %col: index) -> vector<[2]x[2]xi64> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[2]x[2]xi64> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[2]xi64> from vector<[2]x[2]xi64> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[2]xi64> into vector<[2]x[2]xi64> + %tile = arm_sme.get_tile : vector<[2]x[2]xi64> + %new_tile = vector.insert %el, %tile[%row, %col] : i64 into vector<[2]x[2]xi64> + return %new_tile : vector<[2]x[2]xi64> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_i128 +func.func @vector_insert_element_i128(%el: i128, %row: index, %col: index) -> vector<[1]x[1]xi128> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[1]x[1]xi128> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[1]xi128> from vector<[1]x[1]xi128> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[1]xi128> into vector<[1]x[1]xi128> + %tile = arm_sme.get_tile : vector<[1]x[1]xi128> + %new_tile = vector.insert %el, %tile[%row, %col] : i128 into vector<[1]x[1]xi128> + return %new_tile : vector<[1]x[1]xi128> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_f16 +func.func @vector_insert_element_f16(%el: f16, %row: index, %col: index) -> vector<[8]x[8]xf16> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[8]x[8]xf16> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[8]xf16> from vector<[8]x[8]xf16> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[8]xf16> into vector<[8]x[8]xf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xf16> + %new_tile = vector.insert %el, %tile[%row, %col] : f16 into vector<[8]x[8]xf16> + return %new_tile : vector<[8]x[8]xf16> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_bf16 +func.func @vector_insert_element_bf16(%el: bf16, %row: index, %col: index) -> vector<[8]x[8]xbf16> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[8]x[8]xbf16> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[8]xbf16> from vector<[8]x[8]xbf16> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[8]xbf16> into vector<[8]x[8]xbf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> + %new_tile = vector.insert %el, %tile[%row, %col] : bf16 into vector<[8]x[8]xbf16> + return %new_tile : vector<[8]x[8]xbf16> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_f32 +func.func @vector_insert_element_f32(%el: f32, %row: index, %col: index) -> vector<[4]x[4]xf32> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xf32> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[4]xf32> from vector<[4]x[4]xf32> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[4]xf32> into vector<[4]x[4]xf32> + %tile = arm_sme.get_tile : vector<[4]x[4]xf32> + %new_tile = vector.insert %el, %tile[%row, %col] : f32 into vector<[4]x[4]xf32> + return %new_tile : vector<[4]x[4]xf32> +} + +// ----- + +// CHECK-LABEL: @vector_insert_element_f64 +func.func @vector_insert_element_f64(%el: f64, %row: index, %col: index) -> vector<[2]x[2]xf64> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[2]x[2]xf64> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]]{{.*}} : vector<[2]xf64> from vector<[2]x[2]xf64> + // CHECK: arm_sme.move_vector_to_tile_slice %{{.*}}, %[[TILE]], %{{.*}} : vector<[2]xf64> into vector<[2]x[2]xf64> + %tile = arm_sme.get_tile : vector<[2]x[2]xf64> + %new_tile = vector.insert %el, %tile[%row, %col] : f64 into vector<[2]x[2]xf64> + return %new_tile : vector<[2]x[2]xf64> +} + +//===----------------------------------------------------------------------===// +// vector.extract +//===----------------------------------------------------------------------===// + +// ----- + +// CHECK-LABEL: @vector_extract_slice_i32( +// CHECK-SAME: %[[INDEX:.*]]: index) +func.func @vector_extract_slice_i32(%row: index) -> vector<[4]xi32> { + // CHECK: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> + // CHECK: arm_sme.move_tile_slice_to_vector %[[TILE]][%[[INDEX]]] : vector<[4]xi32> from vector<[4]x[4]xi32> + %tile = arm_sme.get_tile : vector<[4]x[4]xi32> + %slice = vector.extract %tile[%row] : vector<[4]xi32> from vector<[4]x[4]xi32> + return %slice : vector<[4]xi32> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_i8 +func.func @vector_extract_slice_i8(%row: index) -> vector<[16]xi8> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[16]xi8> from vector<[16]x[16]xi8> + %tile = arm_sme.get_tile : vector<[16]x[16]xi8> + %slice = vector.extract %tile[%row] : vector<[16]xi8> from vector<[16]x[16]xi8> + return %slice : vector<[16]xi8> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_i16 +func.func @vector_extract_slice_i16(%row: index) -> vector<[8]xi16> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[8]xi16> from vector<[8]x[8]xi16> + %tile = arm_sme.get_tile : vector<[8]x[8]xi16> + %slice = vector.extract %tile[%row] : vector<[8]xi16> from vector<[8]x[8]xi16> + return %slice : vector<[8]xi16> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_i64 +func.func @vector_extract_slice_i64(%row: index) -> vector<[2]xi64> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[2]xi64> from vector<[2]x[2]xi64> + %tile = arm_sme.get_tile : vector<[2]x[2]xi64> + %slice = vector.extract %tile[%row] : vector<[2]xi64> from vector<[2]x[2]xi64> + return %slice : vector<[2]xi64> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_i128 +func.func @vector_extract_slice_i128(%row: index) -> vector<[1]xi128> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[1]xi128> from vector<[1]x[1]xi128> + %tile = arm_sme.get_tile : vector<[1]x[1]xi128> + %slice = vector.extract %tile[%row] : vector<[1]xi128> from vector<[1]x[1]xi128> + return %slice : vector<[1]xi128> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_f16 +func.func @vector_extract_slice_f16(%row: index) -> vector<[8]xf16> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[8]xf16> from vector<[8]x[8]xf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xf16> + %slice = vector.extract %tile[%row] : vector<[8]xf16> from vector<[8]x[8]xf16> + return %slice : vector<[8]xf16> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_bf16 +func.func @vector_extract_slice_bf16(%row: index) -> vector<[8]xbf16> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[8]xbf16> from vector<[8]x[8]xbf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> + %slice = vector.extract %tile[%row] : vector<[8]xbf16> from vector<[8]x[8]xbf16> + return %slice : vector<[8]xbf16> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_f32 +func.func @vector_extract_slice_f32(%row: index) -> vector<[4]xf32> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[4]xf32> from vector<[4]x[4]xf32> + %tile = arm_sme.get_tile : vector<[4]x[4]xf32> + %slice = vector.extract %tile[%row] : vector<[4]xf32> from vector<[4]x[4]xf32> + return %slice : vector<[4]xf32> +} + +// ----- + +// CHECK-LABEL: @vector_extract_slice_f64 +func.func @vector_extract_slice_f64(%row: index) -> vector<[2]xf64> { + // CHECK: arm_sme.move_tile_slice_to_vector {{.*}} : vector<[2]xf64> from vector<[2]x[2]xf64> + %tile = arm_sme.get_tile : vector<[2]x[2]xf64> + %slice = vector.extract %tile[%row] : vector<[2]xf64> from vector<[2]x[2]xf64> + return %slice : vector<[2]xf64> +} + +// ----- + +// CHECK-LABEL: @vector_extract_element( +// CHECK-SAME: %[[ROW:.*]]: index, +// CHECK-SAME: %[[COL:.*]]: index) +func.func @vector_extract_element(%row: index, %col: index) -> i32 { + // CHECK-NEXT: %[[TILE:.*]] = arm_sme.get_tile : vector<[4]x[4]xi32> + // CHECK-NEXT: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %[[TILE]][%[[ROW]]] : vector<[4]xi32> from vector<[4]x[4]xi32> + // CHECK-NEXT: %[[EL:.*]] = vector.extract %[[SLICE]]{{\[}}%[[COL]]] : i32 from vector<[4]xi32> + %tile = arm_sme.get_tile : vector<[4]x[4]xi32> + %el = vector.extract %tile[%row, %col] : i32 from vector<[4]x[4]xi32> + return %el : i32 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_i8 +func.func @vector_extract_element_i8(%row: index, %col: index) -> i8 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[16]xi8> from vector<[16]x[16]xi8> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i8 from vector<[16]xi8> + %tile = arm_sme.get_tile : vector<[16]x[16]xi8> + %el = vector.extract %tile[%row, %col] : i8 from vector<[16]x[16]xi8> + return %el : i8 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_i16 +func.func @vector_extract_element_i16(%row: index, %col: index) -> i16 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[8]xi16> from vector<[8]x[8]xi16> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i16 from vector<[8]xi16> + %tile = arm_sme.get_tile : vector<[8]x[8]xi16> + %el = vector.extract %tile[%row, %col] : i16 from vector<[8]x[8]xi16> + return %el : i16 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_i64 +func.func @vector_extract_element_i64(%row: index, %col: index) -> i64 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[2]xi64> from vector<[2]x[2]xi64> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i64 from vector<[2]xi64> + %tile = arm_sme.get_tile : vector<[2]x[2]xi64> + %el = vector.extract %tile[%row, %col] : i64 from vector<[2]x[2]xi64> + return %el : i64 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_i128 +func.func @vector_extract_element_i128(%row: index, %col: index) -> i128 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[1]xi128> from vector<[1]x[1]xi128> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i128 from vector<[1]xi128> + %tile = arm_sme.get_tile : vector<[1]x[1]xi128> + %el = vector.extract %tile[%row, %col] : i128 from vector<[1]x[1]xi128> + return %el : i128 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_f16 +func.func @vector_extract_element_f16(%row: index, %col: index) -> f16 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[8]xf16> from vector<[8]x[8]xf16> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : f16 from vector<[8]xf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xf16> + %el = vector.extract %tile[%row, %col] : f16 from vector<[8]x[8]xf16> + return %el : f16 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_bf16 +func.func @vector_extract_element_bf16(%row: index, %col: index) -> bf16 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[8]xbf16> from vector<[8]x[8]xbf16> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : bf16 from vector<[8]xbf16> + %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> + %el = vector.extract %tile[%row, %col] : bf16 from vector<[8]x[8]xbf16> + return %el : bf16 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_f32 +func.func @vector_extract_element_f32(%row: index, %col: index) -> f32 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[4]xf32> from vector<[4]x[4]xf32> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : f32 from vector<[4]xf32> + %tile = arm_sme.get_tile : vector<[4]x[4]xf32> + %el = vector.extract %tile[%row, %col] : f32 from vector<[4]x[4]xf32> + return %el : f32 +} + +// ----- + +// CHECK-LABEL: @vector_extract_element_f64 +func.func @vector_extract_element_f64(%row: index, %col: index) -> f64 { + // CHECK: %[[SLICE:.*]] = arm_sme.move_tile_slice_to_vector %{{.*}} : vector<[2]xf64> from vector<[2]x[2]xf64> + // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : f64 from vector<[2]xf64> + %tile = arm_sme.get_tile : vector<[2]x[2]xf64> + %el = vector.extract %tile[%row, %col] : f64 from vector<[2]x[2]xf64> + return %el : f64 +} diff --git a/mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir b/mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir deleted file mode 100644 index 17a070999c20a05327c325574dcd801be78c270c..0000000000000000000000000000000000000000 --- a/mlir/test/Dialect/ArmSME/vector-ops-to-llvm.mlir +++ /dev/null @@ -1,877 +0,0 @@ -// RUN: mlir-opt %s -convert-vector-to-arm-sme -convert-arith-to-arm-sme -allocate-arm-sme-tiles -convert-arm-sme-to-scf -convert-arm-sme-to-llvm -cse -canonicalize -split-input-file -allow-unregistered-dialect -verify-diagnostics | FileCheck %s - -//===----------------------------------------------------------------------===// -// vector.transfer_write -//===----------------------------------------------------------------------===// - -// CHECK-LABEL: @transfer_write_2d_zero_i8( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[ARG0]] : memref to !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index -// CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MIN_SVL_B:.*]] = arith.constant 16 : index -// CHECK-DAG: %[[PTRUE_ALL:.*]] = arith.constant dense : vector<[16]xi1> -// CHECK-DAG: %[[C0_I64:.*]] = builtin.unrealized_conversion_cast %[[C0]] : index to i64 -// CHECK-DAG: "arm_sme.intr.zero"() <{tile_mask = 255 : i32}> : () -> () -// CHECK-DAG: %[[VSCALE:.*]] = vector.vscale -// CHECK-NEXT: %[[SVL_B:.*]] = arith.muli %[[VSCALE]], %[[MIN_SVL_B]] : index -// CHECK-NEXT: scf.for %[[TILE_SLICE:.*]] = %[[C0]] to %[[SVL_B]] step %[[C1]] { -// CHECK: %[[TILE_SLICE_I64:.*]] = builtin.unrealized_conversion_cast %[[TILE_SLICE]] : index to i64 -// CHECK-NEXT: %[[ALIGNED_BASE:.*]] = llvm.extractvalue %[[MEM_DESC]][1] : !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-NEXT: %[[STRIDE0:.*]] = llvm.extractvalue %[[MEM_DESC]][4, 0] : !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-NEXT: %[[OFF0:.*]] = llvm.mul %[[TILE_SLICE_I64]], %[[STRIDE0]] : i64 -// CHECK-NEXT: %[[OFF1:.*]] = llvm.add %[[OFF0]], %[[C0_I64]] : i64 -// CHECK-NEXT: %[[GEP:.*]] = llvm.getelementptr %[[ALIGNED_BASE]]{{\[}}%[[OFF1]]] : (!llvm.ptr, i64) -> !llvm.ptr, i8 -// CHECK-NEXT: %[[TILE_SLICE_I32:.*]] = arith.index_castui %[[TILE_SLICE]] : index to i32 -// CHECK-NEXT: "arm_sme.intr.st1b.horiz"(%[[PTRUE_ALL]], %[[GEP]], %[[TILE_SLICE_I32]]) <{tile_id = 0 : i32}> : (vector<[16]xi1>, !llvm.ptr, i32) -> () -func.func @transfer_write_2d_zero_i8(%arg0 : memref) { - %c0 = arith.constant 0 : index - %cst = arith.constant dense<0> : vector<[16]x[16]xi8> - vector.transfer_write %cst, %arg0[%c0, %c0] {in_bounds = [true, true]} : vector<[16]x[16]xi8>, memref - return -} - -//===----------------------------------------------------------------------===// -// vector.load -//===----------------------------------------------------------------------===// - -// ----- - -// Load an 8-bit tile from a rank 2 memref with a non-zero offset for the first -// memref index. This verifies the offset is preserved when materializing the -// loop of tile slice loads. - -// CHECK-LABEL: @vector_load_i8_with_offset( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[ARG0]] : memref to !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index -// CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[C123:.*]] = arith.constant 123 : index -// CHECK-DAG: %[[MIN_SVL_B:.*]] = arith.constant 16 : index -// CHECK-DAG: %[[PTRUE_ALL:.*]] = arith.constant dense : vector<[16]xi1> -// CHECK-DAG: %[[C0_I64:.*]] = builtin.unrealized_conversion_cast %[[C0]] : index to i64 -// CHECK-DAG: %[[VSCALE:.*]] = vector.vscale -// CHECK-NEXT: %[[SVL_B:.*]] = arith.muli %[[VSCALE]], %[[MIN_SVL_B]] : index -// CHECK-NEXT: scf.for %[[TILE_SLICE:.*]] = %[[C0]] to %[[SVL_B]] step %[[C1]] { -// CHECK-NEXT: %[[TILE_SLICE_PLUS_OFF0:.*]] = arith.addi %[[TILE_SLICE]], %[[C123]] : index -// CHECK-NEXT: %[[TILE_SLICE_PLUS_OFF0_I64:.*]] = builtin.unrealized_conversion_cast %[[TILE_SLICE_PLUS_OFF0]] : index to i64 -// CHECK-NEXT: %[[ALIGNED_BASE:.*]] = llvm.extractvalue %[[MEM_DESC]][1] : !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-NEXT: %[[STRIDE0:.*]] = llvm.extractvalue %[[MEM_DESC]][4, 0] : !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-NEXT: %[[OFF0:.*]] = llvm.mul %[[TILE_SLICE_PLUS_OFF0_I64]], %[[STRIDE0]] : i64 -// CHECK-NEXT: %[[OFF1:.*]] = llvm.add %[[OFF0]], %[[C0_I64]] : i64 -// CHECK-NEXT: %[[GEP:.*]] = llvm.getelementptr %[[ALIGNED_BASE]]{{\[}}%[[OFF1]]] : (!llvm.ptr, i64) -> !llvm.ptr, i8 -// CHECK-NEXT: %[[TILE_SLICE_I32:.*]] = arith.index_castui %[[TILE_SLICE]] : index to i32 -// CHECK-NEXT: "arm_sme.intr.ld1b.horiz"(%[[PTRUE_ALL]], %[[GEP]], %[[TILE_SLICE_I32]]) <{tile_id = 0 : i32}> : (vector<[16]xi1>, !llvm.ptr, i32) -> () -// CHECK-NEXT: } -func.func @vector_load_i8_with_offset(%arg0 : memref) -> vector<[16]x[16]xi8> { - %c0 = arith.constant 0 : index - %c123 = arith.constant 123 : index - %tile = vector.load %arg0[%c123, %c0] : memref, vector<[16]x[16]xi8> - return %tile : vector<[16]x[16]xi8> -} - -// ----- - -// CHECK-LABEL: @vector_load_i8_from_rank_1_memref( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[ARG0]] : memref to !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> -// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index -// CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MIN_SVL_B:.*]] = arith.constant 16 : index -// CHECK-DAG: %[[PTRUE_ALL:.*]] = arith.constant dense : vector<[16]xi1> -// CHECK-DAG: %[[VSCALE:.*]] = vector.vscale -// CHECK-NEXT: %[[SVL_B:.*]] = arith.muli %[[VSCALE]], %[[MIN_SVL_B]] : index -// CHECK-NEXT: scf.for %[[TILE_SLICE:.*]] = %[[C0]] to %[[SVL_B]] step %[[C1]] { -// CHECK-NEXT: %[[TILE_SLICE_IDX:.*]] = arith.muli %[[TILE_SLICE]], %[[SVL_B]] : index -// CHECK-NEXT: %[[TILE_SLICE_IDX_I64:.*]] = builtin.unrealized_conversion_cast %[[TILE_SLICE_IDX]] : index to i64 -// CHECK-NEXT: %[[ALIGNED_BASE:.*]] = llvm.extractvalue %[[MEM_DESC]][1] : !llvm.struct<(ptr, ptr, i64, array<1 x i64>, array<1 x i64>)> -// CHECK-NEXT: %[[GEP:.*]] = llvm.getelementptr %[[ALIGNED_BASE]]{{\[}}%[[TILE_SLICE_IDX_I64]]] : (!llvm.ptr, i64) -> !llvm.ptr, i8 -// CHECK-NEXT: %[[TILE_SLICE_I32:.*]] = arith.index_castui %[[TILE_SLICE]] : index to i32 -// CHECK-NEXT: "arm_sme.intr.ld1b.horiz"(%[[PTRUE_ALL]], %[[GEP]], %[[TILE_SLICE_I32]]) <{tile_id = 0 : i32}> : (vector<[16]xi1>, !llvm.ptr, i32) -> () -// CHECK-NEXT: } -func.func @vector_load_i8_from_rank_1_memref(%arg0 : memref) -> vector<[16]x[16]xi8> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0] : memref, vector<[16]x[16]xi8> - return %tile : vector<[16]x[16]xi8> -} - - -// ----- - -// CHECK-LABEL: @vector_load_i16( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_H:.*]] = arith.constant 8 : index -// CHECK: %[[SVL_H:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_H]] : index -// CHECK: arm_sme.intr.ld1h.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_i16(%arg0 : memref) -> vector<[8]x[8]xi16> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[8]x[8]xi16> - return %tile : vector<[8]x[8]xi16> -} - -// ----- - -// CHECK-LABEL: @vector_load_i32( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_S:.*]] = arith.constant 4 : index -// CHECK: %[[SVL_S:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_S]] : index -// CHECK: arm_sme.intr.ld1w.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_i32(%arg0 : memref) -> vector<[4]x[4]xi32> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[4]x[4]xi32> - return %tile : vector<[4]x[4]xi32> -} - -// ----- - -// CHECK-LABEL: @vector_load_i64( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_D:.*]] = arith.constant 2 : index -// CHECK: %[[SVL_D:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_D]] : index -// CHECK: arm_sme.intr.ld1d.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_i64(%arg0 : memref) -> vector<[2]x[2]xi64> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[2]x[2]xi64> - return %tile : vector<[2]x[2]xi64> -} - -// ----- - -// CHECK-LABEL: @vector_load_f16( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_H:.*]] = arith.constant 8 : index -// CHECK: %[[SVL_H:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_H]] : index -// CHECK: arm_sme.intr.ld1h.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_f16(%arg0 : memref) -> vector<[8]x[8]xf16> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[8]x[8]xf16> - return %tile : vector<[8]x[8]xf16> -} - -// ----- - -// CHECK-LABEL: @vector_load_bf16( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_H:.*]] = arith.constant 8 : index -// CHECK: %[[SVL_H:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_H]] : index -// CHECK: arm_sme.intr.ld1h.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_bf16(%arg0 : memref) -> vector<[8]x[8]xbf16> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[8]x[8]xbf16> - return %tile : vector<[8]x[8]xbf16> -} - -// ----- - -// CHECK-LABEL: @vector_load_f32( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_S:.*]] = arith.constant 4 : index -// CHECK: %[[SVL_S:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_S]] : index -// CHECK: arm_sme.intr.ld1w.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_f32(%arg0 : memref) -> vector<[4]x[4]xf32> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[4]x[4]xf32> - return %tile : vector<[4]x[4]xf32> -} - -// ----- - -// CHECK-LABEL: @vector_load_f64( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MIN_SVL_D:.*]] = arith.constant 2 : index -// CHECK: %[[SVL_D:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_D]] : index -// CHECK: arm_sme.intr.ld1d.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_f64(%arg0 : memref) -> vector<[2]x[2]xf64> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[2]x[2]xf64> - return %tile : vector<[2]x[2]xf64> -} - -// ----- - -// CHECK-LABEL: @vector_load_i128( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: arm_sme.intr.ld1q.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_load_i128(%arg0 : memref) -> vector<[1]x[1]xi128> { - %c0 = arith.constant 0 : index - %tile = vector.load %arg0[%c0, %c0] : memref, vector<[1]x[1]xi128> - return %tile : vector<[1]x[1]xi128> -} - -//===----------------------------------------------------------------------===// -// vector.store -//===----------------------------------------------------------------------===// - -// ----- - -// CHECK-LABEL: @vector_store_i8( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK-DAG: %[[MEM_DESC:.*]] = builtin.unrealized_conversion_cast %[[ARG0]] : memref to !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-DAG: %[[C0:.*]] = arith.constant 0 : index -// CHECK-DAG: %[[C1:.*]] = arith.constant 1 : index -// CHECK-DAG: %[[MIN_SVL_B:.*]] = arith.constant 16 : index -// CHECK-DAG: %[[C0_I64:.*]] = builtin.unrealized_conversion_cast %[[C0]] : index to i64 -// CHECK-DAG: %[[PTRUE_ALL:.*]] = arith.constant dense : vector<[16]xi1> -// CHECK-DAG: %[[VSCALE:.*]] = vector.vscale -// CHECK-NEXT: %[[SVL_B:.*]] = arith.muli %[[VSCALE]], %[[MIN_SVL_B]] : index -// CHECK-NEXT: scf.for %[[TILE_SLICE:.*]] = %[[C0]] to %[[SVL_B]] step %[[C1]] { -// CHECK: %[[TILE_SLICE_I64:.*]] = builtin.unrealized_conversion_cast %[[TILE_SLICE]] : index to i64 -// CHECK-NEXT: %[[ALIGNED_BASE:.*]] = llvm.extractvalue %[[MEM_DESC]][1] : !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-NEXT: %[[STRIDE0:.*]] = llvm.extractvalue %[[MEM_DESC]][4, 0] : !llvm.struct<(ptr, ptr, i64, array<2 x i64>, array<2 x i64>)> -// CHECK-NEXT: %[[OFF0:.*]] = llvm.mul %[[TILE_SLICE_I64]], %[[STRIDE0]] : i64 -// CHECK-NEXT: %[[OFF1:.*]] = llvm.add %[[OFF0]], %[[C0_I64]] : i64 -// CHECK-NEXT: %[[GEP:.*]] = llvm.getelementptr %[[ALIGNED_BASE]]{{\[}}%[[OFF1]]] : (!llvm.ptr, i64) -> !llvm.ptr, i8 -// CHECK-NEXT: %[[TILE_SLICE_I32:.*]] = arith.index_castui %[[TILE_SLICE]] : index to i32 -// CHECK-NEXT: "arm_sme.intr.st1b.horiz"(%[[PTRUE_ALL]], %[[GEP]], %[[TILE_SLICE_I32]]) <{tile_id = 0 : i32}> : (vector<[16]xi1>, !llvm.ptr, i32) -> () -// CHECK-NEXT: } -// CHECK-NEXT: return -func.func @vector_store_i8(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[16]x[16]xi8> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[16]x[16]xi8> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_i16( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_H:.*]] = arith.constant 8 : index -// CHECK: %[[SVL_H:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_H]] : index -// CHECK: arm_sme.intr.st1h.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_i16(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[8]x[8]xi16> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[8]x[8]xi16> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_i32( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_S:.*]] = arith.constant 4 : index -// CHECK: %[[SVL_S:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_S]] : index -// CHECK: arm_sme.intr.st1w.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_i32(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[4]x[4]xi32> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[4]x[4]xi32> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_i64( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_D:.*]] = arith.constant 2 : index -// CHECK: %[[SVL_D:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_D]] : index -// CHECK: arm_sme.intr.st1d.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_i64(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[2]x[2]xi64> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[2]x[2]xi64> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_f16( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_H:.*]] = arith.constant 8 : index -// CHECK: %[[SVL_H:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_H]] : index -// CHECK: arm_sme.intr.st1h.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_f16(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[8]x[8]xf16> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[8]x[8]xf16> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_bf16( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_H:.*]] = arith.constant 8 : index -// CHECK: %[[SVL_H:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_H]] : index -// CHECK: arm_sme.intr.st1h.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_bf16(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[8]x[8]xbf16> - return -} -// ----- - -// CHECK-LABEL: @vector_store_f32( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_S:.*]] = arith.constant 4 : index -// CHECK: %[[SVL_S:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_S]] : index -// CHECK: arm_sme.intr.st1w.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_f32(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[4]x[4]xf32> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[4]x[4]xf32> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_f64( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: %[[MIN_SVL_D:.*]] = arith.constant 2 : index -// CHECK: %[[SVL_D:.*]] = arith.muli %{{.*}}, %[[MIN_SVL_D]] : index -// CHECK: arm_sme.intr.st1d.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_f64(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[2]x[2]xf64> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[2]x[2]xf64> - return -} - -// ----- - -// CHECK-LABEL: @vector_store_i128( -// CHECK-SAME: %[[ARG0:.*]]: memref) -// CHECK: arm_sme.intr.st1q.horiz -// CHECK-SAME: tile_id = 0 -func.func @vector_store_i128(%arg0 : memref) { - %c0 = arith.constant 0 : index - %tile = arm_sme.get_tile : vector<[1]x[1]xi128> - vector.store %tile, %arg0[%c0, %c0] : memref, vector<[1]x[1]xi128> - return -} - -//===----------------------------------------------------------------------===// -// vector.outerproduct -//===----------------------------------------------------------------------===// - -// ----- - -// CHECK-LABEL: @vector_outerproduct_add_f16 -// CHECK-SAME: (%[[LHS:.*]]: vector<[8]xf16>, %[[RHS:.*]]: vector<[8]xf16>) -func.func @vector_outerproduct_add_f16(%lhs : vector<[8]xf16>, %rhs : vector<[8]xf16>) { - // CHECK: %[[PTRUE_ALL:.*]] = arith.constant dense : vector<[8]xi1> - // CHECK: "arm_sme.intr.mopa"(%[[PTRUE_ALL]], %[[PTRUE_ALL]], %[[LHS]], %[[RHS]]) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xf16>, vector<[8]xf16>) - %acc = arm_sme.get_tile : vector<[8]x[8]xf16> - %0 = vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[8]xf16>, vector<[8]xf16> - "prevent.dce"(%0) : (vector<[8]x[8]xf16>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_add_bf16 -func.func @vector_outerproduct_add_bf16(%lhs : vector<[8]xbf16>, %rhs : vector<[8]xbf16>) { - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xbf16>, vector<[8]xbf16>) - %acc = arm_sme.get_tile : vector<[8]x[8]xbf16> - %0 = vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[8]xbf16>, vector<[8]xbf16> - "prevent.dce"(%0) : (vector<[8]x[8]xbf16>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_add_f32 -func.func @vector_outerproduct_add_f32(%lhs : vector<[4]xf32>, %rhs : vector<[4]xf32>) { - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[4]xi1>, vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>) - %acc = arm_sme.get_tile : vector<[4]x[4]xf32> - %0 = vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[4]xf32>, vector<[4]xf32> - "prevent.dce"(%0) : (vector<[4]x[4]xf32>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_add_f64 -func.func @vector_outerproduct_add_f64(%lhs : vector<[2]xf64>, %rhs : vector<[2]xf64>) { - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xi1>, vector<[2]xi1>, vector<[2]xf64>, vector<[2]xf64>) - %acc = arm_sme.get_tile : vector<[2]x[2]xf64> - %0 = vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[2]xf64>, vector<[2]xf64> - "prevent.dce"(%0) : (vector<[2]x[2]xf64>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_no_accumulator -func.func @vector_outerproduct_no_accumulator(%lhs : vector<[2]xf64>, %rhs : vector<[2]xf64>) { - // CHECK: "arm_sme.intr.zero"() <{tile_mask = 1 : i32}> : () -> () - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xi1>, vector<[2]xi1>, vector<[2]xf64>, vector<[2]xf64>) - %0 = vector.outerproduct %lhs, %rhs {kind = #vector.kind} : vector<[2]xf64>, vector<[2]xf64> - "prevent.dce"(%0) : (vector<[2]x[2]xf64>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_masked_f32 -// CHECK-SAME: (%[[LHS:.*]]: vector<[4]xf32>, %[[RHS:.*]]: vector<[4]xf32>, %[[DIM0:.*]]: index, %[[DIM1:.*]]: index -func.func @vector_outerproduct_masked_f32(%lhs : vector<[4]xf32>, %rhs : vector<[4]xf32>, %dim0 : index, %dim1 : index) { - // CHECK: %[[LHS_MASK:.*]] = vector.create_mask %[[DIM0]] : vector<[4]xi1> - // CHECK: %[[RHS_MASK:.*]] = vector.create_mask %[[DIM1]] : vector<[4]xi1> - // CHECK: "arm_sme.intr.mopa"(%[[LHS_MASK]], %[[RHS_MASK]], %[[LHS]], %[[RHS]]) <{tile_id = 0 : i32}> : (vector<[4]xi1>, vector<[4]xi1>, vector<[4]xf32>, vector<[4]xf32>) - %acc = arm_sme.get_tile : vector<[4]x[4]xf32> - %mask = vector.create_mask %dim0, %dim1 : vector<[4]x[4]xi1> - %result = vector.mask %mask { vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[4]xf32>, vector<[4]xf32> } : vector<[4]x[4]xi1> -> vector<[4]x[4]xf32> - "prevent.dce"(%result) : (vector<[4]x[4]xf32>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_masked_f16 -// CHECK-SAME: (%[[LHS:.*]]: vector<[8]xf16>, %[[RHS:.*]]: vector<[8]xf16>, -func.func @vector_outerproduct_masked_f16(%lhs : vector<[8]xf16>, %rhs : vector<[8]xf16>, %dim0 : index, %dim1 : index) { - // CHECK: vector.create_mask {{.*}} : vector<[8]xi1> - // CHECK: vector.create_mask {{.*}} : vector<[8]xi1> - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xf16>, vector<[8]xf16>) - %acc = arm_sme.get_tile : vector<[8]x[8]xf16> - %mask = vector.create_mask %dim0, %dim1 : vector<[8]x[8]xi1> - %result = vector.mask %mask { vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[8]xf16>, vector<[8]xf16> } : vector<[8]x[8]xi1> -> vector<[8]x[8]xf16> - "prevent.dce"(%result) : (vector<[8]x[8]xf16>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_masked_bf16 -// CHECK-SAME: (%[[LHS:.*]]: vector<[8]xbf16>, %[[RHS:.*]]: vector<[8]xbf16> -func.func @vector_outerproduct_masked_bf16(%lhs : vector<[8]xbf16>, %rhs : vector<[8]xbf16>, %dim0 : index, %dim1 : index) { - // CHECK: vector.create_mask {{.*}} : vector<[8]xi1> - // CHECK: vector.create_mask {{.*}} : vector<[8]xi1> - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi1>, vector<[8]xi1>, vector<[8]xbf16>, vector<[8]xbf16>) - %acc = arm_sme.get_tile : vector<[8]x[8]xbf16> - %mask = vector.create_mask %dim0, %dim1 : vector<[8]x[8]xi1> - %result = vector.mask %mask { vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[8]xbf16>, vector<[8]xbf16> } : vector<[8]x[8]xi1> -> vector<[8]x[8]xbf16> - "prevent.dce"(%result) : (vector<[8]x[8]xbf16>) -> () -} - -// ----- - -// CHECK-LABEL: @vector_outerproduct_masked_f64 -// CHECK-SAME: (%[[LHS:.*]]: vector<[2]xf64>, %[[RHS:.*]]: vector<[2]xf64>, -func.func @vector_outerproduct_masked_f64(%lhs : vector<[2]xf64>, %rhs : vector<[2]xf64>, %dim0 : index, %dim1 : index) { - // CHECK: vector.create_mask {{.*}} : vector<[2]xi1> - // CHECK: vector.create_mask {{.*}} : vector<[2]xi1> - // CHECK: "arm_sme.intr.mopa"({{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xi1>, vector<[2]xi1>, vector<[2]xf64>, vector<[2]xf64>) - %acc = arm_sme.get_tile : vector<[2]x[2]xf64> - %mask = vector.create_mask %dim0, %dim1 : vector<[2]x[2]xi1> - %result = vector.mask %mask { vector.outerproduct %lhs, %rhs, %acc {kind = #vector.kind} : vector<[2]xf64>, vector<[2]xf64> } : vector<[2]x[2]xi1> -> vector<[2]x[2]xf64> - "prevent.dce"(%result) : (vector<[2]x[2]xf64>) -> () -} - -//===----------------------------------------------------------------------===// -// vector.insert -//===----------------------------------------------------------------------===// - -// ----- - -// CHECK-LABEL: @vector_insert_slice_i32( -// CHECK-SAME: %[[SLICE:.*]]: vector<[4]xi32>, -// CHECK-SAME: %[[INDEX:.*]]: index) -func.func @vector_insert_slice_i32(%slice: vector<[4]xi32>, %row: index) -> vector<[4]x[4]xi32>{ - // CHECK-NEXT: %[[PTRUE:.*]] = arith.constant dense : vector<[4]xi1> - // CHECK: %[[TILE_SLICE_INDEX:.*]] = arith.index_castui %[[INDEX]] : index to i32 - // CHECK-NEXT: "arm_sme.intr.write.horiz"(%[[TILE_SLICE_INDEX]], %[[PTRUE]], %[[SLICE]]) <{tile_id = 0 : i32}> : (i32, vector<[4]xi1>, vector<[4]xi32>) -> () - %tile = arm_sme.get_tile : vector<[4]x[4]xi32> - %new_tile = vector.insert %slice, %tile[%row] : vector<[4]xi32> into vector<[4]x[4]xi32> - return %new_tile : vector<[4]x[4]xi32> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_i8 -func.func @vector_insert_slice_i8(%slice: vector<[16]xi8>, %row: index) -> vector<[16]x[16]xi8> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[16]xi1>, vector<[16]xi8>) -> () - %tile = arm_sme.get_tile : vector<[16]x[16]xi8> - %new_tile = vector.insert %slice, %tile[%row] : vector<[16]xi8> into vector<[16]x[16]xi8> - return %new_tile : vector<[16]x[16]xi8> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_i16 -func.func @vector_insert_slice_i16(%slice: vector<[8]xi16>, %row: index) -> vector<[8]x[8]xi16> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[8]xi1>, vector<[8]xi16>) -> () - %tile = arm_sme.get_tile : vector<[8]x[8]xi16> - %new_tile = vector.insert %slice, %tile[%row] : vector<[8]xi16> into vector<[8]x[8]xi16> - return %new_tile : vector<[8]x[8]xi16> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_i64 -func.func @vector_insert_slice_i64(%slice: vector<[2]xi64>, %row: index) -> vector<[2]x[2]xi64> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[2]xi1>, vector<[2]xi64>) -> () - %tile = arm_sme.get_tile : vector<[2]x[2]xi64> - %new_tile = vector.insert %slice, %tile[%row] : vector<[2]xi64> into vector<[2]x[2]xi64> - return %new_tile : vector<[2]x[2]xi64> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_i128 -func.func @vector_insert_slice_i128(%slice: vector<[1]xi128>, %row: index) -> vector<[1]x[1]xi128> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[1]xi1>, vector<[1]xi128>) -> () - %tile = arm_sme.get_tile : vector<[1]x[1]xi128> - %new_tile = vector.insert %slice, %tile[%row] : vector<[1]xi128> into vector<[1]x[1]xi128> - return %new_tile : vector<[1]x[1]xi128> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_f16 -func.func @vector_insert_slice_f16(%slice: vector<[8]xf16>, %row: index) -> vector<[8]x[8]xf16> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[8]xi1>, vector<[8]xf16>) -> () - %tile = arm_sme.get_tile : vector<[8]x[8]xf16> - %new_tile = vector.insert %slice, %tile[%row] : vector<[8]xf16> into vector<[8]x[8]xf16> - return %new_tile : vector<[8]x[8]xf16> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_bf16 -func.func @vector_insert_slice_bf16(%slice: vector<[8]xbf16>, %row: index) -> vector<[8]x[8]xbf16> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[8]xi1>, vector<[8]xbf16>) -> () - %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> - %new_tile = vector.insert %slice, %tile[%row] : vector<[8]xbf16> into vector<[8]x[8]xbf16> - return %new_tile : vector<[8]x[8]xbf16> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_f32 -func.func @vector_insert_slice_f32(%slice: vector<[4]xf32>, %row: index) -> vector<[4]x[4]xf32> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[4]xi1>, vector<[4]xf32>) -> () - %tile = arm_sme.get_tile : vector<[4]x[4]xf32> - %new_tile = vector.insert %slice, %tile[%row] : vector<[4]xf32> into vector<[4]x[4]xf32> - return %new_tile : vector<[4]x[4]xf32> -} - -// ----- - -// CHECK-LABEL: @vector_insert_slice_f64 -func.func @vector_insert_slice_f64(%slice: vector<[2]xf64>, %row: index) -> vector<[2]x[2]xf64> { - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[2]xi1>, vector<[2]xf64>) -> () - %tile = arm_sme.get_tile : vector<[2]x[2]xf64> - %new_tile = vector.insert %slice, %tile[%row] : vector<[2]xf64> into vector<[2]x[2]xf64> - return %new_tile : vector<[2]x[2]xf64> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_i32( -// CHECK-SAME: %[[EL:.*]]: i32, -// CHECK-SAME: %[[ROW:.*]]: index, -// CHECK-SAME: %[[COL:.*]]: index) -func.func @vector_insert_element_i32(%el: i32, %row: index, %col: index) -> vector<[4]x[4]xi32> { - // CHECK-DAG: %[[ZERO_VEC:.*]] = arith.constant dense<0> : vector<[4]xi32> - // CHECK-DAG: %[[PTRUE:.*]] = arith.constant dense : vector<[4]xi1> - // CHECK-DAG: %[[ROW_I32:.*]] = arith.index_cast %[[ROW]] : index to i32 - // CHECK-NEXT: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%[[ZERO_VEC]], %[[PTRUE]], %[[ROW_I32]]) <{tile_id = 0 : i32}> : (vector<[4]xi32>, vector<[4]xi1>, i32) -> vector<[4]xi32> - // CHECK-NEXT: %[[NEW_SLICE:.*]] = vector.insert %[[EL]], %[[SLICE]] [%[[COL]]] : i32 into vector<[4]xi32> - // CHECK-NEXT: %[[SLICE_INDEX:.*]] = arith.index_castui %[[ROW]] : index to i32 - // CHECK-NEXT: "arm_sme.intr.write.horiz"(%[[SLICE_INDEX]], %[[PTRUE]], %[[NEW_SLICE]]) <{tile_id = 0 : i32}> : (i32, vector<[4]xi1>, vector<[4]xi32>) -> () - %tile = arm_sme.get_tile : vector<[4]x[4]xi32> - %new_tile = vector.insert %el, %tile[%row, %col] : i32 into vector<[4]x[4]xi32> - return %new_tile : vector<[4]x[4]xi32> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_i8 -func.func @vector_insert_element_i8(%el: i8, %row: index, %col: index) -> vector<[16]x[16]xi8> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi8>, vector<[16]xi1>, i32) -> vector<[16]xi8> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[16]xi1>, vector<[16]xi8>) -> () - %tile = arm_sme.get_tile : vector<[16]x[16]xi8> - %new_tile = vector.insert %el, %tile[%row, %col] : i8 into vector<[16]x[16]xi8> - return %new_tile : vector<[16]x[16]xi8> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_i16 -func.func @vector_insert_element_i16(%el: i16, %row: index, %col: index) -> vector<[8]x[8]xi16> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi16>, vector<[8]xi1>, i32) -> vector<[8]xi16> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[8]xi1>, vector<[8]xi16>) -> () - %tile = arm_sme.get_tile : vector<[8]x[8]xi16> - %new_tile = vector.insert %el, %tile[%row, %col] : i16 into vector<[8]x[8]xi16> - return %new_tile : vector<[8]x[8]xi16> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_i64 -func.func @vector_insert_element_i64(%el: i64, %row: index, %col: index) -> vector<[2]x[2]xi64> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xi64>, vector<[2]xi1>, i32) -> vector<[2]xi64> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[2]xi1>, vector<[2]xi64>) -> () - %tile = arm_sme.get_tile : vector<[2]x[2]xi64> - %new_tile = vector.insert %el, %tile[%row, %col] : i64 into vector<[2]x[2]xi64> - return %new_tile : vector<[2]x[2]xi64> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_i128 -func.func @vector_insert_element_i128(%el: i128, %row: index, %col: index) -> vector<[1]x[1]xi128> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[1]xi128>, vector<[1]xi1>, i32) -> vector<[1]xi128> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[1]xi1>, vector<[1]xi128>) -> () - %tile = arm_sme.get_tile : vector<[1]x[1]xi128> - %new_tile = vector.insert %el, %tile[%row, %col] : i128 into vector<[1]x[1]xi128> - return %new_tile : vector<[1]x[1]xi128> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_f16 -func.func @vector_insert_element_f16(%el: f16, %row: index, %col: index) -> vector<[8]x[8]xf16> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xf16>, vector<[8]xi1>, i32) -> vector<[8]xf16> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[8]xi1>, vector<[8]xf16>) -> () - %tile = arm_sme.get_tile : vector<[8]x[8]xf16> - %new_tile = vector.insert %el, %tile[%row, %col] : f16 into vector<[8]x[8]xf16> - return %new_tile : vector<[8]x[8]xf16> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_bf16 -func.func @vector_insert_element_bf16(%el: bf16, %row: index, %col: index) -> vector<[8]x[8]xbf16> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xbf16>, vector<[8]xi1>, i32) -> vector<[8]xbf16> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[8]xi1>, vector<[8]xbf16>) -> () - %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> - %new_tile = vector.insert %el, %tile[%row, %col] : bf16 into vector<[8]x[8]xbf16> - return %new_tile : vector<[8]x[8]xbf16> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_f32 -func.func @vector_insert_element_f32(%el: f32, %row: index, %col: index) -> vector<[4]x[4]xf32> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[4]xf32>, vector<[4]xi1>, i32) -> vector<[4]xf32> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[4]xi1>, vector<[4]xf32>) -> () - %tile = arm_sme.get_tile : vector<[4]x[4]xf32> - %new_tile = vector.insert %el, %tile[%row, %col] : f32 into vector<[4]x[4]xf32> - return %new_tile : vector<[4]x[4]xf32> -} - -// ----- - -// CHECK-LABEL: @vector_insert_element_f64 -func.func @vector_insert_element_f64(%el: f64, %row: index, %col: index) -> vector<[2]x[2]xf64> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xf64>, vector<[2]xi1>, i32) -> vector<[2]xf64> - // CHECK: "arm_sme.intr.write.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (i32, vector<[2]xi1>, vector<[2]xf64>) -> () - %tile = arm_sme.get_tile : vector<[2]x[2]xf64> - %new_tile = vector.insert %el, %tile[%row, %col] : f64 into vector<[2]x[2]xf64> - return %new_tile : vector<[2]x[2]xf64> -} - -//===----------------------------------------------------------------------===// -// vector.extract -//===----------------------------------------------------------------------===// - -// ----- - -// CHECK-LABEL: @vector_extract_slice_i32( -// CHECK-SAME: %[[INDEX:.*]]: index) -func.func @vector_extract_slice_i32(%row: index) -> vector<[4]xi32> { - // CHECK-NEXT: %[[PTRUE:.*]] = arith.constant dense : vector<[4]xi1> - // CHECK-NEXT: %[[ZERO_VEC:.*]] = arith.constant dense<0> : vector<[4]xi32> - // CHECK-NEXT: %[[TILE_SLICE_INDEX:.*]] = arith.index_cast %[[INDEX]] : index to i32 - // CHECK-NEXT: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%[[ZERO_VEC]], %[[PTRUE]], %[[TILE_SLICE_INDEX]]) <{tile_id = 0 : i32}> : (vector<[4]xi32>, vector<[4]xi1>, i32) -> vector<[4]xi32> - %tile = arm_sme.get_tile : vector<[4]x[4]xi32> - %slice = vector.extract %tile[%row] : vector<[4]xi32> from vector<[4]x[4]xi32> - return %slice : vector<[4]xi32> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_i8 -func.func @vector_extract_slice_i8(%row: index) -> vector<[16]xi8> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi8>, vector<[16]xi1>, i32) -> vector<[16]xi8> - %tile = arm_sme.get_tile : vector<[16]x[16]xi8> - %slice = vector.extract %tile[%row] : vector<[16]xi8> from vector<[16]x[16]xi8> - return %slice : vector<[16]xi8> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_i16 -func.func @vector_extract_slice_i16(%row: index) -> vector<[8]xi16> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi16>, vector<[8]xi1>, i32) -> vector<[8]xi16> - %tile = arm_sme.get_tile : vector<[8]x[8]xi16> - %slice = vector.extract %tile[%row] : vector<[8]xi16> from vector<[8]x[8]xi16> - return %slice : vector<[8]xi16> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_i64 -func.func @vector_extract_slice_i64(%row: index) -> vector<[2]xi64> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xi64>, vector<[2]xi1>, i32) -> vector<[2]xi64> - %tile = arm_sme.get_tile : vector<[2]x[2]xi64> - %slice = vector.extract %tile[%row] : vector<[2]xi64> from vector<[2]x[2]xi64> - return %slice : vector<[2]xi64> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_i128 -func.func @vector_extract_slice_i128(%row: index) -> vector<[1]xi128> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[1]xi128>, vector<[1]xi1>, i32) -> vector<[1]xi128> - %tile = arm_sme.get_tile : vector<[1]x[1]xi128> - %slice = vector.extract %tile[%row] : vector<[1]xi128> from vector<[1]x[1]xi128> - return %slice : vector<[1]xi128> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_f16 -func.func @vector_extract_slice_f16(%row: index) -> vector<[8]xf16> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xf16>, vector<[8]xi1>, i32) -> vector<[8]xf16> - %tile = arm_sme.get_tile : vector<[8]x[8]xf16> - %slice = vector.extract %tile[%row] : vector<[8]xf16> from vector<[8]x[8]xf16> - return %slice : vector<[8]xf16> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_bf16 -func.func @vector_extract_slice_bf16(%row: index) -> vector<[8]xbf16> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xbf16>, vector<[8]xi1>, i32) -> vector<[8]xbf16> - %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> - %slice = vector.extract %tile[%row] : vector<[8]xbf16> from vector<[8]x[8]xbf16> - return %slice : vector<[8]xbf16> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_f32 -func.func @vector_extract_slice_f32(%row: index) -> vector<[4]xf32> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[4]xf32>, vector<[4]xi1>, i32) -> vector<[4]xf32> - %tile = arm_sme.get_tile : vector<[4]x[4]xf32> - %slice = vector.extract %tile[%row] : vector<[4]xf32> from vector<[4]x[4]xf32> - return %slice : vector<[4]xf32> -} - -// ----- - -// CHECK-LABEL: @vector_extract_slice_f64 -func.func @vector_extract_slice_f64(%row: index) -> vector<[2]xf64> { - // CHECK: %{{.*}} = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xf64>, vector<[2]xi1>, i32) -> vector<[2]xf64> - %tile = arm_sme.get_tile : vector<[2]x[2]xf64> - %slice = vector.extract %tile[%row] : vector<[2]xf64> from vector<[2]x[2]xf64> - return %slice : vector<[2]xf64> -} - -// ----- - -// CHECK-LABEL: @vector_extract_element( -// CHECK-SAME: %[[ROW:.*]]: index, -// CHECK-SAME: %[[COL:.*]]: index) -func.func @vector_extract_element(%row: index, %col: index) -> i32 { - // CHECK-NEXT: %[[PTRUE:.*]] = arith.constant dense : vector<[4]xi1> - // CHECK-NEXT: %[[ZERO_VEC:.*]] = arith.constant dense<0> : vector<[4]xi32> - // CHECK-NEXT: %[[ROW_I32:.*]] = arith.index_cast %[[ROW]] : index to i32 - // CHECK-NEXT: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%[[ZERO_VEC]], %[[PTRUE]], %[[ROW_I32]]) <{tile_id = 0 : i32}> : (vector<[4]xi32>, vector<[4]xi1>, i32) -> vector<[4]xi32> - // CHECK-NEXT: %[[EL:.*]] = vector.extract %[[SLICE]]{{\[}}%[[COL]]] : i32 from vector<[4]xi32> - %tile = arm_sme.get_tile : vector<[4]x[4]xi32> - %el = vector.extract %tile[%row, %col] : i32 from vector<[4]x[4]xi32> - return %el : i32 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_i8 -func.func @vector_extract_element_i8(%row: index, %col: index) -> i8 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[16]xi8>, vector<[16]xi1>, i32) -> vector<[16]xi8> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i8 from vector<[16]xi8> - %tile = arm_sme.get_tile : vector<[16]x[16]xi8> - %el = vector.extract %tile[%row, %col] : i8 from vector<[16]x[16]xi8> - return %el : i8 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_i16 -func.func @vector_extract_element_i16(%row: index, %col: index) -> i16 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xi16>, vector<[8]xi1>, i32) -> vector<[8]xi16> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i16 from vector<[8]xi16> - %tile = arm_sme.get_tile : vector<[8]x[8]xi16> - %el = vector.extract %tile[%row, %col] : i16 from vector<[8]x[8]xi16> - return %el : i16 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_i64 -func.func @vector_extract_element_i64(%row: index, %col: index) -> i64 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xi64>, vector<[2]xi1>, i32) -> vector<[2]xi64> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i64 from vector<[2]xi64> - %tile = arm_sme.get_tile : vector<[2]x[2]xi64> - %el = vector.extract %tile[%row, %col] : i64 from vector<[2]x[2]xi64> - return %el : i64 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_i128 -func.func @vector_extract_element_i128(%row: index, %col: index) -> i128 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[1]xi128>, vector<[1]xi1>, i32) -> vector<[1]xi128> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : i128 from vector<[1]xi128> - %tile = arm_sme.get_tile : vector<[1]x[1]xi128> - %el = vector.extract %tile[%row, %col] : i128 from vector<[1]x[1]xi128> - return %el : i128 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_f16 -func.func @vector_extract_element_f16(%row: index, %col: index) -> f16 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xf16>, vector<[8]xi1>, i32) -> vector<[8]xf16> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : f16 from vector<[8]xf16> - %tile = arm_sme.get_tile : vector<[8]x[8]xf16> - %el = vector.extract %tile[%row, %col] : f16 from vector<[8]x[8]xf16> - return %el : f16 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_bf16 -func.func @vector_extract_element_bf16(%row: index, %col: index) -> bf16 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[8]xbf16>, vector<[8]xi1>, i32) -> vector<[8]xbf16> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : bf16 from vector<[8]xbf16> - %tile = arm_sme.get_tile : vector<[8]x[8]xbf16> - %el = vector.extract %tile[%row, %col] : bf16 from vector<[8]x[8]xbf16> - return %el : bf16 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_f32 -func.func @vector_extract_element_f32(%row: index, %col: index) -> f32 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[4]xf32>, vector<[4]xi1>, i32) -> vector<[4]xf32> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : f32 from vector<[4]xf32> - %tile = arm_sme.get_tile : vector<[4]x[4]xf32> - %el = vector.extract %tile[%row, %col] : f32 from vector<[4]x[4]xf32> - return %el : f32 -} - -// ----- - -// CHECK-LABEL: @vector_extract_element_f64 -func.func @vector_extract_element_f64(%row: index, %col: index) -> f64 { - // CHECK: %[[SLICE:.*]] = "arm_sme.intr.read.horiz"(%{{.*}}) <{tile_id = 0 : i32}> : (vector<[2]xf64>, vector<[2]xi1>, i32) -> vector<[2]xf64> - // CHECK-NEXT: %{{.*}} = vector.extract %[[SLICE]]{{\[}}%{{.*}}] : f64 from vector<[2]xf64> - %tile = arm_sme.get_tile : vector<[2]x[2]xf64> - %el = vector.extract %tile[%row, %col] : f64 from vector<[2]x[2]xf64> - return %el : f64 -} diff --git a/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir b/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir index 37720e98d92a9e85a34b7f387e11680aaf781343..b1b06740f194422ee4a50c96cd0024949f13a4df 100644 --- a/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir +++ b/mlir/test/Dialect/LLVMIR/legalize-for-export.mlir @@ -32,14 +32,17 @@ llvm.func @repeated_successor_no_args(%arg0: i1) { // CHECK: @repeated_successor_openmp llvm.func @repeated_successor_openmp(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) { - omp.wsloop for (%arg4) : i64 = (%arg0) to (%arg1) step (%arg2) { - // CHECK: llvm.cond_br %{{.*}}, ^[[BB1:.*]]({{.*}}), ^[[BB2:.*]]({{.*}}) - llvm.cond_br %arg3, ^bb1(%arg0 : i64), ^bb1(%arg1 : i64) - // CHECK: ^[[BB1]] - ^bb1(%0: i64): // 2 preds: ^bb0, ^bb0 - omp.yield - // CHECK: ^[[BB2]](%[[ARG:.*]]: i64): - // CHECK: llvm.br ^[[BB1]](%[[ARG]] : i64) + omp.wsloop { + omp.loop_nest (%arg4) : i64 = (%arg0) to (%arg1) step (%arg2) { + // CHECK: llvm.cond_br %{{.*}}, ^[[BB1:.*]]({{.*}}), ^[[BB2:.*]]({{.*}}) + llvm.cond_br %arg3, ^bb1(%arg0 : i64), ^bb1(%arg1 : i64) + // CHECK: ^[[BB1]] + ^bb1(%0: i64): // 2 preds: ^bb0, ^bb0 + omp.yield + // CHECK: ^[[BB2]](%[[ARG:.*]]: i64): + // CHECK: llvm.br ^[[BB1]](%[[ARG]] : i64) + } + omp.terminator } llvm.return } diff --git a/mlir/test/Dialect/LLVMIR/mem2reg.mlir b/mlir/test/Dialect/LLVMIR/mem2reg.mlir index 644d30f9f9f13318b47bd67abaeebb085b194617..38c836c139da622ffe4585eb84eb9533f7c8ae2e 100644 --- a/mlir/test/Dialect/LLVMIR/mem2reg.mlir +++ b/mlir/test/Dialect/LLVMIR/mem2reg.mlir @@ -856,28 +856,6 @@ llvm.func @stores_with_different_types(%arg0: i64, %arg1: f64, %cond: i1) -> f64 // ----- -// Verifies that stores with smaller bitsize inputs are not replaced. A trivial -// implementation will be incorrect due to endianness considerations. - -// CHECK-LABEL: @stores_with_different_type_sizes -llvm.func @stores_with_different_type_sizes(%arg0: i64, %arg1: f32, %cond: i1) -> f64 { - %0 = llvm.mlir.constant(1 : i32) : i32 - // CHECK: llvm.alloca - %1 = llvm.alloca %0 x i64 {alignment = 4 : i64} : (i32) -> !llvm.ptr - llvm.cond_br %cond, ^bb1, ^bb2 -^bb1: - llvm.store %arg0, %1 {alignment = 4 : i64} : i64, !llvm.ptr - llvm.br ^bb3 -^bb2: - llvm.store %arg1, %1 {alignment = 4 : i64} : f32, !llvm.ptr - llvm.br ^bb3 -^bb3: - %2 = llvm.load %1 {alignment = 4 : i64} : !llvm.ptr -> f64 - llvm.return %2 : f64 -} - -// ----- - // CHECK-LABEL: @load_smaller_int llvm.func @load_smaller_int() -> i16 { %0 = llvm.mlir.constant(1 : i32) : i32 @@ -1047,3 +1025,135 @@ llvm.func @scalable_llvm_vector() -> i16 { %2 = llvm.load %1 : !llvm.ptr -> i16 llvm.return %2 : i16 } + +// ----- + +// CHECK-LABEL: @smaller_store_forwarding +// CHECK-SAME: %[[ARG:.+]]: i16 +llvm.func @smaller_store_forwarding(%arg : i16) { + %0 = llvm.mlir.constant(1 : i32) : i32 + // CHECK-NOT: llvm.alloca + // CHECK: %[[UNDEF:.+]] = llvm.mlir.undef : i32 + %1 = llvm.alloca %0 x i32 : (i32) -> !llvm.ptr + + // CHECK: %[[ZEXT:.+]] = llvm.zext %[[ARG]] : i16 to i32 + // CHECK: %[[MASK:.+]] = llvm.mlir.constant(-65536 : i32) : i32 + // CHECK: %[[MASKED:.+]] = llvm.and %[[UNDEF]], %[[MASK]] + // CHECK: %[[NEW_DEF:.+]] = llvm.or %[[MASKED]], %[[ZEXT]] + llvm.store %arg, %1 : i16, !llvm.ptr + llvm.return +} + +// ----- + +module attributes { dlti.dl_spec = #dlti.dl_spec< + #dlti.dl_entry<"dlti.endianness", "big"> +>} { + // CHECK-LABEL: @smaller_store_forwarding_big_endian + // CHECK-SAME: %[[ARG:.+]]: i16 + llvm.func @smaller_store_forwarding_big_endian(%arg : i16) { + %0 = llvm.mlir.constant(1 : i32) : i32 + // CHECK-NOT: llvm.alloca + // CHECK: %[[UNDEF:.+]] = llvm.mlir.undef : i32 + %1 = llvm.alloca %0 x i32 : (i32) -> !llvm.ptr + + // CHECK: %[[ZEXT:.+]] = llvm.zext %[[ARG]] : i16 to i32 + // CHECK: %[[SHIFT_WIDTH:.+]] = llvm.mlir.constant(16 : i32) : i32 + // CHECK: %[[SHIFTED:.+]] = llvm.shl %[[ZEXT]], %[[SHIFT_WIDTH]] + // CHECK: %[[MASK:.+]] = llvm.mlir.constant(65535 : i32) : i32 + // CHECK: %[[MASKED:.+]] = llvm.and %[[UNDEF]], %[[MASK]] + // CHECK: %[[NEW_DEF:.+]] = llvm.or %[[MASKED]], %[[SHIFTED]] + llvm.store %arg, %1 : i16, !llvm.ptr + llvm.return + } +} + +// ----- + +// CHECK-LABEL: @smaller_store_forwarding_type_mix +// CHECK-SAME: %[[ARG:.+]]: vector<1xi8> +llvm.func @smaller_store_forwarding_type_mix(%arg : vector<1xi8>) { + %0 = llvm.mlir.constant(1 : i32) : i32 + // CHECK-NOT: llvm.alloca + // CHECK: %[[UNDEF:.+]] = llvm.mlir.undef : f32 + %1 = llvm.alloca %0 x f32 : (i32) -> !llvm.ptr + + // CHECK: %[[CASTED_DEF:.+]] = llvm.bitcast %[[UNDEF]] : f32 to i32 + // CHECK: %[[CASTED_ARG:.+]] = llvm.bitcast %[[ARG]] : vector<1xi8> to i8 + // CHECK: %[[ZEXT:.+]] = llvm.zext %[[CASTED_ARG]] : i8 to i32 + // CHECK: %[[MASK:.+]] = llvm.mlir.constant(-256 : i32) : i32 + // CHECK: %[[MASKED:.+]] = llvm.and %[[CASTED_DEF]], %[[MASK]] + // CHECK: %[[NEW_DEF:.+]] = llvm.or %[[MASKED]], %[[ZEXT]] + // CHECK: %[[CASTED_NEW_DEF:.+]] = llvm.bitcast %[[NEW_DEF]] : i32 to f32 + llvm.store %arg, %1 : vector<1xi8>, !llvm.ptr + llvm.return +} + +// ----- + +module attributes { dlti.dl_spec = #dlti.dl_spec< + #dlti.dl_entry<"dlti.endianness", "big"> +>} { + // CHECK-LABEL: @smaller_store_forwarding_type_mix + // CHECK-SAME: %[[ARG:.+]]: vector<1xi8> + llvm.func @smaller_store_forwarding_type_mix(%arg : vector<1xi8>) { + %0 = llvm.mlir.constant(1 : i32) : i32 + // CHECK-NOT: llvm.alloca + // CHECK: %[[UNDEF:.+]] = llvm.mlir.undef : f32 + %1 = llvm.alloca %0 x f32 : (i32) -> !llvm.ptr + + // CHECK: %[[CASTED_DEF:.+]] = llvm.bitcast %[[UNDEF]] : f32 to i32 + // CHECK: %[[CASTED_ARG:.+]] = llvm.bitcast %[[ARG]] : vector<1xi8> to i8 + // CHECK: %[[ZEXT:.+]] = llvm.zext %[[CASTED_ARG]] : i8 to i32 + // CHECK: %[[SHIFT_WIDTH:.+]] = llvm.mlir.constant(24 : i32) : i32 + // CHECK: %[[SHIFTED:.+]] = llvm.shl %[[ZEXT]], %[[SHIFT_WIDTH]] + // CHECK: %[[MASK:.+]] = llvm.mlir.constant(16777215 : i32) : i32 + // CHECK: %[[MASKED:.+]] = llvm.and %[[CASTED_DEF]], %[[MASK]] + // CHECK: %[[NEW_DEF:.+]] = llvm.or %[[MASKED]], %[[SHIFTED]] + // CHECK: %[[CASTED_NEW_DEF:.+]] = llvm.bitcast %[[NEW_DEF]] : i32 to f32 + llvm.store %arg, %1 : vector<1xi8>, !llvm.ptr + llvm.return + } +} + +// ----- + +// CHECK-LABEL: @stores_with_different_types_branches +// CHECK-SAME: %[[ARG0:.+]]: i64 +// CHECK-SAME: %[[ARG1:.+]]: f32 +llvm.func @stores_with_different_types_branches(%arg0: i64, %arg1: f32, %cond: i1) -> f64 { + %0 = llvm.mlir.constant(1 : i32) : i32 + // CHECK-NOT: llvm.alloca + // CHECK: %[[UNDEF:.+]] = llvm.mlir.undef : i64 + %1 = llvm.alloca %0 x i64 {alignment = 4 : i64} : (i32) -> !llvm.ptr + llvm.cond_br %cond, ^bb1, ^bb2 +^bb1: + llvm.store %arg0, %1 {alignment = 4 : i64} : i64, !llvm.ptr + // CHECK: llvm.br ^[[BB3:.+]](%[[ARG0]] : i64) + llvm.br ^bb3 +^bb2: + llvm.store %arg1, %1 {alignment = 4 : i64} : f32, !llvm.ptr + // CHECK: %[[CAST:.+]] = llvm.bitcast %[[ARG1]] : f32 to i32 + // CHECK: %[[ZEXT:.+]] = llvm.zext %[[CAST]] : i32 to i64 + // CHECK: %[[MASK:.+]] = llvm.mlir.constant(-4294967296 : i64) : i64 + // CHECK: %[[MASKED:.+]] = llvm.and %[[UNDEF]], %[[MASK]] + // CHECK: %[[NEW_DEF:.+]] = llvm.or %[[MASKED]], %[[ZEXT]] + // CHECK: llvm.br ^[[BB3]](%[[NEW_DEF]] : i64) + llvm.br ^bb3 +^bb3: + %2 = llvm.load %1 {alignment = 4 : i64} : !llvm.ptr -> f64 + llvm.return %2 : f64 +} + +// ----- + +// Verifiy that mem2reg does not touch stores with undefined semantics. + +// CHECK-LABEL: @store_out_of_bounds +llvm.func @store_out_of_bounds(%arg : i64) { + %0 = llvm.mlir.constant(1 : i32) : i32 + // CHECK: llvm.alloca + %1 = llvm.alloca %0 x i32 : (i32) -> !llvm.ptr + llvm.store %arg, %1 : i64, !llvm.ptr + llvm.return +} diff --git a/mlir/test/Dialect/OpenMP/invalid.mlir b/mlir/test/Dialect/OpenMP/invalid.mlir index 2f24dce4233e48ecce30ea1f24a5633f8e44b7c1..e329b3010017cf594846f099cd51430e5b198592 100644 --- a/mlir/test/Dialect/OpenMP/invalid.mlir +++ b/mlir/test/Dialect/OpenMP/invalid.mlir @@ -149,50 +149,74 @@ func.func @invalid_parent(%lb : index, %ub : index, %step : index) { // ----- func.func @invalid_wrapper(%lb : index, %ub : index, %step : index) { - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.parallel { %0 = arith.constant 0 : i32 // expected-error@+1 {{op expects parent op to be a valid loop wrapper}} omp.loop_nest (%iv2) : index = (%lb) to (%ub) step (%step) { omp.yield } - omp.yield + omp.terminator } } // ----- func.func @type_mismatch(%lb : index, %ub : index, %step : index) { - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // expected-error@+1 {{range argument type does not match corresponding IV type}} "omp.loop_nest" (%lb, %ub, %step) ({ ^bb0(%iv2: i32): omp.yield }) : (index, index, index) -> () - omp.yield + omp.terminator } } // ----- func.func @iv_number_mismatch(%lb : index, %ub : index, %step : index) { - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // expected-error@+1 {{number of range arguments and IVs do not match}} "omp.loop_nest" (%lb, %ub, %step) ({ ^bb0(%iv1 : index, %iv2 : index): omp.yield }) : (index, index, index) -> () - omp.yield + omp.terminator + } +} + +// ----- + +func.func @no_wrapper(%lb : index, %ub : index, %step : index) { + // expected-error @below {{op must be a loop wrapper}} + omp.wsloop { + %0 = arith.constant 0 : i32 + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } +} + +// ----- + +func.func @invalid_nested_wrapper(%lb : index, %ub : index, %step : index) { + // expected-error @below {{only supported nested wrapper is 'omp.simd'}} + omp.wsloop { + omp.distribute { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } + omp.terminator } } // ----- func.func @no_loops(%lb : index, %ub : index, %step : index) { - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // expected-error@+1 {{op must represent at least one loop}} "omp.loop_nest" () ({ ^bb0(): @@ -205,10 +229,12 @@ func.func @no_loops(%lb : index, %ub : index, %step : index) { // ----- func.func @inclusive_not_a_clause(%lb : index, %ub : index, %step : index) { - // expected-error @below {{expected 'for'}} - omp.wsloop nowait inclusive - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield + // expected-error @below {{expected '{'}} + omp.wsloop nowait inclusive { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } } @@ -216,39 +242,47 @@ func.func @inclusive_not_a_clause(%lb : index, %ub : index, %step : index) { func.func @order_value(%lb : index, %ub : index, %step : index) { // expected-error @below {{invalid clause value: 'default'}} - omp.wsloop order(default) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop order(default) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } } // ----- func.func @if_not_allowed(%lb : index, %ub : index, %step : index, %bool_var : i1) { - // expected-error @below {{expected 'for'}} - omp.wsloop if(%bool_var: i1) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield + // expected-error @below {{expected '{'}} + omp.wsloop if(%bool_var: i1) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } } // ----- func.func @num_threads_not_allowed(%lb : index, %ub : index, %step : index, %int_var : i32) { - // expected-error @below {{expected 'for'}} - omp.wsloop num_threads(%int_var: i32) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield + // expected-error @below {{expected '{'}} + omp.wsloop num_threads(%int_var: i32) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } } // ----- func.func @proc_bind_not_allowed(%lb : index, %ub : index, %step : index) { - // expected-error @below {{expected 'for'}} - omp.wsloop proc_bind(close) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield + // expected-error @below {{expected '{'}} + omp.wsloop proc_bind(close) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } } @@ -256,9 +290,11 @@ func.func @proc_bind_not_allowed(%lb : index, %ub : index, %step : index) { llvm.func @test_omp_wsloop_dynamic_bad_modifier(%lb : i64, %ub : i64, %step : i64) -> () { // expected-error @+1 {{unknown modifier type: ginandtonic}} - omp.wsloop schedule(dynamic, ginandtonic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop schedule(dynamic, ginandtonic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } llvm.return } @@ -267,9 +303,11 @@ llvm.func @test_omp_wsloop_dynamic_bad_modifier(%lb : i64, %ub : i64, %step : i6 llvm.func @test_omp_wsloop_dynamic_many_modifier(%lb : i64, %ub : i64, %step : i64) -> () { // expected-error @+1 {{unexpected modifier(s)}} - omp.wsloop schedule(dynamic, monotonic, monotonic, monotonic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop schedule(dynamic, monotonic, monotonic, monotonic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } llvm.return } @@ -278,9 +316,11 @@ llvm.func @test_omp_wsloop_dynamic_many_modifier(%lb : i64, %ub : i64, %step : i llvm.func @test_omp_wsloop_dynamic_wrong_modifier(%lb : i64, %ub : i64, %step : i64) -> () { // expected-error @+1 {{incorrect modifier order}} - omp.wsloop schedule(dynamic, simd, monotonic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop schedule(dynamic, simd, monotonic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } llvm.return } @@ -289,9 +329,11 @@ llvm.func @test_omp_wsloop_dynamic_wrong_modifier(%lb : i64, %ub : i64, %step : llvm.func @test_omp_wsloop_dynamic_wrong_modifier2(%lb : i64, %ub : i64, %step : i64) -> () { // expected-error @+1 {{incorrect modifier order}} - omp.wsloop schedule(dynamic, monotonic, monotonic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop schedule(dynamic, monotonic, monotonic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } llvm.return } @@ -300,9 +342,11 @@ llvm.func @test_omp_wsloop_dynamic_wrong_modifier2(%lb : i64, %ub : i64, %step : llvm.func @test_omp_wsloop_dynamic_wrong_modifier3(%lb : i64, %ub : i64, %step : i64) -> () { // expected-error @+1 {{incorrect modifier order}} - omp.wsloop schedule(dynamic, simd, simd) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop schedule(dynamic, simd, simd) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } llvm.return } @@ -601,11 +645,13 @@ func.func @foo(%lb : index, %ub : index, %step : index) { %1 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr // expected-error @below {{expected symbol reference @foo to point to a reduction declaration}} - omp.wsloop reduction(@foo %0 -> %prv : !llvm.ptr) - for (%iv) : index = (%lb) to (%ub) step (%step) { - %2 = arith.constant 2.0 : f32 - omp.reduction %2, %1 : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@foo %0 -> %prv : !llvm.ptr) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %2 = arith.constant 2.0 : f32 + omp.reduction %2, %1 : f32, !llvm.ptr + omp.yield + } + omp.terminator } return } @@ -629,11 +675,13 @@ func.func @foo(%lb : index, %ub : index, %step : index) { %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr // expected-error @below {{accumulator variable used more than once}} - omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr, @add_f32 %0 -> %prv1 : !llvm.ptr) - for (%iv) : index = (%lb) to (%ub) step (%step) { - %2 = arith.constant 2.0 : f32 - omp.reduction %2, %0 : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr, @add_f32 %0 -> %prv1 : !llvm.ptr) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %2 = arith.constant 2.0 : f32 + omp.reduction %2, %0 : f32, !llvm.ptr + omp.yield + } + omp.terminator } return } @@ -662,11 +710,13 @@ func.func @foo(%lb : index, %ub : index, %step : index, %mem : memref<1xf32>) { %c1 = arith.constant 1 : i32 // expected-error @below {{expected accumulator ('memref<1xf32>') to be the same type as reduction declaration ('!llvm.ptr')}} - omp.wsloop reduction(@add_f32 %mem -> %prv : memref<1xf32>) - for (%iv) : index = (%lb) to (%ub) step (%step) { - %2 = arith.constant 2.0 : f32 - omp.reduction %2, %mem : f32, memref<1xf32> - omp.yield + omp.wsloop reduction(@add_f32 %mem -> %prv : memref<1xf32>) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %2 = arith.constant 2.0 : f32 + omp.reduction %2, %mem : f32, memref<1xf32> + omp.yield + } + omp.terminator } return } @@ -698,60 +748,112 @@ omp.critical.declare @mutex hint(invalid_hint) // ----- -func.func @omp_ordered1(%arg1 : i32, %arg2 : i32, %arg3 : i32) -> () { - omp.wsloop ordered(1) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // expected-error @below {{ordered region must be closely nested inside a worksharing-loop region with an ordered clause without parameter present}} - omp.ordered.region { - omp.terminator +func.func @omp_ordered_region1(%x : i32) -> () { + omp.distribute { + omp.loop_nest (%i) : i32 = (%x) to (%x) step (%x) { + // expected-error @below {{op must be nested inside of a worksharing, simd or worksharing simd loop}} + omp.ordered.region { + omp.terminator + } + omp.yield } - omp.yield + omp.terminator } return } // ----- -func.func @omp_ordered2(%arg1 : i32, %arg2 : i32, %arg3 : i32) -> () { - omp.wsloop for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // expected-error @below {{ordered region must be closely nested inside a worksharing-loop region with an ordered clause without parameter present}} - omp.ordered.region { - omp.terminator +func.func @omp_ordered_region2(%x : i32) -> () { + omp.wsloop { + omp.loop_nest (%i) : i32 = (%x) to (%x) step (%x) { + // expected-error @below {{the enclosing worksharing-loop region must have an ordered clause}} + omp.ordered.region { + omp.terminator + } + omp.yield } - omp.yield + omp.terminator } return } // ----- -func.func @omp_ordered3(%vec0 : i64) -> () { - // expected-error @below {{ordered depend directive must be closely nested inside a worksharing-loop with ordered clause with parameter present}} +func.func @omp_ordered_region3(%x : i32) -> () { + omp.wsloop ordered(1) { + omp.loop_nest (%i) : i32 = (%x) to (%x) step (%x) { + // expected-error @below {{the enclosing loop's ordered clause must not have a parameter present}} + omp.ordered.region { + omp.terminator + } + omp.yield + } + omp.terminator + } + return +} + +// ----- + +func.func @omp_ordered1(%vec0 : i64) -> () { + // expected-error @below {{op must be nested inside of a loop}} omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} return } // ----- -func.func @omp_ordered4(%arg1 : i32, %arg2 : i32, %arg3 : i32, %vec0 : i64) -> () { - omp.wsloop ordered(0) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // expected-error @below {{ordered depend directive must be closely nested inside a worksharing-loop with ordered clause with parameter present}} - omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} +func.func @omp_ordered2(%arg1 : i32, %arg2 : i32, %arg3 : i32, %vec0 : i64) -> () { + omp.distribute { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // expected-error @below {{op must be nested inside of a worksharing, simd or worksharing simd loop}} + omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} + omp.yield + } + omp.terminator + } + return +} - omp.yield +// ----- + +func.func @omp_ordered3(%arg1 : i32, %arg2 : i32, %arg3 : i32, %vec0 : i64) -> () { + omp.wsloop { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // expected-error @below {{the enclosing worksharing-loop region must have an ordered clause}} + omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} + omp.yield + } + omp.terminator } return } + // ----- -func.func @omp_ordered5(%arg1 : i32, %arg2 : i32, %arg3 : i32, %vec0 : i64, %vec1 : i64) -> () { - omp.wsloop ordered(1) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // expected-error @below {{number of variables in depend clause does not match number of iteration variables in the doacross loop}} - omp.ordered depend_type(dependsource) depend_vec(%vec0, %vec1 : i64, i64) {num_loops_val = 2 : i64} +func.func @omp_ordered4(%arg1 : i32, %arg2 : i32, %arg3 : i32, %vec0 : i64) -> () { + omp.wsloop ordered(0) { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // expected-error @below {{the enclosing loop's ordered clause must have a parameter present}} + omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} + omp.yield + } + omp.terminator + } + return +} - omp.yield +// ----- + +func.func @omp_ordered5(%arg1 : i32, %arg2 : i32, %arg3 : i32, %vec0 : i64, %vec1 : i64) -> () { + omp.wsloop ordered(1) { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // expected-error @below {{number of variables in depend clause does not match number of iteration variables in the doacross loop}} + omp.ordered depend_type(dependsource) depend_vec(%vec0, %vec1 : i64, i64) {num_loops_val = 2 : i64} + omp.yield + } + omp.terminator } return } @@ -1590,11 +1692,13 @@ func.func @omp_cancel2() { // ----- func.func @omp_cancel3(%arg1 : i32, %arg2 : i32, %arg3 : i32) -> () { - omp.wsloop nowait - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // expected-error @below {{A worksharing construct that is canceled must not have a nowait clause}} - omp.cancel cancellation_construct_type(loop) - // CHECK: omp.terminator + omp.wsloop nowait { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // expected-error @below {{A worksharing construct that is canceled must not have a nowait clause}} + omp.cancel cancellation_construct_type(loop) + // CHECK: omp.yield + omp.yield + } omp.terminator } return @@ -1603,11 +1707,13 @@ func.func @omp_cancel3(%arg1 : i32, %arg2 : i32, %arg3 : i32) -> () { // ----- func.func @omp_cancel4(%arg1 : i32, %arg2 : i32, %arg3 : i32) -> () { - omp.wsloop ordered(1) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // expected-error @below {{A worksharing construct that is canceled must not have an ordered clause}} - omp.cancel cancellation_construct_type(loop) - // CHECK: omp.terminator + omp.wsloop ordered(1) { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // expected-error @below {{A worksharing construct that is canceled must not have an ordered clause}} + omp.cancel cancellation_construct_type(loop) + // CHECK: omp.yield + omp.yield + } omp.terminator } return @@ -2143,4 +2249,4 @@ func.func @undefined_privatizer(%arg0: !llvm.ptr) { omp.terminator }) : (!llvm.ptr) -> () return -} +} \ No newline at end of file diff --git a/mlir/test/Dialect/OpenMP/ops.mlir b/mlir/test/Dialect/OpenMP/ops.mlir index 56709c2e4d168b4f99356c3668123db039862354..be65aa02bfd4f337e13ea6537fd7232096e660a9 100644 --- a/mlir/test/Dialect/OpenMP/ops.mlir +++ b/mlir/test/Dialect/OpenMP/ops.mlir @@ -90,10 +90,9 @@ func.func @omp_parallel(%data_var : memref, %if_cond : i1, %num_threads : i // CHECK-NEXT: omp.parallel omp.parallel { // CHECK-NEXT: omp.wsloop - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%idx) to (%idx) step (%idx) { + omp.wsloop { // CHECK-NEXT: omp.loop_nest - omp.loop_nest (%iv2) : index = (%idx) to (%idx) step (%idx) { + omp.loop_nest (%iv) : index = (%idx) to (%idx) step (%idx) { omp.yield } omp.terminator @@ -153,49 +152,45 @@ func.func @omp_parallel_pretty(%data_var : memref, %if_cond : i1, %num_thre // CHECK-LABEL: omp_loop_nest func.func @omp_loop_nest(%lb : index, %ub : index, %step : index) -> () { - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}) to (%{{.*}}) step (%{{.*}}) "omp.loop_nest" (%lb, %ub, %step) ({ - ^bb0(%iv2: index): + ^bb0(%iv: index): omp.yield }) : (index, index, index) -> () - omp.yield + omp.terminator } - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) "omp.loop_nest" (%lb, %ub, %step) ({ - ^bb0(%iv2: index): + ^bb0(%iv: index): omp.yield }) {inclusive} : (index, index, index) -> () - omp.yield + omp.terminator } - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}, %{{.*}}) : index = // CHECK-SAME: (%{{.*}}, %{{.*}}) to (%{{.*}}, %{{.*}}) step (%{{.*}}, %{{.*}}) "omp.loop_nest" (%lb, %lb, %ub, %ub, %step, %step) ({ - ^bb0(%iv2: index, %iv3: index): + ^bb0(%iv: index, %iv3: index): omp.yield }) : (index, index, index, index, index, index) -> () - omp.yield + omp.terminator } - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}) to (%{{.*}}) step (%{{.*}}) "omp.loop_nest" (%lb, %ub, %step) ({ - ^bb0(%iv2: index): + ^bb0(%iv: index): // CHECK: test.op1 "test.op1"(%lb) : (index) -> () // CHECK: test.op2 @@ -203,7 +198,7 @@ func.func @omp_loop_nest(%lb : index, %ub : index, %step : index) -> () { // CHECK: omp.yield omp.yield }) : (index, index, index) -> () - omp.yield + omp.terminator } return @@ -211,45 +206,41 @@ func.func @omp_loop_nest(%lb : index, %ub : index, %step : index) -> () { // CHECK-LABEL: omp_loop_nest_pretty func.func @omp_loop_nest_pretty(%lb : index, %ub : index, %step : index) -> () { - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.loop_nest (%iv2) : index = (%lb) to (%ub) step (%step) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { omp.yield } - omp.yield + omp.terminator } - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) - omp.loop_nest (%iv2) : index = (%lb) to (%ub) inclusive step (%step) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) inclusive step (%step) { omp.yield } - omp.yield + omp.terminator } - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}, %{{.*}}) to (%{{.*}}, %{{.*}}) step (%{{.*}}, %{{.*}}) - omp.loop_nest (%iv2, %iv3) : index = (%lb, %lb) to (%ub, %ub) step (%step, %step) { + omp.loop_nest (%iv1, %iv2) : index = (%lb, %lb) to (%ub, %ub) step (%step, %step) { omp.yield } - omp.yield + omp.terminator } - // TODO Remove induction variables from omp.wsloop. - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { + omp.wsloop { // CHECK: omp.loop_nest // CHECK-SAME: (%{{.*}}) : index = // CHECK-SAME: (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.loop_nest (%iv2) : index = (%lb) to (%ub) step (%step) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { // CHECK: test.op1 "test.op1"(%lb) : (index) -> () // CHECK: test.op2 @@ -257,201 +248,271 @@ func.func @omp_loop_nest_pretty(%lb : index, %ub : index, %step : index) -> () { // CHECK: omp.yield omp.yield } - omp.yield + omp.terminator } return } -// CHECK-LABEL: omp_wsloop -func.func @omp_wsloop(%lb : index, %ub : index, %step : index, %data_var : memref, %linear_var : i32, %chunk_var : i32) -> () { +// CHECK-LABEL: omp_loop_nest_pretty_multi_block +func.func @omp_loop_nest_pretty_multi_block(%lb : index, %ub : index, + %step : index, %data1 : memref, %data2 : memref) -> () { - // CHECK: omp.wsloop ordered(1) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - "omp.wsloop" (%lb, %ub, %step) ({ - ^bb0(%iv: index): + omp.wsloop { + // CHECK: omp.loop_nest (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %1 = "test.payload"(%iv) : (index) -> (i32) + cf.br ^bb1(%1: i32) + ^bb1(%arg: i32): + memref.store %arg, %data1[%iv] : memref omp.yield - }) {operandSegmentSizes = array, ordered_val = 1} : - (index, index, index) -> () + } + omp.terminator + } - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(static) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - "omp.wsloop" (%lb, %ub, %step, %data_var, %linear_var) ({ - ^bb0(%iv: index): + omp.wsloop { + // CHECK: omp.loop_nest (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %c = "test.condition"(%iv) : (index) -> (i1) + %v1 = "test.payload"(%iv) : (index) -> (i32) + cf.cond_br %c, ^bb1(%v1: i32), ^bb2(%v1: i32) + ^bb1(%arg0: i32): + memref.store %arg0, %data1[%iv] : memref + cf.br ^bb3 + ^bb2(%arg1: i32): + memref.store %arg1, %data2[%iv] : memref + cf.br ^bb3 + ^bb3: omp.yield - }) {operandSegmentSizes = array, schedule_val = #omp} : - (index, index, index, memref, i32) -> () + } + omp.terminator + } - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref, %{{.*}} = %{{.*}} : memref) schedule(static) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - "omp.wsloop" (%lb, %ub, %step, %data_var, %data_var, %linear_var, %linear_var) ({ - ^bb0(%iv: index): + omp.wsloop { + // CHECK: omp.loop_nest (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %c = "test.condition"(%iv) : (index) -> (i1) + %v1 = "test.payload"(%iv) : (index) -> (i32) + cf.cond_br %c, ^bb1(%v1: i32), ^bb2(%v1: i32) + ^bb1(%arg0: i32): + memref.store %arg0, %data1[%iv] : memref + omp.yield + ^bb2(%arg1: i32): + memref.store %arg1, %data2[%iv] : memref omp.yield - }) {operandSegmentSizes = array, schedule_val = #omp} : - (index, index, index, memref, memref, i32, i32) -> () + } + omp.terminator + } - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(dynamic = %{{.*}}) ordered(2) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - "omp.wsloop" (%lb, %ub, %step, %data_var, %linear_var, %chunk_var) ({ - ^bb0(%iv: index): + return +} + +// CHECK-LABEL: omp_loop_nest_pretty_non_index +func.func @omp_loop_nest_pretty_non_index(%lb1 : i32, %ub1 : i32, %step1 : i32, + %lb2 : i64, %ub2 : i64, %step2 : i64, %data1 : memref, + %data2 : memref) -> () { + + omp.wsloop { + // CHECK: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) + omp.loop_nest (%iv1) : i32 = (%lb1) to (%ub1) step (%step1) { + %1 = "test.payload"(%iv1) : (i32) -> (index) + cf.br ^bb1(%1: index) + ^bb1(%arg1: index): + memref.store %iv1, %data1[%arg1] : memref omp.yield - }) {operandSegmentSizes = array, schedule_val = #omp, ordered_val = 2} : - (index, index, index, memref, i32, i32) -> () + } + omp.terminator + } - // CHECK: omp.wsloop schedule(auto) nowait - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - "omp.wsloop" (%lb, %ub, %step) ({ - ^bb0(%iv: index): + omp.wsloop { + // CHECK: omp.loop_nest (%{{.*}}) : i64 = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) + omp.loop_nest (%iv) : i64 = (%lb2) to (%ub2) step (%step2) { + %2 = "test.payload"(%iv) : (i64) -> (index) + cf.br ^bb1(%2: index) + ^bb1(%arg2: index): + memref.store %iv, %data2[%arg2] : memref omp.yield - }) {operandSegmentSizes = array, nowait, schedule_val = #omp} : - (index, index, index) -> () + } + omp.terminator + } return } -// CHECK-LABEL: omp_wsloop_pretty -func.func @omp_wsloop_pretty(%lb : index, %ub : index, %step : index, %data_var : memref, %linear_var : i32, %chunk_var : i32, %chunk_var2 : i16) -> () { +// CHECK-LABEL: omp_loop_nest_pretty_multiple +func.func @omp_loop_nest_pretty_multiple(%lb1 : i32, %ub1 : i32, %step1 : i32, + %lb2 : i32, %ub2 : i32, %step2 : i32, %data1 : memref) -> () { - // CHECK: omp.wsloop ordered(2) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop ordered(2) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield + omp.wsloop { + // CHECK: omp.loop_nest (%{{.*}}, %{{.*}}) : i32 = (%{{.*}}, %{{.*}}) to (%{{.*}}, %{{.*}}) step (%{{.*}}, %{{.*}}) + omp.loop_nest (%iv1, %iv2) : i32 = (%lb1, %lb2) to (%ub1, %ub2) step (%step1, %step2) { + %1 = "test.payload"(%iv1) : (i32) -> (index) + %2 = "test.payload"(%iv2) : (i32) -> (index) + memref.store %iv1, %data1[%1] : memref + memref.store %iv2, %data1[%2] : memref + omp.yield + } + omp.terminator } - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(static) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop schedule(static) linear(%data_var = %linear_var : memref) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } + return +} - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(static = %{{.*}} : i32) ordered(2) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop ordered(2) linear(%data_var = %linear_var : memref) schedule(static = %chunk_var : i32) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } +// CHECK-LABEL: omp_wsloop +func.func @omp_wsloop(%lb : index, %ub : index, %step : index, %data_var : memref, %linear_var : i32, %chunk_var : i32) -> () { - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(dynamic = %{{.*}} : i32, nonmonotonic) ordered(2) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop ordered(2) linear(%data_var = %linear_var : memref) schedule(dynamic = %chunk_var : i32, nonmonotonic) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } + // CHECK: omp.wsloop ordered(1) { + // CHECK-NEXT: omp.loop_nest + "omp.wsloop" () ({ + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + }) {operandSegmentSizes = array, ordered_val = 1} : + () -> () - // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(dynamic = %{{.*}} : i16, monotonic) ordered(2) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop ordered(2) linear(%data_var = %linear_var : memref) schedule(dynamic = %chunk_var2 : i16, monotonic) - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(static) { + // CHECK-NEXT: omp.loop_nest + "omp.wsloop" (%data_var, %linear_var) ({ + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + }) {operandSegmentSizes = array, schedule_val = #omp} : + (memref, i32) -> () - // CHECK: omp.wsloop for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref, %{{.*}} = %{{.*}} : memref) schedule(static) { + // CHECK-NEXT: omp.loop_nest + "omp.wsloop" (%data_var, %data_var, %linear_var, %linear_var) ({ + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + }) {operandSegmentSizes = array, schedule_val = #omp} : + (memref, memref, i32, i32) -> () - // CHECK: omp.wsloop for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) inclusive step (%step) { - omp.yield - } + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(dynamic = %{{.*}}) ordered(2) { + // CHECK-NEXT: omp.loop_nest + "omp.wsloop" (%data_var, %linear_var, %chunk_var) ({ + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + }) {operandSegmentSizes = array, schedule_val = #omp, ordered_val = 2} : + (memref, i32, i32) -> () - // CHECK: omp.wsloop nowait - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop nowait - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } + // CHECK: omp.wsloop schedule(auto) nowait { + // CHECK-NEXT: omp.loop_nest + "omp.wsloop" () ({ + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + }) {operandSegmentSizes = array, nowait, schedule_val = #omp} : + () -> () - // CHECK: omp.wsloop nowait order(concurrent) - // CHECK-SAME: for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop order(concurrent) nowait - for (%iv) : index = (%lb) to (%ub) step (%step) { - omp.yield - } + // CHECK: omp.wsloop { + // CHECK-NEXT: omp.simd + // CHECK-NEXT: omp.loop_nest + "omp.wsloop" () ({ + omp.simd { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } + omp.terminator + }) : () -> () return } -// CHECK-LABEL: omp_wsloop_pretty_multi_block -func.func @omp_wsloop_pretty_multi_block(%lb : index, %ub : index, %step : index, %data1 : memref, %data2 : memref) -> () { +// CHECK-LABEL: omp_wsloop_pretty +func.func @omp_wsloop_pretty(%lb : index, %ub : index, %step : index, %data_var : memref, %linear_var : i32, %chunk_var : i32, %chunk_var2 : i16) -> () { - // CHECK: omp.wsloop for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { - %1 = "test.payload"(%iv) : (index) -> (i32) - cf.br ^bb1(%1: i32) - ^bb1(%arg: i32): - memref.store %arg, %data1[%iv] : memref - omp.yield + // CHECK: omp.wsloop ordered(2) { + // CHECK-NEXT: omp.loop_nest + omp.wsloop ordered(2) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } - // CHECK: omp.wsloop for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { - %c = "test.condition"(%iv) : (index) -> (i1) - %v1 = "test.payload"(%iv) : (index) -> (i32) - cf.cond_br %c, ^bb1(%v1: i32), ^bb2(%v1: i32) - ^bb1(%arg0: i32): - memref.store %arg0, %data1[%iv] : memref - cf.br ^bb3 - ^bb2(%arg1: i32): - memref.store %arg1, %data2[%iv] : memref - cf.br ^bb3 - ^bb3: - omp.yield + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(static) { + // CHECK-NEXT: omp.loop_nest + omp.wsloop schedule(static) linear(%data_var = %linear_var : memref) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } - // CHECK: omp.wsloop for (%{{.*}}) : index = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { - %c = "test.condition"(%iv) : (index) -> (i1) - %v1 = "test.payload"(%iv) : (index) -> (i32) - cf.cond_br %c, ^bb1(%v1: i32), ^bb2(%v1: i32) - ^bb1(%arg0: i32): - memref.store %arg0, %data1[%iv] : memref - omp.yield - ^bb2(%arg1: i32): - memref.store %arg1, %data2[%iv] : memref - omp.yield + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(static = %{{.*}} : i32) ordered(2) { + // CHECK-NEXT: omp.loop_nest + omp.wsloop ordered(2) linear(%data_var = %linear_var : memref) schedule(static = %chunk_var : i32) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } - return -} - -// CHECK-LABEL: omp_wsloop_pretty_non_index -func.func @omp_wsloop_pretty_non_index(%lb1 : i32, %ub1 : i32, %step1 : i32, %lb2 : i64, %ub2 : i64, %step2 : i64, - %data1 : memref, %data2 : memref) -> () { + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(dynamic = %{{.*}} : i32, nonmonotonic) ordered(2) { + // CHECK-NEXT: omp.loop_nest + omp.wsloop ordered(2) linear(%data_var = %linear_var : memref) schedule(dynamic = %chunk_var : i32, nonmonotonic) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } - // CHECK: omp.wsloop for (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop for (%iv1) : i32 = (%lb1) to (%ub1) step (%step1) { - %1 = "test.payload"(%iv1) : (i32) -> (index) - cf.br ^bb1(%1: index) - ^bb1(%arg1: index): - memref.store %iv1, %data1[%arg1] : memref - omp.yield + // CHECK: omp.wsloop linear(%{{.*}} = %{{.*}} : memref) schedule(dynamic = %{{.*}} : i16, monotonic) ordered(2) { + // CHECK-NEXT: omp.loop_nest + omp.wsloop ordered(2) linear(%data_var = %linear_var : memref) schedule(dynamic = %chunk_var2 : i16, monotonic) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } - // CHECK: omp.wsloop for (%{{.*}}) : i64 = (%{{.*}}) to (%{{.*}}) step (%{{.*}}) - omp.wsloop for (%iv2) : i64 = (%lb2) to (%ub2) step (%step2) { - %2 = "test.payload"(%iv2) : (i64) -> (index) - cf.br ^bb1(%2: index) - ^bb1(%arg2: index): - memref.store %iv2, %data2[%arg2] : memref - omp.yield + // CHECK: omp.wsloop { + // CHECK-NEXT: omp.loop_nest + omp.wsloop { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator } - return -} + // CHECK: omp.wsloop nowait { + // CHECK-NEXT: omp.loop_nest + omp.wsloop nowait { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } -// CHECK-LABEL: omp_wsloop_pretty_multiple -func.func @omp_wsloop_pretty_multiple(%lb1 : i32, %ub1 : i32, %step1 : i32, %lb2 : i32, %ub2 : i32, %step2 : i32, %data1 : memref) -> () { + // CHECK: omp.wsloop nowait order(concurrent) { + // CHECK-NEXT: omp.loop_nest + omp.wsloop order(concurrent) nowait { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } - // CHECK: omp.wsloop for (%{{.*}}, %{{.*}}) : i32 = (%{{.*}}, %{{.*}}) to (%{{.*}}, %{{.*}}) step (%{{.*}}, %{{.*}}) - omp.wsloop for (%iv1, %iv2) : i32 = (%lb1, %lb2) to (%ub1, %ub2) step (%step1, %step2) { - %1 = "test.payload"(%iv1) : (i32) -> (index) - %2 = "test.payload"(%iv2) : (i32) -> (index) - memref.store %iv1, %data1[%1] : memref - memref.store %iv2, %data1[%2] : memref - omp.yield + // CHECK: omp.wsloop { + // CHECK-NEXT: omp.simd + // CHECK-NEXT: omp.loop_nest + omp.wsloop { + omp.simd { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + omp.yield + } + omp.terminator + } + omp.terminator } return @@ -659,7 +720,7 @@ func.func @omp_distribute(%chunk_size : i32, %data_var : memref, %arg0 : i3 // CHECK: omp.distribute omp.distribute { omp.simd { - omp.loop_nest (%iv2) : i32 = (%arg0) to (%arg0) step (%arg0) { + omp.loop_nest (%iv) : i32 = (%arg0) to (%arg0) step (%arg0) { omp.yield } } @@ -791,17 +852,19 @@ func.func @wsloop_reduction(%lb : index, %ub : index, %step : index) { %c1 = arith.constant 1 : i32 %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr // CHECK: reduction(@add_f32 %{{.+}} -> %[[PRV:.+]] : !llvm.ptr) - omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr) - for (%iv) : index = (%lb) to (%ub) step (%step) { - // CHECK: %[[CST:.+]] = arith.constant 2.0{{.*}} : f32 - %cst = arith.constant 2.0 : f32 - // CHECK: %[[LPRV:.+]] = llvm.load %[[PRV]] : !llvm.ptr -> f32 - %lprv = llvm.load %prv : !llvm.ptr -> f32 - // CHECK: %[[RES:.+]] = llvm.fadd %[[LPRV]], %[[CST]] : f32 - %res = llvm.fadd %lprv, %cst: f32 - // CHECK: llvm.store %[[RES]], %[[PRV]] : f32, !llvm.ptr - llvm.store %res, %prv : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + // CHECK: %[[CST:.+]] = arith.constant 2.0{{.*}} : f32 + %cst = arith.constant 2.0 : f32 + // CHECK: %[[LPRV:.+]] = llvm.load %[[PRV]] : !llvm.ptr -> f32 + %lprv = llvm.load %prv : !llvm.ptr -> f32 + // CHECK: %[[RES:.+]] = llvm.fadd %[[LPRV]], %[[CST]] : f32 + %res = llvm.fadd %lprv, %cst: f32 + // CHECK: llvm.store %[[RES]], %[[PRV]] : f32, !llvm.ptr + llvm.store %res, %prv : f32, !llvm.ptr + omp.yield + } + omp.terminator } return } @@ -828,14 +891,19 @@ func.func @parallel_wsloop_reduction(%lb : index, %ub : index, %step : index) { %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr // CHECK: omp.parallel reduction(@add_f32 %{{.*}} -> %{{.+}} : !llvm.ptr) { omp.parallel reduction(@add_f32 %0 -> %prv : !llvm.ptr) { - // CHECK: omp.wsloop for (%{{.+}}) : index = (%{{.+}}) to (%{{.+}}) step (%{{.+}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { - %1 = arith.constant 2.0 : f32 - %2 = llvm.load %prv : !llvm.ptr -> f32 - // CHECK: llvm.fadd %{{.+}}, %{{.+}} : f32 - llvm.fadd %1, %2 : f32 - // CHECK: omp.yield - omp.yield + // CHECK: omp.wsloop { + omp.wsloop { + // CHECK: omp.loop_nest (%{{.+}}) : index = (%{{.+}}) to (%{{.+}}) step (%{{.+}}) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %1 = arith.constant 2.0 : f32 + %2 = llvm.load %prv : !llvm.ptr -> f32 + // CHECK: llvm.fadd %{{.+}}, %{{.+}} : f32 + llvm.fadd %1, %2 : f32 + // CHECK: omp.yield + omp.yield + } + // CHECK: omp.terminator + omp.terminator } // CHECK: omp.terminator omp.terminator @@ -959,16 +1027,18 @@ combiner { // CHECK-LABEL: func @wsloop_reduction2 func.func @wsloop_reduction2(%lb : index, %ub : index, %step : index) { %0 = memref.alloca() : memref<1xf32> - // CHECK: omp.wsloop reduction(@add2_f32 %{{.+}} -> %{{.+}} : memref<1xf32>) - omp.wsloop reduction(@add2_f32 %0 -> %prv : memref<1xf32>) - for (%iv) : index = (%lb) to (%ub) step (%step) { - %1 = arith.constant 2.0 : f32 - %2 = arith.constant 0 : index - %3 = memref.load %prv[%2] : memref<1xf32> - // CHECK: llvm.fadd - %4 = llvm.fadd %1, %3 : f32 - memref.store %4, %prv[%2] : memref<1xf32> - omp.yield + // CHECK: omp.wsloop reduction(@add2_f32 %{{.+}} -> %{{.+}} : memref<1xf32>) { + omp.wsloop reduction(@add2_f32 %0 -> %prv : memref<1xf32>) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %1 = arith.constant 2.0 : f32 + %2 = arith.constant 0 : index + %3 = memref.load %prv[%2] : memref<1xf32> + // CHECK: llvm.fadd + %4 = llvm.fadd %1, %3 : f32 + memref.store %4, %prv[%2] : memref<1xf32> + omp.yield + } + omp.terminator } return } @@ -995,14 +1065,19 @@ func.func @parallel_wsloop_reduction2(%lb : index, %ub : index, %step : index) { %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr // CHECK: omp.parallel reduction(@add2_f32 %{{.*}} -> %{{.+}} : !llvm.ptr) { omp.parallel reduction(@add2_f32 %0 -> %prv : !llvm.ptr) { - // CHECK: omp.wsloop for (%{{.+}}) : index = (%{{.+}}) to (%{{.+}}) step (%{{.+}}) - omp.wsloop for (%iv) : index = (%lb) to (%ub) step (%step) { - %1 = arith.constant 2.0 : f32 - %2 = llvm.load %prv : !llvm.ptr -> f32 - // CHECK: llvm.fadd %{{.+}}, %{{.+}} : f32 - %3 = llvm.fadd %1, %2 : f32 - // CHECK: omp.yield - omp.yield + // CHECK: omp.wsloop { + omp.wsloop { + // CHECK: omp.loop_nest (%{{.+}}) : index = (%{{.+}}) to (%{{.+}}) step (%{{.+}}) { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + %1 = arith.constant 2.0 : f32 + %2 = llvm.load %prv : !llvm.ptr -> f32 + // CHECK: llvm.fadd %{{.+}}, %{{.+}} : f32 + %3 = llvm.fadd %1, %2 : f32 + // CHECK: omp.yield + omp.yield + } + // CHECK: omp.terminator + omp.terminator } // CHECK: omp.terminator omp.terminator @@ -1076,36 +1151,44 @@ func.func @omp_ordered(%arg1 : i32, %arg2 : i32, %arg3 : i32, omp.terminator } - omp.wsloop ordered(0) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - omp.ordered.region { - omp.terminator + omp.wsloop ordered(0) { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // CHECK: omp.ordered.region + omp.ordered.region { + // CHECK: omp.terminator + omp.terminator + } + omp.yield } - omp.yield + omp.terminator } - omp.wsloop ordered(1) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // Only one DEPEND(SINK: vec) clause - // CHECK: omp.ordered depend_type(dependsink) depend_vec(%{{.*}} : i64) {num_loops_val = 1 : i64} - omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} + omp.wsloop ordered(1) { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // Only one DEPEND(SINK: vec) clause + // CHECK: omp.ordered depend_type(dependsink) depend_vec(%{{.*}} : i64) {num_loops_val = 1 : i64} + omp.ordered depend_type(dependsink) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} - // CHECK: omp.ordered depend_type(dependsource) depend_vec(%{{.*}} : i64) {num_loops_val = 1 : i64} - omp.ordered depend_type(dependsource) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} + // CHECK: omp.ordered depend_type(dependsource) depend_vec(%{{.*}} : i64) {num_loops_val = 1 : i64} + omp.ordered depend_type(dependsource) depend_vec(%vec0 : i64) {num_loops_val = 1 : i64} - omp.yield + omp.yield + } + omp.terminator } - omp.wsloop ordered(2) - for (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { - // Multiple DEPEND(SINK: vec) clauses - // CHECK: omp.ordered depend_type(dependsink) depend_vec(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : i64, i64, i64, i64) {num_loops_val = 2 : i64} - omp.ordered depend_type(dependsink) depend_vec(%vec0, %vec1, %vec2, %vec3 : i64, i64, i64, i64) {num_loops_val = 2 : i64} + omp.wsloop ordered(2) { + omp.loop_nest (%0) : i32 = (%arg1) to (%arg2) step (%arg3) { + // Multiple DEPEND(SINK: vec) clauses + // CHECK: omp.ordered depend_type(dependsink) depend_vec(%{{.*}}, %{{.*}}, %{{.*}}, %{{.*}} : i64, i64, i64, i64) {num_loops_val = 2 : i64} + omp.ordered depend_type(dependsink) depend_vec(%vec0, %vec1, %vec2, %vec3 : i64, i64, i64, i64) {num_loops_val = 2 : i64} - // CHECK: omp.ordered depend_type(dependsource) depend_vec(%{{.*}}, %{{.*}} : i64, i64) {num_loops_val = 2 : i64} - omp.ordered depend_type(dependsource) depend_vec(%vec0, %vec1 : i64, i64) {num_loops_val = 2 : i64} + // CHECK: omp.ordered depend_type(dependsource) depend_vec(%{{.*}}, %{{.*}} : i64, i64) {num_loops_val = 2 : i64} + omp.ordered depend_type(dependsource) depend_vec(%vec0, %vec1 : i64, i64) {num_loops_val = 2 : i64} - omp.yield + omp.yield + } + omp.terminator } return @@ -1956,11 +2039,13 @@ func.func @omp_cancel_parallel(%if_cond : i1) -> () { } func.func @omp_cancel_wsloop(%lb : index, %ub : index, %step : index) { - omp.wsloop - for (%iv) : index = (%lb) to (%ub) step (%step) { - // CHECK: omp.cancel cancellation_construct_type(loop) - omp.cancel cancellation_construct_type(loop) - // CHECK: omp.terminator + omp.wsloop { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + // CHECK: omp.cancel cancellation_construct_type(loop) + omp.cancel cancellation_construct_type(loop) + // CHECK: omp.yield + omp.yield + } omp.terminator } return @@ -1991,13 +2076,15 @@ func.func @omp_cancellationpoint_parallel() -> () { } func.func @omp_cancellationpoint_wsloop(%lb : index, %ub : index, %step : index) { - omp.wsloop - for (%iv) : index = (%lb) to (%ub) step (%step) { - // CHECK: omp.cancellation_point cancellation_construct_type(loop) - omp.cancellation_point cancellation_construct_type(loop) - // CHECK: omp.cancel cancellation_construct_type(loop) - omp.cancel cancellation_construct_type(loop) - // CHECK: omp.terminator + omp.wsloop { + omp.loop_nest (%iv) : index = (%lb) to (%ub) step (%step) { + // CHECK: omp.cancellation_point cancellation_construct_type(loop) + omp.cancellation_point cancellation_construct_type(loop) + // CHECK: omp.cancel cancellation_construct_type(loop) + omp.cancel cancellation_construct_type(loop) + // CHECK: omp.yield + omp.yield + } omp.terminator } return diff --git a/mlir/test/Dialect/SCF/forall-to-for.mlir b/mlir/test/Dialect/SCF/forall-to-for.mlir new file mode 100644 index 0000000000000000000000000000000000000000..e7d183fb9d2b54d379adb0391b00d75d406ec8fd --- /dev/null +++ b/mlir/test/Dialect/SCF/forall-to-for.mlir @@ -0,0 +1,57 @@ +// RUN: mlir-opt %s -pass-pipeline='builtin.module(func.func(scf-forall-to-for))' -split-input-file | FileCheck %s + +func.func private @callee(%i: index, %j: index) + +// CHECK-LABEL: @two_iters +// CHECK-SAME: %[[UB1:.+]]: index, %[[UB2:.+]]: index +func.func @two_iters(%ub1: index, %ub2: index) { + scf.forall (%i, %j) in (%ub1, %ub2) { + func.call @callee(%i, %j) : (index, index) -> () + } + // CHECK: scf.for %[[IV1:.+]] = %{{.*}} to %[[UB1]] + // CHECK: scf.for %[[IV2:.+]] = %{{.*}} to %[[UB2]] + // CHECK: func.call @callee(%[[IV1]], %[[IV2]]) + return +} + +// ----- + +func.func private @callee(%i: index, %j: index) + +// CHECK-LABEL: @repeated +// CHECK-SAME: %[[UB1:.+]]: index, %[[UB2:.+]]: index +func.func @repeated(%ub1: index, %ub2: index) { + scf.forall (%i, %j) in (%ub1, %ub2) { + func.call @callee(%i, %j) : (index, index) -> () + } + // CHECK: scf.for %[[IV1:.+]] = %{{.*}} to %[[UB1]] + // CHECK: scf.for %[[IV2:.+]] = %{{.*}} to %[[UB2]] + // CHECK: func.call @callee(%[[IV1]], %[[IV2]]) + scf.forall (%i, %j) in (%ub1, %ub2) { + func.call @callee(%i, %j) : (index, index) -> () + } + // CHECK: scf.for %[[IV1:.+]] = %{{.*}} to %[[UB1]] + // CHECK: scf.for %[[IV2:.+]] = %{{.*}} to %[[UB2]] + // CHECK: func.call @callee(%[[IV1]], %[[IV2]]) + return +} + +// ----- + +func.func private @callee(%i: index, %j: index, %k: index, %l: index) + +// CHECK-LABEL: @nested +// CHECK-SAME: %[[UB1:.+]]: index, %[[UB2:.+]]: index, %[[UB3:.+]]: index, %[[UB4:.+]]: index +func.func @nested(%ub1: index, %ub2: index, %ub3: index, %ub4: index) { + // CHECK: scf.for %[[IV1:.+]] = %{{.*}} to %[[UB1]] + // CHECK: scf.for %[[IV2:.+]] = %{{.*}} to %[[UB2]] + // CHECK: scf.for %[[IV3:.+]] = %{{.*}} to %[[UB3]] + // CHECK: scf.for %[[IV4:.+]] = %{{.*}} to %[[UB4]] + // CHECK: func.call @callee(%[[IV1]], %[[IV2]], %[[IV3]], %[[IV4]]) + scf.forall (%i, %j) in (%ub1, %ub2) { + scf.forall (%k, %l) in (%ub3, %ub4) { + func.call @callee(%i, %j, %k, %l) : (index, index, index, index) -> () + } + } + return +} diff --git a/mlir/test/Dialect/SparseTensor/fuse_sparse_concat_with_extract_slice.mlir b/mlir/test/Dialect/SparseTensor/fuse_sparse_concat_with_extract_slice.mlir new file mode 100644 index 0000000000000000000000000000000000000000..5d93301bc8ca76489242024c51082272df45c0cb --- /dev/null +++ b/mlir/test/Dialect/SparseTensor/fuse_sparse_concat_with_extract_slice.mlir @@ -0,0 +1,23 @@ +// RUN: mlir-opt %s --pre-sparsification-rewrite | FileCheck %s + +#CCCD = #sparse_tensor.encoding<{ map = (d0, d1, d2, d3) -> (d0 : compressed, d1 : compressed, d2 : compressed, d3 : dense) }> + + + +// CHECK-LABEL: func.func @fuse_concat_with_extract( +// CHECK-SAME: %[[VAL_0:.*0]]: tensor<128x32x32x1xf32, #sparse{{[0-9]*}}>, +// CHECK-SAME: %[[VAL_1:.*1]]: tensor<128x32x32x1xf32, #sparse{{[0-9]*}}>, +// CHECK-SAME: %[[VAL_2:.*2]]: tensor<128x32x32x1xf32, #sparse{{[0-9]*}}>) +// CHECK-NOT: tensor.concat +// CHECK-NOT: tensor.extract_slice +// CHECK: return %[[VAL_0]], %[[VAL_1]], %[[VAL_2]] +// CHECK: } +func.func @fuse_concat_with_extract(%t0 : tensor<128x32x32x1xf32, #CCCD>, + %t1 : tensor<128x32x32x1xf32, #CCCD>, + %t2 : tensor<128x32x32x1xf32, #CCCD>) -> (tensor<128x32x32x1xf32, #CCCD>, tensor<128x32x32x1xf32, #CCCD>, tensor<128x32x32x1xf32, #CCCD>) { + %concat = tensor.concat dim(3) %t0, %t1, %t2 : (tensor<128x32x32x1xf32, #CCCD>, tensor<128x32x32x1xf32, #CCCD>, tensor<128x32x32x1xf32, #CCCD>) -> tensor<128x32x32x3xf32, #CCCD> + %r0 = tensor.extract_slice %concat[0, 0, 0, 0] [128, 32, 32, 1] [1, 1, 1, 1] : tensor<128x32x32x3xf32, #CCCD> to tensor<128x32x32x1xf32, #CCCD> + %r1 = tensor.extract_slice %concat[0, 0, 0, 1] [128, 32, 32, 1] [1, 1, 1, 1] : tensor<128x32x32x3xf32, #CCCD> to tensor<128x32x32x1xf32, #CCCD> + %r2 = tensor.extract_slice %concat[0, 0, 0, 2] [128, 32, 32, 1] [1, 1, 1, 1] : tensor<128x32x32x3xf32, #CCCD> to tensor<128x32x32x1xf32, #CCCD> + return %r0, %r1, %r2 : tensor<128x32x32x1xf32, #CCCD>, tensor<128x32x32x1xf32, #CCCD>, tensor<128x32x32x1xf32, #CCCD> +} diff --git a/mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir b/mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir index 66e61afd897dd13747427eecba8206b8f978c871..7eeda9a988026885b54f05e04afcb6101e117a85 100644 --- a/mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir +++ b/mlir/test/Dialect/SparseTensor/roundtrip_encoding.mlir @@ -22,6 +22,64 @@ func.func private @sparse_csr(tensor) // ----- +#CSR_OnlyOnes = #sparse_tensor.encoding<{ + map = (d0, d1) -> (d0 : dense, d1 : compressed), + posWidth = 64, + crdWidth = 64, + explicitVal = 1.0 : f32, + implicitVal = 0.0 : f32 +}> + +// CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed), posWidth = 64, crdWidth = 64, explicitVal = 1.000000e+00 : f32, implicitVal = 0.000000e+00 : f32 }> +// CHECK-LABEL: func private @sparse_csr( +// CHECK-SAME: tensor) +func.func private @sparse_csr(tensor) + +// ----- + +#CSR_OnlyOnes = #sparse_tensor.encoding<{ + map = (d0, d1) -> (d0 : dense, d1 : compressed), + explicitVal = 1.0 : f64, + implicitVal = 0.0 : f64 +}> + +// CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed), explicitVal = 1.000000e+00 : f64, implicitVal = 0.000000e+00 : f64 }> +// CHECK-LABEL: func private @sparse_csr( +// CHECK-SAME: tensor) +func.func private @sparse_csr(tensor) + +// ----- + +#CSR_OnlyOnes = #sparse_tensor.encoding<{ + map = (d0, d1) -> (d0 : dense, d1 : compressed), + posWidth = 64, + crdWidth = 64, + explicitVal = 1 : i32, + implicitVal = 0 : i32 +}> + +// CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed), posWidth = 64, crdWidth = 64, explicitVal = 1 : i32, implicitVal = 0 : i32 }> +// CHECK-LABEL: func private @sparse_csr( +// CHECK-SAME: tensor) +func.func private @sparse_csr(tensor) + +// ----- + +#CSR_OnlyOnes = #sparse_tensor.encoding<{ + map = (d0, d1) -> (d0 : dense, d1 : compressed), + posWidth = 64, + crdWidth = 64, + explicitVal = 1 : i64, + implicitVal = 0 : i64 +}> + +// CHECK: #[[$CSR_OnlyOnes:.*]] = #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 : compressed), posWidth = 64, crdWidth = 64, explicitVal = 1 : i64, implicitVal = 0 : i64 }> +// CHECK-LABEL: func private @sparse_csr( +// CHECK-SAME: tensor) +func.func private @sparse_csr(tensor) + +// ----- + #BCSR = #sparse_tensor.encoding<{ map = (d0, d1, d2) -> (d0 : batch, d1: dense, d2 : compressed), }> diff --git a/mlir/test/Dialect/XeGPU/XeGPUOps.mlir b/mlir/test/Dialect/XeGPU/XeGPUOps.mlir index f0945c79a94ac3db85e3dc4f1c03759049dabf51..00d32d2a2ee9436d08650d968db303fde829f32e 100644 --- a/mlir/test/Dialect/XeGPU/XeGPUOps.mlir +++ b/mlir/test/Dialect/XeGPU/XeGPUOps.mlir @@ -80,7 +80,7 @@ gpu.func @test_prefetch_vc(%src: ui64) { //CHECK: %[[R0:.*]] = xegpu.create_tdesc %arg0 [0, 8, 16, 24] {chunk_size = 2 : i64} : ui64 -> !xegpu.tensor_desc<4x2xf32, #xegpu.tdesc_attr> %1 = xegpu.create_tdesc %src[0, 8, 16, 24] {chunk_size = 2} : ui64 -> !xegpu.tensor_desc<4x2xf32, #xegpu.tdesc_attr> // CHECK: xegpu.prefetch %[[R0]] <{l1_hint = #xegpu.cache_hint, l2_hint = #xegpu.cache_hint}> : !xegpu.tensor_desc<4x2xf32, #xegpu.tdesc_attr> - xegpu.prefetch %1 <{l1_hint = #xegpu.cache_hint, l2_hint = #xegpu.cache_hint}>: !xegpu.tensor_desc<4x2xf32, #xegpu.tdesc_attr> + xegpu.prefetch %1 <{l1_hint = #xegpu.cache_hint, l2_hint = #xegpu.cache_hint}>: !xegpu.tensor_desc<4x2xf32, #xegpu.tdesc_attr> gpu.return } @@ -121,4 +121,59 @@ gpu.func @test_create_update_tdesc_vc(%src: ui64) { gpu.return } -} \ No newline at end of file +// CHECK: gpu.func @test_dpas_vc(%[[arg0:.*]]: vector<8x8x2xf16>, %[[arg1:.*]]: vector<8x16x2xf16>) +gpu.func @test_dpas_vc(%a : vector<8x8x2xf16>, %b: vector<8x16x2xf16>) { + // CHECK: %0 = xegpu.dpas %[[arg0]], %[[arg1]] : vector<8x8x2xf16>, vector<8x16x2xf16> -> vector<8x16xf32> + %1 = xegpu.dpas %a, %b: vector<8x8x2xf16>, vector<8x16x2xf16> -> vector<8x16xf32> + gpu.return +} + +// CHECK: gpu.func @test_atomic_rmw(%[[arg0:.*]]: ui64, %[[arg1:.*]]: vector<16xf32>, %[[arg2:.*]]: vector<16xi1>) +gpu.func @test_atomic_rmw(%src: ui64, %value : vector<16xf32>, %mask : vector<16xi1>) { + //CHECK: %[[R0:.*]] = xegpu.create_tdesc %[[arg0]] [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] : ui64 -> !xegpu.tensor_desc<16xf32, #xegpu.tdesc_attr> + %1 = xegpu.create_tdesc %src[0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]: ui64 -> !xegpu.tensor_desc<16xf32, #xegpu.tdesc_attr> + //CHECK: %[[R1:.*]] = xegpu.atomic_rmw addf %[[R0]], %[[arg2]], %[[arg1]] : <16xf32, #xegpu.tdesc_attr>, vector<16xi1>, vector<16xf32> -> vector<16xf32> + xegpu.atomic_rmw addf %1, %mask, %value: !xegpu.tensor_desc<16xf32, #xegpu.tdesc_attr>, vector<16xi1>, vector<16xf32> -> vector<16xf32> + gpu.return +} + +// CHECK: gpu.func @alloc_nbarrier({{.*}}) { +gpu.func @alloc_nbarrier() { + // CHECK: xegpu.alloc_nbarrier + xegpu.alloc_nbarrier 8 + gpu.return +} + +// CHECK: gpu.func @init_nbarrier({{.*}}) { +gpu.func @init_nbarrier() { + //CHECK: %[[c1:.*]] = arith.constant 1 : i8 + //CHECK: %[[c16:.*]] = arith.constant 16 : i8 + %nbarrier_id = arith.constant 1 : i8 + %threads_count = arith.constant 16 : i8 + //CHECK: xegpu.init_nbarrier %[[c1]], %[[c16]] : i8, i8 -> !xegpu.nbarrier + %nbarrier = xegpu.init_nbarrier %nbarrier_id, %threads_count : i8, i8 -> !xegpu.nbarrier + gpu.return +} + +// CHECK: gpu.func @nbarrier_arrive(%[[arg0:.*]]: !xegpu.nbarrier) { +gpu.func @nbarrier_arrive(%nbarrier : !xegpu.nbarrier) { + //CHECK: xegpu.nbarrier_arrive %[[arg0]] : !xegpu.nbarrier + xegpu.nbarrier_arrive %nbarrier : !xegpu.nbarrier + gpu.return +} + +// CHECK: gpu.func @nbarrier_wait(%[[arg0:.*]]: !xegpu.nbarrier) { +gpu.func @nbarrier_wait(%nbarrier : !xegpu.nbarrier) { + //CHECK: xegpu.nbarrier_wait %[[arg0]] : !xegpu.nbarrier + xegpu.nbarrier_wait %nbarrier : !xegpu.nbarrier + gpu.return +} + +// CHECK-LABEL: gpu.func @fence({{.*}}) { +gpu.func @fence() { + //CHECK: xegpu.fence memory_kind = global, fence_scope = workgroup + xegpu.fence memory_kind = global, fence_scope = workgroup + gpu.return +} + +} diff --git a/mlir/test/Dialect/XeGPU/invalid.mlir b/mlir/test/Dialect/XeGPU/invalid.mlir index 5e29361ec690873bf1bbfb60326f6f4ee2bc0619..7819ad60b97d923abb56eb96d8fda19fe21eca49 100644 --- a/mlir/test/Dialect/XeGPU/invalid.mlir +++ b/mlir/test/Dialect/XeGPU/invalid.mlir @@ -156,4 +156,32 @@ func.func @test_store_scatter_vc_2(%src: ui64) { xegpu.store %1, %2, %0 <{l1_hint = #xegpu.cache_hint}> : vector<4x2xf32>, !xegpu.tensor_desc<4x2xf32, #xegpu.tdesc_attr>, vector<4xi1> return +} + +// ----- +func.func @test_dpas_vc_1(%a : vector<8x4x2xf16>, %b: vector<8x16x2xf16>) { + // expected-error@+1 {{K-dimension or vnni-factor mismatch}} + %1 = xegpu.dpas %a, %b : vector<8x4x2xf16>, vector<8x16x2xf16> -> vector<8x16xf32> + return +} + +// ----- +func.func @test_dpas_vc_2(%a : vector<8x16xf16>, %b: vector<8x16x2xf16>) { + // expected-error@+1 {{lhs and rhs rank does not match for dpas op, or their rank is not 3}} + %1 = xegpu.dpas %a, %b : vector<8x16xf16>, vector<8x16x2xf16> -> vector<8x16xf32> + return +} + +// ----- +func.func @test_dpas_vc_3(%a : vector<8x16xf16>, %b: vector<16x16xf16>) { + // expected-error@+1 {{lhs and rhs rank does not match for dpas op, or their rank is not 3}} + %1 = xegpu.dpas %a, %b : vector<8x16xf16>, vector<16x16xf16> -> vector<8x16xf32> + return +} + +// ----- +func.func @test_dpas_vc_4(%a : vector<8x8x2xf16>, %b: vector<8x16x2xf16>, %c : vector<8x16xf16>) { + // expected-error@+1 {{Accumulator and Result for dpas op should have the same type}} + %1 = xegpu.dpas %a, %b, %c : vector<8x8x2xf16>, vector<8x16x2xf16>, vector<8x16xf16> -> vector<8x16xf32> + return } \ No newline at end of file diff --git a/mlir/test/Examples/NVGPU/Ch0.py b/mlir/test/Examples/NVGPU/Ch0.py new file mode 100644 index 0000000000000000000000000000000000000000..8f60088178d11952aab22dd99c9a7fd244fd2c81 --- /dev/null +++ b/mlir/test/Examples/NVGPU/Ch0.py @@ -0,0 +1,50 @@ +# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \ +# RUN: %PYTHON %s | FileCheck %s + +# ===----------------------------------------------------------------------===// +# Chapter 0 : Hello World +# ===----------------------------------------------------------------------===// +# +# This program demonstrates Hello World: +# 1. Build MLIR function with arguments +# 2. Build MLIR GPU kernel +# 3. Print from a GPU thread +# 4. Pass arguments, JIT compile and run the MLIR function +# +# ===----------------------------------------------------------------------===// + + +from mlir.dialects import gpu +from tools.nvdsl import * + + +# 1. The decorator generates a MLIR func.func. +# Everything inside the Python function becomes the body of the func. +# The decorator also translates `alpha` to an `index` type. +@NVDSL.mlir_func +def main(alpha): + # 2. The decorator generates a MLIR gpu.launch. + # Everything inside the Python function becomes the body of the gpu.launch. + # This allows for late outlining of the GPU kernel, enabling optimizations + # like constant folding from host to device. + @NVDSL.mlir_gpu_launch(grid=(1, 1, 1), block=(4, 1, 1)) + def kernel(): + tidx = gpu.thread_id(gpu.Dimension.x) + # + operator generates arith.addi + myValue = alpha + tidx + # Print from a GPU thread + gpu.printf("GPU thread %llu has %llu\n", [tidx, myValue]) + + # 3. Call the GPU kernel + kernel() + + +alpha = 100 +# 4. The `mlir_func` decorator JIT compiles the IR and executes the MLIR function. +main(alpha) + + +# CHECK: GPU thread 0 has 100 +# CHECK: GPU thread 1 has 101 +# CHECK: GPU thread 2 has 102 +# CHECK: GPU thread 3 has 103 diff --git a/mlir/test/Examples/NVGPU/Ch1.py b/mlir/test/Examples/NVGPU/Ch1.py new file mode 100644 index 0000000000000000000000000000000000000000..da65aa2ef6a172a33628c6f764250dbf5622e46b --- /dev/null +++ b/mlir/test/Examples/NVGPU/Ch1.py @@ -0,0 +1,66 @@ +# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \ +# RUN: %PYTHON %s | FileCheck %s + +# ===----------------------------------------------------------------------===// +# Chapter 1 : 2D Saxpy +# ===----------------------------------------------------------------------===// +# +# This program demonstrates 2D Saxpy: +# 1. Use GPU dialect to allocate and copy memory host to gpu and vice versa +# 2. Computes 2D SAXPY kernel using operator overloading +# 3. Pass numpy arrays to MLIR as memref arguments +# 4. Verify MLIR program with reference computation in python +# +# ===----------------------------------------------------------------------===// + + +from mlir import ir +from mlir.dialects import gpu, memref +from tools.nvdsl import * +import numpy as np + + +@NVDSL.mlir_func +def saxpy(x, y, alpha): + # 1. Use MLIR GPU dialect to allocate and copy memory + token_ty = ir.Type.parse("!gpu.async.token") + t1 = gpu.wait(token_ty, []) + x_dev, t2 = gpu.alloc(x.type, token_ty, [t1], [], []) + y_dev, t3 = gpu.alloc(y.type, token_ty, [t2], [], []) + t4 = gpu.memcpy(token_ty, [t3], x_dev, x) + t5 = gpu.memcpy(token_ty, [t4], y_dev, y) + t6 = gpu.wait(token_ty, [t5]) + + # 2. Compute 2D SAXPY kernel + @NVDSL.mlir_gpu_launch(grid=(M, 1, 1), block=(N, 1, 1)) + def saxpy_kernel(): + bidx = gpu.block_id(gpu.Dimension.x) + tidx = gpu.thread_id(gpu.Dimension.x) + x_val = memref.load(x_dev, [bidx, tidx]) + y_val = memref.load(y_dev, [bidx, tidx]) + + # SAXPY: y[i] += a * x[i]; + y_val += x_val * alpha + + memref.store(y_val, y_dev, [bidx, tidx]) + + saxpy_kernel() + + t7 = gpu.memcpy(token_ty, [t6], y, y_dev) + gpu.wait(token_ty, [t7]) + + +# 3. Pass numpy arrays to MLIR +M = 256 +N = 32 +alpha = 2.0 +x = np.random.randn(M, N).astype(np.float32) +y = np.ones((M, N), np.float32) +saxpy(x, y, alpha) + +# 4. Verify MLIR with reference computation +ref = np.ones((M, N), np.float32) +ref += x * alpha +np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01) +print("PASS") +# CHECK-NOT: Mismatched elements diff --git a/mlir/test/Examples/NVGPU/Ch2.py b/mlir/test/Examples/NVGPU/Ch2.py new file mode 100644 index 0000000000000000000000000000000000000000..78c14cb2c7ad8ce5040cff496bff2f6fd0160855 --- /dev/null +++ b/mlir/test/Examples/NVGPU/Ch2.py @@ -0,0 +1,93 @@ +# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \ +# RUN: %PYTHON %s | FileCheck %s + +# ===----------------------------------------------------------------------===// +# Chapter 2 : 2D Saxpy with TMA +# ===----------------------------------------------------------------------===// +# +# This program demonstrates 2D Saxpy. It is same as Chapter 1, +# but it loads data using TMA (Tensor Memory Accelerator) +# +# This chapter introduces demonstrates: +# 1. Computes 2D SAXPY in the same way as Ch1.py but loads data using TMA +# 2. Create and initialize 1 asynchronous transactional barrier (mbarrier) +# 3. Thread-0 Load request data load from TMA for each thread block +# 4. Each thread block loads <1x32xf32> for x and y. +# 5. Wait for completion of TMA load with mbarrier +# +# ===----------------------------------------------------------------------===// + +from mlir import ir +from mlir.dialects import nvgpu, scf, arith, memref, vector, gpu +from tools.nvdsl import * +from mlir import runtime as rt +from mlir.extras import types as T +import numpy as np + + +@NVDSL.mlir_func +def saxpy(x, y, alpha): + token_ty = ir.Type.parse("!gpu.async.token") + t1 = gpu.wait(token_ty, []) + x_dev, t2 = gpu.alloc(x.type, token_ty, [t1], [], []) + y_dev, t3 = gpu.alloc(y.type, token_ty, [t2], [], []) + t4 = gpu.memcpy(token_ty, [t3], x_dev, x) + t5 = gpu.memcpy(token_ty, [t4], y_dev, y) + t6 = gpu.wait(token_ty, [t5]) + + x_tma = TMA([1, N], x.type) + y_tma = TMA([1, N], y.type) + x_tma.create_descriptor(x_dev) + y_tma.create_descriptor(y_dev) + sz_x = get_type_size(x_tma.tma_memref) + sz_y = get_type_size(x_tma.tma_memref) + sz = sz_x + sz_y + + @NVDSL.mlir_gpu_launch(grid=(M, 1, 1), block=(N, 1, 1), smem=sz) + def saxpy_tma_kernel(): + bidx = gpu.block_id(gpu.Dimension.x) + tidx = gpu.thread_id(gpu.Dimension.x) + isThread0 = tidx == 0 + + # 1. Create and initialize asynchronous transactional barrier (mbarrier) + mbar_group = Mbarriers(number_of_barriers=1) + mbar_group[0].init(1, predicate=isThread0) + + # 2. Execute Tensor Memory Accelerator (TMA) Load + x_smem = get_dynamic_shared_memory([1, N], T.f32()) + y_smem = get_dynamic_shared_memory([1, N], T.f32(), offset=sz_x) + x_tma.load(x_smem, mbar_group[0], coords=[0, bidx], predicate=isThread0) + y_tma.load(y_smem, mbar_group[0], coords=[0, bidx], predicate=isThread0) + mbar_group[0].arrive(txcount=sz, predicate=isThread0) + + # 3. Wait for completion of TMA load with mbarrier + mbar_group[0].try_wait() + + x_val = memref.load(x_smem, [const(0), tidx]) + y_val = memref.load(y_smem, [const(0), tidx]) + + # SAXPY: y[i] += a * x[i]; + y_val += x_val * alpha + + memref.store(y_val, y_dev, [bidx, tidx]) + + saxpy_tma_kernel() + + t7 = gpu.memcpy(token_ty, [t6], y, y_dev) + gpu.wait(token_ty, [t7]) + + +# 3. Pass numpy arrays to MLIR +M = 256 +N = 32 +alpha = 2.0 +x = np.random.randn(M, N).astype(np.float32) +y = np.ones((M, N), np.float32) +saxpy(x, y, alpha) + +# 4. Verify MLIR with reference computation +ref = np.ones((M, N), np.float32) +ref += x * alpha +np.testing.assert_allclose(y, ref, rtol=5e-03, atol=1e-01) +print("PASS") +# CHECK-NOT: Mismatched elements diff --git a/mlir/test/Examples/NVGPU/Ch3.py b/mlir/test/Examples/NVGPU/Ch3.py new file mode 100644 index 0000000000000000000000000000000000000000..a417014de8b49a4d9afabcff110ea288581363ce --- /dev/null +++ b/mlir/test/Examples/NVGPU/Ch3.py @@ -0,0 +1,129 @@ +# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \ +# RUN: %PYTHON %s | FileCheck %s + +# ===----------------------------------------------------------------------===// +# Chapter 3 : GEMM 128x128x64 with Tensor Core +# ===----------------------------------------------------------------------===// +# +# This program demonstrates a GEMM operation with 128x128x64 matrix multiplication +# +# This chapter introduces demonstrates: +# 1. Execute TMA Load for two input matrices +# 2. Performs Tensor Core GEMM 128x128x64 by warpgroup +# 3. Stores fragmented registers to global memory by warpgroup +# +# ===----------------------------------------------------------------------===// + + +from mlir import ir +from mlir.dialects import nvgpu, scf, arith, memref, vector, gpu +from tools.nvdsl import * +from mlir.extras import types as T +import numpy as np + + +def tma_load( + mbar_group: Mbarriers, + a_tma: TMA, + b_tma: TMA, + p, +): + """ + TMA loads two input matrices from global memory to shared memory. It performs the following operations: + + - tma.load a_shared_memory[0] at coordinate [0, 0] (Loads 128x64) + - tma.load b_shared_memory[0] at coordinate [0, 0] (Loads 64x64) + - tma.load b_shared_memory[0] at coordinate [64, 0] (Loads 64x64) + + mbarrier.arrive ta_count = 128x64xf16 + 64x128xf16 + """ + + size_tma_a = get_type_size(a_tma.tma_memref) + size_tma_b = get_type_size(b_tma.tma_memref) + ta_count = size_tma_a + (size_tma_b * 2) + + off_b = size_tma_a + off_b2 = off_b + size_tma_b + a_elem_ty = a_tma.tma_memref.element_type + b_elem_ty = b_tma.tma_memref.element_type + a = get_dynamic_shared_memory(a_tma.tma_memref.shape, a_elem_ty) + b1 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b) + b2 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b2) + + mbar_group[0].arrive(ta_count, predicate=p) + + a_tma.load(a, mbar_group[0], coords=[0, 0], predicate=p) + b_tma.load(b1, mbar_group[0], coords=[0, 0], predicate=p) + b_tma.load(b2, mbar_group[0], coords=[64, 0], predicate=p) + + +@NVDSL.mlir_func +def gemm_128_128_64(a, b, d): + token_ty = ir.Type.parse("!gpu.async.token") + t1 = gpu.wait(token_ty, []) + a_dev, t2 = gpu.alloc(a.type, token_ty, [t1], [], []) + b_dev, t3 = gpu.alloc(b.type, token_ty, [t2], [], []) + d_dev, t4 = gpu.alloc(d.type, token_ty, [t3], [], []) + t5 = gpu.memcpy(token_ty, [t4], a_dev, a) + t6 = gpu.memcpy(token_ty, [t5], b_dev, b) + t7 = gpu.wait(token_ty, [t6]) + + sw = nvgpu.TensorMapSwizzleKind.SWIZZLE_128B + a_tma = TMA([128, 64], a.type, swizzle=sw) + b_tma = TMA([64, 64], b.type, swizzle=sw) + a_tma.create_descriptor(a_dev) + b_tma.create_descriptor(b_dev) + a_size = get_type_size(a.type) + b_size = get_type_size(b.type) + smem_size_in_bytes = a_size + b_size + + @NVDSL.mlir_gpu_launch(grid=(1, 1, 1), block=(128, 1, 1), smem=smem_size_in_bytes) + def gemm_tma_kernel(): + tidx = gpu.thread_id(gpu.Dimension.x) + + mbar_group = Mbarriers(number_of_barriers=1) + isThread0 = tidx == 0 + + mbar_group[0].init(1, predicate=isThread0) + a_tma.prefetch(predicate=isThread0) + b_tma.prefetch(predicate=isThread0) + + a_smem = get_dynamic_shared_memory((M, K), T.f16()) + b_smem = get_dynamic_shared_memory((K, N), T.f16(), offset=a_size) + + # 1. TMA Load for two input matrices + tma_load(mbar_group, a_tma, b_tma, isThread0) + + # 2. All threads wait TMA load completion + mbar_group[0].try_wait() + + # 3. Performs Tensor Core GEMM 128x128x64 by warpgroup + A = WGMMAMatrix(WGMMAType.Descriptor, [M, K], desc=a_tma, smem=a_smem) + B = WGMMAMatrix(WGMMAType.Descriptor, [K, N], desc=b_tma, smem=b_smem) + D = WGMMAMatrix(WGMMAType.Accumulator, shape=[M, N], ty=T.f32()) + + # Matrix Multiply + D += A @ B + + # 4. Stores fragmented registers to global memory by warpgroup + D.store_accumulator(d_dev) + + gemm_tma_kernel() + + t8 = gpu.memcpy(token_ty, [t7], d, d_dev) + gpu.wait(None, [t8]) + + +# Python pass arguments to MLIR +M = 128 +N = 128 +K = 64 +a = np.random.randn(M, K).astype(np.float16) +b = np.random.randn(K, N).astype(np.float16) +d = np.zeros((M, N), np.float32) +gemm_128_128_64(a, b, d) + +ref_d = a.astype(np.float16) @ b.astype(np.float16) +np.testing.assert_allclose(d, ref_d, rtol=5e-03, atol=1e-01) +print("PASS") +# CHECK-NOT: Mismatched elements diff --git a/mlir/test/Examples/NVGPU/Ch4.py b/mlir/test/Examples/NVGPU/Ch4.py new file mode 100644 index 0000000000000000000000000000000000000000..8f38d8a90add31c30d45b7a3d3635258eeecc3ef --- /dev/null +++ b/mlir/test/Examples/NVGPU/Ch4.py @@ -0,0 +1,323 @@ +# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \ +# RUN: %PYTHON %s | FileCheck %s + +# ===----------------------------------------------------------------------===// +# Chapter 4 : Multistage GEMM with Tensor Core +# ===----------------------------------------------------------------------===// +# +# This program exemplifies a GEMM operation for `f32+=f16*f16`, utilizing the +# Multistage method with a tile size of 128x128x64. The code completely +# parallelizes the two outermost loops into thread blocks. It launches one Warp +# Groups (128 threads in total) and allocates multiple slots/stage in the +# shared memory. The program consists of three main parts: prologue, mainloop, +# and epilogue. In the prologue, thread0 requests for TMA to load data into +# shared memory slots. The mainloop executes MMA while simultaneously loading +# TMA for the utilized slots. This overlap of TMA and MMA operations enhances +# performance by maximizing computational throughput. +# +# Loops illustration: +# +# for s in range(num_stages): +# TMA_128x64_64x128... +# for ti in range(M//128): # -> blockIdx.x +# for tj in range(N//128): # -> blockIdx.y +# for tk in range(K//64): +# MMA_128x128x64... +# TMA_128x64_64x128... +# Epilogue... +# +# This chapter introduces demonstrates: +# 1. Partition shape based on block IDs +# 2. Prologue +# 2.1 Execute TMA Load for two input matrices for each stage +# 3. Main loop +# 3.1 Wait for completion of TMA load with mbarrier +# 3.2 Performs Tensor Core GEMM 64x128x64 by warpgroup +# 3.3 Load next stage if needed +# 4. Epilogue +# 4.1 Store fragmented registers to shared memory +# 4.2 Store shared memory to global +# +# ===----------------------------------------------------------------------===// + + +from mlir import ir +from mlir.dialects import gpu, scf, nvgpu, nvvm +from mlir.extras import types as T +from tools.nvdsl import * +import numpy as np + + +def partition_shape(): + """ + Calculate the partition shape based on the block IDs. + + It partitions the shape like below: + for(.. i < M ...) --> blockIdx.x + for(.. j < N ...) --> blockIdx.y + for(.. k < K ...) + + Returns: + dimX (int): Dimension along the x-axis. + dimY (int): Dimension along the y-axis. + """ + bidx = gpu.block_id(gpu.Dimension.x) + bidy = gpu.block_id(gpu.Dimension.y) + dimX = bidx * TILE_M + dimY = bidy * TILE_N + return dimX, dimY + + +def tma_load( + mbar_group: Mbarriers, + a_tma: TMA, + b_tma: TMA, + slot, + stage, + num_stages, + p=None, +): + """ + TMA loads two input matrices from global memory to shared memory. It performs the following operations: + + - tma.load a_shared_memory[off_x] at coordinate [x, z] (Loads 128x64) + - tma.load b_shared_memory[off_y1] at coordinate [y, x] (Loads 64x64) + - tma.load b_shared_memory[off_y2] at coordinate [y + 64, x] (Loads 64x64) + + mbarrier.arrive ta_count = 128x64x2x4 + """ + dimX, dimY = partition_shape() + + tidx = gpu.thread_id(gpu.Dimension.x) + begin_b = num_stages * get_type_size(a_tma.tma_memref) + size_tma_a = get_type_size(a_tma.tma_memref) + size_tma_b = get_type_size(b_tma.tma_memref) + ta_count = size_tma_a + (size_tma_b * 2) + tidx = gpu.thread_id(gpu.Dimension.x) + + p = tidx == 0 if p is None else p + + off_a = slot * size_tma_a + off_b = (slot * size_tma_a) + begin_b + off_b2 = off_b + size_tma_b + a_elem_ty = a_tma.tma_memref.element_type + b_elem_ty = b_tma.tma_memref.element_type + a = get_dynamic_shared_memory(a_tma.tma_memref.shape, a_elem_ty, off_a) + b1 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b) + b2 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b2) + + mbar_group[slot].arrive(ta_count, predicate=p) + + c1 = stage * 64 + a_tma.load(a, mbar_group[slot], coords=[c1, dimX], predicate=p) + b_tma.load(b1, mbar_group[slot], coords=[dimY, c1], predicate=p) + b_tma.load(b2, mbar_group[slot], coords=[dimY + 64, c1], predicate=p) + + +def initialize(a_tma: TMA, b_tma: TMA, num_stages): + """ + Initialize mbarriers and prefetch TMA descriptors. + """ + tidx = gpu.thread_id(gpu.Dimension.x) + mbar_group = Mbarriers(number_of_barriers=num_stages) + isThread0 = tidx == const(0) + with ir.InsertionPoint(scf.IfOp(isThread0).then_block): + for i in scf.for_(0, num_stages, 1): + mbar_group[i].init(1) + scf.yield_([]) + a_tma.prefetch() + b_tma.prefetch() + scf.yield_([]) + + return mbar_group + + +def prologue(mbar_group: Mbarriers, a_tma: TMA, b_tma: TMA, num_stages): + """ + Prologue of the GEMM kernel. It loads 2 input matrices for each stage in loop like below: + + for stage in range(NUM_STAGES): + tma_load x, y, stage + + """ + ns = num_stages if num_stages == 1 else num_stages - 1 + for iv in scf.for_(0, ns, 1): + tma_load(mbar_group, a_tma, b_tma, iv, iv, num_stages) + scf.yield_([]) + + +def mainloop(mbar_group: Mbarriers, a_tma: TMA, b_tma: TMA, num_stages): + """ + Main loop of the Multistage GEMM kernel. It iterates through + stages and performs matrix multiplication, loading data by TMA to shared memory. It like following + + MatrixAccumulator D + for k in range(K // TILE_K): + + try_wait(stage, ...) # Wait TMA load + + Matrix A(stage, ...) # Find shared memory slot + Matrix B(stage, ...) # Find shared memory slot + D += A @ B # Multiply and accumulate + + if(needLoad) # Load next stage if needed + tma_load(x, y, nextSlot, nextStage) + + """ + ns = num_stages if num_stages == 1 else num_stages - 1 + + tidx = gpu.thread_id(gpu.Dimension.x) + begin_b = num_stages * get_type_size(a_tma.tma_memref) + + size_a = TILE_M * TILE_K * get_type_size(T.f16()) + + # Initialize A and B (input matrices) and C (accumulator) + A = WGMMAMatrix(WGMMAType.Descriptor, [TILE_M, TILE_K], desc=a_tma) + B = WGMMAMatrix(WGMMAType.Descriptor, [TILE_K, TILE_N], desc=b_tma) + D = WGMMAMatrix(WGMMAType.Accumulator, shape=[TILE_M, TILE_N], ty=T.f32()) + + phase = const(False, ty=T.bool()) + + # Main Loop + for_op = scf.ForOp(const(0), const(K // TILE_K), const(1), [D.acc_op, phase]) + with ir.InsertionPoint(for_op.body): + phase = for_op.inner_iter_args[1] + iv = for_op.induction_variable + stage = iv % num_stages + + # Wait for current stage + mbar_group[stage].try_wait(phase=phase) + + # Find shared memory slot + offset_a = stage * size_a + offset_b = offset_a + begin_b + a_smem = get_dynamic_shared_memory([TILE_M, TILE_K], T.f16(), offset_a) + b_smem = get_dynamic_shared_memory([TILE_K, TILE_N], T.f16(), offset_b) + + # Iterate input matrices, update accumulator + A.update_smem(a_smem) + B.update_smem(b_smem) + D.update_accumulator(for_op.inner_iter_args[0]) + + # Matrix Multiply + D += A @ B + + # Wait Tensor Core for single stage + if num_stages == 1: + nvvm.WgmmaWaitGroupSyncOp(0) + + # Load next stage + pred = ((iv + ns) < const(K // TILE_K)) & (tidx == 0) + nextStage = iv + ns + nextSlot = nextStage % num_stages + tma_load(mbar_group, a_tma, b_tma, nextSlot, nextStage, num_stages, pred) + + # Switch phase parity for the mbarrier + newPhase = arith.select( + stage == (num_stages - 1), + (phase ^ const(True, ty=T.bool())), + phase, + ) + scf.yield_([D.acc_op, newPhase]) + + nvvm.WgmmaWaitGroupSyncOp(0) + + D.update_accumulator(for_op.results[0]) + return D + + +def epilogue(D: WGMMAMatrix, d_dev): + """ + Epilogue of the GEMM kernel. It stores the fragmented registers to global memory. + + MatrixAccumulator D # Fragmented results + store D -> Shared Memory # Store Shared Memory + Shared Memory -> Z[dimX][dimY] # Store Shared Memory to Global Memory + + """ + tidx = gpu.thread_id(gpu.Dimension.x) + dimX, dimY = partition_shape() + + d_smem = get_dynamic_shared_memory([TILE_M, TILE_N], T.f32()) + d_gmem = memref.subview(d_dev, [dimX, dimY], [TILE_M, TILE_N], [1, 1]) + + # Store (registers -> shared memory) + D.store_accumulator(d_smem) + gpu.barrier() + + # Store (shared memory --> global memory) + for i in scf.for_(0, TILE_M, 1): + val = memref.load(d_smem, [i, tidx]) + memref.store(val, d_gmem, [i, tidx]) + scf.yield_([]) + + +# The decorator generates +# a -> memref +# b -> memref +# d -> memref +@NVDSL.mlir_func +def gemm_multistage(a, b, d, num_stages): + token_ty = ir.Type.parse("!gpu.async.token") + t1 = gpu.wait(token_ty, []) + a_dev, t2 = gpu.alloc(a.type, token_ty, [t1], [], []) + b_dev, t3 = gpu.alloc(b.type, token_ty, [t2], [], []) + d_dev, t4 = gpu.alloc(d.type, token_ty, [t3], [], []) + t5 = gpu.memcpy(token_ty, [t4], a_dev, a) + t6 = gpu.memcpy(token_ty, [t5], b_dev, b) + t7 = gpu.wait(token_ty, [t6]) + + sw = nvgpu.TensorMapSwizzleKind.SWIZZLE_128B + a_tma = TMA([128, 64], a.type, swizzle=sw) + b_tma = TMA([64, 64], b.type, swizzle=sw) + a_tma.create_descriptor(a_dev) + b_tma.create_descriptor(b_dev) + + grid = [(M // TILE_M), (N // TILE_N), 1] + block = [128, 1, 1] + + size_a = get_type_size(a.type.element_type) * TILE_M * TILE_K + size_b = get_type_size(b.type.element_type) * TILE_N * TILE_K + smem_size_in_bytes = (size_a + size_b) * num_stages + + @NVDSL.mlir_gpu_launch(grid=grid, block=block, smem=smem_size_in_bytes) + def gemm_multistage_kernel(): + # Initialize mbarriers and prefetch TMA descriptors + mbar_group = initialize(a_tma, b_tma, num_stages) + + # Fill the pipeline stages + prologue(mbar_group, a_tma, b_tma, num_stages) + + # Main loop + D = mainloop(mbar_group, a_tma, b_tma, num_stages) + + # Store registers to global memory + epilogue(D, d_dev) + + gemm_multistage_kernel() + + t8 = gpu.memcpy(token_ty, [t7], d, d_dev) + gpu.wait(None, [t8]) + + +# Python pass arguments to MLIR +N = 256 +M = 512 +K = 1024 +TILE_M = 128 +TILE_N = 128 +TILE_K = 64 +a = np.random.randn(M, K).astype(np.float16) +b = np.random.randn(K, N).astype(np.float16) +d = np.zeros((M, N), np.float32) + +gemm_multistage(a, b, d, num_stages=7) + + +# Verify MLIR with reference computation +ref_d = a.astype(np.float16) @ b.astype(np.float16) +np.testing.assert_allclose(d, ref_d, rtol=5e-03, atol=1e-01) + + +print("PASS") +# CHECK-NOT: Mismatched elements diff --git a/mlir/test/Examples/NVGPU/Ch5.py b/mlir/test/Examples/NVGPU/Ch5.py new file mode 100644 index 0000000000000000000000000000000000000000..92e9314e1b812d5a36d23c76c47ad73ed9bcb30f --- /dev/null +++ b/mlir/test/Examples/NVGPU/Ch5.py @@ -0,0 +1,321 @@ +# RUN: env SUPPORT_LIB=%mlir_cuda_runtime \ +# RUN: %PYTHON %s | FileCheck %s + +# ===----------------------------------------------------------------------===// +# Chapter 5 : Warp Specialized GEMM with Tensor Core +# ===----------------------------------------------------------------------===// +# +# This program demonstrates a GEMM operation for `f32+=f16*f16`, utilizing the +# Warp Specialized method with a tile size of 128x128x64. The code completely +# parallelizes the two outermost loops into thread blocks. It launches two Warp +# Groups (256 threads in total): one for the producer and the other for the consumer. +# Each group takes a different control-flow. The producer thread group is responsible +# for loading data into shared memory, while the consumer group executes the Tensor +# Core GEMM operation and epilogue. +# +# for ti in range(M//128): # -> blockIdx.x +# for tj in range(N//128): # -> blockIdx.y +# with wg_producer: +# for tk in range(K//64): +# TMA_128x64_64x128... +# with wg_consumer: +# for tk in range(K//64): +# MMA_128x128x64... +# Epilogue.. +# +# This chapter demonstrates: +# 2 WG (warpgroups) +# Producer: +# 2.1.1 Wait MMA Barrier +# 2.1.1 Load TMA with TMA barrier +# 2.1.1 Arrive TMA barrier with txcount +# Consumer: +# Loop +# Wait TMA barrier +# Performs Tensor Core GEMM 64x128x64 by warpgroup +# Arrive MMA Barrier +# Epilogue +# Store fragmented registers to shared memory +# Store shared memory to global +# +# ===----------------------------------------------------------------------===// + + +from mlir import ir +from mlir.dialects import gpu, scf, nvgpu, nvvm +from mlir.extras import types as T +from tools.nvdsl import * +import numpy as np + + +def partition_shape(): + """ + Calculate the partition shape based on the block IDs. + + It parallelizes the two outermost loops into thread blocks. + for ti in range(M//128): # -> blockIdx.x + for tj in range(N//128): # -> blockIdx.y + D = 0 + for tk in range(K//64): + for i in range(128): + for j in range(128): + for k in range(64): + FMA + + Returns: + dimX (int): Dimension along the x-axis. + dimY (int): Dimension along the y-axis. + """ + bidx = gpu.block_id(gpu.Dimension.x) + bidy = gpu.block_id(gpu.Dimension.y) + dimX = bidx * TILE_M + dimY = bidy * TILE_N + return dimX, dimY + + +def tma_load( + mbar_group: Mbarriers, + a_tma: TMA, + b_tma: TMA, + slot, + stage, + num_stages, + p=None, +): + """ + TMA loads two input matrices from global memory to shared memory. It performs the following operations: + + - tma.load a_shared_memory[off_x] at coordinate [x, z] (Loads 128x64) + - tma.load b_shared_memory[off_y1] at coordinate [y, x] (Loads 64x64) + - tma.load b_shared_memory[off_y2] at coordinate [y + 64, x] (Loads 64x64) + + mbarrier.arrive ta_count = 128x64x2x4 + """ + dimX, dimY = partition_shape() + + tidx = gpu.thread_id(gpu.Dimension.x) + begin_b = num_stages * get_type_size(a_tma.tma_memref) + size_tma_a = get_type_size(a_tma.tma_memref) + size_tma_b = get_type_size(b_tma.tma_memref) + ta_count = size_tma_a + (size_tma_b * 2) + + off_a = slot * size_tma_a + off_b = (slot * size_tma_a) + begin_b + off_b2 = off_b + size_tma_b + a_elem_ty = a_tma.tma_memref.element_type + b_elem_ty = b_tma.tma_memref.element_type + a = get_dynamic_shared_memory(a_tma.tma_memref.shape, a_elem_ty, off_a) + b1 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b) + b2 = get_dynamic_shared_memory(b_tma.tma_memref.shape, b_elem_ty, off_b2) + + mbar_group[slot].arrive(ta_count, predicate=p) + p = (tidx % WARP_GROUP_SIZE) == 0 + c1 = stage * 64 + a_tma.load(a, mbar_group[slot], coords=[c1, dimX], predicate=p) + b_tma.load(b1, mbar_group[slot], coords=[dimY, c1], predicate=p) + b_tma.load(b2, mbar_group[slot], coords=[dimY + 64, c1], predicate=p) + + +def initialize(a_tma: TMA, b_tma: TMA, num_stages): + """ + Initialize mbarriers and prefetch TMA descriptors. + """ + tidx = gpu.thread_id(gpu.Dimension.x) + mbar_group_tma = Mbarriers(number_of_barriers=num_stages) + mbar_group_mma = Mbarriers(number_of_barriers=num_stages) + isThread0 = tidx == const(0) + with ir.InsertionPoint(scf.IfOp(isThread0).then_block): + for i in scf.for_(0, num_stages, 1): + mbar_group_tma[i].init(1) + mbar_group_mma[i].init(1) + scf.yield_([]) + a_tma.prefetch() + b_tma.prefetch() + scf.yield_([]) + + return mbar_group_tma, mbar_group_mma + + +def switch_phase(stage, phase, num_stages): + p = stage == (num_stages - 1) + phase = arith.select( + p, + (phase ^ const(True, ty=T.bool())), + phase, + ) + return phase + + +def producer_loop( + mbar_tma: Mbarriers, + mbar_mma: Mbarriers, + a_tma: TMA, + b_tma: TMA, + wg_me: Warpgroup, + num_stages, +): + phase = const(True, ty=T.bool()) + + for iv, phase in scf.for_(0, (K // TILE_K), 1, [phase]): + stage = iv % num_stages + # Wait MMA to be done + mbar_mma[stage].try_wait(phase) + # New phase for mbarrier + phase = switch_phase(stage, phase, num_stages) + # TMA Load + tma_load(mbar_tma, a_tma, b_tma, stage, iv, num_stages, wg_me.is_wg_primary) + scf.yield_([phase]) + + +def consumer_loop( + mbar_tma: Mbarriers, + mbar_mma: Mbarriers, + a_tma: TMA, + b_tma: TMA, + wg_me: Warpgroup, + num_stages, +): + begin_b = num_stages * get_type_size(a_tma.tma_memref) + + size_a = TILE_M * TILE_K * get_type_size(T.f16()) + + phase = const(False, ty=T.bool()) + A = WGMMAMatrix(WGMMAType.Descriptor, [TILE_M, TILE_K], desc=a_tma) + B = WGMMAMatrix(WGMMAType.Descriptor, [TILE_K, TILE_N], desc=b_tma) + D = WGMMAMatrix(WGMMAType.Accumulator, shape=[TILE_M, TILE_N], ty=T.f32()) + + for_op = scf.ForOp(const(0), const(K // TILE_K), const(1), [D.acc_op, phase]) + with ir.InsertionPoint(for_op.body): + phase = for_op.inner_iter_args[1] + iv = for_op.induction_variable + stage = iv % num_stages + + # Wait TMA for current stage + mbar_tma[stage].try_wait(phase) + + # Find shared memory slot + offset_a = stage * size_a + offset_b = offset_a + begin_b + a_smem = get_dynamic_shared_memory([TILE_M, TILE_K], T.f16(), offset_a) + b_smem = get_dynamic_shared_memory([TILE_K, TILE_N], T.f16(), offset_b) + + # Iterate input matrices, update accumulator + A.update_smem(a_smem) + B.update_smem(b_smem) + D.update_accumulator(for_op.inner_iter_args[0]) + + # Matrix Multiply + D += A @ B + + # MMA Barrier Arrive + p_arrive = (iv > 0) & wg_me.is_wg_primary + with ir.InsertionPoint(scf.IfOp(p_arrive).then_block): + barId = arith.select((stage == 0), const(num_stages - 1), (stage - 1)) + mbar_mma[barId].arrive() + scf.yield_([]) + + phase = switch_phase(stage, phase, num_stages) + scf.yield_([D.acc_op, phase]) + + nvvm.WgmmaWaitGroupSyncOp(0) + D.update_accumulator(for_op.results[0]) + return D + + +def epilogue(D: WGMMAMatrix, d_dev): + """ + Epilogue of the GEMM kernel. It stores the fragmented registers to global memory. + + MatrixAccumulator D # Fragmented results + store D -> Shared Memory # Store Shared Memory + Shared Memory -> Z[dimX][dimY] # Store Shared Memory to Global Memory + + """ + tidx = gpu.thread_id(gpu.Dimension.x) + dimX, dimY = partition_shape() + # s = tidx - WARP_GROUP_SIZE + # debug_print("[Epilogue] store to global memory @ s={}", s) + + d_smem = get_dynamic_shared_memory([TILE_M, TILE_N], T.f32()) + d_gmem = memref.subview(d_dev, [dimX, dimY], [TILE_M, TILE_N], [1, 1]) + + # Store (registers -> shared memory) + D.store_accumulator(d_smem) + gpu.barrier() + + # Store (shared memory --> global memory) + for i in scf.for_(0, TILE_M, 1): + val = memref.load(d_smem, [i, tidx]) + memref.store(val, d_gmem, [i, tidx]) + scf.yield_([]) + + +@NVDSL.mlir_func +def gemm_warp_specialized(a, b, d, num_stages): + token_ty = ir.Type.parse("!gpu.async.token") + t1 = gpu.wait(token_ty, []) + a_dev, t2 = gpu.alloc(a.type, token_ty, [t1], [], []) + b_dev, t3 = gpu.alloc(b.type, token_ty, [t2], [], []) + d_dev, t4 = gpu.alloc(d.type, token_ty, [t3], [], []) + t5 = gpu.memcpy(token_ty, [t4], a_dev, a) + t6 = gpu.memcpy(token_ty, [t5], b_dev, b) + t7 = gpu.wait(token_ty, [t6]) + + sw = nvgpu.TensorMapSwizzleKind.SWIZZLE_128B + a_tma = TMA([128, 64], a.type, swizzle=sw) + b_tma = TMA([64, 64], b.type, swizzle=sw) + a_tma.create_descriptor(a_dev) + b_tma.create_descriptor(b_dev) + + grid = [(M // TILE_M), (N // TILE_N), 1] + block = [256, 1, 1] + + size_a = get_type_size(a.type.element_type) * TILE_M * TILE_K + size_b = get_type_size(b.type.element_type) * TILE_N * TILE_K + smem_size_in_bytes = (size_a + size_b) * num_stages + + @NVDSL.mlir_gpu_launch(grid=grid, block=block, smem=smem_size_in_bytes) + def gemm_warp_specialized_kernel(): + # Init Warpgroups + wg_producer = Warpgroup(primary_thread=128, register_size=40) + wg_consumer = Warpgroup(primary_thread=0, register_size=232) + + # Initialize mbarriers and prefetch TMA descriptors + mbar_mma, mbar_tma = initialize(a_tma, b_tma, num_stages) + + # Producer performs TMA + with wg_producer: + producer_loop(mbar_tma, mbar_mma, a_tma, b_tma, wg_producer, num_stages) + + # Consumer performs MMA/Tensor Core + with wg_consumer: + D = consumer_loop(mbar_tma, mbar_mma, a_tma, b_tma, wg_consumer, num_stages) + epilogue(D, d_dev) + + gemm_warp_specialized_kernel() + + t8 = gpu.memcpy(token_ty, [t7], d, d_dev) + gpu.wait(None, [t8]) + + +# Python pass arguments to MLIR +N = 256 +M = 512 +K = 1024 +TILE_M = 128 +TILE_N = 128 +TILE_K = 64 +a = np.random.randn(M, K).astype(np.float16) +b = np.random.randn(K, N).astype(np.float16) +d = np.zeros((M, N), np.float32) + +gemm_warp_specialized(a, b, d, num_stages=7) + + +# Verify MLIR with reference computation +ref_d = a.astype(np.float16) @ b.astype(np.float16) +np.testing.assert_allclose(d, ref_d, rtol=5e-03, atol=1e-01) + + +print("PASS") +# CHECK-NOT: Mismatched elements diff --git a/mlir/test/Examples/NVGPU/lit.local.cfg b/mlir/test/Examples/NVGPU/lit.local.cfg new file mode 100644 index 0000000000000000000000000000000000000000..689cd252e7a254f0b6276673d9aefa0f009c27ea --- /dev/null +++ b/mlir/test/Examples/NVGPU/lit.local.cfg @@ -0,0 +1,4 @@ +config.unsupported = False +if not config.enable_cuda_runner or not config.mlir_run_cuda_sm90_tests: + config.unsupported = True + \ No newline at end of file diff --git a/mlir/test/Examples/NVGPU/tools/lit.local.cfg b/mlir/test/Examples/NVGPU/tools/lit.local.cfg new file mode 100644 index 0000000000000000000000000000000000000000..d9f34f219c4d955fdf66804369eff8524edf60e2 --- /dev/null +++ b/mlir/test/Examples/NVGPU/tools/lit.local.cfg @@ -0,0 +1,3 @@ +# Files in this directory are tools, not tests. +config.unsupported = True + diff --git a/mlir/test/Examples/NVGPU/tools/nvdsl.py b/mlir/test/Examples/NVGPU/tools/nvdsl.py new file mode 100644 index 0000000000000000000000000000000000000000..600cae5b47eeecdae5f79b961f0f483c90a254ee --- /dev/null +++ b/mlir/test/Examples/NVGPU/tools/nvdsl.py @@ -0,0 +1,456 @@ +from enum import Enum +import functools, sys, ctypes, os, errno +import numpy as np +from functools import partialmethod +from mlir import ir +from mlir.dialects import arith, func, gpu, memref, nvgpu, scf, nvvm +from mlir.extras import types as T +from mlir import runtime as rt +from tools import nvgpucompiler + +MLIR_DYNAMIC = -9223372036854775808 + + +def const(value: int, ty=None): + ty = T.index() if ty is None else ty + if isinstance(value, ir.Value) and ( + value.type.isinstance(value.type) or T.bool().isinstance(value.type) + ): + return value + return arith.constant(ty, value) + + +def get_type_size(ty): + if ir.MemRefType.isinstance(ty): + size = get_type_size(ty.element_type) + for sz in ty.shape: + size *= sz + return size + if ir.FloatType.isinstance(ty): + return ir.FloatType(ty).width // 8 + if ir.IntegerType.isinstance(ty): + return ir.IntegerType(ty).width // 8 + raise NotImplementedError(ty) + + +def get_mlir_func_obj_ty(inputArgs): + args = [] + c_int_p = ctypes.c_int * 1 + c_float_p = ctypes.c_float * 1 + c_bool_p = ctypes.c_bool * 1 + for arg in inputArgs: + if isinstance(arg, bool): + args.append(c_bool_p(arg)) + elif isinstance(arg, int): + args.append(c_int_p(arg)) + elif isinstance(arg, float): + args.append(c_float_p(arg)) + elif isinstance(arg, np.ndarray): + args.append( + ctypes.pointer(ctypes.pointer(rt.get_ranked_memref_descriptor(arg))) + ) + else: + raise NotImplementedError(arg) + return args + + +class Mbarriers: + def __init__(self, number_of_barriers=1): + self.mbar_ty = ir.Type.parse( + "!nvgpu.mbarrier.group, num_barriers = " + + str(number_of_barriers) + + ">" + ) + self.mbar_group_op = nvgpu.mbarrier_create(self.mbar_ty) + self.number_of_barriers = number_of_barriers + + def __getitem__(self, key): + self.id_op = const(key) + return self + + def init(self, count: int, predicate=None): + count_op = const(count) + if predicate is None: + nvgpu.mbarrier_init(self.mbar_group_op, count_op, self.id_op) + else: + nvgpu.mbarrier_init( + self.mbar_group_op, count_op, self.id_op, predicate=predicate + ) + + def arrive(self, txcount: int = 0, predicate=None): + if txcount != 0: + txcount_op = const(txcount) + nvgpu.mbarrier_arrive_expect_tx( + self.mbar_group_op, txcount_op, self.id_op, predicate=predicate + ) + else: + nvgpu.mbarrier_arrive( + ir.Type.parse("!nvgpu.mbarrier.token"), self.mbar_group_op, self.id_op + ) + + def try_wait(self, phase: bool = False, ticks: int = 10000000): + ticks_op = const(ticks) + phase_op = const(phase, T.bool()) + nvgpu.MBarrierTryWaitParityOp( + self.mbar_group_op, + phase_op, + ticks_op, + mbarId=self.id_op, + ) + + +class TMA: + """A class that builds a TMA descriptor.""" + + def __init__( + self, + tma_box_shape, + memref_ty, + swizzle=nvgpu.TensorMapSwizzleKind.SWIZZLE_NONE, + l2promo=nvgpu.TensorMapL2PromoKind.L2PROMO_NONE, + oob=nvgpu.TensorMapOOBKind.OOB_ZERO, + interleave=nvgpu.TensorMapInterleaveKind.INTERLEAVE_NONE, + ): + self.swizzle = swizzle # mlir.nvgpu.TensorMapSwizzleKind + self.l2promo = l2promo # mlir.nvgpu.TensorMapL2PromoKind + self.oob = oob # mlir.nvgpu.TensorMapOOBKind + self.interleave = interleave # mlir.nvgpu.TensorMapInterleaveKind + self.tma_box_shape = tma_box_shape + self.memref_ty = memref_ty # MemRefType + self.tma_memref = ir.MemRefType.get(tma_box_shape, memref_ty.element_type) + + @property + def tensormap_descriptor_ty(self): + """Returns a tensormap descriptor type.""" + tensorMemrefType = ir.MemRefType.get( + self.tma_box_shape, + self.memref_ty.element_type, + memory_space=ir.Attribute.parse("3"), + ) + return nvgpu.TensorMapDescriptorType.get( + tensorMemrefType, + self.swizzle, + self.l2promo, + self.oob, + self.interleave, + ) + + def create_descriptor(self, device_ptr): + tma_descriptor_ty = self.tensormap_descriptor_ty + device_unranked_memref = memref.CastOp( + ir.UnrankedMemRefType.get( + self.memref_ty.element_type, self.memref_ty.memory_space + ), + device_ptr, + ) + self.tma_descriptor = nvgpu.TmaCreateDescriptorOp( + tma_descriptor_ty, device_unranked_memref, map(const, self.tma_box_shape) + ) + return self.tma_descriptor.result + + def prefetch(self, predicate=None): + nvgpu.tma_prefetch_descriptor(self.tma_descriptor, predicate=predicate) + + def load(self, dest, mbarrier: Mbarriers, coords=[0], predicate=None): + nvgpu.TmaAsyncLoadOp( + dest, + mbarrier.mbar_group_op, + self.tma_descriptor, + coordinates=map(const, coords), + mbarId=mbarrier.id_op, + predicate=predicate, + ) + + +WARP_GROUP_SIZE = 128 # Number of threads in a warpgroup + + +class Warpgroup: + def __init__(self, primary_thread, register_size): + assert (primary_thread % WARP_GROUP_SIZE) == 0 + tidx = gpu.thread_id(gpu.Dimension.x) + self.primary_thread = primary_thread + self.register_size = register_size + self.is_wg_primary = (tidx % WARP_GROUP_SIZE) == 0 + self.wg_id = tidx / WARP_GROUP_SIZE + self.is_me = self.wg_id == (primary_thread // WARP_GROUP_SIZE) + + def __enter__(self): + if_op = scf.IfOp(self.is_me) + self.ipoint_op = ir.InsertionPoint(if_op.then_block) + self.ipoint_op.__enter__() + if self.register_size < 64: + nvvm.setmaxregister(self.register_size, nvvm.SetMaxRegisterAction.decrease) + else: + nvvm.setmaxregister(self.register_size, nvvm.SetMaxRegisterAction.increase) + + def __exit__(self, exc_type, exc_value, traceback): + scf.yield_([]) + self.ipoint_op.__exit__(exc_type, exc_value, traceback) + return True + + +class WGMMAType(Enum): + Accumulator = 1 + Descriptor = 2 + + +class WGMMAMatrix: + def __init__( + self, + matrix_type: WGMMAType, + shape: list = None, + desc: TMA = None, + smem=None, + ty=None, + acc_op=None, + ): + if acc_op is None: + self.M = shape[0] + self.N = shape[1] + self.ty = ty + self.matrix_type = matrix_type + self.desc = desc + self.smem = smem + if matrix_type is WGMMAType.Accumulator: + self.acc_op = nvgpu.warpgroup_mma_init_accumulator(self.acc_ty) + elif acc_op: + self.acc_op = acc_op + self.matrix_type = WGMMAType.Accumulator + + @property + def acc_ty(self): + parse_str = f"!nvgpu.warpgroup.accumulator>" + return ir.Type.parse(parse_str) + + @property + def wgmma_ty(self): + parse_str = f"!nvgpu.warpgroup.descriptor>>" + return ir.Type.parse(parse_str) + + def store_accumulator(self, dest): + assert self.matrix_type == WGMMAType.Accumulator + nvgpu.warpgroup_mma_store(self.acc_op, dest) + + def update_smem(self, smem): + self.smem = smem + + def update_accumulator(self, acc_op): + self.acc_op = acc_op + + def __matmul__(self, rhs): + lhs = nvgpu.warpgroup_generate_descriptor( + self.wgmma_ty, self.smem, self.desc.tma_descriptor + ) + rhs = nvgpu.warpgroup_generate_descriptor( + rhs.wgmma_ty, rhs.smem, rhs.desc.tma_descriptor + ) + return [lhs, rhs] + + def __iadd__(self, matmulResult): + lhs = matmulResult[0] + rhs = matmulResult[1] + acc_op = nvgpu.WarpgroupMmaOp( + self.acc_op.type, lhs, rhs, self.acc_op, transposeB=True + ) + return WGMMAMatrix(WGMMAType.Accumulator, acc_op=acc_op) + + +def get_dynamic_shared_memory(shape=None, ty=None, offset: int = 0): + smem_space_str = "#gpu.address_space" + smem_space = ir.Attribute.parse(smem_space_str) + dynamic_smem = gpu.dynamic_shared_memory( + ir.MemRefType.get((MLIR_DYNAMIC,), T.i8(), memory_space=smem_space) + ) + if shape is None: + return dynamic_smem + memref_ty = ir.MemRefType.get(shape, ty, memory_space=smem_space) + return memref.view( + ir.MemRefType.get( + memref_ty.shape, memref_ty.element_type, memory_space=smem_space + ), + dynamic_smem, + const(offset), + [], + ) + + +def get_mlir_ty(arg): + def get_mlir_ty_from_np(dtype): + if dtype == np.float16: + return T.f16() + if dtype == np.float32: + return T.f32() + if dtype == np.float64: + return T.f64() + if dtype == np.int32: + return T.i32() + if dtype == np.int64: + return T.i64() + raise NotImplementedError(dtype) + + if isinstance(arg, bool): + return T.bool() + elif isinstance(arg, int): + return T.index() + elif isinstance(arg, float): + return T.f32() + elif isinstance(arg, np.ndarray): + descriptor = rt.get_ranked_memref_descriptor(arg) + dtype = get_mlir_ty_from_np(arg.dtype) + shape = descriptor.shape + return memref.MemRefType.get(shape, dtype) + raise NotImplementedError(arg) + + +class NVDSL: + @staticmethod + def mlir_gpu_launch(grid=(1, 1, 1), block=(1, 1, 1), smem=0): + def decorator(func): + @functools.wraps(func) + def wrapper(*args, **kwargs): + launch_op = gpu.LaunchOp( + None, + [], + *map(const, grid), + *map(const, block), + dynamicSharedMemorySize=arith.constant(T.i32(), smem), + ) + launch_op.body.blocks.append(*([T.index()] * 12)) + with ir.InsertionPoint(launch_op.body.blocks[0]): + result = func(*args, **kwargs) + gpu.terminator() + return result + + return wrapper + + return decorator + + @staticmethod + def mlir_func(funcBody): + @functools.wraps(funcBody) + def wrapper(*args, **kwargs): + function_name = funcBody.__name__ + + def saveIR(module): + """Save generated IR""" + if True: # self.saveIR: + # print(mlir_nvgpu_module) + original_stdout = sys.stdout + with open("nvdsl.mlir", "w") as f: + sys.stdout = f + print(module) + sys.stdout = original_stdout + + def _binary_op(lhs, rhs, op: str, predAtt="") -> "ArithValue": + """Generate MLIR's Arith dialects binary operations.""" + rhs = const(rhs) + if arith._is_float_type(lhs.type) and arith._is_float_type(rhs.type): + op += "F" + if op.startswith("Cmp"): + predicateAttr = getattr(arith, f"CmpFPredicate").__dict__[ + predAtt + ] + elif arith._is_integer_like_type( + lhs.type + ) and arith._is_integer_like_type(lhs.type): + if op == "Div" or op == "Rem": + op += "U" + op += "I" + if op.startswith("Cmp"): + predicateAttr = getattr(arith, f"CmpIPredicate").__dict__[ + predAtt + ] + else: + raise NotImplementedError( + f"Unsupported '{op}' operands: {lhs}, {rhs}" + ) + + if op.startswith("Cmp"): + op = getattr(arith, f"{op}Op") + + return op(predicateAttr, lhs, rhs).result + else: + op = getattr(arith, f"{op}Op") + return op(lhs, rhs).result + + @ir.register_value_caster(ir.IndexType.static_typeid) + @ir.register_value_caster(ir.F32Type.static_typeid) + @ir.register_value_caster(ir.F16Type.static_typeid) + @ir.register_value_caster(ir.F64Type.static_typeid) + @ir.register_value_caster(ir.IntegerType.static_typeid) + class ArithValue(ir.Value): + """Overloads operators for MLIR's Arith dialects binary operations.""" + + def __init__(self, v): + super().__init__(v) + + __add__ = partialmethod(_binary_op, op="Add") + __sub__ = partialmethod(_binary_op, op="Sub") + __mul__ = partialmethod(_binary_op, op="Mul") + __truediv__ = partialmethod(_binary_op, op="Div") + __mod__ = partialmethod(_binary_op, op="Rem") + __xor__ = partialmethod(_binary_op, op="XOr") + __lt__ = partialmethod(_binary_op, op="Cmp", predAtt="ult") + __le__ = partialmethod(_binary_op, op="Cmp", predAtt="ule") + __eq__ = partialmethod(_binary_op, op="Cmp", predAtt="eq") + __ne__ = partialmethod(_binary_op, op="Cmp", predAtt="ne") + __gt__ = partialmethod(_binary_op, op="Cmp", predAtt="ugt") + __ge__ = partialmethod(_binary_op, op="Cmp", predAtt="uge") + __and__ = partialmethod(_binary_op, op="And") + __or__ = partialmethod(_binary_op, op="Or") + + def __str__(self): + return ( + super() + .__str__() + .replace(ir.Value.__name__, ArithValue.__name__) + ) + + # Generate MLIR Context and start generating IR + with ir.Context(), ir.Location.unknown(): + types = [] + for arg in args: + types.append(get_mlir_ty(arg)) + + # Build IR + module = ir.Module.create() + with ir.InsertionPoint(module.body): + fop = func.FuncOp(function_name, (types, [])) + fop.attributes["llvm.emit_c_interface"] = ir.UnitAttr.get() + with ir.InsertionPoint(fop.add_entry_block()): + fargs = [] + for i, a in enumerate(types): + fargs.append(fop.arguments[i]) + + # Call user function body + result = funcBody(*fargs, **kwargs) + func.ReturnOp([]) + + # Save IR in a file + # saveIR(module) + + # Verify the module + # module.operation.verify() + + # Compile and JIT MLIR module + options = f"cubin-chip=sm_90a cubin-features=+ptx80 opt-level=3" + support_lib = os.getenv("SUPPORT_LIB") + if not os.path.exists(support_lib): + raise FileNotFoundError( + errno.ENOENT, os.strerror(errno.ENOENT), support_lib + ) + compiler = nvgpucompiler.NvgpuCompiler( + options, opt_level=3, shared_libs=[support_lib] + ) + engine = compiler.compile_and_jit(module) + + # Convert input arguments to MLIR arguments + newArgs = get_mlir_func_obj_ty(args) + + # Run the compiled program + engine.invoke(function_name, *newArgs) + + return result + + return wrapper diff --git a/mlir/test/Examples/NVGPU/tools/nvgpucompiler.py b/mlir/test/Examples/NVGPU/tools/nvgpucompiler.py new file mode 100644 index 0000000000000000000000000000000000000000..1c9cc74fcd169cb523e8c81bf8d4749e5cad50e0 --- /dev/null +++ b/mlir/test/Examples/NVGPU/tools/nvgpucompiler.py @@ -0,0 +1,45 @@ +# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +# This file contains the Nvgpu class. + +from mlir import execution_engine +from mlir import ir +from mlir import passmanager +from typing import Sequence +import errno +import os +import sys + +_SCRIPT_PATH = os.path.dirname(os.path.abspath(__file__)) +sys.path.append(_SCRIPT_PATH) + + +class NvgpuCompiler: + """Nvgpu class for compiling and building MLIR modules.""" + + def __init__(self, options: str, opt_level: int, shared_libs: Sequence[str]): + pipeline = f"builtin.module(gpu-lower-to-nvvm-pipeline{{{options}}})" + self.pipeline = pipeline + self.shared_libs = shared_libs + self.opt_level = opt_level + + def __call__(self, module: ir.Module): + """Convenience application method.""" + self.compile(module) + + def compile(self, module: ir.Module): + """Compiles the module by invoking the nvgpu pipeline.""" + passmanager.PassManager.parse(self.pipeline).run(module.operation) + + def jit(self, module: ir.Module) -> execution_engine.ExecutionEngine: + """Wraps the module in a JIT execution engine.""" + return execution_engine.ExecutionEngine( + module, opt_level=self.opt_level, shared_libs=self.shared_libs + ) + + def compile_and_jit(self, module: ir.Module) -> execution_engine.ExecutionEngine: + """Compiles and jits the module.""" + self.compile(module) + return self.jit(module) diff --git a/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir b/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir index b0fe642238f14f5e2b0a17aeffb9ab95ec41fe9e..360b3b0c0e60c1791e7fed19c8cf1761f4bce881 100644 --- a/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-parallel-wsloop.mlir @@ -12,10 +12,13 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop for (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { - %gep = llvm.getelementptr %arg0[0, %loop_cnt] : (!llvm.ptr, i32) -> !llvm.ptr, !llvm.array<10 x i32> - llvm.store %loop_cnt, %gep : i32, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { + %gep = llvm.getelementptr %arg0[0, %loop_cnt] : (!llvm.ptr, i32) -> !llvm.ptr, !llvm.array<10 x i32> + llvm.store %loop_cnt, %gep : i32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } diff --git a/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir b/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir index 0d77423abcb4f1354e13551fbb5b13ebd255c481..13d34b7e58f77e19b1dd2ab25645f78e0f1f73c2 100644 --- a/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-wsloop-collapsed.mlir @@ -8,13 +8,16 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo %loop_ub = llvm.mlir.constant(99 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : index) : i32 - omp.wsloop for (%arg1, %arg2) : i32 = (%loop_lb, %loop_lb) to (%loop_ub, %loop_ub) inclusive step (%loop_step, %loop_step) { - %1 = llvm.add %arg1, %arg2 : i32 - %2 = llvm.mul %arg2, %loop_ub overflow : i32 - %3 = llvm.add %arg1, %2 :i32 - %4 = llvm.getelementptr %arg0[%3] : (!llvm.ptr, i32) -> !llvm.ptr, i32 - llvm.store %1, %4 : i32, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%arg1, %arg2) : i32 = (%loop_lb, %loop_lb) to (%loop_ub, %loop_ub) inclusive step (%loop_step, %loop_step) { + %1 = llvm.add %arg1, %arg2 : i32 + %2 = llvm.mul %arg2, %loop_ub overflow : i32 + %3 = llvm.add %arg1, %2 :i32 + %4 = llvm.getelementptr %arg0[%3] : (!llvm.ptr, i32) -> !llvm.ptr, i32 + llvm.store %1, %4 : i32, !llvm.ptr + omp.yield + } + omp.terminator } llvm.return } diff --git a/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir b/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir index 0f3f503dfa5377b2eaa1287885862103c9d4ca24..ee851eaf71ac0b726bb52a74c36a5f90a6f94975 100644 --- a/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir +++ b/mlir/test/Target/LLVMIR/omptarget-wsloop.mlir @@ -8,10 +8,13 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop for (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { - %gep = llvm.getelementptr %arg0[0, %loop_cnt] : (!llvm.ptr, i32) -> !llvm.ptr, !llvm.array<10 x i32> - llvm.store %loop_cnt, %gep : i32, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { + %gep = llvm.getelementptr %arg0[0, %loop_cnt] : (!llvm.ptr, i32) -> !llvm.ptr, !llvm.array<10 x i32> + llvm.store %loop_cnt, %gep : i32, !llvm.ptr + omp.yield + } + omp.terminator } llvm.return } @@ -20,8 +23,11 @@ module attributes {dlti.dl_spec = #dlti.dl_spec<#dlti.dl_entry<"dlti.alloca_memo %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop for (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { - omp.yield + omp.wsloop { + omp.loop_nest (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { + omp.yield + } + omp.terminator } llvm.return } diff --git a/mlir/test/Target/LLVMIR/openmp-data-target-device.mlir b/mlir/test/Target/LLVMIR/openmp-data-target-device.mlir index d41429a6de066f51643d0fee4f60dd8f71ff3ed7..4ea9df369af66c62793f58149c939f6d9ce079f9 100644 --- a/mlir/test/Target/LLVMIR/openmp-data-target-device.mlir +++ b/mlir/test/Target/LLVMIR/openmp-data-target-device.mlir @@ -31,20 +31,23 @@ module attributes { } { %18 = llvm.mlir.constant(1 : i64) : i64 %19 = llvm.alloca %18 x i32 {pinned} : (i64) -> !llvm.ptr<5> %20 = llvm.addrspacecast %19 : !llvm.ptr<5> to !llvm.ptr - omp.wsloop for (%arg2) : i32 = (%16) to (%15) inclusive step (%16) { - llvm.store %arg2, %20 : i32, !llvm.ptr - %21 = llvm.load %20 : !llvm.ptr -> i32 - %22 = llvm.sext %21 : i32 to i64 - %23 = llvm.mlir.constant(1 : i64) : i64 - %24 = llvm.mlir.constant(0 : i64) : i64 - %25 = llvm.sub %22, %23 overflow : i64 - %26 = llvm.mul %25, %23 overflow : i64 - %27 = llvm.mul %26, %23 overflow : i64 - %28 = llvm.add %27, %24 overflow : i64 - %29 = llvm.mul %23, %17 overflow : i64 - %30 = llvm.getelementptr %arg0[%28] : (!llvm.ptr, i64) -> !llvm.ptr, i32 - llvm.store %21, %30 : i32, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%arg2) : i32 = (%16) to (%15) inclusive step (%16) { + llvm.store %arg2, %20 : i32, !llvm.ptr + %21 = llvm.load %20 : !llvm.ptr -> i32 + %22 = llvm.sext %21 : i32 to i64 + %23 = llvm.mlir.constant(1 : i64) : i64 + %24 = llvm.mlir.constant(0 : i64) : i64 + %25 = llvm.sub %22, %23 overflow : i64 + %26 = llvm.mul %25, %23 overflow : i64 + %27 = llvm.mul %26, %23 overflow : i64 + %28 = llvm.add %27, %24 overflow : i64 + %29 = llvm.mul %23, %17 overflow : i64 + %30 = llvm.getelementptr %arg0[%28] : (!llvm.ptr, i64) -> !llvm.ptr, i32 + llvm.store %21, %30 : i32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } diff --git a/mlir/test/Target/LLVMIR/openmp-llvm.mlir b/mlir/test/Target/LLVMIR/openmp-llvm.mlir index d1390022c1dc442b8e24350fe9cab02b3d548b20..ad40ca26bec9f821ffd8e3f17b7b8c8347a480ba 100644 --- a/mlir/test/Target/LLVMIR/openmp-llvm.mlir +++ b/mlir/test/Target/LLVMIR/openmp-llvm.mlir @@ -320,18 +320,20 @@ llvm.func @wsloop_simple(%arg0: !llvm.ptr) { %1 = llvm.mlir.constant(10 : index) : i64 %2 = llvm.mlir.constant(1 : index) : i64 omp.parallel { - "omp.wsloop"(%1, %0, %2) ({ - ^bb0(%arg1: i64): - // The form of the emitted IR is controlled by OpenMPIRBuilder and - // tested there. Just check that the right functions are called. - // CHECK: call i32 @__kmpc_global_thread_num - // CHECK: call void @__kmpc_for_static_init_{{.*}}(ptr @[[$loc_struct]], - %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 - %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr, i64) -> !llvm.ptr, f32 - llvm.store %3, %4 : f32, !llvm.ptr - omp.yield + "omp.wsloop"() ({ + omp.loop_nest (%arg1) : i64 = (%1) to (%0) step (%2) { + // The form of the emitted IR is controlled by OpenMPIRBuilder and + // tested there. Just check that the right functions are called. + // CHECK: call i32 @__kmpc_global_thread_num + // CHECK: call void @__kmpc_for_static_init_{{.*}}(ptr @[[$loc_struct]], + %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 + %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr, i64) -> !llvm.ptr, f32 + llvm.store %3, %4 : f32, !llvm.ptr + omp.yield + } + omp.terminator // CHECK: call void @__kmpc_for_static_fini(ptr @[[$loc_struct]], - }) {operandSegmentSizes = array} : (i64, i64, i64) -> () + }) : () -> () omp.terminator } llvm.return @@ -345,13 +347,15 @@ llvm.func @wsloop_inclusive_1(%arg0: !llvm.ptr) { %1 = llvm.mlir.constant(10 : index) : i64 %2 = llvm.mlir.constant(1 : index) : i64 // CHECK: store i64 31, ptr %{{.*}}upperbound - "omp.wsloop"(%1, %0, %2) ({ - ^bb0(%arg1: i64): - %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 - %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr, i64) -> !llvm.ptr, f32 - llvm.store %3, %4 : f32, !llvm.ptr - omp.yield - }) {operandSegmentSizes = array} : (i64, i64, i64) -> () + "omp.wsloop"() ({ + omp.loop_nest (%arg1) : i64 = (%1) to (%0) step (%2) { + %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 + %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr, i64) -> !llvm.ptr, f32 + llvm.store %3, %4 : f32, !llvm.ptr + omp.yield + } + omp.terminator + }) : () -> () llvm.return } @@ -363,13 +367,15 @@ llvm.func @wsloop_inclusive_2(%arg0: !llvm.ptr) { %1 = llvm.mlir.constant(10 : index) : i64 %2 = llvm.mlir.constant(1 : index) : i64 // CHECK: store i64 32, ptr %{{.*}}upperbound - "omp.wsloop"(%1, %0, %2) ({ - ^bb0(%arg1: i64): - %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 - %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr, i64) -> !llvm.ptr, f32 - llvm.store %3, %4 : f32, !llvm.ptr - omp.yield - }) {inclusive, operandSegmentSizes = array} : (i64, i64, i64) -> () + "omp.wsloop"() ({ + omp.loop_nest (%arg1) : i64 = (%1) to (%0) inclusive step (%2) { + %3 = llvm.mlir.constant(2.000000e+00 : f32) : f32 + %4 = llvm.getelementptr %arg0[%arg1] : (!llvm.ptr, i64) -> !llvm.ptr, f32 + llvm.store %3, %4 : f32, !llvm.ptr + omp.yield + } + omp.terminator + }) : () -> () llvm.return } @@ -379,14 +385,16 @@ llvm.func @body(i32) // CHECK-LABEL: @test_omp_wsloop_static_defchunk llvm.func @test_omp_wsloop_static_defchunk(%lb : i32, %ub : i32, %step : i32) -> () { - omp.wsloop schedule(static) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 34, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 0) - // CHECK: call void @__kmpc_for_static_fini - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(static) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 34, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 0) + // CHECK: call void @__kmpc_for_static_fini + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -395,15 +403,17 @@ llvm.func @body(i32) // CHECK-LABEL: @test_omp_wsloop_static_1 llvm.func @test_omp_wsloop_static_1(%lb : i32, %ub : i32, %step : i32) -> () { - %static_chunk_size = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop schedule(static = %static_chunk_size : i32) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 33, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 1) - // CHECK: call void @__kmpc_for_static_fini - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + %static_chunk_size = llvm.mlir.constant(1 : i32) : i32 + omp.wsloop schedule(static = %static_chunk_size : i32) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 33, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 1) + // CHECK: call void @__kmpc_for_static_fini + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -412,15 +422,17 @@ llvm.func @body(i32) // CHECK-LABEL: @test_omp_wsloop_static_2 llvm.func @test_omp_wsloop_static_2(%lb : i32, %ub : i32, %step : i32) -> () { - %static_chunk_size = llvm.mlir.constant(2 : i32) : i32 - omp.wsloop schedule(static = %static_chunk_size : i32) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 33, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 2) - // CHECK: call void @__kmpc_for_static_fini - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + %static_chunk_size = llvm.mlir.constant(2 : i32) : i32 + omp.wsloop schedule(static = %static_chunk_size : i32) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_for_static_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 33, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, ptr %{{.*}}, i32 1, i32 2) + // CHECK: call void @__kmpc_for_static_fini + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -428,16 +440,18 @@ llvm.func @test_omp_wsloop_static_2(%lb : i32, %ub : i32, %step : i32) -> () { llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(dynamic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(dynamic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -445,17 +459,19 @@ llvm.func @test_omp_wsloop_dynamic(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic_chunk_const(%lb : i64, %ub : i64, %step : i64) -> () { - %chunk_size_const = llvm.mlir.constant(2 : i16) : i16 - omp.wsloop schedule(dynamic = %chunk_size_const : i16) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i64 {{.*}}, i64 %{{.*}}, i64 {{.*}}, i64 2) - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + %chunk_size_const = llvm.mlir.constant(2 : i16) : i16 + omp.wsloop schedule(dynamic = %chunk_size_const : i16) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i64 {{.*}}, i64 %{{.*}}, i64 {{.*}}, i64 2) + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -463,20 +479,22 @@ llvm.func @test_omp_wsloop_dynamic_chunk_const(%lb : i64, %ub : i64, %step : i64 llvm.func @body(i32) llvm.func @test_omp_wsloop_dynamic_chunk_var(%lb : i32, %ub : i32, %step : i32) -> () { - %1 = llvm.mlir.constant(1 : i64) : i64 - %chunk_size_alloca = llvm.alloca %1 x i16 {bindc_name = "chunk_size", in_type = i16, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr - %chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr -> i16 - omp.wsloop schedule(dynamic = %chunk_size_var : i16) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: %[[CHUNK_SIZE:.*]] = sext i16 %{{.*}} to i32 - // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]]) - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + %1 = llvm.mlir.constant(1 : i64) : i64 + %chunk_size_alloca = llvm.alloca %1 x i16 {bindc_name = "chunk_size", in_type = i16, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr + %chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr -> i16 + omp.wsloop schedule(dynamic = %chunk_size_var : i16) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: %[[CHUNK_SIZE:.*]] = sext i16 %{{.*}} to i32 + // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]]) + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -484,20 +502,22 @@ llvm.func @test_omp_wsloop_dynamic_chunk_var(%lb : i32, %ub : i32, %step : i32) llvm.func @body(i32) llvm.func @test_omp_wsloop_dynamic_chunk_var2(%lb : i32, %ub : i32, %step : i32) -> () { - %1 = llvm.mlir.constant(1 : i64) : i64 - %chunk_size_alloca = llvm.alloca %1 x i64 {bindc_name = "chunk_size", in_type = i64, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr - %chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr -> i64 - omp.wsloop schedule(dynamic = %chunk_size_var : i64) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: %[[CHUNK_SIZE:.*]] = trunc i64 %{{.*}} to i32 - // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]]) - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + %1 = llvm.mlir.constant(1 : i64) : i64 + %chunk_size_alloca = llvm.alloca %1 x i64 {bindc_name = "chunk_size", in_type = i64, uniq_name = "_QFsub1Echunk_size"} : (i64) -> !llvm.ptr + %chunk_size_var = llvm.load %chunk_size_alloca : !llvm.ptr -> i64 + omp.wsloop schedule(dynamic = %chunk_size_var : i64) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: %[[CHUNK_SIZE:.*]] = trunc i64 %{{.*}} to i32 + // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %[[CHUNK_SIZE]]) + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -505,16 +525,18 @@ llvm.func @test_omp_wsloop_dynamic_chunk_var2(%lb : i32, %ub : i32, %step : i32) llvm.func @body(i32) llvm.func @test_omp_wsloop_dynamic_chunk_var3(%lb : i32, %ub : i32, %step : i32, %chunk_size : i32) -> () { - omp.wsloop schedule(dynamic = %chunk_size : i32) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %{{.*}}) - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(dynamic = %chunk_size : i32) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859, i32 {{.*}}, i32 %{{.*}}, i32 {{.*}}, i32 %{{.*}}) + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK: br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -522,16 +544,18 @@ llvm.func @test_omp_wsloop_dynamic_chunk_var3(%lb : i32, %ub : i32, %step : i32, llvm.func @body(i64) llvm.func @test_omp_wsloop_auto(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(auto) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(auto) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -539,14 +563,16 @@ llvm.func @test_omp_wsloop_auto(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @body(i64) llvm.func @test_omp_wsloop_runtime(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(runtime) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield + omp.wsloop schedule(runtime) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator } llvm.return } @@ -556,14 +582,16 @@ llvm.func @test_omp_wsloop_runtime(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @body(i64) llvm.func @test_omp_wsloop_guided(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(guided) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield + omp.wsloop schedule(guided) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator } llvm.return } @@ -573,14 +601,16 @@ llvm.func @test_omp_wsloop_guided(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic_nonmonotonic(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(dynamic, nonmonotonic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859 - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield + omp.wsloop schedule(dynamic, nonmonotonic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741859 + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator } llvm.return } @@ -590,14 +620,16 @@ llvm.func @test_omp_wsloop_dynamic_nonmonotonic(%lb : i64, %ub : i64, %step : i6 llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic_monotonic(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(dynamic, monotonic) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 536870947 - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield + omp.wsloop schedule(dynamic, monotonic) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 536870947 + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator } llvm.return } @@ -607,14 +639,16 @@ llvm.func @test_omp_wsloop_dynamic_monotonic(%lb : i64, %ub : i64, %step : i64) llvm.func @body(i64) llvm.func @test_omp_wsloop_runtime_simd(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(runtime, simd) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741871 - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield + omp.wsloop schedule(runtime, simd) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741871 + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator } llvm.return } @@ -624,14 +658,16 @@ llvm.func @test_omp_wsloop_runtime_simd(%lb : i64, %ub : i64, %step : i64) -> () llvm.func @body(i64) llvm.func @test_omp_wsloop_guided_simd(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(guided, simd) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741870 - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield + omp.wsloop schedule(guided, simd) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741870 + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator } llvm.return } @@ -793,17 +829,19 @@ llvm.func @simd_if(%arg0: !llvm.ptr {fir.bindc_name = "n"}, %arg1: !llvm.ptr {fi llvm.func @body(i64) llvm.func @test_omp_wsloop_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -811,17 +849,19 @@ llvm.func @test_omp_wsloop_ordered(%lb : i64, %ub : i64, %step : i64) -> () { llvm.func @body(i64) llvm.func @test_omp_wsloop_static_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(static) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(static) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 66, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -829,18 +869,20 @@ llvm.func @test_omp_wsloop_static_ordered(%lb : i64, %ub : i64, %step : i64) -> llvm.func @body(i32) llvm.func @test_omp_wsloop_static_chunk_ordered(%lb : i32, %ub : i32, %step : i32) -> () { - %static_chunk_size = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop schedule(static = %static_chunk_size : i32) ordered(0) - for (%iv) : i32 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 65, i32 1, i32 %{{.*}}, i32 1, i32 1) - // CHECK: call void @__kmpc_dispatch_fini_4u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i32) -> () - omp.yield - } - llvm.return + %static_chunk_size = llvm.mlir.constant(1 : i32) : i32 + omp.wsloop schedule(static = %static_chunk_size : i32) ordered(0) { + omp.loop_nest (%iv) : i32 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_4u(ptr @{{.*}}, i32 %{{.*}}, i32 65, i32 1, i32 %{{.*}}, i32 1, i32 1) + // CHECK: call void @__kmpc_dispatch_fini_4u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_4u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i32) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -848,17 +890,19 @@ llvm.func @test_omp_wsloop_static_chunk_ordered(%lb : i32, %ub : i32, %step : i3 llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(dynamic) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 67, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(dynamic) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 67, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -866,17 +910,19 @@ llvm.func @test_omp_wsloop_dynamic_ordered(%lb : i64, %ub : i64, %step : i64) -> llvm.func @body(i64) llvm.func @test_omp_wsloop_auto_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(auto) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 70, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(auto) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 70, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -884,17 +930,19 @@ llvm.func @test_omp_wsloop_auto_ordered(%lb : i64, %ub : i64, %step : i64) -> () llvm.func @body(i64) llvm.func @test_omp_wsloop_runtime_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(runtime) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 69, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(runtime) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 69, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -902,17 +950,19 @@ llvm.func @test_omp_wsloop_runtime_ordered(%lb : i64, %ub : i64, %step : i64) -> llvm.func @body(i64) llvm.func @test_omp_wsloop_guided_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(guided) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 68, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(guided) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 68, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -920,17 +970,19 @@ llvm.func @test_omp_wsloop_guided_ordered(%lb : i64, %ub : i64, %step : i64) -> llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic_nonmonotonic_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(dynamic, nonmonotonic) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741891, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(dynamic, nonmonotonic) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 1073741891, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -938,17 +990,19 @@ llvm.func @test_omp_wsloop_dynamic_nonmonotonic_ordered(%lb : i64, %ub : i64, %s llvm.func @body(i64) llvm.func @test_omp_wsloop_dynamic_monotonic_ordered(%lb : i64, %ub : i64, %step : i64) -> () { - omp.wsloop schedule(dynamic, monotonic) ordered(0) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 536870979, i64 1, i64 %{{.*}}, i64 1, i64 1) - // CHECK: call void @__kmpc_dispatch_fini_8u - // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u - // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 - // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} - llvm.call @body(%iv) : (i64) -> () - omp.yield - } - llvm.return + omp.wsloop schedule(dynamic, monotonic) ordered(0) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + // CHECK: call void @__kmpc_dispatch_init_8u(ptr @{{.*}}, i32 %{{.*}}, i32 536870979, i64 1, i64 %{{.*}}, i64 1, i64 1) + // CHECK: call void @__kmpc_dispatch_fini_8u + // CHECK: %[[continue:.*]] = call i32 @__kmpc_dispatch_next_8u + // CHECK: %[[cond:.*]] = icmp ne i32 %[[continue]], 0 + // CHECK br i1 %[[cond]], label %omp_loop.header{{.*}}, label %omp_loop.exit{{.*}} + llvm.call @body(%iv) : (i64) -> () + omp.yield + } + omp.terminator + } + llvm.return } // ----- @@ -1114,14 +1168,16 @@ llvm.func @collapse_wsloop( // CHECK: %[[TOTAL_SUB_1:.*]] = sub i32 %[[TOTAL]], 1 // CHECK: store i32 %[[TOTAL_SUB_1]], ptr // CHECK: call void @__kmpc_for_static_init_4u - omp.wsloop - for (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) { - %31 = llvm.load %20 : !llvm.ptr -> i32 - %32 = llvm.add %31, %arg0 : i32 - %33 = llvm.add %32, %arg1 : i32 - %34 = llvm.add %33, %arg2 : i32 - llvm.store %34, %20 : i32, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) { + %31 = llvm.load %20 : !llvm.ptr -> i32 + %32 = llvm.add %31, %arg0 : i32 + %33 = llvm.add %32, %arg1 : i32 + %34 = llvm.add %33, %arg2 : i32 + llvm.store %34, %20 : i32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -1175,14 +1231,16 @@ llvm.func @collapse_wsloop_dynamic( // CHECK: store i32 1, ptr // CHECK: store i32 %[[TOTAL]], ptr // CHECK: call void @__kmpc_dispatch_init_4u - omp.wsloop schedule(dynamic) - for (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) { - %31 = llvm.load %20 : !llvm.ptr -> i32 - %32 = llvm.add %31, %arg0 : i32 - %33 = llvm.add %32, %arg1 : i32 - %34 = llvm.add %33, %arg2 : i32 - llvm.store %34, %20 : i32, !llvm.ptr - omp.yield + omp.wsloop schedule(dynamic) { + omp.loop_nest (%arg0, %arg1, %arg2) : i32 = (%0, %1, %2) to (%3, %4, %5) step (%6, %7, %8) { + %31 = llvm.load %20 : !llvm.ptr -> i32 + %32 = llvm.add %31, %arg0 : i32 + %33 = llvm.add %32, %arg1 : i32 + %34 = llvm.add %33, %arg2 : i32 + llvm.store %34, %20 : i32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -1207,63 +1265,69 @@ llvm.func @omp_ordered(%arg0 : i32, %arg1 : i32, %arg2 : i32, %arg3 : i64, // CHECK: call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[OMP_THREAD]]) } - omp.wsloop ordered(0) - for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { - // CHECK: call void @__kmpc_ordered(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_THREAD2:%.*]]) - omp.ordered.region { - omp.terminator - // CHECK: call void @__kmpc_end_ordered(ptr @[[GLOB3]], i32 [[OMP_THREAD2]]) + omp.wsloop ordered(0) { + omp.loop_nest (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { + // CHECK: call void @__kmpc_ordered(ptr @[[GLOB3:[0-9]+]], i32 [[OMP_THREAD2:%.*]]) + omp.ordered.region { + omp.terminator + // CHECK: call void @__kmpc_end_ordered(ptr @[[GLOB3]], i32 [[OMP_THREAD2]]) + } + omp.yield } - omp.yield + omp.terminator } - omp.wsloop ordered(1) - for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { - // CHECK: [[TMP:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR]], i64 0, i64 0 - // CHECK: store i64 [[ARG0:%.*]], ptr [[TMP]], align 8 - // CHECK: [[TMP2:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR]], i64 0, i64 0 - // CHECK: [[OMP_THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) - // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB3]], i32 [[OMP_THREAD2]], ptr [[TMP2]]) - omp.ordered depend_type(dependsink) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64} + omp.wsloop ordered(1) { + omp.loop_nest (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { + // CHECK: [[TMP:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR]], i64 0, i64 0 + // CHECK: store i64 [[ARG0:%.*]], ptr [[TMP]], align 8 + // CHECK: [[TMP2:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR]], i64 0, i64 0 + // CHECK: [[OMP_THREAD2:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB3:[0-9]+]]) + // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB3]], i32 [[OMP_THREAD2]], ptr [[TMP2]]) + omp.ordered depend_type(dependsink) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64} - // CHECK: [[TMP3:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR3]], i64 0, i64 0 - // CHECK: store i64 [[ARG0]], ptr [[TMP3]], align 8 - // CHECK: [[TMP4:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR3]], i64 0, i64 0 - // CHECK: [[OMP_THREAD4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]) - // CHECK: call void @__kmpc_doacross_post(ptr @[[GLOB5]], i32 [[OMP_THREAD4]], ptr [[TMP4]]) - omp.ordered depend_type(dependsource) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64} + // CHECK: [[TMP3:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR3]], i64 0, i64 0 + // CHECK: store i64 [[ARG0]], ptr [[TMP3]], align 8 + // CHECK: [[TMP4:%.*]] = getelementptr inbounds [1 x i64], ptr [[ADDR3]], i64 0, i64 0 + // CHECK: [[OMP_THREAD4:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB5:[0-9]+]]) + // CHECK: call void @__kmpc_doacross_post(ptr @[[GLOB5]], i32 [[OMP_THREAD4]], ptr [[TMP4]]) + omp.ordered depend_type(dependsource) depend_vec(%arg3 : i64) {num_loops_val = 1 : i64} - omp.yield + omp.yield + } + omp.terminator } - omp.wsloop ordered(2) - for (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { - // CHECK: [[TMP5:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 0 - // CHECK: store i64 [[ARG0]], ptr [[TMP5]], align 8 - // CHECK: [[TMP6:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 1 - // CHECK: store i64 [[ARG1:%.*]], ptr [[TMP6]], align 8 - // CHECK: [[TMP7:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 0 - // CHECK: [[OMP_THREAD6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]) - // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB7]], i32 [[OMP_THREAD6]], ptr [[TMP7]]) - // CHECK: [[TMP8:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 0 - // CHECK: store i64 [[ARG2:%.*]], ptr [[TMP8]], align 8 - // CHECK: [[TMP9:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 1 - // CHECK: store i64 [[ARG3:%.*]], ptr [[TMP9]], align 8 - // CHECK: [[TMP10:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 0 - // CHECK: [[OMP_THREAD8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) - // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB7]], i32 [[OMP_THREAD8]], ptr [[TMP10]]) - omp.ordered depend_type(dependsink) depend_vec(%arg3, %arg4, %arg5, %arg6 : i64, i64, i64, i64) {num_loops_val = 2 : i64} + omp.wsloop ordered(2) { + omp.loop_nest (%arg7) : i32 = (%arg0) to (%arg1) step (%arg2) { + // CHECK: [[TMP5:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 0 + // CHECK: store i64 [[ARG0]], ptr [[TMP5]], align 8 + // CHECK: [[TMP6:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 1 + // CHECK: store i64 [[ARG1:%.*]], ptr [[TMP6]], align 8 + // CHECK: [[TMP7:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR5]], i64 0, i64 0 + // CHECK: [[OMP_THREAD6:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7:[0-9]+]]) + // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB7]], i32 [[OMP_THREAD6]], ptr [[TMP7]]) + // CHECK: [[TMP8:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 0 + // CHECK: store i64 [[ARG2:%.*]], ptr [[TMP8]], align 8 + // CHECK: [[TMP9:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 1 + // CHECK: store i64 [[ARG3:%.*]], ptr [[TMP9]], align 8 + // CHECK: [[TMP10:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR7]], i64 0, i64 0 + // CHECK: [[OMP_THREAD8:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB7]]) + // CHECK: call void @__kmpc_doacross_wait(ptr @[[GLOB7]], i32 [[OMP_THREAD8]], ptr [[TMP10]]) + omp.ordered depend_type(dependsink) depend_vec(%arg3, %arg4, %arg5, %arg6 : i64, i64, i64, i64) {num_loops_val = 2 : i64} + + // CHECK: [[TMP11:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 0 + // CHECK: store i64 [[ARG0]], ptr [[TMP11]], align 8 + // CHECK: [[TMP12:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 1 + // CHECK: store i64 [[ARG1]], ptr [[TMP12]], align 8 + // CHECK: [[TMP13:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 0 + // CHECK: [[OMP_THREAD10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) + // CHECK: call void @__kmpc_doacross_post(ptr @[[GLOB9]], i32 [[OMP_THREAD10]], ptr [[TMP13]]) + omp.ordered depend_type(dependsource) depend_vec(%arg3, %arg4 : i64, i64) {num_loops_val = 2 : i64} - // CHECK: [[TMP11:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 0 - // CHECK: store i64 [[ARG0]], ptr [[TMP11]], align 8 - // CHECK: [[TMP12:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 1 - // CHECK: store i64 [[ARG1]], ptr [[TMP12]], align 8 - // CHECK: [[TMP13:%.*]] = getelementptr inbounds [2 x i64], ptr [[ADDR9]], i64 0, i64 0 - // CHECK: [[OMP_THREAD10:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB9:[0-9]+]]) - // CHECK: call void @__kmpc_doacross_post(ptr @[[GLOB9]], i32 [[OMP_THREAD10]], ptr [[TMP13]]) - omp.ordered depend_type(dependsource) depend_vec(%arg3, %arg4 : i64, i64) {num_loops_val = 2 : i64} - - omp.yield + omp.yield + } + omp.terminator } llvm.return @@ -2133,10 +2197,13 @@ llvm.func @omp_sections_with_clauses() -> () { // introduction mechanism itself is tested elsewhere. // CHECK-LABEL: @repeated_successor llvm.func @repeated_successor(%arg0: i64, %arg1: i64, %arg2: i64, %arg3: i1) { - omp.wsloop for (%arg4) : i64 = (%arg0) to (%arg1) step (%arg2) { - llvm.cond_br %arg3, ^bb1(%arg0 : i64), ^bb1(%arg1 : i64) - ^bb1(%0: i64): // 2 preds: ^bb0, ^bb0 - omp.yield + omp.wsloop { + omp.loop_nest (%arg4) : i64 = (%arg0) to (%arg1) step (%arg2) { + llvm.cond_br %arg3, ^bb1(%arg0 : i64), ^bb1(%arg1 : i64) + ^bb1(%0: i64): // 2 preds: ^bb0, ^bb0 + omp.yield + } + omp.terminator } llvm.return } diff --git a/mlir/test/Target/LLVMIR/openmp-nested.mlir b/mlir/test/Target/LLVMIR/openmp-nested.mlir index e1fdfdd24a3cb06a9fbc2656ad59ac16a595114c..ce5f22f10d7dce1534652bd74cb8e0f83802b30d 100644 --- a/mlir/test/Target/LLVMIR/openmp-nested.mlir +++ b/mlir/test/Target/LLVMIR/openmp-nested.mlir @@ -11,20 +11,26 @@ module { %2 = llvm.mlir.constant(0 : index) : i64 %4 = llvm.mlir.constant(0 : i32) : i32 %12 = llvm.alloca %0 x i64 : (i64) -> !llvm.ptr - omp.wsloop for (%arg2) : i64 = (%2) to (%1) step (%0) { - omp.parallel { - omp.wsloop for (%arg3) : i64 = (%2) to (%0) step (%0) { - llvm.store %2, %12 : i64, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%arg2) : i64 = (%2) to (%1) step (%0) { + omp.parallel { + omp.wsloop { + omp.loop_nest (%arg3) : i64 = (%2) to (%0) step (%0) { + llvm.store %2, %12 : i64, !llvm.ptr + omp.yield + } + omp.terminator + } + omp.terminator } - omp.terminator + %19 = llvm.load %12 : !llvm.ptr -> i64 + %20 = llvm.trunc %19 : i64 to i32 + %5 = llvm.mlir.addressof @str0 : !llvm.ptr + %6 = llvm.getelementptr %5[%4, %4] : (!llvm.ptr, i32, i32) -> !llvm.ptr, !llvm.array<29 x i8> + %21 = llvm.call @printf(%6, %20, %20) vararg(!llvm.func): (!llvm.ptr, i32, i32) -> i32 + omp.yield } - %19 = llvm.load %12 : !llvm.ptr -> i64 - %20 = llvm.trunc %19 : i64 to i32 - %5 = llvm.mlir.addressof @str0 : !llvm.ptr - %6 = llvm.getelementptr %5[%4, %4] : (!llvm.ptr, i32, i32) -> !llvm.ptr, !llvm.array<29 x i8> - %21 = llvm.call @printf(%6, %20, %20) vararg(!llvm.func): (!llvm.ptr, i32, i32) -> i32 - omp.yield + omp.terminator } omp.terminator } diff --git a/mlir/test/Target/LLVMIR/openmp-reduction.mlir b/mlir/test/Target/LLVMIR/openmp-reduction.mlir index 39b64d71a2274b0510594e1596fde4d3d552a314..bfdad8c19335e11bf8b8c19f1e98c84b4dfa0b79 100644 --- a/mlir/test/Target/LLVMIR/openmp-reduction.mlir +++ b/mlir/test/Target/LLVMIR/openmp-reduction.mlir @@ -26,13 +26,15 @@ llvm.func @simple_reduction(%lb : i64, %ub : i64, %step : i64) { %c1 = llvm.mlir.constant(1 : i32) : i32 %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr omp.parallel { - omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - %1 = llvm.mlir.constant(2.0 : f32) : f32 - %2 = llvm.load %prv : !llvm.ptr -> f32 - %3 = llvm.fadd %1, %2 : f32 - llvm.store %3, %prv : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %2 = llvm.load %prv : !llvm.ptr -> f32 + %3 = llvm.fadd %1, %2 : f32 + llvm.store %3, %prv : f32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -105,16 +107,18 @@ llvm.func @reuse_declaration(%lb : i64, %ub : i64, %step : i64) { %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr %2 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr omp.parallel { - omp.wsloop reduction(@add_f32 %0 -> %prv0 : !llvm.ptr, @add_f32 %2 -> %prv1 : !llvm.ptr) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - %1 = llvm.mlir.constant(2.0 : f32) : f32 - %3 = llvm.load %prv0 : !llvm.ptr -> f32 - %4 = llvm.fadd %3, %1 : f32 - llvm.store %4, %prv0 : f32, !llvm.ptr - %5 = llvm.load %prv1 : !llvm.ptr -> f32 - %6 = llvm.fadd %5, %1 : f32 - llvm.store %6, %prv1 : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv0 : !llvm.ptr, @add_f32 %2 -> %prv1 : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %3 = llvm.load %prv0 : !llvm.ptr -> f32 + %4 = llvm.fadd %3, %1 : f32 + llvm.store %4, %prv0 : f32, !llvm.ptr + %5 = llvm.load %prv1 : !llvm.ptr -> f32 + %6 = llvm.fadd %5, %1 : f32 + llvm.store %6, %prv1 : f32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -195,13 +199,15 @@ llvm.func @missing_omp_reduction(%lb : i64, %ub : i64, %step : i64) { %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr %2 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr omp.parallel { - omp.wsloop reduction(@add_f32 %0 -> %prv0 : !llvm.ptr, @add_f32 %2 -> %prv1 : !llvm.ptr) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - %1 = llvm.mlir.constant(2.0 : f32) : f32 - %3 = llvm.load %prv0 : !llvm.ptr -> f32 - %4 = llvm.fadd %3, %1 : f32 - llvm.store %4, %prv0 : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv0 : !llvm.ptr, @add_f32 %2 -> %prv1 : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %3 = llvm.load %prv0 : !llvm.ptr -> f32 + %4 = llvm.fadd %3, %1 : f32 + llvm.store %4, %prv0 : f32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -280,16 +286,18 @@ llvm.func @double_reference(%lb : i64, %ub : i64, %step : i64) { %c1 = llvm.mlir.constant(1 : i32) : i32 %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr omp.parallel { - omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - %1 = llvm.mlir.constant(2.0 : f32) : f32 - %2 = llvm.load %prv : !llvm.ptr -> f32 - %3 = llvm.fadd %2, %1 : f32 - llvm.store %3, %prv : f32, !llvm.ptr - %4 = llvm.load %prv : !llvm.ptr -> f32 - %5 = llvm.fadd %4, %1 : f32 - llvm.store %5, %prv : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %2 = llvm.load %prv : !llvm.ptr -> f32 + %3 = llvm.fadd %2, %1 : f32 + llvm.store %3, %prv : f32, !llvm.ptr + %4 = llvm.load %prv : !llvm.ptr -> f32 + %5 = llvm.fadd %4, %1 : f32 + llvm.store %5, %prv : f32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -374,16 +382,18 @@ llvm.func @no_atomic(%lb : i64, %ub : i64, %step : i64) { %0 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr %2 = llvm.alloca %c1 x i32 : (i32) -> !llvm.ptr omp.parallel { - omp.wsloop reduction(@add_f32 %0 -> %prv0 : !llvm.ptr, @mul_f32 %2 -> %prv1 : !llvm.ptr) - for (%iv) : i64 = (%lb) to (%ub) step (%step) { - %1 = llvm.mlir.constant(2.0 : f32) : f32 - %3 = llvm.load %prv0 : !llvm.ptr -> f32 - %4 = llvm.fadd %3, %1 : f32 - llvm.store %4, %prv0 : f32, !llvm.ptr - %5 = llvm.load %prv1 : !llvm.ptr -> f32 - %6 = llvm.fmul %5, %1 : f32 - llvm.store %6, %prv1 : f32, !llvm.ptr - omp.yield + omp.wsloop reduction(@add_f32 %0 -> %prv0 : !llvm.ptr, @mul_f32 %2 -> %prv1 : !llvm.ptr) { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %1 = llvm.mlir.constant(2.0 : f32) : f32 + %3 = llvm.load %prv0 : !llvm.ptr -> f32 + %4 = llvm.fadd %3, %1 : f32 + llvm.store %4, %prv0 : f32, !llvm.ptr + %5 = llvm.load %prv1 : !llvm.ptr -> f32 + %6 = llvm.fmul %5, %1 : f32 + llvm.store %6, %prv1 : f32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } @@ -531,12 +541,15 @@ llvm.func @parallel_nested_workshare_reduction(%ub : i64) { %step = llvm.mlir.constant(1 : i64) : i64 omp.parallel reduction(@add_i32 %0 -> %prv : !llvm.ptr) { - omp.wsloop for (%iv) : i64 = (%lb) to (%ub) step (%step) { - %ival = llvm.trunc %iv : i64 to i32 - %lprv = llvm.load %prv : !llvm.ptr -> i32 - %add = llvm.add %lprv, %ival : i32 - llvm.store %add, %prv : i32, !llvm.ptr - omp.yield + omp.wsloop { + omp.loop_nest (%iv) : i64 = (%lb) to (%ub) step (%step) { + %ival = llvm.trunc %iv : i64 to i32 + %lprv = llvm.load %prv : !llvm.ptr -> i32 + %add = llvm.add %lprv, %ival : i32 + llvm.store %add, %prv : i32, !llvm.ptr + omp.yield + } + omp.terminator } omp.terminator } diff --git a/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir b/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir index 3842522934e48e0d4f604c2897f69134f9a7241d..7a1a31830ce9bc2e0dbcd1ede4429e20e16dfa87 100644 --- a/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir +++ b/mlir/test/Target/LLVMIR/openmp-wsloop-reduction-cleanup.mlir @@ -30,9 +30,12 @@ %loop_ub = llvm.mlir.constant(9 : i32) : i32 %loop_lb = llvm.mlir.constant(0 : i32) : i32 %loop_step = llvm.mlir.constant(1 : i32) : i32 - omp.wsloop byref reduction(@add_reduction_i_32 %1 -> %arg0 : !llvm.ptr, @add_reduction_i_32 %2 -> %arg1 : !llvm.ptr) for (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { - llvm.store %0, %arg0 : i32, !llvm.ptr - llvm.store %0, %arg1 : i32, !llvm.ptr + omp.wsloop byref reduction(@add_reduction_i_32 %1 -> %arg0 : !llvm.ptr, @add_reduction_i_32 %2 -> %arg1 : !llvm.ptr) { + omp.loop_nest (%loop_cnt) : i32 = (%loop_lb) to (%loop_ub) inclusive step (%loop_step) { + llvm.store %0, %arg0 : i32, !llvm.ptr + llvm.store %0, %arg1 : i32, !llvm.ptr + omp.yield + } omp.terminator } llvm.return diff --git a/mlir/test/lib/Dialect/Test/CMakeLists.txt b/mlir/test/lib/Dialect/Test/CMakeLists.txt index f63e4d330e6ac1a4a0f1344cfee9ba977ea5c8f5..fab89378093326d64f71e08223f56cbfdcac4798 100644 --- a/mlir/test/lib/Dialect/Test/CMakeLists.txt +++ b/mlir/test/lib/Dialect/Test/CMakeLists.txt @@ -31,8 +31,6 @@ mlir_tablegen(TestOpEnums.cpp.inc -gen-enum-defs) add_public_tablegen_target(MLIRTestEnumDefIncGen) set(LLVM_TARGET_DEFINITIONS TestOps.td) -mlir_tablegen(TestOps.h.inc -gen-op-decls) -mlir_tablegen(TestOps.cpp.inc -gen-op-defs) mlir_tablegen(TestOpsDialect.h.inc -gen-dialect-decls -dialect=test) mlir_tablegen(TestOpsDialect.cpp.inc -gen-dialect-defs -dialect=test) mlir_tablegen(TestPatterns.inc -gen-rewriters) @@ -43,6 +41,8 @@ mlir_tablegen(TestOpsSyntax.h.inc -gen-op-decls) mlir_tablegen(TestOpsSyntax.cpp.inc -gen-op-defs) add_public_tablegen_target(MLIRTestOpsSyntaxIncGen) +add_sharded_ops(TestOps 20) + # Exclude tests from libMLIR.so add_mlir_library(MLIRTestDialect TestAttributes.cpp @@ -56,6 +56,7 @@ add_mlir_library(MLIRTestDialect TestTypes.cpp TestOpsSyntax.cpp TestDialectInterfaces.cpp + ${SHARDED_SRCS} EXCLUDE_FROM_LIBMLIR @@ -66,6 +67,7 @@ add_mlir_library(MLIRTestDialect MLIRTestTypeDefIncGen MLIRTestOpsIncGen MLIRTestOpsSyntaxIncGen + MLIRTestOpsShardGen LINK_LIBS PUBLIC MLIRControlFlowInterfaces diff --git a/mlir/test/lib/Dialect/Test/TestDialect.cpp b/mlir/test/lib/Dialect/Test/TestDialect.cpp index 77fd7e61bd3a068ae27b5d2107fd522da61c2198..bfb9592e6382880cfccaae6c28934e900fd7d63e 100644 --- a/mlir/test/lib/Dialect/Test/TestDialect.cpp +++ b/mlir/test/lib/Dialect/Test/TestDialect.cpp @@ -326,12 +326,9 @@ struct TestOpEffectInterfaceFallback void TestDialect::initialize() { registerAttributes(); registerTypes(); - addOperations< -#define GET_OP_LIST -#include "TestOps.cpp.inc" - >(); registerOpsSyntax(); addOperations(); + registerTestDialectOperations(this); registerDynamicOp(getDynamicGenericOp(this)); registerDynamicOp(getDynamicOneOperandTwoResultsOp(this)); registerDynamicOp(getDynamicCustomParserPrinterOp(this)); diff --git a/mlir/test/lib/Dialect/Test/TestOps.cpp b/mlir/test/lib/Dialect/Test/TestOps.cpp index ce7e476be74e65e0d5f0268b85abde8fd5866a50..47d5b1b19121efa92059b0939f51959e9f9d7005 100644 --- a/mlir/test/lib/Dialect/Test/TestOps.cpp +++ b/mlir/test/lib/Dialect/Test/TestOps.cpp @@ -14,5 +14,4 @@ using namespace mlir; using namespace test; -#define GET_OP_CLASSES #include "TestOps.cpp.inc" diff --git a/mlir/test/mlir-tblgen/shard-op-defs.td b/mlir/test/mlir-tblgen/shard-op-defs.td new file mode 100644 index 0000000000000000000000000000000000000000..84ac6b0fbe9ebeea1cb4fba221bb0f8666f3c372 --- /dev/null +++ b/mlir/test/mlir-tblgen/shard-op-defs.td @@ -0,0 +1,33 @@ +// RUN: mlir-tblgen -gen-op-defs -op-shard-count=2 -I %S/../../include %s | FileCheck %s --check-prefix=DEFS +// RUN: mlir-tblgen -gen-op-decls -op-shard-count=2 -I %S/../../include %s | FileCheck %s --check-prefix=DECLS + +include "mlir/IR/OpBase.td" + +def Test_Dialect : Dialect { + let name = "test"; + let cppNamespace = "test"; +} + +class Test_Op traits = []> + : Op; + +def OpA : Test_Op<"a">; +def OpB : Test_Op<"b">; +def OpC : Test_Op<"c">; + +// DECLS: OpA +// DECLS: OpB +// DECLS: OpC +// DECLS: registerTestDialectOperations( +// DECLS: registerTestDialectOperations0( +// DECLS: registerTestDialectOperations1( + +// DEFS-LABEL: GET_OP_DEFS_0 +// DEFS: void test::registerTestDialectOperations( +// DEFS: void test::registerTestDialectOperations0( +// DEFS: OpAAdaptor +// DEFS: OpBAdaptor + +// DEFS-LABEL: GET_OP_DEFS_1 +// DEFS: void test::registerTestDialectOperations1( +// DEFS: OpCAdaptor diff --git a/mlir/test/python/dialects/llvm.py b/mlir/test/python/dialects/llvm.py index fb4b343b170bae6de9813f3cce655efad882ce36..d9ffdeb65bfd40b412c7e226965522a4bdc74da5 100644 --- a/mlir/test/python/dialects/llvm.py +++ b/mlir/test/python/dialects/llvm.py @@ -107,3 +107,46 @@ def testSmoke(): ) result = llvm.UndefOp(mat64f32_t) # CHECK: %0 = llvm.mlir.undef : !llvm.struct<(f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32, f32)> + + +# CHECK-LABEL: testPointerType +@constructAndPrintInModule +def testPointerType(): + ptr = llvm.PointerType.get() + # CHECK: !llvm.ptr + print(ptr) + + ptr_with_addr = llvm.PointerType.get(1) + # CHECK: !llvm.ptr<1> + print(ptr_with_addr) + + +# CHECK-LABEL: testConstant +@constructAndPrintInModule +def testConstant(): + i32 = IntegerType.get_signless(32) + c_128 = llvm.mlir_constant(IntegerAttr.get(i32, 128)) + # CHECK: %{{.*}} = llvm.mlir.constant(128 : i32) : i32 + print(c_128.owner) + + +# CHECK-LABEL: testIntrinsics +@constructAndPrintInModule +def testIntrinsics(): + i32 = IntegerType.get_signless(32) + ptr = llvm.PointerType.get() + c_128 = llvm.mlir_constant(IntegerAttr.get(i32, 128)) + # CHECK: %[[CST128:.*]] = llvm.mlir.constant(128 : i32) : i32 + print(c_128.owner) + + alloca = llvm.alloca(ptr, c_128, i32) + # CHECK: %[[ALLOCA:.*]] = llvm.alloca %[[CST128]] x i32 : (i32) -> !llvm.ptr + print(alloca.owner) + + c_0 = llvm.mlir_constant(IntegerAttr.get(IntegerType.get_signless(8), 0)) + # CHECK: %[[CST0:.+]] = llvm.mlir.constant(0 : i8) : i8 + print(c_0.owner) + + result = llvm.intr_memset(alloca, c_0, c_128, False) + # CHECK: "llvm.intr.memset"(%[[ALLOCA]], %[[CST0]], %[[CST128]]) <{isVolatile = false}> : (!llvm.ptr, i8, i32) -> () + print(result) diff --git a/mlir/test/python/dialects/sparse_tensor/dialect.py b/mlir/test/python/dialects/sparse_tensor/dialect.py index 5666d090c3d5ee67b3af1a135efef604664e8f28..3cc4575eb3e240193d90e71184f2568de34ac42d 100644 --- a/mlir/test/python/dialects/sparse_tensor/dialect.py +++ b/mlir/test/python/dialects/sparse_tensor/dialect.py @@ -2,6 +2,7 @@ from mlir.ir import * from mlir.dialects import sparse_tensor as st +import textwrap def run(f): @@ -15,13 +16,18 @@ def run(f): def testEncodingAttr1D(): with Context() as ctx: parsed = Attribute.parse( - "#sparse_tensor.encoding<{" - " map = (d0) -> (d0 : compressed)," - " posWidth = 16," - " crdWidth = 32" - "}>" + textwrap.dedent( + """\ + #sparse_tensor.encoding<{ + map = (d0) -> (d0 : compressed), + posWidth = 16, + crdWidth = 32, + explicitVal = 1.0 : f64 + }>\ + """ + ) ) - # CHECK: #sparse_tensor.encoding<{ map = (d0) -> (d0 : compressed), posWidth = 16, crdWidth = 32 }> + # CHECK: #sparse_tensor.encoding<{ map = (d0) -> (d0 : compressed), posWidth = 16, crdWidth = 32, explicitVal = 1.000000e+00 : f64 }> print(parsed) casted = st.EncodingAttr(parsed) @@ -38,9 +44,16 @@ def testEncodingAttr1D(): print(f"pos_width: {casted.pos_width}") # CHECK: crd_width: 32 print(f"crd_width: {casted.crd_width}") + # CHECK: explicit_val: 1.000000e+00 + print(f"explicit_val: {casted.explicit_val}") + # CHECK: implicit_val: None + print(f"implicit_val: {casted.implicit_val}") - created = st.EncodingAttr.get(casted.lvl_types, None, None, 0, 0) - # CHECK: #sparse_tensor.encoding<{ map = (d0) -> (d0 : compressed) }> + new_explicit_val = FloatAttr.get_f64(1.0) + created = st.EncodingAttr.get( + casted.lvl_types, None, None, 0, 0, new_explicit_val + ) + # CHECK: #sparse_tensor.encoding<{ map = (d0) -> (d0 : compressed), explicitVal = 1.000000e+00 : f64 }> print(created) # CHECK: created_equal: False print(f"created_equal: {created == casted}") @@ -57,12 +70,16 @@ def testEncodingAttr1D(): def testEncodingAttrStructure(): with Context() as ctx: parsed = Attribute.parse( - "#sparse_tensor.encoding<{" - " map = (d0, d1) -> (d0 : dense, d1 floordiv 4 : dense," - " d1 mod 4 : structured[2, 4])," - " posWidth = 16," - " crdWidth = 32" - "}>" + textwrap.dedent( + """\ + #sparse_tensor.encoding<{ + map = (d0, d1) -> (d0 : dense, d1 floordiv 4 : dense, + d1 mod 4 : structured[2, 4]), + posWidth = 16, + crdWidth = 32, + }>\ + """ + ) ) # CHECK: #sparse_tensor.encoding<{ map = (d0, d1) -> (d0 : dense, d1 floordiv 4 : dense, d1 mod 4 : structured[2, 4]), posWidth = 16, crdWidth = 32 }> print(parsed) @@ -144,11 +161,15 @@ def testEncodingAttrStructure(): def testEncodingAttr2D(): with Context() as ctx: parsed = Attribute.parse( - "#sparse_tensor.encoding<{" - " map = (d0, d1) -> (d1 : dense, d0 : compressed)," - " posWidth = 8," - " crdWidth = 32" - "}>" + textwrap.dedent( + """\ + #sparse_tensor.encoding<{ + map = (d0, d1) -> (d1 : dense, d0 : compressed), + posWidth = 8, + crdWidth = 32, + }>\ + """ + ) ) # CHECK: #sparse_tensor.encoding<{ map = (d0, d1) -> (d1 : dense, d0 : compressed), posWidth = 8, crdWidth = 32 }> print(parsed) @@ -187,11 +208,15 @@ def testEncodingAttrOnTensorType(): with Context() as ctx, Location.unknown(): encoding = st.EncodingAttr( Attribute.parse( - "#sparse_tensor.encoding<{" - " map = (d0) -> (d0 : compressed), " - " posWidth = 64," - " crdWidth = 32" - "}>" + textwrap.dedent( + """\ + #sparse_tensor.encoding<{ + map = (d0) -> (d0 : compressed), + posWidth = 64, + crdWidth = 32, + }>\ + """ + ) ) ) tt = RankedTensorType.get((1024,), F32Type.get(), encoding=encoding) diff --git a/mlir/test/python/dialects/transform_interpreter.py b/mlir/test/python/dialects/transform_interpreter.py index 807a98c49327970453de16b7f23f3c97ff279418..819a3be1db9d5a3a67954b9c706d702235454f31 100644 --- a/mlir/test/python/dialects/transform_interpreter.py +++ b/mlir/test/python/dialects/transform_interpreter.py @@ -45,6 +45,21 @@ def print_other(): # CHECK: this.is.payload +@test_in_context +def transform_options(): + options = interp.TransformOptions() + options.expensive_checks = False + options.enforce_single_top_level_transform_op = True + m = ir.Module.parse( + print_root_module.replace("from interpreter", "transform_options") + ) + payload = ir.Module.parse("module attributes { this.is.payload } {}") + interp.apply_named_sequence(payload, m.body.operations[0], m, options) + + +# CHECK-LABEL: transform_options + + @test_in_context def failed(): payload = ir.Module.parse("module attributes { this.is.payload } {}") diff --git a/mlir/tools/mlir-src-sharder/CMakeLists.txt b/mlir/tools/mlir-src-sharder/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..4ef870b61124adf12496ece3a17ef88c90d56997 --- /dev/null +++ b/mlir/tools/mlir-src-sharder/CMakeLists.txt @@ -0,0 +1,14 @@ +set(LLVM_LINK_COMPONENTS Support) +set(LIBS MLIRSupport) + +add_tablegen(mlir-src-sharder MLIR_SRC_SHARDER + mlir-src-sharder.cpp + + DEPENDS + ${LIBS} + ) + +set_target_properties(mlir-src-sharder PROPERTIES FOLDER "Tablegenning") +target_link_libraries(mlir-src-sharder PRIVATE ${LIBS}) + +mlir_check_all_link_libraries(mlir-src-sharder) diff --git a/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp b/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp new file mode 100644 index 0000000000000000000000000000000000000000..dc1e2939c7d25b267af2a3108c299c1d2554a301 --- /dev/null +++ b/mlir/tools/mlir-src-sharder/mlir-src-sharder.cpp @@ -0,0 +1,114 @@ +//===- mlir-src-sharder.cpp - A tool for sharder generated source files ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Support/FileUtilities.h" +#include "mlir/Support/LogicalResult.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/InitLLVM.h" +#include "llvm/Support/MemoryBuffer.h" +#include "llvm/Support/ToolOutputFile.h" + +using namespace mlir; + +/// Create a dependency file for `-d` option. +/// +/// This functionality is generally only for the benefit of the build system, +/// and is modeled after the same option in TableGen. +static LogicalResult createDependencyFile(StringRef outputFilename, + StringRef dependencyFile) { + if (outputFilename == "-") { + llvm::errs() << "error: the option -d must be used together with -o\n"; + return failure(); + } + + std::string errorMessage; + std::unique_ptr outputFile = + openOutputFile(dependencyFile, &errorMessage); + if (!outputFile) { + llvm::errs() << errorMessage << "\n"; + return failure(); + } + + outputFile->os() << outputFilename << ":\n"; + outputFile->keep(); + return success(); +} + +int main(int argc, char **argv) { + // FIXME: This is necessary because we link in TableGen, which defines its + // options as static variables.. some of which overlap with our options. + llvm::cl::ResetCommandLineParser(); + + llvm::cl::opt opShardIndex( + "op-shard-index", llvm::cl::desc("The current shard index")); + llvm::cl::opt inputFilename(llvm::cl::Positional, + llvm::cl::desc(""), + llvm::cl::init("-")); + llvm::cl::opt outputFilename( + "o", llvm::cl::desc("Output filename"), llvm::cl::value_desc("filename"), + llvm::cl::init("-")); + llvm::cl::list includeDirs( + "I", llvm::cl::desc("Directory of include files"), + llvm::cl::value_desc("directory"), llvm::cl::Prefix); + llvm::cl::opt dependencyFilename( + "d", llvm::cl::desc("Dependency filename"), + llvm::cl::value_desc("filename"), llvm::cl::init("")); + llvm::cl::opt writeIfChanged( + "write-if-changed", + llvm::cl::desc("Only write to the output file if it changed")); + + llvm::InitLLVM y(argc, argv); + llvm::cl::ParseCommandLineOptions(argc, argv); + + // Open the input file. + std::string errorMessage; + std::unique_ptr inputFile = + openInputFile(inputFilename, &errorMessage); + if (!inputFile) { + llvm::errs() << errorMessage << "\n"; + return 1; + } + + // Write the output to a buffer. + std::string outputStr; + llvm::raw_string_ostream os(outputStr); + os << "#define GET_OP_DEFS_" << opShardIndex << "\n" + << inputFile->getBuffer(); + + // Determine whether we need to write the output file. + bool shouldWriteOutput = true; + if (writeIfChanged) { + // Only update the real output file if there are any differences. This + // prevents recompilation of all the files depending on it if there aren't + // any. + if (auto existingOrErr = + llvm::MemoryBuffer::getFile(outputFilename, /*IsText=*/true)) + if (std::move(existingOrErr.get())->getBuffer() == os.str()) + shouldWriteOutput = false; + } + + // Populate the output file if necessary. + if (shouldWriteOutput) { + std::unique_ptr outputFile = + openOutputFile(outputFilename, &errorMessage); + if (!outputFile) { + llvm::errs() << errorMessage << "\n"; + return 1; + } + outputFile->os() << os.str(); + outputFile->keep(); + } + + // Always write the depfile, even if the main output hasn't changed. If it's + // missing, Ninja considers the output dirty. + if (!dependencyFilename.empty()) + if (failed(createDependencyFile(outputFilename, dependencyFilename))) + return 1; + + return 0; +} diff --git a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp index 53ed5cb7c043ecad04c2d52aa4a55cbeafb9e0df..63fe5a8099074650faf02bb897a6bfcd752f67aa 100644 --- a/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp +++ b/mlir/tools/mlir-tblgen/OpDefinitionsGen.cpp @@ -4303,32 +4303,15 @@ void OpOperandAdaptorEmitter::emitDef( emitter.adaptor.writeDefTo(os); } -// Emits the opcode enum and op classes. -static void emitOpClasses(const RecordKeeper &recordKeeper, - const std::vector &defs, raw_ostream &os, - bool emitDecl) { - // First emit forward declaration for each class, this allows them to refer - // to each others in traits for example. - if (emitDecl) { - os << "#if defined(GET_OP_CLASSES) || defined(GET_OP_FWD_DEFINES)\n"; - os << "#undef GET_OP_FWD_DEFINES\n"; - for (auto *def : defs) { - Operator op(*def); - NamespaceEmitter emitter(os, op.getCppNamespace()); - os << "class " << op.getCppClassName() << ";\n"; - } - os << "#endif\n\n"; - } - - IfDefScope scope("GET_OP_CLASSES", os); +/// Emit the class declarations or definitions for the given op defs. +static void +emitOpClasses(const RecordKeeper &recordKeeper, + const std::vector &defs, raw_ostream &os, + const StaticVerifierFunctionEmitter &staticVerifierEmitter, + bool emitDecl) { if (defs.empty()) return; - // Generate all of the locally instantiated methods first. - StaticVerifierFunctionEmitter staticVerifierEmitter(os, recordKeeper); - os << formatv(opCommentHeader, "Local Utility Method", "Definitions"); - staticVerifierEmitter.emitOpConstraints(defs, emitDecl); - for (auto *def : defs) { Operator op(*def); if (emitDecl) { @@ -4358,34 +4341,145 @@ static void emitOpClasses(const RecordKeeper &recordKeeper, } } -// Emits a comma-separated list of the ops. -static void emitOpList(const std::vector &defs, raw_ostream &os) { - IfDefScope scope("GET_OP_LIST", os); +/// Emit the declarations for the provided op classes. +static void emitOpClassDecls(const RecordKeeper &recordKeeper, + const std::vector &defs, + raw_ostream &os) { + // First emit forward declaration for each class, this allows them to refer + // to each others in traits for example. + for (auto *def : defs) { + Operator op(*def); + NamespaceEmitter emitter(os, op.getCppNamespace()); + os << "class " << op.getCppClassName() << ";\n"; + } + + // Emit the op class declarations. + IfDefScope scope("GET_OP_CLASSES", os); + if (defs.empty()) + return; + StaticVerifierFunctionEmitter staticVerifierEmitter(os, recordKeeper); + staticVerifierEmitter.collectOpConstraints(defs); + emitOpClasses(recordKeeper, defs, os, staticVerifierEmitter, + /*emitDecl=*/true); +} + +/// Emit the definitions for the provided op classes. +static void emitOpClassDefs(const RecordKeeper &recordKeeper, + ArrayRef defs, raw_ostream &os, + StringRef constraintPrefix = "") { + if (defs.empty()) + return; + + // Generate all of the locally instantiated methods first. + StaticVerifierFunctionEmitter staticVerifierEmitter(os, recordKeeper, + constraintPrefix); + os << formatv(opCommentHeader, "Local Utility Method", "Definitions"); + staticVerifierEmitter.collectOpConstraints(defs); + staticVerifierEmitter.emitOpConstraints(defs); - interleave( - // TODO: We are constructing the Operator wrapper instance just for - // getting it's qualified class name here. Reduce the overhead by having a - // lightweight version of Operator class just for that purpose. - defs, [&os](Record *def) { os << Operator(def).getQualCppClassName(); }, - [&os]() { os << ",\n"; }); + // Emit the classes. + emitOpClasses(recordKeeper, defs, os, staticVerifierEmitter, + /*emitDecl=*/false); } +/// Emit op declarations for all op records. static bool emitOpDecls(const RecordKeeper &recordKeeper, raw_ostream &os) { emitSourceFileHeader("Op Declarations", os, recordKeeper); std::vector defs = getRequestedOpDefinitions(recordKeeper); - emitOpClasses(recordKeeper, defs, os, /*emitDecl=*/true); + emitOpClassDecls(recordKeeper, defs, os); + + // If we are generating sharded op definitions, emit the sharded op + // registration hooks. + SmallVector, 4> shardedDefs; + shardOpDefinitions(defs, shardedDefs); + if (defs.empty() || shardedDefs.size() <= 1) + return false; + + Dialect dialect = Operator(defs.front()).getDialect(); + NamespaceEmitter ns(os, dialect); + + const char *const opRegistrationHook = + "void register{0}Operations{1}({2}::{0} *dialect);\n"; + os << formatv(opRegistrationHook, dialect.getCppClassName(), "", + dialect.getCppNamespace()); + for (unsigned i = 0; i < shardedDefs.size(); ++i) { + os << formatv(opRegistrationHook, dialect.getCppClassName(), i, + dialect.getCppNamespace()); + } return false; } +/// Generate the dialect op registration hook and the op class definitions for a +/// shard of ops. +static void emitOpDefShard(const RecordKeeper &recordKeeper, + ArrayRef defs, const Dialect &dialect, + unsigned shardIndex, unsigned shardCount, + raw_ostream &os) { + std::string shardGuard = "GET_OP_DEFS_"; + std::string indexStr = std::to_string(shardIndex); + shardGuard += indexStr; + IfDefScope scope(shardGuard, os); + + // Emit the op registration hook in the first shard. + const char *const opRegistrationHook = + "void {0}::register{1}Operations{2}({0}::{1} *dialect) {{\n"; + if (shardIndex == 0) { + os << formatv(opRegistrationHook, dialect.getCppNamespace(), + dialect.getCppClassName(), ""); + for (unsigned i = 0; i < shardCount; ++i) { + os << formatv(" {0}::register{1}Operations{2}(dialect);\n", + dialect.getCppNamespace(), dialect.getCppClassName(), i); + } + os << "}\n"; + } + + // Generate the per-shard op registration hook. + os << formatv(opCommentHeader, dialect.getCppClassName(), + "Op Registration Hook") + << formatv(opRegistrationHook, dialect.getCppNamespace(), + dialect.getCppClassName(), shardIndex); + for (Record *def : defs) { + os << formatv(" ::mlir::RegisteredOperationName::insert<{0}>(*dialect);\n", + Operator(def).getQualCppClassName()); + } + os << "}\n"; + + // Generate the per-shard op definitions. + emitOpClassDefs(recordKeeper, defs, os, indexStr); +} + +/// Emit op definitions for all op records. static bool emitOpDefs(const RecordKeeper &recordKeeper, raw_ostream &os) { emitSourceFileHeader("Op Definitions", os, recordKeeper); std::vector defs = getRequestedOpDefinitions(recordKeeper); - emitOpList(defs, os); - emitOpClasses(recordKeeper, defs, os, /*emitDecl=*/false); + SmallVector, 4> shardedDefs; + shardOpDefinitions(defs, shardedDefs); + + // If no shard was requested, emit the regular op list and class definitions. + if (shardedDefs.size() == 1) { + { + IfDefScope scope("GET_OP_LIST", os); + interleave( + defs, os, + [&](Record *def) { os << Operator(def).getQualCppClassName(); }, + ",\n"); + } + { + IfDefScope scope("GET_OP_CLASSES", os); + emitOpClassDefs(recordKeeper, defs, os); + } + return false; + } + if (defs.empty()) + return false; + Dialect dialect = Operator(defs.front()).getDialect(); + for (auto [idx, value] : llvm::enumerate(shardedDefs)) { + emitOpDefShard(recordKeeper, value, dialect, idx, shardedDefs.size(), os); + } return false; } diff --git a/mlir/tools/mlir-tblgen/OpGenHelpers.cpp b/mlir/tools/mlir-tblgen/OpGenHelpers.cpp index 7fd34df8460d398075b42154a47a417f4c15bd90..c2a2423a2402699668f1b6be47dcb71ebdf2ed4d 100644 --- a/mlir/tools/mlir-tblgen/OpGenHelpers.cpp +++ b/mlir/tools/mlir-tblgen/OpGenHelpers.cpp @@ -31,6 +31,10 @@ static cl::opt opExcFilter( "op-exclude-regex", cl::desc("Regex of name of op's to exclude (no filter if empty)"), cl::cat(opDefGenCat)); +static cl::opt opShardCount( + "op-shard-count", + cl::desc("The number of shards into which the op classes will be divided"), + cl::cat(opDefGenCat), cl::init(1)); static std::string getOperationName(const Record &def) { auto prefix = def.getValueAsDef("opDialect")->getValueAsString("name"); @@ -79,4 +83,23 @@ bool mlir::tblgen::isPythonReserved(StringRef str) { reserved.insert("issubclass"); reserved.insert("type"); return reserved.contains(str); -} \ No newline at end of file +} + +void mlir::tblgen::shardOpDefinitions( + ArrayRef defs, + SmallVectorImpl> &shardedDefs) { + assert(opShardCount > 0 && "expected a positive shard count"); + if (opShardCount == 1) { + shardedDefs.push_back(defs); + return; + } + + unsigned minShardSize = defs.size() / opShardCount; + unsigned numMissing = defs.size() - minShardSize * opShardCount; + shardedDefs.reserve(opShardCount); + for (unsigned i = 0, start = 0; i < opShardCount; ++i) { + unsigned size = minShardSize + (i < numMissing); + shardedDefs.push_back(defs.slice(start, size)); + start += size; + } +} diff --git a/mlir/tools/mlir-tblgen/OpGenHelpers.h b/mlir/tools/mlir-tblgen/OpGenHelpers.h index 3dcff14d1221ee36c08eb2f44924bcffcc5a1d71..1b43d5d3ce3a7df326bd469e11bc662a631b3db9 100644 --- a/mlir/tools/mlir-tblgen/OpGenHelpers.h +++ b/mlir/tools/mlir-tblgen/OpGenHelpers.h @@ -13,6 +13,7 @@ #ifndef MLIR_TOOLS_MLIRTBLGEN_OPGENHELPERS_H_ #define MLIR_TOOLS_MLIRTBLGEN_OPGENHELPERS_H_ +#include "mlir/Support/LLVM.h" #include "llvm/TableGen/Record.h" #include @@ -28,6 +29,10 @@ getRequestedOpDefinitions(const llvm::RecordKeeper &recordKeeper); /// Regenerate using python -c"print(set(sorted(__import__('keyword').kwlist)))" bool isPythonReserved(llvm::StringRef str); +/// Shard the op defintions into the number of shards set by "op-shard-count". +void shardOpDefinitions(ArrayRef defs, + SmallVectorImpl> &shardedDefs); + } // namespace tblgen } // namespace mlir diff --git a/mlir/unittests/CMakeLists.txt b/mlir/unittests/CMakeLists.txt index 6fad249a0b2fbae8e7cd625663dc428bed59ab3e..6d8aa290e82f25559190a2665cc2cefb0b8f07a9 100644 --- a/mlir/unittests/CMakeLists.txt +++ b/mlir/unittests/CMakeLists.txt @@ -20,6 +20,7 @@ add_subdirectory(Support) add_subdirectory(Rewrite) add_subdirectory(TableGen) add_subdirectory(Target) +add_subdirectory(Tools) add_subdirectory(Transforms) if(MLIR_ENABLE_EXECUTION_ENGINE) diff --git a/mlir/unittests/Tools/CMakeLists.txt b/mlir/unittests/Tools/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..a97588d928668571821aceb085079703fe553b8e --- /dev/null +++ b/mlir/unittests/Tools/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory(lsp-server-support) diff --git a/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt b/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt new file mode 100644 index 0000000000000000000000000000000000000000..3aa8b9c4bc7735b0f8d541de65a263de9e4195ee --- /dev/null +++ b/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt @@ -0,0 +1,6 @@ +add_mlir_unittest(MLIRLspServerSupportTests + Transport.cpp +) +target_link_libraries(MLIRLspServerSupportTests + PRIVATE + MLIRLspServerSupportLib) diff --git a/mlir/unittests/Tools/lsp-server-support/Transport.cpp b/mlir/unittests/Tools/lsp-server-support/Transport.cpp new file mode 100644 index 0000000000000000000000000000000000000000..48eae32a0fc3a428efb560a34c984052b7bf7293 --- /dev/null +++ b/mlir/unittests/Tools/lsp-server-support/Transport.cpp @@ -0,0 +1,121 @@ +//===- Transport.cpp - LSP JSON transport unit tests ----------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Tools/lsp-server-support/Transport.h" +#include "mlir/Tools/lsp-server-support/Logging.h" +#include "mlir/Tools/lsp-server-support/Protocol.h" +#include "llvm/Support/FileSystem.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +using namespace mlir; +using namespace mlir::lsp; +using namespace testing; + +namespace { + +TEST(TransportTest, SendReply) { + std::string out; + llvm::raw_string_ostream os(out); + JSONTransport transport(nullptr, os); + MessageHandler handler(transport); + + transport.reply(1989, nullptr); + EXPECT_THAT(out, HasSubstr("\"id\":1989")); + EXPECT_THAT(out, HasSubstr("\"result\":null")); +} + +class TransportInputTest : public Test { + std::optional inputTempFile; + std::FILE *in = nullptr; + std::string output = ""; + llvm::raw_string_ostream os; + std::optional transport = std::nullopt; + std::optional messageHandler = std::nullopt; + +protected: + TransportInputTest() : os(output) {} + + void SetUp() override { + auto tempOr = llvm::sys::fs::TempFile::create("lsp-unittest-%%%%%%.json"); + ASSERT_TRUE((bool)tempOr); + llvm::sys::fs::TempFile t = std::move(*tempOr); + inputTempFile = std::move(t); + + in = std::fopen(inputTempFile->TmpName.c_str(), "r"); + transport.emplace(in, os, JSONStreamStyle::Delimited); + messageHandler.emplace(*transport); + } + + void TearDown() override { + EXPECT_FALSE(inputTempFile->discard()); + EXPECT_EQ(std::fclose(in), 0); + } + + void writeInput(StringRef buffer) { + std::error_code ec; + llvm::raw_fd_ostream os(inputTempFile->TmpName, ec); + ASSERT_FALSE(ec); + os << buffer; + os.close(); + } + + StringRef getOutput() const { return output; } + MessageHandler &getMessageHandler() { return *messageHandler; } + + void runTransport() { + bool gotEOF = false; + llvm::Error err = llvm::handleErrors( + transport->run(*messageHandler), [&](const llvm::ECError &ecErr) { + gotEOF = ecErr.convertToErrorCode() == std::errc::io_error; + }); + llvm::consumeError(std::move(err)); + EXPECT_TRUE(gotEOF); + } +}; + +TEST_F(TransportInputTest, RequestWithInvalidParams) { + struct Handler { + void onMethod(const TextDocumentItem ¶ms, + mlir::lsp::Callback callback) {} + } handler; + getMessageHandler().method("invalid-params-request", &handler, + &Handler::onMethod); + + writeInput("{\"jsonrpc\":\"2.0\",\"id\":92," + "\"method\":\"invalid-params-request\",\"params\":{}}\n"); + runTransport(); + EXPECT_THAT(getOutput(), HasSubstr("error")); + EXPECT_THAT(getOutput(), HasSubstr("missing value at (root).uri")); +} + +TEST_F(TransportInputTest, NotificationWithInvalidParams) { + // JSON parsing errors are only reported via error logging. As a result, this + // test can't make any expectations -- but it prints the output anyway, by way + // of demonstration. + Logger::setLogLevel(Logger::Level::Error); + + struct Handler { + void onNotification(const TextDocumentItem ¶ms) {} + } handler; + getMessageHandler().notification("invalid-params-notification", &handler, + &Handler::onNotification); + + writeInput("{\"jsonrpc\":\"2.0\",\"method\":\"invalid-params-notification\"," + "\"params\":{}}\n"); + runTransport(); +} + +TEST_F(TransportInputTest, MethodNotFound) { + writeInput("{\"jsonrpc\":\"2.0\",\"id\":29,\"method\":\"ack\"}\n"); + runTransport(); + EXPECT_THAT(getOutput(), HasSubstr("\"id\":29")); + EXPECT_THAT(getOutput(), HasSubstr("\"error\"")); + EXPECT_THAT(getOutput(), HasSubstr("\"message\":\"method not found: ack\"")); +} +} // namespace diff --git a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel index 3df8341712aa9317b029c0da910c02f6af0f35eb..aa9f665c350ae3b1fdbd32184e1c53bfe36f1bf3 100644 --- a/utils/bazel/llvm-project-overlay/libc/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/BUILD.bazel @@ -23,17 +23,6 @@ package( licenses(["notice"]) -PRINTF_COPTS = [ - "LIBC_COPT_STDIO_USE_SYSTEM_FILE", - "LIBC_COPT_PRINTF_DISABLE_WRITE_INT", -] - -MEMORY_COPTS = [ - # "LIBC_COPT_MEMCPY_X86_USE_REPMOVSB_FROM_SIZE=0", - # "LIBC_COPT_MEMCPY_X86_USE_SOFTWARE_PREFETCHING", - # "LIBC_COPT_MEMSET_X86_USE_SOFTWARE_PREFETCHING", -] - # A flag to pick which `mpfr` to use for math tests. # Usage: `--@llvm-project//libc:mpfr=`. # Flag documentation: https://bazel.build/extending/config @@ -2421,7 +2410,6 @@ libc_support_library( "src/string/memory_utils/op_x86.h", "src/string/memory_utils/utils.h", ], - defines = MEMORY_COPTS, textual_hdrs = [ "src/string/memory_utils/aarch64/inline_bcmp.h", "src/string/memory_utils/aarch64/inline_memcmp.h", @@ -3191,7 +3179,6 @@ libc_function( libc_support_library( name = "printf_config", hdrs = ["src/stdio/printf_core/printf_config.h"], - defines = PRINTF_COPTS, deps = [ ], ) @@ -3199,7 +3186,6 @@ libc_support_library( libc_support_library( name = "printf_core_structs", hdrs = ["src/stdio/printf_core/core_structs.h"], - defines = PRINTF_COPTS, deps = [ ":__support_cpp_string_view", ":__support_fputil_fp_bits", @@ -3210,7 +3196,6 @@ libc_support_library( libc_support_library( name = "printf_parser", hdrs = ["src/stdio/printf_core/parser.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_common", @@ -3231,7 +3216,7 @@ libc_support_library( libc_support_library( name = "printf_mock_parser", hdrs = ["src/stdio/printf_core/parser.h"], - defines = PRINTF_COPTS + ["LIBC_COPT_MOCK_ARG_LIST"], + local_defines = ["LIBC_COPT_MOCK_ARG_LIST"], deps = [ ":__support_arg_list", ":__support_common", @@ -3251,7 +3236,6 @@ libc_support_library( name = "printf_writer", srcs = ["src/stdio/printf_core/writer.cpp"], hdrs = ["src/stdio/printf_core/writer.h"], - defines = PRINTF_COPTS, deps = [ ":__support_cpp_string_view", ":__support_macros_optimization", @@ -3276,7 +3260,6 @@ libc_support_library( "src/stdio/printf_core/string_converter.h", "src/stdio/printf_core/write_int_converter.h", ], - defines = PRINTF_COPTS, deps = [ ":__support_big_int", ":__support_common", @@ -3300,7 +3283,6 @@ libc_support_library( name = "printf_main", srcs = ["src/stdio/printf_core/printf_main.cpp"], hdrs = ["src/stdio/printf_core/printf_main.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":printf_converter", @@ -3313,7 +3295,6 @@ libc_support_library( libc_support_library( name = "vfprintf_internal", hdrs = ["src/stdio/printf_core/vfprintf_internal.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_file_file", @@ -3327,7 +3308,6 @@ libc_function( name = "sprintf", srcs = ["src/stdio/sprintf.cpp"], hdrs = ["src/stdio/sprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_cpp_limits", @@ -3341,7 +3321,6 @@ libc_function( name = "snprintf", srcs = ["src/stdio/snprintf.cpp"], hdrs = ["src/stdio/snprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":errno", @@ -3354,7 +3333,6 @@ libc_function( name = "printf", srcs = ["src/stdio/printf.cpp"], hdrs = ["src/stdio/printf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_file_file", @@ -3367,7 +3345,6 @@ libc_function( name = "fprintf", srcs = ["src/stdio/fprintf.cpp"], hdrs = ["src/stdio/fprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_file_file", @@ -3380,7 +3357,6 @@ libc_function( name = "vsprintf", srcs = ["src/stdio/vsprintf.cpp"], hdrs = ["src/stdio/vsprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_cpp_limits", @@ -3394,7 +3370,6 @@ libc_function( name = "vsnprintf", srcs = ["src/stdio/vsnprintf.cpp"], hdrs = ["src/stdio/vsnprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":errno", @@ -3407,7 +3382,6 @@ libc_function( name = "vprintf", srcs = ["src/stdio/vprintf.cpp"], hdrs = ["src/stdio/vprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_file_file", @@ -3420,7 +3394,6 @@ libc_function( name = "vfprintf", srcs = ["src/stdio/vfprintf.cpp"], hdrs = ["src/stdio/vfprintf.h"], - defines = PRINTF_COPTS, deps = [ ":__support_arg_list", ":__support_file_file", diff --git a/utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl b/utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl index be59e18ffd89a9627d43882cb6d69f111983e52c..ec3714407cb91494d0d118523bb493c1ebff3566 100644 --- a/utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl +++ b/utils/bazel/llvm-project-overlay/libc/libc_build_rules.bzl @@ -6,6 +6,7 @@ load("@bazel_skylib//lib:paths.bzl", "paths") load("@bazel_skylib//lib:selects.bzl", "selects") +load(":libc_configure_options.bzl", "LIBC_CONFIGURE_OPTIONS") load(":libc_namespace.bzl", "LIBC_NAMESPACE") load(":platforms.bzl", "PLATFORM_CPU_ARM64", "PLATFORM_CPU_X86_64") @@ -21,13 +22,14 @@ def libc_common_copts(): "-DLIBC_NAMESPACE=" + LIBC_NAMESPACE, ] -def _libc_library(name, hidden, copts = [], deps = [], **kwargs): +def _libc_library(name, hidden, copts = [], deps = [], local_defines = [], **kwargs): """Internal macro to serve as a base for all other libc library rules. Args: name: Target name. copts: The special compiler options for the target. deps: The list of target dependencies if any. + local_defines: The list of target local_defines if any. hidden: Whether the symbols should be explicitly hidden or not. **kwargs: All other attributes relevant for the cc_library rule. """ @@ -40,6 +42,7 @@ def _libc_library(name, hidden, copts = [], deps = [], **kwargs): native.cc_library( name = name, copts = copts + libc_common_copts(), + local_defines = local_defines + LIBC_CONFIGURE_OPTIONS, deps = deps, linkstatic = 1, **kwargs diff --git a/utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl b/utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl new file mode 100644 index 0000000000000000000000000000000000000000..f780c323d9a996981091ea79103da34bd21dec4c --- /dev/null +++ b/utils/bazel/llvm-project-overlay/libc/libc_configure_options.bzl @@ -0,0 +1,49 @@ +# This file is licensed under the Apache License v2.0 with LLVM Exceptions. +# See https://llvm.org/LICENSE.txt for license information. +# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception + +"""LLVM libc configuration options. +The canonical list of user options is in 'libc/config/config.json'. +These options are then processed by CMake and turned into preprocessor +definitions. We don't have this logic in Bazel yet but the list of definitions +is discoverable with the following command: + +> git grep -hoE '\bLIBC_COPT_\\w*' -- '*.h' '*.cpp' | sort -u +""" + +# This list of definitions is used to customize LLVM libc. +LIBC_CONFIGURE_OPTIONS = [ + # Documentation in libc/docs/dev/printf_behavior.rst + # "LIBC_COPT_FLOAT_TO_STR_NO_SPECIALIZE_LD", + # "LIBC_COPT_FLOAT_TO_STR_NO_TABLE", + # "LIBC_COPT_FLOAT_TO_STR_USE_DYADIC_FLOAT", + # "LIBC_COPT_FLOAT_TO_STR_USE_DYADIC_FLOAT_LD", + # "LIBC_COPT_FLOAT_TO_STR_USE_INT_CALC", + # "LIBC_COPT_FLOAT_TO_STR_USE_MEGA_LONG_DOUBLE_TABLE", + + # Documentation in libc/src/string/memory_utils/... + # "LIBC_COPT_MEMCPY_USE_EMBEDDED_TINY", + # "LIBC_COPT_MEMCPY_X86_USE_REPMOVSB_FROM_SIZE", + # "LIBC_COPT_MEMCPY_X86_USE_SOFTWARE_PREFETCHING", + # "LIBC_COPT_MEMSET_X86_USE_SOFTWARE_PREFETCHING", + + # Documentation in libc/docs/dev/printf_behavior.rst + # "LIBC_COPT_PRINTF_CONV_ATLAS", + # "LIBC_COPT_PRINTF_DISABLE_FIXED_POINT", + # "LIBC_COPT_PRINTF_DISABLE_FLOAT", + # "LIBC_COPT_PRINTF_DISABLE_INDEX_MODE", + "LIBC_COPT_PRINTF_DISABLE_WRITE_INT", + # "LIBC_COPT_PRINTF_HEX_LONG_DOUBLE", + # "LIBC_COPT_PRINTF_INDEX_ARR_LEN", + # "LIBC_COPT_PRINTF_NO_NULLPTR_CHECKS", + # "LIBC_COPT_SCANF_DISABLE_FLOAT", + # "LIBC_COPT_SCANF_DISABLE_INDEX_MODE", + "LIBC_COPT_STDIO_USE_SYSTEM_FILE", + # "LIBC_COPT_STRING_UNSAFE_WIDE_READ", + # "LIBC_COPT_STRTOFLOAT_DISABLE_CLINGER_FAST_PATH", + # "LIBC_COPT_STRTOFLOAT_DISABLE_EISEL_LEMIRE", + # "LIBC_COPT_STRTOFLOAT_DISABLE_SIMPLE_DECIMAL_CONVERSION", + + # Documentation in libc/src/__support/libc_assert.h + # "LIBC_COPT_USE_C_ASSERT", +] diff --git a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel index e55804b1ea79e559c0cad4eb24d5d4a99db5b211..6126a4a8fca83069738702b25a99f701fc2eb9be 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/UnitTest/BUILD.bazel @@ -65,10 +65,12 @@ libc_support_library( libc_support_library( name = "fp_test_helpers", srcs = [ + "FEnvSafeTest.cpp", "FPExceptMatcher.cpp", "RoundingModeUtils.cpp", ], hdrs = [ + "FEnvSafeTest.h", "FPExceptMatcher.h", "FPMatcher.h", "RoundingModeUtils.h", @@ -82,13 +84,15 @@ libc_support_library( "//libc:__support_cpp_bitset", "//libc:__support_cpp_span", "//libc:__support_cpp_type_traits", + "//libc:__support_cpp_utility", "//libc:__support_fputil_fenv_impl", "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_fpbits_str", "//libc:__support_fputil_rounding_mode", + "//libc:__support_macros_properties_architectures", "//libc:hdr_math_macros", - "//libc:hdr_fenv_macros", - "//libc:types_fenv_t", + "//libc:hdr_fenv_macros", + "//libc:types_fenv_t", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl b/utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl index 18056bacfd50cea1dd3f30ef9997ea22066e7543..ae24a41c60418b129ccfffe074efc744b91eae5a 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl +++ b/utils/bazel/llvm-project-overlay/libc/test/libc_test_rules.bzl @@ -13,8 +13,9 @@ When performing tests we make sure to always use the internal version. """ load("//libc:libc_build_rules.bzl", "libc_common_copts", "libc_internal_target") +load("//libc:libc_configure_options.bzl", "LIBC_CONFIGURE_OPTIONS") -def libc_test(name, srcs, libc_function_deps = [], copts = [], deps = [], **kwargs): +def libc_test(name, srcs, libc_function_deps = [], copts = [], deps = [], local_defines = [], **kwargs): """Add target for a libc test. Args: @@ -23,12 +24,14 @@ def libc_test(name, srcs, libc_function_deps = [], copts = [], deps = [], **kwar libc_function_deps: List of libc_function targets used by this test. copts: The list of options to add to the C++ compilation command. deps: The list of other libraries to be linked in to the test target. + local_defines: The list of target local_defines if any. **kwargs: Attributes relevant for a libc_test. For example, name, srcs. """ all_function_deps = libc_function_deps + ["//libc:errno"] native.cc_test( name = name, srcs = srcs, + local_defines = local_defines + LIBC_CONFIGURE_OPTIONS, deps = [libc_internal_target(d) for d in all_function_deps] + [ "//libc/test/UnitTest:LibcUnitTest", ] + deps, diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel index fc3ab3da3587c57996ea5e6d7b706898e685a1bf..03c94d1db23aa74bf3e4563c4b8e15259d3f00c5 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/fenv/BUILD.bazel @@ -12,7 +12,10 @@ licenses(["notice"]) libc_test( name = "exception_status_test", - srcs = ["exception_status_test.cpp"], + srcs = [ + "exception_status_test.cpp", + "excepts.h", + ], libc_function_deps = [ "//libc:feclearexcept", "//libc:feraiseexcept", @@ -21,23 +24,33 @@ libc_test( ], deps = [ "//libc:__support_fputil_fenv_impl", - "//libc:hdr_fenv_macros", + "//libc:hdr_fenv_macros", + "//libc/test/UnitTest:fp_test_helpers", ], ) libc_test( name = "rounding_mode_test", - srcs = ["rounding_mode_test.cpp"], + srcs = [ + "excepts.h", + "rounding_mode_test.cpp", + ], libc_function_deps = [ "//libc:fegetround", "//libc:fesetround", ], - deps = ["//libc:hdr_fenv_macros"], + deps = [ + "//libc:hdr_fenv_macros", + "//libc/test/UnitTest:fp_test_helpers", + ], ) libc_test( name = "enabled_exceptions_test", - srcs = ["enabled_exceptions_test.cpp"], + srcs = [ + "enabled_exceptions_test.cpp", + "excepts.h", + ], libc_function_deps = [ "//libc:feclearexcept", "//libc:feraiseexcept", @@ -48,14 +61,17 @@ libc_test( "//libc:__support_common", "//libc:__support_fputil_fenv_impl", "//libc:__support_macros_properties_architectures", + "//libc:hdr_fenv_macros", "//libc/test/UnitTest:fp_test_helpers", - "//libc:hdr_fenv_macros", ], ) libc_test( name = "feholdexcept_test", - srcs = ["feholdexcept_test.cpp"], + srcs = [ + "excepts.h", + "feholdexcept_test.cpp", + ], libc_function_deps = [ "//libc:feholdexcept", ], @@ -64,14 +80,18 @@ libc_test( "//libc:__support_common", "//libc:__support_fputil_fenv_impl", "//libc:__support_macros_properties_architectures", + "//libc:hdr_fenv_macros", + "//libc:types_fenv_t", "//libc/test/UnitTest:fp_test_helpers", - "//libc:types_fenv_t", ], ) libc_test( name = "exception_flags_test", - srcs = ["exception_flags_test.cpp"], + srcs = [ + "exception_flags_test.cpp", + "excepts.h", + ], libc_function_deps = [ "//libc:fegetexceptflag", "//libc:fesetexceptflag", @@ -79,25 +99,34 @@ libc_test( ], deps = [ "//libc:__support_fputil_fenv_impl", - "//libc:types_fexcept_t", + "//libc:hdr_fenv_macros", + "//libc:types_fexcept_t", + "//libc/test/UnitTest:fp_test_helpers", ], ) libc_test( name = "feclearexcept_test", - srcs = ["feclearexcept_test.cpp"], + srcs = [ + "excepts.h", + "feclearexcept_test.cpp", + ], libc_function_deps = [ "//libc:feclearexcept", ], deps = [ "//libc:__support_fputil_fenv_impl", - "//libc:hdr_fenv_macros", + "//libc:hdr_fenv_macros", + "//libc/test/UnitTest:fp_test_helpers", ], ) libc_test( name = "feenableexcept_test", - srcs = ["feenableexcept_test.cpp"], + srcs = [ + "excepts.h", + "feenableexcept_test.cpp", + ], libc_function_deps = [ "//libc:fedisableexcept", "//libc:feenableexcept", @@ -106,25 +135,34 @@ libc_test( deps = [ "//libc:__support_common", "//libc:__support_macros_properties_architectures", - "//libc:hdr_fenv_macros", + "//libc:hdr_fenv_macros", + "//libc/test/UnitTest:fp_test_helpers", ], ) libc_test( name = "feupdateenv_test", - srcs = ["feupdateenv_test.cpp"], + srcs = [ + "excepts.h", + "feupdateenv_test.cpp", + ], libc_function_deps = [ "//libc:feupdateenv", ], deps = [ "//libc:__support_fputil_fenv_impl", - "//libc:types_fenv_t", + "//libc:hdr_fenv_macros", + "//libc:types_fenv_t", + "//libc/test/UnitTest:fp_test_helpers", ], ) libc_test( name = "getenv_and_setenv_test", - srcs = ["getenv_and_setenv_test.cpp"], + srcs = [ + "excepts.h", + "getenv_and_setenv_test.cpp", + ], libc_function_deps = [ "//libc:fegetenv", "//libc:fegetround", @@ -133,6 +171,8 @@ libc_test( ], deps = [ "//libc:__support_fputil_fenv_impl", - "//libc:types_fenv_t", + "//libc:hdr_fenv_macros", + "//libc:types_fenv_t", + "//libc/test/UnitTest:fp_test_helpers", ], ) diff --git a/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel b/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel index e30c8bf023cf2a4631ee70f656bf091fbfcaf999..4f72a0a8e1863a6a1638136ed4e70cbd71436438 100644 --- a/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/libc/test/src/math/BUILD.bazel @@ -298,6 +298,7 @@ libc_support_library( "//libc:__support_fputil_fp_bits", "//libc:__support_fputil_manipulation_functions", "//libc:hdr_math_macros", + "//libc/test/UnitTest:fp_test_helpers", "//libc/test/UnitTest:LibcUnitTest", ], ) diff --git a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel index e0907a838148f5e26137525efea300135a9f0239..13fec77fe567bb5d3b170cb0928cb26627bad5aa 100644 --- a/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/lldb/source/Plugins/BUILD.bazel @@ -2092,6 +2092,10 @@ cc_library( srcs = glob(["Process/Linux/*.cpp"]), hdrs = glob(["Process/Linux/*.h"]), include_prefix = "Plugins", + target_compatible_with = select({ + "@platforms//os:linux": [], + "//conditions:default": ["@platforms//:incompatible"], + }), deps = [ ":PluginProcessPOSIX", ":PluginProcessUtility", diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index c9c0edb1dc3109020a75a6d1caee9a9b457db9aa..3223eb92d869ebdd1f78f9c7b5ceaa18645bc7dc 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -636,6 +636,7 @@ cc_binary( name = "llvm-min-tblgen", srcs = [ "utils/TableGen/Attributes.cpp", + "utils/TableGen/ARMTargetDefEmitter.cpp", "utils/TableGen/Basic/CodeGenIntrinsics.cpp", "utils/TableGen/Basic/CodeGenIntrinsics.h", "utils/TableGen/Basic/SDNodeProperties.cpp", @@ -1231,6 +1232,30 @@ cc_library( ], ) +gentbl( + name = "ARMTargetParserDefGen", + tbl_outs = [("-gen-arm-target-def", "include/llvm/TargetParser/ARMTargetParserDef.inc")], + tblgen = ":llvm-min-tblgen", + td_file = "lib/Target/ARM/ARM.td", + td_srcs = [ + ":common_target_td_sources", + ] + glob([ + "lib/Target/ARM/**/*.td", + ]), +) + +gentbl( + name = "AArch64TargetParserDefGen", + tbl_outs = [("-gen-arm-target-def", "include/llvm/TargetParser/AArch64TargetParserDef.inc")], + tblgen = ":llvm-min-tblgen", + td_file = "lib/Target/AArch64/AArch64.td", + td_srcs = [ + ":common_target_td_sources", + ] + glob([ + "lib/Target/AArch64/**/*.td", + ]), +) + gentbl( name = "RISCVTargetParserDefGen", tbl_outs = [("-gen-riscv-target-def", "include/llvm/TargetParser/RISCVTargetParserDef.inc")], @@ -1261,6 +1286,8 @@ cc_library( copts = llvm_copts, includes = ["include"], textual_hdrs = [ + "include/llvm/TargetParser/ARMTargetParserDef.inc", + "include/llvm/TargetParser/AArch64TargetParserDef.inc", "include/llvm/TargetParser/RISCVTargetParserDef.inc", ] + glob([ "include/llvm/TargetParser/*.def", diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 63b24b9f46b20adcc30ac59a90526d298b9d1571..3eb0f67bbd88a54d649142b97904f1036bb1175c 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -5,8 +5,8 @@ # Description: # The MLIR "Multi-Level Intermediate Representation" Compiler Infrastructure -load("@bazel_skylib//rules:expand_template.bzl", "expand_template") load("@bazel_skylib//rules:common_settings.bzl", "bool_flag") +load("@bazel_skylib//rules:expand_template.bzl", "expand_template") load( ":build_defs.bzl", "cc_headers_only", @@ -3652,14 +3652,6 @@ gentbl_cc_library( ], "include/mlir/Dialect/XeGPU/IR/XeGPUTypes.cpp.inc", ), - ( - ["-gen-enum-decls"], - "include/mlir/Dialect/XeGPU/IR/XeGPUEnums.h.inc", - ), - ( - ["-gen-enum-defs"], - "include/mlir/Dialect/XeGPU/IR/XeGPUEnums.cpp.inc", - ), ( [ "-gen-attrdef-decls", @@ -3677,7 +3669,44 @@ gentbl_cc_library( ], tblgen = ":mlir-tblgen", td_file = "include/mlir/Dialect/XeGPU/IR/XeGPU.td", - deps = [":XeGPUTdFiles"], + deps = [ + ":ArithOpsTdFiles", + ":XeGPUTdFiles", + ], +) + +td_library( + name = "XeGPUAttrTdFiles", + srcs = [ + "include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td", + "include/mlir/Dialect/XeGPU/IR/XeGPUDialect.td", + ], + includes = ["include"], + deps = [ + ":BuiltinDialectTdFiles", + ":OpBaseTdFiles", + ":ShapedOpInterfacesTdFiles", + ":ViewLikeInterfaceTdFiles", + ], +) + +# Separated from the XeGPUIncGen target because the enum declaration causes +# duplicate declarations with the Arith enums. +gentbl_cc_library( + name = "XeGPUEnumsIncGen", + tbl_outs = [ + ( + ["-gen-enum-decls"], + "include/mlir/Dialect/XeGPU/IR/XeGPUEnums.h.inc", + ), + ( + ["-gen-enum-defs"], + "include/mlir/Dialect/XeGPU/IR/XeGPUEnums.cpp.inc", + ), + ], + tblgen = ":mlir-tblgen", + td_file = "include/mlir/Dialect/XeGPU/IR/XeGPUAttrs.td", + deps = [":XeGPUAttrTdFiles"], ) cc_library( @@ -3689,12 +3718,14 @@ cc_library( hdrs = ["include/mlir/Dialect/XeGPU/IR/XeGPU.h"], includes = ["include"], deps = [ + ":ArithDialect", ":BytecodeOpInterface", ":DialectUtils", ":IR", ":ShapedOpInterfaces", ":SideEffectInterfaces", ":ViewLikeInterface", + ":XeGPUEnumsIncGen", ":XeGPUIncGen", "//llvm:Support", ], @@ -9740,6 +9771,15 @@ cc_binary( ], ) +cc_binary( + name = "mlir-src-sharder", + srcs = ["tools/mlir-src-sharder/mlir-src-sharder.cpp"], + deps = [ + ":Support", + "//llvm:Support", + ], +) + cc_binary( name = "mlir-linalg-ods-yaml-gen", srcs = [ diff --git a/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl b/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl index fdf6a57107ac34c47de05662580afc06af65c5d2..e45ba1fe0ef721191b09466c4481bf8595cc8cb6 100644 --- a/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl +++ b/utils/bazel/llvm-project-overlay/mlir/tblgen.bzl @@ -432,3 +432,136 @@ def gentbl_cc_library( copts = copts, **kwargs ) + +def _gentbl_shard_impl(ctx): + args = ctx.actions.args() + args.add(ctx.file.src_file) + args.add("-op-shard-index", ctx.attr.index) + args.add("-o", ctx.outputs.out.path) + ctx.actions.run( + outputs = [ctx.outputs.out], + inputs = [ctx.file.src_file], + executable = ctx.executable.sharder, + arguments = [args], + use_default_shell_env = True, + mnemonic = "ShardGenerate", + ) + +gentbl_shard_rule = rule( + _gentbl_shard_impl, + doc = "", + output_to_genfiles = True, + attrs = { + "index": attr.int(mandatory = True, doc = ""), + "sharder": attr.label( + doc = "", + executable = True, + cfg = "exec", + ), + "src_file": attr.label( + doc = "", + allow_single_file = True, + mandatory = True, + ), + "out": attr.output( + doc = "", + mandatory = True, + ), + }, +) + +def gentbl_sharded_ops( + name, + tblgen, + sharder, + td_file, + shard_count, + src_file, + src_out, + hdr_out, + test = False, + includes = [], + strip_include_prefix = None, + deps = []): + """Generate sharded op declarations and definitions. + + This special build rule shards op definitions in a TableGen file and generates multiple copies + of a template source file for including and compiling each shard. The rule defines a filegroup + consisting of the source shards, the generated source file, and the generated header file. + + Args: + name: The name of the filegroup. + tblgen: The binary used to produce the output. + sharder: The source file sharder to use. + td_file: The primary table definitions file. + shard_count: The number of op definition shards to produce. + src_file: The source file template. + src_out: The generated source file. + hdr_out: The generated header file. + test: Whether this is a test target. + includes: See gentbl_rule.includes + deps: See gentbl_rule.deps + strip_include_prefix: Attribute to pass through to cc_library. + """ + cc_lib_name = name + "__gentbl_cc_lib" + gentbl_cc_library( + name = cc_lib_name, + strip_include_prefix = strip_include_prefix, + includes = includes, + tbl_outs = [ + ( + [ + "-gen-op-defs", + "-op-shard-count=" + str(shard_count), + ], + src_out, + ), + ( + [ + "-gen-op-decls", + "-op-shard-count=" + str(shard_count), + ], + hdr_out, + ), + ], + tblgen = tblgen, + td_file = td_file, + test = test, + deps = deps, + ) + all_files = [hdr_out, src_out] + for i in range(0, shard_count): + out_file = "shard_copy_" + str(i) + "_" + src_file + gentbl_shard_rule( + index = i, + name = name + "__src_shard" + str(i), + testonly = test, + out = out_file, + sharder = sharder, + src_file = src_file, + ) + all_files.append(out_file) + native.filegroup(name = name, srcs = all_files) + +def gentbl_sharded_op_defs(name, source_file, shard_count): + """Generates multiple copies of a source file that includes sharded op definitions. + + Args: + name: The name of the rule. + source_file: The source to copy. + shard_count: The number of shards. + + Returns: + A list of the copied filenames to be included in the dialect library. + """ + copies = [] + for i in range(0, shard_count): + out_file = "shard_copy_" + str(i) + "_" + source_file + copies.append(out_file) + native.genrule( + name = name + "_shard_" + str(i), + srcs = [source_file], + outs = [out_file], + cmd = "echo -e \"#define GET_OP_DEFS_" + str(i) + "\n$$(cat $(SRCS))\" > $(OUTS)", + ) + return copies diff --git a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel index dc5f4047c286dbcc78a4fc2764fe60cd4fed780b..0ebfcbe284bd3726ebc8eea5ca50a1ef978a0a17 100644 --- a/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/test/BUILD.bazel @@ -4,7 +4,7 @@ load("@bazel_skylib//rules:expand_template.bzl", "expand_template") load("//llvm:lit_test.bzl", "package_path") -load("//mlir:tblgen.bzl", "gentbl_cc_library", "td_library") +load("//mlir:tblgen.bzl", "gentbl_cc_library", "gentbl_sharded_ops", "td_library") package( default_visibility = ["//visibility:public"], @@ -151,14 +151,6 @@ gentbl_cc_library( name = "TestOpsIncGen", strip_include_prefix = "lib/Dialect/Test", tbl_outs = [ - ( - ["-gen-op-decls"], - "lib/Dialect/Test/TestOps.h.inc", - ), - ( - ["-gen-op-defs"], - "lib/Dialect/Test/TestOps.cpp.inc", - ), ( [ "-gen-dialect-decls", @@ -370,12 +362,25 @@ cc_library( ], ) +gentbl_sharded_ops( + name = "TestDialectOpSrcs", + hdr_out = "lib/Dialect/Test/TestOps.h.inc", + shard_count = 20, + sharder = "//mlir:mlir-src-sharder", + src_file = "lib/Dialect/Test/TestOps.cpp", + src_out = "lib/Dialect/Test/TestOps.cpp.inc", + tblgen = "//mlir:mlir-tblgen", + td_file = "lib/Dialect/Test/TestOps.td", + test = True, + deps = [":TestOpTdFiles"], +) + cc_library( name = "TestDialect", srcs = glob( ["lib/Dialect/Test/*.cpp"], exclude = ["lib/Dialect/Test/TestToLLVMIRTranslation.cpp"], - ), + ) + [":TestDialectOpSrcs"], hdrs = glob(["lib/Dialect/Test/*.h"]), includes = [ "lib/Dialect/Test", @@ -418,9 +423,9 @@ cc_library( "//mlir:SideEffectInterfaces", "//mlir:Support", "//mlir:TensorDialect", - "//mlir:TranslateLib", "//mlir:TransformUtils", "//mlir:Transforms", + "//mlir:TranslateLib", "//mlir:ValueBoundsOpInterface", "//mlir:ViewLikeInterface", ],